diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md new file mode 100644 index 00000000000..c1e467e6c4d --- /dev/null +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1,35 @@ +### Summary of this Pull Request (PR) 拉取/合并请求的简述 + +**Add description here.** **请在这里加入描述** + +### Intent for your PR 拉取/合并请求的目的 + +Choose one (Mandatory): 必须选择一项 + +- [ ] This PR is for a code-review and is intended to get feedback 本拉取/合并请求是一个草稿版本 +- [ ] This PR is mature, and ready to be integrated into the repo 本拉取/合并请求是一个成熟版本 + +### Reviewers (Mandatory): 代码审阅者（必须指定） + +(@ Ex: @user1, @user2) + +### Code Quality： 代码质量 + +As part of this pull request, I've considered the following: +我在这个拉取/合并请求中已经考虑了： + +- [ ] Already check the difference between PR and old code 已经仔细查看过代码改动的对比 +- [ ] Style guide is adhered to, including spacing, naming and other style 代码风格正确，包括缩进空格，命名及其他风格 +- [ ] All redundant code is removed and cleaned up 没有垃圾代码，代码尽量精简，不包含`#if 0`代码，不包含已经被注释了的代码 +- [ ] All modifications are justified and not affect other components or BSP 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP +- [ ] I've commented appropriately where code is tricky 对难懂代码均提供对应的注释 +- [ ] Code in this PR is of high quality 本拉取/合并请求代码是高质量的 + +### Testing：代码测试 + +I've tested the code using the following test programs (provide list here): +我已经在如下场合跑过对应的测试： + +- [ ] application 1 +- [ ] application 2 +- [ ] ...(add others here) diff --git a/bsp/CME_M7/rtconfig.h b/bsp/CME_M7/rtconfig.h index d0e44c8d283..886c28cb9ea 100644 --- a/bsp/CME_M7/rtconfig.h +++ b/bsp/CME_M7/rtconfig.h @@ -55,6 +55,7 @@ #define RT_USING_DEVICE #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* SECTION: Console options */ #define RT_USING_CONSOLE @@ -100,8 +101,14 @@ /* Enable DHCP */ // #define RT_LWIP_DHCP -/* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 3 +#define RT_MEMP_NUM_NETCONN 12 +#define RT_LWIP_PBUF_NUM 3 +#define RT_LWIP_RAW_PCB_NUM 2 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 8 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 4380 +#define RT_LWIP_TCP_WND 4380 /* ip address of target */ #define RT_LWIP_IPADDR "192.168.1.30" diff --git a/bsp/CME_M7/rtconfig.py b/bsp/CME_M7/rtconfig.py index 134ef61559d..650d4bb7f89 100644 --- a/bsp/CME_M7/rtconfig.py +++ b/bsp/CME_M7/rtconfig.py @@ -15,8 +15,10 @@ PLATFORM = 'armcc' EXEC_PATH = 'C:/Keil' elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + print('================ERROR============================') + print('Not support iar yet!') + print('=================================================') + exit(0) if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -64,15 +66,14 @@ LINK = 'armlink' TARGET_EXT = 'axf' - DEVICE = ' --cortex-m3' + DEVICE = ' --cpu Cortex-M3' CFLAGS = DEVICE + ' --c99 --apcs=interwork' AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter nuc472_flash.sct' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter CME_M7.sct' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' - EXEC_PATH += '/arm/bin40/' + EXEC_PATH += '/ARM/ARMCC/bin' if BUILD == 'debug': CFLAGS += ' -g -O0' diff --git a/bsp/allwinner_tina/.config b/bsp/allwinner_tina/.config index 3a40f9d5666..de547c5a349 100644 --- a/bsp/allwinner_tina/.config +++ b/bsp/allwinner_tina/.config @@ -120,6 +120,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/allwinner_tina/libcpu/start_gcc.S b/bsp/allwinner_tina/libcpu/start_gcc.S index 94c985a3706..8ef36826df7 100644 --- a/bsp/allwinner_tina/libcpu/start_gcc.S +++ b/bsp/allwinner_tina/libcpu/start_gcc.S @@ -48,7 +48,7 @@ _vector_reset: _vector_undef: .word vector_undef _vector_swi: - .word vector_swi + .word SVC_Handler _vector_pabt: .word vector_pabt _vector_dabt: @@ -314,7 +314,9 @@ rt_hw_context_switch_interrupt_do: str lr, [r0, #14*4] .endm - .align 5 + .align 5 +.weak SVC_Handler +SVC_Handler: vector_swi: push_svc_reg bl rt_hw_trap_swi diff --git a/bsp/allwinner_tina/rtconfig.h b/bsp/allwinner_tina/rtconfig.h index 2fb7c07df3e..25a1302b1ae 100644 --- a/bsp/allwinner_tina/rtconfig.h +++ b/bsp/allwinner_tina/rtconfig.h @@ -111,6 +111,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/allwinner_tina/rtconfig.py b/bsp/allwinner_tina/rtconfig.py index f3c4f699ab8..2fa3ea78d00 100644 --- a/bsp/allwinner_tina/rtconfig.py +++ b/bsp/allwinner_tina/rtconfig.py @@ -2,7 +2,7 @@ # toolchains options ARCH ='arm' -CPU ='R6' +CPU ='arm9' CROSS_TOOL ='gcc' if os.getenv('RTT_ROOT'): diff --git a/bsp/amebaz/.config b/bsp/amebaz/.config index 4a513007e70..9412058c8e6 100644 --- a/bsp/amebaz/.config +++ b/bsp/amebaz/.config @@ -106,6 +106,7 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/amebaz/drivers/wlan/drv_wifi.c b/bsp/amebaz/drivers/wlan/drv_wifi.c index 67a870b034e..7e62ed1acfc 100644 --- a/bsp/amebaz/drivers/wlan/drv_wifi.c +++ b/bsp/amebaz/drivers/wlan/drv_wifi.c @@ -91,10 +91,16 @@ int rthw_wifi_register(struct ameba_wifi *wifi) if ((wifi->flag & WIFI_INIT_FLAG) == 0) { + wlan = rt_malloc(sizeof(struct rt_wlan_device)); + RT_ASSERT(wlan != RT_NULL); if (wifi->type == WIFI_TYPE_STA) - wlan = rt_wlan_dev_register(RT_WLAN_DEVICE_STA_NAME, &ops, 0, wifi); + { + rt_wlan_dev_register(wlan, RT_WLAN_DEVICE_STA_NAME, &ops, 0, wifi); + } if (wifi->type == WIFI_TYPE_AP) - wlan = rt_wlan_dev_register(RT_WLAN_DEVICE_AP_NAME, &ops, 0, wifi); + { + rt_wlan_dev_register(wlan, RT_WLAN_DEVICE_AP_NAME, &ops, 0, wifi); + } wifi->flag |= WIFI_INIT_FLAG; wifi->wlan = wlan; LOG_D("F:%s L:%d wifi:0x%08x wlan:0x%08x\n", __FUNCTION__, __LINE__, wifi, wlan); diff --git a/bsp/amebaz/rtconfig.h b/bsp/amebaz/rtconfig.h index 5d8ee1df025..92bac2d2940 100644 --- a/bsp/amebaz/rtconfig.h +++ b/bsp/amebaz/rtconfig.h @@ -75,6 +75,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* Using WiFi */ diff --git a/bsp/apollo2/rtconfig.h b/bsp/apollo2/rtconfig.h index 5f94db4eff7..dfa458bc4e0 100644 --- a/bsp/apollo2/rtconfig.h +++ b/bsp/apollo2/rtconfig.h @@ -99,6 +99,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ #define RT_USING_I2C diff --git a/bsp/apollo2/rtconfig.py b/bsp/apollo2/rtconfig.py index 506ee78ecae..79989091097 100644 --- a/bsp/apollo2/rtconfig.py +++ b/bsp/apollo2/rtconfig.py @@ -64,16 +64,14 @@ LINK = 'armlink' TARGET_EXT = 'axf' - DEVICE = ' --device DARMSTM' - CFLAGS = DEVICE + ' --apcs=interwork' + DEVICE = ' --cpu Cortex-M4' + CFLAGS = DEVICE + ' --c99 --apcs=interwork' AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-apollo2.map --scatter rtthread-apollo2.sct' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-apollo2.map --scatter rtthread.sct' - CFLAGS += ' --c99' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' - EXEC_PATH += '/arm/bin40/' + EXEC_PATH += '/ARM/ARMCC/bin' if BUILD == 'debug': CFLAGS += ' -g -O0' diff --git a/bsp/asm9260t/.config b/bsp/asm9260t/.config index ed77c0678d2..e634c994c8d 100644 --- a/bsp/asm9260t/.config +++ b/bsp/asm9260t/.config @@ -83,6 +83,7 @@ CONFIG_FINSH_CMD_SIZE=80 # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_I2C is not set diff --git a/bsp/asm9260t/rtconfig.h b/bsp/asm9260t/rtconfig.h index def7f36a713..bf1f76fefbe 100644 --- a/bsp/asm9260t/rtconfig.h +++ b/bsp/asm9260t/rtconfig.h @@ -75,6 +75,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_I2C is not set */ diff --git a/bsp/at91sam9260/.config b/bsp/at91sam9260/.config new file mode 100644 index 00000000000..a19ac15d3d9 --- /dev/null +++ b/bsp/at91sam9260/.config @@ -0,0 +1,311 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +CONFIG_RT_USING_INTERRUPT_INFO=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="dbgu" + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_STM32F4_HAL is not set +# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_RT_USING_DBGU=y +# CONFIG_RT_USING_UART0 is not set +# CONFIG_RT_USING_UART1 is not set +# CONFIG_RT_USING_UART2 is not set +# CONFIG_RT_USING_UART3 is not set +CONFIG_RT_USING_LED=y diff --git a/bsp/at91sam9260/Kconfig b/bsp/at91sam9260/Kconfig new file mode 100644 index 00000000000..f07968f982a --- /dev/null +++ b/bsp/at91sam9260/Kconfig @@ -0,0 +1,46 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config RT_USING_DBGU + bool "Using RT_USING_DBGU" + default y + +config RT_USING_UART0 + bool "Using RT_USING_UART0" + default n + +config RT_USING_UART1 + bool "Using RT_USING_UART1" + default n + +config RT_USING_UART2 + bool "Using RT_USING_UART2" + default n + +config RT_USING_UART3 + bool "Using RT_USING_UART3" + default n + +config RT_USING_LED + bool "Using RT_USING_LED" + default y + help + led blink demo + diff --git a/bsp/at91sam9260/applications/application.c b/bsp/at91sam9260/applications/application.c index 5800ba53d25..48c526957a4 100644 --- a/bsp/at91sam9260/applications/application.c +++ b/bsp/at91sam9260/applications/application.c @@ -96,7 +96,10 @@ int main(void) #endif } #endif - + +#ifdef RT_USING_LED + rt_led_app_init(); +#endif } #ifdef RT_USING_LED @@ -121,7 +124,6 @@ void rt_led_thread_entry(void* parameter) led_on(3); else led_off(3); - } } #endif diff --git a/bsp/at91sam9260/drivers/board.c b/bsp/at91sam9260/drivers/board.c index d058c309355..a7ec6008dae 100644 --- a/bsp/at91sam9260/drivers/board.c +++ b/bsp/at91sam9260/drivers/board.c @@ -43,7 +43,7 @@ extern unsigned char __bss_end__; #define HEAP_BEGIN (__section_end(".noinit")) #endif -#define HEAP_END (0x24000000) +#define HEAP_END (((rt_uint32_t)HEAP_BEGIN & (0xF0 << 24)) + (32 << 20)) extern void rt_hw_interrupt_init(void); extern void rt_hw_clock_init(void); @@ -57,8 +57,8 @@ static struct mem_desc at91_mem_desc[] = { { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */ { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */ { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */ - { 0x90000000, 0x90400000 - 1, 0x00200000, RW_NCNB }, /* 4K SRAM0 + 4k SRAM1 */ - { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ + { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */ + { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ }; diff --git a/bsp/at91sam9260/drivers/led.c b/bsp/at91sam9260/drivers/led.c index 6c8f2021086..3791b2a5685 100644 --- a/bsp/at91sam9260/drivers/led.c +++ b/bsp/at91sam9260/drivers/led.c @@ -26,12 +26,27 @@ #include #include "led.h" +#if 1 +// GB9260 board +#define PIO_LED AT91_PIOB +#define LED1 (1 << 25) // LED_SYS +#define LED2 (0) +#define LED3 (1 << 23) // LED_USR +#define LED_ALL (LED1 | LED2 | LED3) +#else +#define PIO_LED AT91_PIOC +#define LED1 (1 << 8) +#define LED2 (1 << 11) +#define LED3 (1 << 6) +#define LED_ALL (LED1 | LED2 | LED3) +#endif + void led_init(void) { - at91_sys_write(AT91_PIOC, (1<<8)|(1<<11)|(1<<6)); - at91_sys_write(AT91_PIOC+0x10, (1<<8)|(1<<11)|(1<<6)); - at91_sys_write(AT91_PIOC+0x64, (1<<8)|(1<<11)|(1<<6)); - at91_sys_write(AT91_PIOC+0x30, (1<<8)|(1<<11)|(1<<6)); + at91_sys_write(PIO_LED+0x00, LED_ALL); + at91_sys_write(PIO_LED+0x10, LED_ALL); + at91_sys_write(PIO_LED+0x64, LED_ALL); + at91_sys_write(PIO_LED+0x30, LED_ALL); } void led_on(int num) @@ -39,18 +54,17 @@ void led_on(int num) switch(num) { case 1: - at91_sys_write(AT91_PIOC+0x34, 1<<8); + at91_sys_write(PIO_LED+0x34, LED1); break; case 2: - at91_sys_write(AT91_PIOC+0x34, 1<<11); + at91_sys_write(PIO_LED+0x34, LED2); break; case 3: - at91_sys_write(AT91_PIOC+0x34, 1<<6); + at91_sys_write(PIO_LED+0x34, LED3); break; default: break; } - } void led_off(int num) @@ -58,16 +72,15 @@ void led_off(int num) switch(num) { case 1: - at91_sys_write(AT91_PIOC+0x30, 1<<8); + at91_sys_write(PIO_LED+0x30, LED1); break; case 2: - at91_sys_write(AT91_PIOC+0x30, 1<<11); + at91_sys_write(PIO_LED+0x30, LED2); break; case 3: - at91_sys_write(AT91_PIOC+0x30, 1<<6); + at91_sys_write(PIO_LED+0x30, LED3); break; default: break; } - //at91_sys_write(AT91_PIOC+0x30, 1<<8); } diff --git a/bsp/at91sam9260/platform/interrupt.c b/bsp/at91sam9260/platform/interrupt.c index 7a83fca494b..07084605787 100644 --- a/bsp/at91sam9260/platform/interrupt.c +++ b/bsp/at91sam9260/platform/interrupt.c @@ -30,7 +30,7 @@ extern rt_uint32_t rt_interrupt_nest; /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; rt_uint32_t rt_thread_switch_interrupt_flag; @@ -101,17 +101,17 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector, void *param) rt_uint32_t isr, pio, irq_n; void *parameter; - if (vector == AT91SAM9260_ID_PIOA) + if (vector == AT91SAM9260_ID_PIOA) { pio = AT91_PIOA; irq_n = AIC_IRQS; } - else if (vector == AT91SAM9260_ID_PIOB) + else if (vector == AT91SAM9260_ID_PIOB) { pio = AT91_PIOB; irq_n = AIC_IRQS + 32; } - else if (vector == AT91SAM9260_ID_PIOC) + else if (vector == AT91SAM9260_ID_PIOC) { pio = AT91_PIOC; irq_n = AIC_IRQS + 32*2; @@ -119,9 +119,9 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector, void *param) else return RT_NULL; isr = at91_sys_read(pio+PIO_ISR) & at91_sys_read(pio+PIO_IMR); - while (isr) + while (isr) { - if (isr & 1) + if (isr & 1) { parameter = irq_desc[irq_n].param; irq_desc[irq_n].handler(irq_n, parameter); @@ -175,7 +175,7 @@ static void at91_gpio_irq_init() { int i, idx; char *name[] = {"PIOA", "PIOB", "PIOC"}; - + at91_sys_write(AT91_PIOA+PIO_IDR, 0xffffffff); at91_sys_write(AT91_PIOB+PIO_IDR, 0xffffffff); at91_sys_write(AT91_PIOC+PIO_IDR, 0xffffffff); @@ -183,11 +183,13 @@ static void at91_gpio_irq_init() idx = AT91SAM9260_ID_PIOA; for (i = 0; i < 3; i++) { - rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]); irq_desc[idx].handler = (rt_isr_handler_t)at91_gpio_irq_handle; irq_desc[idx].param = RT_NULL; +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]); irq_desc[idx].counter = 0; - idx++; +#endif + idx++; } rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA); @@ -203,7 +205,7 @@ void rt_hw_interrupt_init(void) { register rt_uint32_t idx; rt_uint32_t *priority = at91sam9260_default_irq_priority; - + at91_extern_irq = (1UL << AT91SAM9260_ID_IRQ0) | (1UL << AT91SAM9260_ID_IRQ1) | (1UL << AT91SAM9260_ID_IRQ2); @@ -213,10 +215,12 @@ void rt_hw_interrupt_init(void) /* init exceptions table */ for(idx=0; idx < MAX_HANDLERS; idx++) { - rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; irq_desc[idx].param = RT_NULL; - irq_desc[idx].counter = 0; +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); + irq_desc[idx].counter = 0; +#endif } at91_gpio_irq_init(); @@ -234,15 +238,15 @@ static void at91_gpio_irq_mask(int irq) bank = (irq - AIC_IRQS)>>5; - if (bank == 0) + if (bank == 0) { pio = AT91_PIOA; } - else if (bank == 1) + else if (bank == 1) { pio = AT91_PIOB; } - else if (bank == 2) + else if (bank == 2) { pio = AT91_PIOC; } @@ -258,7 +262,7 @@ static void at91_gpio_irq_mask(int irq) */ void rt_hw_interrupt_mask(int irq) { - if (irq >= AIC_IRQS) + if (irq >= AIC_IRQS) { at91_gpio_irq_mask(irq); } @@ -275,15 +279,15 @@ static void at91_gpio_irq_umask(int irq) bank = (irq - AIC_IRQS)>>5; - if (bank == 0) + if (bank == 0) { pio = AT91_PIOA; } - else if (bank == 1) + else if (bank == 1) { pio = AT91_PIOB; } - else if (bank == 2) + else if (bank == 2) { pio = AT91_PIOC; } @@ -299,7 +303,7 @@ static void at91_gpio_irq_umask(int irq) */ void rt_hw_interrupt_umask(int irq) { - if (irq >= AIC_IRQS) + if (irq >= AIC_IRQS) { at91_gpio_irq_umask(irq); } @@ -328,10 +332,12 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, old_handler = irq_desc[vector].handler; if (handler != RT_NULL) { - rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); irq_desc[vector].handler = (rt_isr_handler_t)handler; irq_desc[vector].param = param; +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); irq_desc[vector].counter = 0; +#endif } } @@ -353,15 +359,15 @@ static int at91_aic_set_type(unsigned irq, unsigned type) srctype = AT91_AIC_SRCTYPE_RISING; break; case IRQ_TYPE_LEVEL_LOW: - // only supported on external interrupts - if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) + // only supported on external interrupts + if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) srctype = AT91_AIC_SRCTYPE_LOW; else return -1; break; case IRQ_TYPE_EDGE_FALLING: - // only supported on external interrupts - if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) + // only supported on external interrupts + if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) srctype = AT91_AIC_SRCTYPE_FALLING; else return -1; @@ -409,7 +415,7 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id) void list_irq(void) { int irq; - + rt_kprintf("number\tcount\tname\n"); for (irq = 0; irq < MAX_HANDLERS; irq++) { diff --git a/bsp/at91sam9260/rtconfig.h b/bsp/at91sam9260/rtconfig.h index 62ceba49140..816054c3e10 100755 --- a/bsp/at91sam9260/rtconfig.h +++ b/bsp/at91sam9260/rtconfig.h @@ -1,253 +1,160 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 32 +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 - -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 256 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -#define RT_DEBUG -//#define SCHEDULER_DEBUG -/* #define RT_THREAD_DEBUG */ +/* RT-Thread Kernel */ +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK - -#define RT_USING_INTERRUPT_INFO - -/* Using Hook */ #define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG -/* Using Software Timer */ -#define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 8 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 +/* Inter-Thread communication */ -/* SECTION: IPC */ -/* Using Semaphore */ #define RT_USING_SEMAPHORE - -/* Using Mutex */ #define RT_USING_MUTEX - -/* Using Event */ #define RT_USING_EVENT - -/* Using MailBox */ #define RT_USING_MAILBOX - -/* Using Message Queue */ #define RT_USING_MESSAGEQUEUE -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -#define RT_USING_MEMPOOL +/* Memory Management */ -/* Using Dynamic Heap Management */ +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM #define RT_USING_HEAP -/* Using Small MM */ -/* #define RT_USING_SMALL_MEM */ +/* Kernel Device Object */ -/* Using SLAB Allocator */ -#define RT_USING_SLAB +#define RT_USING_DEVICE +#define RT_USING_INTERRUPT_INFO +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "dbgu" -/* SECTION: the runtime libc library */ -/* the runtime libc library */ -#define RT_USING_LIBC -#define RT_USING_PTHREADS +/* RT-Thread Components */ -/* Using Module System */ -#define RT_USING_MODULE +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 -/* SECTION: Device System */ -/* Using Device System */ -#define RT_USING_DEVICE +/* C++ features */ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA -/* SECTION: Console options */ -#define RT_USING_CONSOLE -/* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "dbgu" +/* Command shell */ -/* SECTION: finsh, a C-Express shell */ -/* Using FinSH as Shell*/ #define RT_USING_FINSH -/* Using symbol table */ +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 #define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 -/* SECTION: C++ support */ -/* Using C++ support */ -/* #define RT_USING_CPLUSPLUS */ +/* Device virtual file system */ -/* SECTION: Device filesystem support */ -/* using DFS support */ #define RT_USING_DFS -#define RT_USING_DFS_ELMFAT -/* use long file name feature */ -#define RT_DFS_ELM_USE_LFN 2 -#define RT_DFS_ELM_REENTRANT -/* define OEM code page */ -#define RT_DFS_ELM_CODE_PAGE 936 -/* Using OEM code page file */ -// #define RT_DFS_ELM_CODE_PAGE_FILE -/* the max number of file length */ -#define RT_DFS_ELM_MAX_LFN 128 -/* #define RT_USING_DFS_YAFFS2 */ +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 #define RT_USING_DFS_DEVFS -#define RT_USING_DFS_NFS -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +/* Device Drivers */ -#define DFS_USING_WORKDIR +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_PIN -/* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 4 -/* the max number of opened files */ -#define DFS_FD_MAX 16 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +/* Using USB */ -/* Enable freemodbus protocol stack*/ -/* #define RT_USING_MODBUS */ -//#define RT_USING_LED +/* POSIX layer and C standard library */ -#define RT_USING_SDIO +#define RT_USING_LIBC -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS +/* Network */ -#define RT_USING_DBGU -/* #define RT_USING_UART0 */ -/* #define RT_USING_UART1 */ -/* #define RT_USING_UART2 */ -/* #define RT_USING_UART3 */ +/* Socket abstraction layer */ -/* SECTION: lwip, a lightweight TCP/IP protocol stack */ -/* Using lightweight TCP/IP protocol stack */ -#define RT_USING_LWIP -#define RT_LWIP_DNS -/* Trace LwIP protocol */ -// #define RT_LWIP_DEBUG +/* light weight TCP/IP stack */ -/* Enable ICMP protocol */ -#define RT_LWIP_ICMP -/* Enable IGMP protocol */ -#define RT_LWIP_IGMP +/* Modbus master and slave stack */ -/* Enable UDP protocol */ -#define RT_LWIP_UDP -/* Enable TCP protocol */ -#define RT_LWIP_TCP +/* AT commands */ -/* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 -/* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 1024*10 +/* VBUS(Virtual Software BUS) */ -/* TCP receive window. */ -#define RT_LWIP_TCP_WND 1024*8 -/* Enable SNMP protocol */ -/* #define RT_LWIP_SNMP */ +/* Utilities */ -/* Using DHCP */ -/* #define RT_LWIP_DHCP */ -/* ip address of target */ -#define RT_LWIP_IPADDR "192.168.1.30" +/* RT-Thread online packages */ -/* gateway address of target */ -#define RT_LWIP_GWADDR "192.168.1.1" +/* IoT - internet of things */ -/* mask address of target */ -#define RT_LWIP_MSKADDR "255.255.255.0" -/* the number of blocks for pbuf */ -#define RT_LWIP_PBUF_NUM 16 +/* Wi-Fi */ -/* the number of simultaneously queued TCP */ -#define RT_LWIP_TCP_SEG_NUM 40 +/* Marvell WiFi */ -/* thread priority of tcpip thread */ -#define RT_LWIP_TCPTHREAD_PRIORITY 128 -/* mail box size of tcpip thread to wait for */ -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 +/* Wiced WiFi */ -/* thread stack size of tcpip thread */ -#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 -/* thread priority of ethnetif thread */ -#define RT_LWIP_ETHTHREAD_PRIORITY 144 +/* IoT Cloud */ -/* mail box size of ethnetif thread to wait for */ -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 -/* thread stack size of ethnetif thread */ -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +/* security packages */ -/* SECTION: RTGUI support */ -/* using RTGUI support */ -/* #define RT_USING_RTGUI */ +/* language packages */ -/* name length of RTGUI object */ -//#define RTGUI_NAME_MAX 16 -/* support 16 weight font */ -//#define RTGUI_USING_FONT16 -/* support 16 weight font */ -//#define RTGUI_USING_FONT12 -/* support Chinese font */ -//#define RTGUI_USING_FONTHZ -/* use DFS as file interface */ -//#define RTGUI_USING_DFS_FILERW -/* use font file as Chinese font */ -/* #define RTGUI_USING_HZ_FILE */ -/* use Chinese bitmap font */ -//#define RTGUI_USING_HZ_BMP -/* use small size in RTGUI */ -/* #define RTGUI_USING_SMALL_SIZE */ -/* use mouse cursor */ -/* #define RTGUI_USING_MOUSE_CURSOR */ -/* SECTION: FTK support */ -/* using FTK support */ -/* #define RT_USING_FTK */ +/* multimedia packages */ -/* - * Note on FTK: - * - * FTK depends : - * #define RT_USING_NEWLIB - * #define DFS_USING_WORKDIR - * - * And the maximal length must great than 64 - * #define RT_DFS_ELM_MAX_LFN 128 - */ -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + +/* samples: kernel and components samples */ + + +/* example package: hello */ + +#define RT_USING_DBGU +#define RT_USING_LED #endif diff --git a/bsp/at91sam9260/rtconfig.py b/bsp/at91sam9260/rtconfig.py index 3aefb30fad9..da3be0fd59b 100755 --- a/bsp/at91sam9260/rtconfig.py +++ b/bsp/at91sam9260/rtconfig.py @@ -11,6 +11,12 @@ if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' EXEC_PATH = r'D:\arm-2013.11\bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') diff --git a/bsp/at91sam9260/template.ewp b/bsp/at91sam9260/template.ewp new file mode 100644 index 00000000000..c9cc04c3db6 --- /dev/null +++ b/bsp/at91sam9260/template.ewp @@ -0,0 +1,1914 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 24 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/at91sam9260/template.eww b/bsp/at91sam9260/template.eww new file mode 100644 index 00000000000..bd036bb4c98 --- /dev/null +++ b/bsp/at91sam9260/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/at91sam9260/template.uvopt b/bsp/at91sam9260/template.uvopt new file mode 100644 index 00000000000..2dca5102b8b --- /dev/null +++ b/bsp/at91sam9260/template.uvopt @@ -0,0 +1,174 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 18432000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 16 + + + 0 + Datasheet + DATASHTS\ATMEL\AT91SAM9260_DS.PDF + + + 1 + Summary + DATASHTS\ATMEL\AT91SAM9260_DC.PDF + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 5 + + + + + + + + + + .\jlink\at91sam9260.ini + Segger\JLTAgdi.dll + + + + 0 + JLTAgdi + -O558 -J1 -Y1000 -Z1 -FO0 -FD200000 -FC800 -FN0 + + + 0 + UL2ARM + -UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/at91sam9260/template.uvproj b/bsp/at91sam9260/template.uvproj new file mode 100644 index 00000000000..c644bc54408 --- /dev/null +++ b/bsp/at91sam9260/template.uvproj @@ -0,0 +1,407 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + + + AT91SAM9260 + Atmel + IRAM(0x200000-0x200FFF) IRAM2(0x300000-0x300FFF) IROM(0x100000-0x107FFF) CLOCK(18432000) CPUTYPE(ARM926EJ-S) + + "STARTUP\Atmel\SAM9260.s" ("Atmel AT91SAM9260 Startup Code") + UL2ARM(-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00) + 4210 + AT91SAM9260.H + + + + + + + + + + + 0 + 0 + + + + Atmel\SAM9260\ + Atmel\SAM9260\ + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARM.DLL + -cAT91SAM9260 + DARMATS9.DLL + -p91SAM9260 + SARM.DLL + + TARMATS9.DLL + -p91SAM9260 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + + 0 + 5 + + + + + + + + + + + + + .\jlink\at91sam9260.ini + Segger\JLTAgdi.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2ARM.DLL + "" () + .\jlink\at91sam9260.ini + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + ARM926EJ-S + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x200000 + 0x1000 + + + 1 + 0x100000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x20000000 + 0x800000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x100000 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20800000 + 0x1800000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x200000 + 0x1000 + + + 0 + 0x300000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + RT_USING_INTERRUPT_INFO + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + .\platform + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x20000000 + 0x20800000 + + .\link_scripts\at91sam9260_ram.scat + + + + + + + + + + + + diff --git a/bsp/beaglebone/.config b/bsp/beaglebone/.config index 0ff69f11644..409e89d18e7 100644 --- a/bsp/beaglebone/.config +++ b/bsp/beaglebone/.config @@ -115,6 +115,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/beaglebone/rtconfig.h b/bsp/beaglebone/rtconfig.h index 5bc7ab92dba..c49528049dd 100644 --- a/bsp/beaglebone/rtconfig.h +++ b/bsp/beaglebone/rtconfig.h @@ -77,6 +77,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using USB */ diff --git a/bsp/ck802/.config b/bsp/ck802/.config index 4284658f943..e91f93fd0e1 100644 --- a/bsp/ck802/.config +++ b/bsp/ck802/.config @@ -97,6 +97,7 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/ck802/rtconfig.h b/bsp/ck802/rtconfig.h index 3eb48b11f00..076d48e5345 100644 --- a/bsp/ck802/rtconfig.h +++ b/bsp/ck802/rtconfig.h @@ -71,6 +71,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using USB */ diff --git a/bsp/dm365/.config b/bsp/dm365/.config index 30dc0871e51..6974ff8ae00 100644 --- a/bsp/dm365/.config +++ b/bsp/dm365/.config @@ -134,6 +134,7 @@ CONFIG_RT_NFS_HOST_EXPORT="192.168.1.5:/" CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/dm365/rtconfig.h b/bsp/dm365/rtconfig.h index ae16abdca6a..4f3698f1245 100644 --- a/bsp/dm365/rtconfig.h +++ b/bsp/dm365/rtconfig.h @@ -125,6 +125,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/fh8620/rtconfig.h b/bsp/fh8620/rtconfig.h index cefbff053c1..01a2d2d45c6 100644 --- a/bsp/fh8620/rtconfig.h +++ b/bsp/fh8620/rtconfig.h @@ -74,6 +74,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // #define RT_UART_RX_BUFFER_SIZE 64 // diff --git a/bsp/frdm-k64f/MK64F.sct b/bsp/frdm-k64f/MK64F.sct index 1aafaed2009..4c91774b2d1 100644 --- a/bsp/frdm-k64f/MK64F.sct +++ b/bsp/frdm-k64f/MK64F.sct @@ -7,7 +7,7 @@ LR_IROM1 0x00000000 0x100000 { ; load region size_region (1000k) } ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198 ; 0x40000 - 0x198 = 0x3FE68 - RW_IRAM1 0x1FFF0198 0x3FE68 { + RW_IRAM2 0x20000000 0x30000 { .ANY (+RW +ZI) } } diff --git a/bsp/frdm-k64f/rtconfig.h b/bsp/frdm-k64f/rtconfig.h index d8e6f6dbc5a..8d0ad639ce4 100644 --- a/bsp/frdm-k64f/rtconfig.h +++ b/bsp/frdm-k64f/rtconfig.h @@ -63,6 +63,7 @@ #define RT_USING_DEVICE_IPC /* Using Serial Device Driver Framework" default="true" */ #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA //
#define RT_USING_COMPONENTS_INIT diff --git a/bsp/frdm-k64f/rtconfig.py b/bsp/frdm-k64f/rtconfig.py index 1f4d8d246ef..e92c9b15e69 100644 --- a/bsp/frdm-k64f/rtconfig.py +++ b/bsp/frdm-k64f/rtconfig.py @@ -64,17 +64,16 @@ TARGET_EXT = 'axf' DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = DEVICE + ' --apcs=interwork' + CFLAGS = DEVICE + ' --c99 --apcs=interwork' AFLAGS = DEVICE LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-k64f.map --scatter MK64F.sct' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' - EXEC_PATH += '/arm/bin40/' + EXEC_PATH += '/ARM/ARMCC/bin' if BUILD == 'debug': - CFLAGS += ' --c99 -g -O0' + CFLAGS += ' -g -O0' AFLAGS += ' -g' else: CFLAGS += ' -O2' diff --git a/bsp/gd32303e-eval/.config b/bsp/gd32303e-eval/.config index 94c9a258f0a..b61d310f03b 100644 --- a/bsp/gd32303e-eval/.config +++ b/bsp/gd32303e-eval/.config @@ -120,6 +120,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/gd32303e-eval/rtconfig.h b/bsp/gd32303e-eval/rtconfig.h index 26f476db785..479ad99af56 100644 --- a/bsp/gd32303e-eval/rtconfig.h +++ b/bsp/gd32303e-eval/rtconfig.h @@ -87,6 +87,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_I2C #define RT_USING_PIN #define RT_USING_SPI diff --git a/bsp/gd32450z-eval/.config b/bsp/gd32450z-eval/.config index a04025b693f..e2f00a07fcb 100644 --- a/bsp/gd32450z-eval/.config +++ b/bsp/gd32450z-eval/.config @@ -131,6 +131,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/gd32450z-eval/rtconfig.h b/bsp/gd32450z-eval/rtconfig.h index 1eaeb4b827c..500aab62906 100644 --- a/bsp/gd32450z-eval/rtconfig.h +++ b/bsp/gd32450z-eval/rtconfig.h @@ -88,6 +88,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using USB */ diff --git a/bsp/gkipc/.config b/bsp/gkipc/.config index b3a1cd2628f..975b82b5b25 100644 --- a/bsp/gkipc/.config +++ b/bsp/gkipc/.config @@ -123,6 +123,7 @@ CONFIG_RT_NFS_HOST_EXPORT="192.168.10.82:/" # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/gkipc/rtconfig.h b/bsp/gkipc/rtconfig.h index 23df0f07042..2c0233cf29c 100644 --- a/bsp/gkipc/rtconfig.h +++ b/bsp/gkipc/rtconfig.h @@ -114,6 +114,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/imx6sx/cortex-a9/.config b/bsp/imx6sx/cortex-a9/.config index cb857b4c0f5..ce2e256f2cd 100644 --- a/bsp/imx6sx/cortex-a9/.config +++ b/bsp/imx6sx/cortex-a9/.config @@ -116,6 +116,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/imx6sx/cortex-a9/rtconfig.h b/bsp/imx6sx/cortex-a9/rtconfig.h index 71f7cf4d9b1..30de937b05a 100644 --- a/bsp/imx6sx/cortex-a9/rtconfig.h +++ b/bsp/imx6sx/cortex-a9/rtconfig.h @@ -77,6 +77,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using USB */ diff --git a/bsp/imx6ul/rtconfig.h b/bsp/imx6ul/rtconfig.h index f37f620a9c5..ee3857dcb86 100644 --- a/bsp/imx6ul/rtconfig.h +++ b/bsp/imx6ul/rtconfig.h @@ -72,6 +72,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // #define RT_UART_RX_BUFFER_SIZE 64 // diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c index d74ab47e233..1f4a98c57cd 100644 --- a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c @@ -33,7 +33,6 @@ */ #include "fsl_flexspi.h" - /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.flexspi" @@ -113,21 +112,21 @@ static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT]; #endif /*! @brief Pointers to flexspi bases for each instance. */ -static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS; +static FLEXSPI_Type *const s_flexspiBases[] SECTION("itcm") = FLEXSPI_BASE_PTRS; /*! @brief Pointers to flexspi IRQ number for each instance. */ -static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS; +static const IRQn_Type s_flexspiIrqs[] SECTION("itcm") = FLEXSPI_IRQS; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Clock name array */ -static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS; +static const clock_ip_name_t s_flexspiClock[] SECTION("itcm") = FLEXSPI_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /******************************************************************************* * Code ******************************************************************************/ -uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) +SECTION("itcm") uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) { uint32_t instance; @@ -145,7 +144,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) return instance; } -static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config) +SECTION("itcm") static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config) { bool isUnifiedConfig = true; uint32_t flexspiDllValue; @@ -199,7 +198,7 @@ static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t return flexspiDllValue; } -status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) +SECTION("itcm") status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) { status_t result = kStatus_Success; @@ -236,7 +235,7 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) return result; } -void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) +SECTION("itcm") void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) { uint32_t configValue = 0; uint8_t i = 0; @@ -309,7 +308,7 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1); } -void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) +SECTION("itcm") void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) { config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; config->enableSckFreeRunning = false; @@ -339,13 +338,13 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) config->ahbConfig.enableAHBCachable = false; } -void FLEXSPI_Deinit(FLEXSPI_Type *base) +SECTION("itcm") void FLEXSPI_Deinit(FLEXSPI_Type *base) { /* Reset peripheral. */ FLEXSPI_SoftwareReset(base); } -void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) +SECTION("itcm") void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) { uint32_t configValue = 0; uint8_t index = port >> 1; /* PortA with index 0, PortB with index 1. */ @@ -416,7 +415,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; } -void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count) +SECTION("itcm") void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count) { assert(index < 64U); @@ -443,7 +442,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, base->LUTCR = 0x01; } -status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) +SECTION("itcm") status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) { uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1; uint32_t status; @@ -491,7 +490,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size return result; } -status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) +SECTION("itcm") status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) { uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1; uint32_t status; @@ -561,7 +560,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) return result; } -status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) +SECTION("itcm") status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) { uint32_t configValue = 0; status_t result = kStatus_Success; @@ -618,7 +617,7 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) return result; } -void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, +SECTION("itcm") void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_callback_t callback, void *userData) @@ -643,7 +642,7 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, EnableIRQ(s_flexspiIrqs[instance]); } -status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer) +SECTION("itcm") status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer) { uint32_t configValue = 0; status_t result = kStatus_Success; @@ -709,7 +708,7 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl return result; } -status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count) +SECTION("itcm") status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count) { assert(handle); @@ -727,7 +726,7 @@ status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, return result; } -void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle) +SECTION("itcm") void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle) { assert(handle); @@ -735,7 +734,7 @@ void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle) handle->state = kFLEXSPI_Idle; } -void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) +SECTION("itcm") void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) { uint8_t status; status_t result; @@ -832,7 +831,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) #if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ #if defined(FLEXSPI) -void FLEXSPI_DriverIRQHandler(void) +SECTION("itcm") void FLEXSPI_DriverIRQHandler(void) { FLEXSPI_TransferHandleIRQ(FLEXSPI, s_flexspiHandle[0]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping @@ -844,7 +843,7 @@ void FLEXSPI_DriverIRQHandler(void) #endif #if defined(FLEXSPI0) -void FLEXSPI0_DriverIRQHandler(void) +void FLEXSPI0_DriverIRQHandler(void) SECTION("itcm") { FLEXSPI_TransferHandleIRQ(FLEXSPI0, s_flexspiHandle[0]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping @@ -855,7 +854,7 @@ void FLEXSPI0_DriverIRQHandler(void) } #endif #if defined(FLEXSPI1) -void FLEXSPI1_DriverIRQHandler(void) +void FLEXSPI1_DriverIRQHandler(void) SECTION("itcm") { FLEXSPI_TransferHandleIRQ(FLEXSPI1, s_flexspiHandle[1]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping diff --git a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h index e2f00393b3d..b1162924f90 100644 --- a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h +++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h @@ -34,7 +34,7 @@ #ifndef __FSL_FLEXSPI_H_ #define __FSL_FLEXSPI_H_ - +#include #include #include "fsl_device_registers.h" #include "fsl_common.h" @@ -401,7 +401,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, * * @param base FLEXSPI peripheral base address. */ -static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) +static SECTION("itcm") inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) { base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) @@ -415,7 +415,7 @@ static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) * @param base FLEXSPI peripheral base address. * @param enable True means enable FLEXSPI, false means disable. */ -static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) +static SECTION("itcm") inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) { if (enable) { @@ -439,7 +439,7 @@ static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) * @param base FLEXSPI peripheral base address. * @param mask FLEXSPI interrupt source. */ -static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask) +static SECTION("itcm") inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask) { base->INTEN |= mask; } @@ -450,7 +450,7 @@ static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask) * @param base FLEXSPI peripheral base address. * @param mask FLEXSPI interrupt source. */ -static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask) +static SECTION("itcm") inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask) { base->INTEN &= ~mask; } @@ -466,7 +466,7 @@ static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask) * @param base FLEXSPI peripheral base address. * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable. */ -static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable) +static SECTION("itcm") inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable) { if (enable) { @@ -484,7 +484,7 @@ static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable) * @param base FLEXSPI peripheral base address. * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable. */ -static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable) +static SECTION("itcm") inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable) { if (enable) { @@ -502,7 +502,7 @@ static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable) * @param base FLEXSPI peripheral base address. * @retval The tx fifo address. */ -static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base) +static SECTION("itcm") inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base) { return (uint32_t)&base->TFDR[0]; } @@ -513,7 +513,7 @@ static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base) * @param base FLEXSPI peripheral base address. * @retval The rx fifo address. */ -static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base) +static SECTION("itcm") inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base) { return (uint32_t)&base->RFDR[0]; } @@ -529,7 +529,7 @@ static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base) * @param txFifo Pass true to reset TX FIFO. * @param rxFifo Pass true to reset RX FIFO. */ -static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo) +static SECTION("itcm") inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo) { if (txFifo) { @@ -550,7 +550,7 @@ static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFi * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. * Pass NULL if this value is not required. */ -static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount) +static SECTION("itcm") inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount) { if (txCount) { @@ -574,7 +574,7 @@ static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, si * @param base FLEXSPI peripheral base address. * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status. */ -static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) +static SECTION("itcm") inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) { return base->INTR; } @@ -585,7 +585,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) * @param base FLEXSPI peripheral base address. * @param interrupt status flag. */ -static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask) +static SECTION("itcm") inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask) { base->INTR |= mask; } @@ -616,7 +616,7 @@ static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *por * @param base FLEXSPI peripheral base address. * @retval trigger source of current command sequence. */ -static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base) +static SECTION("itcm") inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base) { return (flexspi_arb_command_source_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT); } @@ -627,7 +627,7 @@ static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FL * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. * @retval error code when IP command error detected. */ -static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) +static SECTION("itcm") inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) { *index = (base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT; return (flexspi_ip_error_code_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT); @@ -639,7 +639,7 @@ static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. * @retval error code when AHB command error detected. */ -static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) +static SECTION("itcm") inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) { *index = (base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT; return (flexspi_ahb_error_code_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> @@ -652,7 +652,7 @@ static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Ty * @retval true Bus is idle. * @retval false Bus is busy. */ -static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) +static SECTION("itcm") inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) { return (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK); } @@ -668,7 +668,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) * @param base FLEXSPI peripheral base address. * @param enable True means enable parallel mode, false means disable parallel mode. */ -static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable) +static SECTION("itcm") inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable) { if (enable) { @@ -685,7 +685,7 @@ static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable) * @param base FLEXSPI peripheral base address. * @param enable True means enable parallel mode, false means disable parallel mode. */ -static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable) +static SECTION("itcm") inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable) { if (enable) { @@ -715,7 +715,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, * @param data The data bytes to send * @param fifoIndex Destination fifo index. */ -static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex) +static SECTION("itcm") inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex) { base->TFDR[fifoIndex] = data; } @@ -727,7 +727,7 @@ static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t * @param fifoIndex Source fifo index. * @return The data in the FIFO. */ -static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex) +static SECTION("itcm") inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex) { return base->RFDR[fifoIndex]; } diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript index fa1b4693f54..d22ab2b10a6 100644 --- a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript @@ -11,7 +11,13 @@ drv_cache.c CPPPATH = [cwd] CPPDEFINES = [] -# add sdram driver code +if GetDepend('BOARD_USING_QSPIFLASH'): + src += ['drv_flexspi_nor.c'] + +if GetDepend('BOARD_USING_HYPERFLASH'): + src += ['drv_flexspi_hyper.c'] + +# add sdram driver code if GetDepend('RT_USING_SDRAM'): src = src + ['drv_sdram.c'] @@ -21,7 +27,7 @@ if GetDepend('RT_USING_PIN'): # add rtc driver code if GetDepend('RT_USING_RTC_HP'): - src = src + ['drv_rtc.c'] + src += ['drv_rtc.c'] # add spibus driver code if GetDepend('RT_USING_SPI'): diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_hyper.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_hyper.c new file mode 100644 index 00000000000..aa851f7b391 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_hyper.c @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-07-05 ZYH the first version + */ + +#include +#define PRINTF rt_kprintf +#include "board.h" +#include +#include "drv_flexspi.h" + +#define DBG_ENABLE +#define DBG_SECTION_NAME "[Hyper]" +#define DBG_LEVEL DBG_LOG +#define DBG_COLOR +#include + +#define FLEXSPI_CLOCK kCLOCK_FlexSpi +#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10 +#define CUSTOM_LUT_LENGTH 48 + +static flexspi_device_config_t deviceconfig = { + .flexspiRootClk = 42000000, /* 42MHZ SPI serial clock */ + .isSck2Enabled = false, + .flashSize = FLASH_SIZE, + .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, + .CSInterval = 2, + .CSHoldTime = 0, + .CSSetupTime = 3, + .dataValidTime = 1, + .columnspace = 3, + .enableWordAddress = true, + .AWRSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA, + .AWRSeqNumber = 1, + .ARDSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA, + .ARDSeqNumber = 1, + .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, + .AHBWriteWaitInterval = 20, +}; + +static uint32_t customLUT[CUSTOM_LUT_LENGTH] = { + /* Read Data */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04), + + /* Write Data */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02), + /* Read Status */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), + + /* Write Enable */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + + /* Erase Sector */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), + + /* program page */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80), +}; + + + +SECTION("itcm") status_t flexspi_nor_hyperbus_read(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) +{ + flexspi_transfer_t flashXfer; + status_t status; + flashXfer.deviceAddress = addr * 2; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA; + flashXfer.data = buffer; + flashXfer.dataSize = bytes; + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + return status; + } + return status; +} + +SECTION("itcm") status_t flexspi_nor_hyperbus_write(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) +{ + flexspi_transfer_t flashXfer; + status_t status; + flashXfer.deviceAddress = addr * 2; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA; + flashXfer.data = buffer; + flashXfer.dataSize = bytes; + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + return status; + } + return status; +} + +SECTION("itcm") status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) +{ + flexspi_transfer_t flashXfer; + status_t status; + /* Write neable */ + flashXfer.deviceAddress = baseAddr; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 2; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking(base, &flashXfer); + return status; +} + +SECTION("itcm") status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) +{ + /* Wait status ready. */ + bool isBusy; + uint32_t readValue; + status_t status; + flexspi_transfer_t flashXfer; + + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 2; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS; + flashXfer.data = &readValue; + flashXfer.dataSize = 2; + + do + { + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + return status; + } + if (readValue & 0x8000) + { + isBusy = false; + } + else + { + isBusy = true; + } + + if (readValue & 0x3200) + { + status = kStatus_Fail; + break; + } + + } while (isBusy); + + return status; +} + +SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) +{ + status_t status; + flexspi_transfer_t flashXfer; + rt_uint32_t level; + level = rt_hw_interrupt_disable(); + FLEXSPI_Enable(FLEXSPI, false); + CLOCK_DisableClock(FLEXSPI_CLOCK); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */ + CLOCK_EnableClock(FLEXSPI_CLOCK); + FLEXSPI_Enable(FLEXSPI, true); + /* Write enable */ + status = flexspi_nor_write_enable(base, address); + + if (status != kStatus_Success) + { + FLEXSPI_Enable(FLEXSPI, false); + CLOCK_DisableClock(FLEXSPI_CLOCK); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ + CLOCK_EnableClock(FLEXSPI_CLOCK); + FLEXSPI_Enable(FLEXSPI, true); + FLEXSPI_SoftwareReset(FLEXSPI); + rt_hw_interrupt_enable(level); + return status; + } + + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 4; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + FLEXSPI_Enable(FLEXSPI, false); + CLOCK_DisableClock(FLEXSPI_CLOCK); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ + CLOCK_EnableClock(FLEXSPI_CLOCK); + FLEXSPI_Enable(FLEXSPI, true); + FLEXSPI_SoftwareReset(FLEXSPI); + rt_hw_interrupt_enable(level); + return status; + } + + status = flexspi_nor_wait_bus_busy(base); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE); + rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE); + FLEXSPI_Enable(FLEXSPI, false); + CLOCK_DisableClock(FLEXSPI_CLOCK); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ + CLOCK_EnableClock(FLEXSPI_CLOCK); + FLEXSPI_Enable(FLEXSPI, true); + FLEXSPI_SoftwareReset(FLEXSPI); + rt_hw_interrupt_enable(level); + return status; +} + + SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src) +{ + status_t status; + flexspi_transfer_t flashXfer; + rt_uint32_t level; + level = rt_hw_interrupt_disable(); + FLEXSPI_Enable(FLEXSPI, false); + CLOCK_DisableClock(FLEXSPI_CLOCK); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */ + CLOCK_EnableClock(FLEXSPI_CLOCK); + FLEXSPI_Enable(FLEXSPI, true); + /* Write neable */ + status = flexspi_nor_write_enable(base, address); + + if (status != kStatus_Success) + { + rt_hw_interrupt_enable(level); + return status; + } + + /* Prepare page program command */ + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 2; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM; + flashXfer.data = (uint32_t *)src; + flashXfer.dataSize = FLASH_PAGE_SIZE; + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + rt_hw_interrupt_enable(level); + return status; + } + + status = flexspi_nor_wait_bus_busy(base); + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE); + rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE); + FLEXSPI_Enable(FLEXSPI, false); + CLOCK_DisableClock(FLEXSPI_CLOCK); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ + CLOCK_EnableClock(FLEXSPI_CLOCK); + FLEXSPI_Enable(FLEXSPI, true); + FLEXSPI_SoftwareReset(FLEXSPI); + rt_hw_interrupt_enable(level); + return status; +} + +SECTION("itcm") status_t flexspi_nor_hyperflash_cfi(FLEXSPI_Type *base) +{ + /* + * Read ID-CFI Parameters + */ + // CFI Entry + status_t status; + uint32_t buffer[2]; + uint32_t data = 0x9800; + status = flexspi_nor_hyperbus_write(base, 0x555, &data, 2); + if (status != kStatus_Success) + { + return status; + } + // ID-CFI Read + // Read Query Unique ASCII String + status = flexspi_nor_hyperbus_read(base, 0x10, &buffer[0], sizeof(buffer)); + if (status != kStatus_Success) + { + return status; + } + buffer[1] &= 0xFFFF; + // Check that the data read out is unicode "QRY" in big-endian order + if ((buffer[0] != 0x52005100) || (buffer[1] != 0x5900)) + { + status = kStatus_Fail; + return status; + } + // ASO Exit + data = 0xF000; + status = flexspi_nor_hyperbus_write(base, 0x0, &data, 2); + if (status != kStatus_Success) + { + return status; + } + return status; +} +SECTION("itcm") int rt_hw_flexspi_init(void) +{ + flexspi_config_t config; + status_t status; + rt_uint32_t level; + level = rt_hw_interrupt_disable(); + // Set flexspi root clock to 166MHZ. + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 26); /* Set PLL3 PFD0 clock 332MHZ. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */ + + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 83M, DDR mode, internal clock 42M. */ + + + /*Get FLEXSPI default settings and configure the flexspi. */ + FLEXSPI_GetDefaultConfig(&config); + + /*Set AHB buffer size for reading data through AHB bus. */ + config.ahbConfig.enableAHBPrefetch = true; + /*Allow AHB read start address do not follow the alignment requirement. */ + config.ahbConfig.enableReadAddressOpt = true; + /* enable diff clock and DQS */ + config.enableSckBDiffOpt = true; + config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad; + config.enableCombination = true; + FLEXSPI_Init(FLEXSPI, &config); + + /* Configure flash settings according to serial flash feature. */ + FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1); + + /* Update LUT table. */ + FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + + status = flexspi_nor_hyperflash_cfi(FLEXSPI); + /* Get vendor ID. */ + if (status != kStatus_Success) + { + FLEXSPI_Enable(FLEXSPI, false); + CLOCK_DisableClock(FLEXSPI_CLOCK); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ + CLOCK_EnableClock(FLEXSPI_CLOCK); + FLEXSPI_Enable(FLEXSPI, true); + FLEXSPI_SoftwareReset(FLEXSPI); + rt_hw_interrupt_enable(level); + return status; + } + FLEXSPI_Enable(FLEXSPI, false); + CLOCK_DisableClock(FLEXSPI_CLOCK); + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */ + CLOCK_EnableClock(FLEXSPI_CLOCK); + FLEXSPI_Enable(FLEXSPI, true); + FLEXSPI_SoftwareReset(FLEXSPI); + rt_hw_interrupt_enable(level); + return 0; +} diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_nor.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_nor.c new file mode 100644 index 00000000000..c48e43c2e01 --- /dev/null +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_nor.c @@ -0,0 +1,373 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-07-05 ZYH the first version + */ +#include +#define PRINTF rt_kprintf +#include "board.h" +#include +#include "drv_flexspi.h" +#define DBG_ENABLE +#define DBG_SECTION_NAME "[FLEXSPI]" +#define DBG_LEVEL DBG_LOG +#define DBG_COLOR +#include + +#define FLEXSPI_CLOCK kCLOCK_FlexSpi +#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0 +#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 1 +#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 3 +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 4 +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6 +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7 +#define NOR_CMD_LUT_SEQ_IDX_READID 8 +#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9 +#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10 +#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12 +#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 13 +#define CUSTOM_LUT_LENGTH 60 +#define FLASH_BUSY_STATUS_POL 1 +#define FLASH_BUSY_STATUS_OFFSET 0 + +static flexspi_device_config_t deviceconfig = +{ + .flexspiRootClk = 100000000, + .flashSize = FLASH_SIZE, + .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, + .CSInterval = 2, + .CSHoldTime = 3, + .CSSetupTime = 3, + .dataValidTime = 0, + .columnspace = 0, + .enableWordAddress = 0, + .AWRSeqIndex = 0, + .AWRSeqNumber = 0, + .ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD, + .ARDSeqNumber = 1, + .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, + .AHBWriteWaitInterval = 0, +}; + +static uint32_t customLUT[CUSTOM_LUT_LENGTH] = +{ + /* Normal read mode -SDR */ + [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Fast read mode - SDR */ + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Fast read quad mode - SDR */ + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x6B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04), + + /* Read extend parameters */ + [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Write Enable */ + [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Erase Sector */ + [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + + /* Page Program - single mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Page Program - quad mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Read ID */ + [4 * NOR_CMD_LUT_SEQ_IDX_READID] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xAB, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_READID + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Enable Quad mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04), + + /* Enter QPI mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x38, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Exit QPI mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xFF, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Read status register */ + [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Erase Chip */ + [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), +}; + + + +SECTION("itcm") static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) +{ + flexspi_transfer_t flashXfer; + status_t status; + + /* Write neable */ + flashXfer.deviceAddress = baseAddr; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + return status; +} + +SECTION("itcm") static status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) +{ + /* Wait status ready. */ + bool isBusy; + uint32_t readValue; + status_t status; + flexspi_transfer_t flashXfer; + + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; + flashXfer.data = &readValue; + flashXfer.dataSize = 1; + + do + { + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + return status; + } + if (FLASH_BUSY_STATUS_POL) + { + if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) + { + isBusy = true; + } + else + { + isBusy = false; + } + } + else + { + if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) + { + isBusy = false; + } + else + { + isBusy = true; + } + } + + } + while (isBusy); + + return status; +} + +SECTION("itcm") static status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base) +{ + flexspi_transfer_t flashXfer; + status_t status; + uint32_t writeValue = 0x40; + + /* Write neable */ + status = flexspi_nor_write_enable(base, 0); + + if (status != kStatus_Success) + { + return status; + } + + /* Enable quad mode. */ + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG; + flashXfer.data = &writeValue; + flashXfer.dataSize = 1; + + status = FLEXSPI_TransferBlocking(base, &flashXfer); + if (status != kStatus_Success) + { + dbg_log(DBG_ERROR, "flexspi tranfer error\n"); + dbg_here + return status; + } + + status = flexspi_nor_wait_bus_busy(base); + + return status; +} + +SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Write enable */ + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + dbg_log(DBG_ERROR, "flexspi tranfer error\n"); + dbg_here + return status; + } + + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + dbg_log(DBG_ERROR, "flexspi tranfer error\n"); + dbg_here + return status; + } + + status = flexspi_nor_wait_bus_busy(base); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE); + rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE); + return status; +} + +SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Write neable */ + status = flexspi_nor_write_enable(base, address); + + if (status != kStatus_Success) + { + return status; + } + + /* Prepare page program command */ + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; + flashXfer.data = (uint32_t *)src; + flashXfer.dataSize = FLASH_PAGE_SIZE; + status = FLEXSPI_TransferBlocking(base, &flashXfer); + + if (status != kStatus_Success) + { + return status; + } + + status = flexspi_nor_wait_bus_busy(base); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE); + rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE); + return status; +} + +SECTION("itcm") static status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId) +{ + uint32_t temp; + flexspi_transfer_t flashXfer; + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID; + flashXfer.data = &temp; + flashXfer.dataSize = 1; + + status_t status = FLEXSPI_TransferBlocking(base, &flashXfer); + + *vendorId = temp; + + return status; +} + +SECTION("itcm") int rt_hw_flexspi_init(void) +{ + flexspi_config_t config; + status_t status; + uint8_t vendorID = 0; + + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + rt_uint32_t level; + level = rt_hw_interrupt_disable(); + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24); /* Set PLL3 PFD0 clock 360MHZ. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* flexspi clock 120M. */ + + dbg_log(DBG_INFO, "NorFlash Init\r\n"); + + FLEXSPI_GetDefaultConfig(&config); + + config.ahbConfig.enableAHBPrefetch = true; + FLEXSPI_Init(FLEXSPI, &config); + + FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1); + + FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH); + + status = flexspi_nor_get_vendor_id(FLEXSPI, &vendorID); + if (status != kStatus_Success) + { + return status; + } + dbg_log(DBG_INFO, "Vendor ID: 0x%x\r\n", vendorID); + + status = flexspi_nor_enable_quad_mode(FLEXSPI); + if (status != kStatus_Success) + { + dbg_log(DBG_ERROR, "Entry Quad mode failed\r\n"); + return status; + } + dbg_log(DBG_INFO, "NorFlash Init Done\r\n"); + rt_hw_interrupt_enable(level); + return 0; +} diff --git a/bsp/imxrt/imxrt1050-ArchMix/.config b/bsp/imxrt/imxrt1050-ArchMix/.config index 3406bd3ee88..899b0a2cd27 100644 --- a/bsp/imxrt/imxrt1050-ArchMix/.config +++ b/bsp/imxrt/imxrt1050-ArchMix/.config @@ -15,6 +15,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set @@ -60,10 +61,12 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x30102 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_FPU=y CONFIG_ARCH_ARM_CORTEX_M7=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -102,8 +105,8 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_MNTTABLE is not set CONFIG_RT_USING_DFS_ELMFAT=y @@ -135,6 +138,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set CONFIG_RT_USING_CPUTIME=y @@ -142,13 +146,14 @@ CONFIG_RT_USING_CPUTIME_CORTEXM=y CONFIG_RT_USING_I2C=y CONFIG_RT_USING_I2C_BITOPS=y CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RTC_SYNC_USING_NTP is not set CONFIG_RT_USING_SDIO=y CONFIG_RT_SDIO_STACK_SIZE=512 CONFIG_RT_SDIO_THREAD_PRIORITY=15 @@ -157,6 +162,7 @@ CONFIG_RT_MMCSD_THREAD_PREORITY=22 CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_SDIO_DEBUG is not set CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set # CONFIG_RT_USING_SFUD is not set # CONFIG_RT_USING_W25QXX is not set @@ -219,6 +225,8 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS @@ -235,6 +243,7 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set @@ -269,6 +278,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set # # security packages @@ -289,7 +299,6 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_BEEPPLAYER is not set # # tools packages @@ -299,6 +308,8 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set # CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set # # system packages @@ -315,6 +326,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -326,6 +338,10 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -339,10 +355,8 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set - -# -# sample package -# +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -351,14 +365,10 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_IMXRT1052=y CONFIG_BOARD_RT1050_ArchMix=y -# CONFIG_BOARD_USING_HYPERFLASH is not set CONFIG_BOARD_USING_QSPIFLASH=y # diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript b/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript index a7090a02d31..3d9c8e1b4f3 100644 --- a/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript @@ -5,11 +5,23 @@ cwd = GetCurrentDir() # add the general drivers. src = Split(""" board.c +drv_flexspi.c """) CPPPATH = [cwd] CPPDEFINES = [] +if GetDepend('PKG_USING_EASYFLASH'): + src += ['ports/ef_fal_port.c'] + +if GetDepend('PKG_USING_FAL'): + src += ['ports/fal_flexspi_nor_flash_port.c'] + +if GetDepend('PKG_USING_FAL') and GetDepend('PKG_USING_EASYFLASH'): + src += ['ports/fal_flash_init.c', 'ports/ef_update.c'] + +CPPPATH += [cwd + '/ports'] + group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.c b/bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.c new file mode 100644 index 00000000000..e8bcef3d962 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-29 flybreak first implementation + */ + +#include +#include + +INIT_PREV_EXPORT(rt_hw_flexspi_init); diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.h b/bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.h new file mode 100644 index 00000000000..0131494324e --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-29 flybreak first implementation + */ + +#ifndef __DRV_FLEXSPI_H__ +#define __DRV_FLEXSPI_H__ +#include "fsl_flexspi.h" +#include "fsl_common.h" +#ifdef BOARD_USING_QSPIFLASH +#define FLASH_SIZE 0x2000 /* 64Mb/KByte */ +#define FLASH_PAGE_SIZE 256 +#define FLEXSPI_NOR_SECTOR_SIZE 0x1000 /* 4K */ +#elif defined(BOARD_USING_HYPERFLASH) +#define FLASH_SIZE 0x10000 /* 512Mb/KByte */ +#define FLASH_PAGE_SIZE 512 +#define FLEXSPI_NOR_SECTOR_SIZE 0x40000 /* 256K */ +#endif +#define FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE +extern int rt_hw_flexspi_init(void); +extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address); +extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src); +#endif diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_fal_port.c b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_fal_port.c new file mode 100644 index 00000000000..7ba3517423e --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_fal_port.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-19 armink the first version + */ + +#include +#include +#include +#include +#include +#include +#include + +/* EasyFlash partition name on FAL partition table */ +#define FAL_EF_PART_NAME "env" + +/* default ENV set for user */ +static const ef_env default_env_set[] = { + {"stay_in_bootloader","0"}, + {"check_upgrade","0"}, + {"bootdelay","1"}, +}; + +static char log_buf[RT_CONSOLEBUF_SIZE]; +static struct rt_semaphore env_cache_lock; +static const struct fal_partition *part = NULL; + +/** + * Flash port for hardware initialize. + * + * @param default_env default ENV set for user + * @param default_env_size default ENV size + * + * @return result + */ +EfErrCode ef_port_init(ef_env const **default_env, size_t *default_env_size) { + EfErrCode result = EF_NO_ERR; + + *default_env = default_env_set; + *default_env_size = sizeof(default_env_set) / sizeof(default_env_set[0]); + + rt_sem_init(&env_cache_lock, "env lock", 1, RT_IPC_FLAG_PRIO); + + part = fal_partition_find(FAL_EF_PART_NAME); + EF_ASSERT(part); + + return result; +} + +/** + * Read data from flash. + * @note This operation's units is word. + * + * @param addr flash address + * @param buf buffer to store read data + * @param size read bytes size + * + * @return result + */ +EfErrCode ef_port_read(uint32_t addr, uint32_t *buf, size_t size) { + EfErrCode result = EF_NO_ERR; + + EF_ASSERT(size % 4 == 0); + + fal_partition_read(part, addr, (uint8_t *)buf, size); + + return result; +} + +/** + * Erase data on flash. + * @note This operation is irreversible. + * @note This operation's units is different which on many chips. + * + * @param addr flash address + * @param size erase bytes size + * + * @return result + */ +EfErrCode ef_port_erase(uint32_t addr, size_t size) { + EfErrCode result = EF_NO_ERR; + + /* make sure the start address is a multiple of FLASH_ERASE_MIN_SIZE */ + EF_ASSERT(addr % EF_ERASE_MIN_SIZE == 0); + + if (fal_partition_erase(part, addr, size) < 0) + { + result = EF_ERASE_ERR; + } + + return result; +} +/** + * Write data to flash. + * @note This operation's units is word. + * @note This operation must after erase. @see flash_erase. + * + * @param addr flash address + * @param buf the write data buffer + * @param size write bytes size + * + * @return result + */ +EfErrCode ef_port_write(uint32_t addr, const uint32_t *buf, size_t size) { + EfErrCode result = EF_NO_ERR; + + EF_ASSERT(size % 4 == 0); + + if (fal_partition_write(part, addr, (uint8_t *)buf, size) < 0) + { + result = EF_WRITE_ERR; + } + + return result; +} + +/** + * lock the ENV ram cache + */ +void ef_port_env_lock(void) { + rt_sem_take(&env_cache_lock, RT_WAITING_FOREVER); +} + +/** + * unlock the ENV ram cache + */ +void ef_port_env_unlock(void) { + rt_sem_release(&env_cache_lock); +} + +/** + * This function is print flash debug info. + * + * @param file the file which has call this function + * @param line the line number which has call this function + * @param format output format + * @param ... args + * + */ +void ef_log_debug(const char *file, const long line, const char *format, ...) { + +#ifdef PRINT_DEBUG + + va_list args; + + /* args point to the first variable parameter */ + va_start(args, format); + ef_print("[Flash] (%s:%ld) ", file, line); + /* must use vprintf to print */ + rt_vsprintf(log_buf, format, args); + ef_print("%s", log_buf); + va_end(args); + +#endif + +} + +/** + * This function is print flash routine info. + * + * @param format output format + * @param ... args + */ +void ef_log_info(const char *format, ...) { + va_list args; + + /* args point to the first variable parameter */ + va_start(args, format); + ef_print("[Flash] "); + /* must use vprintf to print */ + rt_vsprintf(log_buf, format, args); + ef_print("%s", log_buf); + va_end(args); +} +/** + * This function is print flash non-package info. + * + * @param format output format + * @param ... args + */ +void ef_print(const char *format, ...) { + va_list args; + + /* args point to the first variable parameter */ + va_start(args, format); + /* must use vprintf to print */ + rt_vsprintf(log_buf, format, args); + rt_kprintf("%s", log_buf); + va_end(args); +} diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_update.c b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_update.c new file mode 100644 index 00000000000..87428e83235 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_update.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-29 flybreak first implementation + */ + +#include +#include +#include + +void reset(void) +{ + SCB->AIRCR = 0x05fa0000 | 0x04UL; + while (1) + { + } +} +MSH_CMD_EXPORT(reset, reset system.); + +#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) && defined(EF_USING_ENV) +#include +#if defined(EF_USING_ENV) + +static void update(uint8_t argc, char **argv) +{ + ef_set_env("check_upgrade", "1"); + ef_save_env(); + reset(); +} +MSH_CMD_EXPORT(update, reset and check update.); + +#endif /* defined(EF_USING_ENV) */ +#endif /* defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) */ diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_cfg.h b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_cfg.h new file mode 100644 index 00000000000..666eb2c9214 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_cfg.h @@ -0,0 +1,52 @@ +/* + * File : fal_cfg.h + * COPYRIGHT (C) 2012-2018, Shanghai Real-Thread Technology Co., Ltd + * + * Change Logs: + * Date Author Notes + * 2018-05-17 armink the first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +/* ===================== Flash device Configuration ========================= */ +extern struct fal_flash_dev nor_flash0; + +#define RT_FAL_BL_PART_LEN (256*1024) +#define RT_FAL_ENV_PART_LEN (1*1024) +#define RT_FAL_PT_PART_LEN (1*1024) +#define RT_FAL_APP_PART_LEN (1*1024*1024) +#define RT_FAL_DL_PART_LEN (1*1024*1024) + +#define RT_FAL_FLASH_BASE 0 +#define RT_FAL_BL_PART_OFFSET RT_FAL_FLASH_BASE +#define RT_FAL_ENV_PART_OFFSET (RT_FAL_BL_PART_OFFSET + RT_FAL_BL_PART_LEN) +#define RT_FAL_PT_PART_OFFSET (RT_FAL_ENV_PART_OFFSET + RT_FAL_ENV_PART_LEN) +#define RT_FAL_APP_PART_OFFSET (RT_FAL_PT_PART_OFFSET + RT_FAL_PT_PART_LEN) +#define RT_FAL_DL_PART_OFFSET (RT_FAL_APP_PART_OFFSET + RT_FAL_APP_PART_LEN) +#define RT_FAL_FS_PART_OFFSET (RT_FAL_DL_PART_OFFSET + RT_FAL_DL_PART_LEN) + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "bl", "norflash0", RT_FAL_BL_PART_OFFSET, RT_FAL_BL_PART_LEN, 0}, \ + {FAL_PART_MAGIC_WROD, "env", "norflash0", RT_FAL_ENV_PART_OFFSET, RT_FAL_ENV_PART_LEN, 0}, \ + {FAL_PART_MAGIC_WROD, "pt", "norflash0", RT_FAL_PT_PART_OFFSET, RT_FAL_PT_PART_LEN, 0}, \ + {FAL_PART_MAGIC_WROD, "app", "norflash0", RT_FAL_APP_PART_OFFSET, RT_FAL_APP_PART_LEN, 0}, \ + {FAL_PART_MAGIC_WROD, "download", "norflash0", RT_FAL_DL_PART_OFFSET, RT_FAL_DL_PART_LEN, 0}, \ + {FAL_PART_MAGIC_WROD, "fs", "norflash0", RT_FAL_FS_PART_OFFSET, 0, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flash_init.c b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flash_init.c new file mode 100644 index 00000000000..a22d75e59a6 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flash_init.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-29 flybreak first implementation + */ + +#include +#include +#include + +#define FAL_FS_PART_NAME "fs" +#define FAL_DOWNLOAD_PART_NAME "download" + +int rt_fal_flash_init(void) +{ + fal_init(); + easyflash_init(); + + fal_blk_device_create(FAL_FS_PART_NAME); + fal_char_device_create(FAL_DOWNLOAD_PART_NAME); + + return 0; +} +INIT_DEVICE_EXPORT(rt_fal_flash_init); diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flexspi_nor_flash_port.c b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flexspi_nor_flash_port.c new file mode 100644 index 00000000000..8c7a2325561 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flexspi_nor_flash_port.c @@ -0,0 +1,75 @@ +/* + * File : rt_ota_flash_sfud_port.c + * COPYRIGHT (C) 2012-2018, Shanghai Real-Thread Technology Co., Ltd + * + * Change Logs: + * Date Author Notes + * 2018-01-26 armink the first version + */ + +#include +#include +#include +#include + +static int read(long offset, uint8_t *buf, size_t size) +{ + memcpy(buf,(const void *)(FLEXSPI_AMBA_BASE+offset),size); + return size; +} + +static int write(long offset, const uint8_t *buf, size_t size) +{ + static char write_buffer[FLASH_PAGE_SIZE]; + size_t writen_size = 0; + rt_uint32_t level; + level = rt_hw_interrupt_disable(); + while(size) + { + if(size >= FLASH_PAGE_SIZE) + { + flexspi_nor_flash_page_program(FLEXSPI,offset,(const unsigned int *)buf); + size -= FLASH_PAGE_SIZE; + writen_size += FLASH_PAGE_SIZE; + } + else + { + memcpy(write_buffer,(const void *)(FLEXSPI_AMBA_BASE+offset),FLASH_PAGE_SIZE); + memcpy(write_buffer,buf,size); + flexspi_nor_flash_page_program(FLEXSPI,offset,(const unsigned int *)write_buffer); + writen_size += size; + size = 0; + } + offset += FLASH_PAGE_SIZE; + buf += FLASH_PAGE_SIZE; + } + rt_hw_interrupt_enable(level); + return writen_size; +} + +static int erase(long offset, size_t size) +{ + size_t erase_size = size; + rt_uint32_t level; + level = rt_hw_interrupt_disable(); + size = offset; + offset = (offset/FLEXSPI_NOR_SECTOR_SIZE)*FLEXSPI_NOR_SECTOR_SIZE; + size = erase_size + size - offset; + while(size) + { + flexspi_nor_flash_erase_sector(FLEXSPI,offset); + if(size >= FLEXSPI_NOR_SECTOR_SIZE) + { + size -= FLEXSPI_NOR_SECTOR_SIZE; + } + else + { + size = 0; + } + offset += FLEXSPI_NOR_SECTOR_SIZE; + } + rt_hw_interrupt_enable(level); + return erase_size; +} +struct fal_flash_dev nor_flash0 = { "norflash0", 0, FLASH_SIZE*1024, FLEXSPI_NOR_SECTOR_SIZE, {NULL, read, write, erase} }; + diff --git a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf index 5e0834cd48f..268ea3642ee 100644 --- a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf +++ b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf @@ -122,4 +122,13 @@ LR_IROM1 m_text_start m_text_size * (NonCacheable.init) * (NonCacheable) } + ITCM 0x400 0xFBFF { + ;drv_flexspi_hyper.o(+RO) + ;fsl_flexspi.o(+RO) + * (*CLOCK_DisableClock) + * (*CLOCK_ControlGate) + * (*CLOCK_EnableClock) + * (*CLOCK_SetDiv) + * (itcm) + } } diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.ewp b/bsp/imxrt/imxrt1050-ArchMix/project.ewp index 9ad86219cf4..b051ec3cbfd 100644 --- a/bsp/imxrt/imxrt1050-ArchMix/project.ewp +++ b/bsp/imxrt/imxrt1050-ArchMix/project.ewp @@ -1,2478 +1,2335 @@ - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 21 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - 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$PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif_edma.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_src.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_trng.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\iar\startup_MIMXRT1052.s + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.eww b/bsp/imxrt/imxrt1050-ArchMix/project.eww index faa93f37cdf..c2cb02eb1e8 100644 --- a/bsp/imxrt/imxrt1050-ArchMix/project.eww +++ b/bsp/imxrt/imxrt1050-ArchMix/project.eww @@ -1,10 +1,10 @@ - - - - - $WS_DIR$\project.ewp - - - - - + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx b/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx index 0a3c8c8bc0e..376fbfb9ef0 100644 --- a/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx +++ b/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx @@ -1,10 +1,6 @@ - - 1.0 -
### uVision Project, (C) Keil Software
- *.c *.s*; *.src; *.a* @@ -15,12 +11,10 @@ *.cpp 0 - 0 0 - RT-Thread IMXRT1052 0x4 @@ -101,20 +95,18 @@ 0 0 1 - 0 - 0 - 4 - - - - - - - - - + 2 + + + + + + + + + .\flexspi_nor.ini - Segger\JL2CM3.dll + BIN\CMSIS_AGDI.dll @@ -133,7 +125,7 @@ UL2CM3(-S0 -C0 -P0 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM)) - + 0 @@ -163,1690 +155,17 @@ 0 0 - - + + 0 0 0 - - - - - - - - + + + + - - - Applications - 0 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - applications\lcd_init.c - lcd_init.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - applications\main.c - main.c - 0 - 0 - - - - - Drivers - 0 - 0 - 0 - 0 - - 2 - 3 - 1 - 0 - 0 - 0 - drivers\board.c - board.c - 0 - 0 - - - 2 - 4 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\drivers\drv_uart.c - drv_uart.c - 0 - 0 - - - 2 - 5 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\drivers\drv_cache.c - drv_cache.c - 0 - 0 - - - 2 - 6 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\drivers\drv_sdram.c - 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startup_MIMXRT1052.s - 0 - 0 - - - ::CMSIS 0 @@ -1854,5 +173,4 @@ 0 1 - diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx b/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx index 5efaa5332e8..15f0a8b4ecb 100644 --- a/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx +++ b/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx @@ -1,17 +1,13 @@ - 2.1 -
### uVision Project, (C) Keil Software
- RT-Thread IMXRT1052 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 + 5060528::V5.06 update 5 (build 528)::ARMCC MIMXRT1052:M7 @@ -19,28 +15,28 @@ NXP.iMXRT_DFP.1.0.2 http://mcuxpresso.nxp.com/cmsis_pack/repo/ IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0RT1050 -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\RT1050.FLM)) 0 $$Device:MIMXRT1052$Device\Include\MIMXRT1052.h - - - - - - - - - + + + + + + + + + $$Device:MIMXRT1052$SVD\MIMXRT1052.svd 0 0 - - - - - + + + + + 0 0 @@ -62,8 +58,8 @@ 0 0 - - + + 0 0 0 @@ -72,8 +68,8 @@ 0 0 - - + + 0 0 0 @@ -83,14 +79,14 @@ 1 0 fromelf --bin !L --output rtthread-mdk.bin - + 0 0 0 0 0 - + 0 @@ -104,8 +100,8 @@ 0 0 3 - - + + 1 @@ -138,11 +134,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -175,7 +171,7 @@ 0 0 "Cortex-M7" - + 0 0 0 @@ -307,7 +303,7 @@ 0x20000 - + 1 @@ -324,7 +320,6 @@ 0 0 1 - 0 0 1 1 @@ -336,8 +331,8 @@ --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 SKIP_SYSCLK_INIT, EVK_MCIMXRM, CPU_MIMXRT1052DVL6B, RT_USING_ARM_LIBC, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 - - applications;.;drivers;..\Libraries\imxrt1050\drivers;..\..\..\include;..\..\..\libcpu\arm\cortex-m7;..\..\..\libcpu\arm\common;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\Libraries\imxrt1050\CMSIS\Include;..\Libraries\imxrt1050\devices\MIMXRT1052;..\Libraries\imxrt1050\devices\MIMXRT1052\drivers;..\Libraries\imxrt1050\devices\MIMXRT1052\utilities + + applications;.;drivers;drivers\ports;..\Libraries\imxrt1050\drivers;..\..\..\include;..\..\..\libcpu\arm\cortex-m7;..\..\..\libcpu\arm\common;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\Libraries\imxrt1050\CMSIS\Include;..\Libraries\imxrt1050\devices\MIMXRT1052;..\Libraries\imxrt1050\devices\MIMXRT1052\drivers;..\Libraries\imxrt1050\devices\MIMXRT1052\utilities @@ -352,10 +347,10 @@ 0 0 - - - - + + + + @@ -367,13 +362,13 @@ 0 0x00000000 0x10000000 - + .\flexspi_nor.scf - - + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) - - + + @@ -386,6 +381,8 @@ 1 applications\lcd_init.c + + main.c 1 @@ -401,46 +398,78 @@ 1 drivers\board.c + + + + drv_flexspi.c + 1 + drivers\drv_flexspi.c + + + drv_uart.c 1 ..\Libraries\imxrt1050\drivers\drv_uart.c + + drv_cache.c 1 ..\Libraries\imxrt1050\drivers\drv_cache.c + + + + drv_flexspi_nor.c + 1 + ..\Libraries\imxrt1050\drivers\drv_flexspi_nor.c + + + drv_sdram.c 1 ..\Libraries\imxrt1050\drivers\drv_sdram.c + + drv_pin.c 1 ..\Libraries\imxrt1050\drivers\drv_pin.c + + drv_rtc.c 1 ..\Libraries\imxrt1050\drivers\drv_rtc.c + + drv_spi_bus.c 1 ..\Libraries\imxrt1050\drivers\drv_spi_bus.c + + drv_i2c.c 1 ..\Libraries\imxrt1050\drivers\drv_i2c.c + + drv_lcd.c 1 ..\Libraries\imxrt1050\drivers\drv_lcd.c + + drv_sdio.c 1 @@ -456,66 +485,99 @@ 1 ..\..\..\src\clock.c + + components.c 1 ..\..\..\src\components.c + + + + cpu.c + 1 + ..\..\..\src\cpu.c + + + device.c 1 ..\..\..\src\device.c + + idle.c 1 ..\..\..\src\idle.c + + ipc.c 1 ..\..\..\src\ipc.c + + irq.c 1 ..\..\..\src\irq.c + + kservice.c 1 ..\..\..\src\kservice.c + + memheap.c 1 ..\..\..\src\memheap.c + + mempool.c 1 ..\..\..\src\mempool.c + + object.c 1 ..\..\..\src\object.c + + scheduler.c 1 ..\..\..\src\scheduler.c + + signal.c 1 ..\..\..\src\signal.c + + thread.c 1 ..\..\..\src\thread.c + + timer.c 1 @@ -531,21 +593,29 @@ 1 ..\..\..\libcpu\arm\cortex-m7\cpuport.c + + context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m7\context_rvds.S + + backtrace.c 1 ..\..\..\libcpu\arm\common\backtrace.c + + div0.c 1 ..\..\..\libcpu\arm\common\div0.c + + showmem.c 1 @@ -561,36 +631,50 @@ 1 ..\..\..\components\dfs\src\dfs.c + + dfs_file.c 1 ..\..\..\components\dfs\src\dfs_file.c + + dfs_fs.c 1 ..\..\..\components\dfs\src\dfs_fs.c + + dfs_posix.c 1 ..\..\..\components\dfs\src\dfs_posix.c + + devfs.c 1 ..\..\..\components\dfs\filesystems\devfs\devfs.c + + dfs_elm.c 1 ..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + ff.c 1 ..\..\..\components\dfs\filesystems\elmfat\ff.c + + ccsbcs.c 1 @@ -600,187 +684,172 @@ DeviceDrivers - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - cputime.c 1 ..\..\..\components\drivers\cputime\cputime.c + + cputime_cortexm.c 1 ..\..\..\components\drivers\cputime\cputime_cortexm.c + + i2c_core.c 1 ..\..\..\components\drivers\i2c\i2c_core.c + + i2c_dev.c 1 ..\..\..\components\drivers\i2c\i2c_dev.c + + i2c-bit-ops.c 1 ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + pin.c 1 ..\..\..\components\drivers\misc\pin.c + + rtc.c 1 ..\..\..\components\drivers\rtc\rtc.c + + block_dev.c 1 ..\..\..\components\drivers\sdio\block_dev.c + + mmcsd_core.c 1 ..\..\..\components\drivers\sdio\mmcsd_core.c + + sd.c 1 ..\..\..\components\drivers\sdio\sd.c + + sdio.c 1 ..\..\..\components\drivers\sdio\sdio.c + + mmc.c 1 ..\..\..\components\drivers\sdio\mmc.c + + serial.c 1 ..\..\..\components\drivers\serial\serial.c + + spi_core.c 1 ..\..\..\components\drivers\spi\spi_core.c + + spi_dev.c 1 ..\..\..\components\drivers\spi\spi_dev.c + + completion.c 1 ..\..\..\components\drivers\src\completion.c + + dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c + + pipe.c 1 ..\..\..\components\drivers\src\pipe.c + + ringblk_buf.c 1 ..\..\..\components\drivers\src\ringblk_buf.c + + ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c + + waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c + + workqueue.c 1 ..\..\..\components\drivers\src\workqueue.c + + + + + + + + + + + + finsh @@ -790,26 +859,36 @@ 1 ..\..\..\components\finsh\shell.c + + symbol.c 1 ..\..\..\components\finsh\symbol.c + + cmd.c 1 ..\..\..\components\finsh\cmd.c + + msh.c 1 ..\..\..\components\finsh\msh.c + + msh_cmd.c 1 ..\..\..\components\finsh\msh_cmd.c + + msh_file.c 1 @@ -825,27 +904,42 @@ 1 ..\..\..\components\libc\compilers\armlibc\libc.c + + mem_std.c 1 ..\..\..\components\libc\compilers\armlibc\mem_std.c + + stdio.c 1 ..\..\..\components\libc\compilers\armlibc\stdio.c + + stubs.c 1 ..\..\..\components\libc\compilers\armlibc\stubs.c + + time.c 1 ..\..\..\components\libc\compilers\armlibc\time.c + + + gmtime_r.c + 1 + ..\..\..\components\libc\compilers\common\gmtime_r.c + + Libraries @@ -855,301 +949,421 @@ 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc.c + + fsl_adc_etc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc_etc.c + + fsl_aipstz.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_aipstz.c + + fsl_aoi.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_aoi.c + + fsl_bee.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_bee.c + + fsl_cache.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_cache.c + + fsl_clock.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_clock.c + + fsl_cmp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_cmp.c + + fsl_common.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_common.c + + fsl_csi.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_csi.c + + fsl_dcdc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dcdc.c + + fsl_dcp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dcp.c + + fsl_dmamux.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dmamux.c + + fsl_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_edma.c + + fsl_elcdif.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_elcdif.c + + fsl_enc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enc.c + + fsl_enet.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enet.c + + fsl_ewm.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_ewm.c + + fsl_flexcan.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexcan.c + + fsl_flexio.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio.c + + fsl_flexio_i2c_master.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2c_master.c + + fsl_flexio_i2s.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s.c + + fsl_flexio_i2s_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s_edma.c + + fsl_flexio_spi.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi.c + + fsl_flexio_spi_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi_edma.c + + fsl_flexio_uart.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart.c + + fsl_flexio_uart_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart_edma.c + + fsl_flexram.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexram.c + + fsl_flexspi.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexspi.c + + fsl_gpc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpc.c + + fsl_gpio.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpio.c + + fsl_gpt.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpt.c + + fsl_kpp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_kpp.c + + fsl_lpi2c.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c.c + + fsl_lpi2c_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c_edma.c + + fsl_lpspi.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi.c + + fsl_lpspi_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi_edma.c + + fsl_lpuart.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart.c + + fsl_lpuart_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart_edma.c + + fsl_pit.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pit.c + + fsl_pmu.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pmu.c + + fsl_pwm.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pwm.c + + fsl_pxp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pxp.c + + fsl_qtmr.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_qtmr.c + + fsl_rtwdog.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_rtwdog.c + + fsl_sai.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai.c + + fsl_sai_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai_edma.c + + fsl_semc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_semc.c + + fsl_snvs_hp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_hp.c + + fsl_snvs_lp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_lp.c + + fsl_spdif.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif.c + + fsl_spdif_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif_edma.c + + fsl_src.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_src.c + + fsl_trng.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_trng.c + + fsl_tsc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c + + fsl_usdhc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c + + fsl_wdog.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c + + fsl_xbara.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c + + fsl_xbarb.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c + + system_MIMXRT1052.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c + + startup_MIMXRT1052.s 2 @@ -1157,24 +1371,19 @@ - - ::CMSIS - - - + - + - + - + - diff --git a/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h index 525013e73ec..c7a80daf619 100644 --- a/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h +++ b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h @@ -13,6 +13,7 @@ #define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK #define RT_IDEL_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_DEBUG @@ -38,6 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x30102 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_FPU @@ -73,8 +75,8 @@ #define RT_USING_DFS #define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 #define DFS_FD_MAX 16 #define RT_USING_DFS_ELMFAT @@ -95,6 +97,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_CPUTIME #define RT_USING_CPUTIME_CORTEXM #define RT_USING_I2C @@ -179,13 +182,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_IMXRT1052 #define BOARD_RT1050_ArchMix #define BOARD_USING_QSPIFLASH diff --git a/bsp/imxrt/imxrt1050-evk/.config b/bsp/imxrt/imxrt1050-evk/.config index ba6c3d19ad3..2be76d2ec32 100644 --- a/bsp/imxrt/imxrt1050-evk/.config +++ b/bsp/imxrt/imxrt1050-evk/.config @@ -15,6 +15,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set @@ -60,10 +61,12 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x30102 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_FPU=y CONFIG_ARCH_ARM_CORTEX_M7=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -136,6 +139,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set CONFIG_RT_USING_CPUTIME=y @@ -143,13 +147,14 @@ CONFIG_RT_USING_CPUTIME_CORTEXM=y CONFIG_RT_USING_I2C=y CONFIG_RT_USING_I2C_BITOPS=y CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RTC_SYNC_USING_NTP is not set CONFIG_RT_USING_SDIO=y CONFIG_RT_SDIO_STACK_SIZE=512 CONFIG_RT_SDIO_THREAD_PRIORITY=15 @@ -158,6 +163,7 @@ CONFIG_RT_MMCSD_THREAD_PREORITY=22 CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_SDIO_DEBUG is not set CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set # CONFIG_RT_USING_SFUD is not set # CONFIG_RT_USING_W25QXX is not set @@ -204,6 +210,7 @@ CONFIG_RT_USING_POSIX=y CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP210 is not set # CONFIG_RT_USING_LWIP_IPV6 is not set # CONFIG_RT_LWIP_IGMP is not set CONFIG_RT_LWIP_ICMP=y @@ -271,6 +278,8 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS @@ -287,6 +296,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set @@ -312,6 +322,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set # # IoT Cloud @@ -320,6 +331,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set # # security packages @@ -348,6 +360,9 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set # # system packages @@ -363,9 +378,8 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set -# CONFIG_PKG_USING_CMSIS_LATEST_VERSION is not set -# CONFIG_PKG_USING_CMSIS_V500 is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -376,6 +390,11 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_AP3216C is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -389,10 +408,8 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set - -# -# sample package -# +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -401,11 +418,8 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_IMXRT1052=y CONFIG_BOARD_USING_HYPERFLASH=y # CONFIG_BOARD_USING_QSPIFLASH is not set diff --git a/bsp/imxrt/imxrt1050-evk/drivers/SConscript b/bsp/imxrt/imxrt1050-evk/drivers/SConscript index a7090a02d31..3c78eb06d38 100644 --- a/bsp/imxrt/imxrt1050-evk/drivers/SConscript +++ b/bsp/imxrt/imxrt1050-evk/drivers/SConscript @@ -5,6 +5,7 @@ cwd = GetCurrentDir() # add the general drivers. src = Split(""" board.c +drv_flexspi.c """) CPPPATH = [cwd] diff --git a/bsp/imxrt/imxrt1050-evk/drivers/drv_flexspi.c b/bsp/imxrt/imxrt1050-evk/drivers/drv_flexspi.c new file mode 100644 index 00000000000..e8bcef3d962 --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/drivers/drv_flexspi.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-29 flybreak first implementation + */ + +#include +#include + +INIT_PREV_EXPORT(rt_hw_flexspi_init); diff --git a/bsp/imxrt/imxrt1050-evk/drivers/drv_flexspi.h b/bsp/imxrt/imxrt1050-evk/drivers/drv_flexspi.h new file mode 100644 index 00000000000..6d52601ca1f --- /dev/null +++ b/bsp/imxrt/imxrt1050-evk/drivers/drv_flexspi.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-29 flybreak first implementation + */ + +#ifndef __DRV_FLEXSPI_H__ +#define __DRV_FLEXSPI_H__ +#include "fsl_flexspi.h" +#include "fsl_common.h" +#ifdef BOARD_USING_QSPIFLASH +#define FLASH_SIZE 0x8000 /* 256Mb/KByte */ +#define FLASH_PAGE_SIZE 256 +#define FLEXSPI_NOR_SECTOR_SIZE 0x1000 /* 4K */ +#elif defined(BOARD_USING_HYPERFLASH) +#define FLASH_SIZE 0x10000 /* 512Mb/KByte */ +#define FLASH_PAGE_SIZE 512 +#define FLEXSPI_NOR_SECTOR_SIZE 0x40000 /* 256K */ +#endif +#define FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE +extern int rt_hw_flexspi_init(void); +extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address); +extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src); +#endif diff --git a/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf b/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf index 5e0834cd48f..268ea3642ee 100644 --- a/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf +++ b/bsp/imxrt/imxrt1050-evk/flexspi_nor.scf @@ -122,4 +122,13 @@ LR_IROM1 m_text_start m_text_size * (NonCacheable.init) * (NonCacheable) } + ITCM 0x400 0xFBFF { + ;drv_flexspi_hyper.o(+RO) + ;fsl_flexspi.o(+RO) + * (*CLOCK_DisableClock) + * (*CLOCK_ControlGate) + * (*CLOCK_EnableClock) + * (*CLOCK_SetDiv) + * (itcm) + } } diff --git a/bsp/imxrt/imxrt1050-evk/project.ewp b/bsp/imxrt/imxrt1050-evk/project.ewp index 9ad86219cf4..0067c401429 100644 --- a/bsp/imxrt/imxrt1050-evk/project.ewp +++ b/bsp/imxrt/imxrt1050-evk/project.ewp @@ -1,2478 +1,2527 @@ - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 21 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 14 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 21 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 14 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Applications - - 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$PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs\devfs.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ff.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\cputime\cputime.c + + + $PROJ_DIR$\..\..\..\components\drivers\cputime\cputime_cortexm.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\rtc\rtc.c + + + $PROJ_DIR$\..\..\..\components\drivers\sdio\block_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\sdio\mmcsd_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\sdio\sd.c + + + $PROJ_DIR$\..\..\..\components\drivers\sdio\sdio.c + + + $PROJ_DIR$\..\..\..\components\drivers\sdio\mmc.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + + + finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\symbol.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_file.c + + + + libc + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\gmtime_r.c + + + + dlib + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\libc.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\rmtx.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\stdio.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\time.c + + + + pthreads + + $PROJ_DIR$\..\..\..\components\libc\pthreads\mqueue.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_attr.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_barrier.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_cond.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_mutex.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_rwlock.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_spin.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_tls.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\sched.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\semaphore.c + + + $PROJ_DIR$\..\..\..\components\libc\time\clock_time.c + + + $PROJ_DIR$\..\..\..\components\libc\time\posix_sleep.c + + + + lwIP + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\api\api_lib.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\api\api_msg.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\api\err.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\api\netbuf.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\api\netdb.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\api\netifapi.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\api\sockets.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\api\tcpip.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\def.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\dns.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\init.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\ip.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\memp.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\netif.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\pbuf.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\raw.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\stats.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\sys.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\tcp.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\tcp_in.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\tcp_out.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\timeouts.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\udp.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\netif\ethernet.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c + + + $PROJ_DIR$\..\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c + + + + Libraries + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc_etc.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_aipstz.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_aoi.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_bee.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_cache.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_clock.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_cmp.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_common.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_csi.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dcdc.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dcp.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dmamux.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_edma.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_elcdif.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enc.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enet.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_ewm.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexcan.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2c_master.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s_edma.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi_edma.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart_edma.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexram.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexspi.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpc.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpio.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpt.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_kpp.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c_edma.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi_edma.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart_edma.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pit.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pmu.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pwm.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pxp.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_qtmr.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_rtwdog.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai_edma.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_semc.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_hp.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_lp.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif_edma.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_src.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_trng.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c + + + $PROJ_DIR$\..\Libraries\imxrt1050\devices\MIMXRT1052\iar\startup_MIMXRT1052.s + + + diff --git a/bsp/imxrt/imxrt1050-evk/project.eww b/bsp/imxrt/imxrt1050-evk/project.eww index faa93f37cdf..c2cb02eb1e8 100644 --- a/bsp/imxrt/imxrt1050-evk/project.eww +++ b/bsp/imxrt/imxrt1050-evk/project.eww @@ -1,10 +1,10 @@ - - - - - $WS_DIR$\project.ewp - - - - - + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/imxrt/imxrt1050-evk/project.uvoptx b/bsp/imxrt/imxrt1050-evk/project.uvoptx index b6a82eb3b4d..38055496d38 100644 --- a/bsp/imxrt/imxrt1050-evk/project.uvoptx +++ b/bsp/imxrt/imxrt1050-evk/project.uvoptx @@ -173,2358 +173,6 @@ - - Applications - 0 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - applications\lcd_init.c - lcd_init.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - applications\main.c - main.c - 0 - 0 - - - - - Drivers - 0 - 0 - 0 - 0 - - 2 - 3 - 1 - 0 - 0 - 0 - drivers\board.c - board.c - 0 - 0 - - - 2 - 4 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\drivers\drv_uart.c - drv_uart.c - 0 - 0 - - - 2 - 5 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\drivers\drv_cache.c - drv_cache.c - 0 - 0 - - - 2 - 6 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\drivers\drv_sdram.c - drv_sdram.c - 0 - 0 - - - 2 - 7 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\drivers\drv_pin.c - drv_pin.c - 0 - 0 - - - 2 - 8 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\drivers\drv_rtc.c - drv_rtc.c - 0 - 0 - - - 2 - 9 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\drivers\drv_spi_bus.c - drv_spi_bus.c - 0 - 0 - - - 2 - 10 - 1 - 0 - 0 - 0 - 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..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif_edma.c - fsl_spdif_edma.c - 0 - 0 - - - 12 - 180 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_src.c - fsl_src.c - 0 - 0 - - - 12 - 181 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_trng.c - fsl_trng.c - 0 - 0 - - - 12 - 182 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c - fsl_tsc.c - 0 - 0 - - - 12 - 183 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c - fsl_usdhc.c - 0 - 0 - - - 12 - 184 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c - fsl_wdog.c - 0 - 0 - - - 12 - 185 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c - fsl_xbara.c - 0 - 0 - - - 12 - 186 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c - fsl_xbarb.c - 0 - 0 - - - 12 - 187 - 1 - 0 - 0 - 0 - ..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c - system_MIMXRT1052.c - 0 - 0 - - - 12 - 188 - 2 - 0 - 0 - 0 - ..\Libraries\imxrt1050\devices\MIMXRT1052\arm\startup_MIMXRT1052.s - startup_MIMXRT1052.s - 0 - 0 - - - ::CMSIS 0 diff --git a/bsp/imxrt/imxrt1050-evk/project.uvprojx b/bsp/imxrt/imxrt1050-evk/project.uvprojx index 5aa2a861c95..c32997d231b 100644 --- a/bsp/imxrt/imxrt1050-evk/project.uvprojx +++ b/bsp/imxrt/imxrt1050-evk/project.uvprojx @@ -1,16 +1,13 @@ - 2.1 -
### uVision Project, (C) Keil Software
- RT-Thread IMXRT1052 0x4 ARM-ADS - 5060422::V5.06 update 4 (build 422)::ARMCC + 5060528::V5.06 update 5 (build 528)::ARMCC MIMXRT1052:M7 @@ -18,28 +15,28 @@ NXP.iMXRT_DFP.1.0.2 http://mcuxpresso.nxp.com/cmsis_pack/repo/ IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0RT1050 -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\RT1050.FLM)) 0 $$Device:MIMXRT1052$Device\Include\MIMXRT1052.h - - - - - - - - - + + + + + + + + + $$Device:MIMXRT1052$SVD\MIMXRT1052.svd 0 0 - - - - - + + + + + 0 0 @@ -61,8 +58,8 @@ 0 0 - - + + 0 0 0 @@ -71,8 +68,8 @@ 0 0 - - + + 0 0 0 @@ -82,14 +79,14 @@ 1 0 fromelf --bin !L --output rtthread-mdk.bin - + 0 0 0 0 0 - + 0 @@ -103,8 +100,8 @@ 0 0 3 - - + + 1 @@ -137,11 +134,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -174,7 +171,7 @@ 0 0 "Cortex-M7" - + 0 0 0 @@ -306,7 +303,7 @@ 0x20000 - + 1 @@ -334,8 +331,8 @@ --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 SKIP_SYSCLK_INIT, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1, EVK_MCIMXRM, FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE, CPU_MIMXRT1052DVL6B, RT_USING_ARM_LIBC - - applications;.;drivers;..\Libraries\imxrt1050\drivers;xip;..\..\..\include;..\..\..\libcpu\arm\cortex-m7;..\..\..\libcpu\arm\common;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\pthreads;..\..\..\components\libc\time;..\..\..\components\net\lwip-2.0.2\src;..\..\..\components\net\lwip-2.0.2\src\include;..\..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\..\components\net\lwip-2.0.2\src\arch\include;..\..\..\components\net\lwip-2.0.2\src\include\netif;..\..\..\components\net\lwip-2.0.2\src\include\posix;..\Libraries\imxrt1050\CMSIS\Include;..\Libraries\imxrt1050\devices\MIMXRT1052;..\Libraries\imxrt1050\devices\MIMXRT1052\drivers;..\Libraries\imxrt1050\devices\MIMXRT1052\utilities + + applications;.;drivers;..\Libraries\imxrt1050\drivers;xip;..\..\..\include;..\..\..\libcpu\arm\cortex-m7;..\..\..\libcpu\arm\common;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\..\..\components\libc\pthreads;..\..\..\components\libc\time;..\..\..\components\net\lwip-2.0.2\src;..\..\..\components\net\lwip-2.0.2\src\include;..\..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\..\components\net\lwip-2.0.2\src\arch\include;..\..\..\components\net\lwip-2.0.2\src\include\netif;..\..\..\components\net\lwip-2.0.2\src\include\posix;..\Libraries\imxrt1050\CMSIS\Include;..\Libraries\imxrt1050\devices\MIMXRT1052;..\Libraries\imxrt1050\devices\MIMXRT1052\drivers;..\Libraries\imxrt1050\devices\MIMXRT1052\utilities @@ -350,10 +347,10 @@ 0 0 - - - - + + + + @@ -365,13 +362,13 @@ 0 0x00000000 0x10000000 - + .\flexspi_nor.scf - - + + --keep=*(.boot_hdr.ivt)--keep=*(.boot_hdr.boot_data)--keep=*(.boot_hdr.dcd_data)--keep=*(.boot_hdr.conf) --keep *.o(.rti_fn.*) --keep *.o(FSymTab) - - + + @@ -384,6 +381,8 @@ 1 applications\lcd_init.c + + main.c 1 @@ -399,56 +398,92 @@ 1 drivers\board.c + + + + drv_flexspi.c + 1 + drivers\drv_flexspi.c + + + drv_uart.c 1 ..\Libraries\imxrt1050\drivers\drv_uart.c + + drv_cache.c 1 ..\Libraries\imxrt1050\drivers\drv_cache.c + + + + drv_flexspi_hyper.c + 1 + ..\Libraries\imxrt1050\drivers\drv_flexspi_hyper.c + + + drv_sdram.c 1 ..\Libraries\imxrt1050\drivers\drv_sdram.c + + drv_pin.c 1 ..\Libraries\imxrt1050\drivers\drv_pin.c + + drv_rtc.c 1 ..\Libraries\imxrt1050\drivers\drv_rtc.c + + drv_spi_bus.c 1 ..\Libraries\imxrt1050\drivers\drv_spi_bus.c + + drv_i2c.c 1 ..\Libraries\imxrt1050\drivers\drv_i2c.c + + drv_lcd.c 1 ..\Libraries\imxrt1050\drivers\drv_lcd.c + + drv_sdio.c 1 ..\Libraries\imxrt1050\drivers\drv_sdio.c + + drv_eth.c 1 ..\Libraries\imxrt1050\drivers\drv_eth.c + + fsl_phy.c 1 @@ -464,6 +499,8 @@ 1 xip\fsl_flexspi_nor_boot.c + + fsl_flexspi_nor_flash.c 1 @@ -479,66 +516,99 @@ 1 ..\..\..\src\clock.c + + components.c 1 ..\..\..\src\components.c + + + + cpu.c + 1 + ..\..\..\src\cpu.c + + + device.c 1 ..\..\..\src\device.c + + idle.c 1 ..\..\..\src\idle.c + + ipc.c 1 ..\..\..\src\ipc.c + + irq.c 1 ..\..\..\src\irq.c + + kservice.c 1 ..\..\..\src\kservice.c + + memheap.c 1 ..\..\..\src\memheap.c + + mempool.c 1 ..\..\..\src\mempool.c + + object.c 1 ..\..\..\src\object.c + + scheduler.c 1 ..\..\..\src\scheduler.c + + signal.c 1 ..\..\..\src\signal.c + + thread.c 1 ..\..\..\src\thread.c + + timer.c 1 @@ -554,21 +624,29 @@ 1 ..\..\..\libcpu\arm\cortex-m7\cpuport.c + + context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m7\context_rvds.S + + backtrace.c 1 ..\..\..\libcpu\arm\common\backtrace.c + + div0.c 1 ..\..\..\libcpu\arm\common\div0.c + + showmem.c 1 @@ -584,46 +662,64 @@ 1 ..\..\..\components\dfs\src\dfs.c + + dfs_file.c 1 ..\..\..\components\dfs\src\dfs_file.c + + dfs_fs.c 1 ..\..\..\components\dfs\src\dfs_fs.c + + dfs_posix.c 1 ..\..\..\components\dfs\src\dfs_posix.c + + poll.c 1 ..\..\..\components\dfs\src\poll.c + + select.c 1 ..\..\..\components\dfs\src\select.c + + devfs.c 1 ..\..\..\components\dfs\filesystems\devfs\devfs.c + + dfs_elm.c 1 ..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + ff.c 1 ..\..\..\components\dfs\filesystems\elmfat\ff.c + + ccsbcs.c 1 @@ -633,186 +729,172 @@ DeviceDrivers - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - cputime.c 1 ..\..\..\components\drivers\cputime\cputime.c + + cputime_cortexm.c 1 ..\..\..\components\drivers\cputime\cputime_cortexm.c + + i2c_core.c 1 ..\..\..\components\drivers\i2c\i2c_core.c + + i2c_dev.c 1 ..\..\..\components\drivers\i2c\i2c_dev.c + + i2c-bit-ops.c 1 ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + pin.c 1 ..\..\..\components\drivers\misc\pin.c + + rtc.c 1 ..\..\..\components\drivers\rtc\rtc.c + + block_dev.c 1 ..\..\..\components\drivers\sdio\block_dev.c + + mmcsd_core.c 1 ..\..\..\components\drivers\sdio\mmcsd_core.c + + sd.c 1 ..\..\..\components\drivers\sdio\sd.c + + sdio.c 1 ..\..\..\components\drivers\sdio\sdio.c + + mmc.c 1 ..\..\..\components\drivers\sdio\mmc.c + + serial.c 1 ..\..\..\components\drivers\serial\serial.c + + spi_core.c 1 ..\..\..\components\drivers\spi\spi_core.c + + spi_dev.c 1 ..\..\..\components\drivers\spi\spi_dev.c + + completion.c 1 ..\..\..\components\drivers\src\completion.c + + dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c + + pipe.c 1 ..\..\..\components\drivers\src\pipe.c + + ringblk_buf.c 1 ..\..\..\components\drivers\src\ringblk_buf.c + + ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c + + waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c + + workqueue.c 1 ..\..\..\components\drivers\src\workqueue.c + + + + + + + + + + + + finsh @@ -822,26 +904,36 @@ 1 ..\..\..\components\finsh\shell.c + + symbol.c 1 ..\..\..\components\finsh\symbol.c + + cmd.c 1 ..\..\..\components\finsh\cmd.c + + msh.c 1 ..\..\..\components\finsh\msh.c + + msh_cmd.c 1 ..\..\..\components\finsh\msh_cmd.c + + msh_file.c 1 @@ -857,27 +949,42 @@ 1 ..\..\..\components\libc\compilers\armlibc\libc.c + + mem_std.c 1 ..\..\..\components\libc\compilers\armlibc\mem_std.c + + stdio.c 1 ..\..\..\components\libc\compilers\armlibc\stdio.c + + stubs.c 1 ..\..\..\components\libc\compilers\armlibc\stubs.c + + time.c 1 ..\..\..\components\libc\compilers\armlibc\time.c + + + gmtime_r.c + 1 + ..\..\..\components\libc\compilers\common\gmtime_r.c + + pthreads @@ -887,61 +994,85 @@ 1 ..\..\..\components\libc\pthreads\mqueue.c + + pthread.c 1 ..\..\..\components\libc\pthreads\pthread.c + + pthread_attr.c 1 ..\..\..\components\libc\pthreads\pthread_attr.c + + pthread_barrier.c 1 ..\..\..\components\libc\pthreads\pthread_barrier.c + + pthread_cond.c 1 ..\..\..\components\libc\pthreads\pthread_cond.c + + pthread_mutex.c 1 ..\..\..\components\libc\pthreads\pthread_mutex.c + + pthread_rwlock.c 1 ..\..\..\components\libc\pthreads\pthread_rwlock.c + + pthread_spin.c 1 ..\..\..\components\libc\pthreads\pthread_spin.c + + pthread_tls.c 1 ..\..\..\components\libc\pthreads\pthread_tls.c + + sched.c 1 ..\..\..\components\libc\pthreads\sched.c + + semaphore.c 1 ..\..\..\components\libc\pthreads\semaphore.c + + clock_time.c 1 ..\..\..\components\libc\time\clock_time.c + + posix_sleep.c 1 @@ -957,176 +1088,246 @@ 1 ..\..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c + + api_lib.c 1 ..\..\..\components\net\lwip-2.0.2\src\api\api_lib.c + + api_msg.c 1 ..\..\..\components\net\lwip-2.0.2\src\api\api_msg.c + + err.c 1 ..\..\..\components\net\lwip-2.0.2\src\api\err.c + + netbuf.c 1 ..\..\..\components\net\lwip-2.0.2\src\api\netbuf.c + + netdb.c 1 ..\..\..\components\net\lwip-2.0.2\src\api\netdb.c + + netifapi.c 1 ..\..\..\components\net\lwip-2.0.2\src\api\netifapi.c + + sockets.c 1 ..\..\..\components\net\lwip-2.0.2\src\api\sockets.c + + tcpip.c 1 ..\..\..\components\net\lwip-2.0.2\src\api\tcpip.c + + def.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\def.c + + dns.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\dns.c + + inet_chksum.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c + + init.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\init.c + + ip.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\ip.c + + memp.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\memp.c + + netif.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\netif.c + + pbuf.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\pbuf.c + + raw.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\raw.c + + stats.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\stats.c + + sys.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\sys.c + + tcp.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\tcp.c + + tcp_in.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\tcp_in.c + + tcp_out.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\tcp_out.c + + timeouts.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\timeouts.c + + udp.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\udp.c + + ethernet.c 1 ..\..\..\components\net\lwip-2.0.2\src\netif\ethernet.c + + ethernetif.c 1 ..\..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c + + lowpan6.c 1 ..\..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c + + autoip.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c + + dhcp.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c + + etharp.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c + + icmp.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c + + igmp.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c + + ip4.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c + + ip4_addr.c 1 ..\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c + + ip4_frag.c 1 @@ -1142,301 +1343,421 @@ 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc.c + + fsl_adc_etc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc_etc.c + + fsl_aipstz.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_aipstz.c + + fsl_aoi.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_aoi.c + + fsl_bee.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_bee.c + + fsl_cache.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_cache.c + + fsl_clock.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_clock.c + + fsl_cmp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_cmp.c + + fsl_common.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_common.c + + fsl_csi.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_csi.c + + fsl_dcdc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dcdc.c + + fsl_dcp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dcp.c + + fsl_dmamux.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dmamux.c + + fsl_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_edma.c + + fsl_elcdif.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_elcdif.c + + fsl_enc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enc.c + + fsl_enet.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enet.c + + fsl_ewm.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_ewm.c + + fsl_flexcan.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexcan.c + + fsl_flexio.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio.c + + fsl_flexio_i2c_master.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2c_master.c + + fsl_flexio_i2s.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s.c + + fsl_flexio_i2s_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s_edma.c + + fsl_flexio_spi.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi.c + + fsl_flexio_spi_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi_edma.c + + fsl_flexio_uart.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart.c + + fsl_flexio_uart_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart_edma.c + + fsl_flexram.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexram.c + + fsl_flexspi.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexspi.c + + fsl_gpc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpc.c + + fsl_gpio.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpio.c + + fsl_gpt.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpt.c + + fsl_kpp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_kpp.c + + fsl_lpi2c.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c.c + + fsl_lpi2c_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c_edma.c + + fsl_lpspi.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi.c + + fsl_lpspi_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi_edma.c + + fsl_lpuart.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart.c + + fsl_lpuart_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart_edma.c + + fsl_pit.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pit.c + + fsl_pmu.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pmu.c + + fsl_pwm.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pwm.c + + fsl_pxp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pxp.c + + fsl_qtmr.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_qtmr.c + + fsl_rtwdog.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_rtwdog.c + + fsl_sai.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai.c + + fsl_sai_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai_edma.c + + fsl_semc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_semc.c + + fsl_snvs_hp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_hp.c + + fsl_snvs_lp.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_lp.c + + fsl_spdif.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif.c + + fsl_spdif_edma.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif_edma.c + + fsl_src.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_src.c + + fsl_trng.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_trng.c + + fsl_tsc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c + + fsl_usdhc.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c + + fsl_wdog.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c + + fsl_xbara.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c + + fsl_xbarb.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c + + system_MIMXRT1052.c 1 ..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c + + startup_MIMXRT1052.s 2 @@ -1444,24 +1765,19 @@ - - ::CMSIS - - - + - + - + - + - diff --git a/bsp/imxrt/imxrt1050-evk/rtconfig.h b/bsp/imxrt/imxrt1050-evk/rtconfig.h index b5e68cdab94..5256a508183 100644 --- a/bsp/imxrt/imxrt1050-evk/rtconfig.h +++ b/bsp/imxrt/imxrt1050-evk/rtconfig.h @@ -13,6 +13,7 @@ #define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK #define RT_IDEL_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_DEBUG @@ -38,6 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x30102 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_FPU @@ -95,6 +97,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_CPUTIME #define RT_USING_CPUTIME_CORTEXM #define RT_USING_I2C @@ -216,13 +219,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_IMXRT1052 #define BOARD_USING_HYPERFLASH #define BOARD_RT1050_EVK diff --git a/bsp/imxrt1052-evk/.config b/bsp/imxrt1052-evk/.config index ece95385957..88643d85b48 100644 --- a/bsp/imxrt1052-evk/.config +++ b/bsp/imxrt1052-evk/.config @@ -124,6 +124,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/imxrt1052-evk/rtconfig.h b/bsp/imxrt1052-evk/rtconfig.h index ef00ef09ff3..d4298a93ca7 100644 --- a/bsp/imxrt1052-evk/rtconfig.h +++ b/bsp/imxrt1052-evk/rtconfig.h @@ -91,6 +91,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN diff --git a/bsp/lpc176x/SConstruct b/bsp/lpc176x/SConstruct index 681e6469c48..4afcf966024 100644 --- a/bsp/lpc176x/SConstruct +++ b/bsp/lpc176x/SConstruct @@ -14,7 +14,6 @@ TARGET = 'rtthread-lpc17xx.' + rtconfig.TARGET_EXT env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) diff --git a/bsp/lpc408x/.config b/bsp/lpc408x/.config index e10d9ce3f91..eed04f9c323 100644 --- a/bsp/lpc408x/.config +++ b/bsp/lpc408x/.config @@ -121,6 +121,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_USING_CAN=y # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/lpc408x/rtconfig.h b/bsp/lpc408x/rtconfig.h index 650dade6f08..0d5469786f0 100644 --- a/bsp/lpc408x/rtconfig.h +++ b/bsp/lpc408x/rtconfig.h @@ -112,6 +112,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_CAN /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/lpc43xx/M0/rtconfig.h b/bsp/lpc43xx/M0/rtconfig.h index c48cf2525c8..90531287dd9 100644 --- a/bsp/lpc43xx/M0/rtconfig.h +++ b/bsp/lpc43xx/M0/rtconfig.h @@ -75,6 +75,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // #define RT_UART_RX_BUFFER_SIZE 256 // diff --git a/bsp/lpc43xx/M4/rtconfig.h b/bsp/lpc43xx/M4/rtconfig.h index 9bb1b656f20..0b30998cc0f 100644 --- a/bsp/lpc43xx/M4/rtconfig.h +++ b/bsp/lpc43xx/M4/rtconfig.h @@ -74,6 +74,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // #define RT_UART_RX_BUFFER_SIZE 256 // diff --git a/bsp/lpc5410x/rtconfig.h b/bsp/lpc5410x/rtconfig.h index bd231931e3e..c054bfabbaa 100644 --- a/bsp/lpc5410x/rtconfig.h +++ b/bsp/lpc5410x/rtconfig.h @@ -68,6 +68,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA //
//
diff --git a/bsp/lpc54114-lite/.config b/bsp/lpc54114-lite/.config new file mode 100644 index 00000000000..04a1aea3323 --- /dev/null +++ b/bsp/lpc54114-lite/.config @@ -0,0 +1,390 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x30102 +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +CONFIG_RT_USING_DFS_ROMFS=y +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +CONFIG_RT_USING_I2C_BITOPS=y +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +CONFIG_RT_USING_SPI_MSD=y +CONFIG_RT_USING_SFUD=y +# CONFIG_RT_SFUD_USING_SFDP is not set +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_W25QXX is not set +# CONFIG_RT_USING_GD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# ARM CMSIS +# +# CONFIG_RT_USING_CMSIS_OS is not set +# CONFIG_RT_USING_RTT_CMSIS is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +CONFIG_SOC_LPC54114=y + +# +# LPC54110 Bsp Config +# + +# +# Select uart drivers +# +CONFIG_BSP_USING_UART0=y + +# +# Select spi bus drivers +# +CONFIG_BSP_USING_SPI2=y + +# +# Select i2c bus drivers +# +CONFIG_BSP_USING_I2C4=y +CONFIG_BSP_USING_ROMFS=y +CONFIG_BSP_USING_SDCARD=y +CONFIG_BSP_USING_SPIFLASH=y diff --git a/bsp/lpc54114-lite/Kconfig b/bsp/lpc54114-lite/Kconfig new file mode 100644 index 00000000000..052b48cd370 --- /dev/null +++ b/bsp/lpc54114-lite/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_LPC54114 + bool + select ARCH_ARM_CORTEX_M4 + default y + + +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/SConscript b/bsp/lpc54114-lite/Libraries/CMSIS/Include/SConscript new file mode 100644 index 00000000000..9524170709e --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/SConscript @@ -0,0 +1,12 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +CPPPATH = [cwd] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/arm_common_tables.h new file mode 100644 index 00000000000..dfea7460e9a --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/arm_const_structs.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/arm_const_structs.h new file mode 100644 index 00000000000..80a3e8bbe72 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/arm_math.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/arm_math.h new file mode 100644 index 00000000000..ea9dd26aa81 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armcc.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 00000000000..093d35b9e5c --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,870 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armclang.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 00000000000..5c4c20e8777 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1877 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_compiler.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 00000000000..94212eb87a9 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_gcc.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 00000000000..5d0f07e8acc --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 00000000000..edcaee3d4ab --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_version.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_version.h new file mode 100644 index 00000000000..660f612aa31 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mbl.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 00000000000..47a39893ace --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1896 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mml.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mml.h new file mode 100644 index 00000000000..0951a1f7812 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2960 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm0.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 00000000000..a3f1b9ac330 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 00000000000..f8f30c3496a --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1023 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm23.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm23.h new file mode 100644 index 00000000000..7d1d478af2a --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm23.h @@ -0,0 +1,1899 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm3.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 00000000000..a2c0d080572 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1933 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm33.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm33.h new file mode 100644 index 00000000000..b1efbcae7c7 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm33.h @@ -0,0 +1,2963 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm4.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 00000000000..a11a3817a23 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,2118 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm7.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 00000000000..1fe53bf012f --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2660 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_sc000.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 00000000000..9aab5e5b3ea --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,1016 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_sc300.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 00000000000..a569ef2acec --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1903 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv7.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv7.h new file mode 100644 index 00000000000..aa180c9e596 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv8.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv8.h new file mode 100644 index 00000000000..0ccfc74fe5b --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Pos) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/Include/tz_context.h b/bsp/lpc54114-lite/Libraries/CMSIS/Include/tz_context.h new file mode 100644 index 00000000000..0d09749f3a5 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/lpc54114-lite/Libraries/CMSIS/SConscript b/bsp/lpc54114-lite/Libraries/CMSIS/SConscript new file mode 100644 index 00000000000..4c815c49b83 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/CMSIS/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/lpc54114-lite/Libraries/SConscript b/bsp/lpc54114-lite/Libraries/SConscript new file mode 100644 index 00000000000..4c815c49b83 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus.h new file mode 100644 index 00000000000..6dff1ea844f --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus.h @@ -0,0 +1,7103 @@ +/* +** ################################################################### +** Processors: LPC54114J256BD64_cm0plus +** LPC54114J256UK49_cm0plus +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b180227 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC54114_cm0plus +** +** The Clear BSD License +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-04-29) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file LPC54114_cm0plus.h + * @version 1.0 + * @date 2016-04-29 + * @brief CMSIS Peripheral Access Layer for LPC54114_cm0plus + * + * CMSIS Peripheral Access Layer for LPC54114_cm0plus + */ + +#ifndef _LPC54114_CM0PLUS_H_ +#define _LPC54114_CM0PLUS_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ + DMA0_IRQn = 1, /**< DMA controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ + ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ + ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ + ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ + DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */ + HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + IOH_IRQn = 30, /**< IOH */ + MAILBOX_IRQn = 31 /**< Mailbox interrupt (present on selected devices) */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M0 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration + * @{ + */ + +#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ +#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ + +#include "core_cm0plus.h" /* Core Peripheral Access Layer */ +#include "system_LPC54114_cm0plus.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 */ + kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 1 */ + kDmaRequestNoDMARequest18 = 18U, /**< No DMA request 18 */ + kDmaRequestNoDMARequest19 = 19U, /**< No DMA request 19 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ + __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ + __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ + __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ + uint8_t RESERVED_0[8]; + __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ + __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ + __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ + __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ + __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ + __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ + __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ + __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ + __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ + __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ +/*! @{ */ +#define ADC_CTRL_CLKDIV_MASK (0xFFU) +#define ADC_CTRL_CLKDIV_SHIFT (0U) +#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) +#define ADC_CTRL_ASYNMODE_MASK (0x100U) +#define ADC_CTRL_ASYNMODE_SHIFT (8U) +#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) +#define ADC_CTRL_RESOL_MASK (0x600U) +#define ADC_CTRL_RESOL_SHIFT (9U) +#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) +#define ADC_CTRL_BYPASSCAL_MASK (0x800U) +#define ADC_CTRL_BYPASSCAL_SHIFT (11U) +#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) +#define ADC_CTRL_TSAMP_MASK (0x7000U) +#define ADC_CTRL_TSAMP_SHIFT (12U) +#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) +/*! @} */ + +/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ +/*! @{ */ +#define ADC_INSEL_SEL_MASK (0x3U) +#define ADC_INSEL_SEL_SHIFT (0U) +#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) +/*! @} */ + +/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ +/*! @{ */ +#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) +#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) +#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) +#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) +#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) +#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) +#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) +#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) +#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) +#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) +#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) +#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) +#define ADC_SEQ_CTRL_START_MASK (0x4000000U) +#define ADC_SEQ_CTRL_START_SHIFT (26U) +#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) +#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) +#define ADC_SEQ_CTRL_BURST_SHIFT (27U) +#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) +#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) +#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) +#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) +#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) +#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) +#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) +#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) +#define ADC_SEQ_CTRL_MODE_SHIFT (30U) +#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) +#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) +#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) +#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) +/*! @} */ + +/* The count of ADC_SEQ_CTRL */ +#define ADC_SEQ_CTRL_COUNT (2U) + +/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ +/*! @{ */ +#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) +#define ADC_SEQ_GDAT_RESULT_SHIFT (4U) +#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) +#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) +#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) +#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) +#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) +#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) +#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) +#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) +#define ADC_SEQ_GDAT_CHN_SHIFT (26U) +#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) +#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) +#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) +#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) +#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) +#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) +#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) +/*! @} */ + +/* The count of ADC_SEQ_GDAT */ +#define ADC_SEQ_GDAT_COUNT (2U) + +/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ +/*! @{ */ +#define ADC_DAT_RESULT_MASK (0xFFF0U) +#define ADC_DAT_RESULT_SHIFT (4U) +#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) +#define ADC_DAT_THCMPRANGE_MASK (0x30000U) +#define ADC_DAT_THCMPRANGE_SHIFT (16U) +#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) +#define ADC_DAT_THCMPCROSS_MASK (0xC0000U) +#define ADC_DAT_THCMPCROSS_SHIFT (18U) +#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) +#define ADC_DAT_CHANNEL_MASK (0x3C000000U) +#define ADC_DAT_CHANNEL_SHIFT (26U) +#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) +#define ADC_DAT_OVERRUN_MASK (0x40000000U) +#define ADC_DAT_OVERRUN_SHIFT (30U) +#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) +#define ADC_DAT_DATAVALID_MASK (0x80000000U) +#define ADC_DAT_DATAVALID_SHIFT (31U) +#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) +/*! @} */ + +/* The count of ADC_DAT */ +#define ADC_DAT_COUNT (12U) + +/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +/*! @{ */ +#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) +#define ADC_THR0_LOW_THRLOW_SHIFT (4U) +#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) +/*! @} */ + +/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +/*! @{ */ +#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) +#define ADC_THR1_LOW_THRLOW_SHIFT (4U) +#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) +/*! @} */ + +/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +/*! @{ */ +#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) +#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) +#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) +/*! @} */ + +/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +/*! @{ */ +#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) +#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) +#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) +/*! @} */ + +/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ +/*! @{ */ +#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) +#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) +#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) +#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) +#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) +#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) +#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) +#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) +#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) +#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) +#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) +#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) +#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) +#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) +#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) +#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) +#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) +#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) +#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) +#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) +#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) +#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) +#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) +#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) +#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) +/*! @} */ + +/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ +/*! @{ */ +#define ADC_INTEN_SEQA_INTEN_MASK (0x1U) +#define ADC_INTEN_SEQA_INTEN_SHIFT (0U) +#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) +#define ADC_INTEN_SEQB_INTEN_MASK (0x2U) +#define ADC_INTEN_SEQB_INTEN_SHIFT (1U) +#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) +#define ADC_INTEN_OVR_INTEN_MASK (0x4U) +#define ADC_INTEN_OVR_INTEN_SHIFT (2U) +#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) +#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) +#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) +#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) +#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) +#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) +#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) +#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) +#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) +#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) +#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) +#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) +#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) +#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) +#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) +#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) +#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) +#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) +#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) +#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) +#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) +#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) +#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) +#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) +#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) +#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) +#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) +#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) +#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) +#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) +#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) +#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) +#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) +#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) +#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) +#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) +#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) +/*! @} */ + +/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ +/*! @{ */ +#define ADC_FLAGS_THCMP0_MASK (0x1U) +#define ADC_FLAGS_THCMP0_SHIFT (0U) +#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) +#define ADC_FLAGS_THCMP1_MASK (0x2U) +#define ADC_FLAGS_THCMP1_SHIFT (1U) +#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) +#define ADC_FLAGS_THCMP2_MASK (0x4U) +#define ADC_FLAGS_THCMP2_SHIFT (2U) +#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) +#define ADC_FLAGS_THCMP3_MASK (0x8U) +#define ADC_FLAGS_THCMP3_SHIFT (3U) +#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) +#define ADC_FLAGS_THCMP4_MASK (0x10U) +#define ADC_FLAGS_THCMP4_SHIFT (4U) +#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) +#define ADC_FLAGS_THCMP5_MASK (0x20U) +#define ADC_FLAGS_THCMP5_SHIFT (5U) +#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) +#define ADC_FLAGS_THCMP6_MASK (0x40U) +#define ADC_FLAGS_THCMP6_SHIFT (6U) +#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) +#define ADC_FLAGS_THCMP7_MASK (0x80U) +#define ADC_FLAGS_THCMP7_SHIFT (7U) +#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) +#define ADC_FLAGS_THCMP8_MASK (0x100U) +#define ADC_FLAGS_THCMP8_SHIFT (8U) +#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) +#define ADC_FLAGS_THCMP9_MASK (0x200U) +#define ADC_FLAGS_THCMP9_SHIFT (9U) +#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) +#define ADC_FLAGS_THCMP10_MASK (0x400U) +#define ADC_FLAGS_THCMP10_SHIFT (10U) +#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) +#define ADC_FLAGS_THCMP11_MASK (0x800U) +#define ADC_FLAGS_THCMP11_SHIFT (11U) +#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) +#define ADC_FLAGS_OVERRUN0_MASK (0x1000U) +#define ADC_FLAGS_OVERRUN0_SHIFT (12U) +#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) +#define ADC_FLAGS_OVERRUN1_MASK (0x2000U) +#define ADC_FLAGS_OVERRUN1_SHIFT (13U) +#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) +#define ADC_FLAGS_OVERRUN2_MASK (0x4000U) +#define ADC_FLAGS_OVERRUN2_SHIFT (14U) +#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) +#define ADC_FLAGS_OVERRUN3_MASK (0x8000U) +#define ADC_FLAGS_OVERRUN3_SHIFT (15U) +#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) +#define ADC_FLAGS_OVERRUN4_MASK (0x10000U) +#define ADC_FLAGS_OVERRUN4_SHIFT (16U) +#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) +#define ADC_FLAGS_OVERRUN5_MASK (0x20000U) +#define ADC_FLAGS_OVERRUN5_SHIFT (17U) +#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) +#define ADC_FLAGS_OVERRUN6_MASK (0x40000U) +#define ADC_FLAGS_OVERRUN6_SHIFT (18U) +#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) +#define ADC_FLAGS_OVERRUN7_MASK (0x80000U) +#define ADC_FLAGS_OVERRUN7_SHIFT (19U) +#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) +#define ADC_FLAGS_OVERRUN8_MASK (0x100000U) +#define ADC_FLAGS_OVERRUN8_SHIFT (20U) +#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) +#define ADC_FLAGS_OVERRUN9_MASK (0x200000U) +#define ADC_FLAGS_OVERRUN9_SHIFT (21U) +#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) +#define ADC_FLAGS_OVERRUN10_MASK (0x400000U) +#define ADC_FLAGS_OVERRUN10_SHIFT (22U) +#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) +#define ADC_FLAGS_OVERRUN11_MASK (0x800000U) +#define ADC_FLAGS_OVERRUN11_SHIFT (23U) +#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) +#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) +#define ADC_FLAGS_SEQA_OVR_SHIFT (24U) +#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) +#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) +#define ADC_FLAGS_SEQB_OVR_SHIFT (25U) +#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) +#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) +#define ADC_FLAGS_SEQA_INT_SHIFT (28U) +#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) +#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) +#define ADC_FLAGS_SEQB_INT_SHIFT (29U) +#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) +#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) +#define ADC_FLAGS_THCMP_INT_SHIFT (30U) +#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) +#define ADC_FLAGS_OVR_INT_MASK (0x80000000U) +#define ADC_FLAGS_OVR_INT_SHIFT (31U) +#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) +/*! @} */ + +/*! @name STARTUP - ADC Startup register. */ +/*! @{ */ +#define ADC_STARTUP_ADC_ENA_MASK (0x1U) +#define ADC_STARTUP_ADC_ENA_SHIFT (0U) +#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) +#define ADC_STARTUP_ADC_INIT_MASK (0x2U) +#define ADC_STARTUP_ADC_INIT_SHIFT (1U) +#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) +/*! @} */ + +/*! @name CALIB - ADC Calibration register. */ +/*! @{ */ +#define ADC_CALIB_CALIB_MASK (0x1U) +#define ADC_CALIB_CALIB_SHIFT (0U) +#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) +#define ADC_CALIB_CALREQD_MASK (0x2U) +#define ADC_CALIB_CALREQD_SHIFT (1U) +#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) +#define ADC_CALIB_CALVALUE_MASK (0x1FCU) +#define ADC_CALIB_CALVALUE_SHIFT (2U) +#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400A0000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } +#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ASYNC_SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer + * @{ + */ + +/** ASYNC_SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ + __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ + __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ + __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ + __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ +} ASYNC_SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- ASYNC_SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks + * @{ + */ + +/*! @name ASYNCPRESETCTRL - Async peripheral reset control */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) +/*! @} */ + +/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) +/*! @} */ + +/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ASYNC_SYSCON_Register_Masks */ + + +/* ASYNC_SYSCON - Peripheral instance base addresses */ +/** Peripheral ASYNC_SYSCON base address */ +#define ASYNC_SYSCON_BASE (0x40040000u) +/** Peripheral ASYNC_SYSCON base pointer */ +#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) +/** Array initializer of ASYNC_SYSCON peripheral base addresses */ +#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } +/** Array initializer of ASYNC_SYSCON peripheral base pointers */ +#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } + +/*! + * @} + */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +/*! @{ */ +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ + +/*! @name SEED - CRC seed register */ +/*! @{ */ +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ + +/*! @name SUM - CRC checksum register */ +/*! @{ */ +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ + +/*! @name WR_DATA - CRC data register */ +/*! @{ */ +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC_ENGINE base address */ +#define CRC_ENGINE_BASE (0x40095000u) +/** Peripheral CRC_ENGINE base pointer */ +#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC_ENGINE_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC_ENGINE } + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ + +/*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ +/*! @{ */ +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ +/*! @{ */ +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ +/*! @{ */ +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ +/*! @{ */ +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) +/*! @} */ + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ +/*! @{ */ +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40008000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40009000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40028000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40048000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40049000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, NotAvail_IRQn, CTIMER3_IRQn, NotAvail_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[1]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[20]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +/*! @{ */ +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status. */ +/*! @{ */ +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (20U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (20U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (20U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40082000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMIC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer + * @{ + */ + +/** DMIC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x100 */ + __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */ + __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */ + __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */ + __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */ + __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */ + uint8_t RESERVED_0[108]; + __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */ + __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */ + __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */ + __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */ + __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */ + uint8_t RESERVED_1[108]; + } CHANNEL[2]; + uint8_t RESERVED_0[3328]; + __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ + uint8_t RESERVED_1[8]; + __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */ + __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */ + uint8_t RESERVED_2[108]; + __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */ + __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */ + __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */ + __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */ + __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */ + __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */ + __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */ + uint8_t RESERVED_3[96]; + __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */ +} DMIC_Type; + +/* ---------------------------------------------------------------------------- + -- DMIC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMIC_Register_Masks DMIC Register Masks + * @{ + */ + +/*! @name CHANNEL_OSR - Oversample Rate register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) +#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) +#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_OSR */ +#define DMIC_CHANNEL_OSR_COUNT (2U) + +/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_DIVHFCLK */ +#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) + +/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ +/*! @{ */ +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_PREAC2FSCOEF */ +#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) + +/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ +/*! @{ */ +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_PREAC4FSCOEF */ +#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) + +/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ +/*! @{ */ +#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) +#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) +#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_GAINSHIFT */ +#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) + +/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) +#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) +#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) +#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) +#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_FIFO_CTRL */ +#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) + +/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) +#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) +#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_FIFO_STATUS */ +#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) + +/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) +#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) +#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_FIFO_DATA */ +#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) + +/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_PHY_CTRL */ +#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) + +/*! @name CHANNEL_DC_CTRL - DC Control register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) +#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) +#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) +#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) +#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) +#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_DC_CTRL */ +#define DMIC_CHANNEL_DC_CTRL_COUNT (2U) + +/*! @name CHANEN - Channel Enable register */ +/*! @{ */ +#define DMIC_CHANEN_EN_CH0_MASK (0x1U) +#define DMIC_CHANEN_EN_CH0_SHIFT (0U) +#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) +#define DMIC_CHANEN_EN_CH1_MASK (0x2U) +#define DMIC_CHANEN_EN_CH1_SHIFT (1U) +#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) +/*! @} */ + +/*! @name IOCFG - I/O Configuration register */ +/*! @{ */ +#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) +#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) +#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) +#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U) +#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U) +#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK) +#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) +#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) +#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) +/*! @} */ + +/*! @name USE2FS - Use 2FS register */ +/*! @{ */ +#define DMIC_USE2FS_USE2FS_MASK (0x1U) +#define DMIC_USE2FS_USE2FS_SHIFT (0U) +#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) +/*! @} */ + +/*! @name HWVADGAIN - HWVAD input gain register */ +/*! @{ */ +#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) +#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) +#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) +/*! @} */ + +/*! @name HWVADHPFS - HWVAD filter control register */ +/*! @{ */ +#define DMIC_HWVADHPFS_HPFS_MASK (0x3U) +#define DMIC_HWVADHPFS_HPFS_SHIFT (0U) +#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) +/*! @} */ + +/*! @name HWVADST10 - HWVAD control register */ +/*! @{ */ +#define DMIC_HWVADST10_ST10_MASK (0x1U) +#define DMIC_HWVADST10_ST10_SHIFT (0U) +#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) +/*! @} */ + +/*! @name HWVADRSTT - HWVAD filter reset register */ +/*! @{ */ +#define DMIC_HWVADRSTT_RSTT_MASK (0x1U) +#define DMIC_HWVADRSTT_RSTT_SHIFT (0U) +#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) +/*! @} */ + +/*! @name HWVADTHGN - HWVAD noise estimator gain register */ +/*! @{ */ +#define DMIC_HWVADTHGN_THGN_MASK (0xFU) +#define DMIC_HWVADTHGN_THGN_SHIFT (0U) +#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) +/*! @} */ + +/*! @name HWVADTHGS - HWVAD signal estimator gain register */ +/*! @{ */ +#define DMIC_HWVADTHGS_THGS_MASK (0xFU) +#define DMIC_HWVADTHGS_THGS_SHIFT (0U) +#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) +/*! @} */ + +/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ +/*! @{ */ +#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) +#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) +#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) +/*! @} */ + +/*! @name ID - Module Identification register */ +/*! @{ */ +#define DMIC_ID_ID_MASK (0xFFFFFFFFU) +#define DMIC_ID_ID_SHIFT (0U) +#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DMIC_Register_Masks */ + + +/* DMIC - Peripheral instance base addresses */ +/** Peripheral DMIC0 base address */ +#define DMIC0_BASE (0x40090000u) +/** Peripheral DMIC0 base pointer */ +#define DMIC0 ((DMIC_Type *)DMIC0_BASE) +/** Array initializer of DMIC peripheral base addresses */ +#define DMIC_BASE_ADDRS { DMIC0_BASE } +/** Array initializer of DMIC peripheral base pointers */ +#define DMIC_BASE_PTRS { DMIC0 } +/** Interrupt vectors for the DMIC peripheral type */ +#define DMIC_IRQS { DMIC0_IRQn } +#define DMIC_HWVAD_IRQS { HWVAD0_IRQn } + +/*! + * @} + */ /* end of group DMIC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral identification register. */ +/*! @{ */ +#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) +#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) +#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) +#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) +#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) +#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +/** Peripheral FLEXCOMM0 base address */ +#define FLEXCOMM0_BASE (0x40086000u) +/** Peripheral FLEXCOMM0 base pointer */ +#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) +/** Peripheral FLEXCOMM1 base address */ +#define FLEXCOMM1_BASE (0x40087000u) +/** Peripheral FLEXCOMM1 base pointer */ +#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) +/** Peripheral FLEXCOMM2 base address */ +#define FLEXCOMM2_BASE (0x40088000u) +/** Peripheral FLEXCOMM2 base pointer */ +#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) +/** Peripheral FLEXCOMM3 base address */ +#define FLEXCOMM3_BASE (0x40089000u) +/** Peripheral FLEXCOMM3 base pointer */ +#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) +/** Peripheral FLEXCOMM4 base address */ +#define FLEXCOMM4_BASE (0x4008A000u) +/** Peripheral FLEXCOMM4 base pointer */ +#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) +/** Peripheral FLEXCOMM5 base address */ +#define FLEXCOMM5_BASE (0x40096000u) +/** Peripheral FLEXCOMM5 base pointer */ +#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) +/** Peripheral FLEXCOMM6 base address */ +#define FLEXCOMM6_BASE (0x40097000u) +/** Peripheral FLEXCOMM6 base pointer */ +#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) +/** Peripheral FLEXCOMM7 base address */ +#define FLEXCOMM7_BASE (0x40098000u) +/** Peripheral FLEXCOMM7 base pointer */ +#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) +/** Array initializer of FLEXCOMM peripheral base addresses */ +#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE } +/** Array initializer of FLEXCOMM peripheral base pointers */ +#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7 } +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +/** Peripheral GINT0 base address */ +#define GINT0_BASE (0x40002000u) +/** Peripheral GINT0 base pointer */ +#define GINT0 ((GINT_Type *)GINT0_BASE) +/** Peripheral GINT1 base address */ +#define GINT1_BASE (0x40003000u) +/** Peripheral GINT1 base pointer */ +#define GINT1 ((GINT_Type *)GINT1_BASE) +/** Array initializer of GINT peripheral base addresses */ +#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } +/** Array initializer of GINT peripheral base pointers */ +#define GINT_BASE_PTRS { GINT0, GINT1 } +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[4032]; + __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3840]; + __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[120]; + __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[120]; + __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[120]; + __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[120]; + __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[120]; + __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[120]; + __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[120]; + __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ +/*! @{ */ +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_B */ +#define GPIO_B_COUNT (2U) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ +/*! @{ */ +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_W */ +#define GPIO_W_COUNT (2U) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers */ +/*! @{ */ +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (2U) + +/*! @name MASK - Mask register */ +/*! @{ */ +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (2U) + +/*! @name PIN - Port pin register */ +/*! @{ */ +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (2U) + +/*! @name MPIN - Masked port register */ +/*! @{ */ +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (2U) + +/*! @name SET - Write: Set register for port Read: output bits for port */ +/*! @{ */ +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (2U) + +/*! @name CLR - Clear port */ +/*! @{ */ +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (2U) + +/*! @name NOT - Toggle port */ +/*! @{ */ +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (2U) + +/*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (2U) + +/*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (2U) + +/*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (2U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO base address */ +#define GPIO_BASE (0x4008C000u) +/** Peripheral GPIO base pointer */ +#define GPIO ((GPIO_Type *)GPIO_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +/*! @{ */ +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master control register. */ +/*! @{ */ +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave control register. */ +/*! @{ */ +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave address register. */ +/*! @{ */ +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C0 base address */ +#define I2C0_BASE (0x40086000u) +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_Type *)I2C0_BASE) +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x40087000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x40088000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Peripheral I2C3 base address */ +#define I2C3_BASE (0x40089000u) +/** Peripheral I2C3 base pointer */ +#define I2C3 ((I2C_Type *)I2C3_BASE) +/** Peripheral I2C4 base address */ +#define I2C4_BASE (0x4008A000u) +/** Peripheral I2C4 base pointer */ +#define I2C4 ((I2C_Type *)I2C4_BASE) +/** Peripheral I2C5 base address */ +#define I2C5_BASE (0x40096000u) +/** Peripheral I2C5 base pointer */ +#define I2C5 ((I2C_Type *)I2C5_BASE) +/** Peripheral I2C6 base address */ +#define I2C6_BASE (0x40097000u) +/** Peripheral I2C6 base pointer */ +#define I2C6 ((I2C_Type *)I2C6_BASE) +/** Peripheral I2C7 base address */ +#define I2C7_BASE (0x40098000u) +/** Peripheral I2C7 base pointer */ +#define I2C7 ((I2C_Type *)I2C7_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + uint8_t RESERVED_2[480]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) +#define I2S_CFG1_PDMDATA_MASK (0x800U) +#define I2S_CFG1_PDMDATA_SHIFT (11U) +#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) +#define I2S_FIFOCFG_TXI2SSE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SSE0_SHIFT (2U) +#define I2S_FIFOCFG_TXI2SSE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SSE0_SHIFT)) & I2S_FIFOCFG_TXI2SSE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) +#define I2S_FIFOCFG_POPDBG_SHIFT (18U) +#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S0 base address */ +#define I2S0_BASE (0x40097000u) +/** Peripheral I2S0 base pointer */ +#define I2S0 ((I2S_Type *)I2S0_BASE) +/** Peripheral I2S1 base address */ +#define I2S1_BASE (0x40098000u) +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_Type *)I2S1_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { I2S0, I2S1 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[192]; + __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA_ITRIG_INMUX[22]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_1[40]; + __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ +#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (8U) + +/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ +/*! @{ */ +#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA_ITRIG_INMUX */ +#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U) + +/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ +/*! @{ */ +#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA_OTRIG_INMUX */ +#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX base address */ +#define INPUTMUX_BASE (0x40005000u) +/** Peripheral INPUTMUX base pointer */ +#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX } + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ +#define IOCON_PIO_FUNC_MASK (0x7U) +#define IOCON_PIO_FUNC_SHIFT (0U) +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) +#define IOCON_PIO_MODE_MASK (0x18U) +#define IOCON_PIO_MODE_SHIFT (3U) +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) +#define IOCON_PIO_I2CSLEW_MASK (0x20U) +#define IOCON_PIO_I2CSLEW_SHIFT (5U) +#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) +#define IOCON_PIO_INVERT_MASK (0x40U) +#define IOCON_PIO_INVERT_SHIFT (6U) +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) +#define IOCON_PIO_DIGIMODE_MASK (0x80U) +#define IOCON_PIO_DIGIMODE_SHIFT (7U) +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) +#define IOCON_PIO_FILTEROFF_MASK (0x100U) +#define IOCON_PIO_FILTEROFF_SHIFT (8U) +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) +#define IOCON_PIO_I2CDRIVE_MASK (0x200U) +#define IOCON_PIO_I2CDRIVE_SHIFT (9U) +#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) +#define IOCON_PIO_SLEW_MASK (0x200U) +#define IOCON_PIO_SLEW_SHIFT (9U) +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) +#define IOCON_PIO_I2CFILTER_MASK (0x400U) +#define IOCON_PIO_I2CFILTER_SHIFT (10U) +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +#define IOCON_PIO_OD_MASK (0x400U) +#define IOCON_PIO_OD_SHIFT (10U) +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (2U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +/** Peripheral IOCON base address */ +#define IOCON_BASE (0x40001000u) +/** Peripheral IOCON base pointer */ +#define IOCON ((IOCON_Type *)IOCON_BASE) +/** Array initializer of IOCON peripheral base addresses */ +#define IOCON_BASE_ADDRS { IOCON_BASE } +/** Array initializer of IOCON peripheral base pointers */ +#define IOCON_BASE_PTRS { IOCON } + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer + * @{ + */ + +/** MAILBOX - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ + __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ + __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } MBOXIRQ[2]; + uint8_t RESERVED_0[216]; + __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ +} MAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- MAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks + * @{ + */ + +/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQ */ +#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) + +/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQSET */ +#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) + +/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQCLR */ +#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) + +/*! @name MUTEX - Mutual exclusion register[1] */ +/*! @{ */ +#define MAILBOX_MUTEX_EX_MASK (0x1U) +#define MAILBOX_MUTEX_EX_SHIFT (0U) +#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MAILBOX_Register_Masks */ + + +/* MAILBOX - Peripheral instance base addresses */ +/** Peripheral MAILBOX base address */ +#define MAILBOX_BASE (0x4008B000u) +/** Peripheral MAILBOX base pointer */ +#define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) +/** Array initializer of MAILBOX peripheral base addresses */ +#define MAILBOX_BASE_ADDRS { MAILBOX_BASE } +/** Array initializer of MAILBOX peripheral base pointers */ +#define MAILBOX_BASE_PTRS { MAILBOX } +/** Interrupt vectors for the MAILBOX peripheral type */ +#define MAILBOX_IRQS { MAILBOX_IRQn } + +/*! + * @} + */ /* end of group MAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +/** Peripheral MRT0 base address */ +#define MRT0_BASE (0x4000D000u) +/** Peripheral MRT0 base pointer */ +#define MRT0 ((MRT_Type *)MRT0_BASE) +/** Array initializer of MRT peripheral base addresses */ +#define MRT_BASE_ADDRS { MRT0_BASE } +/** Array initializer of MRT peripheral base pointers */ +#define MRT_BASE_PTRS { MRT0 } +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin interrupt status register */ +/*! @{ */ +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +/** Peripheral PINT base address */ +#define PINT_BASE (0x40004000u) +/** Peripheral PINT base pointer */ +#define PINT ((PINT_Type *)PINT_BASE) +/** Array initializer of PINT peripheral base addresses */ +#define PINT_BASE_ADDRS { PINT_BASE } +/** Array initializer of PINT peripheral base pointers */ +#define PINT_BASE_PTRS { PINT } +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +/*! @{ */ +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) +#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) +#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) +#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) +/*! @} */ + +/*! @name MATCH - RTC match register */ +/*! @{ */ +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ + +/*! @name COUNT - RTC counter register */ +/*! @{ */ +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ + +/*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE (0x4002C000u) +/** Peripheral RTC base pointer */ +#define RTC ((RTC_Type *)RTC_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + uint8_t RESERVED_0[40]; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_2[216]; + union { /* offset: 0x200 */ + __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_3[216]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EVENT[10]; + uint8_t RESERVED_4[432]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[8]; + uint8_t RESERVED_5[700]; + uint32_t MODULECONTENT; /**< Reserved, offset: 0x7FC */ +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +/*! @{ */ +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) +#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) +#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) +#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT control register */ +/*! @{ */ +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMIT - SCT limit event select register */ +/*! @{ */ +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALT - SCT halt event select register */ +/*! @{ */ +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOP - SCT stop event select register */ +/*! @{ */ +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name START - SCT start event select register */ +/*! @{ */ +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name COUNT - SCT counter register */ +/*! @{ */ +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATE - SCT state register */ +/*! @{ */ +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - SCT input register */ +/*! @{ */ +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ + +/*! @name OUTPUT - SCT output register */ +/*! @{ */ +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ + +/*! @name RES - SCT conflict resolution register */ +/*! @{ */ +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ + +/*! @name DMA0REQUEST - SCT DMA request 0 register */ +/*! @{ */ +#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) +#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) +#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) +#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) +#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) +#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) +#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) +#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) +#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) +/*! @} */ + +/*! @name DMA1REQUEST - SCT DMA request 1 register */ +/*! @{ */ +#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) +#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) +#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) +#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) +#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) +#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) +#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) +#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) +#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ + +/*! @name EVFLAG - SCT event flag register */ +/*! @{ */ +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ + +/*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ + +/*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name SCTCAP - SCT capture register of capture channel */ +/*! @{ */ +#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) +#define SCT_SCTCAP_CAPn_L_SHIFT (0U) +#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) +#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAP_CAPn_H_SHIFT (16U) +#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAP */ +#define SCT_SCTCAP_COUNT (10U) + +/*! @name SCTMATCH - SCT match value register of match channels */ +/*! @{ */ +#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) +#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) +#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) +#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTMATCH */ +#define SCT_SCTMATCH_COUNT (10U) + +/*! @name SCTCAPCTRL - SCT capture control register */ +/*! @{ */ +#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) +#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) +#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) +#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAPCTRL */ +#define SCT_SCTCAPCTRL_COUNT (10U) + +/*! @name SCTMATCHREL - SCT match reload value register */ +/*! @{ */ +#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) +#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) +#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) +#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTMATCHREL */ +#define SCT_SCTMATCHREL_COUNT (10U) + +/*! @name EVENT_STATE - SCT event state register 0 */ +/*! @{ */ +#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) +#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EVENT_STATE */ +#define SCT_EVENT_STATE_COUNT (10U) + +/*! @name EVENT_CTRL - SCT event control register 0 */ +/*! @{ */ +#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) +#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) +#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) +#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) +#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) +#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) +#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) +#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) +#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) +#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) +#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) +#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) +#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) +#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) +#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) +#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) +#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) +#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) +#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) +#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) +#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) +#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EVENT_CTRL */ +#define SCT_EVENT_CTRL_COUNT (10U) + +/*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (8U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (8U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +/** Peripheral SCT0 base address */ +#define SCT0_BASE (0x40085000u) +/** Peripheral SCT0 base pointer */ +#define SCT0 ((SCT_Type *)SCT0_BASE) +/** Array initializer of SCT peripheral base addresses */ +#define SCT_BASE_ADDRS { SCT0_BASE } +/** Array initializer of SCT peripheral base pointers */ +#define SCT_BASE_PTRS { SCT0 } +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +/*! @{ */ +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - SPI Delay register */ +/*! @{ */ +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - SPI clock Divider */ +/*! @{ */ +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +/** Peripheral SPI0 base address */ +#define SPI0_BASE (0x40086000u) +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) +/** Peripheral SPI1 base address */ +#define SPI1_BASE (0x40087000u) +/** Peripheral SPI1 base pointer */ +#define SPI1 ((SPI_Type *)SPI1_BASE) +/** Peripheral SPI2 base address */ +#define SPI2_BASE (0x40088000u) +/** Peripheral SPI2 base pointer */ +#define SPI2 ((SPI_Type *)SPI2_BASE) +/** Peripheral SPI3 base address */ +#define SPI3_BASE (0x40089000u) +/** Peripheral SPI3 base pointer */ +#define SPI3 ((SPI_Type *)SPI3_BASE) +/** Peripheral SPI4 base address */ +#define SPI4_BASE (0x4008A000u) +/** Peripheral SPI4 base pointer */ +#define SPI4 ((SPI_Type *)SPI4_BASE) +/** Peripheral SPI5 base address */ +#define SPI5_BASE (0x40096000u) +/** Peripheral SPI5 base pointer */ +#define SPI5 ((SPI_Type *)SPI5_BASE) +/** Peripheral SPI6 base address */ +#define SPI6_BASE (0x40097000u) +/** Peripheral SPI6 base pointer */ +#define SPI6 ((SPI_Type *)SPI6_BASE) +/** Peripheral SPI7 base address */ +#define SPI7_BASE (0x40098000u) +/** Peripheral SPI7 base pointer */ +#define SPI7 ((SPI_Type *)SPI7_BASE) +/** Array initializer of SPI peripheral base addresses */ +#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE } +/** Array initializer of SPI peripheral base pointers */ +#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPIFI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer + * @{ + */ + +/** SPIFI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */ + __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */ + __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */ + __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */ + __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */ + __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */ + __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */ + __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */ +} SPIFI_Type; + +/* ---------------------------------------------------------------------------- + -- SPIFI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPIFI_Register_Masks SPIFI Register Masks + * @{ + */ + +/*! @name CTRL - SPIFI control register */ +/*! @{ */ +#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) +#define SPIFI_CTRL_TIMEOUT_SHIFT (0U) +#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) +#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U) +#define SPIFI_CTRL_CSHIGH_SHIFT (16U) +#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK) +#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U) +#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U) +#define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK) +#define SPIFI_CTRL_INTEN_MASK (0x400000U) +#define SPIFI_CTRL_INTEN_SHIFT (22U) +#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK) +#define SPIFI_CTRL_MODE3_MASK (0x800000U) +#define SPIFI_CTRL_MODE3_SHIFT (23U) +#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK) +#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U) +#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U) +#define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK) +#define SPIFI_CTRL_DUAL_MASK (0x10000000U) +#define SPIFI_CTRL_DUAL_SHIFT (28U) +#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK) +#define SPIFI_CTRL_RFCLK_MASK (0x20000000U) +#define SPIFI_CTRL_RFCLK_SHIFT (29U) +#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK) +#define SPIFI_CTRL_FBCLK_MASK (0x40000000U) +#define SPIFI_CTRL_FBCLK_SHIFT (30U) +#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK) +#define SPIFI_CTRL_DMAEN_MASK (0x80000000U) +#define SPIFI_CTRL_DMAEN_SHIFT (31U) +#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) +/*! @} */ + +/*! @name CMD - SPIFI command register */ +/*! @{ */ +#define SPIFI_CMD_DATALEN_MASK (0x3FFFU) +#define SPIFI_CMD_DATALEN_SHIFT (0U) +#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) +#define SPIFI_CMD_POLL_MASK (0x4000U) +#define SPIFI_CMD_POLL_SHIFT (14U) +#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK) +#define SPIFI_CMD_DOUT_MASK (0x8000U) +#define SPIFI_CMD_DOUT_SHIFT (15U) +#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK) +#define SPIFI_CMD_INTLEN_MASK (0x70000U) +#define SPIFI_CMD_INTLEN_SHIFT (16U) +#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK) +#define SPIFI_CMD_FIELDFORM_MASK (0x180000U) +#define SPIFI_CMD_FIELDFORM_SHIFT (19U) +#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK) +#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U) +#define SPIFI_CMD_FRAMEFORM_SHIFT (21U) +#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK) +#define SPIFI_CMD_OPCODE_MASK (0xFF000000U) +#define SPIFI_CMD_OPCODE_SHIFT (24U) +#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) +/*! @} */ + +/*! @name ADDR - SPIFI address register */ +/*! @{ */ +#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) +#define SPIFI_ADDR_ADDRESS_SHIFT (0U) +#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name IDATA - SPIFI intermediate data register */ +/*! @{ */ +#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) +#define SPIFI_IDATA_IDATA_SHIFT (0U) +#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) +/*! @} */ + +/*! @name CLIMIT - SPIFI limit register */ +/*! @{ */ +#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) +#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) +#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) +/*! @} */ + +/*! @name DATA - SPIFI data register */ +/*! @{ */ +#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) +#define SPIFI_DATA_DATA_SHIFT (0U) +#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) +/*! @} */ + +/*! @name MCMD - SPIFI memory command register */ +/*! @{ */ +#define SPIFI_MCMD_POLL_MASK (0x4000U) +#define SPIFI_MCMD_POLL_SHIFT (14U) +#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) +#define SPIFI_MCMD_DOUT_MASK (0x8000U) +#define SPIFI_MCMD_DOUT_SHIFT (15U) +#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK) +#define SPIFI_MCMD_INTLEN_MASK (0x70000U) +#define SPIFI_MCMD_INTLEN_SHIFT (16U) +#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK) +#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U) +#define SPIFI_MCMD_FIELDFORM_SHIFT (19U) +#define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK) +#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U) +#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U) +#define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK) +#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) +#define SPIFI_MCMD_OPCODE_SHIFT (24U) +#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) +/*! @} */ + +/*! @name STAT - SPIFI status register */ +/*! @{ */ +#define SPIFI_STAT_MCINIT_MASK (0x1U) +#define SPIFI_STAT_MCINIT_SHIFT (0U) +#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) +#define SPIFI_STAT_CMD_MASK (0x2U) +#define SPIFI_STAT_CMD_SHIFT (1U) +#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK) +#define SPIFI_STAT_RESET_MASK (0x10U) +#define SPIFI_STAT_RESET_SHIFT (4U) +#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK) +#define SPIFI_STAT_INTRQ_MASK (0x20U) +#define SPIFI_STAT_INTRQ_SHIFT (5U) +#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK) +#define SPIFI_STAT_VERSION_MASK (0xFF000000U) +#define SPIFI_STAT_VERSION_SHIFT (24U) +#define SPIFI_STAT_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPIFI_Register_Masks */ + + +/* SPIFI - Peripheral instance base addresses */ +/** Peripheral SPIFI0 base address */ +#define SPIFI0_BASE (0x40080000u) +/** Peripheral SPIFI0 base pointer */ +#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE) +/** Array initializer of SPIFI peripheral base addresses */ +#define SPIFI_BASE_ADDRS { SPIFI0_BASE } +/** Array initializer of SPIFI peripheral base pointers */ +#define SPIFI_BASE_PTRS { SPIFI0 } + +/*! + * @} + */ /* end of group SPIFI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ + uint8_t RESERVED_1[44]; + __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ + uint8_t RESERVED_3[112]; + __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ + uint8_t RESERVED_5[40]; + __IO uint32_t PRESETCTRL[2]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_6[24]; + __O uint32_t PRESETCTRLSET[2]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_7[24]; + __O uint32_t PRESETCTRLCLR[2]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_8[168]; + __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t AHBCLKCTRL[2]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __O uint32_t AHBCLKCTRLSET[2]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_11[24]; + __O uint32_t AHBCLKCTRLCLR[2]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_12[56]; + __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ + __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ + uint8_t RESERVED_13[4]; + __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ + uint8_t RESERVED_14[12]; + __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */ + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USBCLKSEL; /**< USB clock source select, offset: 0x2A8 */ + uint8_t RESERVED_15[4]; + __IO uint32_t FXCOMCLKSEL[8]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */ + uint8_t RESERVED_16[16]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_17[4]; + __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ + __IO uint32_t DMICCLKSEL; /**< Digital microphone (D-Mic) subsystem clock select, offset: 0x2EC */ + uint8_t RESERVED_18[16]; + __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ + __IO uint32_t TRACECLKDIV; /**< Trace clock divider, offset: 0x304 */ + uint8_t RESERVED_19[120]; + __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + uint8_t RESERVED_20[8]; + __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */ + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USBCLKDIV; /**< USB clock divider, offset: 0x398 */ + uint8_t RESERVED_21[4]; + __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ + uint8_t RESERVED_22[4]; + __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */ + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_23[80]; + __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ + uint8_t RESERVED_24[8]; + __IO uint32_t USBCLKCTRL; /**< USB clock control, offset: 0x40C */ + __IO uint32_t USBCLKSTAT; /**< USB clock status, offset: 0x410 */ + uint8_t RESERVED_25[4]; + __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ + uint8_t RESERVED_26[4]; + __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ + uint8_t RESERVED_27[220]; + __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ + uint8_t RESERVED_28[4]; + __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ + __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ + uint8_t RESERVED_29[112]; + __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x580 */ + __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ + __IO uint32_t SYSPLLNDEC; /**< PLL N decoder, offset: 0x588 */ + __IO uint32_t SYSPLLPDEC; /**< PLL P decoder, offset: 0x58C */ + __IO uint32_t SYSPLLSSCTRL0; /**< PLL spread spectrum control 0, offset: 0x590 */ + __IO uint32_t SYSPLLSSCTRL1; /**< PLL spread spectrum control 1, offset: 0x594 */ + uint8_t RESERVED_30[104]; + __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register n, array offset: 0x600, array step: 0x4 */ + uint8_t RESERVED_31[8]; + __IO uint32_t PDRUNCFG[2]; /**< Power configuration register n, array offset: 0x610, array step: 0x4 */ + uint8_t RESERVED_32[8]; + __O uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFGn, array offset: 0x620, array step: 0x4 */ + uint8_t RESERVED_33[8]; + __O uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFGn, array offset: 0x630, array step: 0x4 */ + uint8_t RESERVED_34[72]; + __IO uint32_t STARTERP[2]; /**< Start logic n wake-up enable register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_35[24]; + __O uint32_t STARTERSET[2]; /**< Set bits in STARTERn, array offset: 0x6A0, array step: 0x4 */ + uint8_t RESERVED_36[24]; + __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTERn, array offset: 0x6C0, array step: 0x4 */ + uint8_t RESERVED_37[184]; + __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ + uint8_t RESERVED_38[124]; + __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ + __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ + __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ + __I uint32_t CPSTAT; /**< Coprocessor Status, offset: 0x80C */ + uint8_t RESERVED_39[1524]; + __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */ + uint8_t RESERVED_40[492]; + __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ + __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ + uint8_t RESERVED_41[127044]; + __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name AHBMATPRIO - AHB multilayer matrix priority control */ +/*! @{ */ +#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) +#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) +#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) +#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) +#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) +#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) +#define SYSCON_AHBMATPRIO_PRI_M0_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_M0_SHIFT (6U) +#define SYSCON_AHBMATPRIO_PRI_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_M0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_M0_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_SHIFT (8U) +#define SYSCON_AHBMATPRIO_PRI_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_MASK) +#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U) +#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) +/*! @} */ + +/*! @name SYSTCKCAL - System tick counter calibration */ +/*! @{ */ +#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) +#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) +#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) +#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) +#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) +#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) +#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ +#define SYSCON_NMISRC_IRQM4_MASK (0x3FU) +#define SYSCON_NMISRC_IRQM4_SHIFT (0U) +#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) +#define SYSCON_NMISRC_IRQM0_MASK (0x3F00U) +#define SYSCON_NMISRC_IRQM0_SHIFT (8U) +#define SYSCON_NMISRC_IRQM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM0_SHIFT)) & SYSCON_NMISRC_IRQM0_MASK) +#define SYSCON_NMISRC_NMIENM0_MASK (0x40000000U) +#define SYSCON_NMISRC_NMIENM0_SHIFT (30U) +#define SYSCON_NMISRC_NMIENM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM0_SHIFT)) & SYSCON_NMISRC_NMIENM0_MASK) +#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENM4_SHIFT (31U) +#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) +/*! @} */ + +/*! @name ASYNCAPBCTRL - Asynchronous APB Control */ +/*! @{ */ +#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) +#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) +#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) +/*! @} */ + +/*! @name PIOPORCAP - POR captured value of port n */ +/*! @{ */ +#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) +#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) +#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) +/*! @} */ + +/* The count of SYSCON_PIOPORCAP */ +#define SYSCON_PIOPORCAP_COUNT (2U) + +/*! @name PIORESCAP - Reset captured value of port n */ +/*! @{ */ +#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) +#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) +#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) +/*! @} */ + +/* The count of SYSCON_PIORESCAP */ +#define SYSCON_PIORESCAP_COUNT (2U) + +/*! @name PRESETCTRL - Peripheral reset control n */ +/*! @{ */ +#define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U) +#define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK) +#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) +#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) +#define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) +#define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) +#define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) +#define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) +#define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U) +#define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK) +#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) +#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) +#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) +#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) +#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) +#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) +#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) +#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) +#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) +#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) +#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) +#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) +#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) +#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) +#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) +#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) +#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) +#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) +#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) +#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) +#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) +#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) +#define SYSCON_PRESETCTRL_DMIC0_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL_DMIC0_RST_SHIFT (19U) +#define SYSCON_PRESETCTRL_DMIC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC0_RST_MASK) +#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) +#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) +#define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) +#define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) +#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) +#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U) +#define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK) +#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) +#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) +#define SYSCON_PRESETCTRL_USB0_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL_USB0_RST_SHIFT (25U) +#define SYSCON_PRESETCTRL_USB0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) +#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) +#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) +#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) +#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRL */ +#define SYSCON_PRESETCTRL_COUNT (2U) + +/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ +/*! @{ */ +#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) +#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (2U) + +/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ +/*! @{ */ +#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) +#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (2U) + +/*! @name SYSRSTSTAT - System reset status register */ +/*! @{ */ +#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) +#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) +#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) +#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) +#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) +#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) +#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) +#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) +#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) +#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) +#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) +#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) +#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) +#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) +#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL - AHB Clock control n */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U) +#define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U) +#define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK) +#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) +#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) +#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) +#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) +#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) +#define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U) +#define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK) +#define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U) +#define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK) +#define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) +#define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) +#define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) +#define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) +#define SYSCON_AHBCLKCTRL_UTICK0_MASK (0x400U) +#define SYSCON_AHBCLKCTRL_UTICK0_SHIFT (10U) +#define SYSCON_AHBCLKCTRL_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK0_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) +#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) +#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) +#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) +#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) +#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) +#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) +#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) +#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) +#define SYSCON_AHBCLKCTRL_DMIC0_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL_DMIC0_SHIFT (19U) +#define SYSCON_AHBCLKCTRL_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC0_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC0_MASK) +#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) +#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) +#define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U) +#define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK) +#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) +#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U) +#define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK) +#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) +#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) +#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) +#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) +#define SYSCON_AHBCLKCTRL_USB0_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL_USB0_SHIFT (25U) +#define SYSCON_AHBCLKCTRL_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0_SHIFT)) & SYSCON_AHBCLKCTRL_USB0_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) +#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) +#define SYSCON_AHBCLKCTRL_MAILBOX_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL_MAILBOX_SHIFT (26U) +#define SYSCON_AHBCLKCTRL_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL_MAILBOX_MASK) +#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) +#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) +#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRL */ +#define SYSCON_AHBCLKCTRL_COUNT (2U) + +/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) +#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (2U) + +/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (2U) + +/*! @name MAINCLKSELA - Main clock source select A */ +/*! @{ */ +#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select B */ +/*! @{ */ +#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSELA - CLKOUT clock source select A */ +/*! @{ */ +#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) +#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) +#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) +/*! @} */ + +/*! @name SYSPLLCLKSEL - PLL clock source select */ +/*! @{ */ +#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) +#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SPIFICLKSEL - SPIFI clock source select */ +/*! @{ */ +#define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) +#define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) +#define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USBCLKSEL - USB clock source select */ +/*! @{ */ +#define SYSCON_USBCLKSEL_SEL_MASK (0x7U) +#define SYSCON_USBCLKSEL_SEL_SHIFT (0U) +#define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FXCOMCLKSEL - Flexcomm 0 clock source select */ +/*! @{ */ +#define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U) +#define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_FXCOMCLKSEL */ +#define SYSCON_FXCOMCLKSEL_COUNT (8U) + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ +/*! @{ */ +#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) +#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name DMICCLKSEL - Digital microphone (D-Mic) subsystem clock select */ +/*! @{ */ +#define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) +#define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) +#define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV - SYSTICK clock divider */ +/*! @{ */ +#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) +#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) +#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) +#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) +#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name TRACECLKDIV - Trace clock divider */ +/*! @{ */ +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) +/*! @} */ + +/*! @name AHBCLKDIV - AHB clock divider */ +/*! @{ */ +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) +#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) +#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) +#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) +#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) +/*! @} */ + +/*! @name SPIFICLKDIV - SPIFI clock divider */ +/*! @{ */ +#define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) +#define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) +#define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U) +#define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK) +#define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) +#define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) +/*! @} */ + +/*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ +#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) +#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) +#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) +#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) +#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name USBCLKDIV - USB clock divider */ +/*! @{ */ +#define SYSCON_USBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USBCLKDIV_DIV_SHIFT (0U) +#define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK) +#define SYSCON_USBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USBCLKDIV_RESET_SHIFT (29U) +#define SYSCON_USBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_RESET_SHIFT)) & SYSCON_USBCLKDIV_RESET_MASK) +#define SYSCON_USBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USBCLKDIV_HALT_SHIFT (30U) +#define SYSCON_USBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_HALT_SHIFT)) & SYSCON_USBCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name FRGCTRL - Fractional rate divider */ +/*! @{ */ +#define SYSCON_FRGCTRL_DIV_MASK (0xFFU) +#define SYSCON_FRGCTRL_DIV_SHIFT (0U) +#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) +#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) +#define SYSCON_FRGCTRL_MULT_SHIFT (8U) +#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) +/*! @} */ + +/*! @name DMICCLKDIV - DMIC clock divider */ +/*! @{ */ +#define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) +#define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) +#define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_DMICCLKDIV_RESET_SHIFT (29U) +#define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK) +#define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) +#define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name FLASHCFG - Flash wait states configuration */ +/*! @{ */ +#define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) +#define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) +#define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) +#define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) +#define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) +#define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) +#define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) +#define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) +#define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) +#define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) +#define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) +#define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) +#define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) +#define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) +#define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) +#define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) +#define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) +#define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) +/*! @} */ + +/*! @name USBCLKCTRL - USB clock control */ +/*! @{ */ +#define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U) +#define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U) +#define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK) +/*! @} */ + +/*! @name USBCLKSTAT - USB clock status */ +/*! @{ */ +#define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U) +#define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U) +#define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK) +/*! @} */ + +/*! @name FREQMECTRL - Frequency measure register */ +/*! @{ */ +#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) +#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) +#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) +#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) +#define SYSCON_FREQMECTRL_PROG_SHIFT (31U) +#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK input/output control */ +/*! @{ */ +#define SYSCON_MCLKIO_DIR_MASK (0x1U) +#define SYSCON_MCLKIO_DIR_SHIFT (0U) +#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) +/*! @} */ + +/*! @name FROCTRL - FRO oscillator control */ +/*! @{ */ +#define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) +#define SYSCON_FROCTRL_TRIM_SHIFT (0U) +#define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) +#define SYSCON_FROCTRL_SEL_MASK (0x4000U) +#define SYSCON_FROCTRL_SEL_SHIFT (14U) +#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) +#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) +#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) +#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) +#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) +#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) +#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) +#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) +#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) +#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) +#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) +#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) +#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) +#define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) +#define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) +#define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) +/*! @} */ + +/*! @name WDTOSCCTRL - Watchdog oscillator control */ +/*! @{ */ +#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) +#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) +#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) +#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) +#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) +#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) +/*! @} */ + +/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ +/*! @{ */ +#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) +#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) +#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) +/*! @} */ + +/*! @name SYSPLLCTRL - PLL control */ +/*! @{ */ +#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) +#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) +#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) +#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) +#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) +#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) +#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) +#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) +#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) +#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) +#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) +#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) +#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK (0x10000U) +#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT (16U) +#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) +#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) +#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) +#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) +#define SYSCON_SYSPLLCTRL_BANDSEL_MASK (0x40000U) +#define SYSCON_SYSPLLCTRL_BANDSEL_SHIFT (18U) +#define SYSCON_SYSPLLCTRL_BANDSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT)) & SYSCON_SYSPLLCTRL_BANDSEL_MASK) +#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) +#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) +#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) +#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) +#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) +#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) +/*! @} */ + +/*! @name SYSPLLSTAT - PLL status */ +/*! @{ */ +#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) +#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) +#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) +/*! @} */ + +/*! @name SYSPLLNDEC - PLL N decoder */ +/*! @{ */ +#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) +#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) +#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) +#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) +#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) +#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) +/*! @} */ + +/*! @name SYSPLLPDEC - PLL P decoder */ +/*! @{ */ +#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) +#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) +#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) +#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) +#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) +#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) +/*! @} */ + +/*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */ +/*! @{ */ +#define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU) +#define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U) +#define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK) +#define SYSCON_SYSPLLSSCTRL0_MREQ_MASK (0x20000U) +#define SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT (17U) +#define SYSCON_SYSPLLSSCTRL0_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MREQ_MASK) +#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U) +#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U) +#define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) +/*! @} */ + +/*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */ +/*! @{ */ +#define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU) +#define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U) +#define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK) +#define SYSCON_SYSPLLSSCTRL1_MDREQ_MASK (0x80000U) +#define SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT (19U) +#define SYSCON_SYSPLLSSCTRL1_MDREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MDREQ_MASK) +#define SYSCON_SYSPLLSSCTRL1_MF_MASK (0x700000U) +#define SYSCON_SYSPLLSSCTRL1_MF_SHIFT (20U) +#define SYSCON_SYSPLLSSCTRL1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MF_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MF_MASK) +#define SYSCON_SYSPLLSSCTRL1_MR_MASK (0x3800000U) +#define SYSCON_SYSPLLSSCTRL1_MR_SHIFT (23U) +#define SYSCON_SYSPLLSSCTRL1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MR_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MR_MASK) +#define SYSCON_SYSPLLSSCTRL1_MC_MASK (0xC000000U) +#define SYSCON_SYSPLLSSCTRL1_MC_SHIFT (26U) +#define SYSCON_SYSPLLSSCTRL1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MC_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MC_MASK) +#define SYSCON_SYSPLLSSCTRL1_PD_MASK (0x10000000U) +#define SYSCON_SYSPLLSSCTRL1_PD_SHIFT (28U) +#define SYSCON_SYSPLLSSCTRL1_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_PD_MASK) +#define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U) +#define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U) +#define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK) +/*! @} */ + +/*! @name PDSLEEPCFG - Sleep configuration register n */ +/*! @{ */ +#define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU) +#define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U) +#define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK) +/*! @} */ + +/* The count of SYSCON_PDSLEEPCFG */ +#define SYSCON_PDSLEEPCFG_COUNT (2U) + +/*! @name PDRUNCFG - Power configuration register n */ +/*! @{ */ +#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) +#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) +#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) +#define SYSCON_PDRUNCFG_PD_FLASH_MASK (0x20U) +#define SYSCON_PDRUNCFG_PD_FLASH_SHIFT (5U) +#define SYSCON_PDRUNCFG_PD_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_MASK) +#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) +#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) +#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) +#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) +#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) +#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) +#define SYSCON_PDRUNCFG_PD_VDDFLASH_MASK (0x800U) +#define SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT (11U) +#define SYSCON_PDRUNCFG_PD_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDFLASH_MASK) +#define SYSCON_PDRUNCFG_LP_VDDFLASH_MASK (0x1000U) +#define SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT (12U) +#define SYSCON_PDRUNCFG_LP_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_LP_VDDFLASH_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x2000U) +#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (13U) +#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAM1_MASK (0x4000U) +#define SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT (14U) +#define SYSCON_PDRUNCFG_PDEN_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAM2_MASK (0x8000U) +#define SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT (15U) +#define SYSCON_PDRUNCFG_PDEN_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM2_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x10000U) +#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (16U) +#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) +#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) +#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) +#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) +#define SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK (0x40000U) +#define SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT (18U) +#define SYSCON_PDRUNCFG_PD_VDDHV_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK) +#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) +#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) +#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) +#define SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK (0x200000U) +#define SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT (21U) +#define SYSCON_PDRUNCFG_PDEN_USB_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) +#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) +#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) +#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) +#define SYSCON_PDRUNCFG_PD_FLASH_BG_MASK (0x2000000U) +#define SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT (25U) +#define SYSCON_PDRUNCFG_PD_FLASH_BG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_BG_MASK) +#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK (0x10000000U) +#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT (28U) +#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK) +#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK (0x20000000U) +#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT (29U) +#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK) +/*! @} */ + +/* The count of SYSCON_PDRUNCFG */ +#define SYSCON_PDRUNCFG_COUNT (2U) + +/*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */ +/*! @{ */ +#define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU) +#define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U) +#define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK) +/*! @} */ + +/* The count of SYSCON_PDRUNCFGSET */ +#define SYSCON_PDRUNCFGSET_COUNT (2U) + +/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */ +/*! @{ */ +#define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U) +#define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_PDRUNCFGCLR */ +#define SYSCON_PDRUNCFGCLR_COUNT (2U) + +/*! @name STARTERP - Start logic n wake-up enable register */ +/*! @{ */ +#define SYSCON_STARTERP_PINT4_MASK (0x1U) +#define SYSCON_STARTERP_PINT4_SHIFT (0U) +#define SYSCON_STARTERP_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT4_SHIFT)) & SYSCON_STARTERP_PINT4_MASK) +#define SYSCON_STARTERP_WDT_BOD_MASK (0x1U) +#define SYSCON_STARTERP_WDT_BOD_SHIFT (0U) +#define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK) +#define SYSCON_STARTERP_DMA0_MASK (0x2U) +#define SYSCON_STARTERP_DMA0_SHIFT (1U) +#define SYSCON_STARTERP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMA0_SHIFT)) & SYSCON_STARTERP_DMA0_MASK) +#define SYSCON_STARTERP_PINT5_MASK (0x2U) +#define SYSCON_STARTERP_PINT5_SHIFT (1U) +#define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK) +#define SYSCON_STARTERP_GINT0_MASK (0x4U) +#define SYSCON_STARTERP_GINT0_SHIFT (2U) +#define SYSCON_STARTERP_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT0_SHIFT)) & SYSCON_STARTERP_GINT0_MASK) +#define SYSCON_STARTERP_PINT6_MASK (0x4U) +#define SYSCON_STARTERP_PINT6_SHIFT (2U) +#define SYSCON_STARTERP_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT6_SHIFT)) & SYSCON_STARTERP_PINT6_MASK) +#define SYSCON_STARTERP_GINT1_MASK (0x8U) +#define SYSCON_STARTERP_GINT1_SHIFT (3U) +#define SYSCON_STARTERP_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT1_SHIFT)) & SYSCON_STARTERP_GINT1_MASK) +#define SYSCON_STARTERP_PINT7_MASK (0x8U) +#define SYSCON_STARTERP_PINT7_SHIFT (3U) +#define SYSCON_STARTERP_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT7_SHIFT)) & SYSCON_STARTERP_PINT7_MASK) +#define SYSCON_STARTERP_CTIMER2_MASK (0x10U) +#define SYSCON_STARTERP_CTIMER2_SHIFT (4U) +#define SYSCON_STARTERP_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER2_SHIFT)) & SYSCON_STARTERP_CTIMER2_MASK) +#define SYSCON_STARTERP_PIN_INT0_MASK (0x10U) +#define SYSCON_STARTERP_PIN_INT0_SHIFT (4U) +#define SYSCON_STARTERP_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT0_SHIFT)) & SYSCON_STARTERP_PIN_INT0_MASK) +#define SYSCON_STARTERP_CTIMER4_MASK (0x20U) +#define SYSCON_STARTERP_CTIMER4_SHIFT (5U) +#define SYSCON_STARTERP_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER4_SHIFT)) & SYSCON_STARTERP_CTIMER4_MASK) +#define SYSCON_STARTERP_PIN_INT1_MASK (0x20U) +#define SYSCON_STARTERP_PIN_INT1_SHIFT (5U) +#define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK) +#define SYSCON_STARTERP_PIN_INT2_MASK (0x40U) +#define SYSCON_STARTERP_PIN_INT2_SHIFT (6U) +#define SYSCON_STARTERP_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT2_SHIFT)) & SYSCON_STARTERP_PIN_INT2_MASK) +#define SYSCON_STARTERP_PIN_INT3_MASK (0x80U) +#define SYSCON_STARTERP_PIN_INT3_SHIFT (7U) +#define SYSCON_STARTERP_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT3_SHIFT)) & SYSCON_STARTERP_PIN_INT3_MASK) +#define SYSCON_STARTERP_UTICK0_MASK (0x100U) +#define SYSCON_STARTERP_UTICK0_SHIFT (8U) +#define SYSCON_STARTERP_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_UTICK0_SHIFT)) & SYSCON_STARTERP_UTICK0_MASK) +#define SYSCON_STARTERP_MRT0_MASK (0x200U) +#define SYSCON_STARTERP_MRT0_SHIFT (9U) +#define SYSCON_STARTERP_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MRT0_SHIFT)) & SYSCON_STARTERP_MRT0_MASK) +#define SYSCON_STARTERP_CTIMER0_MASK (0x400U) +#define SYSCON_STARTERP_CTIMER0_SHIFT (10U) +#define SYSCON_STARTERP_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER0_SHIFT)) & SYSCON_STARTERP_CTIMER0_MASK) +#define SYSCON_STARTERP_CTIMER1_MASK (0x800U) +#define SYSCON_STARTERP_CTIMER1_SHIFT (11U) +#define SYSCON_STARTERP_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER1_SHIFT)) & SYSCON_STARTERP_CTIMER1_MASK) +#define SYSCON_STARTERP_SCT0_MASK (0x1000U) +#define SYSCON_STARTERP_SCT0_SHIFT (12U) +#define SYSCON_STARTERP_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_SCT0_SHIFT)) & SYSCON_STARTERP_SCT0_MASK) +#define SYSCON_STARTERP_CTIMER3_MASK (0x2000U) +#define SYSCON_STARTERP_CTIMER3_SHIFT (13U) +#define SYSCON_STARTERP_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER3_SHIFT)) & SYSCON_STARTERP_CTIMER3_MASK) +#define SYSCON_STARTERP_FLEXCOMM0_MASK (0x4000U) +#define SYSCON_STARTERP_FLEXCOMM0_SHIFT (14U) +#define SYSCON_STARTERP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM0_SHIFT)) & SYSCON_STARTERP_FLEXCOMM0_MASK) +#define SYSCON_STARTERP_FLEXCOMM1_MASK (0x8000U) +#define SYSCON_STARTERP_FLEXCOMM1_SHIFT (15U) +#define SYSCON_STARTERP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM1_SHIFT)) & SYSCON_STARTERP_FLEXCOMM1_MASK) +#define SYSCON_STARTERP_FLEXCOMM2_MASK (0x10000U) +#define SYSCON_STARTERP_FLEXCOMM2_SHIFT (16U) +#define SYSCON_STARTERP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM2_SHIFT)) & SYSCON_STARTERP_FLEXCOMM2_MASK) +#define SYSCON_STARTERP_FLEXCOMM3_MASK (0x20000U) +#define SYSCON_STARTERP_FLEXCOMM3_SHIFT (17U) +#define SYSCON_STARTERP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM3_SHIFT)) & SYSCON_STARTERP_FLEXCOMM3_MASK) +#define SYSCON_STARTERP_FLEXCOMM4_MASK (0x40000U) +#define SYSCON_STARTERP_FLEXCOMM4_SHIFT (18U) +#define SYSCON_STARTERP_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM4_SHIFT)) & SYSCON_STARTERP_FLEXCOMM4_MASK) +#define SYSCON_STARTERP_FLEXCOMM5_MASK (0x80000U) +#define SYSCON_STARTERP_FLEXCOMM5_SHIFT (19U) +#define SYSCON_STARTERP_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM5_SHIFT)) & SYSCON_STARTERP_FLEXCOMM5_MASK) +#define SYSCON_STARTERP_FLEXCOMM6_MASK (0x100000U) +#define SYSCON_STARTERP_FLEXCOMM6_SHIFT (20U) +#define SYSCON_STARTERP_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM6_SHIFT)) & SYSCON_STARTERP_FLEXCOMM6_MASK) +#define SYSCON_STARTERP_FLEXCOMM7_MASK (0x200000U) +#define SYSCON_STARTERP_FLEXCOMM7_SHIFT (21U) +#define SYSCON_STARTERP_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM7_SHIFT)) & SYSCON_STARTERP_FLEXCOMM7_MASK) +#define SYSCON_STARTERP_ADC0_SEQA_MASK (0x400000U) +#define SYSCON_STARTERP_ADC0_SEQA_SHIFT (22U) +#define SYSCON_STARTERP_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQA_SHIFT)) & SYSCON_STARTERP_ADC0_SEQA_MASK) +#define SYSCON_STARTERP_ADC0_SEQB_MASK (0x800000U) +#define SYSCON_STARTERP_ADC0_SEQB_SHIFT (23U) +#define SYSCON_STARTERP_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQB_SHIFT)) & SYSCON_STARTERP_ADC0_SEQB_MASK) +#define SYSCON_STARTERP_ADC0_THCMP_MASK (0x1000000U) +#define SYSCON_STARTERP_ADC0_THCMP_SHIFT (24U) +#define SYSCON_STARTERP_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_THCMP_SHIFT)) & SYSCON_STARTERP_ADC0_THCMP_MASK) +#define SYSCON_STARTERP_DMIC0_MASK (0x2000000U) +#define SYSCON_STARTERP_DMIC0_SHIFT (25U) +#define SYSCON_STARTERP_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMIC0_SHIFT)) & SYSCON_STARTERP_DMIC0_MASK) +#define SYSCON_STARTERP_USB0_NEEDCLK_MASK (0x8000000U) +#define SYSCON_STARTERP_USB0_NEEDCLK_SHIFT (27U) +#define SYSCON_STARTERP_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTERP_USB0_NEEDCLK_MASK) +#define SYSCON_STARTERP_USB0_MASK (0x10000000U) +#define SYSCON_STARTERP_USB0_SHIFT (28U) +#define SYSCON_STARTERP_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_SHIFT)) & SYSCON_STARTERP_USB0_MASK) +#define SYSCON_STARTERP_RTC_MASK (0x20000000U) +#define SYSCON_STARTERP_RTC_SHIFT (29U) +#define SYSCON_STARTERP_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_RTC_SHIFT)) & SYSCON_STARTERP_RTC_MASK) +#define SYSCON_STARTERP_MAILBOX_MASK (0x80000000U) +#define SYSCON_STARTERP_MAILBOX_SHIFT (31U) +#define SYSCON_STARTERP_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MAILBOX_SHIFT)) & SYSCON_STARTERP_MAILBOX_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERP */ +#define SYSCON_STARTERP_COUNT (2U) + +/*! @name STARTERSET - Set bits in STARTERn */ +/*! @{ */ +#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) +#define SYSCON_STARTERSET_START_SET_SHIFT (0U) +#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERSET */ +#define SYSCON_STARTERSET_COUNT (2U) + +/*! @name STARTERCLR - Clear bits in STARTERn */ +/*! @{ */ +#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) +#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERCLR */ +#define SYSCON_STARTERCLR_COUNT (2U) + +/*! @name HWWAKE - Configures special cases of hardware wake-up */ +/*! @{ */ +#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) +#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) +#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) +#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) +#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) +#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) +#define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U) +#define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U) +#define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK) +#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) +#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) +#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) +/*! @} */ + +/*! @name CPUCTRL - CPU Control for multiple processors */ +/*! @{ */ +#define SYSCON_CPUCTRL_MASTERCPU_MASK (0x1U) +#define SYSCON_CPUCTRL_MASTERCPU_SHIFT (0U) +#define SYSCON_CPUCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_MASTERCPU_SHIFT)) & SYSCON_CPUCTRL_MASTERCPU_MASK) +#define SYSCON_CPUCTRL_CM4CLKEN_MASK (0x4U) +#define SYSCON_CPUCTRL_CM4CLKEN_SHIFT (2U) +#define SYSCON_CPUCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM4CLKEN_MASK) +#define SYSCON_CPUCTRL_CM0CLKEN_MASK (0x8U) +#define SYSCON_CPUCTRL_CM0CLKEN_SHIFT (3U) +#define SYSCON_CPUCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM0CLKEN_MASK) +#define SYSCON_CPUCTRL_CM4RSTEN_MASK (0x10U) +#define SYSCON_CPUCTRL_CM4RSTEN_SHIFT (4U) +#define SYSCON_CPUCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM4RSTEN_MASK) +#define SYSCON_CPUCTRL_CM0RSTEN_MASK (0x20U) +#define SYSCON_CPUCTRL_CM0RSTEN_SHIFT (5U) +#define SYSCON_CPUCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM0RSTEN_MASK) +#define SYSCON_CPUCTRL_POWERCPU_MASK (0x40U) +#define SYSCON_CPUCTRL_POWERCPU_SHIFT (6U) +#define SYSCON_CPUCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_POWERCPU_SHIFT)) & SYSCON_CPUCTRL_POWERCPU_MASK) +/*! @} */ + +/*! @name CPBOOT - Coprocessor Boot Address */ +/*! @{ */ +#define SYSCON_CPBOOT_BOOTADDR_MASK (0xFFFFFFFFU) +#define SYSCON_CPBOOT_BOOTADDR_SHIFT (0U) +#define SYSCON_CPBOOT_BOOTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_BOOTADDR_SHIFT)) & SYSCON_CPBOOT_BOOTADDR_MASK) +/*! @} */ + +/*! @name CPSTACK - Coprocessor Stack Address */ +/*! @{ */ +#define SYSCON_CPSTACK_STACKADDR_MASK (0xFFFFFFFFU) +#define SYSCON_CPSTACK_STACKADDR_SHIFT (0U) +#define SYSCON_CPSTACK_STACKADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_STACKADDR_SHIFT)) & SYSCON_CPSTACK_STACKADDR_MASK) +/*! @} */ + +/*! @name CPSTAT - Coprocessor Status */ +/*! @{ */ +#define SYSCON_CPSTAT_CM4SLEEPING_MASK (0x1U) +#define SYSCON_CPSTAT_CM4SLEEPING_SHIFT (0U) +#define SYSCON_CPSTAT_CM4SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM4SLEEPING_MASK) +#define SYSCON_CPSTAT_CM0SLEEPING_MASK (0x2U) +#define SYSCON_CPSTAT_CM0SLEEPING_SHIFT (1U) +#define SYSCON_CPSTAT_CM0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM0SLEEPING_MASK) +#define SYSCON_CPSTAT_CM4LOCKUP_MASK (0x4U) +#define SYSCON_CPSTAT_CM4LOCKUP_SHIFT (2U) +#define SYSCON_CPSTAT_CM4LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM4LOCKUP_MASK) +#define SYSCON_CPSTAT_CM0LOCKUP_MASK (0x8U) +#define SYSCON_CPSTAT_CM0LOCKUP_SHIFT (3U) +#define SYSCON_CPSTAT_CM0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM0LOCKUP_MASK) +/*! @} */ + +/*! @name AUTOCGOR - Auto Clock-Gate Override Register */ +/*! @{ */ +#define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) +#define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) +#define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) +#define SYSCON_AUTOCGOR_RAM1_MASK (0x4U) +#define SYSCON_AUTOCGOR_RAM1_SHIFT (2U) +#define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK) +#define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) +#define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) +#define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) +/*! @} */ + +/*! @name JTAGIDCODE - JTAG ID code register */ +/*! @{ */ +#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) +#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) +#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Part ID register */ +/*! @{ */ +#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) +#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) +/*! @} */ + +/*! @name DEVICE_ID1 - Boot ROM and die revision register */ +/*! @{ */ +#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) +#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) +/*! @} */ + +/*! @name BODCTRL - Brown-Out Detect control */ +/*! @{ */ +#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) +#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) +#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) +#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) +#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) +#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) +#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) +#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) +#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) +#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) +#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) +#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) +#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) +#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) +#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) +#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) +#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) +#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40000000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) +#define USART_CFG_IOMODE_MASK (0x10000U) +#define USART_CFG_IOMODE_SHIFT (16U) +#define USART_CFG_IOMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_IOMODE_SHIFT)) & USART_CFG_IOMODE_MASK) +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +/** Peripheral USART0 base address */ +#define USART0_BASE (0x40086000u) +/** Peripheral USART0 base pointer */ +#define USART0 ((USART_Type *)USART0_BASE) +/** Peripheral USART1 base address */ +#define USART1_BASE (0x40087000u) +/** Peripheral USART1 base pointer */ +#define USART1 ((USART_Type *)USART1_BASE) +/** Peripheral USART2 base address */ +#define USART2_BASE (0x40088000u) +/** Peripheral USART2 base pointer */ +#define USART2 ((USART_Type *)USART2_BASE) +/** Peripheral USART3 base address */ +#define USART3_BASE (0x40089000u) +/** Peripheral USART3 base pointer */ +#define USART3 ((USART_Type *)USART3_BASE) +/** Peripheral USART4 base address */ +#define USART4_BASE (0x4008A000u) +/** Peripheral USART4 base pointer */ +#define USART4 ((USART_Type *)USART4_BASE) +/** Peripheral USART5 base address */ +#define USART5_BASE (0x40096000u) +/** Peripheral USART5 base pointer */ +#define USART5 ((USART_Type *)USART5_BASE) +/** Peripheral USART6 base address */ +#define USART6_BASE (0x40097000u) +/** Peripheral USART6 base pointer */ +#define USART6 ((USART_Type *)USART6_BASE) +/** Peripheral USART7 base address */ +#define USART7_BASE (0x40098000u) +/** Peripheral USART7 base pointer */ +#define USART7 ((USART_Type *)USART7_BASE) +/** Array initializer of USART peripheral base addresses */ +#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } +/** Array initializer of USART peripheral base pointers */ +#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ +#define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x40084000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +/*! @{ */ +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status register. */ +/*! @{ */ +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture configuration register. */ +/*! @{ */ +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture clear register. */ +/*! @{ */ +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture register . */ +/*! @{ */ +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000E000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) +/*! @} */ + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT base address */ +#define WWDT_BASE (0x4000C000u) +/** Peripheral WWDT base pointer */ +#define WWDT ((WWDT_Type *)WWDT_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT } +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC54114_CM0PLUS_H_ */ + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus_features.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus_features.h new file mode 100644 index 00000000000..a13ad9a40b7 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm0plus_features.h @@ -0,0 +1,249 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2016-05-09 +** Build: b180327 +** +** Abstract: +** Chip specific module features. +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-05-09) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _LPC54114_cm0plus_FEATURES_H_ +#define _LPC54114_cm0plus_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) +/* @brief ASYNC_SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (1) +/* @brief DMIC availability on the SoC. */ +#define FSL_FEATURE_SOC_DMIC_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (8) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (8) +/* @brief SPIFI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPIFI_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* ADC module features */ + +/* @brief Do not has input select (register INSEL). */ +#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) +/* @brief Has startup register. */ +#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) +/* @brief Has ADTrim register */ +#define FSL_FEATURE_ADC_HAS_TRIM_REG (0) +/* @brief Has Calibration register. */ +#define FSL_FEATURE_ADC_HAS_CALIB_REG (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM7 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core. */ +#define FSL_FEATURE_MAILBOX_SIDE_B (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8) + +/* SYSCON module features */ + +/* @brief Pointer to ROM IAP entry functions */ +#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* USB module features */ + +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +#endif /* _LPC54114_cm0plus_FEATURES_H_ */ + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4.h new file mode 100644 index 00000000000..8b46983446b --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4.h @@ -0,0 +1,7116 @@ +/* +** ################################################################### +** Processors: LPC54114J256BD64_cm4 +** LPC54114J256UK49_cm4 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b180227 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC54114_cm4 +** +** The Clear BSD License +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-04-29) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file LPC54114_cm4.h + * @version 1.0 + * @date 2016-04-29 + * @brief CMSIS Peripheral Access Layer for LPC54114_cm4 + * + * CMSIS Peripheral Access Layer for LPC54114_cm4 + */ + +#ifndef _LPC54114_CM4_H_ +#define _LPC54114_CM4_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 56 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ + DMA0_IRQn = 1, /**< DMA controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ + ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ + ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ + ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ + DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */ + HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + IOH_IRQn = 30, /**< IOH */ + MAILBOX_IRQn = 31, /**< Mailbox interrupt (present on selected devices) */ + PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ + PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ + PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ + PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ + CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ + CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ + Reserved54_IRQn = 38, /**< Reserved interrupt */ + SPIFI0_IRQn = 39 /**< SPI flash interface */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_LPC54114_cm4.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestFlexcomm0Rx = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDmaRequestFlexcomm0Tx = 1U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDmaRequestFlexcomm1Rx = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDmaRequestFlexcomm1Tx = 3U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDmaRequestFlexcomm2Rx = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDmaRequestFlexcomm2Tx = 5U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDmaRequestFlexcomm3Rx = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDmaRequestFlexcomm3Tx = 7U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDmaRequestFlexcomm4Rx = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDmaRequestFlexcomm4Tx = 9U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDmaRequestFlexcomm5Rx = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDmaRequestFlexcomm5Tx = 11U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDmaRequestFlexcomm6Rx = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDmaRequestFlexcomm6Tx = 13U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDmaRequestFlexcomm7Rx = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDmaRequestFlexcomm7Tx = 15U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDmaRequestDMIC0 = 16U, /**< Digital microphone interface 0 */ + kDmaRequestDMIC1 = 17U, /**< Digital microphone interface 1 */ + kDmaRequestNoDMARequest18 = 18U, /**< No DMA request 18 */ + kDmaRequestNoDMARequest19 = 19U, /**< No DMA request 19 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ + __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ + __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ + __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ + uint8_t RESERVED_0[8]; + __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ + __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ + __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ + __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ + __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ + __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ + __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ + __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ + __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ + __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ +/*! @{ */ +#define ADC_CTRL_CLKDIV_MASK (0xFFU) +#define ADC_CTRL_CLKDIV_SHIFT (0U) +#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) +#define ADC_CTRL_ASYNMODE_MASK (0x100U) +#define ADC_CTRL_ASYNMODE_SHIFT (8U) +#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) +#define ADC_CTRL_RESOL_MASK (0x600U) +#define ADC_CTRL_RESOL_SHIFT (9U) +#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) +#define ADC_CTRL_BYPASSCAL_MASK (0x800U) +#define ADC_CTRL_BYPASSCAL_SHIFT (11U) +#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) +#define ADC_CTRL_TSAMP_MASK (0x7000U) +#define ADC_CTRL_TSAMP_SHIFT (12U) +#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) +/*! @} */ + +/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ +/*! @{ */ +#define ADC_INSEL_SEL_MASK (0x3U) +#define ADC_INSEL_SEL_SHIFT (0U) +#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) +/*! @} */ + +/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ +/*! @{ */ +#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) +#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) +#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) +#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) +#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) +#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) +#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) +#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) +#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) +#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) +#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) +#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) +#define ADC_SEQ_CTRL_START_MASK (0x4000000U) +#define ADC_SEQ_CTRL_START_SHIFT (26U) +#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) +#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) +#define ADC_SEQ_CTRL_BURST_SHIFT (27U) +#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) +#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) +#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) +#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) +#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) +#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) +#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) +#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) +#define ADC_SEQ_CTRL_MODE_SHIFT (30U) +#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) +#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) +#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) +#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) +/*! @} */ + +/* The count of ADC_SEQ_CTRL */ +#define ADC_SEQ_CTRL_COUNT (2U) + +/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ +/*! @{ */ +#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) +#define ADC_SEQ_GDAT_RESULT_SHIFT (4U) +#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) +#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) +#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) +#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) +#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) +#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) +#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) +#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) +#define ADC_SEQ_GDAT_CHN_SHIFT (26U) +#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) +#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) +#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) +#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) +#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) +#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) +#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) +/*! @} */ + +/* The count of ADC_SEQ_GDAT */ +#define ADC_SEQ_GDAT_COUNT (2U) + +/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ +/*! @{ */ +#define ADC_DAT_RESULT_MASK (0xFFF0U) +#define ADC_DAT_RESULT_SHIFT (4U) +#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) +#define ADC_DAT_THCMPRANGE_MASK (0x30000U) +#define ADC_DAT_THCMPRANGE_SHIFT (16U) +#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) +#define ADC_DAT_THCMPCROSS_MASK (0xC0000U) +#define ADC_DAT_THCMPCROSS_SHIFT (18U) +#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) +#define ADC_DAT_CHANNEL_MASK (0x3C000000U) +#define ADC_DAT_CHANNEL_SHIFT (26U) +#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) +#define ADC_DAT_OVERRUN_MASK (0x40000000U) +#define ADC_DAT_OVERRUN_SHIFT (30U) +#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) +#define ADC_DAT_DATAVALID_MASK (0x80000000U) +#define ADC_DAT_DATAVALID_SHIFT (31U) +#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) +/*! @} */ + +/* The count of ADC_DAT */ +#define ADC_DAT_COUNT (12U) + +/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +/*! @{ */ +#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) +#define ADC_THR0_LOW_THRLOW_SHIFT (4U) +#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) +/*! @} */ + +/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +/*! @{ */ +#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) +#define ADC_THR1_LOW_THRLOW_SHIFT (4U) +#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) +/*! @} */ + +/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +/*! @{ */ +#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) +#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) +#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) +/*! @} */ + +/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +/*! @{ */ +#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) +#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) +#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) +/*! @} */ + +/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ +/*! @{ */ +#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) +#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) +#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) +#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) +#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) +#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) +#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) +#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) +#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) +#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) +#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) +#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) +#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) +#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) +#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) +#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) +#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) +#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) +#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) +#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) +#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) +#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) +#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) +#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) +#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) +/*! @} */ + +/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ +/*! @{ */ +#define ADC_INTEN_SEQA_INTEN_MASK (0x1U) +#define ADC_INTEN_SEQA_INTEN_SHIFT (0U) +#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) +#define ADC_INTEN_SEQB_INTEN_MASK (0x2U) +#define ADC_INTEN_SEQB_INTEN_SHIFT (1U) +#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) +#define ADC_INTEN_OVR_INTEN_MASK (0x4U) +#define ADC_INTEN_OVR_INTEN_SHIFT (2U) +#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) +#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) +#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) +#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) +#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) +#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) +#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) +#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) +#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) +#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) +#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) +#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) +#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) +#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) +#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) +#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) +#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) +#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) +#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) +#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) +#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) +#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) +#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) +#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) +#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) +#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) +#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) +#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) +#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) +#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) +#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) +#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) +#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) +#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) +#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) +#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) +#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) +/*! @} */ + +/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ +/*! @{ */ +#define ADC_FLAGS_THCMP0_MASK (0x1U) +#define ADC_FLAGS_THCMP0_SHIFT (0U) +#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) +#define ADC_FLAGS_THCMP1_MASK (0x2U) +#define ADC_FLAGS_THCMP1_SHIFT (1U) +#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) +#define ADC_FLAGS_THCMP2_MASK (0x4U) +#define ADC_FLAGS_THCMP2_SHIFT (2U) +#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) +#define ADC_FLAGS_THCMP3_MASK (0x8U) +#define ADC_FLAGS_THCMP3_SHIFT (3U) +#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) +#define ADC_FLAGS_THCMP4_MASK (0x10U) +#define ADC_FLAGS_THCMP4_SHIFT (4U) +#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) +#define ADC_FLAGS_THCMP5_MASK (0x20U) +#define ADC_FLAGS_THCMP5_SHIFT (5U) +#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) +#define ADC_FLAGS_THCMP6_MASK (0x40U) +#define ADC_FLAGS_THCMP6_SHIFT (6U) +#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) +#define ADC_FLAGS_THCMP7_MASK (0x80U) +#define ADC_FLAGS_THCMP7_SHIFT (7U) +#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) +#define ADC_FLAGS_THCMP8_MASK (0x100U) +#define ADC_FLAGS_THCMP8_SHIFT (8U) +#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) +#define ADC_FLAGS_THCMP9_MASK (0x200U) +#define ADC_FLAGS_THCMP9_SHIFT (9U) +#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) +#define ADC_FLAGS_THCMP10_MASK (0x400U) +#define ADC_FLAGS_THCMP10_SHIFT (10U) +#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) +#define ADC_FLAGS_THCMP11_MASK (0x800U) +#define ADC_FLAGS_THCMP11_SHIFT (11U) +#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) +#define ADC_FLAGS_OVERRUN0_MASK (0x1000U) +#define ADC_FLAGS_OVERRUN0_SHIFT (12U) +#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) +#define ADC_FLAGS_OVERRUN1_MASK (0x2000U) +#define ADC_FLAGS_OVERRUN1_SHIFT (13U) +#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) +#define ADC_FLAGS_OVERRUN2_MASK (0x4000U) +#define ADC_FLAGS_OVERRUN2_SHIFT (14U) +#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) +#define ADC_FLAGS_OVERRUN3_MASK (0x8000U) +#define ADC_FLAGS_OVERRUN3_SHIFT (15U) +#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) +#define ADC_FLAGS_OVERRUN4_MASK (0x10000U) +#define ADC_FLAGS_OVERRUN4_SHIFT (16U) +#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) +#define ADC_FLAGS_OVERRUN5_MASK (0x20000U) +#define ADC_FLAGS_OVERRUN5_SHIFT (17U) +#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) +#define ADC_FLAGS_OVERRUN6_MASK (0x40000U) +#define ADC_FLAGS_OVERRUN6_SHIFT (18U) +#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) +#define ADC_FLAGS_OVERRUN7_MASK (0x80000U) +#define ADC_FLAGS_OVERRUN7_SHIFT (19U) +#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) +#define ADC_FLAGS_OVERRUN8_MASK (0x100000U) +#define ADC_FLAGS_OVERRUN8_SHIFT (20U) +#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) +#define ADC_FLAGS_OVERRUN9_MASK (0x200000U) +#define ADC_FLAGS_OVERRUN9_SHIFT (21U) +#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) +#define ADC_FLAGS_OVERRUN10_MASK (0x400000U) +#define ADC_FLAGS_OVERRUN10_SHIFT (22U) +#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) +#define ADC_FLAGS_OVERRUN11_MASK (0x800000U) +#define ADC_FLAGS_OVERRUN11_SHIFT (23U) +#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) +#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) +#define ADC_FLAGS_SEQA_OVR_SHIFT (24U) +#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) +#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) +#define ADC_FLAGS_SEQB_OVR_SHIFT (25U) +#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) +#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) +#define ADC_FLAGS_SEQA_INT_SHIFT (28U) +#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) +#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) +#define ADC_FLAGS_SEQB_INT_SHIFT (29U) +#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) +#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) +#define ADC_FLAGS_THCMP_INT_SHIFT (30U) +#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) +#define ADC_FLAGS_OVR_INT_MASK (0x80000000U) +#define ADC_FLAGS_OVR_INT_SHIFT (31U) +#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) +/*! @} */ + +/*! @name STARTUP - ADC Startup register. */ +/*! @{ */ +#define ADC_STARTUP_ADC_ENA_MASK (0x1U) +#define ADC_STARTUP_ADC_ENA_SHIFT (0U) +#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) +#define ADC_STARTUP_ADC_INIT_MASK (0x2U) +#define ADC_STARTUP_ADC_INIT_SHIFT (1U) +#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) +/*! @} */ + +/*! @name CALIB - ADC Calibration register. */ +/*! @{ */ +#define ADC_CALIB_CALIB_MASK (0x1U) +#define ADC_CALIB_CALIB_SHIFT (0U) +#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) +#define ADC_CALIB_CALREQD_MASK (0x2U) +#define ADC_CALIB_CALREQD_SHIFT (1U) +#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) +#define ADC_CALIB_CALVALUE_MASK (0x1FCU) +#define ADC_CALIB_CALVALUE_SHIFT (2U) +#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400A0000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } +#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ASYNC_SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer + * @{ + */ + +/** ASYNC_SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ + __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ + __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ + __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ + __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ +} ASYNC_SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- ASYNC_SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks + * @{ + */ + +/*! @name ASYNCPRESETCTRL - Async peripheral reset control */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) +/*! @} */ + +/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) +/*! @} */ + +/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ASYNC_SYSCON_Register_Masks */ + + +/* ASYNC_SYSCON - Peripheral instance base addresses */ +/** Peripheral ASYNC_SYSCON base address */ +#define ASYNC_SYSCON_BASE (0x40040000u) +/** Peripheral ASYNC_SYSCON base pointer */ +#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) +/** Array initializer of ASYNC_SYSCON peripheral base addresses */ +#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } +/** Array initializer of ASYNC_SYSCON peripheral base pointers */ +#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } + +/*! + * @} + */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +/*! @{ */ +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ + +/*! @name SEED - CRC seed register */ +/*! @{ */ +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ + +/*! @name SUM - CRC checksum register */ +/*! @{ */ +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ + +/*! @name WR_DATA - CRC data register */ +/*! @{ */ +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC_ENGINE base address */ +#define CRC_ENGINE_BASE (0x40095000u) +/** Peripheral CRC_ENGINE base pointer */ +#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC_ENGINE_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC_ENGINE } + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ + +/*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ +/*! @{ */ +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ +/*! @{ */ +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ +/*! @{ */ +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ +/*! @{ */ +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) +/*! @} */ + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ +/*! @{ */ +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40008000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40009000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40028000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40048000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40049000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[1]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[20]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +/*! @{ */ +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status. */ +/*! @{ */ +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (20U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (20U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (20U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40082000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMIC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer + * @{ + */ + +/** DMIC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x100 */ + __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */ + __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */ + __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */ + __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */ + __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */ + uint8_t RESERVED_0[108]; + __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */ + __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */ + __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */ + __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */ + __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */ + uint8_t RESERVED_1[108]; + } CHANNEL[2]; + uint8_t RESERVED_0[3328]; + __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ + uint8_t RESERVED_1[8]; + __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */ + __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */ + uint8_t RESERVED_2[108]; + __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */ + __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */ + __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */ + __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */ + __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */ + __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */ + __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */ + uint8_t RESERVED_3[96]; + __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */ +} DMIC_Type; + +/* ---------------------------------------------------------------------------- + -- DMIC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMIC_Register_Masks DMIC Register Masks + * @{ + */ + +/*! @name CHANNEL_OSR - Oversample Rate register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) +#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) +#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_OSR */ +#define DMIC_CHANNEL_OSR_COUNT (2U) + +/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_DIVHFCLK */ +#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) + +/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ +/*! @{ */ +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_PREAC2FSCOEF */ +#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) + +/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ +/*! @{ */ +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_PREAC4FSCOEF */ +#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) + +/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ +/*! @{ */ +#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) +#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) +#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_GAINSHIFT */ +#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) + +/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) +#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) +#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) +#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) +#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_FIFO_CTRL */ +#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) + +/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) +#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) +#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_FIFO_STATUS */ +#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) + +/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) +#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) +#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_FIFO_DATA */ +#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) + +/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_PHY_CTRL */ +#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) + +/*! @name CHANNEL_DC_CTRL - DC Control register 0 */ +/*! @{ */ +#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) +#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) +#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) +#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) +#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) +#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) +/*! @} */ + +/* The count of DMIC_CHANNEL_DC_CTRL */ +#define DMIC_CHANNEL_DC_CTRL_COUNT (2U) + +/*! @name CHANEN - Channel Enable register */ +/*! @{ */ +#define DMIC_CHANEN_EN_CH0_MASK (0x1U) +#define DMIC_CHANEN_EN_CH0_SHIFT (0U) +#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) +#define DMIC_CHANEN_EN_CH1_MASK (0x2U) +#define DMIC_CHANEN_EN_CH1_SHIFT (1U) +#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) +/*! @} */ + +/*! @name IOCFG - I/O Configuration register */ +/*! @{ */ +#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) +#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) +#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) +#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U) +#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U) +#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK) +#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) +#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) +#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) +/*! @} */ + +/*! @name USE2FS - Use 2FS register */ +/*! @{ */ +#define DMIC_USE2FS_USE2FS_MASK (0x1U) +#define DMIC_USE2FS_USE2FS_SHIFT (0U) +#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) +/*! @} */ + +/*! @name HWVADGAIN - HWVAD input gain register */ +/*! @{ */ +#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) +#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) +#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) +/*! @} */ + +/*! @name HWVADHPFS - HWVAD filter control register */ +/*! @{ */ +#define DMIC_HWVADHPFS_HPFS_MASK (0x3U) +#define DMIC_HWVADHPFS_HPFS_SHIFT (0U) +#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) +/*! @} */ + +/*! @name HWVADST10 - HWVAD control register */ +/*! @{ */ +#define DMIC_HWVADST10_ST10_MASK (0x1U) +#define DMIC_HWVADST10_ST10_SHIFT (0U) +#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) +/*! @} */ + +/*! @name HWVADRSTT - HWVAD filter reset register */ +/*! @{ */ +#define DMIC_HWVADRSTT_RSTT_MASK (0x1U) +#define DMIC_HWVADRSTT_RSTT_SHIFT (0U) +#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) +/*! @} */ + +/*! @name HWVADTHGN - HWVAD noise estimator gain register */ +/*! @{ */ +#define DMIC_HWVADTHGN_THGN_MASK (0xFU) +#define DMIC_HWVADTHGN_THGN_SHIFT (0U) +#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) +/*! @} */ + +/*! @name HWVADTHGS - HWVAD signal estimator gain register */ +/*! @{ */ +#define DMIC_HWVADTHGS_THGS_MASK (0xFU) +#define DMIC_HWVADTHGS_THGS_SHIFT (0U) +#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) +/*! @} */ + +/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ +/*! @{ */ +#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) +#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) +#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) +/*! @} */ + +/*! @name ID - Module Identification register */ +/*! @{ */ +#define DMIC_ID_ID_MASK (0xFFFFFFFFU) +#define DMIC_ID_ID_SHIFT (0U) +#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DMIC_Register_Masks */ + + +/* DMIC - Peripheral instance base addresses */ +/** Peripheral DMIC0 base address */ +#define DMIC0_BASE (0x40090000u) +/** Peripheral DMIC0 base pointer */ +#define DMIC0 ((DMIC_Type *)DMIC0_BASE) +/** Array initializer of DMIC peripheral base addresses */ +#define DMIC_BASE_ADDRS { DMIC0_BASE } +/** Array initializer of DMIC peripheral base pointers */ +#define DMIC_BASE_PTRS { DMIC0 } +/** Interrupt vectors for the DMIC peripheral type */ +#define DMIC_IRQS { DMIC0_IRQn } +#define DMIC_HWVAD_IRQS { HWVAD0_IRQn } + +/*! + * @} + */ /* end of group DMIC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral identification register. */ +/*! @{ */ +#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) +#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) +#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) +#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) +#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) +#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +/** Peripheral FLEXCOMM0 base address */ +#define FLEXCOMM0_BASE (0x40086000u) +/** Peripheral FLEXCOMM0 base pointer */ +#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) +/** Peripheral FLEXCOMM1 base address */ +#define FLEXCOMM1_BASE (0x40087000u) +/** Peripheral FLEXCOMM1 base pointer */ +#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) +/** Peripheral FLEXCOMM2 base address */ +#define FLEXCOMM2_BASE (0x40088000u) +/** Peripheral FLEXCOMM2 base pointer */ +#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) +/** Peripheral FLEXCOMM3 base address */ +#define FLEXCOMM3_BASE (0x40089000u) +/** Peripheral FLEXCOMM3 base pointer */ +#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) +/** Peripheral FLEXCOMM4 base address */ +#define FLEXCOMM4_BASE (0x4008A000u) +/** Peripheral FLEXCOMM4 base pointer */ +#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) +/** Peripheral FLEXCOMM5 base address */ +#define FLEXCOMM5_BASE (0x40096000u) +/** Peripheral FLEXCOMM5 base pointer */ +#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) +/** Peripheral FLEXCOMM6 base address */ +#define FLEXCOMM6_BASE (0x40097000u) +/** Peripheral FLEXCOMM6 base pointer */ +#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) +/** Peripheral FLEXCOMM7 base address */ +#define FLEXCOMM7_BASE (0x40098000u) +/** Peripheral FLEXCOMM7 base pointer */ +#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) +/** Array initializer of FLEXCOMM peripheral base addresses */ +#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE } +/** Array initializer of FLEXCOMM peripheral base pointers */ +#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7 } +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +/** Peripheral GINT0 base address */ +#define GINT0_BASE (0x40002000u) +/** Peripheral GINT0 base pointer */ +#define GINT0 ((GINT_Type *)GINT0_BASE) +/** Peripheral GINT1 base address */ +#define GINT1_BASE (0x40003000u) +/** Peripheral GINT1 base pointer */ +#define GINT1 ((GINT_Type *)GINT1_BASE) +/** Array initializer of GINT peripheral base addresses */ +#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } +/** Array initializer of GINT peripheral base pointers */ +#define GINT_BASE_PTRS { GINT0, GINT1 } +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[4032]; + __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3840]; + __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[120]; + __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[120]; + __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[120]; + __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[120]; + __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[120]; + __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[120]; + __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[120]; + __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ +/*! @{ */ +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_B */ +#define GPIO_B_COUNT (2U) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ +/*! @{ */ +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_W */ +#define GPIO_W_COUNT (2U) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers */ +/*! @{ */ +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (2U) + +/*! @name MASK - Mask register */ +/*! @{ */ +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (2U) + +/*! @name PIN - Port pin register */ +/*! @{ */ +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (2U) + +/*! @name MPIN - Masked port register */ +/*! @{ */ +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (2U) + +/*! @name SET - Write: Set register for port Read: output bits for port */ +/*! @{ */ +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (2U) + +/*! @name CLR - Clear port */ +/*! @{ */ +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (2U) + +/*! @name NOT - Toggle port */ +/*! @{ */ +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (2U) + +/*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (2U) + +/*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (2U) + +/*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (2U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO base address */ +#define GPIO_BASE (0x4008C000u) +/** Peripheral GPIO base pointer */ +#define GPIO ((GPIO_Type *)GPIO_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +/*! @{ */ +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master control register. */ +/*! @{ */ +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave control register. */ +/*! @{ */ +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave address register. */ +/*! @{ */ +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C0 base address */ +#define I2C0_BASE (0x40086000u) +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_Type *)I2C0_BASE) +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x40087000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x40088000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Peripheral I2C3 base address */ +#define I2C3_BASE (0x40089000u) +/** Peripheral I2C3 base pointer */ +#define I2C3 ((I2C_Type *)I2C3_BASE) +/** Peripheral I2C4 base address */ +#define I2C4_BASE (0x4008A000u) +/** Peripheral I2C4 base pointer */ +#define I2C4 ((I2C_Type *)I2C4_BASE) +/** Peripheral I2C5 base address */ +#define I2C5_BASE (0x40096000u) +/** Peripheral I2C5 base pointer */ +#define I2C5 ((I2C_Type *)I2C5_BASE) +/** Peripheral I2C6 base address */ +#define I2C6_BASE (0x40097000u) +/** Peripheral I2C6 base pointer */ +#define I2C6 ((I2C_Type *)I2C6_BASE) +/** Peripheral I2C7 base address */ +#define I2C7_BASE (0x40098000u) +/** Peripheral I2C7 base pointer */ +#define I2C7 ((I2C_Type *)I2C7_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + uint8_t RESERVED_2[480]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) +#define I2S_CFG1_PDMDATA_MASK (0x800U) +#define I2S_CFG1_PDMDATA_SHIFT (11U) +#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) +#define I2S_FIFOCFG_TXI2SSE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SSE0_SHIFT (2U) +#define I2S_FIFOCFG_TXI2SSE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SSE0_SHIFT)) & I2S_FIFOCFG_TXI2SSE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) +#define I2S_FIFOCFG_POPDBG_SHIFT (18U) +#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S0 base address */ +#define I2S0_BASE (0x40097000u) +/** Peripheral I2S0 base pointer */ +#define I2S0 ((I2S_Type *)I2S0_BASE) +/** Peripheral I2S1 base address */ +#define I2S1_BASE (0x40098000u) +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_Type *)I2S1_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { I2S0, I2S1 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[192]; + __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA_ITRIG_INMUX[22]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_1[40]; + __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ +#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (8U) + +/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ +/*! @{ */ +#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA_ITRIG_INMUX */ +#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U) + +/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ +/*! @{ */ +#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA_OTRIG_INMUX */ +#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX base address */ +#define INPUTMUX_BASE (0x40005000u) +/** Peripheral INPUTMUX base pointer */ +#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX } + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ +#define IOCON_PIO_FUNC_MASK (0x7U) +#define IOCON_PIO_FUNC_SHIFT (0U) +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) +#define IOCON_PIO_MODE_MASK (0x18U) +#define IOCON_PIO_MODE_SHIFT (3U) +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) +#define IOCON_PIO_I2CSLEW_MASK (0x20U) +#define IOCON_PIO_I2CSLEW_SHIFT (5U) +#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) +#define IOCON_PIO_INVERT_MASK (0x40U) +#define IOCON_PIO_INVERT_SHIFT (6U) +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) +#define IOCON_PIO_DIGIMODE_MASK (0x80U) +#define IOCON_PIO_DIGIMODE_SHIFT (7U) +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) +#define IOCON_PIO_FILTEROFF_MASK (0x100U) +#define IOCON_PIO_FILTEROFF_SHIFT (8U) +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) +#define IOCON_PIO_I2CDRIVE_MASK (0x200U) +#define IOCON_PIO_I2CDRIVE_SHIFT (9U) +#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) +#define IOCON_PIO_SLEW_MASK (0x200U) +#define IOCON_PIO_SLEW_SHIFT (9U) +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) +#define IOCON_PIO_I2CFILTER_MASK (0x400U) +#define IOCON_PIO_I2CFILTER_SHIFT (10U) +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +#define IOCON_PIO_OD_MASK (0x400U) +#define IOCON_PIO_OD_SHIFT (10U) +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (2U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +/** Peripheral IOCON base address */ +#define IOCON_BASE (0x40001000u) +/** Peripheral IOCON base pointer */ +#define IOCON ((IOCON_Type *)IOCON_BASE) +/** Array initializer of IOCON peripheral base addresses */ +#define IOCON_BASE_ADDRS { IOCON_BASE } +/** Array initializer of IOCON peripheral base pointers */ +#define IOCON_BASE_PTRS { IOCON } + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer + * @{ + */ + +/** MAILBOX - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ + __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ + __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } MBOXIRQ[2]; + uint8_t RESERVED_0[216]; + __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ +} MAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- MAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks + * @{ + */ + +/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQ */ +#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) + +/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQSET */ +#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) + +/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQCLR */ +#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) + +/*! @name MUTEX - Mutual exclusion register[1] */ +/*! @{ */ +#define MAILBOX_MUTEX_EX_MASK (0x1U) +#define MAILBOX_MUTEX_EX_SHIFT (0U) +#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MAILBOX_Register_Masks */ + + +/* MAILBOX - Peripheral instance base addresses */ +/** Peripheral MAILBOX base address */ +#define MAILBOX_BASE (0x4008B000u) +/** Peripheral MAILBOX base pointer */ +#define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) +/** Array initializer of MAILBOX peripheral base addresses */ +#define MAILBOX_BASE_ADDRS { MAILBOX_BASE } +/** Array initializer of MAILBOX peripheral base pointers */ +#define MAILBOX_BASE_PTRS { MAILBOX } +/** Interrupt vectors for the MAILBOX peripheral type */ +#define MAILBOX_IRQS { MAILBOX_IRQn } + +/*! + * @} + */ /* end of group MAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +/** Peripheral MRT0 base address */ +#define MRT0_BASE (0x4000D000u) +/** Peripheral MRT0 base pointer */ +#define MRT0 ((MRT_Type *)MRT0_BASE) +/** Array initializer of MRT peripheral base addresses */ +#define MRT_BASE_ADDRS { MRT0_BASE } +/** Array initializer of MRT peripheral base pointers */ +#define MRT_BASE_PTRS { MRT0 } +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin interrupt status register */ +/*! @{ */ +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +/** Peripheral PINT base address */ +#define PINT_BASE (0x40004000u) +/** Peripheral PINT base pointer */ +#define PINT ((PINT_Type *)PINT_BASE) +/** Array initializer of PINT peripheral base addresses */ +#define PINT_BASE_ADDRS { PINT_BASE } +/** Array initializer of PINT peripheral base pointers */ +#define PINT_BASE_PTRS { PINT } +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +/*! @{ */ +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) +#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) +#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) +#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) +/*! @} */ + +/*! @name MATCH - RTC match register */ +/*! @{ */ +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ + +/*! @name COUNT - RTC counter register */ +/*! @{ */ +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ + +/*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE (0x4002C000u) +/** Peripheral RTC base pointer */ +#define RTC ((RTC_Type *)RTC_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + uint8_t RESERVED_0[40]; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_2[216]; + union { /* offset: 0x200 */ + __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_3[216]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EVENT[10]; + uint8_t RESERVED_4[432]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[8]; + uint8_t RESERVED_5[700]; + uint32_t MODULECONTENT; /**< Reserved, offset: 0x7FC */ +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +/*! @{ */ +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) +#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) +#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) +#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT control register */ +/*! @{ */ +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMIT - SCT limit event select register */ +/*! @{ */ +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALT - SCT halt event select register */ +/*! @{ */ +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOP - SCT stop event select register */ +/*! @{ */ +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name START - SCT start event select register */ +/*! @{ */ +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name COUNT - SCT counter register */ +/*! @{ */ +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATE - SCT state register */ +/*! @{ */ +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - SCT input register */ +/*! @{ */ +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ + +/*! @name OUTPUT - SCT output register */ +/*! @{ */ +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ + +/*! @name RES - SCT conflict resolution register */ +/*! @{ */ +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ + +/*! @name DMA0REQUEST - SCT DMA request 0 register */ +/*! @{ */ +#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) +#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) +#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) +#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) +#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) +#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) +#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) +#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) +#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) +/*! @} */ + +/*! @name DMA1REQUEST - SCT DMA request 1 register */ +/*! @{ */ +#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) +#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) +#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) +#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) +#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) +#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) +#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) +#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) +#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ + +/*! @name EVFLAG - SCT event flag register */ +/*! @{ */ +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ + +/*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ + +/*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name SCTCAP - SCT capture register of capture channel */ +/*! @{ */ +#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) +#define SCT_SCTCAP_CAPn_L_SHIFT (0U) +#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) +#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAP_CAPn_H_SHIFT (16U) +#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAP */ +#define SCT_SCTCAP_COUNT (10U) + +/*! @name SCTMATCH - SCT match value register of match channels */ +/*! @{ */ +#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) +#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) +#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) +#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTMATCH */ +#define SCT_SCTMATCH_COUNT (10U) + +/*! @name SCTCAPCTRL - SCT capture control register */ +/*! @{ */ +#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) +#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) +#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) +#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAPCTRL */ +#define SCT_SCTCAPCTRL_COUNT (10U) + +/*! @name SCTMATCHREL - SCT match reload value register */ +/*! @{ */ +#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) +#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) +#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) +#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTMATCHREL */ +#define SCT_SCTMATCHREL_COUNT (10U) + +/*! @name EVENT_STATE - SCT event state register 0 */ +/*! @{ */ +#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) +#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EVENT_STATE */ +#define SCT_EVENT_STATE_COUNT (10U) + +/*! @name EVENT_CTRL - SCT event control register 0 */ +/*! @{ */ +#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) +#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) +#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) +#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) +#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) +#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) +#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) +#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) +#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) +#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) +#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) +#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) +#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) +#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) +#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) +#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) +#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) +#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) +#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) +#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) +#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) +#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EVENT_CTRL */ +#define SCT_EVENT_CTRL_COUNT (10U) + +/*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (8U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (8U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +/** Peripheral SCT0 base address */ +#define SCT0_BASE (0x40085000u) +/** Peripheral SCT0 base pointer */ +#define SCT0 ((SCT_Type *)SCT0_BASE) +/** Array initializer of SCT peripheral base addresses */ +#define SCT_BASE_ADDRS { SCT0_BASE } +/** Array initializer of SCT peripheral base pointers */ +#define SCT_BASE_PTRS { SCT0 } +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +/*! @{ */ +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - SPI Delay register */ +/*! @{ */ +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - SPI clock Divider */ +/*! @{ */ +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +/** Peripheral SPI0 base address */ +#define SPI0_BASE (0x40086000u) +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) +/** Peripheral SPI1 base address */ +#define SPI1_BASE (0x40087000u) +/** Peripheral SPI1 base pointer */ +#define SPI1 ((SPI_Type *)SPI1_BASE) +/** Peripheral SPI2 base address */ +#define SPI2_BASE (0x40088000u) +/** Peripheral SPI2 base pointer */ +#define SPI2 ((SPI_Type *)SPI2_BASE) +/** Peripheral SPI3 base address */ +#define SPI3_BASE (0x40089000u) +/** Peripheral SPI3 base pointer */ +#define SPI3 ((SPI_Type *)SPI3_BASE) +/** Peripheral SPI4 base address */ +#define SPI4_BASE (0x4008A000u) +/** Peripheral SPI4 base pointer */ +#define SPI4 ((SPI_Type *)SPI4_BASE) +/** Peripheral SPI5 base address */ +#define SPI5_BASE (0x40096000u) +/** Peripheral SPI5 base pointer */ +#define SPI5 ((SPI_Type *)SPI5_BASE) +/** Peripheral SPI6 base address */ +#define SPI6_BASE (0x40097000u) +/** Peripheral SPI6 base pointer */ +#define SPI6 ((SPI_Type *)SPI6_BASE) +/** Peripheral SPI7 base address */ +#define SPI7_BASE (0x40098000u) +/** Peripheral SPI7 base pointer */ +#define SPI7 ((SPI_Type *)SPI7_BASE) +/** Array initializer of SPI peripheral base addresses */ +#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE } +/** Array initializer of SPI peripheral base pointers */ +#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPIFI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer + * @{ + */ + +/** SPIFI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */ + __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */ + __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */ + __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */ + __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */ + __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */ + __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */ + __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */ +} SPIFI_Type; + +/* ---------------------------------------------------------------------------- + -- SPIFI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPIFI_Register_Masks SPIFI Register Masks + * @{ + */ + +/*! @name CTRL - SPIFI control register */ +/*! @{ */ +#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) +#define SPIFI_CTRL_TIMEOUT_SHIFT (0U) +#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) +#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U) +#define SPIFI_CTRL_CSHIGH_SHIFT (16U) +#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK) +#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U) +#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U) +#define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK) +#define SPIFI_CTRL_INTEN_MASK (0x400000U) +#define SPIFI_CTRL_INTEN_SHIFT (22U) +#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK) +#define SPIFI_CTRL_MODE3_MASK (0x800000U) +#define SPIFI_CTRL_MODE3_SHIFT (23U) +#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK) +#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U) +#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U) +#define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK) +#define SPIFI_CTRL_DUAL_MASK (0x10000000U) +#define SPIFI_CTRL_DUAL_SHIFT (28U) +#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK) +#define SPIFI_CTRL_RFCLK_MASK (0x20000000U) +#define SPIFI_CTRL_RFCLK_SHIFT (29U) +#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK) +#define SPIFI_CTRL_FBCLK_MASK (0x40000000U) +#define SPIFI_CTRL_FBCLK_SHIFT (30U) +#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK) +#define SPIFI_CTRL_DMAEN_MASK (0x80000000U) +#define SPIFI_CTRL_DMAEN_SHIFT (31U) +#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) +/*! @} */ + +/*! @name CMD - SPIFI command register */ +/*! @{ */ +#define SPIFI_CMD_DATALEN_MASK (0x3FFFU) +#define SPIFI_CMD_DATALEN_SHIFT (0U) +#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) +#define SPIFI_CMD_POLL_MASK (0x4000U) +#define SPIFI_CMD_POLL_SHIFT (14U) +#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK) +#define SPIFI_CMD_DOUT_MASK (0x8000U) +#define SPIFI_CMD_DOUT_SHIFT (15U) +#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK) +#define SPIFI_CMD_INTLEN_MASK (0x70000U) +#define SPIFI_CMD_INTLEN_SHIFT (16U) +#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK) +#define SPIFI_CMD_FIELDFORM_MASK (0x180000U) +#define SPIFI_CMD_FIELDFORM_SHIFT (19U) +#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK) +#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U) +#define SPIFI_CMD_FRAMEFORM_SHIFT (21U) +#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK) +#define SPIFI_CMD_OPCODE_MASK (0xFF000000U) +#define SPIFI_CMD_OPCODE_SHIFT (24U) +#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) +/*! @} */ + +/*! @name ADDR - SPIFI address register */ +/*! @{ */ +#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) +#define SPIFI_ADDR_ADDRESS_SHIFT (0U) +#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name IDATA - SPIFI intermediate data register */ +/*! @{ */ +#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) +#define SPIFI_IDATA_IDATA_SHIFT (0U) +#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) +/*! @} */ + +/*! @name CLIMIT - SPIFI limit register */ +/*! @{ */ +#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) +#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) +#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) +/*! @} */ + +/*! @name DATA - SPIFI data register */ +/*! @{ */ +#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) +#define SPIFI_DATA_DATA_SHIFT (0U) +#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) +/*! @} */ + +/*! @name MCMD - SPIFI memory command register */ +/*! @{ */ +#define SPIFI_MCMD_POLL_MASK (0x4000U) +#define SPIFI_MCMD_POLL_SHIFT (14U) +#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) +#define SPIFI_MCMD_DOUT_MASK (0x8000U) +#define SPIFI_MCMD_DOUT_SHIFT (15U) +#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK) +#define SPIFI_MCMD_INTLEN_MASK (0x70000U) +#define SPIFI_MCMD_INTLEN_SHIFT (16U) +#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK) +#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U) +#define SPIFI_MCMD_FIELDFORM_SHIFT (19U) +#define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK) +#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U) +#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U) +#define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK) +#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) +#define SPIFI_MCMD_OPCODE_SHIFT (24U) +#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) +/*! @} */ + +/*! @name STAT - SPIFI status register */ +/*! @{ */ +#define SPIFI_STAT_MCINIT_MASK (0x1U) +#define SPIFI_STAT_MCINIT_SHIFT (0U) +#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) +#define SPIFI_STAT_CMD_MASK (0x2U) +#define SPIFI_STAT_CMD_SHIFT (1U) +#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK) +#define SPIFI_STAT_RESET_MASK (0x10U) +#define SPIFI_STAT_RESET_SHIFT (4U) +#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK) +#define SPIFI_STAT_INTRQ_MASK (0x20U) +#define SPIFI_STAT_INTRQ_SHIFT (5U) +#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK) +#define SPIFI_STAT_VERSION_MASK (0xFF000000U) +#define SPIFI_STAT_VERSION_SHIFT (24U) +#define SPIFI_STAT_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPIFI_Register_Masks */ + + +/* SPIFI - Peripheral instance base addresses */ +/** Peripheral SPIFI0 base address */ +#define SPIFI0_BASE (0x40080000u) +/** Peripheral SPIFI0 base pointer */ +#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE) +/** Array initializer of SPIFI peripheral base addresses */ +#define SPIFI_BASE_ADDRS { SPIFI0_BASE } +/** Array initializer of SPIFI peripheral base pointers */ +#define SPIFI_BASE_PTRS { SPIFI0 } +/** Interrupt vectors for the SPIFI peripheral type */ +#define SPIFI_IRQS { SPIFI0_IRQn } + +/*! + * @} + */ /* end of group SPIFI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ + uint8_t RESERVED_1[44]; + __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ + uint8_t RESERVED_3[112]; + __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ + uint8_t RESERVED_5[40]; + __IO uint32_t PRESETCTRL[2]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_6[24]; + __O uint32_t PRESETCTRLSET[2]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_7[24]; + __O uint32_t PRESETCTRLCLR[2]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_8[168]; + __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t AHBCLKCTRL[2]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __O uint32_t AHBCLKCTRLSET[2]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_11[24]; + __O uint32_t AHBCLKCTRLCLR[2]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_12[56]; + __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ + __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ + uint8_t RESERVED_13[4]; + __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ + uint8_t RESERVED_14[12]; + __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */ + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USBCLKSEL; /**< USB clock source select, offset: 0x2A8 */ + uint8_t RESERVED_15[4]; + __IO uint32_t FXCOMCLKSEL[8]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */ + uint8_t RESERVED_16[16]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_17[4]; + __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ + __IO uint32_t DMICCLKSEL; /**< Digital microphone (D-Mic) subsystem clock select, offset: 0x2EC */ + uint8_t RESERVED_18[16]; + __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ + __IO uint32_t TRACECLKDIV; /**< Trace clock divider, offset: 0x304 */ + uint8_t RESERVED_19[120]; + __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + uint8_t RESERVED_20[8]; + __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */ + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USBCLKDIV; /**< USB clock divider, offset: 0x398 */ + uint8_t RESERVED_21[4]; + __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ + uint8_t RESERVED_22[4]; + __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */ + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_23[80]; + __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ + uint8_t RESERVED_24[8]; + __IO uint32_t USBCLKCTRL; /**< USB clock control, offset: 0x40C */ + __IO uint32_t USBCLKSTAT; /**< USB clock status, offset: 0x410 */ + uint8_t RESERVED_25[4]; + __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ + uint8_t RESERVED_26[4]; + __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ + uint8_t RESERVED_27[220]; + __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ + uint8_t RESERVED_28[4]; + __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ + __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ + uint8_t RESERVED_29[112]; + __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x580 */ + __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ + __IO uint32_t SYSPLLNDEC; /**< PLL N decoder, offset: 0x588 */ + __IO uint32_t SYSPLLPDEC; /**< PLL P decoder, offset: 0x58C */ + __IO uint32_t SYSPLLSSCTRL0; /**< PLL spread spectrum control 0, offset: 0x590 */ + __IO uint32_t SYSPLLSSCTRL1; /**< PLL spread spectrum control 1, offset: 0x594 */ + uint8_t RESERVED_30[104]; + __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register n, array offset: 0x600, array step: 0x4 */ + uint8_t RESERVED_31[8]; + __IO uint32_t PDRUNCFG[2]; /**< Power configuration register n, array offset: 0x610, array step: 0x4 */ + uint8_t RESERVED_32[8]; + __O uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFGn, array offset: 0x620, array step: 0x4 */ + uint8_t RESERVED_33[8]; + __O uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFGn, array offset: 0x630, array step: 0x4 */ + uint8_t RESERVED_34[72]; + __IO uint32_t STARTERP[2]; /**< Start logic n wake-up enable register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_35[24]; + __O uint32_t STARTERSET[2]; /**< Set bits in STARTERn, array offset: 0x6A0, array step: 0x4 */ + uint8_t RESERVED_36[24]; + __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTERn, array offset: 0x6C0, array step: 0x4 */ + uint8_t RESERVED_37[184]; + __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ + uint8_t RESERVED_38[124]; + __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ + __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ + __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ + __I uint32_t CPSTAT; /**< Coprocessor Status, offset: 0x80C */ + uint8_t RESERVED_39[1524]; + __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */ + uint8_t RESERVED_40[492]; + __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ + __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ + uint8_t RESERVED_41[127044]; + __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name AHBMATPRIO - AHB multilayer matrix priority control */ +/*! @{ */ +#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) +#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) +#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) +#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) +#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) +#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) +#define SYSCON_AHBMATPRIO_PRI_M0_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_M0_SHIFT (6U) +#define SYSCON_AHBMATPRIO_PRI_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_M0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_M0_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_SHIFT (8U) +#define SYSCON_AHBMATPRIO_PRI_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_MASK) +#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U) +#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) +/*! @} */ + +/*! @name SYSTCKCAL - System tick counter calibration */ +/*! @{ */ +#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) +#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) +#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) +#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) +#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) +#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) +#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ +#define SYSCON_NMISRC_IRQM4_MASK (0x3FU) +#define SYSCON_NMISRC_IRQM4_SHIFT (0U) +#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) +#define SYSCON_NMISRC_IRQM0_MASK (0x3F00U) +#define SYSCON_NMISRC_IRQM0_SHIFT (8U) +#define SYSCON_NMISRC_IRQM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM0_SHIFT)) & SYSCON_NMISRC_IRQM0_MASK) +#define SYSCON_NMISRC_NMIENM0_MASK (0x40000000U) +#define SYSCON_NMISRC_NMIENM0_SHIFT (30U) +#define SYSCON_NMISRC_NMIENM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM0_SHIFT)) & SYSCON_NMISRC_NMIENM0_MASK) +#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENM4_SHIFT (31U) +#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) +/*! @} */ + +/*! @name ASYNCAPBCTRL - Asynchronous APB Control */ +/*! @{ */ +#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) +#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) +#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) +/*! @} */ + +/*! @name PIOPORCAP - POR captured value of port n */ +/*! @{ */ +#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) +#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) +#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) +/*! @} */ + +/* The count of SYSCON_PIOPORCAP */ +#define SYSCON_PIOPORCAP_COUNT (2U) + +/*! @name PIORESCAP - Reset captured value of port n */ +/*! @{ */ +#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) +#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) +#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) +/*! @} */ + +/* The count of SYSCON_PIORESCAP */ +#define SYSCON_PIORESCAP_COUNT (2U) + +/*! @name PRESETCTRL - Peripheral reset control n */ +/*! @{ */ +#define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U) +#define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK) +#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) +#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) +#define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) +#define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) +#define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) +#define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) +#define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U) +#define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK) +#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) +#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) +#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) +#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) +#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) +#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) +#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) +#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) +#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) +#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) +#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) +#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) +#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) +#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) +#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) +#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) +#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) +#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) +#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) +#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) +#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) +#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) +#define SYSCON_PRESETCTRL_DMIC0_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL_DMIC0_RST_SHIFT (19U) +#define SYSCON_PRESETCTRL_DMIC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC0_RST_MASK) +#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) +#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) +#define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) +#define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) +#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) +#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U) +#define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK) +#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) +#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) +#define SYSCON_PRESETCTRL_USB0_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL_USB0_RST_SHIFT (25U) +#define SYSCON_PRESETCTRL_USB0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) +#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) +#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) +#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) +#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRL */ +#define SYSCON_PRESETCTRL_COUNT (2U) + +/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ +/*! @{ */ +#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) +#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (2U) + +/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ +/*! @{ */ +#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) +#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (2U) + +/*! @name SYSRSTSTAT - System reset status register */ +/*! @{ */ +#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) +#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) +#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) +#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) +#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) +#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) +#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) +#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) +#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) +#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) +#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) +#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) +#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) +#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) +#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL - AHB Clock control n */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U) +#define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U) +#define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK) +#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) +#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) +#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) +#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) +#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) +#define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U) +#define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK) +#define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U) +#define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK) +#define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) +#define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) +#define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) +#define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) +#define SYSCON_AHBCLKCTRL_UTICK0_MASK (0x400U) +#define SYSCON_AHBCLKCTRL_UTICK0_SHIFT (10U) +#define SYSCON_AHBCLKCTRL_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK0_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) +#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) +#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) +#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) +#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) +#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) +#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) +#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) +#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) +#define SYSCON_AHBCLKCTRL_DMIC0_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL_DMIC0_SHIFT (19U) +#define SYSCON_AHBCLKCTRL_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC0_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC0_MASK) +#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) +#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) +#define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U) +#define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK) +#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) +#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U) +#define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK) +#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) +#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) +#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) +#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) +#define SYSCON_AHBCLKCTRL_USB0_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL_USB0_SHIFT (25U) +#define SYSCON_AHBCLKCTRL_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0_SHIFT)) & SYSCON_AHBCLKCTRL_USB0_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) +#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) +#define SYSCON_AHBCLKCTRL_MAILBOX_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL_MAILBOX_SHIFT (26U) +#define SYSCON_AHBCLKCTRL_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL_MAILBOX_MASK) +#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) +#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) +#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRL */ +#define SYSCON_AHBCLKCTRL_COUNT (2U) + +/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) +#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (2U) + +/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (2U) + +/*! @name MAINCLKSELA - Main clock source select A */ +/*! @{ */ +#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select B */ +/*! @{ */ +#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSELA - CLKOUT clock source select A */ +/*! @{ */ +#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) +#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) +#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) +/*! @} */ + +/*! @name SYSPLLCLKSEL - PLL clock source select */ +/*! @{ */ +#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) +#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SPIFICLKSEL - SPIFI clock source select */ +/*! @{ */ +#define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) +#define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) +#define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USBCLKSEL - USB clock source select */ +/*! @{ */ +#define SYSCON_USBCLKSEL_SEL_MASK (0x7U) +#define SYSCON_USBCLKSEL_SEL_SHIFT (0U) +#define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FXCOMCLKSEL - Flexcomm 0 clock source select */ +/*! @{ */ +#define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U) +#define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_FXCOMCLKSEL */ +#define SYSCON_FXCOMCLKSEL_COUNT (8U) + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ +/*! @{ */ +#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) +#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name DMICCLKSEL - Digital microphone (D-Mic) subsystem clock select */ +/*! @{ */ +#define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) +#define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) +#define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV - SYSTICK clock divider */ +/*! @{ */ +#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) +#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) +#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) +#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) +#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name TRACECLKDIV - Trace clock divider */ +/*! @{ */ +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) +/*! @} */ + +/*! @name AHBCLKDIV - AHB clock divider */ +/*! @{ */ +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) +#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) +#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) +#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) +#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) +/*! @} */ + +/*! @name SPIFICLKDIV - SPIFI clock divider */ +/*! @{ */ +#define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) +#define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) +#define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U) +#define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK) +#define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) +#define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) +/*! @} */ + +/*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ +#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) +#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) +#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) +#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) +#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name USBCLKDIV - USB clock divider */ +/*! @{ */ +#define SYSCON_USBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USBCLKDIV_DIV_SHIFT (0U) +#define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK) +#define SYSCON_USBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USBCLKDIV_RESET_SHIFT (29U) +#define SYSCON_USBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_RESET_SHIFT)) & SYSCON_USBCLKDIV_RESET_MASK) +#define SYSCON_USBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USBCLKDIV_HALT_SHIFT (30U) +#define SYSCON_USBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_HALT_SHIFT)) & SYSCON_USBCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name FRGCTRL - Fractional rate divider */ +/*! @{ */ +#define SYSCON_FRGCTRL_DIV_MASK (0xFFU) +#define SYSCON_FRGCTRL_DIV_SHIFT (0U) +#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) +#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) +#define SYSCON_FRGCTRL_MULT_SHIFT (8U) +#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) +/*! @} */ + +/*! @name DMICCLKDIV - DMIC clock divider */ +/*! @{ */ +#define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) +#define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) +#define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_DMICCLKDIV_RESET_SHIFT (29U) +#define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK) +#define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) +#define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) +/*! @} */ + +/*! @name FLASHCFG - Flash wait states configuration */ +/*! @{ */ +#define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) +#define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) +#define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) +#define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) +#define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) +#define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) +#define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) +#define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) +#define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) +#define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) +#define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) +#define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) +#define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) +#define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) +#define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) +#define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) +#define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) +#define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) +/*! @} */ + +/*! @name USBCLKCTRL - USB clock control */ +/*! @{ */ +#define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U) +#define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U) +#define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK) +/*! @} */ + +/*! @name USBCLKSTAT - USB clock status */ +/*! @{ */ +#define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U) +#define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U) +#define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK) +/*! @} */ + +/*! @name FREQMECTRL - Frequency measure register */ +/*! @{ */ +#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) +#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) +#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) +#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) +#define SYSCON_FREQMECTRL_PROG_SHIFT (31U) +#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK input/output control */ +/*! @{ */ +#define SYSCON_MCLKIO_DIR_MASK (0x1U) +#define SYSCON_MCLKIO_DIR_SHIFT (0U) +#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) +/*! @} */ + +/*! @name FROCTRL - FRO oscillator control */ +/*! @{ */ +#define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) +#define SYSCON_FROCTRL_TRIM_SHIFT (0U) +#define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) +#define SYSCON_FROCTRL_SEL_MASK (0x4000U) +#define SYSCON_FROCTRL_SEL_SHIFT (14U) +#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) +#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) +#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) +#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) +#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) +#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) +#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) +#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) +#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) +#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) +#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) +#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) +#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) +#define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) +#define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) +#define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) +/*! @} */ + +/*! @name WDTOSCCTRL - Watchdog oscillator control */ +/*! @{ */ +#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) +#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) +#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) +#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) +#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) +#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) +/*! @} */ + +/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ +/*! @{ */ +#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) +#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) +#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) +/*! @} */ + +/*! @name SYSPLLCTRL - PLL control */ +/*! @{ */ +#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) +#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) +#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) +#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) +#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) +#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) +#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) +#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) +#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) +#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) +#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) +#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) +#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK (0x10000U) +#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT (16U) +#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) +#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) +#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) +#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) +#define SYSCON_SYSPLLCTRL_BANDSEL_MASK (0x40000U) +#define SYSCON_SYSPLLCTRL_BANDSEL_SHIFT (18U) +#define SYSCON_SYSPLLCTRL_BANDSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT)) & SYSCON_SYSPLLCTRL_BANDSEL_MASK) +#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) +#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) +#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) +#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) +#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) +#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) +/*! @} */ + +/*! @name SYSPLLSTAT - PLL status */ +/*! @{ */ +#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) +#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) +#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) +/*! @} */ + +/*! @name SYSPLLNDEC - PLL N decoder */ +/*! @{ */ +#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) +#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) +#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) +#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) +#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) +#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) +/*! @} */ + +/*! @name SYSPLLPDEC - PLL P decoder */ +/*! @{ */ +#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) +#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) +#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) +#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) +#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) +#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) +/*! @} */ + +/*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */ +/*! @{ */ +#define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU) +#define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U) +#define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK) +#define SYSCON_SYSPLLSSCTRL0_MREQ_MASK (0x20000U) +#define SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT (17U) +#define SYSCON_SYSPLLSSCTRL0_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MREQ_MASK) +#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U) +#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U) +#define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) +/*! @} */ + +/*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */ +/*! @{ */ +#define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU) +#define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U) +#define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK) +#define SYSCON_SYSPLLSSCTRL1_MDREQ_MASK (0x80000U) +#define SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT (19U) +#define SYSCON_SYSPLLSSCTRL1_MDREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MDREQ_MASK) +#define SYSCON_SYSPLLSSCTRL1_MF_MASK (0x700000U) +#define SYSCON_SYSPLLSSCTRL1_MF_SHIFT (20U) +#define SYSCON_SYSPLLSSCTRL1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MF_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MF_MASK) +#define SYSCON_SYSPLLSSCTRL1_MR_MASK (0x3800000U) +#define SYSCON_SYSPLLSSCTRL1_MR_SHIFT (23U) +#define SYSCON_SYSPLLSSCTRL1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MR_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MR_MASK) +#define SYSCON_SYSPLLSSCTRL1_MC_MASK (0xC000000U) +#define SYSCON_SYSPLLSSCTRL1_MC_SHIFT (26U) +#define SYSCON_SYSPLLSSCTRL1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MC_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MC_MASK) +#define SYSCON_SYSPLLSSCTRL1_PD_MASK (0x10000000U) +#define SYSCON_SYSPLLSSCTRL1_PD_SHIFT (28U) +#define SYSCON_SYSPLLSSCTRL1_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_PD_MASK) +#define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U) +#define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U) +#define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK) +/*! @} */ + +/*! @name PDSLEEPCFG - Sleep configuration register n */ +/*! @{ */ +#define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU) +#define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U) +#define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK) +/*! @} */ + +/* The count of SYSCON_PDSLEEPCFG */ +#define SYSCON_PDSLEEPCFG_COUNT (2U) + +/*! @name PDRUNCFG - Power configuration register n */ +/*! @{ */ +#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) +#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) +#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) +#define SYSCON_PDRUNCFG_PD_FLASH_MASK (0x20U) +#define SYSCON_PDRUNCFG_PD_FLASH_SHIFT (5U) +#define SYSCON_PDRUNCFG_PD_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_MASK) +#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) +#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) +#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) +#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) +#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) +#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) +#define SYSCON_PDRUNCFG_PD_VDDFLASH_MASK (0x800U) +#define SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT (11U) +#define SYSCON_PDRUNCFG_PD_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDFLASH_MASK) +#define SYSCON_PDRUNCFG_LP_VDDFLASH_MASK (0x1000U) +#define SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT (12U) +#define SYSCON_PDRUNCFG_LP_VDDFLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_LP_VDDFLASH_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x2000U) +#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (13U) +#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAM1_MASK (0x4000U) +#define SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT (14U) +#define SYSCON_PDRUNCFG_PDEN_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAM2_MASK (0x8000U) +#define SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT (15U) +#define SYSCON_PDRUNCFG_PDEN_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM2_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x10000U) +#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (16U) +#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) +#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) +#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) +#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) +#define SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK (0x40000U) +#define SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT (18U) +#define SYSCON_PDRUNCFG_PD_VDDHV_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK) +#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) +#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) +#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) +#define SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK (0x200000U) +#define SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT (21U) +#define SYSCON_PDRUNCFG_PDEN_USB_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) +#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) +#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) +#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) +#define SYSCON_PDRUNCFG_PD_FLASH_BG_MASK (0x2000000U) +#define SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT (25U) +#define SYSCON_PDRUNCFG_PD_FLASH_BG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_BG_MASK) +#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK (0x10000000U) +#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT (28U) +#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK) +#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK (0x20000000U) +#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT (29U) +#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK) +/*! @} */ + +/* The count of SYSCON_PDRUNCFG */ +#define SYSCON_PDRUNCFG_COUNT (2U) + +/*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */ +/*! @{ */ +#define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU) +#define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U) +#define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK) +/*! @} */ + +/* The count of SYSCON_PDRUNCFGSET */ +#define SYSCON_PDRUNCFGSET_COUNT (2U) + +/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */ +/*! @{ */ +#define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U) +#define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_PDRUNCFGCLR */ +#define SYSCON_PDRUNCFGCLR_COUNT (2U) + +/*! @name STARTERP - Start logic n wake-up enable register */ +/*! @{ */ +#define SYSCON_STARTERP_PINT4_MASK (0x1U) +#define SYSCON_STARTERP_PINT4_SHIFT (0U) +#define SYSCON_STARTERP_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT4_SHIFT)) & SYSCON_STARTERP_PINT4_MASK) +#define SYSCON_STARTERP_WDT_BOD_MASK (0x1U) +#define SYSCON_STARTERP_WDT_BOD_SHIFT (0U) +#define SYSCON_STARTERP_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK) +#define SYSCON_STARTERP_DMA0_MASK (0x2U) +#define SYSCON_STARTERP_DMA0_SHIFT (1U) +#define SYSCON_STARTERP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMA0_SHIFT)) & SYSCON_STARTERP_DMA0_MASK) +#define SYSCON_STARTERP_PINT5_MASK (0x2U) +#define SYSCON_STARTERP_PINT5_SHIFT (1U) +#define SYSCON_STARTERP_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK) +#define SYSCON_STARTERP_GINT0_MASK (0x4U) +#define SYSCON_STARTERP_GINT0_SHIFT (2U) +#define SYSCON_STARTERP_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT0_SHIFT)) & SYSCON_STARTERP_GINT0_MASK) +#define SYSCON_STARTERP_PINT6_MASK (0x4U) +#define SYSCON_STARTERP_PINT6_SHIFT (2U) +#define SYSCON_STARTERP_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT6_SHIFT)) & SYSCON_STARTERP_PINT6_MASK) +#define SYSCON_STARTERP_GINT1_MASK (0x8U) +#define SYSCON_STARTERP_GINT1_SHIFT (3U) +#define SYSCON_STARTERP_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT1_SHIFT)) & SYSCON_STARTERP_GINT1_MASK) +#define SYSCON_STARTERP_PINT7_MASK (0x8U) +#define SYSCON_STARTERP_PINT7_SHIFT (3U) +#define SYSCON_STARTERP_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT7_SHIFT)) & SYSCON_STARTERP_PINT7_MASK) +#define SYSCON_STARTERP_CTIMER2_MASK (0x10U) +#define SYSCON_STARTERP_CTIMER2_SHIFT (4U) +#define SYSCON_STARTERP_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER2_SHIFT)) & SYSCON_STARTERP_CTIMER2_MASK) +#define SYSCON_STARTERP_PIN_INT0_MASK (0x10U) +#define SYSCON_STARTERP_PIN_INT0_SHIFT (4U) +#define SYSCON_STARTERP_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT0_SHIFT)) & SYSCON_STARTERP_PIN_INT0_MASK) +#define SYSCON_STARTERP_CTIMER4_MASK (0x20U) +#define SYSCON_STARTERP_CTIMER4_SHIFT (5U) +#define SYSCON_STARTERP_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER4_SHIFT)) & SYSCON_STARTERP_CTIMER4_MASK) +#define SYSCON_STARTERP_PIN_INT1_MASK (0x20U) +#define SYSCON_STARTERP_PIN_INT1_SHIFT (5U) +#define SYSCON_STARTERP_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK) +#define SYSCON_STARTERP_PIN_INT2_MASK (0x40U) +#define SYSCON_STARTERP_PIN_INT2_SHIFT (6U) +#define SYSCON_STARTERP_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT2_SHIFT)) & SYSCON_STARTERP_PIN_INT2_MASK) +#define SYSCON_STARTERP_PIN_INT3_MASK (0x80U) +#define SYSCON_STARTERP_PIN_INT3_SHIFT (7U) +#define SYSCON_STARTERP_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT3_SHIFT)) & SYSCON_STARTERP_PIN_INT3_MASK) +#define SYSCON_STARTERP_UTICK0_MASK (0x100U) +#define SYSCON_STARTERP_UTICK0_SHIFT (8U) +#define SYSCON_STARTERP_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_UTICK0_SHIFT)) & SYSCON_STARTERP_UTICK0_MASK) +#define SYSCON_STARTERP_MRT0_MASK (0x200U) +#define SYSCON_STARTERP_MRT0_SHIFT (9U) +#define SYSCON_STARTERP_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MRT0_SHIFT)) & SYSCON_STARTERP_MRT0_MASK) +#define SYSCON_STARTERP_CTIMER0_MASK (0x400U) +#define SYSCON_STARTERP_CTIMER0_SHIFT (10U) +#define SYSCON_STARTERP_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER0_SHIFT)) & SYSCON_STARTERP_CTIMER0_MASK) +#define SYSCON_STARTERP_CTIMER1_MASK (0x800U) +#define SYSCON_STARTERP_CTIMER1_SHIFT (11U) +#define SYSCON_STARTERP_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER1_SHIFT)) & SYSCON_STARTERP_CTIMER1_MASK) +#define SYSCON_STARTERP_SCT0_MASK (0x1000U) +#define SYSCON_STARTERP_SCT0_SHIFT (12U) +#define SYSCON_STARTERP_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_SCT0_SHIFT)) & SYSCON_STARTERP_SCT0_MASK) +#define SYSCON_STARTERP_CTIMER3_MASK (0x2000U) +#define SYSCON_STARTERP_CTIMER3_SHIFT (13U) +#define SYSCON_STARTERP_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER3_SHIFT)) & SYSCON_STARTERP_CTIMER3_MASK) +#define SYSCON_STARTERP_FLEXCOMM0_MASK (0x4000U) +#define SYSCON_STARTERP_FLEXCOMM0_SHIFT (14U) +#define SYSCON_STARTERP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM0_SHIFT)) & SYSCON_STARTERP_FLEXCOMM0_MASK) +#define SYSCON_STARTERP_FLEXCOMM1_MASK (0x8000U) +#define SYSCON_STARTERP_FLEXCOMM1_SHIFT (15U) +#define SYSCON_STARTERP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM1_SHIFT)) & SYSCON_STARTERP_FLEXCOMM1_MASK) +#define SYSCON_STARTERP_FLEXCOMM2_MASK (0x10000U) +#define SYSCON_STARTERP_FLEXCOMM2_SHIFT (16U) +#define SYSCON_STARTERP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM2_SHIFT)) & SYSCON_STARTERP_FLEXCOMM2_MASK) +#define SYSCON_STARTERP_FLEXCOMM3_MASK (0x20000U) +#define SYSCON_STARTERP_FLEXCOMM3_SHIFT (17U) +#define SYSCON_STARTERP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM3_SHIFT)) & SYSCON_STARTERP_FLEXCOMM3_MASK) +#define SYSCON_STARTERP_FLEXCOMM4_MASK (0x40000U) +#define SYSCON_STARTERP_FLEXCOMM4_SHIFT (18U) +#define SYSCON_STARTERP_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM4_SHIFT)) & SYSCON_STARTERP_FLEXCOMM4_MASK) +#define SYSCON_STARTERP_FLEXCOMM5_MASK (0x80000U) +#define SYSCON_STARTERP_FLEXCOMM5_SHIFT (19U) +#define SYSCON_STARTERP_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM5_SHIFT)) & SYSCON_STARTERP_FLEXCOMM5_MASK) +#define SYSCON_STARTERP_FLEXCOMM6_MASK (0x100000U) +#define SYSCON_STARTERP_FLEXCOMM6_SHIFT (20U) +#define SYSCON_STARTERP_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM6_SHIFT)) & SYSCON_STARTERP_FLEXCOMM6_MASK) +#define SYSCON_STARTERP_FLEXCOMM7_MASK (0x200000U) +#define SYSCON_STARTERP_FLEXCOMM7_SHIFT (21U) +#define SYSCON_STARTERP_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM7_SHIFT)) & SYSCON_STARTERP_FLEXCOMM7_MASK) +#define SYSCON_STARTERP_ADC0_SEQA_MASK (0x400000U) +#define SYSCON_STARTERP_ADC0_SEQA_SHIFT (22U) +#define SYSCON_STARTERP_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQA_SHIFT)) & SYSCON_STARTERP_ADC0_SEQA_MASK) +#define SYSCON_STARTERP_ADC0_SEQB_MASK (0x800000U) +#define SYSCON_STARTERP_ADC0_SEQB_SHIFT (23U) +#define SYSCON_STARTERP_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQB_SHIFT)) & SYSCON_STARTERP_ADC0_SEQB_MASK) +#define SYSCON_STARTERP_ADC0_THCMP_MASK (0x1000000U) +#define SYSCON_STARTERP_ADC0_THCMP_SHIFT (24U) +#define SYSCON_STARTERP_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_THCMP_SHIFT)) & SYSCON_STARTERP_ADC0_THCMP_MASK) +#define SYSCON_STARTERP_DMIC0_MASK (0x2000000U) +#define SYSCON_STARTERP_DMIC0_SHIFT (25U) +#define SYSCON_STARTERP_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMIC0_SHIFT)) & SYSCON_STARTERP_DMIC0_MASK) +#define SYSCON_STARTERP_USB0_NEEDCLK_MASK (0x8000000U) +#define SYSCON_STARTERP_USB0_NEEDCLK_SHIFT (27U) +#define SYSCON_STARTERP_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTERP_USB0_NEEDCLK_MASK) +#define SYSCON_STARTERP_USB0_MASK (0x10000000U) +#define SYSCON_STARTERP_USB0_SHIFT (28U) +#define SYSCON_STARTERP_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_SHIFT)) & SYSCON_STARTERP_USB0_MASK) +#define SYSCON_STARTERP_RTC_MASK (0x20000000U) +#define SYSCON_STARTERP_RTC_SHIFT (29U) +#define SYSCON_STARTERP_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_RTC_SHIFT)) & SYSCON_STARTERP_RTC_MASK) +#define SYSCON_STARTERP_MAILBOX_MASK (0x80000000U) +#define SYSCON_STARTERP_MAILBOX_SHIFT (31U) +#define SYSCON_STARTERP_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MAILBOX_SHIFT)) & SYSCON_STARTERP_MAILBOX_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERP */ +#define SYSCON_STARTERP_COUNT (2U) + +/*! @name STARTERSET - Set bits in STARTERn */ +/*! @{ */ +#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) +#define SYSCON_STARTERSET_START_SET_SHIFT (0U) +#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERSET */ +#define SYSCON_STARTERSET_COUNT (2U) + +/*! @name STARTERCLR - Clear bits in STARTERn */ +/*! @{ */ +#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) +#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERCLR */ +#define SYSCON_STARTERCLR_COUNT (2U) + +/*! @name HWWAKE - Configures special cases of hardware wake-up */ +/*! @{ */ +#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) +#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) +#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) +#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) +#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) +#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) +#define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U) +#define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U) +#define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK) +#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) +#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) +#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) +/*! @} */ + +/*! @name CPUCTRL - CPU Control for multiple processors */ +/*! @{ */ +#define SYSCON_CPUCTRL_MASTERCPU_MASK (0x1U) +#define SYSCON_CPUCTRL_MASTERCPU_SHIFT (0U) +#define SYSCON_CPUCTRL_MASTERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_MASTERCPU_SHIFT)) & SYSCON_CPUCTRL_MASTERCPU_MASK) +#define SYSCON_CPUCTRL_CM4CLKEN_MASK (0x4U) +#define SYSCON_CPUCTRL_CM4CLKEN_SHIFT (2U) +#define SYSCON_CPUCTRL_CM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM4CLKEN_MASK) +#define SYSCON_CPUCTRL_CM0CLKEN_MASK (0x8U) +#define SYSCON_CPUCTRL_CM0CLKEN_SHIFT (3U) +#define SYSCON_CPUCTRL_CM0CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPUCTRL_CM0CLKEN_MASK) +#define SYSCON_CPUCTRL_CM4RSTEN_MASK (0x10U) +#define SYSCON_CPUCTRL_CM4RSTEN_SHIFT (4U) +#define SYSCON_CPUCTRL_CM4RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM4RSTEN_MASK) +#define SYSCON_CPUCTRL_CM0RSTEN_MASK (0x20U) +#define SYSCON_CPUCTRL_CM0RSTEN_SHIFT (5U) +#define SYSCON_CPUCTRL_CM0RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPUCTRL_CM0RSTEN_MASK) +#define SYSCON_CPUCTRL_POWERCPU_MASK (0x40U) +#define SYSCON_CPUCTRL_POWERCPU_SHIFT (6U) +#define SYSCON_CPUCTRL_POWERCPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_POWERCPU_SHIFT)) & SYSCON_CPUCTRL_POWERCPU_MASK) +/*! @} */ + +/*! @name CPBOOT - Coprocessor Boot Address */ +/*! @{ */ +#define SYSCON_CPBOOT_BOOTADDR_MASK (0xFFFFFFFFU) +#define SYSCON_CPBOOT_BOOTADDR_SHIFT (0U) +#define SYSCON_CPBOOT_BOOTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_BOOTADDR_SHIFT)) & SYSCON_CPBOOT_BOOTADDR_MASK) +/*! @} */ + +/*! @name CPSTACK - Coprocessor Stack Address */ +/*! @{ */ +#define SYSCON_CPSTACK_STACKADDR_MASK (0xFFFFFFFFU) +#define SYSCON_CPSTACK_STACKADDR_SHIFT (0U) +#define SYSCON_CPSTACK_STACKADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_STACKADDR_SHIFT)) & SYSCON_CPSTACK_STACKADDR_MASK) +/*! @} */ + +/*! @name CPSTAT - Coprocessor Status */ +/*! @{ */ +#define SYSCON_CPSTAT_CM4SLEEPING_MASK (0x1U) +#define SYSCON_CPSTAT_CM4SLEEPING_SHIFT (0U) +#define SYSCON_CPSTAT_CM4SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM4SLEEPING_MASK) +#define SYSCON_CPSTAT_CM0SLEEPING_MASK (0x2U) +#define SYSCON_CPSTAT_CM0SLEEPING_SHIFT (1U) +#define SYSCON_CPSTAT_CM0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM0SLEEPING_MASK) +#define SYSCON_CPSTAT_CM4LOCKUP_MASK (0x4U) +#define SYSCON_CPSTAT_CM4LOCKUP_SHIFT (2U) +#define SYSCON_CPSTAT_CM4LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM4LOCKUP_MASK) +#define SYSCON_CPSTAT_CM0LOCKUP_MASK (0x8U) +#define SYSCON_CPSTAT_CM0LOCKUP_SHIFT (3U) +#define SYSCON_CPSTAT_CM0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM0LOCKUP_MASK) +/*! @} */ + +/*! @name AUTOCGOR - Auto Clock-Gate Override Register */ +/*! @{ */ +#define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) +#define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) +#define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) +#define SYSCON_AUTOCGOR_RAM1_MASK (0x4U) +#define SYSCON_AUTOCGOR_RAM1_SHIFT (2U) +#define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK) +#define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) +#define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) +#define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) +/*! @} */ + +/*! @name JTAGIDCODE - JTAG ID code register */ +/*! @{ */ +#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) +#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) +#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Part ID register */ +/*! @{ */ +#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) +#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) +/*! @} */ + +/*! @name DEVICE_ID1 - Boot ROM and die revision register */ +/*! @{ */ +#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) +#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) +/*! @} */ + +/*! @name BODCTRL - Brown-Out Detect control */ +/*! @{ */ +#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) +#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) +#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) +#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) +#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) +#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) +#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) +#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) +#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) +#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) +#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) +#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) +#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) +#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) +#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) +#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) +#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) +#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40000000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) +#define USART_CFG_IOMODE_MASK (0x10000U) +#define USART_CFG_IOMODE_SHIFT (16U) +#define USART_CFG_IOMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_IOMODE_SHIFT)) & USART_CFG_IOMODE_MASK) +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +/** Peripheral USART0 base address */ +#define USART0_BASE (0x40086000u) +/** Peripheral USART0 base pointer */ +#define USART0 ((USART_Type *)USART0_BASE) +/** Peripheral USART1 base address */ +#define USART1_BASE (0x40087000u) +/** Peripheral USART1 base pointer */ +#define USART1 ((USART_Type *)USART1_BASE) +/** Peripheral USART2 base address */ +#define USART2_BASE (0x40088000u) +/** Peripheral USART2 base pointer */ +#define USART2 ((USART_Type *)USART2_BASE) +/** Peripheral USART3 base address */ +#define USART3_BASE (0x40089000u) +/** Peripheral USART3 base pointer */ +#define USART3 ((USART_Type *)USART3_BASE) +/** Peripheral USART4 base address */ +#define USART4_BASE (0x4008A000u) +/** Peripheral USART4 base pointer */ +#define USART4 ((USART_Type *)USART4_BASE) +/** Peripheral USART5 base address */ +#define USART5_BASE (0x40096000u) +/** Peripheral USART5 base pointer */ +#define USART5 ((USART_Type *)USART5_BASE) +/** Peripheral USART6 base address */ +#define USART6_BASE (0x40097000u) +/** Peripheral USART6 base pointer */ +#define USART6 ((USART_Type *)USART6_BASE) +/** Peripheral USART7 base address */ +#define USART7_BASE (0x40098000u) +/** Peripheral USART7 base pointer */ +#define USART7 ((USART_Type *)USART7_BASE) +/** Array initializer of USART peripheral base addresses */ +#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } +/** Array initializer of USART peripheral base pointers */ +#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ +#define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x40084000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +/*! @{ */ +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status register. */ +/*! @{ */ +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture configuration register. */ +/*! @{ */ +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture clear register. */ +/*! @{ */ +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture register . */ +/*! @{ */ +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000E000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) +/*! @} */ + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT base address */ +#define WWDT_BASE (0x4000C000u) +/** Peripheral WWDT base pointer */ +#define WWDT ((WWDT_Type *)WWDT_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT } +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC54114_CM4_H_ */ + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4_features.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4_features.h new file mode 100644 index 00000000000..0fe1ee1ab6b --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/LPC54114_cm4_features.h @@ -0,0 +1,249 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2016-05-09 +** Build: b180327 +** +** Abstract: +** Chip specific module features. +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-05-09) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _LPC54114_cm4_FEATURES_H_ +#define _LPC54114_cm4_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) +/* @brief ASYNC_SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (1) +/* @brief DMIC availability on the SoC. */ +#define FSL_FEATURE_SOC_DMIC_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (8) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (8) +/* @brief SPIFI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPIFI_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* ADC module features */ + +/* @brief Do not has input select (register INSEL). */ +#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) +/* @brief Has startup register. */ +#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) +/* @brief Has ADTrim register */ +#define FSL_FEATURE_ADC_HAS_TRIM_REG (0) +/* @brief Has Calibration register. */ +#define FSL_FEATURE_ADC_HAS_CALIB_REG (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM7 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core. */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8) + +/* SYSCON module features */ + +/* @brief Pointer to ROM IAP entry functions */ +#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* USB module features */ + +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +#endif /* _LPC54114_cm4_FEATURES_H_ */ + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/SConscript b/bsp/lpc54114-lite/Libraries/devices/LPC54114/SConscript new file mode 100644 index 00000000000..34fd4268fb2 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/SConscript @@ -0,0 +1,35 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) +CPPDEFINES = [] + +objs = objs + SConscript(os.path.join('drivers', 'SConscript')) +objs = objs + SConscript(os.path.join('utilities', 'SConscript')) + +if rtconfig.CROSS_TOOL == 'gcc': + objs = objs + SConscript(os.path.join('gcc', 'SConscript')) + CPPDEFINES += ['__USE_CMSIS'] +elif rtconfig.CROSS_TOOL == 'keil': + objs = objs + SConscript(os.path.join('arm', 'SConscript')) +elif rtconfig.CROSS_TOOL == 'iar': + objs = objs + SConscript(os.path.join('iar', 'SConscript')) + +src = Split(""" +system_LPC54114_cm4.c +""") + +CPPPATH = [cwd] +CPPDEFINES += ['CORE_M4', 'CPU_LPC54114', 'CPU_LPC54114J256BD64_cm4=1'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +objs = objs + group + +Return('objs') diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus.scf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus.scf new file mode 100644 index 00000000000..b0d9176b43b --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus.scf @@ -0,0 +1,107 @@ +#! armcc -E +/* +** ################################################################### +** Processors: LPC54114J256BD64_cm0plus +** LPC54114J256UK49_cm0plus +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC5411x User manual Rev. 1.0 16 February 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b160606 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x20010000 +#define m_interrupts_size 0x000000C0 + +#define m_text_start 0x200100C0 +#define m_text_size 0x0000FF40 + +#if (defined(__use_shmem__)) +#define m_rpmsg_sh_mem_start 0x20026800 +#define m_rpmsg_sh_mem_size 0x00001800 +#define m_data_start 0x20020000 +#define m_data_size 0x00006800 +#else +#define m_data_start 0x20020000 +#define m_data_size 0x00008000 +#endif + + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP ((ImageLimit(RW_m_data) == m_data_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif +} + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus_ram.scf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus_ram.scf new file mode 100644 index 00000000000..99970a0bb32 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm0plus_ram.scf @@ -0,0 +1,105 @@ +#! armcc -E +/* +** ################################################################### +** Processors: LPC54114J256BD64_cm0plus +** LPC54114J256UK49_cm0plus +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC5411x User manual Rev. 1.0 16 February 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b160606 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x20010000 +#define m_interrupts_size 0x000000C0 + +#define m_text_start 0x200100C0 +#define m_text_size 0x0000FF40 + +#if (defined(__use_shmem__)) +#define m_rpmsg_sh_mem_start 0x20026800 +#define m_rpmsg_sh_mem_size 0x00001800 +#define m_data_start 0x20020000 +#define m_data_size 0x00006800 +#else +#define m_data_start 0x20020000 +#define m_data_size 0x00008000 +#endif + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP ((ImageLimit(RW_m_data) == m_data_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif +} + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm4_ram.scf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm4_ram.scf new file mode 100644 index 00000000000..d9a73cf6330 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/LPC54114J256_cm4_ram.scf @@ -0,0 +1,106 @@ +#! armcc -E +/* +** ################################################################### +** Processors: LPC54114J256BD64_cm4 +** LPC54114J256UK49_cm4 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC5411x User manual Rev. 1.0 16 February 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b160526 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x20000000 +#define m_interrupts_size 0x000000E0 + +#define m_text_start 0x200000E0 +#define m_text_size 0x0001FF20 + +#define m_data_start 0x20020000 +#define m_data_size 0x00008000 + +#define m_stack_start 0x04000000 +#define m_stack_size 0x00008000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + + + +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_stack_start+m_stack_size EMPTY -Stack_Size { ; Stack region growing down + } +} + +LR_m_interrupts m_interrupts_start m_interrupts_size { + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } +} + +LR_m_interrupts_ram m_interrupts_start m_interrupts_size { + VECTOR_RAM m_interrupts_start m_interrupts_size { ; load address = execution address + .ANY (.m_interrupts_ram) + } +} + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/SConscript b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/SConscript new file mode 100644 index 00000000000..578ff8d7c40 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = Split(''' +startup_LPC54114_cm4.s +''') + +group = DefineGroup('Libraries', src, depend = [''], LIBS=['keil_lib_power'], LIBPATH=[cwd]) + +Return('group') diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm0plus.s b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm0plus.s new file mode 100644 index 00000000000..dbaa73ffdd3 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm0plus.s @@ -0,0 +1,532 @@ +;/***************************************************************************** +; * @file: startup_LPC54114_cm0plus.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the +; * LPC54114_cm0plus +; * @version: 1.0 +; * @date: 2016-4-29 +; * +; * The Clear BSD License +; * Copyright 1997 - 2016 Freescale Semiconductor, Inc. +; * Copyright 2016 - 2017 NXP +; * +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted (subject to the limitations in the disclaimer below) provided +; * that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of the copyright holder nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 ; Checksum of the first 7 words + DCD 0 + DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot + DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ; DMA controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) + DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD IOH_IRQHandler ; IOH + DCD MAILBOX_IRQHandler ; Mailbox interrupt (present on selected devices) + +; Code Read Protection level (CRP) +; CRP_Level: +; <0xFFFFFFFF=> Disabled +; <0x4E697370=> NO_ISP +; <0x12345678=> CRP1 +; <0x87654321=> CRP2 +; <0x43218765=> CRP3 (Are you sure?) +; +CRP_Level EQU 0xFFFFFFFF + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + AREA |.text|, CODE, READONLY + +cpu_id EQU 0xE000ED00 +cpu_ctrl EQU 0x40000800 +coproc_boot EQU 0x40000804 +coproc_stack EQU 0x40000808 + +rel_vals + DCD cpu_id, cpu_ctrl, coproc_boot, coproc_stack + DCW 0xFFF, 0xC24 + +; Reset Handler - shared for both cores +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:SLAVEBOOT + ; Both the M0+ and M4 core come via this shared startup code, + ; but the M0+ and M4 core have different vector tables. + ; Determine if the core executing this code is the master or + ; the slave and handle each core state individually. +shared_boot_entry + LDR r6, =rel_vals + MOVS r4, #0 ; Flag for slave core (0) + MOVS r5, #1 + + ; Determine which core (M0+ or M4) this code is running on + ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) +get_current_core_id + LDR r0, [r6, #0] + LDR r1, [r0] ; r1 = CPU ID status + LSRS r1, r1, #4 ; Right justify 12 CPU ID bits + LDRH r2, [r6, #16] ; Mask for CPU ID bits + ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID + LDRH r3, [r6, #18] ; Mask for CPU ID bits + CMP r3, r2 ; Core ID matches M4 identifier + BNE get_master_status + MOV r4, r5 ; Set flag for master core (1) + + ; Determine if M4 core is the master or slave + ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) +get_master_status + LDR r0, [r6, #4] + LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status + ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) + + ; Select boot based on selected master core and core ID +select_boot + EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) + BNE slave_boot + B normal_boot + + ; Slave boot +slave_boot + LDR r0, [r6, #8] + LDR r2, [r0] ; r1 = SYSCON co-processor boot address + CMP r2, #0 ; Slave boot address = 0 (not set up)? + BEQ cpu_sleep + LDR r0, [r6, #12] + LDR r1, [r0] ; r5 = SYSCON co-processor stack address + MOV sp, r1 ; Update slave CPU stack pointer + ; Be sure to update VTOR for the slave MCU to point to the + ; slave vector table in boot memory + BX r2 ; Jump to slave boot address + + ; Slave isn't yet setup for system boot from the master + ; so sleep until the master sets it up and then reboots it +cpu_sleep + MOV sp, r5 ; Will force exception if something happens +cpu_sleep_wfi + WFI ; Sleep forever until master reboots + B cpu_sleep_wfi + ENDIF + + ; Normal boot for master/slave +normal_boot + LDR r0, =SystemInit + BLX r0 + LDR r0, =__main + BX r0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler \ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +WDT_BOD_IRQHandler\ + PROC + EXPORT WDT_BOD_IRQHandler [WEAK] + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + ENDP + +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +GINT0_IRQHandler\ + PROC + EXPORT GINT0_IRQHandler [WEAK] + LDR R0, =GINT0_DriverIRQHandler + BX R0 + ENDP + +GINT1_IRQHandler\ + PROC + EXPORT GINT1_IRQHandler [WEAK] + LDR R0, =GINT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT0_IRQHandler\ + PROC + EXPORT PIN_INT0_IRQHandler [WEAK] + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + ENDP + +PIN_INT1_IRQHandler\ + PROC + EXPORT PIN_INT1_IRQHandler [WEAK] + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT2_IRQHandler\ + PROC + EXPORT PIN_INT2_IRQHandler [WEAK] + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + ENDP + +PIN_INT3_IRQHandler\ + PROC + EXPORT PIN_INT3_IRQHandler [WEAK] + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + ENDP + +UTICK0_IRQHandler\ + PROC + EXPORT UTICK0_IRQHandler [WEAK] + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + ENDP + +MRT0_IRQHandler\ + PROC + EXPORT MRT0_IRQHandler [WEAK] + LDR R0, =MRT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER0_IRQHandler\ + PROC + EXPORT CTIMER0_IRQHandler [WEAK] + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + ENDP + +CTIMER1_IRQHandler\ + PROC + EXPORT CTIMER1_IRQHandler [WEAK] + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + ENDP + +SCT0_IRQHandler\ + PROC + EXPORT SCT0_IRQHandler [WEAK] + LDR R0, =SCT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER3_IRQHandler\ + PROC + EXPORT CTIMER3_IRQHandler [WEAK] + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM0_IRQHandler\ + PROC + EXPORT FLEXCOMM0_IRQHandler [WEAK] + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM1_IRQHandler\ + PROC + EXPORT FLEXCOMM1_IRQHandler [WEAK] + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM2_IRQHandler\ + PROC + EXPORT FLEXCOMM2_IRQHandler [WEAK] + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM3_IRQHandler\ + PROC + EXPORT FLEXCOMM3_IRQHandler [WEAK] + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM4_IRQHandler\ + PROC + EXPORT FLEXCOMM4_IRQHandler [WEAK] + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM5_IRQHandler\ + PROC + EXPORT FLEXCOMM5_IRQHandler [WEAK] + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM6_IRQHandler\ + PROC + EXPORT FLEXCOMM6_IRQHandler [WEAK] + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM7_IRQHandler\ + PROC + EXPORT FLEXCOMM7_IRQHandler [WEAK] + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + ENDP + +ADC0_SEQA_IRQHandler\ + PROC + EXPORT ADC0_SEQA_IRQHandler [WEAK] + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + ENDP + +ADC0_SEQB_IRQHandler\ + PROC + EXPORT ADC0_SEQB_IRQHandler [WEAK] + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + ENDP + +ADC0_THCMP_IRQHandler\ + PROC + EXPORT ADC0_THCMP_IRQHandler [WEAK] + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + ENDP + +DMIC0_IRQHandler\ + PROC + EXPORT DMIC0_IRQHandler [WEAK] + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + ENDP + +HWVAD0_IRQHandler\ + PROC + EXPORT HWVAD0_IRQHandler [WEAK] + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + ENDP + +USB0_NEEDCLK_IRQHandler\ + PROC + EXPORT USB0_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +USB0_IRQHandler\ + PROC + EXPORT USB0_IRQHandler [WEAK] + LDR R0, =USB0_DriverIRQHandler + BX R0 + ENDP + +RTC_IRQHandler\ + PROC + EXPORT RTC_IRQHandler [WEAK] + LDR R0, =RTC_DriverIRQHandler + BX R0 + ENDP + +IOH_IRQHandler\ + PROC + EXPORT IOH_IRQHandler [WEAK] + LDR R0, =IOH_DriverIRQHandler + BX R0 + ENDP + +MAILBOX_IRQHandler\ + PROC + EXPORT MAILBOX_IRQHandler [WEAK] + LDR R0, =MAILBOX_DriverIRQHandler + BX R0 + ENDP + +Default_Handler PROC + EXPORT WDT_BOD_DriverIRQHandler [WEAK] + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT GINT0_DriverIRQHandler [WEAK] + EXPORT GINT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT0_DriverIRQHandler [WEAK] + EXPORT PIN_INT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT2_DriverIRQHandler [WEAK] + EXPORT PIN_INT3_DriverIRQHandler [WEAK] + EXPORT UTICK0_DriverIRQHandler [WEAK] + EXPORT MRT0_DriverIRQHandler [WEAK] + EXPORT CTIMER0_DriverIRQHandler [WEAK] + EXPORT CTIMER1_DriverIRQHandler [WEAK] + EXPORT SCT0_DriverIRQHandler [WEAK] + EXPORT CTIMER3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] + EXPORT ADC0_SEQA_DriverIRQHandler [WEAK] + EXPORT ADC0_SEQB_DriverIRQHandler [WEAK] + EXPORT ADC0_THCMP_DriverIRQHandler [WEAK] + EXPORT DMIC0_DriverIRQHandler [WEAK] + EXPORT HWVAD0_DriverIRQHandler [WEAK] + EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT USB0_DriverIRQHandler [WEAK] + EXPORT RTC_DriverIRQHandler [WEAK] + EXPORT IOH_DriverIRQHandler [WEAK] + EXPORT MAILBOX_DriverIRQHandler [WEAK] + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +IOH_DriverIRQHandler +MAILBOX_DriverIRQHandler + + B . + + ENDP + + + ALIGN + + + END + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm4.s b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm4.s new file mode 100644 index 00000000000..dad9da5a92b --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/arm/startup_LPC54114_cm4.s @@ -0,0 +1,632 @@ +;/***************************************************************************** +; * @file: startup_LPC54114_cm4.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the +; * LPC54114_cm4 +; * @version: 1.0 +; * @date: 2016-4-29 +; * +; * The Clear BSD License +; * Copyright 1997 - 2016 Freescale Semiconductor, Inc. +; * Copyright 2016 - 2017 NXP +; * +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted (subject to the limitations in the disclaimer below) provided +; * that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of the copyright holder nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 ; Checksum of the first 7 words + DCD 0 + DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot + DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ; DMA controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) + DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD IOH_IRQHandler ; IOH + DCD MAILBOX_IRQHandler ; Mailbox interrupt (present on selected devices) + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD Reserved54_IRQHandler ; Reserved interrupt + DCD SPIFI0_IRQHandler ; SPI flash interface + +; Code Read Protection level (CRP) +; CRP_Level: +; <0xFFFFFFFF=> Disabled +; <0x4E697370=> NO_ISP +; <0x12345678=> CRP1 +; <0x87654321=> CRP2 +; <0x43218765=> CRP3 (Are you sure?) +; +CRP_Level EQU 0xFFFFFFFF + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + AREA |.text|, CODE, READONLY + +cpu_id EQU 0xE000ED00 +cpu_ctrl EQU 0x40000800 +coproc_boot EQU 0x40000804 +coproc_stack EQU 0x40000808 + +rel_vals + DCD cpu_id, cpu_ctrl, coproc_boot, coproc_stack + DCW 0xFFF, 0xC24 + +; Reset Handler - shared for both cores +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:SLAVEBOOT + ; Both the M0+ and M4 core come via this shared startup code, + ; but the M0+ and M4 core have different vector tables. + ; Determine if the core executing this code is the master or + ; the slave and handle each core state individually. +shared_boot_entry + LDR r6, =rel_vals + MOVS r4, #0 ; Flag for slave core (0) + MOVS r5, #1 + + ; Determine which core (M0+ or M4) this code is running on + ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) +get_current_core_id + LDR r0, [r6, #0] + LDR r1, [r0] ; r1 = CPU ID status + LSRS r1, r1, #4 ; Right justify 12 CPU ID bits + LDRH r2, [r6, #16] ; Mask for CPU ID bits + ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID + LDRH r3, [r6, #18] ; Mask for CPU ID bits + CMP r3, r2 ; Core ID matches M4 identifier + BNE get_master_status + MOV r4, r5 ; Set flag for master core (1) + + ; Determine if M4 core is the master or slave + ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) +get_master_status + LDR r0, [r6, #4] + LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status + ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) + + ; Select boot based on selected master core and core ID +select_boot + EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) + BNE slave_boot + B normal_boot + + ; Slave boot +slave_boot + LDR r0, [r6, #8] + LDR r2, [r0] ; r1 = SYSCON co-processor boot address + CMP r2, #0 ; Slave boot address = 0 (not set up)? + BEQ cpu_sleep + LDR r0, [r6, #12] + LDR r1, [r0] ; r5 = SYSCON co-processor stack address + MOV sp, r1 ; Update slave CPU stack pointer + ; Be sure to update VTOR for the slave MCU to point to the + ; slave vector table in boot memory + BX r2 ; Jump to slave boot address + + ; Slave isn't yet setup for system boot from the master + ; so sleep until the master sets it up and then reboots it +cpu_sleep + MOV sp, r5 ; Will force exception if something happens +cpu_sleep_wfi + WFI ; Sleep forever until master reboots + B cpu_sleep_wfi + ENDIF + + ; Normal boot for master/slave +normal_boot + LDR r0, =SystemInit + BLX r0 + LDR r0, =__main + BX r0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler \ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +WDT_BOD_IRQHandler\ + PROC + EXPORT WDT_BOD_IRQHandler [WEAK] + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + ENDP + +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +GINT0_IRQHandler\ + PROC + EXPORT GINT0_IRQHandler [WEAK] + LDR R0, =GINT0_DriverIRQHandler + BX R0 + ENDP + +GINT1_IRQHandler\ + PROC + EXPORT GINT1_IRQHandler [WEAK] + LDR R0, =GINT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT0_IRQHandler\ + PROC + EXPORT PIN_INT0_IRQHandler [WEAK] + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + ENDP + +PIN_INT1_IRQHandler\ + PROC + EXPORT PIN_INT1_IRQHandler [WEAK] + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT2_IRQHandler\ + PROC + EXPORT PIN_INT2_IRQHandler [WEAK] + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + ENDP + +PIN_INT3_IRQHandler\ + PROC + EXPORT PIN_INT3_IRQHandler [WEAK] + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + ENDP + +UTICK0_IRQHandler\ + PROC + EXPORT UTICK0_IRQHandler [WEAK] + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + ENDP + +MRT0_IRQHandler\ + PROC + EXPORT MRT0_IRQHandler [WEAK] + LDR R0, =MRT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER0_IRQHandler\ + PROC + EXPORT CTIMER0_IRQHandler [WEAK] + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + ENDP + +CTIMER1_IRQHandler\ + PROC + EXPORT CTIMER1_IRQHandler [WEAK] + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + ENDP + +SCT0_IRQHandler\ + PROC + EXPORT SCT0_IRQHandler [WEAK] + LDR R0, =SCT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER3_IRQHandler\ + PROC + EXPORT CTIMER3_IRQHandler [WEAK] + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM0_IRQHandler\ + PROC + EXPORT FLEXCOMM0_IRQHandler [WEAK] + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM1_IRQHandler\ + PROC + EXPORT FLEXCOMM1_IRQHandler [WEAK] + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM2_IRQHandler\ + PROC + EXPORT FLEXCOMM2_IRQHandler [WEAK] + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM3_IRQHandler\ + PROC + EXPORT FLEXCOMM3_IRQHandler [WEAK] + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM4_IRQHandler\ + PROC + EXPORT FLEXCOMM4_IRQHandler [WEAK] + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM5_IRQHandler\ + PROC + EXPORT FLEXCOMM5_IRQHandler [WEAK] + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM6_IRQHandler\ + PROC + EXPORT FLEXCOMM6_IRQHandler [WEAK] + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM7_IRQHandler\ + PROC + EXPORT FLEXCOMM7_IRQHandler [WEAK] + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + ENDP + +ADC0_SEQA_IRQHandler\ + PROC + EXPORT ADC0_SEQA_IRQHandler [WEAK] + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + ENDP + +ADC0_SEQB_IRQHandler\ + PROC + EXPORT ADC0_SEQB_IRQHandler [WEAK] + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + ENDP + +ADC0_THCMP_IRQHandler\ + PROC + EXPORT ADC0_THCMP_IRQHandler [WEAK] + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + ENDP + +DMIC0_IRQHandler\ + PROC + EXPORT DMIC0_IRQHandler [WEAK] + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + ENDP + +HWVAD0_IRQHandler\ + PROC + EXPORT HWVAD0_IRQHandler [WEAK] + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + ENDP + +USB0_NEEDCLK_IRQHandler\ + PROC + EXPORT USB0_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +USB0_IRQHandler\ + PROC + EXPORT USB0_IRQHandler [WEAK] + LDR R0, =USB0_DriverIRQHandler + BX R0 + ENDP + +RTC_IRQHandler\ + PROC + EXPORT RTC_IRQHandler [WEAK] + LDR R0, =RTC_DriverIRQHandler + BX R0 + ENDP + +IOH_IRQHandler\ + PROC + EXPORT IOH_IRQHandler [WEAK] + LDR R0, =IOH_DriverIRQHandler + BX R0 + ENDP + +MAILBOX_IRQHandler\ + PROC + EXPORT MAILBOX_IRQHandler [WEAK] + LDR R0, =MAILBOX_DriverIRQHandler + BX R0 + ENDP + +PIN_INT4_IRQHandler\ + PROC + EXPORT PIN_INT4_IRQHandler [WEAK] + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + ENDP + +PIN_INT5_IRQHandler\ + PROC + EXPORT PIN_INT5_IRQHandler [WEAK] + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + ENDP + +PIN_INT6_IRQHandler\ + PROC + EXPORT PIN_INT6_IRQHandler [WEAK] + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + ENDP + +PIN_INT7_IRQHandler\ + PROC + EXPORT PIN_INT7_IRQHandler [WEAK] + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + ENDP + +CTIMER2_IRQHandler\ + PROC + EXPORT CTIMER2_IRQHandler [WEAK] + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + ENDP + +CTIMER4_IRQHandler\ + PROC + EXPORT CTIMER4_IRQHandler [WEAK] + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + ENDP + +Reserved54_IRQHandler\ + PROC + EXPORT Reserved54_IRQHandler [WEAK] + LDR R0, =Reserved54_DriverIRQHandler + BX R0 + ENDP + +SPIFI0_IRQHandler\ + PROC + EXPORT SPIFI0_IRQHandler [WEAK] + LDR R0, =SPIFI0_DriverIRQHandler + BX R0 + ENDP + +Default_Handler PROC + EXPORT WDT_BOD_DriverIRQHandler [WEAK] + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT GINT0_DriverIRQHandler [WEAK] + EXPORT GINT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT0_DriverIRQHandler [WEAK] + EXPORT PIN_INT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT2_DriverIRQHandler [WEAK] + EXPORT PIN_INT3_DriverIRQHandler [WEAK] + EXPORT UTICK0_DriverIRQHandler [WEAK] + EXPORT MRT0_DriverIRQHandler [WEAK] + EXPORT CTIMER0_DriverIRQHandler [WEAK] + EXPORT CTIMER1_DriverIRQHandler [WEAK] + EXPORT SCT0_DriverIRQHandler [WEAK] + EXPORT CTIMER3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] + EXPORT ADC0_SEQA_DriverIRQHandler [WEAK] + EXPORT ADC0_SEQB_DriverIRQHandler [WEAK] + EXPORT ADC0_THCMP_DriverIRQHandler [WEAK] + EXPORT DMIC0_DriverIRQHandler [WEAK] + EXPORT HWVAD0_DriverIRQHandler [WEAK] + EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT USB0_DriverIRQHandler [WEAK] + EXPORT RTC_DriverIRQHandler [WEAK] + EXPORT IOH_DriverIRQHandler [WEAK] + EXPORT MAILBOX_DriverIRQHandler [WEAK] + EXPORT PIN_INT4_DriverIRQHandler [WEAK] + EXPORT PIN_INT5_DriverIRQHandler [WEAK] + EXPORT PIN_INT6_DriverIRQHandler [WEAK] + EXPORT PIN_INT7_DriverIRQHandler [WEAK] + EXPORT CTIMER2_DriverIRQHandler [WEAK] + EXPORT CTIMER4_DriverIRQHandler [WEAK] + EXPORT Reserved54_DriverIRQHandler [WEAK] + EXPORT SPIFI0_DriverIRQHandler [WEAK] + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +IOH_DriverIRQHandler +MAILBOX_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +Reserved54_DriverIRQHandler +SPIFI0_DriverIRQHandler + + B . + + ENDP + + + ALIGN + + + END + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.c new file mode 100644 index 00000000000..21bd2ca1262 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.c @@ -0,0 +1,2265 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "fsl_i2c_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_cmsis" +#endif + + +#if (RTE_I2C0 || RTE_I2C1 || RTE_I2C2 || RTE_I2C3 || RTE_I2C4 || RTE_I2C5 || RTE_I2C6 || RTE_I2C7 || RTE_I2C8 || \ + RTE_I2C9) + +#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_i2c_resource +{ + I2C_Type *base; /*!< I2C peripheral base address. */ + uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ + +} cmsis_i2c_resource_t; + +typedef union _cmsis_i2c_handle +{ + i2c_master_handle_t master_handle; /*!< master Interupt transfer handle. */ + i2c_slave_handle_t slave_handle; /*!< slave Interupt transfer handle. */ +} cmsis_i2c_handle_t; + +typedef struct _cmsis_i2c_interrupt_driver_state +{ + cmsis_i2c_resource_t *resource; /*!< Basic I2C resource. */ + cmsis_i2c_handle_t *handle; + ARM_I2C_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_i2c_interrupt_driver_state_t; + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +typedef const struct _cmsis_i2c_dma_resource +{ + DMA_Type *i2cDmaBase; /*!< DMA peripheral base address for i2c. */ + uint32_t i2cDmaChannel; /*!< DMA channel for i2c. */ +} cmsis_i2c_dma_resource_t; + +typedef struct _cmsis_i2c_dma_driver_state +{ + cmsis_i2c_resource_t *resource; /*!< i2c basic resource. */ + cmsis_i2c_dma_resource_t *dmaResource; /*!< i2c DMA resource. */ + i2c_master_dma_handle_t *master_dma_handle; /*!< i2c DMA transfer handle. */ + dma_handle_t *dmaHandle; /*!< DMA i2c handle. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_i2c_dma_driver_state_t; +#endif + +static const ARM_DRIVER_VERSION s_i2cDriverVersion = {ARM_I2C_API_VERSION, ARM_I2C_DRV_VERSION}; + +static const ARM_I2C_CAPABILITIES s_i2cDriverCapabilities = { + 0, /*< supports 10-bit addressing*/ +}; + +extern uint32_t I2C_GetInstance(I2C_Type *base); + +static ARM_DRIVER_VERSION I2Cx_GetVersion(void) +{ + return s_i2cDriverVersion; +} + +static ARM_I2C_CAPABILITIES I2Cx_GetCapabilities(void) +{ + return s_i2cDriverCapabilities; +} + +#endif + +#if (RTE_I2C0_DMA_EN || RTE_I2C1_DMA_EN || RTE_I2C2_DMA_EN || RTE_I2C3_DMA_EN || RTE_I2C4_DMA_EN || RTE_I2C5_DMA_EN || \ + RTE_I2C6_DMA_EN || RTE_I2C7_DMA_EN || RTE_I2C8_DMA_EN || RTE_I2C9_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +void KSDK_I2C_MASTER_DmaCallback(I2C_Type *base, i2c_master_dma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event; + + if (status == kStatus_Success) /* Occurs after Master Transmit/Receive operation has finished. */ + { + event = ARM_I2C_EVENT_TRANSFER_DONE; + } + + if (userData) + { + ((ARM_I2C_SignalEvent_t)userData)(event); + } +} + +static int32_t I2C_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_dma_driver_state_t *i2c) +{ + if (!(i2c->flags & I2C_FLAG_INIT)) + { + DMA_EnableChannel(i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); + DMA_CreateHandle(i2c->dmaHandle, i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); + + I2C_MasterTransferCreateHandleDMA(i2c->resource->base, i2c->master_dma_handle, KSDK_I2C_MASTER_DmaCallback, + (void *)cb_event, i2c->dmaHandle); + i2c->flags = I2C_FLAG_INIT; + } + return ARM_DRIVER_OK; +} + +int32_t I2C_Master_DmaUninitialize(cmsis_i2c_dma_driver_state_t *i2c) +{ + i2c->flags = I2C_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +int32_t I2C_Master_DmaTransmit( + uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + i2c_master_transfer_t masterXfer; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (i2c->master_dma_handle->state != 0) + { + return ARM_DRIVER_ERROR_BUSY; + } + + masterXfer.slaveAddress = addr; /*7-bit slave address.*/ + masterXfer.direction = kI2C_Write; /*Transfer direction.*/ + masterXfer.subaddress = 0; /*Sub address*/ + masterXfer.subaddressSize = 0; /*Size of command buffer.*/ + masterXfer.data = (uint8_t *)data; /*Transfer buffer.*/ + masterXfer.dataSize = num; /*Transfer size.*/ + masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ + + if (xfer_pending) + { + masterXfer.flags |= kI2C_TransferNoStopFlag; + } + + status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer); + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t I2C_Master_DmaReceive( + uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + i2c_master_transfer_t masterXfer; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (i2c->master_dma_handle->state != 0) + { + return ARM_DRIVER_ERROR_BUSY; + } + + masterXfer.slaveAddress = addr; /*7-bit slave address.*/ + masterXfer.direction = kI2C_Read; /*Transfer direction.*/ + masterXfer.subaddress = 0; /*Sub address*/ + masterXfer.subaddressSize = 0; /*Size of command buffer.*/ + masterXfer.data = data; /*Transfer buffer.*/ + masterXfer.dataSize = num; /*Transfer size.*/ + masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ + + if (xfer_pending) + { + masterXfer.flags |= kI2C_TransferNoStopFlag; + } + + status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer); + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t I2C_Master_DmaGetDataCount(cmsis_i2c_dma_driver_state_t *i2c) +{ + size_t cnt; /*the number of currently transferred data bytes*/ + + I2C_MasterTransferGetCountDMA(i2c->resource->base, i2c->master_dma_handle, &cnt); + return cnt; +} + +int32_t I2C_Master_DmaControl(uint32_t control, uint32_t arg, cmsis_i2c_dma_driver_state_t *i2c) +{ + uint32_t baudRate_Bps; + + switch (control) + { + /* Not supported */ + case ARM_I2C_OWN_ADDRESS: + return ARM_DRIVER_ERROR_UNSUPPORTED; + /*Set Bus Speed; arg = bus speed*/ + case ARM_I2C_BUS_SPEED: + switch (arg) + { + case ARM_I2C_BUS_SPEED_STANDARD: + baudRate_Bps = 100000; + break; + case ARM_I2C_BUS_SPEED_FAST: + baudRate_Bps = 400000; + break; + case ARM_I2C_BUS_SPEED_FAST_PLUS: + baudRate_Bps = 1000000; + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); + return ARM_DRIVER_OK; + /* Not supported */ + case ARM_I2C_BUS_CLEAR: + return ARM_DRIVER_ERROR_UNSUPPORTED; + /*Aborts the data transfer when Master for Transmit or Receive*/ + case ARM_I2C_ABORT_TRANSFER: + /*disable dma*/ + I2C_MasterTransferAbortDMA(i2c->resource->base, i2c->master_dma_handle); + + i2c->master_dma_handle->transferCount = 0; + i2c->master_dma_handle->transfer.data = NULL; + i2c->master_dma_handle->transfer.dataSize = 0; + return ARM_DRIVER_OK; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } +} + +int32_t I2C_Master_DmaPowerControl(ARM_POWER_STATE state, cmsis_i2c_dma_driver_state_t *i2c) +{ + switch (state) + { + /*terminates any pending data transfers, disable i2c moduole and i2c clock and related dma*/ + case ARM_POWER_OFF: + if (i2c->flags & I2C_FLAG_POWER) + { + I2C_Master_DmaControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); + I2C_MasterDeinit(i2c->resource->base); + DMA_DisableChannel(i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); + i2c->flags = I2C_FLAG_INIT; + } + + return ARM_DRIVER_OK; + /* Not supported */ + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + /*enable i2c moduole and i2c clock*/ + case ARM_POWER_FULL: + if (i2c->flags == I2C_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (i2c->flags & I2C_FLAG_POWER) + { + /* Driver already powered */ + break; + } + FLEXCOMM_Init(i2c->resource->base, FLEXCOMM_PERIPH_I2C); + I2C_MasterEnable(i2c->resource->base, true); + i2c->flags |= I2C_FLAG_POWER; + + return ARM_DRIVER_OK; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +ARM_I2C_STATUS I2C_Master_DmaGetStatus(cmsis_i2c_dma_driver_state_t *i2c) +{ + ARM_I2C_STATUS stat; + uint32_t ksdk_i2c_status = I2C_GetStatusFlags(i2c->resource->base); + + stat.busy = !(ksdk_i2c_status & I2C_STAT_MSTPENDING_MASK); /*Busy flag.*/ + stat.direction = i2c->master_dma_handle->transfer.direction; /*Direction: 0=Transmitter, 1=Receiver.*/ + stat.mode = 1; /*Mode: 0=Slave, 1=Master.*/ + stat.arbitration_lost = !(!(ksdk_i2c_status & I2C_STAT_MSTARBLOSS_MASK)); + /*Master lost arbitration (cleared on start of next Master operation)*/ + + return stat; +} + +#endif + +#endif + +#if ((RTE_I2C0 && !RTE_I2C0_DMA_EN) || (RTE_I2C1 && !RTE_I2C1_DMA_EN) || (RTE_I2C2 && !RTE_I2C2_DMA_EN) || \ + (RTE_I2C3 && !RTE_I2C3_DMA_EN) || (RTE_I2C4 && !RTE_I2C4_DMA_EN) || (RTE_I2C5 && !RTE_I2C5_DMA_EN) || \ + (RTE_I2C6 && !RTE_I2C6_DMA_EN) || (RTE_I2C7 && !RTE_I2C7_DMA_EN) || (RTE_I2C8 && !RTE_I2C8_DMA_EN) || \ + (RTE_I2C9 && !RTE_I2C9_DMA_EN)) + +static void KSDK_I2C_SLAVE_InterruptCallback(I2C_Type *base, volatile i2c_slave_transfer_t *xfer, void *param) +{ + uint32_t event; + + switch (xfer->event) + { + case kI2C_SlaveCompletionEvent: /* Occurs after Slave Transmit/Receive operation has finished. */ + event = ARM_I2C_EVENT_TRANSFER_DONE; + break; + default: + event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + break; + } + + if (param) + { + ((ARM_I2C_SignalEvent_t)param)(event); + } +} + +static void KSDK_I2C_MASTER_InterruptCallback(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event; + + switch (status) + { + case kStatus_Success: /* Occurs after Master Transmit/Receive operation has finished. */ + event = ARM_I2C_EVENT_TRANSFER_DONE; + break; + case kStatus_I2C_ArbitrationLost: /*Occurs in master mode when arbitration is lost.*/ + event = ARM_I2C_EVENT_ARBITRATION_LOST; + break; + default: + event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + break; + } + + /* User data is actually CMSIS driver callback. */ + if (userData) + { + ((ARM_I2C_SignalEvent_t)userData)(event); + } +} + +static int32_t I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + if (!(i2c->flags & I2C_FLAG_INIT)) + { + i2c->cb_event = cb_event; /* cb_event is CMSIS driver callback. */ + i2c->flags = I2C_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t *i2c) +{ + i2c->flags = I2C_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +int32_t I2C_Master_InterruptTransmit( + uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + i2c_master_transfer_t masterXfer; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (i2c->handle->master_handle.state != 0) + { + return ARM_DRIVER_ERROR_BUSY; + } + + I2C_MasterEnable(i2c->resource->base, true); + + /*create master_handle*/ + I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), + KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); + + masterXfer.slaveAddress = addr; /*7-bit slave address.*/ + masterXfer.direction = kI2C_Write; /*Transfer direction.*/ + masterXfer.subaddress = (uint32_t)NULL; /*Sub address*/ + masterXfer.subaddressSize = 0; /*Size of command buffer.*/ + masterXfer.data = (uint8_t *)data; /*Transfer buffer.*/ + masterXfer.dataSize = num; /*Transfer size.*/ + masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ + + if (xfer_pending) + { + masterXfer.flags |= kI2C_TransferNoStopFlag; + } + + status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t I2C_Master_InterruptReceive( + uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + i2c_master_transfer_t masterXfer; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (i2c->handle->master_handle.state != 0) + { + return ARM_DRIVER_ERROR_BUSY; + } + + I2C_MasterEnable(i2c->resource->base, true); + + /*create master_handle*/ + I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), + KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); + + masterXfer.slaveAddress = addr; /*7-bit slave address.*/ + masterXfer.direction = kI2C_Read; /*Transfer direction.*/ + masterXfer.subaddress = (uint32_t)NULL; /*Sub address*/ + masterXfer.subaddressSize = 0; /*Size of command buffer.*/ + masterXfer.data = data; /*Transfer buffer.*/ + masterXfer.dataSize = num; /*Transfer size.*/ + masterXfer.flags = kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ + + if (xfer_pending) + { + masterXfer.flags |= kI2C_TransferNoStopFlag; + } + + status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t I2C_Slave_InterruptTransmit(const uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + + /* set Slave enable */ + I2C_SlaveEnable(i2c->resource->base, true); + + /*create slave_handle*/ + I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, + (void *)i2c->cb_event); + + status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), kI2C_SlaveCompletionEvent); + + i2c->handle->slave_handle.transfer.txData = + (uint8_t *)data; /*Pointer to buffer with data to transmit to I2C Master*/ + i2c->handle->slave_handle.transfer.txSize = num; /*Number of data bytes to transmit*/ + i2c->handle->slave_handle.transfer.transferredCount = + 0; /*Number of bytes actually transferred since start or last repeated start. */ + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t I2C_Slave_InterruptReceive(uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + + /* set Slave enable */ + I2C_SlaveEnable(i2c->resource->base, true); + + /*create slave_handle*/ + I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, + (void *)i2c->cb_event); + + status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), kI2C_SlaveCompletionEvent); + + i2c->handle->slave_handle.transfer.rxData = data; /*Pointer to buffer with data to transmit to I2C Master*/ + i2c->handle->slave_handle.transfer.rxSize = num; /*Number of data bytes to transmit*/ + i2c->handle->slave_handle.transfer.transferredCount = + 0; /*Number of bytes actually transferred since start or last repeated start. */ + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +int32_t I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t *i2c) +{ + uint32_t cnt = 0; /*the number of currently transferred data bytes*/ + + if (i2c->resource->base->CFG & I2C_CFG_MSTEN_MASK) + { + cnt = i2c->handle->master_handle.transferCount; + } + else + { + cnt = i2c->handle->slave_handle.transfer.transferredCount; + } + + return cnt; +} + +int32_t I2C_InterruptControl(uint32_t control, uint32_t arg, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + uint32_t baudRate_Bps; + + switch (control) + { + /*Set Own Slave Address; arg = slave address*/ + case ARM_I2C_OWN_ADDRESS: + I2C_SlaveSetAddress(i2c->resource->base, kI2C_SlaveAddressRegister0, arg, false); + /* set Slave address 0 qual */ + i2c->resource->base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(0) | I2C_SLVQUAL0_SLVQUAL0(0); + return ARM_DRIVER_OK; + /*Set Bus Speed; arg = bus speed*/ + case ARM_I2C_BUS_SPEED: + switch (arg) + { + case ARM_I2C_BUS_SPEED_STANDARD: + baudRate_Bps = 100000; + break; + case ARM_I2C_BUS_SPEED_FAST: + baudRate_Bps = 400000; + break; + case ARM_I2C_BUS_SPEED_FAST_PLUS: + baudRate_Bps = 1000000; + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); + return ARM_DRIVER_OK; + // Not supported + case ARM_I2C_BUS_CLEAR: + return ARM_DRIVER_ERROR_UNSUPPORTED; + /*Aborts the data transfer between Master and Slave for Transmit or Receive*/ + case ARM_I2C_ABORT_TRANSFER: + if (i2c->resource->base->CFG & I2C_CFG_MSTEN_MASK) + { + /*disable master interrupt and send STOP signal*/ + I2C_MasterTransferAbort(i2c->resource->base, &(i2c->handle->master_handle)); + + i2c->handle->master_handle.transferCount = 0; + i2c->handle->master_handle.transfer.data = NULL; + i2c->handle->master_handle.transfer.dataSize = 0; + } + /*if slave receive*/ + if ((i2c->resource->base->CFG & I2C_CFG_SLVEN_MASK) && + ((i2c->handle->slave_handle.slaveFsm) == kI2C_SlaveFsmReceive)) + { + /*disable slave interrupt*/ + I2C_SlaveTransferAbort(i2c->resource->base, &(i2c->handle->slave_handle)); + + i2c->handle->slave_handle.transfer.transferredCount = 0; + i2c->handle->slave_handle.transfer.txData = NULL; + i2c->handle->slave_handle.transfer.rxData = NULL; + } + return ARM_DRIVER_OK; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } +} + +static int32_t I2C_InterruptPowerControl(ARM_POWER_STATE state, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + switch (state) + { + /*terminates any pending data transfers, disable i2c moduole and i2c clock*/ + case ARM_POWER_OFF: + if (i2c->flags & I2C_FLAG_POWER) + { + I2C_InterruptControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); + I2C_MasterDeinit(i2c->resource->base); + I2C_SlaveDeinit(i2c->resource->base); + i2c->flags = I2C_FLAG_INIT; + } + + return ARM_DRIVER_OK; + /* Not supported */ + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + /*enable i2c moduole and i2c clock*/ + case ARM_POWER_FULL: + if (i2c->flags == I2C_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (i2c->flags & I2C_FLAG_POWER) + { + /* Driver already powered */ + break; + } + FLEXCOMM_Init(i2c->resource->base, FLEXCOMM_PERIPH_I2C); + i2c->flags |= I2C_FLAG_POWER; + + return ARM_DRIVER_OK; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +ARM_I2C_STATUS I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t *i2c) +{ + ARM_I2C_STATUS stat; + uint32_t ksdk_i2c_status = I2C_GetStatusFlags(i2c->resource->base); + + if (i2c->resource->base->CFG & I2C_CFG_MSTEN_MASK) + { + stat.busy = !(ksdk_i2c_status & I2C_STAT_MSTPENDING_MASK); /*Busy flag.*/ + stat.direction = i2c->handle->master_handle.transfer.direction; /*Direction: 0=Transmitter, 1=Receiver.*/ + stat.mode = 1; /*Mode: 0=Slave, 1=Master.*/ + stat.arbitration_lost = !(!(ksdk_i2c_status & I2C_STAT_MSTARBLOSS_MASK)); + /*Master lost arbitration (cleared on start of next Master operation)*/ + } + + if (i2c->resource->base->CFG & I2C_CFG_SLVEN_MASK) + { + stat.busy = !(ksdk_i2c_status & I2C_STAT_SLVPENDING_MASK); /*Busy flag.*/ + if ((i2c->handle->slave_handle.slaveFsm) == kI2C_SlaveFsmReceive) + { + stat.direction = 1; /*Direction: 0=Transmitter, 1=Receiver.*/ + } + else + { + stat.direction = 0; /*Direction: 0=Transmitter, 1=Receiver.*/ + } + stat.mode = 0; /*Mode: 0=Slave, 1=Master.*/ + } + + return stat; +} + +#endif + +#if defined(I2C0) && RTE_I2C0 +/* User needs to provide the implementation for I2C0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C0_GetFreq(void); +extern void I2C0_InitPins(void); +extern void I2C0_DeinitPins(void); + +cmsis_i2c_resource_t I2C0_Resource = {I2C0, I2C0_GetFreq}; + +#if RTE_I2C0_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_i2c_dma_resource_t I2C0_DmaResource = {RTE_I2C0_Master_DMA_BASE, RTE_I2C0_Master_DMA_CH}; + +i2c_master_dma_handle_t I2C0_DmaHandle; +dma_handle_t I2C0_DmaTxRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c0_dma_driver_state") +cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = { +#else +cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = { +#endif + &I2C0_Resource, &I2C0_DmaResource, &I2C0_DmaHandle, &I2C0_DmaTxRxHandle, +}; + +static int32_t I2C0_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C0_InitPins(); + return I2C_Master_DmaInitialize(cb_event, &I2C0_DmaDriverState); +} + +int32_t I2C0_Master_DmaUninitialize(void) +{ + I2C0_DeinitPins(); + return I2C_Master_DmaUninitialize(&I2C0_DmaDriverState); +} + +int32_t I2C0_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C0_DmaDriverState); +} + +int32_t I2C0_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C0_DmaDriverState); +} + +int32_t I2C0_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C0_DmaDriverState); +} + +int32_t I2C0_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C0_DmaDriverState); +} + +int32_t I2C0_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C0_DmaDriverState); +} + +ARM_I2C_STATUS I2C0_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C0_DmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t I2C0_handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c0_interrupt_driver_state") +cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { +#else +cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { +#endif + &I2C0_Resource, &I2C0_handle, + +}; + +static int32_t I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C0_InitPins(); + return I2C_InterruptInitialize(cb_event, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_InterruptUninitialize(void) +{ + I2C0_DeinitPins(); + return I2C_InterruptUninitialize(&I2C0_InterruptDriverState); +} + +static int32_t I2C0_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C0_InterruptDriverState); +} + +int32_t I2C0_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); +} + +int32_t I2C0_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); +} + +int32_t I2C0_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C0_InterruptDriverState); +} + +int32_t I2C0_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C0_InterruptDriverState); +} + +int32_t I2C0_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C0_InterruptDriverState); +} + +int32_t I2C0_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C0_InterruptDriverState); +} + +ARM_I2C_STATUS I2C0_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C0_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C0 = {I2Cx_GetVersion, I2Cx_GetCapabilities, +#if RTE_I2C0_DMA_EN + I2C0_Master_DmaInitialize, I2C0_Master_DmaUninitialize, I2C0_Master_DmaPowerControl, + I2C0_Master_DmaTransmit, I2C0_Master_DmaReceive, NULL, NULL, I2C0_Master_DmaGetDataCount, + I2C0_Master_DmaControl, I2C0_Master_DmaGetStatus +#else + I2C0_InterruptInitialize, I2C0_InterruptUninitialize, I2C0_InterruptPowerControl, + I2C0_Master_InterruptTransmit, I2C0_Master_InterruptReceive, I2C0_Slave_InterruptTransmit, + I2C0_Slave_InterruptReceive, I2C0_InterruptGetDataCount, I2C0_InterruptControl, + I2C0_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C1) && RTE_I2C1 + +/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C1_GetFreq(void); +extern void I2C1_InitPins(void); +extern void I2C1_DeinitPins(void); + +cmsis_i2c_resource_t I2C1_Resource = {I2C1, I2C1_GetFreq}; + +#if RTE_I2C1_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_i2c_dma_resource_t I2C1_DmaResource = {RTE_I2C1_Master_DMA_BASE, RTE_I2C1_Master_DMA_CH}; + +i2c_master_dma_handle_t I2C1_DmaHandle; +dma_handle_t I2C1_DmaTxRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c1_dma_driver_state") +cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = { +#else +cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = { +#endif + &I2C1_Resource, &I2C1_DmaResource, &I2C1_DmaHandle, &I2C1_DmaTxRxHandle, +}; + +static int32_t I2C1_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C1_InitPins(); + return I2C_Master_DmaInitialize(cb_event, &I2C1_DmaDriverState); +} + +int32_t I2C1_Master_DmaUninitialize(void) +{ + I2C1_DeinitPins(); + return I2C_Master_DmaUninitialize(&I2C1_DmaDriverState); +} + +int32_t I2C1_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C1_DmaDriverState); +} + +int32_t I2C1_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C1_DmaDriverState); +} + +int32_t I2C1_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C1_DmaDriverState); +} + +int32_t I2C1_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C1_DmaDriverState); +} + +int32_t I2C1_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C1_DmaDriverState); +} + +ARM_I2C_STATUS I2C1_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C1_DmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t I2C1_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c1_interrupt_driver_state") +cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { +#else +cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { +#endif + &I2C1_Resource, &I2C1_Handle, +}; + +static int32_t I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C1_InitPins(); + return I2C_InterruptInitialize(cb_event, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_InterruptUninitialize(void) +{ + I2C1_DeinitPins(); + return I2C_InterruptUninitialize(&I2C1_InterruptDriverState); +} + +static int32_t I2C1_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C1_InterruptDriverState); +} + +int32_t I2C1_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); +} + +int32_t I2C1_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); +} + +int32_t I2C1_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C1_InterruptDriverState); +} + +int32_t I2C1_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C1_InterruptDriverState); +} + +int32_t I2C1_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C1_InterruptDriverState); +} + +int32_t I2C1_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C1_InterruptDriverState); +} + +ARM_I2C_STATUS I2C1_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C1_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C1 = {I2Cx_GetVersion, I2Cx_GetCapabilities, +#if RTE_I2C1_DMA_EN + I2C1_Master_DmaInitialize, I2C1_Master_DmaUninitialize, I2C1_Master_DmaPowerControl, + I2C1_Master_DmaTransmit, I2C1_Master_DmaReceive, NULL, NULL, I2C1_Master_DmaGetDataCount, + I2C1_Master_DmaControl, I2C1_Master_DmaGetStatus +#else + I2C1_InterruptInitialize, I2C1_InterruptUninitialize, I2C1_InterruptPowerControl, + I2C1_Master_InterruptTransmit, I2C1_Master_InterruptReceive, I2C1_Slave_InterruptTransmit, + I2C1_Slave_InterruptReceive, I2C1_InterruptGetDataCount, I2C1_InterruptControl, + I2C1_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C2) && RTE_I2C2 + +/* User needs to provide the implementation for I2C2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C2_GetFreq(void); +extern void I2C2_InitPins(void); +extern void I2C2_DeinitPins(void); + +cmsis_i2c_resource_t I2C2_Resource = {I2C2, I2C2_GetFreq}; + +#if RTE_I2C2_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_i2c_dma_resource_t I2C2_DmaResource = {RTE_I2C2_Master_DMA_BASE, RTE_I2C2_Master_DMA_CH}; + +i2c_master_dma_handle_t I2C2_DmaHandle; +dma_handle_t I2C2_DmaTxRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c2_dma_driver_state") +cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = { +#else +cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = { +#endif + &I2C2_Resource, &I2C2_DmaResource, &I2C2_DmaHandle, &I2C2_DmaTxRxHandle, +}; + +static int32_t I2C2_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C2_InitPins(); + return I2C_Master_DmaInitialize(cb_event, &I2C2_DmaDriverState); +} + +int32_t I2C2_Master_DmaUninitialize(void) +{ + I2C2_DeinitPins(); + return I2C_Master_DmaUninitialize(&I2C2_DmaDriverState); +} + +int32_t I2C2_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C2_DmaDriverState); +} + +int32_t I2C2_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C2_DmaDriverState); +} + +int32_t I2C2_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C2_DmaDriverState); +} + +int32_t I2C2_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C2_DmaDriverState); +} + +int32_t I2C2_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C2_DmaDriverState); +} + +ARM_I2C_STATUS I2C2_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C2_DmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t I2C2_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c2_interrupt_driver_state") +cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { +#else +cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { +#endif + &I2C2_Resource, &I2C2_Handle, + +}; + +static int32_t I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C2_InitPins(); + return I2C_InterruptInitialize(cb_event, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_InterruptUninitialize(void) +{ + I2C2_DeinitPins(); + return I2C_InterruptUninitialize(&I2C2_InterruptDriverState); +} + +static int32_t I2C2_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C2_InterruptDriverState); +} + +int32_t I2C2_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); +} + +int32_t I2C2_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); +} + +int32_t I2C2_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C2_InterruptDriverState); +} + +int32_t I2C2_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C2_InterruptDriverState); +} + +int32_t I2C2_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C2_InterruptDriverState); +} + +int32_t I2C2_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C2_InterruptDriverState); +} + +ARM_I2C_STATUS I2C2_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C2_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C2 = {I2Cx_GetVersion, I2Cx_GetCapabilities, +#if RTE_I2C2_DMA_EN + I2C2_Master_DmaInitialize, I2C2_Master_DmaUninitialize, I2C2_Master_DmaPowerControl, + I2C2_Master_DmaTransmit, I2C2_Master_DmaReceive, NULL, NULL, I2C2_Master_DmaGetDataCount, + I2C2_Master_DmaControl, I2C2_Master_DmaGetStatus +#else + I2C2_InterruptInitialize, I2C2_InterruptUninitialize, I2C2_InterruptPowerControl, + I2C2_Master_InterruptTransmit, I2C2_Master_InterruptReceive, I2C2_Slave_InterruptTransmit, + I2C2_Slave_InterruptReceive, I2C2_InterruptGetDataCount, I2C2_InterruptControl, + I2C2_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C3) && RTE_I2C3 + +/* User needs to provide the implementation for I2C3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C3_GetFreq(void); +extern void I2C3_InitPins(void); +extern void I2C3_DeinitPins(void); + +cmsis_i2c_resource_t I2C3_Resource = {I2C3, I2C3_GetFreq}; + +#if RTE_I2C3_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_i2c_dma_resource_t I2C3_DmaResource = {RTE_I2C3_Master_DMA_BASE, RTE_I2C3_Master_DMA_CH}; + +i2c_master_dma_handle_t I2C3_DmaHandle; +dma_handle_t I2C3_DmaTxRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c3_dma_driver_state") +cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = { +#else +cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = { +#endif + &I2C3_Resource, &I2C3_DmaResource, &I2C3_DmaHandle, &I2C3_DmaTxRxHandle, +}; + +static int32_t I2C3_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C3_InitPins(); + return I2C_Master_DmaInitialize(cb_event, &I2C3_DmaDriverState); +} + +int32_t I2C3_Master_DmaUninitialize(void) +{ + I2C3_DeinitPins(); + return I2C_Master_DmaUninitialize(&I2C3_DmaDriverState); +} + +int32_t I2C3_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C3_DmaDriverState); +} + +int32_t I2C3_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C3_DmaDriverState); +} + +int32_t I2C3_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C3_DmaDriverState); +} + +int32_t I2C3_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C3_DmaDriverState); +} + +int32_t I2C3_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C3_DmaDriverState); +} + +ARM_I2C_STATUS I2C3_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C3_DmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t I2C3_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c3_interrupt_driver_state") +cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { +#else +cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { +#endif + &I2C3_Resource, &I2C3_Handle, +}; + +static int32_t I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C3_InitPins(); + return I2C_InterruptInitialize(cb_event, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_InterruptUninitialize(void) +{ + I2C3_DeinitPins(); + return I2C_InterruptUninitialize(&I2C3_InterruptDriverState); +} + +static int32_t I2C3_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C3_InterruptDriverState); +} + +int32_t I2C3_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); +} + +int32_t I2C3_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); +} + +int32_t I2C3_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C3_InterruptDriverState); +} + +int32_t I2C3_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C3_InterruptDriverState); +} + +int32_t I2C3_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C3_InterruptDriverState); +} + +int32_t I2C3_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C3_InterruptDriverState); +} + +ARM_I2C_STATUS I2C3_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C3_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C3 = {I2Cx_GetVersion, I2Cx_GetCapabilities, +#if RTE_I2C3_DMA_EN + I2C3_Master_DmaInitialize, I2C3_Master_DmaUninitialize, I2C3_Master_DmaPowerControl, + I2C3_Master_DmaTransmit, I2C3_Master_DmaReceive, NULL, NULL, I2C3_Master_DmaGetDataCount, + I2C3_Master_DmaControl, I2C3_Master_DmaGetStatus +#else + I2C3_InterruptInitialize, I2C3_InterruptUninitialize, I2C3_InterruptPowerControl, + I2C3_Master_InterruptTransmit, I2C3_Master_InterruptReceive, I2C3_Slave_InterruptTransmit, + I2C3_Slave_InterruptReceive, I2C3_InterruptGetDataCount, I2C3_InterruptControl, + I2C3_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C4) && RTE_I2C4 +/* User needs to provide the implementation for I2C4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C4_GetFreq(void); +extern void I2C4_InitPins(void); +extern void I2C4_DeinitPins(void); + +cmsis_i2c_resource_t I2C4_Resource = {I2C4, I2C4_GetFreq}; + +#if RTE_I2C4_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_i2c_dma_resource_t I2C4_DmaResource = {RTE_I2C4_Master_DMA_BASE, RTE_I2C4_Master_DMA_CH}; + +i2c_master_dma_handle_t I2C4_DmaHandle; +dma_handle_t I2C4_DmaTxRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c4_dma_driver_state") +cmsis_i2c_dma_driver_state_t I2C4_DmaDriverState = { +#else +cmsis_i2c_dma_driver_state_t I2C4_DmaDriverState = { +#endif + &I2C4_Resource, &I2C4_DmaResource, &I2C4_DmaHandle, &I2C4_DmaTxRxHandle, +}; + +static int32_t I2C4_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C4_InitPins(); + return I2C_Master_DmaInitialize(cb_event, &I2C4_DmaDriverState); +} + +int32_t I2C4_Master_DmaUninitialize(void) +{ + I2C4_DeinitPins(); + return I2C_Master_DmaUninitialize(&I2C4_DmaDriverState); +} + +int32_t I2C4_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C4_DmaDriverState); +} + +int32_t I2C4_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C4_DmaDriverState); +} + +int32_t I2C4_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C4_DmaDriverState); +} + +int32_t I2C4_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C4_DmaDriverState); +} + +int32_t I2C4_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C4_DmaDriverState); +} + +ARM_I2C_STATUS I2C4_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C4_DmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t I2C4_handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c4_interrupt_driver_state") +cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = { +#else +cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = { +#endif + &I2C4_Resource, &I2C4_handle, + +}; + +static int32_t I2C4_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C4_InitPins(); + return I2C_InterruptInitialize(cb_event, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_InterruptUninitialize(void) +{ + I2C4_DeinitPins(); + return I2C_InterruptUninitialize(&I2C4_InterruptDriverState); +} + +static int32_t I2C4_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C4_InterruptDriverState); +} + +int32_t I2C4_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C4_InterruptDriverState); +} + +int32_t I2C4_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C4_InterruptDriverState); +} + +int32_t I2C4_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C4_InterruptDriverState); +} + +int32_t I2C4_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C4_InterruptDriverState); +} + +int32_t I2C4_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C4_InterruptDriverState); +} + +int32_t I2C4_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C4_InterruptDriverState); +} + +ARM_I2C_STATUS I2C4_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C4_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C4 = {I2Cx_GetVersion, I2Cx_GetCapabilities, +#if RTE_I2C4_DMA_EN + I2C4_Master_DmaInitialize, I2C4_Master_DmaUninitialize, I2C4_Master_DmaPowerControl, + I2C4_Master_DmaTransmit, I2C4_Master_DmaReceive, NULL, NULL, I2C4_Master_DmaGetDataCount, + I2C4_Master_DmaControl, I2C4_Master_DmaGetStatus +#else + I2C4_InterruptInitialize, I2C4_InterruptUninitialize, I2C4_InterruptPowerControl, + I2C4_Master_InterruptTransmit, I2C4_Master_InterruptReceive, I2C4_Slave_InterruptTransmit, + I2C4_Slave_InterruptReceive, I2C4_InterruptGetDataCount, I2C4_InterruptControl, + I2C4_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C5) && RTE_I2C5 +/* User needs to provide the implementation for I2C5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C5_GetFreq(void); +extern void I2C5_InitPins(void); +extern void I2C5_DeinitPins(void); + +cmsis_i2c_resource_t I2C5_Resource = {I2C5, I2C5_GetFreq}; + +#if RTE_I2C5_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_i2c_dma_resource_t I2C5_DmaResource = {RTE_I2C5_Master_DMA_BASE, RTE_I2C5_Master_DMA_CH}; + +i2c_master_dma_handle_t I2C5_DmaHandle; +dma_handle_t I2C5_DmaTxRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c5_dma_driver_state") +cmsis_i2c_dma_driver_state_t I2C5_DmaDriverState = { +#else +cmsis_i2c_dma_driver_state_t I2C5_DmaDriverState = { +#endif + &I2C5_Resource, &I2C5_DmaResource, &I2C5_DmaHandle, &I2C5_DmaTxRxHandle, +}; + +static int32_t I2C5_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C5_InitPins(); + return I2C_Master_DmaInitialize(cb_event, &I2C5_DmaDriverState); +} + +int32_t I2C5_Master_DmaUninitialize(void) +{ + I2C5_DeinitPins(); + return I2C_Master_DmaUninitialize(&I2C5_DmaDriverState); +} + +int32_t I2C5_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C5_DmaDriverState); +} + +int32_t I2C5_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C5_DmaDriverState); +} + +int32_t I2C5_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C5_DmaDriverState); +} + +int32_t I2C5_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C5_DmaDriverState); +} + +int32_t I2C5_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C5_DmaDriverState); +} + +ARM_I2C_STATUS I2C5_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C5_DmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t I2C5_handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c5_interrupt_driver_state") +cmsis_i2c_interrupt_driver_state_t I2C5_InterruptDriverState = { +#else +cmsis_i2c_interrupt_driver_state_t I2C5_InterruptDriverState = { +#endif + &I2C5_Resource, &I2C5_handle, + +}; + +static int32_t I2C5_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C5_InitPins(); + return I2C_InterruptInitialize(cb_event, &I2C5_InterruptDriverState); +} + +static int32_t I2C5_InterruptUninitialize(void) +{ + I2C5_DeinitPins(); + return I2C_InterruptUninitialize(&I2C5_InterruptDriverState); +} + +static int32_t I2C5_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C5_InterruptDriverState); +} + +int32_t I2C5_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C5_InterruptDriverState); +} + +int32_t I2C5_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C5_InterruptDriverState); +} + +int32_t I2C5_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C5_InterruptDriverState); +} + +int32_t I2C5_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C5_InterruptDriverState); +} + +int32_t I2C5_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C5_InterruptDriverState); +} + +int32_t I2C5_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C5_InterruptDriverState); +} + +ARM_I2C_STATUS I2C5_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C5_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C5 = {I2Cx_GetVersion, I2Cx_GetCapabilities, +#if RTE_I2C5_DMA_EN + I2C5_Master_DmaInitialize, I2C5_Master_DmaUninitialize, I2C5_Master_DmaPowerControl, + I2C5_Master_DmaTransmit, I2C5_Master_DmaReceive, NULL, NULL, I2C5_Master_DmaGetDataCount, + I2C5_Master_DmaControl, I2C5_Master_DmaGetStatus +#else + I2C5_InterruptInitialize, I2C5_InterruptUninitialize, I2C5_InterruptPowerControl, + I2C5_Master_InterruptTransmit, I2C5_Master_InterruptReceive, I2C5_Slave_InterruptTransmit, + I2C5_Slave_InterruptReceive, I2C5_InterruptGetDataCount, I2C5_InterruptControl, + I2C5_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C6) && RTE_I2C6 +/* User needs to provide the implementation for I2C6_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C6_GetFreq(void); +extern void I2C6_InitPins(void); +extern void I2C6_DeinitPins(void); + +cmsis_i2c_resource_t I2C6_Resource = {I2C6, I2C6_GetFreq}; + +#if RTE_I2C6_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_i2c_dma_resource_t I2C6_DmaResource = {RTE_I2C6_Master_DMA_BASE, RTE_I2C6_Master_DMA_CH}; + +i2c_master_dma_handle_t I2C6_DmaHandle; +dma_handle_t I2C6_DmaTxRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c6_dma_driver_state") +cmsis_i2c_dma_driver_state_t I2C6_DmaDriverState = { +#else +cmsis_i2c_dma_driver_state_t I2C6_DmaDriverState = { +#endif + &I2C6_Resource, &I2C6_DmaResource, &I2C6_DmaHandle, &I2C6_DmaTxRxHandle, +}; + +static int32_t I2C6_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C6_InitPins(); + return I2C_Master_DmaInitialize(cb_event, &I2C6_DmaDriverState); +} + +int32_t I2C6_Master_DmaUninitialize(void) +{ + I2C6_DeinitPins(); + return I2C_Master_DmaUninitialize(&I2C6_DmaDriverState); +} + +int32_t I2C6_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C6_DmaDriverState); +} + +int32_t I2C6_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C6_DmaDriverState); +} + +int32_t I2C6_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C6_DmaDriverState); +} + +int32_t I2C6_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C6_DmaDriverState); +} + +int32_t I2C6_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C6_DmaDriverState); +} + +ARM_I2C_STATUS I2C6_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C6_DmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t I2C6_handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c6_interrupt_driver_state") +cmsis_i2c_interrupt_driver_state_t I2C6_InterruptDriverState = { +#else +cmsis_i2c_interrupt_driver_state_t I2C6_InterruptDriverState = { +#endif + &I2C6_Resource, &I2C6_handle, + +}; + +static int32_t I2C6_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C6_InitPins(); + return I2C_InterruptInitialize(cb_event, &I2C6_InterruptDriverState); +} + +static int32_t I2C6_InterruptUninitialize(void) +{ + I2C6_DeinitPins(); + return I2C_InterruptUninitialize(&I2C6_InterruptDriverState); +} + +static int32_t I2C6_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C6_InterruptDriverState); +} + +int32_t I2C6_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C6_InterruptDriverState); +} + +int32_t I2C6_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C6_InterruptDriverState); +} + +int32_t I2C6_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C6_InterruptDriverState); +} + +int32_t I2C6_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C6_InterruptDriverState); +} + +int32_t I2C6_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C6_InterruptDriverState); +} + +int32_t I2C6_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C6_InterruptDriverState); +} + +ARM_I2C_STATUS I2C6_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C6_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C6 = {I2Cx_GetVersion, I2Cx_GetCapabilities, +#if RTE_I2C6_DMA_EN + I2C6_Master_DmaInitialize, I2C6_Master_DmaUninitialize, I2C6_Master_DmaPowerControl, + I2C6_Master_DmaTransmit, I2C6_Master_DmaReceive, NULL, NULL, I2C6_Master_DmaGetDataCount, + I2C6_Master_DmaControl, I2C6_Master_DmaGetStatus +#else + I2C6_InterruptInitialize, I2C6_InterruptUninitialize, I2C6_InterruptPowerControl, + I2C6_Master_InterruptTransmit, I2C6_Master_InterruptReceive, I2C6_Slave_InterruptTransmit, + I2C6_Slave_InterruptReceive, I2C6_InterruptGetDataCount, I2C6_InterruptControl, + I2C6_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C7) && RTE_I2C7 +/* User needs to provide the implementation for I2C7_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C7_GetFreq(void); +extern void I2C7_InitPins(void); +extern void I2C7_DeinitPins(void); + +cmsis_i2c_resource_t I2C7_Resource = {I2C7, I2C7_GetFreq}; + +#if RTE_I2C7_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_i2c_dma_resource_t I2C7_DmaResource = {RTE_I2C7_Master_DMA_BASE, RTE_I2C7_Master_DMA_CH}; + +i2c_master_dma_handle_t I2C7_DmaHandle; +dma_handle_t I2C7_DmaTxRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c7_dma_driver_state") +cmsis_i2c_dma_driver_state_t I2C7_DmaDriverState = { +#else +cmsis_i2c_dma_driver_state_t I2C7_DmaDriverState = { +#endif + &I2C7_Resource, &I2C7_DmaResource, &I2C7_DmaHandle, &I2C7_DmaTxRxHandle, +}; + +static int32_t I2C7_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C7_InitPins(); + return I2C_Master_DmaInitialize(cb_event, &I2C7_DmaDriverState); +} + +int32_t I2C7_Master_DmaUninitialize(void) +{ + I2C7_DeinitPins(); + return I2C_Master_DmaUninitialize(&I2C7_DmaDriverState); +} + +int32_t I2C7_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C7_DmaDriverState); +} + +int32_t I2C7_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C7_DmaDriverState); +} + +int32_t I2C7_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C7_DmaDriverState); +} + +int32_t I2C7_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C7_DmaDriverState); +} + +int32_t I2C7_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C7_DmaDriverState); +} + +ARM_I2C_STATUS I2C7_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C7_DmaDriverState); +} + +#endif + +#else +cmsis_i2c_handle_t I2C7_handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c7_interrupt_driver_state") +cmsis_i2c_interrupt_driver_state_t I2C7_InterruptDriverState = { +#else +cmsis_i2c_interrupt_driver_state_t I2C7_InterruptDriverState = { +#endif + &I2C7_Resource, &I2C7_handle, + +}; + +static int32_t I2C7_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C7_InitPins(); + return I2C_InterruptInitialize(cb_event, &I2C7_InterruptDriverState); +} + +static int32_t I2C7_InterruptUninitialize(void) +{ + I2C7_DeinitPins(); + return I2C_InterruptUninitialize(&I2C7_InterruptDriverState); +} + +static int32_t I2C7_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C7_InterruptDriverState); +} + +int32_t I2C7_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C7_InterruptDriverState); +} + +int32_t I2C7_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C7_InterruptDriverState); +} + +int32_t I2C7_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C7_InterruptDriverState); +} + +int32_t I2C7_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C7_InterruptDriverState); +} + +int32_t I2C7_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C7_InterruptDriverState); +} + +int32_t I2C7_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C7_InterruptDriverState); +} + +ARM_I2C_STATUS I2C7_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C7_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C7 = {I2Cx_GetVersion, I2Cx_GetCapabilities, +#if RTE_I2C7_DMA_EN + I2C7_Master_DmaInitialize, I2C7_Master_DmaUninitialize, I2C7_Master_DmaPowerControl, + I2C7_Master_DmaTransmit, I2C7_Master_DmaReceive, NULL, NULL, I2C7_Master_DmaGetDataCount, + I2C7_Master_DmaControl, I2C7_Master_DmaGetStatus +#else + I2C7_InterruptInitialize, I2C7_InterruptUninitialize, I2C7_InterruptPowerControl, + I2C7_Master_InterruptTransmit, I2C7_Master_InterruptReceive, I2C7_Slave_InterruptTransmit, + I2C7_Slave_InterruptReceive, I2C7_InterruptGetDataCount, I2C7_InterruptControl, + I2C7_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C8) && RTE_I2C8 +/* User needs to provide the implementation for I2C8_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C8_GetFreq(void); +extern void I2C8_InitPins(void); +extern void I2C8_DeinitPins(void); + +cmsis_i2c_resource_t I2C8_Resource = {I2C8, I2C8_GetFreq}; + +#if RTE_I2C8_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_i2c_dma_resource_t I2C8_DmaResource = {RTE_I2C8_Master_DMA_BASE, RTE_I2C8_Master_DMA_CH}; + +i2c_master_dma_handle_t I2C8_DmaHandle; +dma_handle_t I2C8_DmaTxRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c8_dma_driver_state") +cmsis_i2c_dma_driver_state_t I2C8_DmaDriverState = { +#else +cmsis_i2c_dma_driver_state_t I2C8_DmaDriverState = { +#endif + &I2C8_Resource, &I2C8_DmaResource, &I2C8_DmaHandle, &I2C8_DmaTxRxHandle, +}; + +static int32_t I2C8_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C8_InitPins(); + return I2C_Master_DmaInitialize(cb_event, &I2C8_DmaDriverState); +} + +int32_t I2C8_Master_DmaUninitialize(void) +{ + I2C8_DeinitPins(); + return I2C_Master_DmaUninitialize(&I2C8_DmaDriverState); +} + +int32_t I2C8_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C8_DmaDriverState); +} + +int32_t I2C8_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C8_DmaDriverState); +} + +int32_t I2C8_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C8_DmaDriverState); +} + +int32_t I2C8_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C8_DmaDriverState); +} + +int32_t I2C8_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C8_DmaDriverState); +} + +ARM_I2C_STATUS I2C8_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C8_DmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t I2C8_handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c8_interrupt_driver_state") +cmsis_i2c_interrupt_driver_state_t I2C8_InterruptDriverState = { +#else +cmsis_i2c_interrupt_driver_state_t I2C8_InterruptDriverState = { +#endif + &I2C8_Resource, &I2C8_handle, + +}; + +static int32_t I2C8_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C8_InitPins(); + return I2C_InterruptInitialize(cb_event, &I2C8_InterruptDriverState); +} + +static int32_t I2C8_InterruptUninitialize(void) +{ + I2C8_DeinitPins(); + return I2C_InterruptUninitialize(&I2C8_InterruptDriverState); +} + +static int32_t I2C8_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C8_InterruptDriverState); +} + +int32_t I2C8_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C8_InterruptDriverState); +} + +int32_t I2C8_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C8_InterruptDriverState); +} + +int32_t I2C8_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C8_InterruptDriverState); +} + +int32_t I2C8_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C8_InterruptDriverState); +} + +int32_t I2C8_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C8_InterruptDriverState); +} + +int32_t I2C8_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C8_InterruptDriverState); +} + +ARM_I2C_STATUS I2C8_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C8_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C8 = {I2Cx_GetVersion, I2Cx_GetCapabilities, +#if RTE_I2C8_DMA_EN + I2C8_Master_DmaInitialize, I2C8_Master_DmaUninitialize, I2C8_Master_DmaPowerControl, + I2C8_Master_DmaTransmit, I2C8_Master_DmaReceive, NULL, NULL, I2C8_Master_DmaGetDataCount, + I2C8_Master_DmaControl, I2C8_Master_DmaGetStatus +#else + I2C8_InterruptInitialize, I2C8_InterruptUninitialize, I2C8_InterruptPowerControl, + I2C8_Master_InterruptTransmit, I2C8_Master_InterruptReceive, I2C8_Slave_InterruptTransmit, + I2C8_Slave_InterruptReceive, I2C8_InterruptGetDataCount, I2C8_InterruptControl, + I2C8_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C9) && RTE_I2C9 +/* User needs to provide the implementation for I2C9_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C9_GetFreq(void); +extern void I2C9_InitPins(void); +extern void I2C9_DeinitPins(void); + +cmsis_i2c_resource_t I2C9_Resource = {I2C9, I2C9_GetFreq}; + +#if RTE_I2C9_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_i2c_dma_resource_t I2C9_DmaResource = {RTE_I2C9_Master_DMA_BASE, RTE_I2C9_Master_DMA_CH}; + +i2c_master_dma_handle_t I2C9_DmaHandle; +dma_handle_t I2C9_DmaTxRxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c9_dma_driver_state") +cmsis_i2c_dma_driver_state_t I2C9_DmaDriverState = { +#else +cmsis_i2c_dma_driver_state_t I2C9_DmaDriverState = { +#endif + &I2C9_Resource, &I2C9_DmaResource, &I2C9_DmaHandle, &I2C9_DmaTxRxHandle, +}; + +static int32_t I2C9_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C9_InitPins(); + return I2C_Master_DmaInitialize(cb_event, &I2C9_DmaDriverState); +} + +int32_t I2C9_Master_DmaUninitialize(void) +{ + I2C9_DeinitPins(); + return I2C_Master_DmaUninitialize(&I2C9_DmaDriverState); +} + +int32_t I2C9_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C9_DmaDriverState); +} + +int32_t I2C9_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C9_DmaDriverState); +} + +int32_t I2C9_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C9_DmaDriverState); +} + +int32_t I2C9_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C9_DmaDriverState); +} + +int32_t I2C9_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C9_DmaDriverState); +} + +ARM_I2C_STATUS I2C9_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C9_DmaDriverState); +} + +#endif + +#else + +cmsis_i2c_handle_t I2C9_handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("i2c9_interrupt_driver_state") +cmsis_i2c_interrupt_driver_state_t I2C9_InterruptDriverState = { +#else +cmsis_i2c_interrupt_driver_state_t I2C9_InterruptDriverState = { +#endif + &I2C9_Resource, &I2C9_handle, + +}; + +static int32_t I2C9_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ + I2C9_InitPins(); + return I2C_InterruptInitialize(cb_event, &I2C9_InterruptDriverState); +} + +static int32_t I2C9_InterruptUninitialize(void) +{ + I2C9_DeinitPins(); + return I2C_InterruptUninitialize(&I2C9_InterruptDriverState); +} + +static int32_t I2C9_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C9_InterruptDriverState); +} + +int32_t I2C9_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C9_InterruptDriverState); +} + +int32_t I2C9_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C9_InterruptDriverState); +} + +int32_t I2C9_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C9_InterruptDriverState); +} + +int32_t I2C9_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C9_InterruptDriverState); +} + +int32_t I2C9_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C9_InterruptDriverState); +} + +int32_t I2C9_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C9_InterruptDriverState); +} + +ARM_I2C_STATUS I2C9_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C9_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C9 = {I2Cx_GetVersion, I2Cx_GetCapabilities, +#if RTE_I2C9_DMA_EN + I2C9_Master_DmaInitialize, I2C9_Master_DmaUninitialize, I2C9_Master_DmaPowerControl, + I2C9_Master_DmaTransmit, I2C9_Master_DmaReceive, NULL, NULL, I2C9_Master_DmaGetDataCount, + I2C9_Master_DmaControl, I2C9_Master_DmaGetStatus +#else + I2C9_InterruptInitialize, I2C9_InterruptUninitialize, I2C9_InterruptPowerControl, + I2C9_Master_InterruptTransmit, I2C9_Master_InterruptReceive, I2C9_Slave_InterruptTransmit, + I2C9_Slave_InterruptReceive, I2C9_InterruptGetDataCount, I2C9_InterruptControl, + I2C9_InterruptGetStatus +#endif +}; + +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.h new file mode 100644 index 00000000000..0844a072837 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_i2c_cmsis.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FSL_I2C_CMSIS_H_ +#define _FSL_I2C_CMSIS_H_ +#include "fsl_common.h" +#include "Driver_I2C.h" +#include "RTE_Device.h" +#include "fsl_i2c.h" +#include "fsl_flexcomm.h" +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +#include "fsl_i2c_dma.h" +#endif + +#if defined(I2C0) +extern ARM_DRIVER_I2C Driver_I2C0; +#endif + +#if defined(I2C1) +extern ARM_DRIVER_I2C Driver_I2C1; +#endif + +#if defined(I2C2) +extern ARM_DRIVER_I2C Driver_I2C2; +#endif + +#if defined(I2C3) +extern ARM_DRIVER_I2C Driver_I2C3; +#endif + +#if defined(I2C4) +extern ARM_DRIVER_I2C Driver_I2C4; +#endif + +#if defined(I2C5) +extern ARM_DRIVER_I2C Driver_I2C5; +#endif + +#if defined(I2C6) +extern ARM_DRIVER_I2C Driver_I2C6; +#endif + +#if defined(I2C7) +extern ARM_DRIVER_I2C Driver_I2C7; +#endif + +#if defined(I2C8) +extern ARM_DRIVER_I2C Driver_I2C8; +#endif + +#if defined(I2C9) +extern ARM_DRIVER_I2C Driver_I2C9; +#endif + +/* I2C Driver state flags */ +#define I2C_FLAG_UNINIT (0) +#define I2C_FLAG_INIT (1 << 0) +#define I2C_FLAG_POWER (1 << 1) + +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.c new file mode 100644 index 00000000000..202e68d67b3 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.c @@ -0,0 +1,2787 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_spi_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_cmsis" +#endif + + +#if (RTE_SPI0 || RTE_SPI1 || RTE_SPI2 || RTE_SPI3 || RTE_SPI4 || RTE_SPI5 || RTE_SPI6 || RTE_SPI7 || RTE_SPI8 || \ + RTE_SPI9) + +#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ + +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +/* Array of SPI reset number. */ +static const reset_ip_name_t s_spiResetInstance[] = FLEXCOMM_RSTS; +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_spi_resource +{ + SPI_Type *base; + uint32_t instance; + uint32_t (*GetFreq)(void); +} cmsis_spi_resource_t; + +typedef union _cmsis_spi_handle +{ + spi_master_handle_t masterHandle; + spi_slave_handle_t slaveHandle; +} cmsis_spi_handle_t; + +typedef struct _cmsis_spi_interrupt_driver_state +{ + cmsis_spi_resource_t *resource; + cmsis_spi_handle_t *handle; + ARM_SPI_SignalEvent_t cb_event; + uint32_t baudRate_Bps; + uint8_t flags; /*!< Control and state flags. */ +} cmsis_spi_interrupt_driver_state_t; + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +typedef const struct _cmsis_spi_dma_resource +{ + DMA_Type *txdmaBase; + uint32_t txdmaChannel; + + DMA_Type *rxdmaBase; + uint32_t rxdmaChannel; +} cmsis_spi_dma_resource_t; + +typedef union _cmsis_spi_dma_handle +{ + spi_dma_handle_t masterHandle; + spi_dma_handle_t slaveHandle; +} cmsis_spi_dma_handle_t; + +typedef struct _cmsis_spi_dma_driver_state +{ + cmsis_spi_resource_t *resource; + cmsis_spi_dma_resource_t *dmaResource; + cmsis_spi_dma_handle_t *handle; + dma_handle_t *dmaRxDataHandle; + dma_handle_t *dmaTxDataHandle; + + uint32_t baudRate_Bps; + ARM_SPI_SignalEvent_t cb_event; + uint8_t flags; /*!< Control and state flags. */ +} cmsis_spi_dma_driver_state_t; +#endif + +/* Driver Version */ +static const ARM_DRIVER_VERSION s_SPIDriverVersion = {ARM_SPI_API_VERSION, ARM_SPI_DRV_VERSION}; + +/* Driver Capabilities */ +static const ARM_SPI_CAPABILITIES s_SPIDriverCapabilities = { + 1, /* Simplex Mode (Master and Slave) */ + 0, /* TI Synchronous Serial Interface */ + 0, /* Microwire Interface */ + 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +void SPI_MasterCommonControl(uint32_t control, + cmsis_spi_resource_t *resource, + uint8_t *status, + spi_master_config_t *masterConfig) +{ + switch (resource->instance) + { + case 0: +#if defined(RTE_SPI0_SSEL_NUM) + masterConfig->sselNum = RTE_SPI0_SSEL_NUM; +#endif +#if defined(RTE_SPI0_SSEL_POL) + masterConfig->sselPol = RTE_SPI0_SSEL_POL; +#endif + break; + + case 1: +#if defined(RTE_SPI1_SSEL_NUM) + masterConfig->sselNum = RTE_SPI1_SSEL_NUM; +#endif +#if defined(RTE_SPI1_SSEL_POL) + masterConfig->sselPol = RTE_SPI1_SSEL_POL; +#endif + break; + case 2: +#if defined(RTE_SPI2_SSEL_NUM) + masterConfig->sselNum = RTE_SPI2_SSEL_NUM; +#endif +#if defined(RTE_SPI2_SSEL_POL) + masterConfig->sselPol = RTE_SPI2_SSEL_POL; +#endif + break; + + case 3: +#if defined(RTE_SPI3_SSEL_NUM) + masterConfig->sselNum = RTE_SPI3_SSEL_NUM; +#endif +#if defined(RTE_SPI3_SSEL_POL) + masterConfig->sselPol = RTE_SPI3_SSEL_POL; +#endif + break; + + case 4: +#if defined(RTE_SPI4_SSEL_NUM) + masterConfig->sselNum = RTE_SPI4_SSEL_NUM; +#endif +#if defined(RTE_SPI4_SSEL_POL) + masterConfig->sselPol = RTE_SPI4_SSEL_POL; +#endif + break; + + case 5: +#if defined(RTE_SPI5_SSEL_NUM) + masterConfig->sselNum = RTE_SPI5_SSEL_NUM; +#endif +#if defined(RTE_SPI5_SSEL_POL) + masterConfig->sselPol = RTE_SPI5_SSEL_POL; +#endif + break; + + case 6: +#if defined(RTE_SPI6_SSEL_NUM) + masterConfig->sselNum = RTE_SPI6_SSEL_NUM; +#endif +#if defined(RTE_SPI6_SSEL_POL) + masterConfig->sselPol = RTE_SPI6_SSEL_POL; +#endif + break; + + case 7: +#if defined(RTE_SPI7_SSEL_NUM) + masterConfig->sselNum = RTE_SPI7_SSEL_NUM; +#endif +#if defined(RTE_SPI7_SSEL_POL) + masterConfig->sselPol = RTE_SPI7_SSEL_POL; +#endif + break; + + case 8: +#if defined(RTE_SPI8_SSEL_NUM) + masterConfig->sselNum = RTE_SPI8_SSEL_NUM; +#endif +#if defined(RTE_SPI8_SSEL_POL) + masterConfig->sselPol = RTE_SPI8_SSEL_POL; +#endif + break; + + case 9: +#if defined(RTE_SPI9_SSEL_NUM) + masterConfig->sselNum = RTE_SPI9_SSEL_NUM; +#endif +#if defined(RTE_SPI9_SSEL_POL) + masterConfig->sselPol = RTE_SPI9_SSEL_POL; +#endif + break; + + default: + break; + } + + switch (control & ARM_SPI_FRAME_FORMAT_Msk) + { + case ARM_SPI_CPOL0_CPHA0: + masterConfig->polarity = kSPI_ClockPolarityActiveHigh; + masterConfig->phase = kSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL0_CPHA1: + masterConfig->polarity = kSPI_ClockPolarityActiveHigh; + masterConfig->phase = kSPI_ClockPhaseSecondEdge; + break; + + case ARM_SPI_CPOL1_CPHA0: + masterConfig->polarity = kSPI_ClockPolarityActiveLow; + masterConfig->phase = kSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL1_CPHA1: + masterConfig->polarity = kSPI_ClockPolarityActiveLow; + masterConfig->phase = kSPI_ClockPhaseSecondEdge; + break; + + default: + break; + } + + if (control & ARM_SPI_DATA_BITS_Msk) /* setting Number of Data bits */ + { + if ((((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4) && + (((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16)) + { + masterConfig->dataWidth = + (spi_data_width_t)(((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1); + } + } + + switch (control & ARM_SPI_BIT_ORDER_Msk) + { + case ARM_SPI_LSB_MSB: + masterConfig->direction = kSPI_LsbFirst; + break; + case ARM_SPI_MSB_LSB: + masterConfig->direction = kSPI_MsbFirst; + break; + + default: + break; + } +} + +void SPI_SlaveCommonControl(uint32_t control, + cmsis_spi_resource_t *resource, + uint8_t *status, + spi_slave_config_t *slaveConfig) +{ + switch (resource->instance) + { + case 0: +#if defined(RTE_SPI0_SSEL_POL) + slaveConfig->sselPol = RTE_SPI0_SSEL_POL; +#endif + break; + + case 1: +#if defined(RTE_SPI1_SSEL_POL) + slaveConfig->sselPol = RTE_SPI1_SSEL_POL; +#endif + break; + case 2: +#if defined(RTE_SPI2_SSEL_POL) + slaveConfig->sselPol = RTE_SPI2_SSEL_POL; +#endif + break; + + case 3: +#if defined(RTE_SPI3_SSEL_POL) + slaveConfig->sselPol = RTE_SPI3_SSEL_POL; +#endif + break; + + case 4: +#if defined(RTE_SPI4_SSEL_POL) + slaveConfig->sselPol = RTE_SPI4_SSEL_POL; +#endif + break; + + case 5: +#if defined(RTE_SPI5_SSEL_POL) + slaveConfig->sselPol = RTE_SPI5_SSEL_POL; +#endif + break; + + case 6: +#if defined(RTE_SPI6_SSEL_POL) + slaveConfig->sselPol = RTE_SPI6_SSEL_POL; +#endif + break; + + case 7: +#if defined(RTE_SPI7_SSEL_POL) + slaveConfig->sselPol = RTE_SPI7_SSEL_POL; +#endif + break; + + case 8: +#if defined(RTE_SPI8_SSEL_POL) + slaveConfig->sselPol = RTE_SPI8_SSEL_POL; +#endif + break; + + case 9: +#if defined(RTE_SPI9_SSEL_POL) + slaveConfig->sselPol = RTE_SPI9_SSEL_POL; +#endif + break; + + default: + break; + } + + switch (control & ARM_SPI_FRAME_FORMAT_Msk) + { + case ARM_SPI_CPOL0_CPHA0: + slaveConfig->polarity = kSPI_ClockPolarityActiveHigh; + slaveConfig->phase = kSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL0_CPHA1: + slaveConfig->polarity = kSPI_ClockPolarityActiveHigh; + slaveConfig->phase = kSPI_ClockPhaseSecondEdge; + break; + + case ARM_SPI_CPOL1_CPHA0: + slaveConfig->polarity = kSPI_ClockPolarityActiveLow; + slaveConfig->phase = kSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL1_CPHA1: + slaveConfig->polarity = kSPI_ClockPolarityActiveLow; + slaveConfig->phase = kSPI_ClockPhaseSecondEdge; + break; + + default: + break; + } + if (control & ARM_SPI_DATA_BITS_Msk) /* setting Number of Data bits */ + { + if ((((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4) && + (((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16)) + { + slaveConfig->dataWidth = + (spi_data_width_t)(((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1); + } + } + switch (control & ARM_SPI_BIT_ORDER_Msk) + { + case ARM_SPI_LSB_MSB: + slaveConfig->direction = kSPI_LsbFirst; + break; + case ARM_SPI_MSB_LSB: + slaveConfig->direction = kSPI_MsbFirst; + break; + + default: + break; + } +} + +static ARM_DRIVER_VERSION SPIx_GetVersion(void) +{ + return s_SPIDriverVersion; +} + +static ARM_SPI_CAPABILITIES SPIx_GetCapabilities(void) +{ + return s_SPIDriverCapabilities; +} + +#endif + +#if (RTE_SPI0_DMA_EN || RTE_SPI1_DMA_EN || RTE_SPI2_DMA_EN || RTE_SPI3_DMA_EN || RTE_SPI4_DMA_EN || RTE_SPI5_DMA_EN || \ + RTE_SPI6_DMA_EN || RTE_SPI7_DMA_EN || RTE_SPI8_DMA_EN || RTE_SPI9_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +void KSDK_SPI_MasterDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + if (kStatus_SPI_Error == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + + if (userData) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} +void KSDK_SPI_SlaveDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + if (kStatus_SPI_Error == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + /* User data is actually CMSIS driver callback. */ + if (userData) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +static int32_t SPI_DMAInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_dma_driver_state_t *spi) +{ + if (!(spi->flags & SPI_FLAG_INIT)) + { + spi->cb_event = cb_event; + spi->flags = SPI_FLAG_INIT; + } + return ARM_DRIVER_OK; +} + +static int32_t SPI_DMAUninitialize(cmsis_spi_dma_driver_state_t *spi) +{ + spi->flags = SPI_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t SPI_DMAPowerControl(ARM_POWER_STATE state, cmsis_spi_dma_driver_state_t *spi) +{ + switch (state) + { + case ARM_POWER_OFF: + if (spi->flags & SPI_FLAG_POWER) + { + SPI_Deinit(spi->resource->base); + RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); + + DMA_DisableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); + DMA_DisableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + DMA_Deinit(spi->dmaResource->txdmaBase); + DMA_Deinit(spi->dmaResource->rxdmaBase); + + spi->flags = SPI_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + if (spi->flags == SPI_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (spi->flags & SPI_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + /* Enable flexcomm clock gate */ + CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]); + /* Init DMA */ + DMA_Init(spi->dmaResource->rxdmaBase); + DMA_Init(spi->dmaResource->txdmaBase); + spi->flags |= SPI_FLAG_POWER; + + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +static int32_t SPI_DMASend(const void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + + xfer.rxData = NULL; + xfer.txData = (uint8_t *)data; + xfer.dataSize = num; + if (spi->flags & SPI_FLAG_MASTER) + { + xfer.configFlags |= kSPI_FrameAssert; + } + + if (spi->flags & SPI_FLAG_MASTER) + { + status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t SPI_DMAReceive(void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + + xfer.txData = NULL; + xfer.rxData = (uint8_t *)data; + xfer.dataSize = num; + if (spi->flags & SPI_FLAG_MASTER) + { + xfer.configFlags |= kSPI_FrameAssert; + } + + if (spi->flags & SPI_FLAG_MASTER) + { + status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t SPI_DMATransfer(const void *data_out, void *data_in, uint32_t num, cmsis_spi_dma_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + + xfer.txData = (uint8_t *)data_out; + xfer.rxData = (uint8_t *)data_in; + xfer.dataSize = num; + if (spi->flags & SPI_FLAG_MASTER) + { + xfer.configFlags |= kSPI_FrameAssert; + } + + if (spi->flags & SPI_FLAG_MASTER) + { + status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} +static uint32_t SPI_DMAGetCount(cmsis_spi_dma_driver_state_t *spi) +{ + uint32_t cnt; + size_t bytes; + + bytes = DMA_GetRemainingBytes(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + + if (spi->flags & SPI_FLAG_MASTER) + { + cnt = spi->handle->masterHandle.transferSize - bytes; + } + else + { + cnt = spi->handle->slaveHandle.transferSize - bytes; + } + + return cnt; +} + +static int32_t SPI_DMAControl(uint32_t control, uint32_t arg, cmsis_spi_dma_driver_state_t *spi) +{ + if (!(spi->flags & SPI_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + switch (control & ARM_SPI_CONTROL_Msk) + { + case ARM_SPI_MODE_INACTIVE: + SPI_Enable(spi->resource->base, false); + break; + case ARM_SPI_MODE_MASTER: + spi->baudRate_Bps = arg; + spi->flags |= SPI_FLAG_MASTER; + break; + + case ARM_SPI_MODE_SLAVE: + spi->flags &= ~SPI_FLAG_MASTER; + break; + + case ARM_SPI_SET_BUS_SPEED: + if (!(spi->flags & SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq()); + + spi->baudRate_Bps = arg; + return ARM_DRIVER_OK; + + case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */ + if (!(spi->flags & SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return spi->baudRate_Bps; + + case ARM_SPI_CONTROL_SS: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_SPI_ABORT_TRANSFER: + if (spi->flags & SPI_FLAG_MASTER) + { + SPI_MasterTransferAbortDMA(spi->resource->base, &spi->handle->masterHandle); + } + else + { + SPI_SlaveTransferAbortDMA(spi->resource->base, &spi->handle->slaveHandle); + } + return ARM_DRIVER_OK; + + case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */ + SPI_SetDummyData(spi->resource->base, (uint8_t)arg); + return ARM_DRIVER_OK; + + case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */ + /* Mode is not supported by current driver. */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */ + /* Mode is not supported by current driver. */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + + default: + break; + } + + if (spi->flags & SPI_FLAG_MASTER) + { + switch (control & ARM_SPI_SS_MASTER_MODE_Msk) + { + /* + * Note: + * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or + * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured + * by user in extern file. Besides, ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver. + */ + case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */ + break; + case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */ + break; + case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */ + break; + case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */ + break; + default: + break; + } + spi_master_config_t masterConfig; + SPI_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = spi->baudRate_Bps; + SPI_MasterCommonControl(control, spi->resource, &spi->flags, &masterConfig); + + if (spi->flags & SPI_FLAG_CONFIGURED) + { + SPI_Deinit(spi->resource->base); + RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); + } + SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq()); + + DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); + DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority3); + DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority2); + DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); + DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + + SPI_MasterTransferCreateHandleDMA(spi->resource->base, &(spi->handle->masterHandle), KSDK_SPI_MasterDMACallback, + (void *)spi->cb_event, spi->dmaTxDataHandle, spi->dmaRxDataHandle); + spi->flags |= SPI_FLAG_CONFIGURED; + } + else + { + /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */ + switch (control & ARM_SPI_SS_SLAVE_MODE_Msk) + { + case ARM_SPI_SS_SLAVE_HW: + break; + case ARM_SPI_SS_SLAVE_SW: + break; + default: + break; + } + + spi_slave_config_t slaveConfig; + SPI_SlaveGetDefaultConfig(&slaveConfig); + SPI_SlaveCommonControl(control, spi->resource, &spi->flags, &slaveConfig); + + if (spi->flags & SPI_FLAG_CONFIGURED) + { + SPI_Deinit(spi->resource->base); + RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); + } + SPI_SlaveInit(spi->resource->base, &slaveConfig); + + DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); + DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority0); + DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority1); + DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); + DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + + SPI_SlaveTransferCreateHandleDMA(spi->resource->base, &(spi->handle->slaveHandle), KSDK_SPI_SlaveDMACallback, + (void *)spi->cb_event, spi->dmaTxDataHandle, spi->dmaRxDataHandle); + + spi->flags |= SPI_FLAG_CONFIGURED; + } + + return ARM_DRIVER_OK; +} + +ARM_SPI_STATUS SPI_DMAGetStatus(cmsis_spi_dma_driver_state_t *spi) +{ + ARM_SPI_STATUS stat; + + if (spi->flags & SPI_FLAG_MASTER) + { + stat.busy = + ((spi->handle->masterHandle.txInProgress == true) || (spi->handle->masterHandle.rxInProgress == true)) ? + (0U) : + (1U); + stat.data_lost = (kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U); + } + else + { + stat.busy = + ((spi->handle->slaveHandle.txInProgress == true) || (spi->handle->slaveHandle.rxInProgress == true)) ? + (0U) : + (1U); + stat.data_lost = (kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U); + } + stat.mode_fault = 0U; + stat.reserved = 0U; + + return stat; +} +#endif /* defined(FSL_FEATURE_SOC_DMA_COUNT) */ + +#endif + +#if ((RTE_SPI0 && !RTE_SPI0_DMA_EN) || (RTE_SPI1 && !RTE_SPI1_DMA_EN) || (RTE_SPI2 && !RTE_SPI2_DMA_EN) || \ + (RTE_SPI3 && !RTE_SPI3_DMA_EN) || (RTE_SPI4 && !RTE_SPI4_DMA_EN) || (RTE_SPI5 && !RTE_SPI5_DMA_EN) || \ + (RTE_SPI6 && !RTE_SPI6_DMA_EN) || (RTE_SPI7 && !RTE_SPI7_DMA_EN) || (RTE_SPI8 && !RTE_SPI8_DMA_EN) || \ + (RTE_SPI9 && !RTE_SPI9_DMA_EN)) + +void KSDK_SPI_MasterInterruptCallback(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0; + + if ((kStatus_Success == status) || (kStatus_SPI_Idle == status)) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + if (kStatus_SPI_Error == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + + /* User data is actually CMSIS driver callback. */ + if (userData) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +void KSDK_SPI_SlaveInterruptCallback(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0; + + if ((kStatus_Success == status) || (kStatus_SPI_Idle == status)) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + if (kStatus_SPI_Error == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + + /* User data is actually CMSIS driver callback. */ + if (userData) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +static int32_t SPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_interrupt_driver_state_t *spi) +{ + if (!(spi->flags & SPI_FLAG_INIT)) + { + spi->cb_event = cb_event; + spi->flags = SPI_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t SPI_InterruptUninitialize(cmsis_spi_interrupt_driver_state_t *spi) +{ + spi->flags = SPI_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t SPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_spi_interrupt_driver_state_t *spi) +{ + switch (state) + { + case ARM_POWER_OFF: + if (spi->flags & SPI_FLAG_POWER) + { + SPI_Deinit(spi->resource->base); + /* Reset Periphera instance, and disable the clock gate */ + RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); + spi->flags = SPI_FLAG_INIT; + } + break; + + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + if (spi->flags == SPI_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (spi->flags & SPI_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + /* Enable flexcomm clock gate */ + CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]); + spi->flags |= SPI_FLAG_POWER; + + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t SPI_InterruptSend(const void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + + xfer.rxData = NULL; + xfer.txData = (uint8_t *)data; + xfer.dataSize = num; + if (spi->flags & SPI_FLAG_MASTER) + { + xfer.configFlags |= kSPI_FrameAssert; + } + + if (spi->flags & SPI_FLAG_MASTER) + { + status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t SPI_InterruptReceive(void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + + xfer.txData = NULL; + xfer.rxData = (uint8_t *)data; + xfer.dataSize = num; + if (spi->flags & SPI_FLAG_MASTER) + { + xfer.configFlags |= kSPI_FrameAssert; + } + + if (spi->flags & SPI_FLAG_MASTER) + { + status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t SPI_InterruptTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_spi_interrupt_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + + xfer.txData = (uint8_t *)data_out; + xfer.rxData = (uint8_t *)data_in; + xfer.dataSize = num; + if (spi->flags & SPI_FLAG_MASTER) + { + xfer.configFlags |= kSPI_FrameAssert; + } + + if (spi->flags & SPI_FLAG_MASTER) + { + status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} +static uint32_t SPI_InterruptGetCount(cmsis_spi_interrupt_driver_state_t *spi) +{ + if (spi->flags & SPI_FLAG_MASTER) + { + return spi->handle->masterHandle.totalByteCount - spi->handle->masterHandle.rxRemainingBytes; + } + else + { + return spi->handle->slaveHandle.toReceiveCount - spi->handle->slaveHandle.rxRemainingBytes; + } +} + +static int32_t SPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_spi_interrupt_driver_state_t *spi) +{ + if (!(spi->flags & SPI_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + switch (control & ARM_SPI_CONTROL_Msk) + { + case ARM_SPI_MODE_INACTIVE: /* SPI mode Inactive */ + FLEXCOMM_Init(spi->resource->base, FLEXCOMM_PERIPH_NONE); + break; + + case ARM_SPI_MODE_MASTER: /* SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps */ + spi->baudRate_Bps = arg; + spi->flags |= SPI_FLAG_MASTER; + break; + + case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on MISO, Input on MOSI) */ + spi->flags &= ~SPI_FLAG_MASTER; + break; + + case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */ + if (!(spi->flags & SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return spi->baudRate_Bps; + + case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */ + if (!(spi->flags & SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq()); + spi->baudRate_Bps = arg; + + return ARM_DRIVER_OK; + + case ARM_SPI_CONTROL_SS: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */ + if (spi->flags & SPI_FLAG_MASTER) + { + SPI_MasterTransferAbort(spi->resource->base, &spi->handle->masterHandle); + } + else + { + SPI_SlaveTransferAbort(spi->resource->base, &spi->handle->slaveHandle); + } + return ARM_DRIVER_OK; + + case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */ + SPI_SetDummyData(spi->resource->base, (uint8_t)arg); + return ARM_DRIVER_OK; + + case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */ + /* Mode is not supported by current driver. */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */ + /* Mode is not supported by current driver. */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + + default: + break; + } + + if (spi->flags & SPI_FLAG_MASTER) + { + switch (control & ARM_SPI_SS_MASTER_MODE_Msk) + { + /* + * Note: + * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or + * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured + * by user in extern file. Besides ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver. + */ + case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */ + break; + case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */ + break; + case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */ + break; + case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */ + break; + default: + break; + } + + spi_master_config_t masterConfig; + SPI_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = spi->baudRate_Bps; + + SPI_MasterCommonControl(control, spi->resource, &spi->flags, &masterConfig); + + if (spi->flags & SPI_FLAG_CONFIGURED) + { + SPI_Deinit(spi->resource->base); + RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); + } + SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq()); + SPI_MasterTransferCreateHandle(spi->resource->base, &spi->handle->masterHandle, + KSDK_SPI_MasterInterruptCallback, (void *)spi->cb_event); + spi->flags |= SPI_FLAG_CONFIGURED; + } + else + { + /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */ + switch (control & ARM_SPI_SS_SLAVE_MODE_Msk) + { + case ARM_SPI_SS_SLAVE_HW: + break; + case ARM_SPI_SS_SLAVE_SW: + break; + default: + break; + } + + spi_slave_config_t slaveConfig; + SPI_SlaveGetDefaultConfig(&slaveConfig); + + SPI_SlaveCommonControl(control, spi->resource, &spi->flags, &slaveConfig); + + if (spi->flags & SPI_FLAG_CONFIGURED) + { + SPI_Deinit(spi->resource->base); + RESET_PeripheralReset(s_spiResetInstance[spi->resource->instance]); + } + SPI_SlaveInit(spi->resource->base, &slaveConfig); + SPI_SlaveTransferCreateHandle(spi->resource->base, &spi->handle->slaveHandle, KSDK_SPI_SlaveInterruptCallback, + (void *)spi->cb_event); + spi->flags |= SPI_FLAG_CONFIGURED; + } + + return ARM_DRIVER_OK; +} + +ARM_SPI_STATUS SPI_InterruptGetStatus(cmsis_spi_interrupt_driver_state_t *spi) +{ + ARM_SPI_STATUS stat; + + if (spi->flags & SPI_FLAG_MASTER) + { + stat.busy = + ((spi->handle->masterHandle.txRemainingBytes > 0) || (spi->handle->masterHandle.rxRemainingBytes > 0)) ? + (0U) : + (1U); + stat.data_lost = (kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U); + } + else + { + stat.busy = + ((spi->handle->slaveHandle.txRemainingBytes > 0) || (spi->handle->slaveHandle.rxRemainingBytes > 0)) ? + (0U) : + (1U); + stat.data_lost = (kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U); + } + stat.mode_fault = 0U; + stat.reserved = 0U; + + return stat; +} + +#endif + +#if defined(SPI0) && RTE_SPI0 + +/* User needs to provide the implementation for SPI0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI0_GetFreq(void); +extern void SPI0_InitPins(void); +extern void SPI0_DeinitPins(void); + +cmsis_spi_resource_t SPI0_Resource = {SPI0, 0, SPI0_GetFreq}; + +#if RTE_SPI0_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_spi_dma_resource_t SPI0_DMAResource = {RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH, RTE_SPI0_DMA_RX_DMA_BASE, + RTE_SPI0_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI0_DmaHandle; +static dma_handle_t SPI0_DmaTxDataHandle; +static dma_handle_t SPI0_DmaRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi0_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = { +#endif + &SPI0_Resource, &SPI0_DMAResource, &SPI0_DmaHandle, &SPI0_DmaTxDataHandle, &SPI0_DmaRxDataHandle, + +}; + +static int32_t SPI0_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI0_InitPins(); + return SPI_DMAInitialize(cb_event, &SPI0_DMADriverState); +} + +static int32_t SPI0_DMAUninitialize(void) +{ + SPI0_DeinitPins(); + return SPI_DMAUninitialize(&SPI0_DMADriverState); +} + +static int32_t SPI0_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI0_DMADriverState); +} + +static int32_t SPI0_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI0_DMADriverState); +} + +static int32_t SPI0_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI0_DMADriverState); +} + +static int32_t SPI0_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI0_DMADriverState); +} + +static uint32_t SPI0_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI0_DMADriverState); +} + +static int32_t SPI0_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI0_DMADriverState); +} + +static ARM_SPI_STATUS SPI0_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI0_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI0_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi0_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = { +#endif + &SPI0_Resource, &SPI0_Handle, +}; + +static int32_t SPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI0_InitPins(); + return SPI_InterruptInitialize(cb_event, &SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptUninitialize(void) +{ + SPI0_DeinitPins(); + return SPI_InterruptUninitialize(&SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI0_InterruptDriverState); +} + +static uint32_t SPI0_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI0_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI0_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI0_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI0 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if RTE_SPI0_DMA_EN + SPI0_DMAInitialize, SPI0_DMAUninitialize, SPI0_DMAPowerControl, SPI0_DMASend, + SPI0_DMAReceive, SPI0_DMATransfer, SPI0_DMAGetCount, SPI0_DMAControl, + SPI0_DMAGetStatus +#else + SPI0_InterruptInitialize, SPI0_InterruptUninitialize, SPI0_InterruptPowerControl, + SPI0_InterruptSend, SPI0_InterruptReceive, SPI0_InterruptTransfer, SPI0_InterruptGetCount, + SPI0_InterruptControl, SPI0_InterruptGetStatus +#endif +}; + +#endif /* SPI0 */ + +#if defined(SPI1) && RTE_SPI1 +/* User needs to provide the implementation for SPI1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI1_GetFreq(void); +extern void SPI1_InitPins(void); +extern void SPI1_DeinitPins(void); +cmsis_spi_resource_t SPI1_Resource = {SPI1, 1, SPI1_GetFreq}; + +#if RTE_SPI1_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_spi_dma_resource_t SPI1_DMAResource = {RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, RTE_SPI1_DMA_RX_DMA_BASE, + RTE_SPI1_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI1_DmaHandle; +static dma_handle_t SPI1_DmaTxDataHandle; +static dma_handle_t SPI1_DmaRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi1_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = { +#endif + &SPI1_Resource, &SPI1_DMAResource, &SPI1_DmaHandle, &SPI1_DmaRxDataHandle, &SPI1_DmaTxDataHandle, +}; + +static int32_t SPI1_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI1_InitPins(); + return SPI_DMAInitialize(cb_event, &SPI1_DMADriverState); +} + +static int32_t SPI1_DMAUninitialize(void) +{ + SPI1_DeinitPins(); + return SPI_DMAUninitialize(&SPI1_DMADriverState); +} + +static int32_t SPI1_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI1_DMADriverState); +} + +static int32_t SPI1_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI1_DMADriverState); +} + +static int32_t SPI1_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI1_DMADriverState); +} + +static int32_t SPI1_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI1_DMADriverState); +} + +static uint32_t SPI1_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI1_DMADriverState); +} + +static int32_t SPI1_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI1_DMADriverState); +} + +static ARM_SPI_STATUS SPI1_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI1_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI1_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi1_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = { +#endif + &SPI1_Resource, &SPI1_Handle, +}; + +static int32_t SPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI1_InitPins(); + return SPI_InterruptInitialize(cb_event, &SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptUninitialize(void) +{ + SPI1_DeinitPins(); + return SPI_InterruptUninitialize(&SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI1_InterruptDriverState); +} + +static uint32_t SPI1_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI1_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI1_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI1_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI1 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if RTE_SPI1_DMA_EN + SPI1_DMAInitialize, SPI1_DMAUninitialize, SPI1_DMAPowerControl, SPI1_DMASend, + SPI1_DMAReceive, SPI1_DMATransfer, SPI1_DMAGetCount, SPI1_DMAControl, + SPI1_DMAGetStatus +#else + SPI1_InterruptInitialize, SPI1_InterruptUninitialize, SPI1_InterruptPowerControl, + SPI1_InterruptSend, SPI1_InterruptReceive, SPI1_InterruptTransfer, SPI1_InterruptGetCount, + SPI1_InterruptControl, SPI1_InterruptGetStatus +#endif +}; + +#endif /* SPI1 */ + +#if defined(SPI2) && RTE_SPI2 + +/* User needs to provide the implementation for SPI2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI2_GetFreq(void); +extern void SPI2_InitPins(void); +extern void SPI2_DeinitPins(void); + +cmsis_spi_resource_t SPI2_Resource = {SPI2, 2, SPI2_GetFreq}; + +#if RTE_SPI2_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_spi_dma_resource_t SPI2_DMAResource = {RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, RTE_SPI2_DMA_RX_DMA_BASE, + RTE_SPI2_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI2_DmaHandle; +static dma_handle_t SPI2_DmaTxDataHandle; +static dma_handle_t SPI2_DmaRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi2_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = { +#endif + &SPI2_Resource, &SPI2_DMAResource, &SPI2_DmaHandle, &SPI2_DmaRxDataHandle, &SPI2_DmaTxDataHandle, +}; + +static int32_t SPI2_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI2_InitPins(); + return SPI_DMAInitialize(cb_event, &SPI2_DMADriverState); +} + +static int32_t SPI2_DMAUninitialize(void) +{ + SPI2_DeinitPins(); + return SPI_DMAUninitialize(&SPI2_DMADriverState); +} + +static int32_t SPI2_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI2_DMADriverState); +} + +static int32_t SPI2_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI2_DMADriverState); +} + +static int32_t SPI2_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI2_DMADriverState); +} + +static int32_t SPI2_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI2_DMADriverState); +} + +static uint32_t SPI2_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI2_DMADriverState); +} + +static int32_t SPI2_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI2_DMADriverState); +} + +static ARM_SPI_STATUS SPI2_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI2_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI2_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi2_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = { +#endif + &SPI2_Resource, &SPI2_Handle, +}; + +static int32_t SPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI2_InitPins(); + return SPI_InterruptInitialize(cb_event, &SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptUninitialize(void) +{ + SPI2_DeinitPins(); + return SPI_InterruptUninitialize(&SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI2_InterruptDriverState); +} + +static uint32_t SPI2_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI2_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI2_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI2_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI2 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if RTE_SPI2_DMA_EN + SPI2_DMAInitialize, SPI2_DMAUninitialize, SPI2_DMAPowerControl, SPI2_DMASend, + SPI2_DMAReceive, SPI2_DMATransfer, SPI2_DMAGetCount, SPI2_DMAControl, + SPI2_DMAGetStatus +#else + SPI2_InterruptInitialize, SPI2_InterruptUninitialize, SPI2_InterruptPowerControl, + SPI2_InterruptSend, SPI2_InterruptReceive, SPI2_InterruptTransfer, SPI2_InterruptGetCount, + SPI2_InterruptControl, SPI2_InterruptGetStatus +#endif +}; + +#endif /* SPI2 */ + +#if defined(SPI3) && RTE_SPI3 + +/* User needs to provide the implementation for SPI3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI3_GetFreq(void); +extern void SPI3_InitPins(void); +extern void SPI3_DeinitPins(void); + +cmsis_spi_resource_t SPI3_Resource = {SPI3, 3, SPI3_GetFreq}; + +#if RTE_SPI3_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_spi_dma_resource_t SPI3_DMAResource = {RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH, RTE_SPI3_DMA_RX_DMA_BASE, + RTE_SPI3_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI3_DmaHandle; +static dma_handle_t SPI3_DmaTxDataHandle; +static dma_handle_t SPI3_DmaRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi3_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = { +#endif + &SPI3_Resource, &SPI3_DMAResource, &SPI3_DmaHandle, &SPI3_DmaRxDataHandle, &SPI3_DmaTxDataHandle, +}; + +static int32_t SPI3_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI3_InitPins(); + return SPI_DMAInitialize(cb_event, &SPI3_DMADriverState); +} + +static int32_t SPI3_DMAUninitialize(void) +{ + SPI3_DeinitPins(); + return SPI_DMAUninitialize(&SPI3_DMADriverState); +} + +static int32_t SPI3_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI3_DMADriverState); +} + +static int32_t SPI3_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI3_DMADriverState); +} + +static int32_t SPI3_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI3_DMADriverState); +} + +static int32_t SPI3_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI3_DMADriverState); +} + +static uint32_t SPI3_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI3_DMADriverState); +} + +static int32_t SPI3_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI3_DMADriverState); +} + +static ARM_SPI_STATUS SPI3_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI3_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI3_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi3_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = { +#endif + &SPI3_Resource, &SPI3_Handle, +}; + +static int32_t SPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI3_InitPins(); + return SPI_InterruptInitialize(cb_event, &SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptUninitialize(void) +{ + SPI3_DeinitPins(); + return SPI_InterruptUninitialize(&SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI3_InterruptDriverState); +} + +static uint32_t SPI3_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI3_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI3_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI3_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI3 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if RTE_SPI3_DMA_EN + SPI3_DMAInitialize, SPI3_DMAUninitialize, SPI3_DMAPowerControl, SPI3_DMASend, + SPI3_DMAReceive, SPI3_DMATransfer, SPI3_DMAGetCount, SPI3_DMAControl, + SPI3_DMAGetStatus +#else + SPI3_InterruptInitialize, SPI3_InterruptUninitialize, SPI3_InterruptPowerControl, + SPI3_InterruptSend, SPI3_InterruptReceive, SPI3_InterruptTransfer, SPI3_InterruptGetCount, + SPI3_InterruptControl, SPI3_InterruptGetStatus +#endif +}; + +#endif /* SPI3 */ + +#if defined(SPI4) && RTE_SPI4 + +/* User needs to provide the implementation for SPI4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI4_GetFreq(void); +extern void SPI4_InitPins(void); +extern void SPI4_DeinitPins(void); + +cmsis_spi_resource_t SPI4_Resource = {SPI4, 4, SPI4_GetFreq}; + +#if RTE_SPI4_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_spi_dma_resource_t SPI4_DMAResource = {RTE_SPI4_DMA_TX_DMA_BASE, RTE_SPI4_DMA_TX_CH, RTE_SPI4_DMA_RX_DMA_BASE, + RTE_SPI4_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI4_DmaHandle; +static dma_handle_t SPI4_DmaTxDataHandle; +static dma_handle_t SPI4_DmaRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi4_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = { +#endif + &SPI4_Resource, &SPI4_DMAResource, &SPI4_DmaHandle, &SPI4_DmaRxDataHandle, &SPI4_DmaTxDataHandle, +}; + +static int32_t SPI4_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI4_InitPins(); + return SPI_DMAInitialize(cb_event, &SPI4_DMADriverState); +} + +static int32_t SPI4_DMAUninitialize(void) +{ + SPI4_DeinitPins(); + return SPI_DMAUninitialize(&SPI4_DMADriverState); +} + +static int32_t SPI4_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI4_DMADriverState); +} + +static int32_t SPI4_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI4_DMADriverState); +} + +static int32_t SPI4_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI4_DMADriverState); +} + +static int32_t SPI4_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI4_DMADriverState); +} + +static uint32_t SPI4_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI4_DMADriverState); +} + +static int32_t SPI4_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI4_DMADriverState); +} + +static ARM_SPI_STATUS SPI4_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI4_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI4_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi4_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = { +#endif + &SPI4_Resource, &SPI4_Handle, +}; + +static int32_t SPI4_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI4_InitPins(); + return SPI_InterruptInitialize(cb_event, &SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptUninitialize(void) +{ + SPI4_DeinitPins(); + return SPI_InterruptUninitialize(&SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI4_InterruptDriverState); +} + +static uint32_t SPI4_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI4_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI4_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI4_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI4 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if RTE_SPI4_DMA_EN + SPI4_DMAInitialize, SPI4_DMAUninitialize, SPI4_DMAPowerControl, SPI4_DMASend, + SPI4_DMAReceive, SPI4_DMATransfer, SPI4_DMAGetCount, SPI4_DMAControl, + SPI4_DMAGetStatus +#else + SPI4_InterruptInitialize, SPI4_InterruptUninitialize, SPI4_InterruptPowerControl, + SPI4_InterruptSend, SPI4_InterruptReceive, SPI4_InterruptTransfer, SPI4_InterruptGetCount, + SPI4_InterruptControl, SPI4_InterruptGetStatus +#endif +}; + +#endif /* SPI4 */ + +#if defined(SPI5) && RTE_SPI5 + +/* User needs to provide the implementation for SPI5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI5_GetFreq(void); +extern void SPI5_InitPins(void); +extern void SPI5_DeinitPins(void); + +cmsis_spi_resource_t SPI5_Resource = {SPI5, 5, SPI5_GetFreq}; + +#if RTE_SPI5_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_spi_dma_resource_t SPI5_DMAResource = {RTE_SPI5_DMA_TX_DMA_BASE, RTE_SPI5_DMA_TX_CH, RTE_SPI5_DMA_RX_DMA_BASE, + RTE_SPI5_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI5_DmaHandle; +static dma_handle_t SPI5_DmaTxDataHandle; +static dma_handle_t SPI5_DmaRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi5_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = { +#endif + &SPI5_Resource, &SPI5_DMAResource, &SPI5_DmaHandle, &SPI5_DmaRxDataHandle, &SPI5_DmaTxDataHandle, +}; + +static int32_t SPI5_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI5_InitPins(); + return SPI_DMAInitialize(cb_event, &SPI5_DMADriverState); +} + +static int32_t SPI5_DMAUninitialize(void) +{ + SPI5_DeinitPins(); + return SPI_DMAUninitialize(&SPI5_DMADriverState); +} + +static int32_t SPI5_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI5_DMADriverState); +} + +static int32_t SPI5_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI5_DMADriverState); +} + +static int32_t SPI5_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI5_DMADriverState); +} + +static int32_t SPI5_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI5_DMADriverState); +} + +static uint32_t SPI5_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI5_DMADriverState); +} + +static int32_t SPI5_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI5_DMADriverState); +} + +static ARM_SPI_STATUS SPI5_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI5_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI5_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi5_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = { +#endif + &SPI5_Resource, &SPI5_Handle, +}; + +static int32_t SPI5_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI5_InitPins(); + return SPI_InterruptInitialize(cb_event, &SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptUninitialize(void) +{ + SPI5_DeinitPins(); + return SPI_InterruptUninitialize(&SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI5_InterruptDriverState); +} + +static uint32_t SPI5_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI5_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI5_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI5_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI5 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if RTE_SPI5_DMA_EN + SPI5_DMAInitialize, SPI5_DMAUninitialize, SPI5_DMAPowerControl, SPI5_DMASend, + SPI5_DMAReceive, SPI5_DMATransfer, SPI5_DMAGetCount, SPI5_DMAControl, + SPI5_DMAGetStatus +#else + SPI5_InterruptInitialize, SPI5_InterruptUninitialize, SPI5_InterruptPowerControl, + SPI5_InterruptSend, SPI5_InterruptReceive, SPI5_InterruptTransfer, SPI5_InterruptGetCount, + SPI5_InterruptControl, SPI5_InterruptGetStatus +#endif +}; + +#endif /* SPI5 */ + +#if defined(SPI6) && RTE_SPI6 + +/* User needs to provide the implementation for SPI6_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI6_GetFreq(void); +extern void SPI6_InitPins(void); +extern void SPI6_DeinitPins(void); + +cmsis_spi_resource_t SPI6_Resource = {SPI6, 6, SPI6_GetFreq}; + +#if RTE_SPI6_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_spi_dma_resource_t SPI6_DMAResource = {RTE_SPI6_DMA_TX_DMA_BASE, RTE_SPI6_DMA_TX_CH, RTE_SPI6_DMA_RX_DMA_BASE, + RTE_SPI6_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI6_DmaHandle; +static dma_handle_t SPI6_DmaTxDataHandle; +static dma_handle_t SPI6_DmaRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi6_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = { +#endif + &SPI6_Resource, &SPI6_DMAResource, &SPI6_DmaHandle, &SPI6_DmaRxDataHandle, &SPI6_DmaTxDataHandle, +}; + +static int32_t SPI6_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI6_InitPins(); + return SPI_DMAInitialize(cb_event, &SPI6_DMADriverState); +} + +static int32_t SPI6_DMAUninitialize(void) +{ + SPI6_DeinitPins(); + return SPI_DMAUninitialize(&SPI6_DMADriverState); +} + +static int32_t SPI6_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI6_DMADriverState); +} + +static int32_t SPI6_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI6_DMADriverState); +} + +static int32_t SPI6_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI6_DMADriverState); +} + +static int32_t SPI6_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI6_DMADriverState); +} + +static uint32_t SPI6_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI6_DMADriverState); +} + +static int32_t SPI6_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI6_DMADriverState); +} + +static ARM_SPI_STATUS SPI6_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI6_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI6_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi6_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = { +#endif + &SPI6_Resource, &SPI6_Handle, +}; + +static int32_t SPI6_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI6_InitPins(); + return SPI_InterruptInitialize(cb_event, &SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptUninitialize(void) +{ + SPI6_DeinitPins(); + return SPI_InterruptUninitialize(&SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI6_InterruptDriverState); +} + +static uint32_t SPI6_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI6_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI6_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI6_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI6 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if RTE_SPI6_DMA_EN + SPI6_DMAInitialize, SPI6_DMAUninitialize, SPI6_DMAPowerControl, SPI6_DMASend, + SPI6_DMAReceive, SPI6_DMATransfer, SPI6_DMAGetCount, SPI6_DMAControl, + SPI6_DMAGetStatus +#else + SPI6_InterruptInitialize, SPI6_InterruptUninitialize, SPI6_InterruptPowerControl, + SPI6_InterruptSend, SPI6_InterruptReceive, SPI6_InterruptTransfer, SPI6_InterruptGetCount, + SPI6_InterruptControl, SPI6_InterruptGetStatus +#endif +}; + +#endif /* SPI6 */ + +#if defined(SPI7) && RTE_SPI7 + +/* User needs to provide the implementation for SPI7_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI7_GetFreq(void); +extern void SPI7_InitPins(void); +extern void SPI7_DeinitPins(void); + +cmsis_spi_resource_t SPI7_Resource = {SPI7, 7, SPI7_GetFreq}; + +#if RTE_SPI7_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_spi_dma_resource_t SPI7_DMAResource = {RTE_SPI7_DMA_TX_DMA_BASE, RTE_SPI7_DMA_TX_CH, RTE_SPI7_DMA_RX_DMA_BASE, + RTE_SPI7_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI7_DmaHandle; +static dma_handle_t SPI7_DmaTxDataHandle; +static dma_handle_t SPI7_DmaRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi7_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = { +#endif + &SPI7_Resource, &SPI7_DMAResource, &SPI7_DmaHandle, &SPI7_DmaRxDataHandle, &SPI7_DmaTxDataHandle, +}; + +static int32_t SPI7_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI7_InitPins(); + return SPI_DMAInitialize(cb_event, &SPI7_DMADriverState); +} + +static int32_t SPI7_DMAUninitialize(void) +{ + SPI7_DeinitPins(); + return SPI_DMAUninitialize(&SPI7_DMADriverState); +} + +static int32_t SPI7_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI7_DMADriverState); +} + +static int32_t SPI7_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI7_DMADriverState); +} + +static int32_t SPI7_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI7_DMADriverState); +} + +static int32_t SPI7_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI7_DMADriverState); +} + +static uint32_t SPI7_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI7_DMADriverState); +} + +static int32_t SPI7_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI7_DMADriverState); +} + +static ARM_SPI_STATUS SPI7_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI7_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI7_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi7_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = { +#endif + &SPI7_Resource, &SPI7_Handle, +}; + +static int32_t SPI7_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI7_InitPins(); + return SPI_InterruptInitialize(cb_event, &SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptUninitialize(void) +{ + SPI7_DeinitPins(); + return SPI_InterruptUninitialize(&SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI7_InterruptDriverState); +} + +static uint32_t SPI7_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI7_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI7_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI7_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI7 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if RTE_SPI7_DMA_EN + SPI7_DMAInitialize, SPI7_DMAUninitialize, SPI7_DMAPowerControl, SPI7_DMASend, + SPI7_DMAReceive, SPI7_DMATransfer, SPI7_DMAGetCount, SPI7_DMAControl, + SPI7_DMAGetStatus +#else + SPI7_InterruptInitialize, SPI7_InterruptUninitialize, SPI7_InterruptPowerControl, + SPI7_InterruptSend, SPI7_InterruptReceive, SPI7_InterruptTransfer, SPI7_InterruptGetCount, + SPI7_InterruptControl, SPI7_InterruptGetStatus +#endif +}; + +#endif /* SPI7 */ + +#if defined(SPI8) && RTE_SPI8 + +/* User needs to provide the implementation for SPI8_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI8_GetFreq(void); +extern void SPI8_InitPins(void); +extern void SPI8_DeinitPins(void); + +cmsis_spi_resource_t SPI8_Resource = {SPI8, 8, SPI8_GetFreq}; + +#if RTE_SPI8_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_spi_dma_resource_t SPI8_DMAResource = {RTE_SPI8_DMA_TX_DMA_BASE, RTE_SPI8_DMA_TX_CH, RTE_SPI8_DMA_RX_DMA_BASE, + RTE_SPI8_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI8_DmaHandle; +static dma_handle_t SPI8_DmaTxDataHandle; +static dma_handle_t SPI8_DmaRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi8_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = { +#endif + &SPI8_Resource, &SPI8_DMAResource, &SPI8_DmaHandle, &SPI8_DmaRxDataHandle, &SPI8_DmaTxDataHandle, +}; + +static int32_t SPI8_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI8_InitPins(); + return SPI_DMAInitialize(cb_event, &SPI8_DMADriverState); +} + +static int32_t SPI8_DMAUninitialize(void) +{ + SPI8_DeinitPins(); + return SPI_DMAUninitialize(&SPI8_DMADriverState); +} + +static int32_t SPI8_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI8_DMADriverState); +} + +static int32_t SPI8_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI8_DMADriverState); +} + +static int32_t SPI8_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI8_DMADriverState); +} + +static int32_t SPI8_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI8_DMADriverState); +} + +static uint32_t SPI8_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI8_DMADriverState); +} + +static int32_t SPI8_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI8_DMADriverState); +} + +static ARM_SPI_STATUS SPI8_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI8_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI8_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi8_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = { +#endif + &SPI8_Resource, &SPI8_Handle, +}; + +static int32_t SPI8_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI8_InitPins(); + return SPI_InterruptInitialize(cb_event, &SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptUninitialize(void) +{ + SPI8_DeinitPins(); + return SPI_InterruptUninitialize(&SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI8_InterruptDriverState); +} + +static uint32_t SPI8_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI8_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI8_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI8_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI8 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if RTE_SPI8_DMA_EN + SPI8_DMAInitialize, SPI8_DMAUninitialize, SPI8_DMAPowerControl, SPI8_DMASend, + SPI8_DMAReceive, SPI8_DMATransfer, SPI8_DMAGetCount, SPI8_DMAControl, + SPI8_DMAGetStatus +#else + SPI8_InterruptInitialize, SPI8_InterruptUninitialize, SPI8_InterruptPowerControl, + SPI8_InterruptSend, SPI8_InterruptReceive, SPI8_InterruptTransfer, SPI8_InterruptGetCount, + SPI8_InterruptControl, SPI8_InterruptGetStatus +#endif +}; + +#endif /* SPI8 */ + +#if defined(SPI9) && RTE_SPI9 + +/* User needs to provide the implementation for SPI9_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI9_GetFreq(void); +extern void SPI9_InitPins(void); +extern void SPI9_DeinitPins(void); + +cmsis_spi_resource_t SPI9_Resource = {SPI9, 9, SPI9_GetFreq}; + +#if RTE_SPI9_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_spi_dma_resource_t SPI9_DMAResource = {RTE_SPI9_DMA_TX_DMA_BASE, RTE_SPI9_DMA_TX_CH, RTE_SPI9_DMA_RX_DMA_BASE, + RTE_SPI9_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI9_DmaHandle; +static dma_handle_t SPI9_DmaTxDataHandle; +static dma_handle_t SPI9_DmaRxDataHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi9_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = { +#endif + &SPI9_Resource, &SPI9_DMAResource, &SPI9_DmaHandle, &SPI9_DmaRxDataHandle, &SPI9_DmaTxDataHandle, +}; + +static int32_t SPI9_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI9_InitPins(); + return SPI_DMAInitialize(cb_event, &SPI9_DMADriverState); +} + +static int32_t SPI9_DMAUninitialize(void) +{ + SPI9_DeinitPins(); + return SPI_DMAUninitialize(&SPI9_DMADriverState); +} + +static int32_t SPI9_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI9_DMADriverState); +} + +static int32_t SPI9_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI9_DMADriverState); +} + +static int32_t SPI9_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI9_DMADriverState); +} + +static int32_t SPI9_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI9_DMADriverState); +} + +static uint32_t SPI9_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI9_DMADriverState); +} + +static int32_t SPI9_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI9_DMADriverState); +} + +static ARM_SPI_STATUS SPI9_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI9_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI9_Handle; + +#if defined(__CC_ARM) +ARMCC_SECTION("spi9_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = { +#endif + &SPI9_Resource, &SPI9_Handle, +}; + +static int32_t SPI9_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ + SPI9_InitPins(); + return SPI_InterruptInitialize(cb_event, &SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptUninitialize(void) +{ + SPI9_DeinitPins(); + return SPI_InterruptUninitialize(&SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI9_InterruptDriverState); +} + +static uint32_t SPI9_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI9_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI9_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI9_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI9 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if RTE_SPI9_DMA_EN + SPI9_DMAInitialize, SPI9_DMAUninitialize, SPI9_DMAPowerControl, SPI9_DMASend, + SPI9_DMAReceive, SPI9_DMATransfer, SPI9_DMAGetCount, SPI9_DMAControl, + SPI9_DMAGetStatus +#else + SPI9_InterruptInitialize, SPI9_InterruptUninitialize, SPI9_InterruptPowerControl, + SPI9_InterruptSend, SPI9_InterruptReceive, SPI9_InterruptTransfer, SPI9_InterruptGetCount, + SPI9_InterruptControl, SPI9_InterruptGetStatus +#endif +}; + +#endif /* SPI9 */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.h new file mode 100644 index 00000000000..f4f93e6a3c7 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_spi_cmsis.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _FSL_SPI_CMSIS_H_ +#define _FSL_SPI_CMSIS_H_ + +#include "fsl_spi.h" +#include "RTE_Device.h" +#include "Driver_SPI.h" +#if defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT) +#include "fsl_spi_dma.h" +#endif + +#if defined(SPI0) +extern ARM_DRIVER_SPI Driver_SPI0; +#endif /* SPI0 */ + +#if defined(SPI1) +extern ARM_DRIVER_SPI Driver_SPI1; +#endif /* SPI1 */ + +#if defined(SPI2) +extern ARM_DRIVER_SPI Driver_SPI2; +#endif /* SPI2 */ + +#if defined(SPI3) +extern ARM_DRIVER_SPI Driver_SPI3; +#endif /* SPI3 */ + +#if defined(SPI4) +extern ARM_DRIVER_SPI Driver_SPI4; +#endif /* SPI4 */ + +#if defined(SPI5) +extern ARM_DRIVER_SPI Driver_SPI5; +#endif /* SPI5 */ + +#if defined(SPI6) +extern ARM_DRIVER_SPI Driver_SPI6; +#endif /* SPI6 */ + +#if defined(SPI7) +extern ARM_DRIVER_SPI Driver_SPI7; +#endif /* SPI7 */ + +#if defined(SPI8) +extern ARM_DRIVER_SPI Driver_SPI8; +#endif /* SPI8 */ + +#if defined(SPI9) +extern ARM_DRIVER_SPI Driver_SPI9; +#endif /* SPI9 */ + +#define SPI_FLAG_UNINIT (0) +#define SPI_FLAG_INIT (1 << 0) +#define SPI_FLAG_POWER (1 << 1) +#define SPI_FLAG_CONFIGURED (1 << 2) +#define SPI_FLAG_MASTER (1 << 3) + +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.c new file mode 100644 index 00000000000..ce87f559246 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.c @@ -0,0 +1,2713 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "fsl_usart_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_cmsis" +#endif + + +#if (RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || RTE_USART4 || RTE_USART5 || RTE_USART6 || RTE_USART7 || \ + RTE_USART8 || RTE_USART9) + +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_usart_resource +{ + USART_Type *base; /*!< usart peripheral base address. */ + uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ +} cmsis_usart_resource_t; + +typedef struct _cmsis_usart_non_blocking_driver_state +{ + cmsis_usart_resource_t *resource; /*!< Basic usart resource. */ + usart_handle_t *handle; /*!< Interupt transfer handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_usart_non_blocking_driver_state_t; + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +typedef const struct _cmsis_usart_dma_resource +{ + DMA_Type *txDmaBase; /*!< DMA peripheral base address for TX. */ + uint32_t txDmaChannel; /*!< DMA channel for usart TX. */ + + DMA_Type *rxDmaBase; /*!< DMA peripheral base address for RX. */ + uint32_t rxDmaChannel; /*!< DMA channel for usart RX. */ +} cmsis_usart_dma_resource_t; + +typedef struct _cmsis_usart_dma_driver_state +{ + cmsis_usart_resource_t *resource; /*!< usart basic resource. */ + cmsis_usart_dma_resource_t *dmaResource; /*!< usart DMA resource. */ + usart_dma_handle_t *handle; /*!< usart DMA transfer handle. */ + dma_handle_t *rxHandle; /*!< DMA RX handle. */ + dma_handle_t *txHandle; /*!< DMA TX handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_usart_dma_driver_state_t; +#endif + +enum _usart_transfer_states +{ + kUSART_TxIdle, /*!< TX idle. */ + kUSART_TxBusy, /*!< TX busy. */ + kUSART_RxIdle, /*!< RX idle. */ + kUSART_RxBusy /*!< RX busy. */ +}; + +/* Driver Version */ +static const ARM_DRIVER_VERSION s_usartDriverVersion = {ARM_USART_API_VERSION, ARM_USART_DRV_VERSION}; + +static const ARM_USART_CAPABILITIES s_usartDriverCapabilities = { + 1, /* supports usart (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports usart Single-wire mode */ + 0, /* supports usart IrDA mode */ + 0, /* supports usart Smart Card mode */ + 0, /* Smart Card Clock generator */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ + 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ +}; + +/* + * Common control function used by usart_NonBlockingControl/usart_DmaControl/usart_EdmaControl + */ +static int32_t USART_CommonControl(uint32_t control, + uint32_t arg, + cmsis_usart_resource_t *resource, + uint8_t *isConfigured) +{ + usart_config_t config; + + USART_GetDefaultConfig(&config); + + switch (control & ARM_USART_CONTROL_Msk) + { + case ARM_USART_MODE_ASYNCHRONOUS: + /* USART Baudrate */ + config.baudRate_Bps = arg; + break; + + /* TX/RX IO is controlled in application layer. */ + case ARM_USART_CONTROL_TX: + if (arg) + { + config.enableTx = true; + } + else + { + config.enableTx = false; + } + return ARM_DRIVER_OK; + + case ARM_USART_CONTROL_RX: + if (arg) + { + config.enableRx = true; + } + else + { + config.enableRx = false; + } + + return ARM_DRIVER_OK; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_PARITY_Msk) + { + case ARM_USART_PARITY_NONE: + config.parityMode = kUSART_ParityDisabled; + break; + case ARM_USART_PARITY_EVEN: + config.parityMode = kUSART_ParityEven; + break; + case ARM_USART_PARITY_ODD: + config.parityMode = kUSART_ParityOdd; + break; + default: + return ARM_USART_ERROR_PARITY; + } + + switch (control & ARM_USART_STOP_BITS_Msk) + { + case ARM_USART_STOP_BITS_1: + /* The GetDefaultConfig has already set for this case. */ + break; + case ARM_USART_STOP_BITS_2: + config.stopBitCount = kUSART_TwoStopBit; + break; + default: + return ARM_USART_ERROR_STOP_BITS; + } + + /* If usart is already configured, deinit it first. */ + if ((*isConfigured) & USART_FLAG_CONFIGURED) + { + USART_Deinit(resource->base); + *isConfigured &= ~USART_FLAG_CONFIGURED; + } + + config.enableTx = true; + config.enableRx = true; + + if (kStatus_USART_BaudrateNotSupport == USART_Init(resource->base, &config, resource->GetFreq())) + { + return ARM_USART_ERROR_BAUDRATE; + } + + *isConfigured |= USART_FLAG_CONFIGURED; + + return ARM_DRIVER_OK; +} + +static ARM_DRIVER_VERSION USARTx_GetVersion(void) +{ + return s_usartDriverVersion; +} + +static ARM_USART_CAPABILITIES USARTx_GetCapabilities(void) +{ + return s_usartDriverCapabilities; +} + +static int32_t USARTx_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS USARTx_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status; + + modem_status.cts = 0U; + modem_status.dsr = 0U; + modem_status.ri = 0U; + modem_status.dcd = 0U; + modem_status.reserved = 0U; + + return modem_status; +} + +#endif + +#if (RTE_USART0_DMA_EN || RTE_USART1_DMA_EN || RTE_USART2_DMA_EN || RTE_USART3_DMA_EN || RTE_USART4_DMA_EN || \ + RTE_USART5_DMA_EN || RTE_USART6_DMA_EN || RTE_USART7_DMA_EN || RTE_USART8_DMA_EN || RTE_USART9_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +void KSDK_USART_DmaCallback(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_USART_TxIdle == status) + { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + + if (kStatus_USART_RxIdle == status) + { + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + } + + /* User data is actually CMSIS driver callback. */ + if (userData) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t USART_DmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_usart_dma_driver_state_t *usart) +{ + if (!(usart->flags & USART_FLAG_INIT)) + { + usart->cb_event = cb_event; + usart->flags = USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t USART_DmaUninitialize(cmsis_usart_dma_driver_state_t *usart) +{ + usart->flags = USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t USART_DmaPowerControl(ARM_POWER_STATE state, cmsis_usart_dma_driver_state_t *usart) +{ + usart_config_t config; + + switch (state) + { + case ARM_POWER_OFF: + if (usart->flags & USART_FLAG_POWER) + { + USART_Deinit(usart->resource->base); + DMA_DisableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); + DMA_DisableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); + usart->flags = USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (usart->flags == USART_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (usart->flags & USART_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + USART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + /* Set up DMA setting. */ + DMA_EnableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); + DMA_EnableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); + + DMA_CreateHandle(usart->rxHandle, usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); + DMA_CreateHandle(usart->txHandle, usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); + + /* Setup the usart. */ + USART_Init(usart->resource->base, &config, usart->resource->GetFreq()); + USART_TransferCreateHandleDMA(usart->resource->base, usart->handle, KSDK_USART_DmaCallback, + (void *)usart->cb_event, usart->txHandle, usart->rxHandle); + + usart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED); + + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t USART_DmaSend(const void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.data = (uint8_t *)data; + xfer.dataSize = num; + + status = USART_TransferSendDMA(usart->resource->base, usart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_DmaReceive(void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.data = data; + xfer.dataSize = num; + + status = USART_TransferReceiveDMA(usart->resource->base, usart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_DmaTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_usart_dma_driver_state_t *usart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static int32_t USART_DmaGetTxCount(cmsis_usart_dma_driver_state_t *usart) +{ + /* Does not support */ + return ARM_DRIVER_ERROR; +} + +static int32_t USART_DmaGetRxCount(cmsis_usart_dma_driver_state_t *usart) +{ + /* Does not support */ + return ARM_DRIVER_ERROR; +} + +static int32_t USART_DmaControl(uint32_t control, uint32_t arg, cmsis_usart_dma_driver_state_t *usart) +{ + /* Must be power on. */ + if (!(usart->flags & USART_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + USART_EnableTxDMA(usart->resource->base, false); + DMA_AbortTransfer(usart->handle->txDmaHandle); + usart->handle->txState = kUSART_TxIdle; + return ARM_DRIVER_OK; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + USART_EnableRxDMA(usart->resource->base, false); + DMA_AbortTransfer(usart->handle->rxDmaHandle); + usart->handle->rxState = kUSART_RxIdle; + return ARM_DRIVER_OK; + + default: + break; + } + + return USART_CommonControl(control, arg, usart->resource, &usart->flags); +} + +static ARM_USART_STATUS USART_DmaGetStatus(cmsis_usart_dma_driver_state_t *usart) +{ + ARM_USART_STATUS stat; + uint32_t ksdk_usart_status = usart->resource->base->STAT; + + stat.tx_busy = ((kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U)); + stat.rx_busy = ((kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U)); + + stat.tx_underflow = 0U; + stat.rx_overflow = 0U; + + stat.rx_break = (!(!(ksdk_usart_status & USART_STAT_RXBRK_MASK))); + + stat.rx_framing_error = (!(!(ksdk_usart_status & USART_STAT_FRAMERRINT_MASK))); + stat.rx_parity_error = (!(!(ksdk_usart_status & USART_STAT_PARITYERRINT_MASK))); + stat.reserved = 0U; + + return stat; +} +#endif + +#endif + +#if ((RTE_USART0 && !RTE_USART0_DMA_EN) || (RTE_USART1 && !RTE_USART1_DMA_EN) || (RTE_USART2 && !RTE_USART2_DMA_EN) || \ + (RTE_USART3 && !RTE_USART3_DMA_EN) || (RTE_USART4 && !RTE_USART4_DMA_EN) || (RTE_USART5 && !RTE_USART5_DMA_EN) || \ + (RTE_USART6 && !RTE_USART6_DMA_EN) || (RTE_USART7 && !RTE_USART7_DMA_EN) || (RTE_USART8 && !RTE_USART8_DMA_EN) || \ + (RTE_USART9 && !RTE_USART9_DMA_EN)) + +void KSDK_USART_NonBlockingCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_USART_TxIdle == status) + { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + if (kStatus_USART_RxIdle == status) + { + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + } + + /* User data is actually CMSIS driver callback. */ + if (userData) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t USART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event, + cmsis_usart_non_blocking_driver_state_t *usart) +{ + if (!(usart->flags & USART_FLAG_INIT)) + { + usart->cb_event = cb_event; + usart->flags = USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t USART_NonBlockingUninitialize(cmsis_usart_non_blocking_driver_state_t *usart) +{ + usart->flags = USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t USART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_usart_non_blocking_driver_state_t *usart) +{ + usart_config_t config; + + switch (state) + { + case ARM_POWER_OFF: + if (usart->flags & USART_FLAG_POWER) + { + USART_Deinit(usart->resource->base); + usart->flags = USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (usart->flags == USART_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (usart->flags & USART_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + USART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + USART_Init(usart->resource->base, &config, usart->resource->GetFreq()); + USART_TransferCreateHandle(usart->resource->base, usart->handle, KSDK_USART_NonBlockingCallback, + (void *)usart->cb_event); + usart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED); + + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t USART_NonBlockingSend(const void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.data = (uint8_t *)data; + xfer.dataSize = num; + + status = USART_TransferSendNonBlocking(usart->resource->base, usart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_NonBlockingReceive(void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.data = data; + xfer.dataSize = num; + + status = USART_TransferReceiveNonBlocking(usart->resource->base, usart->handle, &xfer, NULL); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_NonBlockingTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_usart_non_blocking_driver_state_t *usart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static uint32_t USART_NonBlockingGetTxCount(cmsis_usart_non_blocking_driver_state_t *usart) +{ + uint32_t cnt; + + /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ + if (kUSART_TxIdle == usart->handle->txState) + { + cnt = usart->handle->txDataSizeAll; + } + else + { + cnt = usart->handle->txDataSizeAll - usart->handle->txDataSize; + } + + return cnt; +} + +static uint32_t USART_NonBlockingGetRxCount(cmsis_usart_non_blocking_driver_state_t *usart) +{ + uint32_t cnt; + + if (kUSART_RxIdle == usart->handle->rxState) + { + cnt = usart->handle->rxDataSizeAll; + } + else + { + cnt = usart->handle->rxDataSizeAll - usart->handle->rxDataSize; + } + + return cnt; +} + +static int32_t USART_NonBlockingControl(uint32_t control, uint32_t arg, cmsis_usart_non_blocking_driver_state_t *usart) +{ + /* Must be power on. */ + if (!(usart->flags & USART_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; + usart->handle->txDataSize = 0; + usart->handle->txState = kUSART_TxIdle; + return ARM_DRIVER_OK; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; + usart->handle->rxDataSize = 0U; + usart->handle->rxState = kUSART_RxIdle; + return ARM_DRIVER_OK; + + default: + break; + } + + return USART_CommonControl(control, arg, usart->resource, &usart->flags); +} + +static ARM_USART_STATUS USART_NonBlockingGetStatus(cmsis_usart_non_blocking_driver_state_t *usart) +{ + ARM_USART_STATUS stat; + uint32_t ksdk_usart_status = usart->resource->base->STAT; + + stat.tx_busy = ((kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U)); + stat.rx_busy = ((kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U)); + + stat.tx_underflow = 0U; + stat.rx_overflow = 0U; + + stat.rx_break = (!(!(ksdk_usart_status & USART_STAT_RXBRK_MASK))); + + stat.rx_framing_error = (!(!(ksdk_usart_status & USART_STAT_FRAMERRINT_MASK))); + stat.rx_parity_error = (!(!(ksdk_usart_status & USART_STAT_PARITYERRINT_MASK))); + stat.reserved = 0U; + + return stat; +} + +#endif + +#if defined(USART0) && RTE_USART0 + +/* User needs to provide the implementation for USART0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART0_GetFreq(void); +extern void USART0_InitPins(void); +extern void USART0_DeinitPins(void); + +cmsis_usart_resource_t usart0_Resource = {USART0, USART0_GetFreq}; + +/* usart0 Driver Control Block */ + +#if RTE_USART0_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart0_DmaResource = { + RTE_USART0_DMA_TX_DMA_BASE, RTE_USART0_DMA_TX_CH, RTE_USART0_DMA_RX_DMA_BASE, RTE_USART0_DMA_RX_CH, +}; + +usart_dma_handle_t USART0_DmaHandle; +dma_handle_t USART0_DmaRxHandle; +dma_handle_t USART0_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("usart0_dma_driver_state") +cmsis_usart_dma_driver_state_t usart0_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart0_DmaDriverState = { +#endif + &usart0_Resource, &usart0_DmaResource, &USART0_DmaHandle, &USART0_DmaRxHandle, &USART0_DmaTxHandle, +}; + +static int32_t USART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART0_InitPins(); + return USART_DmaInitialize(cb_event, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaUninitialize(void) +{ + USART0_DeinitPins(); + return USART_DmaUninitialize(&usart0_DmaDriverState); +} + +static int32_t USART0_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart0_DmaDriverState); +} + +static uint32_t USART0_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart0_DmaDriverState); +} + +static uint32_t USART0_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart0_DmaDriverState); +} + +static int32_t USART0_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart0_DmaDriverState); +} + +static ARM_USART_STATUS USART0_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart0_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART0_Handle; +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) +static uint8_t usart0_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("usart0_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = { +#endif + &usart0_Resource, &USART0_Handle, +}; + +static int32_t USART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART0_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingUninitialize(void) +{ + USART0_DeinitPins(); + return USART_NonBlockingUninitialize(&usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart0_NonBlockingDriverState); +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart0_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart0_NonBlockingDriverState.resource->base, + usart0_NonBlockingDriverState.handle, usart0_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART0_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart0_NonBlockingDriverState); +} + +static uint32_t USART0_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart0_NonBlockingDriverState); +} + +static uint32_t USART0_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart0_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart0_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART0_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart0_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART0 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART0_DMA_EN + USART0_DmaInitialize, USART0_DmaUninitialize, USART0_DmaPowerControl, USART0_DmaSend, USART0_DmaReceive, + USART0_DmaTransfer, USART0_DmaGetTxCount, USART0_DmaGetRxCount, USART0_DmaControl, USART0_DmaGetStatus, +#else + USART0_NonBlockingInitialize, + USART0_NonBlockingUninitialize, + USART0_NonBlockingPowerControl, + USART0_NonBlockingSend, + USART0_NonBlockingReceive, + USART0_NonBlockingTransfer, + USART0_NonBlockingGetTxCount, + USART0_NonBlockingGetRxCount, + USART0_NonBlockingControl, + USART0_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart0 */ + +#if defined(USART1) && RTE_USART1 + +/* User needs to provide the implementation for USART1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART1_GetFreq(void); +extern void USART1_InitPins(void); +extern void USART1_DeinitPins(void); + +cmsis_usart_resource_t usart1_Resource = {USART1, USART1_GetFreq}; + +#if RTE_USART1_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart1_DmaResource = { + RTE_USART1_DMA_TX_DMA_BASE, RTE_USART1_DMA_TX_CH, RTE_USART1_DMA_RX_DMA_BASE, RTE_USART1_DMA_RX_CH, +}; + +usart_dma_handle_t USART1_DmaHandle; +dma_handle_t USART1_DmaRxHandle; +dma_handle_t USART1_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("usart1_dma_driver_state") +cmsis_usart_dma_driver_state_t usart1_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart1_DmaDriverState = { +#endif + &usart1_Resource, &usart1_DmaResource, &USART1_DmaHandle, &USART1_DmaRxHandle, &USART1_DmaTxHandle, +}; + +static int32_t USART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART1_InitPins(); + return USART_DmaInitialize(cb_event, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaUninitialize(void) +{ + USART1_DeinitPins(); + return USART_DmaUninitialize(&usart1_DmaDriverState); +} + +static int32_t USART1_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart1_DmaDriverState); +} + +static uint32_t USART1_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart1_DmaDriverState); +} + +static uint32_t USART1_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart1_DmaDriverState); +} + +static int32_t USART1_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart1_DmaDriverState); +} + +static ARM_USART_STATUS USART1_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart1_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART1_Handle; +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) +static uint8_t usart1_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("usart1_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = { +#endif + &usart1_Resource, &USART1_Handle, +}; + +static int32_t USART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART1_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingUninitialize(void) +{ + USART1_DeinitPins(); + return USART_NonBlockingUninitialize(&usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart1_NonBlockingDriverState); +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart1_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart1_NonBlockingDriverState.resource->base, + usart1_NonBlockingDriverState.handle, usart1_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART1_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart1_NonBlockingDriverState); +} + +static uint32_t USART1_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart1_NonBlockingDriverState); +} + +static uint32_t USART1_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart1_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart1_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART1_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart1_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART1 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART1_DMA_EN + USART1_DmaInitialize, USART1_DmaUninitialize, USART1_DmaPowerControl, USART1_DmaSend, USART1_DmaReceive, + USART1_DmaTransfer, USART1_DmaGetTxCount, USART1_DmaGetRxCount, USART1_DmaControl, USART1_DmaGetStatus, +#else + USART1_NonBlockingInitialize, + USART1_NonBlockingUninitialize, + USART1_NonBlockingPowerControl, + USART1_NonBlockingSend, + USART1_NonBlockingReceive, + USART1_NonBlockingTransfer, + USART1_NonBlockingGetTxCount, + USART1_NonBlockingGetRxCount, + USART1_NonBlockingControl, + USART1_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart1 */ + +#if defined(USART2) && RTE_USART2 + +/* User needs to provide the implementation for USART2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART2_GetFreq(void); +extern void USART2_InitPins(void); +extern void USART2_DeinitPins(void); + +cmsis_usart_resource_t usart2_Resource = {USART2, USART2_GetFreq}; + +/* usart2 Driver Control Block */ + +#if RTE_USART2_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart2_DmaResource = { + RTE_USART2_DMA_TX_DMA_BASE, RTE_USART2_DMA_TX_CH, RTE_USART2_DMA_RX_DMA_BASE, RTE_USART2_DMA_RX_CH, +}; + +usart_dma_handle_t USART2_DmaHandle; +dma_handle_t USART2_DmaRxHandle; +dma_handle_t USART2_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("usart2_dma_driver_state") +cmsis_usart_dma_driver_state_t usart2_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart2_DmaDriverState = { +#endif + &usart2_Resource, &usart2_DmaResource, &USART2_DmaHandle, &USART2_DmaRxHandle, &USART2_DmaTxHandle, +}; + +static int32_t USART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART2_InitPins(); + return USART_DmaInitialize(cb_event, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaUninitialize(void) +{ + USART2_DeinitPins(); + return USART_DmaUninitialize(&usart2_DmaDriverState); +} + +static int32_t USART2_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart2_DmaDriverState); +} + +static uint32_t USART2_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart2_DmaDriverState); +} + +static uint32_t USART2_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart2_DmaDriverState); +} + +static int32_t USART2_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart2_DmaDriverState); +} + +static ARM_USART_STATUS USART2_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart2_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART2_Handle; +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) +static uint8_t usart2_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("usart2_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = { +#endif + &usart2_Resource, &USART2_Handle, +}; + +static int32_t USART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART2_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingUninitialize(void) +{ + USART2_DeinitPins(); + return USART_NonBlockingUninitialize(&usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart2_NonBlockingDriverState); +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart2_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart2_NonBlockingDriverState.resource->base, + usart2_NonBlockingDriverState.handle, usart2_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART2_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart2_NonBlockingDriverState); +} + +static uint32_t USART2_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart2_NonBlockingDriverState); +} + +static uint32_t USART2_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart2_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart2_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART2_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart2_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART2 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART2_DMA_EN + USART2_DmaInitialize, USART2_DmaUninitialize, USART2_DmaPowerControl, USART2_DmaSend, USART2_DmaReceive, + USART2_DmaTransfer, USART2_DmaGetTxCount, USART2_DmaGetRxCount, USART2_DmaControl, USART2_DmaGetStatus, +#else + USART2_NonBlockingInitialize, + USART2_NonBlockingUninitialize, + USART2_NonBlockingPowerControl, + USART2_NonBlockingSend, + USART2_NonBlockingReceive, + USART2_NonBlockingTransfer, + USART2_NonBlockingGetTxCount, + USART2_NonBlockingGetRxCount, + USART2_NonBlockingControl, + USART2_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart2 */ + +#if defined(USART3) && RTE_USART3 + +/* User needs to provide the implementation for USART3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART3_GetFreq(void); +extern void USART3_InitPins(void); +extern void USART3_DeinitPins(void); + +cmsis_usart_resource_t usart3_Resource = {USART3, USART3_GetFreq}; + +/* usart3 Driver Control Block */ +#if RTE_USART3_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart3_DmaResource = { + RTE_USART3_DMA_TX_DMA_BASE, RTE_USART3_DMA_TX_CH, RTE_USART3_DMA_RX_DMA_BASE, RTE_USART3_DMA_RX_CH, +}; + +usart_dma_handle_t USART3_DmaHandle; +dma_handle_t USART3_DmaRxHandle; +dma_handle_t USART3_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("usart3_dma_driver_state") +cmsis_usart_dma_driver_state_t usart3_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart3_DmaDriverState = { +#endif + &usart3_Resource, &usart3_DmaResource, &USART3_DmaHandle, &USART3_DmaRxHandle, &USART3_DmaTxHandle, +}; + +static int32_t USART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART3_InitPins(); + return USART_DmaInitialize(cb_event, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaUninitialize(void) +{ + USART3_DeinitPins(); + return USART_DmaUninitialize(&usart3_DmaDriverState); +} + +static int32_t USART3_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart3_DmaDriverState); +} + +static uint32_t USART3_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart3_DmaDriverState); +} + +static uint32_t USART3_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart3_DmaDriverState); +} + +static int32_t USART3_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart3_DmaDriverState); +} + +static ARM_USART_STATUS USART3_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart3_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART3_Handle; +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) +static uint8_t usart3_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("usart3_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = { +#endif + &usart3_Resource, &USART3_Handle, +}; + +static int32_t USART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART3_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingUninitialize(void) +{ + USART3_DeinitPins(); + return USART_NonBlockingUninitialize(&usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart3_NonBlockingDriverState); +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart3_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart3_NonBlockingDriverState.resource->base, + usart3_NonBlockingDriverState.handle, usart3_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART3_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart3_NonBlockingDriverState); +} + +static uint32_t USART3_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart3_NonBlockingDriverState); +} + +static uint32_t USART3_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart3_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart3_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART3_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart3_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART3 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART3_DMA_EN + USART3_DmaInitialize, USART3_DmaUninitialize, USART3_DmaPowerControl, USART3_DmaSend, USART3_DmaReceive, + USART3_DmaTransfer, USART3_DmaGetTxCount, USART3_DmaGetRxCount, USART3_DmaControl, USART3_DmaGetStatus, +#else + USART3_NonBlockingInitialize, + USART3_NonBlockingUninitialize, + USART3_NonBlockingPowerControl, + USART3_NonBlockingSend, + USART3_NonBlockingReceive, + USART3_NonBlockingTransfer, + USART3_NonBlockingGetTxCount, + USART3_NonBlockingGetRxCount, + USART3_NonBlockingControl, + USART3_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart3 */ + +#if defined(USART4) && RTE_USART4 + +/* User needs to provide the implementation for USART4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART4_GetFreq(void); +extern void USART4_InitPins(void); +extern void USART4_DeinitPins(void); + +cmsis_usart_resource_t usart4_Resource = {USART4, USART4_GetFreq}; + +#if RTE_USART4_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart4_DmaResource = { + RTE_USART4_DMA_TX_DMA_BASE, RTE_USART4_DMA_TX_CH, RTE_USART4_DMA_RX_DMA_BASE, RTE_USART4_DMA_RX_CH, +}; + +usart_dma_handle_t USART4_DmaHandle; +dma_handle_t USART4_DmaRxHandle; +dma_handle_t USART4_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("usart4_dma_driver_state") +cmsis_usart_dma_driver_state_t usart4_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart4_DmaDriverState = { +#endif + &usart4_Resource, &usart4_DmaResource, &USART4_DmaHandle, &USART4_DmaRxHandle, &USART4_DmaTxHandle, +}; + +static int32_t USART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART4_InitPins(); + return USART_DmaInitialize(cb_event, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaUninitialize(void) +{ + USART4_DeinitPins(); + return USART_DmaUninitialize(&usart4_DmaDriverState); +} + +static int32_t USART4_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart4_DmaDriverState); +} + +static uint32_t USART4_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart4_DmaDriverState); +} + +static uint32_t USART4_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart4_DmaDriverState); +} + +static int32_t USART4_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart4_DmaDriverState); +} + +static ARM_USART_STATUS USART4_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart4_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART4_Handle; +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) +static uint8_t usart4_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("usart4_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = { +#endif + &usart4_Resource, &USART4_Handle, +}; + +static int32_t USART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART4_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingUninitialize(void) +{ + USART4_DeinitPins(); + return USART_NonBlockingUninitialize(&usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart4_NonBlockingDriverState); +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart4_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart4_NonBlockingDriverState.resource->base, + usart4_NonBlockingDriverState.handle, usart4_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART4_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart4_NonBlockingDriverState); +} + +static uint32_t USART4_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart4_NonBlockingDriverState); +} + +static uint32_t USART4_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart4_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart4_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART4_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart4_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART4 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART4_DMA_EN + USART4_DmaInitialize, USART4_DmaUninitialize, USART4_DmaPowerControl, USART4_DmaSend, USART4_DmaReceive, + USART4_DmaTransfer, USART4_DmaGetTxCount, USART4_DmaGetRxCount, USART4_DmaControl, USART4_DmaGetStatus, +#else + USART4_NonBlockingInitialize, + USART4_NonBlockingUninitialize, + USART4_NonBlockingPowerControl, + USART4_NonBlockingSend, + USART4_NonBlockingReceive, + USART4_NonBlockingTransfer, + USART4_NonBlockingGetTxCount, + USART4_NonBlockingGetRxCount, + USART4_NonBlockingControl, + USART4_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart4 */ + +#if defined(USART5) && RTE_USART5 + +/* User needs to provide the implementation for USART5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART5_GetFreq(void); +extern void USART5_InitPins(void); +extern void USART5_DeinitPins(void); + +cmsis_usart_resource_t usart5_Resource = {USART5, USART5_GetFreq}; + +#if RTE_USART5_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart5_DmaResource = { + RTE_USART5_DMA_TX_DMA_BASE, RTE_USART5_DMA_TX_CH, RTE_USART5_DMA_RX_DMA_BASE, RTE_USART5_DMA_RX_CH, +}; + +usart_dma_handle_t USART5_DmaHandle; +dma_handle_t USART5_DmaRxHandle; +dma_handle_t USART5_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("usart5_dma_driver_state") +cmsis_usart_dma_driver_state_t usart5_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart5_DmaDriverState = { +#endif + &usart5_Resource, &usart5_DmaResource, &USART5_DmaHandle, &USART5_DmaRxHandle, &USART5_DmaTxHandle, +}; + +static int32_t USART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART5_InitPins(); + return USART_DmaInitialize(cb_event, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaUninitialize(void) +{ + USART5_DeinitPins(); + return USART_DmaUninitialize(&usart5_DmaDriverState); +} + +static int32_t USART5_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart5_DmaDriverState); +} + +static uint32_t USART5_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart5_DmaDriverState); +} + +static uint32_t USART5_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart5_DmaDriverState); +} + +static int32_t USART5_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart5_DmaDriverState); +} + +static ARM_USART_STATUS USART5_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart5_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART5_Handle; +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) +static uint8_t usart5_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("usart5_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = { +#endif + &usart5_Resource, &USART5_Handle, +}; + +static int32_t USART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART5_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingUninitialize(void) +{ + USART5_DeinitPins(); + return USART_NonBlockingUninitialize(&usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart5_NonBlockingDriverState); +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart5_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart5_NonBlockingDriverState.resource->base, + usart5_NonBlockingDriverState.handle, usart5_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART5_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart5_NonBlockingDriverState); +} + +static uint32_t USART5_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart5_NonBlockingDriverState); +} + +static uint32_t USART5_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart5_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart5_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART5_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart5_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART5 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART5_DMA_EN + USART5_DmaInitialize, USART5_DmaUninitialize, USART5_DmaPowerControl, USART5_DmaSend, USART5_DmaReceive, + USART5_DmaTransfer, USART5_DmaGetTxCount, USART5_DmaGetRxCount, USART5_DmaControl, USART5_DmaGetStatus, +#else + USART5_NonBlockingInitialize, + USART5_NonBlockingUninitialize, + USART5_NonBlockingPowerControl, + USART5_NonBlockingSend, + USART5_NonBlockingReceive, + USART5_NonBlockingTransfer, + USART5_NonBlockingGetTxCount, + USART5_NonBlockingGetRxCount, + USART5_NonBlockingControl, + USART5_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart5 */ + +#if defined(USART6) && RTE_USART6 + +/* User needs to provide the implementation for USART6_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART6_GetFreq(void); +extern void USART6_InitPins(void); +extern void USART6_DeinitPins(void); + +cmsis_usart_resource_t usart6_Resource = {USART6, USART6_GetFreq}; + +#if RTE_USART6_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart6_DmaResource = { + RTE_USART6_DMA_TX_DMA_BASE, RTE_USART6_DMA_TX_CH, RTE_USART6_DMA_RX_DMA_BASE, RTE_USART6_DMA_RX_CH, +}; + +usart_dma_handle_t USART6_DmaHandle; +dma_handle_t USART6_DmaRxHandle; +dma_handle_t USART6_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("usart6_dma_driver_state") +cmsis_usart_dma_driver_state_t usart6_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart6_DmaDriverState = { +#endif + &usart6_Resource, &usart6_DmaResource, &USART6_DmaHandle, &USART6_DmaRxHandle, &USART6_DmaTxHandle, +}; + +static int32_t USART6_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART6_InitPins(); + return USART_DmaInitialize(cb_event, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaUninitialize(void) +{ + USART6_DeinitPins(); + return USART_DmaUninitialize(&usart6_DmaDriverState); +} + +static int32_t USART6_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart6_DmaDriverState); +} + +static uint32_t USART6_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart6_DmaDriverState); +} + +static uint32_t USART6_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart6_DmaDriverState); +} + +static int32_t USART6_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart6_DmaDriverState); +} + +static ARM_USART_STATUS USART6_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart6_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART6_Handle; +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) +static uint8_t usart6_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("usart6_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = { +#endif + &usart6_Resource, &USART6_Handle, +}; + +static int32_t USART6_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART6_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingUninitialize(void) +{ + USART6_DeinitPins(); + return USART_NonBlockingUninitialize(&usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart6_NonBlockingDriverState); +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart6_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart6_NonBlockingDriverState.resource->base, + usart6_NonBlockingDriverState.handle, usart6_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART6_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart6_NonBlockingDriverState); +} + +static uint32_t USART6_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart6_NonBlockingDriverState); +} + +static uint32_t USART6_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart6_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart6_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART6_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart6_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART6 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART6_DMA_EN + USART6_DmaInitialize, USART6_DmaUninitialize, USART6_DmaPowerControl, USART6_DmaSend, USART6_DmaReceive, + USART6_DmaTransfer, USART6_DmaGetTxCount, USART6_DmaGetRxCount, USART6_DmaControl, USART6_DmaGetStatus, +#else + USART6_NonBlockingInitialize, + USART6_NonBlockingUninitialize, + USART6_NonBlockingPowerControl, + USART6_NonBlockingSend, + USART6_NonBlockingReceive, + USART6_NonBlockingTransfer, + USART6_NonBlockingGetTxCount, + USART6_NonBlockingGetRxCount, + USART6_NonBlockingControl, + USART6_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart6 */ + +#if defined(USART7) && RTE_USART7 + +/* User needs to provide the implementation for USART7_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART7_GetFreq(void); +extern void USART7_InitPins(void); +extern void USART7_DeinitPins(void); + +cmsis_usart_resource_t usart7_Resource = {USART7, USART7_GetFreq}; + +#if RTE_USART7_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart7_DmaResource = { + RTE_USART7_DMA_TX_DMA_BASE, RTE_USART7_DMA_TX_CH, RTE_USART7_DMA_RX_DMA_BASE, RTE_USART7_DMA_RX_CH, +}; + +usart_dma_handle_t USART7_DmaHandle; +dma_handle_t USART7_DmaRxHandle; +dma_handle_t USART7_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("usart7_dma_driver_state") +cmsis_usart_dma_driver_state_t usart7_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart7_DmaDriverState = { +#endif + &usart7_Resource, &usart7_DmaResource, &USART7_DmaHandle, &USART7_DmaRxHandle, &USART7_DmaTxHandle, +}; + +static int32_t USART7_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART7_InitPins(); + return USART_DmaInitialize(cb_event, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaUninitialize(void) +{ + USART7_DeinitPins(); + return USART_DmaUninitialize(&usart7_DmaDriverState); +} + +static int32_t USART7_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart7_DmaDriverState); +} + +static uint32_t USART7_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart7_DmaDriverState); +} + +static uint32_t USART7_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart7_DmaDriverState); +} + +static int32_t USART7_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart7_DmaDriverState); +} + +static ARM_USART_STATUS USART7_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart7_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART7_Handle; +#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) +static uint8_t usart7_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("usart7_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = { +#endif + &usart7_Resource, &USART7_Handle, +}; + +static int32_t USART7_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART7_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingUninitialize(void) +{ + USART7_DeinitPins(); + return USART_NonBlockingUninitialize(&usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart7_NonBlockingDriverState); +#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart7_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart7_NonBlockingDriverState.resource->base, + usart7_NonBlockingDriverState.handle, usart7_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART7_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart7_NonBlockingDriverState); +} + +static uint32_t USART7_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart7_NonBlockingDriverState); +} + +static uint32_t USART7_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart7_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart7_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART7_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart7_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART7 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART7_DMA_EN + USART7_DmaInitialize, USART7_DmaUninitialize, USART7_DmaPowerControl, USART7_DmaSend, USART7_DmaReceive, + USART7_DmaTransfer, USART7_DmaGetTxCount, USART7_DmaGetRxCount, USART7_DmaControl, USART7_DmaGetStatus, +#else + USART7_NonBlockingInitialize, + USART7_NonBlockingUninitialize, + USART7_NonBlockingPowerControl, + USART7_NonBlockingSend, + USART7_NonBlockingReceive, + USART7_NonBlockingTransfer, + USART7_NonBlockingGetTxCount, + USART7_NonBlockingGetRxCount, + USART7_NonBlockingControl, + USART7_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart7 */ + +#if defined(USART8) && RTE_USART8 + +/* User needs to provide the implementation for USART8_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART8_GetFreq(void); +extern void USART8_InitPins(void); +extern void USART8_DeinitPins(void); + +cmsis_usart_resource_t usart8_Resource = {USART8, USART8_GetFreq}; + +#if RTE_USART8_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart8_DmaResource = { + RTE_USART8_DMA_TX_DMA_BASE, RTE_USART8_DMA_TX_CH, RTE_USART8_DMA_RX_DMA_BASE, RTE_USART8_DMA_RX_CH, +}; + +usart_dma_handle_t USART8_DmaHandle; +dma_handle_t USART8_DmaRxHandle; +dma_handle_t USART8_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("usart8_dma_driver_state") +cmsis_usart_dma_driver_state_t usart8_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart8_DmaDriverState = { +#endif + &usart8_Resource, &usart8_DmaResource, &USART8_DmaHandle, &USART8_DmaRxHandle, &USART8_DmaTxHandle, +}; + +static int32_t USART8_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART8_InitPins(); + return USART_DmaInitialize(cb_event, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaUninitialize(void) +{ + USART8_DeinitPins(); + return USART_DmaUninitialize(&usart8_DmaDriverState); +} + +static int32_t USART8_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart8_DmaDriverState); +} + +static uint32_t USART8_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart8_DmaDriverState); +} + +static uint32_t USART8_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart8_DmaDriverState); +} + +static int32_t USART8_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart8_DmaDriverState); +} + +static ARM_USART_STATUS USART8_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart8_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART8_Handle; +#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) +static uint8_t usart8_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("usart8_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = { +#endif + &usart8_Resource, &USART8_Handle, +}; + +static int32_t USART8_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART8_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingUninitialize(void) +{ + USART8_DeinitPins(); + return USART_NonBlockingUninitialize(&usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart8_NonBlockingDriverState); +#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart8_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart8_NonBlockingDriverState.resource->base, + usart8_NonBlockingDriverState.handle, usart8_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t USART8_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart8_NonBlockingDriverState); +} + +static uint32_t USART8_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart8_NonBlockingDriverState); +} + +static uint32_t USART8_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart8_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart8_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART8_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart8_NonBlockingDriverState); +} + +#endif + +/* usart8 Driver Control Block */ +ARM_DRIVER_USART Driver_USART8 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART8_DMA_EN + USART8_DmaInitialize, USART8_DmaUninitialize, USART8_DmaPowerControl, USART8_DmaSend, USART8_DmaReceive, + USART8_DmaTransfer, USART8_DmaGetTxCount, USART8_DmaGetRxCount, USART8_DmaControl, USART8_DmaGetStatus, +#else + USART8_NonBlockingInitialize, + USART8_NonBlockingUninitialize, + USART8_NonBlockingPowerControl, + USART8_NonBlockingSend, + USART8_NonBlockingReceive, + USART8_NonBlockingTransfer, + USART8_NonBlockingGetTxCount, + USART8_NonBlockingGetRxCount, + USART8_NonBlockingControl, + USART8_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart8 */ + +#if defined(USART9) && RTE_USART9 + +/* User needs to provide the implementation for USART9_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART9_GetFreq(void); +extern void USART9_InitPins(void); +extern void USART9_DeinitPins(void); + +cmsis_usart_resource_t usart9_Resource = {USART9, USART9_GetFreq}; + +#if RTE_USART9_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart9_DmaResource = { + RTE_USART9_DMA_TX_DMA_BASE, RTE_USART9_DMA_TX_CH, RTE_USART9_DMA_RX_DMA_BASE, RTE_USART9_DMA_RX_CH, +}; + +usart_dma_handle_t USART9_DmaHandle; +dma_handle_t USART9_DmaRxHandle; +dma_handle_t USART9_DmaTxHandle; + +#if defined(__CC_ARM) +ARMCC_SECTION("usart9_dma_driver_state") +cmsis_usart_dma_driver_state_t usart9_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart9_DmaDriverState = { +#endif + &usart9_Resource, &usart9_DmaResource, &USART9_DmaHandle, &USART9_DmaRxHandle, &USART9_DmaTxHandle, +}; + +static int32_t USART9_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART9_InitPins(); + return USART_DmaInitialize(cb_event, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaUninitialize(void) +{ + USART9_DeinitPins(); + return USART_DmaUninitialize(&usart9_DmaDriverState); +} + +static int32_t USART9_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart9_DmaDriverState); +} + +static uint32_t USART9_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart9_DmaDriverState); +} + +static uint32_t USART9_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart9_DmaDriverState); +} + +static int32_t USART9_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart9_DmaDriverState); +} + +static ARM_USART_STATUS USART9_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart9_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART9_Handle; +#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) +static uint8_t usart9_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) +ARMCC_SECTION("usart9_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = { +#endif + &usart9_Resource, &USART9_Handle, +}; + +static int32_t USART9_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART9_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingUninitialize(void) +{ + USART9_DeinitPins(); + return USART_NonBlockingUninitialize(&usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart9_NonBlockingDriverState); +#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart9_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart9_NonBlockingDriverState.resource->base, + usart9_NonBlockingDriverState.handle, usart9_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t USART9_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart9_NonBlockingDriverState); +} + +static uint32_t USART9_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart9_NonBlockingDriverState); +} + +static uint32_t USART9_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart9_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart9_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART9_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart9_NonBlockingDriverState); +} + +#endif + +/* usart9 Driver Control Block */ +ARM_DRIVER_USART Driver_USART9 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART9_DMA_EN + USART9_DmaInitialize, USART9_DmaUninitialize, USART9_DmaPowerControl, USART9_DmaSend, USART9_DmaReceive, + USART9_DmaTransfer, USART9_DmaGetTxCount, USART9_DmaGetRxCount, USART9_DmaControl, USART9_DmaGetStatus, +#else + USART9_NonBlockingInitialize, + USART9_NonBlockingUninitialize, + USART9_NonBlockingPowerControl, + USART9_NonBlockingSend, + USART9_NonBlockingReceive, + USART9_NonBlockingTransfer, + USART9_NonBlockingGetTxCount, + USART9_NonBlockingGetRxCount, + USART9_NonBlockingControl, + USART9_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart9 */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.h new file mode 100644 index 00000000000..ee6c0928dff --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/cmsis_drivers/fsl_usart_cmsis.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FSL_USART_CMSIS_H_ +#define _FSL_USART_CMSIS_H_ + +#include "fsl_common.h" +#include "Driver_USART.h" +#include "RTE_Device.h" +#include "fsl_usart.h" +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +#include "fsl_usart_dma.h" +#endif + +#if defined(USART0) +extern ARM_DRIVER_USART Driver_USART0; +#endif /* USART0 */ + +#if defined(USART1) +extern ARM_DRIVER_USART Driver_USART1; +#endif /* USART1 */ + +#if defined(USART2) +extern ARM_DRIVER_USART Driver_USART2; +#endif /* USART2 */ + +#if defined(USART3) +extern ARM_DRIVER_USART Driver_USART3; +#endif /* USART3 */ + +#if defined(USART4) +extern ARM_DRIVER_USART Driver_USART4; +#endif /* USART4 */ + +#if defined(USART5) +extern ARM_DRIVER_USART Driver_USART5; +#endif /* USART5 */ + +#if defined(USART6) +extern ARM_DRIVER_USART Driver_USART6; +#endif /* USART6 */ + +#if defined(USART7) +extern ARM_DRIVER_USART Driver_USART7; +#endif /* USART7 */ + +/* USART Driver state flags */ +#define USART_FLAG_UNINIT (0) +#define USART_FLAG_INIT (1 << 0) +#define USART_FLAG_POWER (1 << 1) +#define USART_FLAG_CONFIGURED (1 << 2) + +#endif /* _FSL_USART_CMSIS_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/SConscript b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/SConscript new file mode 100644 index 00000000000..46044bf7bed --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = Glob('*.c') + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.c new file mode 100644 index 00000000000..2c44d9ff7d8 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.c @@ -0,0 +1,399 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_adc.h" +#include "fsl_clock.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_adc" +#endif + + +static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +static uint32_t ADC_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++) + { + if (s_adcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_adcBases)); + + return instance; +} + +void ADC_Init(ADC_Type *base, const adc_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable clock. */ + CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable the interrupts. */ + base->INTEN = 0U; /* Quickly disable all the interrupts. */ + + /* Configure the ADC block. */ + tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber); + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + /* Async or Sync clock mode. */ + switch (config->clockMode) + { + case kADC_ClockAsynchronousMode: + tmp32 |= ADC_CTRL_ASYNMODE_MASK; + break; + default: /* kADC_ClockSynchronousMode */ + break; + } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL + /* Resolution. */ + tmp32 |= ADC_CTRL_RESOL(config->resolution); +#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL + /* Bypass calibration. */ + if (config->enableBypassCalibration) + { + tmp32 |= ADC_CTRL_BYPASSCAL_MASK; + } +#endif/* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP + /* Sample time clock count. */ + tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber); +#endif/* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + if(config->enableLowPowerMode) + { + tmp32 |= ADC_CTRL_LPWRMODE_MASK; + } +#endif/* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ + + base->CTRL = tmp32; + +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + base->TRM &= ~ADC_TRM_VRANGE_MASK; + base->TRM |= ADC_TRM_VRANGE(config->voltageRange); +#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */ +} + +void ADC_GetDefaultConfig(adc_config_t *config) +{ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + config->clockMode = kADC_ClockSynchronousMode; +#endif/* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ + + config->clockDividerNumber = 0U; +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL + config->resolution = kADC_Resolution12bit; +#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL + config->enableBypassCalibration = false; +#endif/* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP + config->sampleTimeNumber = 0U; +#endif/* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + config->enableLowPowerMode = false; +#endif/* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + config->voltageRange = kADC_HighVoltageRange; +#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */ +} + +void ADC_Deinit(ADC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) +#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) & FSL_FEATURE_ADC_HAS_CALIB_REG +bool ADC_DoSelfCalibration(ADC_Type *base) +{ + uint32_t i; + + /* Enable the converter. */ + /* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down. + This bit should be set after at least 10 ms after the ADC is powered on. */ + base->STARTUP = ADC_STARTUP_ADC_ENA_MASK; + for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */ + { + __ASM("NOP"); + } + if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK)) + { + return false; /* ADC is not powered up. */ + } + + /* If not in by-pass mode, do the calibration. */ + if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) && + (0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK))) + { + /* Calibration is needed, do it now. */ + base->CALIB = ADC_CALIB_CALIB_MASK; + i = 0xF0000; + while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i)) + { + } + if (i == 0U) + { + return false; /* Calibration timeout. */ + } + } + + /* A dummy conversion cycle will be performed. */ + base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK; + i = 0x7FFFF; + while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i)) + { + } + if (i == 0U) + { + return false; + } + + return true; +} +#else +bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency) +{ + uint32_t tmp32; + uint32_t i = 0xF0000; + + /* Store the current contents of the ADC CTRL register. */ + tmp32 = base->CTRL; + + /* Start ADC self-calibration. */ + base->CTRL |= ADC_CTRL_CALMODE_MASK; + + /* Divide the system clock to yield an ADC clock of about 500 kHz. */ + base->CTRL &= ~ADC_CTRL_CLKDIV_MASK; + base->CTRL |= ADC_CTRL_CLKDIV((frequency / 500000U) - 1U); + + /* Clear the LPWR bit. */ + base->CTRL &= ~ADC_CTRL_LPWRMODE_MASK; + + /* Wait for the completion of calibration. */ + while ((ADC_CTRL_CALMODE_MASK == (base->CTRL & ADC_CTRL_CALMODE_MASK)) && (--i)) + { + } + /* Restore the contents of the ADC CTRL register. */ + base->CTRL = tmp32; + + /* Judge whether the calibration is overtime. */ + if (i == 0U) + { + return false; /* Calibration timeout. */ + } + + return true; +} +#endif/* FSL_FEATURE_ADC_HAS_CALIB_REG */ +#endif/* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC*/ + +void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32; + + tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask) /* Channel mask. */ + | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */ + + /* Polarity for tirgger signal. */ + switch (config->triggerPolarity) + { + case kADC_TriggerPolarityPositiveEdge: + tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK; + break; + default: /* kADC_TriggerPolarityNegativeEdge */ + break; + } + + /* Bypass the clock Sync. */ + if (config->enableSyncBypass) + { + tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK; + } + + /* Interrupt point. */ + switch (config->interruptMode) + { + case kADC_InterruptForEachSequence: + tmp32 |= ADC_SEQ_CTRL_MODE_MASK; + break; + default: /* kADC_InterruptForEachConversion */ + break; + } + + /* One trigger for a conversion, or for a sequence. */ + if (config->enableSingleStep) + { + tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK; + } + + base->SEQ_CTRL[0] = tmp32; +} + +void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32; + + tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask) /* Channel mask. */ + | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */ + + /* Polarity for tirgger signal. */ + switch (config->triggerPolarity) + { + case kADC_TriggerPolarityPositiveEdge: + tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK; + break; + default: /* kADC_TriggerPolarityPositiveEdge */ + break; + } + + /* Bypass the clock Sync. */ + if (config->enableSyncBypass) + { + tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK; + } + + /* Interrupt point. */ + switch (config->interruptMode) + { + case kADC_InterruptForEachSequence: + tmp32 |= ADC_SEQ_CTRL_MODE_MASK; + break; + default: /* kADC_InterruptForEachConversion */ + break; + } + + /* One trigger for a conversion, or for a sequence. */ + if (config->enableSingleStep) + { + tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK; + } + + base->SEQ_CTRL[1] = tmp32; +} + +bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) +{ + assert(info != NULL); + + uint32_t tmp32 = base->SEQ_GDAT[0]; /* Read to clear the status. */ + + if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32)) + { + return false; + } + + info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT; + info->thresholdCompareStatus = + (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT); + info->thresholdCorssingStatus = + (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT); + info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT; + info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); + + return true; +} + +bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) +{ + assert(info != NULL); + + uint32_t tmp32 = base->SEQ_GDAT[1]; /* Read to clear the status. */ + + if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32)) + { + return false; + } + + info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT; + info->thresholdCompareStatus = + (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT); + info->thresholdCorssingStatus = + (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT); + info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT; + info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); + + return true; +} + +bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info) +{ + assert(info != NULL); + assert(channel < ADC_DAT_COUNT); + + uint32_t tmp32 = base->DAT[channel]; /* Read to clear the status. */ + + if (0U == (ADC_DAT_DATAVALID_MASK & tmp32)) + { + return false; + } + + info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT; + info->thresholdCompareStatus = + (adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT); + info->thresholdCorssingStatus = + (adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT); + info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT; + info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK); + + return true; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.h new file mode 100644 index 00000000000..06f29a26e82 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_adc.h @@ -0,0 +1,729 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_ADC_H__ +#define __FSL_ADC_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_adc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ADC driver version 2.2.0. */ +#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/*! + * @brief Flags + */ +enum _adc_status_flags +{ + kADC_ThresholdCompareFlagOnChn0 = 1U << 0U, /*!< Threshold comparison event on Channel 0. */ + kADC_ThresholdCompareFlagOnChn1 = 1U << 1U, /*!< Threshold comparison event on Channel 1. */ + kADC_ThresholdCompareFlagOnChn2 = 1U << 2U, /*!< Threshold comparison event on Channel 2. */ + kADC_ThresholdCompareFlagOnChn3 = 1U << 3U, /*!< Threshold comparison event on Channel 3. */ + kADC_ThresholdCompareFlagOnChn4 = 1U << 4U, /*!< Threshold comparison event on Channel 4. */ + kADC_ThresholdCompareFlagOnChn5 = 1U << 5U, /*!< Threshold comparison event on Channel 5. */ + kADC_ThresholdCompareFlagOnChn6 = 1U << 6U, /*!< Threshold comparison event on Channel 6. */ + kADC_ThresholdCompareFlagOnChn7 = 1U << 7U, /*!< Threshold comparison event on Channel 7. */ + kADC_ThresholdCompareFlagOnChn8 = 1U << 8U, /*!< Threshold comparison event on Channel 8. */ + kADC_ThresholdCompareFlagOnChn9 = 1U << 9U, /*!< Threshold comparison event on Channel 9. */ + kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */ + kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */ + kADC_OverrunFlagForChn0 = + 1U << 12U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 0. */ + kADC_OverrunFlagForChn1 = + 1U << 13U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 1. */ + kADC_OverrunFlagForChn2 = + 1U << 14U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 2. */ + kADC_OverrunFlagForChn3 = + 1U << 15U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 3. */ + kADC_OverrunFlagForChn4 = + 1U << 16U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 4. */ + kADC_OverrunFlagForChn5 = + 1U << 17U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 5. */ + kADC_OverrunFlagForChn6 = + 1U << 18U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 6. */ + kADC_OverrunFlagForChn7 = + 1U << 19U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 7. */ + kADC_OverrunFlagForChn8 = + 1U << 20U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 8. */ + kADC_OverrunFlagForChn9 = + 1U << 21U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 9. */ + kADC_OverrunFlagForChn10 = + 1U << 22U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 10. */ + kADC_OverrunFlagForChn11 = + 1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */ + kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */ + kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */ + kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */ + kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */ + kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */ + kADC_OverrunInterruptFlag = 1U << 31U, /*!< Overrun interrupt flag. */ +}; + +/*! + * @brief Interrupts + * @note Not all the interrupt options are listed here + */ +enum _adc_interrupt_enable +{ + kADC_ConvSeqAInterruptEnable = ADC_INTEN_SEQA_INTEN_MASK, /*!< Enable interrupt upon completion of each individual + conversion in sequence A, or entire sequence. */ + kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual + conversion in sequence B, or entire sequence. */ + kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of + the channel data registers will cause an overrun + interrupt/DMA trigger. */ +}; + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE +/*! + * @brief Define selection of clock mode. + */ +typedef enum _adc_clock_mode +{ + kADC_ClockSynchronousMode = + 0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */ + kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */ +} adc_clock_mode_t; +#endif/* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ + + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL +/*! + * @brief Define selection of resolution. + */ +typedef enum _adc_resolution +{ + kADC_Resolution6bit = 0U, /*!< 6-bit resolution. */ + kADC_Resolution8bit = 1U, /*!< 8-bit resolution. */ + kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */ + kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */ +} adc_resolution_t; +#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ + +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG +/*! +* @brief Definfe range of the analog supply voltage VDDA. +*/ +typedef enum _adc_voltage_range +{ + kADC_HighVoltageRange = 0U, /* High voltage. VDD = 2.7 V to 3.6 V. */ + kADC_LowVoltageRange = 1U, /* Low voltage. VDD = 2.4 V to 2.7 V. */ +} adc_vdda_range_t; +#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */ + +/*! + * @brief Define selection of polarity of selected input trigger for conversion sequence. + */ +typedef enum _adc_trigger_polarity +{ + kADC_TriggerPolarityNegativeEdge = 0U, /*!< A negative edge launches the conversion sequence on the trigger(s). */ + kADC_TriggerPolarityPositiveEdge = 1U, /*!< A positive edge launches the conversion sequence on the trigger(s). */ +} adc_trigger_polarity_t; + +/*! + * @brief Define selection of conversion sequence's priority. + */ +typedef enum _adc_priority +{ + kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */ + kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when it is started. */ +} adc_priority_t; + +/*! + * @brief Define selection of conversion sequence's interrupt. + */ +typedef enum _adc_seq_interrupt_mode +{ + kADC_InterruptForEachConversion = 0U, /*!< The sequence interrupt/DMA trigger will be set at the end of each + individual ADC conversion inside this conversion sequence. */ + kADC_InterruptForEachSequence = 1U, /*!< The sequence interrupt/DMA trigger will be set when the entire set of + this sequence conversions completes. */ +} adc_seq_interrupt_mode_t; + +/*! + * @brief Define status of threshold compare result. + */ +typedef enum _adc_threshold_compare_status +{ + kADC_ThresholdCompareInRange = 0U, /*!< LOW threshold <= conversion value <= HIGH threshold. */ + kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */ + kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */ +} adc_threshold_compare_status_t; + +/*! + * @brief Define status of threshold crossing detection result. + */ +typedef enum _adc_threshold_crossing_status +{ + /* The conversion on this channel had the same relationship (above or below) to the threshold value established by + * the designated LOW threshold value as did the previous conversion on this channel. */ + kADC_ThresholdCrossingNoDetected = 0U, /*!< No threshold Crossing detected. */ + + /* Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this + * channel was above the threshold value established by the designated LOW threshold value and the current sample is + * below that threshold. */ + kADC_ThresholdCrossingDownward = 2U, /*!< Downward Threshold Crossing detected. */ + + /* Indicates that a thre shold crossing in the upward direction has occurred - i.e. the previous sample on this + * channel was below the threshold value established by the designated LOW threshold value and the current sample is + * above that threshold. */ + kADC_ThresholdCrossingUpward = 3U, /*!< Upward Threshold Crossing Detected. */ +} adc_threshold_crossing_status_t; + +/*! + * @brief Define interrupt mode for threshold compare event. + */ +typedef enum _adc_threshold_interrupt_mode +{ + kADC_ThresholdInterruptDisabled = 0U, /*!< Threshold comparison interrupt is disabled. */ + kADC_ThresholdInterruptOnOutside = 1U, /*!< Threshold comparison interrupt is enabled on outside threshold. */ + kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */ +} adc_threshold_interrupt_mode_t; + +/*! + * @brief Define structure for configuring the block. + */ +typedef struct _adc_config +{ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */ +#endif/* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ + uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode" + field. The divider would be plused by 1 based on the value in this field. The + available range is in 8 bits. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL + adc_resolution_t resolution; /*!< Select the conversion bits. */ +#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL + bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is + powered-up. Re-calibration may be warranted periodically - especially if + operating conditions have changed. To enable this option would avoid the need to + calibrate if offset error is not a concern in the application. */ +#endif/* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP + uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then, + to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/ +#endif/* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + bool enableLowPowerMode; /*!< If disable low-power mode, ADC remains activated even when no conversions are requested. + If enable low-power mode, The ADC is automatically powered-down when no conversions are + taking place. */ +#endif/* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG +adc_vdda_range_t voltageRange; /*!< Configure the ADC for the appropriate operating range of the analog supply voltage VDDA. + Failure to set the area correctly causes the ADC to return incorrect conversion results. */ +#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */ +} adc_config_t; + +/*! + * @brief Define structure for configuring conversion sequence. + */ +typedef struct _adc_conv_seq_config +{ + uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this + sequence is launched. The masked channels would be involved in current conversion + sequence, beginning with the lowest-order. The available range is in 12-bit. */ + uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this + conversion sequence to be initiated. The available range is 6-bit.*/ + adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */ + bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization + flip-flop stages and therefore shorten the time between the trigger input signal and the + start of a conversion. */ + bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next + channel in the sequence instead of the default response of launching an entire sequence + of conversions. */ + adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */ +} adc_conv_seq_config_t; + +/*! + * @brief Define structure of keeping conversion result information. + */ +typedef struct _adc_result_info +{ + uint32_t result; /*!< Keep the conversion data value. */ + adc_threshold_compare_status_t thresholdCompareStatus; /*!< Keep the threshold compare status. */ + adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */ + uint32_t channelNumber; /*!< Keep the channel number for this conversion. */ + bool overrunFlag; /*!< Keep the status whether the conversion is overrun or not. */ + /* The data available flag would be returned by the reading result API. */ +} adc_result_info_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization and Deinitialization + * @{ + */ + +/*! + * @brief Initialize the ADC module. + * + * @param base ADC peripheral base address. + * @param config Pointer to configuration structure, see to #adc_config_t. + */ +void ADC_Init(ADC_Type *base, const adc_config_t *config); + +/*! + * @brief Deinitialize the ADC module. + * + * @param base ADC peripheral base address. + */ +void ADC_Deinit(ADC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the initial configuration structure with an available settings. The default values are: + * @code + * config->clockMode = kADC_ClockSynchronousMode; + * config->clockDividerNumber = 0U; + * config->resolution = kADC_Resolution12bit; + * config->enableBypassCalibration = false; + * config->sampleTimeNumber = 0U; + * @endcode + * @param config Pointer to configuration structure. + */ +void ADC_GetDefaultConfig(adc_config_t *config); + +#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) +#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) && FSL_FEATURE_ADC_HAS_CALIB_REG +/*! + * @brief Do the self hardware calibration. + * + * @param base ADC peripheral base address. + * @retval true Calibration succeed. + * @retval false Calibration failed. + */ +bool ADC_DoSelfCalibration(ADC_Type *base); +#else +/*! + * @brief Do the self calibration. To calibrate the ADC, set the ADC clock to 500 kHz. + * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, + * following every chip reset before initiating normal ADC operation. + * + * @param base ADC peripheral base address. + * @param frequency The ststem clock frequency to ADC. + * @retval true Calibration succeed. + * @retval false Calibration failed. + */ +bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency); +#endif/* FSL_FEATURE_ADC_HAS_CALIB_REG */ +#endif/* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC */ + +#if !(defined(FSL_FEATURE_ADC_HAS_NO_INSEL) && FSL_FEATURE_ADC_HAS_NO_INSEL) +/*! + * @brief Enable the internal temperature sensor measurement. + * + * When enabling the internal temperature sensor measurement, the channel 0 would be connected to internal sensor + * instead of external pin. + * + * @param base ADC peripheral base address. + * @param enable Switcher to enable the feature or not. + */ +static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) +{ + if (enable) + { + base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0x3); + } + else + { + base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0); + } +} +#endif /* FSL_FEATURE_ADC_HAS_NO_INSEL. */ +/* @} */ + +/*! + * @name Control conversion sequence A. + * @{ + */ + +/*! + * @brief Enable the conversion sequence A. + * + * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the + * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the + * sequence during changing the sequence's setting. + * + * @param base ADC peripheral base address. + * @param enable Switcher to enable the feature or not. + */ +static inline void ADC_EnableConvSeqA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_SEQ_ENA_MASK; + } + else + { + base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK; + } +} + +/*! + * @brief Configure the conversion sequence A. + * + * @param base ADC peripheral base address. + * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t. + */ +void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config); + +/*! + * @brief Do trigger the sequence's conversion by software. + * + * @param base ADC peripheral base address. + */ +static inline void ADC_DoSoftwareTriggerConvSeqA(ADC_Type *base) +{ + base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_START_MASK; +} + +/*! + * @brief Enable the burst conversion of sequence A. + * + * Enable the burst mode would cause the conversion sequence to be cntinuously cycled through. Other triggers would be + * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence + * currently in process will be completed before cnversions are terminated. + * Note that a new sequence could begin just before the burst mode is disabled. + * + * @param base ADC peripheral base address. + * @param enable Switcher to enable this feature. + */ +static inline void ADC_EnableConvSeqABurstMode(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_BURST_MASK; + } + else + { + base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_BURST_MASK; + } +} + +/*! + * @brief Set the high priority for conversion sequence A. + * + * @param base ADC peripheral bass address. + */ +static inline void ADC_SetConvSeqAHighPriority(ADC_Type *base) +{ + base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_LOWPRIO_MASK; +} + +/* @} */ + +/*! + * @name Control conversion sequence B. + * @{ + */ + +/*! + * @brief Enable the conversion sequence B. + * + * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the + * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the + * sequence during changing the sequence's setting. + * + * @param base ADC peripheral base address. + * @param enable Switcher to enable the feature or not. + */ +static inline void ADC_EnableConvSeqB(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_SEQ_ENA_MASK; + } + else + { + base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK; + } +} + +/*! + * @brief Configure the conversion sequence B. + * + * @param base ADC peripheral base address. + * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t. + */ +void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config); + +/*! + * @brief Do trigger the sequence's conversion by software. + * + * @param base ADC peripheral base address. + */ +static inline void ADC_DoSoftwareTriggerConvSeqB(ADC_Type *base) +{ + base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_START_MASK; +} + +/*! + * @brief Enable the burst conversion of sequence B. + * + * Enable the burst mode would cause the conversion sequence to be continuously cycled through. Other triggers would be + * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence + * currently in process will be completed before cnversions are terminated. + * Note that a new sequence could begin just before the burst mode is disabled. + * + * @param base ADC peripheral base address. + * @param enable Switcher to enable this feature. + */ +static inline void ADC_EnableConvSeqBBurstMode(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_BURST_MASK; + } + else + { + base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_BURST_MASK; + } +} + +/*! + * @brief Set the high priority for conversion sequence B. + * + * @param base ADC peripheral bass address. + */ +static inline void ADC_SetConvSeqBHighPriority(ADC_Type *base) +{ + base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_LOWPRIO_MASK; +} + +/* @} */ + +/*! + * @name Data result. + * @{ + */ + +/*! + * @brief Get the global ADC conversion infomation of sequence A. + * + * @param base ADC peripheral base address. + * @param info Pointer to information structure, see to #adc_result_info_t; + * @retval true The conversion result is ready. + * @retval false The conversion result is not ready yet. + */ +bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info); + +/*! + * @brief Get the global ADC conversion infomation of sequence B. + * + * @param base ADC peripheral base address. + * @param info Pointer to information structure, see to #adc_result_info_t; + * @retval true The conversion result is ready. + * @retval false The conversion result is not ready yet. + */ +bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info); + +/*! + * @brief Get the channel's ADC conversion completed under each conversion sequence. + * + * @param base ADC peripheral base address. + * @param channel The indicated channel number. + * @param info Pointer to information structure, see to #adc_result_info_t; + * @retval true The conversion result is ready. + * @retval false The conversion result is not ready yet. + */ +bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info); + +/* @} */ + +/*! + * @name Threshold function. + * @{ + */ + +/*! + * @brief Set the threshhold pair 0 with low and high value. + * + * @param base ADC peripheral base address. + * @param lowValue LOW threshold value. + * @param highValue HIGH threshold value. + */ +static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue) +{ + base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue); + base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue); +} + +/*! + * @brief Set the threshhold pair 1 with low and high value. + * + * @param base ADC peripheral base address. + * @param lowValue LOW threshold value. The available value is with 12-bit. + * @param highValue HIGH threshold value. The available value is with 12-bit. + */ +static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue) +{ + base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue); + base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue); +} + +/*! + * @brief Set given channels to apply the threshold pare 0. + * + * @param base ADC peripheral base address. + * @param channelMask Indicated channels' mask. + */ +static inline void ADC_SetChannelWithThresholdPair0(ADC_Type *base, uint32_t channelMask) +{ + base->CHAN_THRSEL &= ~(channelMask); +} + +/*! + * @brief Set given channels to apply the threshold pare 1. + * + * @param base ADC peripheral base address. + * @param channelMask Indicated channels' mask. + */ +static inline void ADC_SetChannelWithThresholdPair1(ADC_Type *base, uint32_t channelMask) +{ + base->CHAN_THRSEL |= channelMask; +} + +/* @} */ + +/*! + * @name Interrupts. + * @{ + */ + +/*! + * @brief Enable interrupts for conversion sequences. + * + * @param base ADC peripheral base address. + * @param mask Mask of interrupt mask value for global block except each channal, see to #_adc_interrupt_enable. + */ +static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t mask) +{ + base->INTEN |= (0x7 & mask); +} + +/*! + * @brief Disable interrupts for conversion sequence. + * + * @param base ADC peripheral base address. + * @param mask Mask of interrupt mask value for global block except each channel, see to #_adc_interrupt_enable. + */ +static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask) +{ + base->INTEN &= ~(0x7 & mask); +} + +/*! + * @brief Enable the interrupt of threshold compare event for each channel. + * @deprecated Do not use this function. It has been superceded by @ADC_EnableThresholdCompareInterrupt + */ +static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base, + uint32_t channel, + adc_threshold_interrupt_mode_t mode) +{ + base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U)); +} + +/*! + * @brief Enable the interrupt of threshold compare event for each channel. + * + * @param base ADC peripheral base address. + * @param channel Channel number. + * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t. + */ +static inline void ADC_EnableThresholdCompareInterrupt(ADC_Type *base, + uint32_t channel, + adc_threshold_interrupt_mode_t mode) +{ + base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U)); +} + +/* @} */ + +/*! + * @name Status. + * @{ + */ + +/*! + * @brief Get status flags of ADC module. + * + * @param base ADC peripheral base address. + * @return Mask of status flags of module, see to #_adc_status_flags. + */ +static inline uint32_t ADC_GetStatusFlags(ADC_Type *base) +{ + return base->FLAGS; +} + +/*! + * @brief Clear status flags of ADC module. + * + * @param base ADC peripheral base address. + * @param mask Mask of status flags of module, see to #_adc_status_flags. + */ +static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->FLAGS = mask; /* Write 1 to clear. */ +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/* @} */ + +#endif /* __FSL_ADC_H__ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.c new file mode 100644 index 00000000000..3d1231bcf3a --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.c @@ -0,0 +1,1605 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_clock.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x8000U) + +#define PLL_MAX_N_DIV 0x100U + +#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000444U) +#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x01000430U) +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_SSCG0_MDEC_VAL_P (0U) /* MDEC is in bits 16 downto 0 */ +#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ +#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (75000000U) +#define PLL_MAX_CCO_FREQ_MHZ (150000000U) +#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */ +#define PLL_MIN_IN_SSMODE (2000000U) +#define PLL_MAX_IN_SSMODE (4000000U) + +/* Middle of the range values for spread-spectrum */ +#define PLL_SSCG_MF_FREQ_VALUE 4U +#define PLL_SSCG_MC_COMP_VALUE 2U +#define PLL_SSCG_MR_DEPTH_VALUE 4U +#define PLL_SSCG_DITHER_VALUE 0U + +/* PLL NDEC reg */ +#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) +/* PLL PDEC reg */ +#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) +/* SSCG control0 */ +#define PLL_SSCG0_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG0_MDEC_VAL_P) & PLL_SSCG0_MDEC_VAL_M) + +/* SSCG control1 */ +#define PLL_SSCG1_MD_FRACT_P 0U +#define PLL_SSCG1_MD_INT_P 11U +#define PLL_SSCG1_MD_FRACT_M (0x7FFUL << PLL_SSCG1_MD_FRACT_P) +#define PLL_SSCG1_MD_INT_M (0xFFUL << PLL_SSCG1_MD_INT_P) + +#define PLL_SSCG1_MD_FRACT_SET(value) (((unsigned long)(value) << PLL_SSCG1_MD_FRACT_P) & PLL_SSCG1_MD_FRACT_M) +#define PLL_SSCG1_MD_INT_SET(value) (((unsigned long)(value) << PLL_SSCG1_MD_INT_P) & PLL_SSCG1_MD_INT_M) + +/* Saved value of PLL output rate, computed whenever needed to save run-time + computation on each call to retrive the PLL rate. */ +static uint32_t s_Pll_Freq; + +/* I2S mclk. */ +static uint32_t s_I2S_Mclk_Freq = 0U; + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +static const uint32_t s_Ext_Clk_Freq = 0U; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Find encoded NDEC value for raw N value, max N = NVALMAX */ +static uint32_t pllEncodeN(uint32_t N); +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC); +/* Find encoded PDEC value for raw P value, max P = PVALMAX */ +static uint32_t pllEncodeP(uint32_t P); +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC); +/* Find encoded MDEC value for raw M value, max M = MVALMAX */ +static uint32_t pllEncodeM(uint32_t M); +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC); +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL NDEC setting */ +static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg); +/* Get postdivider (P) from PLL PDEC setting */ +static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg); +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfig( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS); +/* Update local PLL rate variable */ +static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup); + +static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, + 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; +/******************************************************************************* + * Code + ******************************************************************************/ + +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + bool final_descriptor = false; + uint8_t mux; + uint8_t pos; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->MAINCLKSELA); + + for (i = 0U; (i <= 2U) && (!final_descriptor); i++) + { + connection = (clock_attach_id_t)(connection >> (i * 12U)); /* pick up next descriptor */ + mux = (uint8_t)connection; + if (connection) + { + pos = ((connection & 0xf00U) >> 8U) - 1U; + if (mux == CM_ASYNCAPB) + { + ASYNC_SYSCON->ASYNCAPBCLKSELA = pos; + } + else + { + pClkSel[mux] = pos; + } + } + else + { + final_descriptor = true; + } + } +} + +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV); + if (reset) + { + pClkDiv[div_name] = 1U << 29U; + } + if (divided_by_value == 0U) /* halt */ + { + pClkDiv[div_name] = 1U << 30U; + } + else + { + pClkDiv[div_name] = (divided_by_value - 1U); + } +} + +/* Set FRO Clocking */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq) +{ + uint32_t usb_adj; + if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) + { + return kStatus_Fail; + } + /* Power up the FRO and set this as the base clock */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); + /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */ + usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT; + if (iFreq > 12000000U) + { + if (iFreq == 96000000U) + { + SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) | + SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | + SYSCON_FROCTRL_HSPDCLK(1); + } + else + { + SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) | + SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | + SYSCON_FROCTRL_HSPDCLK(1); + } + } + else + { + SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK(1); + } + + return 0U; +} + +uint32_t CLOCK_GetFro12MFreq(void) +{ + return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U; +} + +uint32_t CLOCK_GetExtClkFreq(void) +{ + return (s_Ext_Clk_Freq); +} +uint32_t CLOCK_GetWdtOscFreq(void) +{ + uint8_t freq_sel, div_sel; + if (SYSCON->PDRUNCFG[kPDRUNCFG_PD_WDT_OSC >> 8UL] & (1UL << (kPDRUNCFG_PD_WDT_OSC & 0xffU))) + { + return 0U; + } + else + { + div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1; + freq_sel = + wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; + return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel); + } +} + +/* Get HF FRO Clk */ +uint32_t CLOCK_GetFroHfFreq(void) +{ + if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) || !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK)) + { + return 0U; + } + + if(SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) + { + return 96000000U; + } + else + { + return 48000000U; + } +} + +uint32_t CLOCK_GetPllOutFreq(void) +{ + return s_Pll_Freq; +} + +uint32_t CLOCK_GetOsc32KFreq(void) +{ + return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */ +} +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + switch(SYSCON->MAINCLKSELB) + { + case 0U: + if(SYSCON->MAINCLKSELA == 0U) + { + freq = CLOCK_GetFro12MFreq(); + } + else if(SYSCON->MAINCLKSELA == 1U) + { + freq = CLOCK_GetExtClkFreq(); + } + else if(SYSCON->MAINCLKSELA == 2U) + { + freq = CLOCK_GetWdtOscFreq(); + } + else if(SYSCON->MAINCLKSELA == 3U) + { + freq = CLOCK_GetFroHfFreq(); + } + else + {} + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + + case 3U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + break; + + } + + return freq; +} +uint32_t CLOCK_GetI2SMClkFreq(void) +{ + return s_I2S_Mclk_Freq; +} + +uint32_t CLOCK_GetAsyncApbClkFreq(void) +{ + async_clock_src_t clkSrc; + uint32_t clkRate; + + clkSrc = CLOCK_GetAsyncApbClkSrc(); + + switch (clkSrc) + { + case kCLOCK_AsyncMainClk: + clkRate = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_AsyncFro12Mhz: + clkRate = CLK_FRO_12MHZ; + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Get FLEXCOMM Clk */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch(SYSCON->FXCOMCLKSEL[id]) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 4U: + freq = CLOCK_GetFrgClkFreq(); + break; + + default: + break; + } + + return freq; +} + +/* Get FRG Clk */ +uint32_t CLOCK_GetFRGInputClock(void) +{ + uint32_t freq = 0U; + + switch(SYSCON->FRGCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + default: + break; + } + + return freq; +} + +/* Get DMIC Clk */ +uint32_t CLOCK_GetDmicClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->DMICCLKSEL) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 4U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 5U: + freq = CLOCK_GetWdtOscFreq(); + break; + default: + break; + } + + return freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);; +} + +uint32_t CLOCK_SetFRGClock(uint32_t freq) +{ + uint32_t input = CLOCK_GetFRGInputClock(); + uint32_t mul; + + if ((freq > 48000000) || (freq > input) || (input / freq >= 2)) + { + /* FRG output frequency should be less than equal to 48MHz */ + return 0; + } + else + { + mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); + SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK; + return 1; + } +} + +/* Get FRG Clk */ +uint32_t CLOCK_GetFrgClkFreq(void) +{ + uint32_t freq = 0U; + + if((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) + { + freq = ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) / + ((SYSCON_FRGCTRL_DIV_MASK + 1) + ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)); + } + else + { + freq = 0U; + } + + return freq; +} + +uint32_t CLOCK_GetUsbClkFreq(void) +{ + uint32_t freq = 0U; + + if(SYSCON->USBCLKSEL == 0U) + { + freq = CLOCK_GetFroHfFreq(); + } + else if (SYSCON->USBCLKSEL == 1) + { + freq = CLOCK_GetPllOutFreq(); + } + else + {} + + return freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U); +} + +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_PllOut: + freq = CLOCK_GetPllOutFreq(); + break; + case kCLOCK_UsbClk: + freq = CLOCK_GetUsbClkFreq(); + break; + case kCLOCK_WdtOsc: + freq = CLOCK_GetWdtOscFreq(); + break; + case kCLOCK_Frg: + freq = CLOCK_GetFrgClkFreq(); + break; + case kCLOCK_Dmic: + freq = CLOCK_GetDmicClkFreq(); + break; + + case kCLOCK_AsyncApbClk: + freq = CLOCK_GetAsyncApbClkFreq(); + break; + + case kCLOCK_FlexI2S: + freq = CLOCK_GetI2SMClkFreq(); + break; + + case kCLOCK_Flexcomm0: + freq = CLOCK_GetFlexCommClkFreq(0U); + break; + case kCLOCK_Flexcomm1: + freq = CLOCK_GetFlexCommClkFreq(1U); + break; + case kCLOCK_Flexcomm2: + freq = CLOCK_GetFlexCommClkFreq(2U); + break; + case kCLOCK_Flexcomm3: + freq = CLOCK_GetFlexCommClkFreq(3U); + break; + case kCLOCK_Flexcomm4: + freq = CLOCK_GetFlexCommClkFreq(4U); + break; + case kCLOCK_Flexcomm5: + freq = CLOCK_GetFlexCommClkFreq(5U); + break; + case kCLOCK_Flexcomm6: + freq = CLOCK_GetFlexCommClkFreq(6U); + break; + case kCLOCK_Flexcomm7: + freq = CLOCK_GetFlexCommClkFreq(7U); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Set the FLASH wait states for the passed frequency */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) +{ + if (iFreq <= 12000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle); + } + else if (iFreq <= 30000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle); + } + else if (iFreq <= 60000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle); + } + else if (iFreq <= 85000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle); + } + else + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle); + } +} + +/* Find encoded NDEC value for raw N value, max N = NVALMAX */ +static uint32_t pllEncodeN(uint32_t N) +{ + uint32_t x, i; + + /* Find NDec */ + switch (N) + { + case 0U: + x = 0x3FFU; + break; + + case 1U: + x = 0x302U; + break; + + case 2U: + x = 0x202U; + break; + + default: + x = 0x080U; + for (i = N; i <= NVALMAX; i++) + { + x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); + } + break; + } + + return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P); +} + +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC) +{ + uint32_t n, x, i; + + /* Find NDec */ + switch (NDEC) + { + case 0x3FFU: + n = 0U; + break; + + case 0x302U: + n = 1U; + break; + + case 0x202U: + n = 2U; + break; + + default: + x = 0x080U; + n = 0xFFFFFFFFU; + for (i = NVALMAX; ((i >= 3U) && (n == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); + if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) + { + /* Decoded value of NDEC */ + n = i; + } + } + break; + } + + return n; +} + +/* Find encoded PDEC value for raw P value, max P = PVALMAX */ +static uint32_t pllEncodeP(uint32_t P) +{ + uint32_t x, i; + + /* Find PDec */ + switch (P) + { + case 0U: + x = 0x7FU; + break; + + case 1U: + x = 0x62U; + break; + + case 2U: + x = 0x42U; + break; + + default: + x = 0x10U; + for (i = P; i <= PVALMAX; i++) + { + x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); + } + break; + } + + return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P); +} + +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC) +{ + uint32_t p, x, i; + + /* Find PDec */ + switch (PDEC) + { + case 0x7FU: + p = 0U; + break; + + case 0x62U: + p = 1U; + break; + + case 0x42U: + p = 2U; + break; + + default: + x = 0x10U; + p = 0xFFFFFFFFU; + for (i = PVALMAX; ((i >= 3U) && (p == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); + if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) + { + /* Decoded value of PDEC */ + p = i; + } + } + break; + } + + return p; +} + +/* Find encoded MDEC value for raw M value, max M = MVALMAX */ +static uint32_t pllEncodeM(uint32_t M) +{ + uint32_t i, x; + + /* Find MDec */ + switch (M) + { + case 0U: + x = 0x1FFFFU; + break; + + case 1U: + x = 0x18003U; + break; + + case 2U: + x = 0x10003U; + break; + + default: + x = 0x04000U; + for (i = M; i <= MVALMAX; i++) + { + x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU); + } + break; + } + + return x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P); +} + +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC) +{ + uint32_t m, i, x; + + /* Find MDec */ + switch (MDEC) + { + case 0x1FFFFU: + m = 0U; + break; + + case 0x18003U: + m = 1U; + break; + + case 0x10003U: + m = 2U; + break; + + default: + x = 0x04000U; + m = 0xFFFFFFFFU; + for (i = MVALMAX; ((i >= 3U) && (m == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 1U)) & 1) << 14U) | ((x >> 1U) & 0x3FFFU); + if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) + { + /* Decoded value of MDEC */ + m = i; + } + } + break; + } + + return m; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + /* bandwidth: compute selP from Multiplier */ + if (M < 60U) + { + *pSelP = (M >> 1U) + 1U; + } + else + { + *pSelP = PVALMAX - 1U; + } + + /* bandwidth: compute selI from Multiplier */ + if (M > 16384U) + { + *pSelI = 1U; + } + else if (M > 8192U) + { + *pSelI = 2U; + } + else if (M > 2048U) + { + *pSelI = 4U; + } + else if (M >= 501U) + { + *pSelI = 8U; + } + else if (M >= 60U) + { + *pSelI = 4U * (1024U / (M + 9U)); + } + else + { + *pSelI = (M & 0x3CU) + 4U; + } + + if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT)) + { + *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT); + } + + *pSelR = 0U; +} + +/* Get predivider (N) from PLL NDEC setting */ +static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U) + { + /* Decode NDEC value to get (N) pre divider */ + preDiv = pllDecodeN(nDecReg & 0x3FFU); + if (preDiv == 0U) + { + preDiv = 1U; + } + } + + /* Adjusted by 1, directi is used to bypass */ + return preDiv; +} + +/* Get postdivider (P) from PLL PDEC setting */ +static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) +{ + uint32_t postDiv = 1U; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U) + { + /* Decode PDEC value to get (P) post divider */ + postDiv = 2U * pllDecodeP(pDecReg & 0x7FU); + if (postDiv == 0U) + { + postDiv = 2U; + } + } + + /* Adjusted by 1, directo is used to bypass */ + return postDiv; +} + +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) +{ + uint32_t mMult = 1U; + + /* Decode MDEC value to get (M) multiplier */ + mMult = pllDecodeM(mDecReg & 0x1FFFFU); + + /* Extra multiply by 2 needed? */ + if ((ctrlReg & (SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK)) == 0U) + { + mMult = mMult << 1U; + } + + if (mMult == 0U) + { + mMult = 1U; + } + + return mMult; +} + +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +/* + * Set PLL output based on desired output rate. + * In this function, the it calculates the PLL setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPllConfigInternal( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) +{ + uint32_t nDivOutHz, fccoHz, multFccoDiv; + uint32_t pllPreDivider, pllMultiplier, pllBypassFBDIV2, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, bandsel, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 0U; /* 0 implies post-divider will be disabled */ + pllDirectOutput = 1U; + if (useFeedbackDiv2) + { + /* Using feedback divider for M, so disable bypass */ + pllBypassFBDIV2 = 0U; + } + else + { + pllBypassFBDIV2 = 1U; + } + multFccoDiv = (2U - pllBypassFBDIV2); + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 2MHz and 4MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 4MHz */ + pllPreDivider = finHz / ((PLL_MIN_IN_SSMODE + PLL_MAX_IN_SSMODE) / 2); + if (pllPreDivider > NVALMAX) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz)); + + if (a > 20000U) + { + a = (multFccoDiv * finHz) / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv; + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, pllBypassFBDIV2, &pllSelP, &pllSelI, &pllSelR); + bandsel = 1U; + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->syspllssctrl[0] = + (PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) | (1U << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)); + + /* Power down SSC, not used */ + pSetup->syspllssctrl[1] = (1U << SYSCON_SYSPLLSSCTRL1_PD_SHIFT); + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = pllSelI = pllSelP = 0U; + bandsel = 0U; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = ((uint64_t)(fccoHz % (multFccoDiv * nDivOutHz)) << 11U) / (multFccoDiv * nDivOutHz); + + /* MDEC set by SSC */ + pSetup->syspllssctrl[0U] = 0U; + + /* Set multiplier */ + pSetup->syspllssctrl[1] = PLL_SSCG1_MD_INT_SET(pllMultiplier) | PLL_SSCG1_MD_FRACT_SET((uint32_t)fc); + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->syspllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider)); + pSetup->syspllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider)); + + /* PLL control */ + pSetup->syspllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) | /* Filter coefficient */ + (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) | /* PLL bypass mode disabled */ + (pllBypassFBDIV2 << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT) | /* Extra M / 2 divider? */ + (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) | /* SS/fractional mode disabled */ + (bandsel << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT) | /* Manual bandwidth selection enabled */ + (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */ + + return kStatus_PLL_Success; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseFeedbackDiv2Cache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPllConfig( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ( (finHz == s_FinHzCache[i]) + && (foutHz == s_FoutHzCache[i]) + && (useFeedbackDiv2 == s_UseFeedbackDiv2Cache[i]) + && (useSS == s_UseSSCache[i]) ) + { + /* Hit the target in cache buffer. */ + pSetup->syspllctrl = s_PllSetupCacheStruct[i].syspllctrl; + pSetup->syspllndec = s_PllSetupCacheStruct[i].syspllndec; + pSetup->syspllpdec = s_PllSetupCacheStruct[i].syspllpdec; + pSetup->syspllssctrl[0] = s_PllSetupCacheStruct[i].syspllssctrl[0]; + pSetup->syspllssctrl[1] = s_PllSetupCacheStruct[i].syspllssctrl[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPllConfigInternal( finHz, foutHz, pSetup, useFeedbackDiv2, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseFeedbackDiv2Cache[s_PllSetupCacheIdx] = useFeedbackDiv2; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllctrl = pSetup->syspllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllndec = pSetup->syspllndec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllpdec = pSetup->syspllpdec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllssctrl[0] = pSetup->syspllssctrl[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllssctrl[1] = pSetup->syspllssctrl[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* Update local PLL rate variable */ +static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup); +} + +/* Return System PLL input clock rate */ +uint32_t CLOCK_GetSystemPLLInClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetWdtOscFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return System PLL output clock rate from setup structure */ +uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) +{ + uint32_t prediv, postdiv, mMult, inPllRate; + uint64_t workRate; + + /* Get the input clock frequency of PLL. */ + inPllRate = CLOCK_GetSystemPLLInClockRate(); + + /* + * If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock. + */ + if ((pSetup->syspllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U) + { + /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ + /* + * 1. Pre-divider + * Pre-divider is only available when the DIRECTI is disabled. + */ + if (0U == (pSetup->syspllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK)) + { + prediv = findPllPreDiv(pSetup->syspllctrl, pSetup->syspllndec); + } + else + { + prediv = 1U; /* The pre-divider is bypassed. */ + } + /* Adjust input clock */ + inPllRate = inPllRate / prediv; + + /* + * 2. M divider + * If using the SS, use the multiplier. + */ + if (pSetup->syspllssctrl[1] & (SYSCON_SYSPLLSSCTRL1_PD_MASK)) + { + /* MDEC used for rate */ + mMult = findPllMMult(pSetup->syspllctrl, pSetup->syspllssctrl[0]); + workRate = (uint64_t)inPllRate * (uint64_t)mMult; + } + else + { + uint64_t fract; + + /* SS multipler used for rate */ + mMult = (pSetup->syspllssctrl[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P; + workRate = (uint64_t)inPllRate * (uint64_t)mMult; + + /* Adjust by fractional */ + fract = (uint64_t)(pSetup->syspllssctrl[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P; + workRate = workRate + ((inPllRate * fract) / 0x800U); + } + + /* + * 3. Post-divider + * Post-divider is only available when the DIRECTO is disabled. + */ + if (0U == (pSetup->syspllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK)) + { + postdiv = findPllPostDiv(pSetup->syspllctrl, pSetup->syspllpdec); + } + else + { + postdiv = 1U; /* The post-divider is bypassed. */ + } + workRate = workRate / ((uint64_t)postdiv); + } + else + { + /* In bypass mode */ + workRate = (uint64_t)inPllRate; + } + + return (uint32_t)workRate; +} + +/* Set the current PLL Rate */ +void CLOCK_SetStoredPLLClockRate(uint32_t rate) +{ + s_Pll_Freq = rate; +} + +/* Return System PLL output clock rate */ +uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll_Freq == 0U)) + { + Setup.syspllctrl = SYSCON->SYSPLLCTRL; + Setup.syspllndec = SYSCON->SYSPLLNDEC; + Setup.syspllpdec = SYSCON->SYSPLLPDEC; + Setup.syspllssctrl[0] = SYSCON->SYSPLLSSCTRL0; + Setup.syspllssctrl[1] = SYSCON->SYSPLLSSCTRL1; + + CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup); + } + + rate = s_Pll_Freq; + + return rate; +} + +/* Set PLL output based on the passed PLL setup data */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); + bool useFbDiv2; + + pll_error_t pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) + { + inRate = pControl->inputRate; + } + else + { + inRate = CLOCK_GetSystemPLLInClockRate(); + } + + if ((pSetup->flags & PLL_SETUPFLAG_USEFEEDBACKDIV2) != 0U) + { + useFbDiv2 = true; + } + else + { + useFbDiv2 = false; + } + + /* PLL flag options */ + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, useFbDiv2, useSS); + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->syspllssctrl[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->syspllssctrl[1] |= (1U << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Set PLL output from PLL setup structure */ +pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) +{ + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->SYSPLLCTRL = pSetup->syspllctrl; + SYSCON->SYSPLLNDEC = pSetup->syspllndec; + SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->SYSPLLPDEC = pSetup->syspllpdec; + SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0]; + SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */ + SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1]; + SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1] | (1U << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT); /* latch */ + + /* Flags for lock or power on */ + if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U) + { + /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ + volatile uint32_t delayX; + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U); + + /* Initialize and power up PLL */ + SYSCON->SYSPLLSSCTRL0 = maxCCO; + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + + /* Set mreq to activate */ + SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U); + + /* Delay for 72 uSec @ 12Mhz */ + for (delayX = 0U; delayX < 172U; ++delayX) + { + } + + /* clear mreq to prepare for restoring mreq */ + SYSCON->SYSPLLSSCTRL0 = curSSCTRL; + + /* set original value back and activate */ + SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U); + + /* Enable peripheral states by setting low */ + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + } + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + while (CLOCK_IsSystemPLLLocked() == false) + { + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup); + + /* System voltage adjustment, occurs prior to setting main system clock */ + if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) + { + POWER_SetVoltageForFreq(s_Pll_Freq); + } + + return kStatus_PLL_Success; +} + +/* Setup PLL Frequency from pre-calculated value */ +pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) +{ + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); + + /* Write PLL setup data */ + SYSCON->SYSPLLCTRL = pSetup->syspllctrl; + SYSCON->SYSPLLNDEC = pSetup->syspllndec; + SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->SYSPLLPDEC = pSetup->syspllpdec; + SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0]; + SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */ + SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1]; + SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1] | (1U << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT); /* latch */ + + /* Flags for lock or power on */ + if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) + { + /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ + volatile uint32_t delayX; + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U); + + /* Initialize and power up PLL */ + SYSCON->SYSPLLSSCTRL0 = maxCCO; + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + + /* Set mreq to activate */ + SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U); + + /* Delay for 72 uSec @ 12Mhz */ + for (delayX = 0U; delayX < 172U; ++delayX) + { + } + + /* clear mreq to prepare for restoring mreq */ + SYSCON->SYSPLLSSCTRL0 = curSSCTRL; + + /* set original value back and activate */ + SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U); + + /* Enable peripheral states by setting low */ + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + } + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + while (CLOCK_IsSystemPLLLocked() == false) + { + } + } + + /* Update current programmed PLL rate var */ + s_Pll_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Set System PLL clock based on the input frequency and multiplier */ +void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) +{ + uint32_t cco_freq = input_freq * multiply_by; + uint32_t pdec = 1U; + uint32_t selr; + uint32_t seli; + uint32_t selp; + uint32_t mdec, ndec; + + uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1); + + while (cco_freq < 75000000U) + { + multiply_by <<= 1U; /* double value in each iteration */ + pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ + cco_freq = input_freq * multiply_by; + } + selr = 0U; + if (multiply_by < 60U) + { + seli = (multiply_by & 0x3cU) + 4U; + selp = (multiply_by >> 1U) + 1U; + } + else + { + selp = 31U; + if (multiply_by > 16384U) + { + seli = 1U; + } + else if (multiply_by > 8192U) + { + seli = 2U; + } + else if (multiply_by > 2048U) + { + seli = 4U; + } + else if (multiply_by >= 501U) + { + seli = 8U; + } + else + { + seli = 4U * (1024U / (multiply_by + 9U)); + } + } + + if (pdec > 1U) + { + directo = 0U; /* use post divider */ + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ + switch (pdec) + { + case 1U: + pdec = 0x62U; /* 1 * 2 */ + break; + case 2U: + pdec = 0x42U; /* 2 * 2 */ + break; + case 4U: + pdec = 0x02U; /* 4 * 2 */ + break; + case 8U: + pdec = 0x0bU; /* 8 * 2 */ + break; + case 16U: + pdec = 0x11U; /* 16 * 2 */ + break; + case 32U: + pdec = 0x08U; /* 32 * 2 */ + break; + default: + pdec = 0x08U; + break; + } + } + + mdec = PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(multiply_by)); + ndec = 0x302U; /* pre divide by 1 (hardcoded) */ + + SYSCON->SYSPLLCTRL = SYSCON_SYSPLLCTRL_BANDSEL(1) | directo | SYSCON_SYSPLLCTRL_BYPASSCCODIV2(1) | + (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) | + (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT); + SYSCON->SYSPLLPDEC = pdec | (1U << 7U); /* set Pdec value and assert preq */ + SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */ + SYSCON->SYSPLLSSCTRL0 = + (1U << 18U) | (1U << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */ +} +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbd0); + + if (kCLOCK_UsbSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsbClk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + case 48000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsbClk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ + break; + default: + ret = false; + break; + } + /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ + SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | + SYSCON_FROCTRL_USBCLKADJ_MASK; + /* select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB_CLK); + } + else + { + /*TODO , we only implement FRO as usb clock source*/ + ret = false; + } + + CLOCK_EnableClock(kCLOCK_Usbd0); + + return ret; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.h new file mode 100644 index 00000000000..d63fd892e68 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_clock.h @@ -0,0 +1,896 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name ofcopyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_device_registers.h" +#include +#include +#include + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.0.2. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/*! @brief Clock ip name array for FLEXCOMM. */ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ + kCLOCK_FlexComm6, kCLOCK_FlexComm7 \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ + kCLOCK_MinUart6, kCLOCK_MinUart7 \ + } + +/*! @brief Clock ip name array for BI2C. */ +#define BI2C_CLOCKS \ + { \ + kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSI_CLOCKS \ + { \ + kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ + } +/*! @brief Clock ip name array for FLEXI2S. */ +#define FLEXI2S_CLOCKS \ + { \ + kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ + kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick \ + } +/*! @brief Clock ip name array for DMIC. */ +#define DMIC_CLOCKS \ + { \ + kCLOCK_DMic \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } +/*! @brief Clock ip name array for CT32B. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1 \ + } +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_Adc0 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for MRT. */ +#define SCT_CLOCKS \ + { \ + kCLOCK_Sct0 \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc \ + } +/*! @brief Clock ip name array for USBD. */ +#define USBD_CLOCKS \ + { \ + kCLOCK_Usbd0 \ + } + +/*! @brief Clock ip name array for GINT. GINT0 & GINT1 share same slot */ +#define GINT_CLOCKS \ + { \ + kCLOCK_Gint, kCLOCK_Gint \ + } + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define ASYNC_CLK_CTRL0 2 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), + kCLOCK_Regfile = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */ + kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), + kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), + kCLOCK_SctIpu0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), + kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), + kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), + kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), + kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), + kCLOCK_Pvtvf0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), + kCLOCK_Pvtvf1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), + kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), + kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), + + kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13), + kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14) +} clock_ip_name_t; + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_FroHf, /*!< FRO48/96 */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_PllOut, /*!< PLL Output */ + kCLOCK_UsbClk, /*!< USB input */ + kCLOCK_WdtOsc, /*!< Watchdog Oscillator */ + kCLOCK_Frg, /*!< Frg Clock */ + kCLOCK_Dmic, /*!< Digital Mic clock */ + kCLOCK_AsyncApbClk, /*!< Async APB clock */ + kCLOCK_FlexI2S, /*!< FlexI2S clock */ + kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */ + kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */ + kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */ + kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */ + kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */ + kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */ + kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */ + kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */ +} clock_name_t; + +/** + * Clock source selections for the asynchronous APB clock + */ +typedef enum _async_clock_src +{ + kCLOCK_AsyncMainClk = 0, /*!< Main System clock */ + kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */ +} async_clock_src_t; + +/*! @brief Clock Mux Switches +* The encoding is as follows each connection identified is 64bits wide +* starting from LSB upwards +* +* [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]* +* +*/ + +#define MUX_A(m, choice) (((m) << 0) | (((choice) + 1) << 8)) +#define MUX_B(m, choice) (((m) << 12) | (((choice) + 1) << 20)) +#define MUX_C(m, choice) (((m) << 24) | (((choice) + 1) << 32)) +#define MUX_D(m, choice) (((m) << 36) | (((choice) + 1) << 44)) +#define MUX_E(m, choice) (((m) << 48) | (((choice) + 1) << 56)) + +#define CM_MAINCLKSELA 0 +#define CM_MAINCLKSELB 1 +#define CM_CLKOUTCLKSELA 2 +#define CM_CLKOUTCLKSELB 3 +#define CM_SYSPLLCLKSEL 4 +#define CM_USBPLLCLKSEL 5 +#define CM_AUDPLLCLKSEL 6 +#define CM_SCTPLLCLKSEL 7 +#define CM_SPIFICLKSEL 8 +#define CM_ADCASYNCCLKSEL 9 +#define CM_USBCLKSEL 10 +#define CM_USB1CLKSEL 11 +#define CM_FXCOMCLKSEL0 12 +#define CM_FXCOMCLKSEL1 13 +#define CM_FXCOMCLKSEL2 14 +#define CM_FXCOMCLKSEL3 15 +#define CM_FXCOMCLKSEL4 16 +#define CM_FXCOMCLKSEL5 17 +#define CM_FXCOMCLKSEL6 18 +#define CM_FXCOMCLKSEL7 19 +#define CM_FXCOMCLKSEL8 20 +#define CM_FXCOMCLKSEL9 21 +#define CM_FXCOMCLKSEL10 22 +#define CM_FXCOMCLKSEL11 23 +#define CM_FXI2S0MCLKCLKSEL 24 +#define CM_FXI2S1MCLKCLKSEL 25 +#define CM_FRGCLKSEL 26 +#define CM_DMICCLKSEL 27 + +#define CM_ASYNCAPB 28 + +typedef enum _clock_attach_id +{ + + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0), + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0), + kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0), + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0), + kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2), + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3), + + kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), + kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), + kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), + kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), + kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), + + kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), + kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), + + kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), + kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), + + kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0), + kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), + kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), + kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), + + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), + kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), + kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), + kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), + + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), + kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), + kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), + kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), + + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), + kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), + kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), + kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), + + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), + kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), + kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), + kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), + + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), + kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), + kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), + kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), + + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), + kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), + kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), + kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), + + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), + kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), + kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), + kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), + + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), + kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), + kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), + kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), + + kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), + kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), + kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), + kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), + kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), + + kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0), + kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1), + kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7), + + kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), + kFRO_HF_to_DMIC = MUX_A(CM_DMICCLKSEL, 1), + kSYS_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), + kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), + kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4), + kWDT_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 5), + kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), + + kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0), + kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1), + kMAIN_CLK_to_USB_CLK = MUX_A(CM_USBCLKSEL, 2), + kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7), + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), + kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), + kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), + kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), + kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), + kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), + kNONE_to_NONE = 0x80000000U, +} clock_attach_id_t; + +/* Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk = 0, + kCLOCK_DivTraceClk = 1, + kCLOCK_DivAhbClk = 32, + kCLOCK_DivClkOut = 33, + kCLOCK_DivSpifiClk = 36, + kCLOCK_DivAdcAsyncClk = 37, + kCLOCK_DivUsbClk = 38, + kCLOCK_DivFrg = 40, + kCLOCK_DivDmicClk = 42, + kCLOCK_DivFxI2s0MClk = 43 +} clock_div_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + if (index < 2) + { + SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } + else + { + ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } +} + +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + if (index < 2) + { + SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } + else + { + ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } +} +/** + * @brief FLASH Access time definitions + */ +typedef enum _clock_flashtim +{ + kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */ + kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */ + kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */ + kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */ + kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */ + kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */ + kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */ + kCLOCK_Flash8Cycle /*!< Flash accesses use 8 CPU clocks */ +} clock_flashtim_t; + +/** + * @brief Set FLASH memory access time in clocks + * @param clks : Clock cycles for FLASH access + * @return Nothing + */ +static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks) +{ + uint32_t tmp; + + tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK); + + /* Don't alter lower bits */ + SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT); +} + +/** + * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq); +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @param reset : Whether to reset the divider counter. + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); +/** + * @brief Set the flash wait states for the input freuqency. + * @param iFreq : Input frequency + * @return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! @brief Return Input frequency for the Fractional baud rate generator + * @return Input Frequency for FRG + */ +uint32_t CLOCK_GetFRGInputClock(void); + +/*! @brief Return Input frequency for the DMIC + * @return Input Frequency for DMIC + */ +uint32_t CLOCK_GetDmicClkFreq(void); + +/*! @brief Return Input frequency for the FRG + * @return Input Frequency for FRG + */ +uint32_t CLOCK_GetFrgClkFreq(void); + +/*! @brief Set output of the Fractional baud rate generator + * @param freq : Desired output frequency + * @return Error Code 0 - fail 1 - success + */ +uint32_t CLOCK_SetFRGClock(uint32_t freq); + +/*! @brief Return Frequency of FRO 12MHz + * @return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void); +/*! @brief Return Frequency of External Clock + * @return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void); +/*! @brief Return Frequency of Watchdog Oscillator + * @return Frequency of Watchdog Oscillator + */ +uint32_t CLOCK_GetWdtOscFreq(void); +/*! @brief Return Frequency of High-Freq output of FRO + * @return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of USB + * @return Frequency of USB + */ +uint32_t CLOCK_GetUsbClkFreq(void); +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPllOutFreq(void); +/*! @brief Return Frequency of 32kHz osc + * @return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void); +/*! @brief Return Frequency of Core System + * @return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); +/*! @brief Return Frequency of I2S MCLK Clock + * @return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void); +/*! @brief Return Frequency of Flexcomm functional Clock + * @return Frequency of Flexcomm functional Clock + */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); +/*! @brief Return Asynchronous APB Clock source + * @return Asynchronous APB CLock source + */ +__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void) +{ + return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3); +} +/*! @brief Return Frequency of Asynchronous APB Clock + * @return Frequency of Asynchronous APB Clock Clock + */ +uint32_t CLOCK_GetAsyncApbClkFreq(void); +/*! @brief Return System PLL input clock rate + * @return System PLL input clock rate + */ +uint32_t CLOCK_GetSystemPLLInClockRate(void); + +/*! @brief Return System PLL output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return System PLL output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute); + +/*! @brief Enables and disables PLL bypass mode + * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass + * @return System PLL output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass) +{ + if (bypass) + { + SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); + } + else + { + SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); + } +} + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void) +{ + return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0); +} + +/*! @brief Store the current PLL rate + * @param rate: Current rate of the PLL + * @return Nothing + **/ +void CLOCK_SetStoredPLLClockRate(uint32_t rate); + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the + * configuration structure must be assigned with the expected PLL frequency. If the + * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration + * function and the driver will determine the PLL rate from the currently selected + * PLL source. This flag might be used to configure the PLL input clock more accurately + * when using the WDT oscillator or a more dyanmic CLKIN source.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT \ + (1 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ + \ \ \ + \ \ \ \ \ + \ \ \ \ \ \ \ + \ \ \ \ \ \ \ \ \ + hardware */ + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the SYSPLLSSCTRL1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ + kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ + kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the SYSPLLSSCTRL1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 23), /*!< k = 1 */ + kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ + kSS_MR_K2 = (3 << 23), /*!< k = 2 */ + kSS_MR_K3 = (4 << 23), /*!< k = 3 */ + kSS_MR_K4 = (5 << 23), /*!< k = 4 */ + kSS_MR_K6 = (6 << 23), /*!< k = 6 */ + kSS_MR_K8 = (7 << 23) /*!< k = 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the SYSPLLSSCTRL1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0 << 26), /*!< no compensation */ + kSS_MC_RECC = (2 << 26), /*!< recommended setting */ + kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL setup structure flags for 'flags' field +* These flags control how the PLL setup function sets up the PLL +*/ +#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ +#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */ + +/*! @brief PLL setup structure +* This structure can be used to pre-build a PLL setup configuration +* at run-time and quickly set the PLL to the configuration. It can be +* populated with the PLL setup function. If powering up or waiting +* for PLL lock, the PLL input clock source should be configured prior +* to PLL setup. +*/ +typedef struct _pll_setup +{ + uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */ + uint32_t syspllndec; /*!< PLL NDEC register SYSPLLNDEC */ + uint32_t syspllpdec; /*!< PLL PDEC register SYSPLLPDEC */ + uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */ + uint32_t pllRate; /*!< Acutal PLL rate */ + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */ +} pll_error_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */ + kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */ + kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ + kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL( + 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */ +} clock_usb_src_t; + +/*! @brief Return System PLL output clock rate from setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate calculated from the setup structure + */ +uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup); + +/*! @brief Set PLL output based on the passed PLL setup data + * @param pControl : Pointer to populated PLL control structure to generate setup with + * @param pSetup : Pointer to PLL setup structure to be filled + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); + +/*! @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure +* @param flagcfg : Flag configuration for PLL config structure + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup); + +/*! @brief Set PLL output based on the multiplier and input frequency + * @param multiply_by : multiplier + * @param input_freq : Clock input frequency of the PLL + * @return Nothing + * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq); + +/*! @brief Disable USB FS clock. + * + * Disable USB FS clock. + */ +static inline void CLOCK_DisableUsbfs0Clock(void) +{ + CLOCK_DisableClock(kCLOCK_Usbd0); +} +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.c new file mode 100644 index 00000000000..903faf52b63 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.c @@ -0,0 +1,192 @@ +/* +* The Clear BSD License +* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP +* All rights reserved. +* +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted (subject to the limitations in the disclaimer below) provided +* that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_common.h" +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned adress to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#ifndef QN908XC_SERIES +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + +#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) + { + SYSCON->STARTERP1 = 1u << intNumber; + } +#else + { + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + } +#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ +#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1)) + { + SYSCON->STARTERP1 &= ~(1u << intNumber); + } +#else + { + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1u << intNumber; + } +#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */ +} +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#endif /* QN908XC_SERIES */ + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); + void *p_align_addr, *p_addr = malloc(alignedsize); + + if (!p_addr) + { + return NULL; + } + + p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; + + return (void *)p_align_addr; +} + +void SDK_Free(void *ptr) +{ + mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + free((void *)((uint32_t)ptr - p_cb->offset)); +} + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.h new file mode 100644 index 00000000000..a53dbc2713d --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_common.h @@ -0,0 +1,576 @@ +/* + * The Clear BSD License + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version 2.0.0. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console base on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console base on SWO. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http://supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__ARMCC_VERSION)) +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __align(alignbytes) var +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var +#endif +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/* @} */ + +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif + } + + /*! + * @brief Enaable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.c new file mode 100644 index 00000000000..840817776a6 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.c @@ -0,0 +1,146 @@ +/* + * The Clear BSD License + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" +#endif + + +#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT +/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ +#define CRC_DRIVER_DEFAULT_REVERSE_IN false +/*< Default is no bit reverse */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false +/*< Default is without complement of written data */ +#define CRC_DRIVER_DEFAULT_REVERSE_OUT false +/*< Default is no bit reverse */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable clock to CRC */ + CLOCK_EnableClock(kCLOCK_Crc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* configure CRC module and write the seed */ + base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | + CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | + CRC_MODE_CMPL_SUM(config->complementOut); + base->SEED = config->seed; +} + +void CRC_GetDefaultConfig(crc_config_t *config) +{ + static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, + CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; + + *config = default_config; +} + +void CRC_Reset(CRC_Type *base) +{ + crc_config_t config; + CRC_GetDefaultConfig(&config); + CRC_Init(base, &config); +} + +void CRC_GetConfig(CRC_Type *base, crc_config_t *config) +{ + /* extract CRC mode settings */ + uint32_t mode = base->MODE; + config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT); + config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); + config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); + config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); + config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); + + /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ + base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); + + /* now we can obtain intermediate raw CRC sum value */ + config->seed = base->SUM; + + /* restore original CRC sum bit reverse and 1's complement setting */ + base->MODE = mode; +} + +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((dataSize) && ((uint32_t)data & 3U)) + { + *((__O uint8_t *)&(base->WR_DATA)) = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)data; + while (dataSize >= sizeof(uint32_t)) + { + *((__O uint32_t *)&(base->WR_DATA)) = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (dataSize) + { + *((__O uint8_t *)&(base->WR_DATA)) = *data; + data++; + dataSize--; + } +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.h new file mode 100644 index 00000000000..b2f8244b834 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_crc.h @@ -0,0 +1,207 @@ +/* + * The Clear BSD License + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CRC_H_ +#define _FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CRC driver version. Version 2.0.1. + * + * Current version: 2.0.1 + * + * Change log: + * - Version 2.0.0 + * - initial version + * - Version 2.0.1 + * - add explicit type cast when writing to WR_DATA + */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ +#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC polynomials to use. */ +typedef enum _crc_polynomial +{ + kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ + kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ + kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ +} crc_polynomial_t; + +/*! +* @brief CRC protocol configuration. +* +* This structure holds the configuration for the CRC protocol. +* +*/ +typedef struct _crc_config +{ + crc_polynomial_t polynomial; /*!< CRC polynomial. */ + bool reverseIn; /*!< Reverse bits on input. */ + bool complementIn; /*!< Perform 1's complement on input. */ + bool reverseOut; /*!< Reverse bits on output. */ + bool complementOut; /*!< Perform 1's complement on output. */ + uint32_t seed; /*!< Starting checksum value. */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This functions enables the CRC peripheral clock in the LPC SYSCON block. + * It also configures the CRC engine and starts checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This functions disables the CRC peripheral clock in the LPC SYSCON block. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* disable clock to CRC */ + CLOCK_DisableClock(kCLOCK_Crc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief resets CRC peripheral module. + * + * @param base CRC peripheral address. + */ +void CRC_Reset(CRC_Type *base); + +/*! + * @brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * @code + * config->polynomial = kCRC_Polynomial_CRC_CCITT; + * config->reverseIn = false; + * config->complementIn = false; + * config->reverseOut = false; + * config->complementOut = false; + * config->seed = 0xFFFFU; + * @endcode + * + * @param config CRC protocol configuration structure + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. + * + * The values, including seed, can be used to resume CRC calculation later. + + * @param base CRC peripheral address. + * @param config CRC protocol configuration structure + */ +void CRC_GetConfig(CRC_Type *base, crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size of the input data buffer in bytes. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads 32-bit checksum from the CRC module. + * + * Reads CRC data register. + * + * @param base CRC peripheral address. + * @return final 32-bit checksum, after configured bit reverse and complement operations. + */ +static inline uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->SUM; +} + +/*! + * @brief Reads 16-bit checksum from the CRC module. + * + * Reads CRC data register. + * + * @param base CRC peripheral address. + * @return final 16-bit checksum, after configured bit reverse and complement operations. + */ +static inline uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + return (uint16_t)base->SUM; +} + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_CRC_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.c new file mode 100644 index 00000000000..87f1d2453b4 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.c @@ -0,0 +1,449 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ctimer.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif + +/*! @brief Pointers real ISRs installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (s_ctimerBases[instance] == base) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module */ + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); + + /* Setup the cimer mode and count select */ + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); + + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + DisableIRQ(s_ctimerIRQ[index]); +} + +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +status_t CTIMER_SetupPwm(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0); + + uint32_t reg; + uint32_t period, pulsePeriod = 0; + uint32_t timerClock = srcClock_Hz / (base->PR + 1); + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == kCTIMER_Match_3) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1U << matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = (timerClock / pwmFreq_Hz) - 1; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0) + { + pulsePeriod = period + 1; + } + else + { + pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; + } + + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = period; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt) +{ + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == kCTIMER_Match_3) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1U << matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) +{ + uint32_t pulsePeriod = 0, period; + + /* Match channel 3 defines the PWM period */ + period = base->MR[kCTIMER_Match_3]; + + /* Calculate pulse width match value */ + pulsePeriod = (period * dutyCyclePercent) / 100; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0) + { + pulsePeriod = period + 1; + } + else + { + pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; + } + + /* Update dutycycle */ + base->MR[matchChannel] = pulsePeriod; +} + +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3))); + reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3))); + reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2)); + reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel); + reg |= (uint32_t)config->outPinInitState << matchChannel; + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + EnableIRQ(s_ctimerIRQ[index]); + } +} + +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3)); + reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3); + EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} + +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0]) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ + { + mask = 0x01 << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if ((int_stat & mask) && (s_ctimerCallback[index][i])) + { + s_ctimerCallback[index][i](int_stat); + } + } + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.h new file mode 100644 index 00000000000..6392451b3f7 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_ctimer.h @@ -0,0 +1,496 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_CTIMER_H_ +#define _FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ +/*@}*/ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Register callback. + * + * @param base Ctimer peripheral base address + * @param cb_func callback function + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + + /* Enable capture interrupts */ + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + + /* Disable capture interrupts */ + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + + /* Get all the capture interrupts enabled */ + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.c new file mode 100644 index 00000000000..5eaf1c5d648 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.c @@ -0,0 +1,481 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMA. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetInstance(DMA_Type *base); + +/*! + * @brief Get virtual channel number. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMA instance number to base pointer. */ +static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map DMA instance number to clock name. */ +static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Array to map DMA instance number to IRQ number. */ +static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; + +/*! @brief Pointers to transfer handle for each DMA channel. */ +static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; + +/*! @brief Static table of descriptors */ +#if defined(__ICCARM__) +#pragma data_alignment = FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE +static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; +#elif defined(__CC_ARM) +__attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) +static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; +#elif defined(__GNUC__) +__attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) +static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t DMA_GetInstance(DMA_Type *base) +{ + int32_t instance; + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) + { + if (s_dmaBases[instance] == base) + { + break; + } + } + assert(instance < ARRAY_SIZE(s_dmaBases)); + + return instance; +} + +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) +{ + uint32_t startChannel = 0, instance = 0; + uint32_t i = 0; + + instance = DMA_GetInstance(base); + + /* Compute start channel */ + for (i = 0; i < instance; i++) + { + startChannel += FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); + } + + return startChannel; +} + +void DMA_Init(DMA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable dma clock gate */ + CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* set descriptor table */ + base->SRAMBASE = (uint32_t)s_dma_descriptor_table; + /* enable dma peripheral */ + base->CTRL |= DMA_CTRL_ENABLE_MASK; +} + +void DMA_Deinit(DMA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Disable DMA peripheral */ + base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); +} + +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) +{ + assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); + + uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | + DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); + tmp = base->CHANNEL[channel].CFG & (~tmp); + tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + base->CHANNEL[channel].CFG = tmp; +} + +/*! + * @brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + + /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes + * impossible to distinguish between: + * - transfer finishes (represented by value '0x3FF') + * - and remaining 1024 bytes to transfer (value 0x3FF) + * for all descriptor in chain, except the last one. + * If you decide to use this function, please use 1023 transfers as maximal value */ + + /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ + if ((!DMA_ChannelIsActive(base, channel)) && + (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) + { + return 0; + } + + return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + + 1; +} + +static void DMA_SetupDescriptor( + dma_descriptor_t *desc, uint32_t xfercfg, void *srcEndAddr, void *dstEndAddr, void *nextDesc) +{ + desc->xfercfg = xfercfg; + desc->srcEndAddr = srcEndAddr; + desc->dstEndAddr = dstEndAddr; + desc->linkToNextDesc = nextDesc; +} + +/* Verify and convert dma_xfercfg_t to XFERCFG register */ +static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) +{ + assert(xfercfg != NULL); + /* check source increment */ + assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4)); + /* check destination increment */ + assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4)); + /* check data width */ + assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4)); + /* check transfer count */ + assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); + + uint32_t xfer = 0, tmp; + /* set valid flag - descriptor is ready now */ + xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0); + /* set reload - allow link to next descriptor */ + xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0); + /* set swtrig flag - start transfer */ + xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig ? 1 : 0); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig ? 1 : 0); + /* set INTA */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0); + /* set INTB */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0); + /* set data width */ + tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1; + xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp); + /* set source increment value */ + tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc; + xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp); + /* set destination increment value */ + tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc; + xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1); + + /* store xferCFG */ + *xfercfg_addr = xfer; +} + +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) +{ + uint32_t xfercfg_reg = 0; + + assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg)); + assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth)); + assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth)); + assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16)); + + /* Setup channel configuration */ + DMA_SetupXferCFG(xfercfg, &xfercfg_reg); + + /* Set descriptor structure */ + DMA_SetupDescriptor( + desc, xfercfg_reg, (uint8_t *)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), + (uint8_t *)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), nextDesc); +} + +void DMA_AbortTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + + DMA_DisableChannel(handle->base, handle->channel); + while (DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & (1U << DMA_CHANNEL_INDEX(handle->channel))) + { + } + DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1U << DMA_CHANNEL_INDEX(handle->channel); + DMA_EnableChannel(handle->base, handle->channel); +} + +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + int32_t dmaInstance; + uint32_t startChannel = 0; + /* base address is invalid DMA instance */ + dmaInstance = DMA_GetInstance(base); + startChannel = DMA_GetVirtualStartChannel(base); + + memset(handle, 0, sizeof(*handle)); + handle->base = base; + handle->channel = channel; + s_DMAHandle[startChannel + channel] = handle; + /* Enable NVIC interrupt */ + EnableIRQ(s_dmaIRQNumber[dmaInstance]); +} + +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc) +{ + uint32_t xfer_count; + assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); + assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4)); + + /* check max */ + xfer_count = transferBytes / byteWidth; + assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth)); + + memset(config, 0, sizeof(*config)); + switch (type) + { + case kDMA_MemoryToMemory: + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 1; + config->isPeriph = false; + break; + case kDMA_PeripheralToMemory: + /* Peripheral register - source doesn't increment */ + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 1; + config->isPeriph = true; + break; + case kDMA_MemoryToPeripheral: + /* Peripheral register - destination doesn't increment */ + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + break; + case kDMA_StaticToStatic: + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + break; + default: + return; + } + + config->dstAddr = (uint8_t *)dstAddr; + config->srcAddr = (uint8_t *)srcAddr; + config->nextDesc = (uint8_t *)nextDesc; + config->xfercfg.transferCount = xfer_count; + config->xfercfg.byteWidth = byteWidth; + config->xfercfg.intA = true; + config->xfercfg.reload = nextDesc != NULL; + config->xfercfg.valid = true; +} + +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) +{ + assert((NULL != handle) && (NULL != config)); + uint32_t instance = DMA_GetInstance(handle->base); + + /* Previous transfer has not finished */ + if (DMA_ChannelIsActive(handle->base, handle->channel)) + { + return kStatus_DMA_Busy; + } + + /* enable/disable peripheral request */ + if (config->isPeriph) + { + DMA_EnableChannelPeriphRq(handle->base, handle->channel); + } + else + { + DMA_DisableChannelPeriphRq(handle->base, handle->channel); + } + + DMA_CreateDescriptor(&(s_dma_descriptor_table[instance][handle->channel]), &config->xfercfg, config->srcAddr, + config->dstAddr, config->nextDesc); + + return kStatus_Success; +} + +void DMA_StartTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + + uint32_t instance = DMA_GetInstance(handle->base); + + /* Enable channel interrupt */ + DMA_EnableChannelInterrupts(handle->base, handle->channel); + + /* If HW trigger is enabled - disable SW trigger */ + if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) + { + s_dma_descriptor_table[instance][handle->channel].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK); + } + /* Otherwise enable SW trigger */ + else + { + s_dma_descriptor_table[instance][handle->channel].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; + } + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[instance][handle->channel].xfercfg; + /* At this moment, the channel ACTIVE bit is set and application cannot modify + * or start another transfer using this channel. Channel ACTIVE bit is cleared by + * 'AbortTransfer' function or when the transfer finishes */ +} + +void DMA_IRQHandle(DMA_Type *base) +{ + dma_handle_t *handle; + int32_t channel_index; + uint32_t startChannel = DMA_GetVirtualStartChannel(base); + uint32_t i = 0; + + /* Find channels that have completed transfer */ + for (i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) + { + handle = s_DMAHandle[i + startChannel]; + /* Handle is not present */ + if (NULL == handle) + { + continue; + } + channel_index = DMA_CHANNEL_INDEX(handle->channel); + /* Channel uses INTA flag */ + if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1U << channel_index)) + { + /* Clear INTA flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1U << channel_index)); + if (handle->callback) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntA); + } + } + /* Channel uses INTB flag */ + if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1U << channel_index)) + { + /* Clear INTB flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1U << channel_index)); + if (handle->callback) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntB); + } + } + /* Error flag */ + if (DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1U << channel_index)) + { + /* Clear error flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1U << channel_index)); + if (handle->callback) + { + (handle->callback)(handle, handle->userData, false, kDMA_IntError); + } + } + } +} + +void DMA0_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if defined(DMA1) +void DMA1_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.h new file mode 100644 index 00000000000..ff2dee43881 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dma.h @@ -0,0 +1,509 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMA_H_ +#define _FSL_DMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dma + * @{ + */ + +/*! @file */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMA driver version */ +#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +#define DMA_MAX_TRANSFER_COUNT 0x400 + +#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +#endif + +/* Channel group consists of 32 channels. channel_group = (channel / 32) */ +#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) +/* Channel index in channel group. channel_index = (channel % 32) */ +#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F) + +#define DMA_COMMON_REG_GET(base, channel, reg) (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_CONST_REG_GET(base, channel, reg) (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_REG_SET(base, channel, reg, value) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) + +/*! @brief DMA descriptor structure */ +typedef struct _dma_descriptor +{ + uint32_t xfercfg; /*!< Transfer configuration */ + void *srcEndAddr; /*!< Last source address of DMA transfer */ + void *dstEndAddr; /*!< Last destination address of DMA transfer */ + void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ +} dma_descriptor_t; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_xfercfg +{ + bool valid; /*!< Descriptor is ready to transfer */ + bool reload; /*!< Reload channel configuration register after + current descriptor is exhausted */ + bool swtrig; /*!< Perform software trigger. Transfer if fired + when 'valid' is set */ + bool clrtrig; /*!< Clear trigger */ + bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ + bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ + uint8_t byteWidth; /*!< Byte width of data to transfer */ + uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ + uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ + uint16_t transferCount; /*!< Number of transfers */ +} dma_xfercfg_t; + +/*! @brief DMA channel priority */ +typedef enum _dma_priority +{ + kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ + kDMA_ChannelPriority1, /*!< Channel priority 1 */ + kDMA_ChannelPriority2, /*!< Channel priority 2 */ + kDMA_ChannelPriority3, /*!< Channel priority 3 */ + kDMA_ChannelPriority4, /*!< Channel priority 4 */ + kDMA_ChannelPriority5, /*!< Channel priority 5 */ + kDMA_ChannelPriority6, /*!< Channel priority 6 */ + kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ +} dma_priority_t; + +/*! @brief DMA interrupt flags */ +typedef enum _dma_int +{ + kDMA_IntA, /*!< DMA interrupt flag A */ + kDMA_IntB, /*!< DMA interrupt flag B */ + kDMA_IntError, /*!< DMA interrupt flag error */ +} dma_irq_t; + +/*! @brief DMA trigger type*/ +typedef enum _dma_trigger_type +{ + kDMA_NoTrigger = 0, /*!< Trigger is disabled */ + kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ + kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | + DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ + kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ + kDMA_RisingEdgeTrigger = + DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ +} dma_trigger_type_t; + +/*! @brief DMA trigger burst */ +typedef enum _dma_trigger_burst +{ + kDMA_SingleTransfer = 0, /*!< Single transfer */ + kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ + kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ + kDMA_EdgeBurstTransfer2 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ + kDMA_EdgeBurstTransfer4 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ + kDMA_EdgeBurstTransfer8 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ + kDMA_EdgeBurstTransfer16 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ + kDMA_EdgeBurstTransfer32 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ + kDMA_EdgeBurstTransfer64 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ + kDMA_EdgeBurstTransfer128 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ + kDMA_EdgeBurstTransfer256 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ + kDMA_EdgeBurstTransfer512 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ + kDMA_EdgeBurstTransfer1024 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ +} dma_trigger_burst_t; + +/*! @brief DMA burst wrapping */ +typedef enum _dma_burst_wrap +{ + kDMA_NoWrap = 0, /*!< Wrapping is disabled */ + kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ + kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ + kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | + DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ +} dma_burst_wrap_t; + +/*! @brief DMA transfer type */ +typedef enum _dma_transfer_type +{ + kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ + kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ + kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ + kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ +} dma_transfer_type_t; + +/*! @brief DMA channel trigger */ +typedef struct _dma_channel_trigger +{ + dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ + dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ + dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ +} dma_channel_trigger_t; + +/*! @brief DMA transfer status */ +enum _dma_transfer_status +{ + kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_transfer_config +{ + uint8_t *srcAddr; /*!< Source data address */ + uint8_t *dstAddr; /*!< Destination data address */ + uint8_t *nextDesc; /*!< Chain custom descriptor */ + dma_xfercfg_t xfercfg; /*!< Transfer options */ + bool isPeriph; /*!< DMA transfer is driven by peripheral */ +} dma_transfer_config_t; + +/*! @brief Callback for DMA */ +struct _dma_handle; + +/*! @brief Define Callback function for DMA. */ +typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); + +/*! @brief DMA transfer handle structure */ +typedef struct _dma_handle +{ + dma_callback callback; /*!< Callback function. Invoked when transfer + of descriptor with interrupt flag finishes */ + void *userData; /*!< Callback function parameter */ + DMA_Type *base; /*!< DMA peripheral base address */ + uint8_t channel; /*!< DMA channel number */ +} dma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMA initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * @param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base); + +/*! + * @brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * @param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base); + +/* @} */ +/*! + * @name DMA Channel Operation + * @{ + */ + +/*! +* @brief Return whether DMA channel is processing transfer +* +* @param base DMA peripheral base address. +* @param channel DMA channel number. +* @return True for active state, false otherwise. +*/ +static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false; +} + +/*! + * @brief Enables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Disables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Enable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Disable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Set PERIPHREQEN of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Get PERIPHREQEN value of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for enabled PeriphRq, false for disabled. + */ +static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Set trigger settings of DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param trigger trigger configuration. + */ +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); + +/*! + * @brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); + +/*! + * @brief Set priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param priority Channel priority value. + */ +static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + base->CHANNEL[channel].CFG = + (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); +} + +/*! + * @brief Get priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return Channel priority value. + */ +static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> + DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); +} + +/*! + * @brief Create application specific DMA descriptor + * to be used in a chain in transfer + * + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcAddr Address of last item to transmit + * @param dstAddr Address of last item to receive. + * @param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); + +/* @} */ + +/*! + * @name DMA Transactional Operation + * @{ + */ + +/*! + * @brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * @param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle); + +/*! + * @brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * @param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * @param handle DMA handle pointer. + * @param callback DMA callback function pointer. + * @param userData Parameter for callback function. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); + +/*! + * @brief Prepares the DMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type dma_transfer_t. + * @param srcAddr DMA transfer source address. + * @param dstAddr DMA transfer destination address. + * @param byteWidth DMA transfer destination address width(bytes). + * @param transferBytes DMA transfer bytes to be transferred. + * @param type DMA transfer type. + * @param nextDesc Chain custom descriptor to transfer. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc); + +/*! + * @brief Submits the DMA transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @retval kStatus_DMA_Success It means submit transfer request succeed. + * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); + +/*! + * @brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * @param handle DMA handle pointer. + */ +void DMA_StartTransfer(dma_handle_t *handle); + +/*! + * @brief DMA IRQ handler for descriptor transfer complete. + * + * This function clears the channel major interrupt flag and call + * the callback function if it is not NULL. + */ +void DMA_HandleIRQ(void); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_DMA_H_*/ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.c new file mode 100644 index 00000000000..d9cb1a4edca --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.c @@ -0,0 +1,255 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dmic.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dmic" +#endif + + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of DMIC peripheral base address. */ +static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS; + +/* Array of DMIC clock name. */ +static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS; + +/* Array of DMIC IRQ number. */ +static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS; + +/*! @brief Callback function array for DMIC(s). */ +static dmic_callback_t s_dmicCallback[FSL_FEATURE_SOC_DMIC_COUNT]; + +/* Array of HWVAD IRQ number. */ +static const IRQn_Type s_dmicHwvadIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_HWVAD_IRQS; + +/*! @brief Callback function array for HWVAD(s). */ +static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT]; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the DMIC instance from peripheral base address. + * + * @param base DMIC peripheral base address. + * @return DMIC instance. + */ +uint32_t DMIC_GetInstance(DMIC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmicBases); instance++) + { + if (s_dmicBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dmicBases)); + + return instance; +} + +void DMIC_Init(DMIC_Type *base) +{ + assert(base); + + /* Enable the clock to the register interface */ + CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]); + + /* Reset the peripheral */ + RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn); + + /* Disable DMA request*/ + base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); + base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); + + /* Disable DMIC interrupt. */ + base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1); + base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1); +} + +void DMIC_DeInit(DMIC_Type *base) +{ + assert(base); + /* Disable the clock to the register interface */ + CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]); +} + +void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config) +{ + base->IOCFG = config; +} + +void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode) +{ + if (mode == kDMIC_OperationModeInterrupt) + { + /* Enable DMIC interrupt. */ + base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1); + base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1); + } + if (mode == kDMIC_OperationModeDma) + { + /* enable DMA request*/ + base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); + base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1); + } +} + +void DMIC_ConfigChannel(DMIC_Type *base, + dmic_channel_t channel, + stereo_side_t side, + dmic_channel_config_t *channel_config) +{ + base->CHANNEL[channel].DIVHFCLK = channel_config->divhfclk; + base->CHANNEL[channel].OSR = channel_config->osr; + base->CHANNEL[channel].GAINSHIFT = channel_config->gainshft; + base->CHANNEL[channel].PREAC2FSCOEF = channel_config->preac2coef; + base->CHANNEL[channel].PREAC4FSCOEF = channel_config->preac4coef; + base->CHANNEL[channel].PHY_CTRL = + DMIC_CHANNEL_PHY_CTRL_PHY_FALL(side) | DMIC_CHANNEL_PHY_CTRL_PHY_HALF(channel_config->sample_rate); + base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(channel_config->dc_cut_level) | + DMIC_CHANNEL_DC_CTRL_DCGAIN(channel_config->post_dc_gain_reduce) | + DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit); +} + +void DMIC_CfgChannelDc(DMIC_Type *base, + dmic_channel_t channel, + dc_removal_t dc_cut_level, + uint32_t post_dc_gain_reduce, + bool saturate16bit) +{ + base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(dc_cut_level) | + DMIC_CHANNEL_DC_CTRL_DCGAIN(post_dc_gain_reduce) | + DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit); +} + +void DMIC_Use2fs(DMIC_Type *base, bool use2fs) +{ + base->USE2FS = (use2fs) ? 0x1 : 0x0; +} + +void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask) +{ + base->CHANEN = channelmask; +} + +void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn) +{ + base->CHANNEL[channel].FIFO_CTRL |= + (base->CHANNEL[channel].FIFO_CTRL & (DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK | DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)) | + DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(trig_level) | DMIC_CHANNEL_FIFO_CTRL_ENABLE(enable) | + DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn); +} + +void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb) +{ + uint32_t instance; + + instance = DMIC_GetInstance(base); + NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); + /* Save callback pointer */ + s_dmicCallback[instance] = cb; + EnableIRQ(s_dmicIRQ[instance]); +} + +void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb) +{ + uint32_t instance; + + instance = DMIC_GetInstance(base); + DisableIRQ(s_dmicIRQ[instance]); + s_dmicCallback[instance] = NULL; + NVIC_ClearPendingIRQ(s_dmicIRQ[instance]); +} + +void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) +{ + uint32_t instance; + + instance = DMIC_GetInstance(base); + NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]); + /* Save callback pointer */ + s_dmicHwvadCallback[instance] = vadcb; + EnableIRQ(s_dmicHwvadIRQ[instance]); +} + +void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb) +{ + uint32_t instance; + + instance = DMIC_GetInstance(base); + DisableIRQ(s_dmicHwvadIRQ[instance]); + s_dmicHwvadCallback[instance] = NULL; + NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]); +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(DMIC0) +/*DMIC0 IRQ handler */ +void DMIC0_DriverIRQHandler(void) +{ + if (s_dmicCallback[0] != NULL) + { + s_dmicCallback[0](); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +/*DMIC0 HWVAD IRQ handler */ +void HWVAD0_DriverIRQHandler(void) +{ + if (s_dmicHwvadCallback[0] != NULL) + { + s_dmicHwvadCallback[0](); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.h new file mode 100644 index 00000000000..575d17cfe6a --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic.h @@ -0,0 +1,457 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMIC_H_ +#define _FSL_DMIC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dmic_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name DMIC version + * @{ + */ + +/*! @brief DMIC driver version 2.0.0. */ +#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief DMIC different operation modes. */ +typedef enum _operation_mode +{ + kDMIC_OperationModePoll = 0U, /*!< Polling mode */ + kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */ + kDMIC_OperationModeDma = 2U, /*!< DMA mode */ +} operation_mode_t; + +/*! @brief DMIC left/right values. */ +typedef enum _stereo_side +{ + kDMIC_Left = 0U, /*!< Left Stereo channel */ + kDMIC_Right = 1U, /*!< Right Stereo channel */ +} stereo_side_t; + +/*! @brief DMIC Clock pre-divider values. */ +typedef enum +{ + kDMIC_PdmDiv1 = 0U, /*!< DMIC pre-divider set in divide by 1 */ + kDMIC_PdmDiv2 = 1U, /*!< DMIC pre-divider set in divide by 2 */ + kDMIC_PdmDiv3 = 2U, /*!< DMIC pre-divider set in divide by 3 */ + kDMIC_PdmDiv4 = 3U, /*!< DMIC pre-divider set in divide by 4 */ + kDMIC_PdmDiv6 = 4U, /*!< DMIC pre-divider set in divide by 6 */ + kDMIC_PdmDiv8 = 5U, /*!< DMIC pre-divider set in divide by 8 */ + kDMIC_PdmDiv12 = 6U, /*!< DMIC pre-divider set in divide by 12 */ + kDMIC_PdmDiv16 = 7U, /*!< DMIC pre-divider set in divide by 16*/ + kDMIC_PdmDiv24 = 8U, /*!< DMIC pre-divider set in divide by 24*/ + kDMIC_PdmDiv32 = 9U, /*!< DMIC pre-divider set in divide by 32 */ + kDMIC_PdmDiv48 = 10U, /*!< DMIC pre-divider set in divide by 48 */ + kDMIC_PdmDiv64 = 11U, /*!< DMIC pre-divider set in divide by 64*/ + kDMIC_PdmDiv96 = 12U, /*!< DMIC pre-divider set in divide by 96*/ + kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */ +} pdm_div_t; + +/*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */ +typedef enum _compensation +{ + kDMIC_CompValueZero = 0U, /*!< Compensation 0 */ + kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */ + kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */ + kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */ +} compensation_t; + +/*! @brief DMIC DC filter control values. */ +typedef enum _dc_removal +{ + kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */ + kDMIC_DcCut155 = 1U, /*!< Cut off Frequency is 155 Hz */ + kDMIC_DcCut78 = 2U, /*!< Cut off Frequency is 78 Hz */ + kDMIC_DcCut39 = 3U, /*!< Cut off Frequency is 39 Hz */ +} dc_removal_t; + +/*! @brief DMIC IO configiration. */ +typedef enum _dmic_io +{ + kDMIC_PdmDual = 0U, /*!< Two separate pairs of PDM wires */ + kDMIC_PdmStereo = 4U, /*!< Stereo Mic */ + kDMIC_PdmBypass = 3U, /*!< Clk Bypass clocks both channels */ + kDMIC_PdmBypassClk0 = 1U, /*!< Clk Bypass clocks only channel0 */ + kDMIC_PdmBypassClk1 = 2U, /*!< Clk Bypas clocks only channel1 */ +} dmic_io_t; + +/*! @brief DMIC Channel number. */ +typedef enum _dmic_channel +{ + kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */ + kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */ +} dmic_channel_t; + +/*! @brief DMIC and decimator sample rates. */ +typedef enum _dmic_phy_sample_rate +{ + kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */ + kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */ +} dmic_phy_sample_rate_t; + +/*! @brief DMIC transfer status.*/ +enum _dmic_status +{ + kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0), /*!< DMIC is busy */ + kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1), /*!< DMIC is idle */ + kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2), /*!< DMIC over run Error */ + kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */ +}; + +/*! @brief DMIC Channel configuration structure. */ +typedef struct _dmic_channel_config +{ + pdm_div_t divhfclk; /*!< DMIC Clock pre-divider values */ + uint32_t osr; /*!< oversampling rate(CIC decimation rate) for PCM */ + int32_t gainshft; /*!< 4FS PCM data gain control */ + compensation_t preac2coef; /*!< Pre-emphasis Filter coefficient value for 2FS */ + compensation_t preac4coef; /*!< Pre-emphasis Filter coefficient value for 4FS */ + dc_removal_t dc_cut_level; /*!< DMIC DC filter control values. */ + uint32_t post_dc_gain_reduce; /*!< Fine gain adjustment in the form of a number of bits to downshift */ + dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */ + bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate. + 1 means if the result overflows, it saturates at 0xFFFF for positive overflow and + 0x8000 for negative overflow.*/ +} dmic_channel_config_t; + +/*! @brief DMIC Callback function. */ +typedef void (*dmic_callback_t)(void); + +/*! @brief HWVAD Callback function. */ +typedef void (*dmic_hwvad_callback_t)(void); + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Get the DMIC instance from peripheral base address. + * + * @param base DMIC peripheral base address. + * @return DMIC instance. + */ +uint32_t DMIC_GetInstance(DMIC_Type *base); + +/*! + * @brief Turns DMIC Clock on + * @param base : DMIC base + * @return Nothing + */ +void DMIC_Init(DMIC_Type *base); + +/*! + * @brief Turns DMIC Clock off + * @param base : DMIC base + * @return Nothing + */ +void DMIC_DeInit(DMIC_Type *base); + +/*! + * @brief Configure DMIC io + * @param base : The base address of DMIC interface + * @param config : DMIC io configuration + * @return Nothing + */ +void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config); + +/*! + * @brief Set DMIC operating mode + * @param base : The base address of DMIC interface + * @param mode : DMIC mode + * @return Nothing + */ +void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode); + +/*! + * @brief Configure DMIC channel + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @param side : stereo_side_t, choice of left or right + * @param channel_config : Channel configuration + * @return Nothing + */ +void DMIC_ConfigChannel(DMIC_Type *base, + dmic_channel_t channel, + stereo_side_t side, + dmic_channel_config_t *channel_config); + +/*! + * @brief Configure DMIC channel + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @param dc_cut_level : dc_removal_t, Cut off Frequency + * @param post_dc_gain_reduce : Fine gain adjustment in the form of a number of bits to downshift. + * @param saturate16bit : If selects 16-bit saturation. + */ +void DMIC_CfgChannelDc(DMIC_Type *base, + dmic_channel_t channel, + dc_removal_t dc_cut_level, + uint32_t post_dc_gain_reduce, + bool saturate16bit); + +/*! + * @brief Configure Clock scaling + * @param base : The base address of DMIC interface + * @param use2fs : clock scaling + * @return Nothing + */ +void DMIC_Use2fs(DMIC_Type *base, bool use2fs); + +/*! + * @brief Enable a particualr channel + * @param base : The base address of DMIC interface + * @param channelmask : Channel selection + * @return Nothing + */ +void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask); + +/*! + * @brief Configure fifo settings for DMIC channel + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @param trig_level : FIFO trigger level + * @param enable : FIFO level + * @param resetn : FIFO reset + * @return Nothing + */ +void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn); + +/*! + * @brief Get FIFO status + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @return FIFO status + */ +static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel) +{ + return base->CHANNEL[channel].FIFO_STATUS; +} + +/*! + * @brief Clear FIFO status + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @param mask : Bits to be cleared + * @return FIFO status + */ +static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask) +{ + base->CHANNEL[channel].FIFO_STATUS = mask; +} + +/*! + * @brief Get FIFO data + * @param base : The base address of DMIC interface + * @param channel : DMIC channel + * @return FIFO data + */ +static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel) +{ + return base->CHANNEL[channel].FIFO_DATA; +} + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected DMIC peripheral. + * The callback function is not enabled until this function is called. + * + * @param base Base address of the DMIC peripheral. + * @param cb callback Pointer to store callback function. + * @retval None. + */ +void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected DMIC peripheral. + * + * @param base Base address of the DMIC peripheral. + * @param cb callback Pointer to store callback function.. + * @retval None. + */ +void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb); + +/** + * @} + */ + +/*! + * @name hwvad + * @{ + */ + +/*! + * @brief Sets the gain value for the noise estimator. + * + * @param base DMIC base pointer + * @param value gain value for the noise estimator. + * @retval None. + */ +static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value) +{ + assert(NULL != base); + base->HWVADTHGN = value & 0xFu; +} + +/*! + * @brief Sets the gain value for the signal estimator. + * + * @param base DMIC base pointer + * @param value gain value for the signal estimator. + * @retval None. + */ +static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value) +{ + assert(NULL != base); + base->HWVADTHGS = value & 0xFu; +} + +/*! + * @brief Sets the hwvad filter cutoff frequency parameter. + * + * @param base DMIC base pointer + * @param value cut off frequency value. + * @retval None. + */ +static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value) +{ + assert(NULL != base); + base->HWVADHPFS = value & 0x3u; +} + +/*! + * @brief Sets the input gain of hwvad. + * + * @param base DMIC base pointer + * @param value input gain value for hwvad. + * @retval None. + */ +static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value) +{ + assert(NULL != base); + base->HWVADGAIN = value & 0xFu; +} + +/*! + * @brief Clears hwvad internal interrupt flag. + * + * @param base DMIC base pointer + * @param st10 bit value. + * @retval None. + */ +static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10) +{ + assert(NULL != base); + base->HWVADST10 = (st10) ? 0x1 : 0x0; +} + +/*! + * @brief Resets hwvad filters. + * + * @param base DMIC base pointer + * @param rstt Reset bit value. + * @retval None. + */ +static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt) +{ + assert(NULL != base); + base->HWVADRSTT = (rstt) ? 0x1 : 0x0; +} + +/*! + * @brief Gets the value from output of the filter z7. + * + * @param base DMIC base pointer + * @retval output of filter z7. + */ +static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base) +{ + assert(NULL != base); + return (base->HWVADLOWZ & 0xFFFFu); +} + +/*! + * @brief Enable hwvad callback. + + * This function enables the hwvad interrupt for the selected DMIC peripheral. + * The callback function is not enabled until this function is called. + * + * @param base Base address of the DMIC peripheral. + * @param vadcb callback Pointer to store callback function. + * @retval None. + */ +void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb); + +/*! + * @brief Disable callback. + + * This function disables the hwvad interrupt for the selected DMIC peripheral. + * + * @param base Base address of the DMIC peripheral. + * @param vadcb callback Pointer to store callback function.. + * @retval None. + */ +void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb); + +/*! @} */ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* __FSL_DMIC_H */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.c new file mode 100644 index 00000000000..d1505dd9423 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.c @@ -0,0 +1,202 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dmic_dma.h" +#include "fsl_dmic.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dmic_dma" +#endif + +#define DMIC_HANDLE_ARRAY_SIZE 1 + +/*handle->state = kDMIC_Idle; + + if (dmicPrivateHandle->handle->callback) + { + dmicPrivateHandle->handle->callback(dmicPrivateHandle->base, dmicPrivateHandle->handle, kStatus_DMIC_Idle, + dmicPrivateHandle->handle->userData); + } +} + +status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, + dmic_dma_handle_t *handle, + dmic_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *rxDmaHandle) +{ + int32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + /* check DMIC instance by 'base'*/ + instance = DMIC_GetInstance(base); + assert(!(instance < 0)); + if (instance < 0) + { + return kStatus_InvalidArgument; + } + + memset(handle, 0, sizeof(*handle)); + /* assign 'base' and 'handle' */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->rxDmaHandle = rxDmaHandle; + + /* Set DMIC state to idle */ + handle->state = kDMIC_Idle; + /* Configure RX. */ + if (rxDmaHandle) + { + DMA_SetCallback(rxDmaHandle, DMIC_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); + } + + return kStatus_Success; +} + +status_t DMIC_TransferReceiveDMA(DMIC_Type *base, + dmic_dma_handle_t *handle, + dmic_transfer_t *xfer, + uint32_t dmic_channel) +{ + assert(handle); + assert(handle->rxDmaHandle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + dma_transfer_config_t xferConfig; + status_t status; + uint32_t srcAddr = (uint32_t)(&base->CHANNEL[dmic_channel].FIFO_DATA); + + /* Check if the device is busy. If previous RX not finished.*/ + if (handle->state == kDMIC_Busy) + { + status = kStatus_DMIC_Busy; + } + else + { + handle->state = kDMIC_Busy; + handle->transferSize = xfer->dataSize; + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, (void *)srcAddr, xfer->data, sizeof(uint16_t), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); + + /* Submit transfer. */ + DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + + DMA_StartTransfer(handle->rxDmaHandle); + + status = kStatus_Success; + } + return status; +} + +void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + handle->state = kDMIC_Idle; +} + +status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(handle->rxDmaHandle); + assert(count); + + if (kDMIC_Idle == handle->state) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.h new file mode 100644 index 00000000000..5ba15107fc4 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_dmic_dma.h @@ -0,0 +1,165 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_DMIC_DMA_H_ +#define _FSL_DMIC_DMA_H_ + +#include "fsl_common.h" +#include "fsl_dma.h" + +/*! + * @addtogroup dmic_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name DMIC DMA version + * @{ + */ + +/*! @brief DMIC DMA driver version 2.0.0. */ +#define FSL_DMIC_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief DMIC transfer structure. */ +typedef struct _dmic_transfer +{ + uint16_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} dmic_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _dmic_dma_handle dmic_dma_handle_t; + +/*! @brief DMIC transfer callback function. */ +typedef void (*dmic_dma_transfer_callback_t)(DMIC_Type *base, + dmic_dma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief DMIC DMA handle +*/ +struct _dmic_dma_handle +{ + DMIC_Type *base; /*!< DMIC peripheral base address. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + dmic_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< DMIC callback function parameter.*/ + size_t transferSize; /*!< Size of the data to receive. */ + volatile uint8_t state; /*!< Internal state of DMIC DMA transfer */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name DMA transactional + * @{ + */ + +/*! + * @brief Initializes the DMIC handle which is used in transactional functions. + * @param base DMIC peripheral base address. + * @param handle Pointer to dmic_dma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base, + dmic_dma_handle_t *handle, + dmic_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer DMIC DMA transfer structure. See #dmic_transfer_t. + * @param dmic_channel DMIC channel + * @retval kStatus_Success + */ +status_t DMIC_TransferReceiveDMA(DMIC_Type *base, + dmic_dma_handle_t *handle, + dmic_transfer_t *xfer, + uint32_t dmic_channel); + +/*! + * @brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * @param base DMIC peripheral base address + * @param handle Pointer to dmic_dma_handle_t structure + */ +void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base DMIC peripheral base address. + * @param handle DMIC handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter count; + */ +status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_DMIC_DMA_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.c new file mode 100644 index 00000000000..62fbdd85ab4 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.c @@ -0,0 +1,137 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flashiap.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flashiap" +#endif + + +#define HZ_TO_KHZ_DIV 1000 + +/******************************************************************************* + * Code + ******************************************************************************/ + +static status_t translate_iap_status(uint32_t status) +{ + /* Translate IAP return code to sdk status code */ + if (status == kStatus_Success) + { + return status; + } + else + { + return MAKE_STATUS(kStatusGroup_FLASHIAP, status); + } +} + +status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector) +{ + uint32_t command[5], result[4]; + + command[0] = kIapCmd_FLASHIAP_PrepareSectorforWrite; + command[1] = startSector; + command[2] = endSector; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock) +{ + uint32_t command[5], result[4]; + + command[0] = kIapCmd_FLASHIAP_CopyRamToFlash; + command[1] = dstAddr; + command[2] = (uint32_t)srcAddr; + command[3] = numOfBytes; + command[4] = systemCoreClock / HZ_TO_KHZ_DIV; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock) +{ + uint32_t command[5], result[4]; + + command[0] = kIapCmd_FLASHIAP_EraseSector; + command[1] = startSector; + command[2] = endSector; + command[3] = systemCoreClock / HZ_TO_KHZ_DIV; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock) +{ + uint32_t command[5], result[4]; + + command[0] = kIapCmd_FLASHIAP_ErasePage; + command[1] = startPage; + command[2] = endPage; + command[3] = systemCoreClock / HZ_TO_KHZ_DIV; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector) +{ + uint32_t command[5], result[4]; + + command[0] = kIapCmd_FLASHIAP_BlankCheckSector; + command[1] = startSector; + command[2] = endSector; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} + +status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes) +{ + uint32_t command[5], result[4]; + + command[0] = kIapCmd_FLASHIAP_Compare; + command[1] = dstAddr; + command[2] = (uint32_t)srcAddr; + command[3] = numOfBytes; + iap_entry(command, result); + + return translate_iap_status(result[0]); +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.h new file mode 100644 index 00000000000..113db1f11f5 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flashiap.h @@ -0,0 +1,268 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLASHIAP_H_ +#define _FSL_FLASHIAP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flashiap_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_FLASHIAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + /*@}*/ + +/*! + * @brief Flashiap status codes. + */ +enum _flashiap_status +{ + kStatus_FLASHIAP_Success = kStatus_Success, /*!< Api is executed successfully */ + kStatus_FLASHIAP_InvalidCommand = MAKE_STATUS(kStatusGroup_FLASHIAP, 1U), /*!< Invalid command */ + kStatus_FLASHIAP_SrcAddrError = + MAKE_STATUS(kStatusGroup_FLASHIAP, 2U), /*!< Source address is not on word boundary */ + kStatus_FLASHIAP_DstAddrError = + MAKE_STATUS(kStatusGroup_FLASHIAP, 3U), /*!< Destination address is not on a correct boundary */ + kStatus_FLASHIAP_SrcAddrNotMapped = + MAKE_STATUS(kStatusGroup_FLASHIAP, 4U), /*!< Source address is not mapped in the memory map */ + kStatus_FLASHIAP_DstAddrNotMapped = + MAKE_STATUS(kStatusGroup_FLASHIAP, 5U), /*!< Destination address is not mapped in the memory map */ + kStatus_FLASHIAP_CountError = + MAKE_STATUS(kStatusGroup_FLASHIAP, 6U), /*!< Byte count is not multiple of 4 or is not a permitted value */ + kStatus_FLASHIAP_InvalidSector = + MAKE_STATUS(kStatusGroup_FLASHIAP, + 7), /*!< Sector number is invalid or end sector number is greater than start sector number */ + kStatus_FLASHIAP_SectorNotblank = MAKE_STATUS(kStatusGroup_FLASHIAP, 8U), /*!< One or more sectors are not blank */ + kStatus_FLASHIAP_NotPrepared = + MAKE_STATUS(kStatusGroup_FLASHIAP, 9U), /*!< Command to prepare sector for write operation was not executed */ + kStatus_FLASHIAP_CompareError = + MAKE_STATUS(kStatusGroup_FLASHIAP, 10U), /*!< Destination and source memory contents do not match */ + kStatus_FLASHIAP_Busy = + MAKE_STATUS(kStatusGroup_FLASHIAP, 11U), /*!< Flash programming hardware interface is busy */ + kStatus_FLASHIAP_ParamError = + MAKE_STATUS(kStatusGroup_FLASHIAP, 12U), /*!< Insufficient number of parameters or invalid parameter */ + kStatus_FLASHIAP_AddrError = MAKE_STATUS(kStatusGroup_FLASHIAP, 13U), /*!< Address is not on word boundary */ + kStatus_FLASHIAP_AddrNotMapped = + MAKE_STATUS(kStatusGroup_FLASHIAP, 14U), /*!< Address is not mapped in the memory map */ + kStatus_FLASHIAP_NoPower = MAKE_STATUS(kStatusGroup_FLASHIAP, 24U), /*!< Flash memory block is powered down */ + kStatus_FLASHIAP_NoClock = + MAKE_STATUS(kStatusGroup_FLASHIAP, 27U), /*!< Flash memory block or controller is not clocked */ +}; + +/*! + * @brief Flashiap command codes. + */ +enum _flashiap_commands +{ + kIapCmd_FLASHIAP_PrepareSectorforWrite = 50U, /*!< Prepare Sector for write */ + kIapCmd_FLASHIAP_CopyRamToFlash = 51U, /*!< Copy RAM to flash */ + kIapCmd_FLASHIAP_EraseSector = 52U, /*!< Erase Sector */ + kIapCmd_FLASHIAP_BlankCheckSector = 53U, /*!< Blank check sector */ + kIapCmd_FLASHIAP_ReadPartId = 54U, /*!< Read part id */ + kIapCmd_FLASHIAP_Read_BootromVersion = 55U, /*!< Read bootrom version */ + kIapCmd_FLASHIAP_Compare = 56U, /*!< Compare */ + kIapCmd_FLASHIAP_ReinvokeISP = 57U, /*!< Reinvoke ISP */ + kIapCmd_FLASHIAP_ReadUid = 58U, /*!< Read Uid isp */ + kIapCmd_FLASHIAP_ErasePage = 59U, /*!< Erase Page */ + kIapCmd_FLASHIAP_ReadMisr = 70U, /*!< Read Misr */ + kIapCmd_FLASHIAP_ReinvokeI2cSpiISP = 71U /*!< Reinvoke I2C/SPI isp */ +}; + +/*! @brief IAP_ENTRY API function type */ +typedef void (*IAP_ENTRY_T)(uint32_t cmd[5], uint32_t stat[4]); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief IAP_ENTRY API function type + * + * Wrapper for rom iap call + * + * @param cmd_param IAP command and relevant parameter array. + * @param status_result IAP status result array. + * + * @retval None. Status/Result is returned via status_result array. + */ +static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result) +{ + ((IAP_ENTRY_T)FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(cmd_param, status_result); +} + +/*! + * @brief Prepare sector for write operation + + * This function prepares sector(s) for write/erase operation. This function must be + * called before calling the FLASHIAP_CopyRamToFlash() or FLASHIAP_EraseSector() or + * FLASHIAP_ErasePage() function. The end sector must be greater than or equal to + * start sector number. + * + * @param startSector Start sector number. + * @param endSector End sector number. + * + * @retval #kStatus_FLASHIAP_Success Api was executed successfully. + * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number + * is greater than start sector number. + * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. + */ +status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector); + +/*! + * @brief Copy RAM to flash. + + * This function programs the flash memory. Corresponding sectors must be prepared + * via FLASHIAP_PrepareSectorForWrite before calling calling this function. The addresses + * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096. + * + * @param dstAddr Destination flash address where data bytes are to be written. + * @param srcAddr Source ram address from where data bytes are to be read. + * @param numOfBytes Number of bytes to be written. + * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * @retval #kStatus_FLASHIAP_Success Api was executed successfully. + * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_FLASHIAP_SrcAddrError Source address is not on word boundary. + * @retval #kStatus_FLASHIAP_DstAddrError Destination address is not on a correct boundary. + * @retval #kStatus_FLASHIAP_SrcAddrNotMapped Source address is not mapped in the memory map. + * @retval #kStatus_FLASHIAP_DstAddrNotMapped Destination address is not mapped in the memory map. + * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value. + * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. + * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. + */ +status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock); + +/*! + * @brief Erase sector + + * This function erases sector(s). The end sector must be greater than or equal to + * start sector number. FLASHIAP_PrepareSectorForWrite must be called before + * calling this function. + * + * @param startSector Start sector number. + * @param endSector End sector number. + * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * @retval #kStatus_FLASHIAP_Success Api was executed successfully. + * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number + * is greater than start sector number. + * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. + * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. + */ +status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock); + +/*! + + * This function erases page(s). The end page must be greater than or equal to + * start page number. Corresponding sectors must be prepared via FLASHIAP_PrepareSectorForWrite + * before calling calling this function. + * + * @param startPage Start page number + * @param endPage End page number + * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the + * rom IAP function. + * + * @retval #kStatus_FLASHIAP_Success Api was executed successfully. + * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_FLASHIAP_InvalidSector Page number is invalid or end page number + * is greater than start page number + * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed. + * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy. + */ +status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock); + +/*! + * @brief Blank check sector(s) + * + * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to + * start sector number. It can be used to verify the sector eraseure after FLASHIAP_EraseSector call. + * + * @param startSector : Start sector number. Must be greater than or equal to start sector number + * @param endSector : End sector number + * @retval #kStatus_FLASHIAP_Success One or more sectors are in erased state. + * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_FLASHIAP_SectorNotblank One or more sectors are not blank. + */ +status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector); + +/*! + * @brief Compare memory contents of flash with ram. + + * This function compares the contents of flash and ram. It can be used to verify the flash + * memory contents after FLASHIAP_CopyRamToFlash call. + * + * @param dstAddr Destination flash address. + * @param srcAddr Source ram address. + * @param numOfBytes Number of bytes to be compared. + * + * @retval #kStatus_FLASHIAP_Success Contents of flash and ram match. + * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down. + * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked. + * @retval #kStatus_FLASHIAP_AddrError Address is not on word boundary. + * @retval #kStatus_FLASHIAP_AddrNotMapped Address is not mapped in the memory map. + * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value. + * @retval #kStatus_FLASHIAP_CompareError Destination and source memory contents do not match. + */ +status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_FLASHIAP_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.c new file mode 100644 index 00000000000..f13a2f836b4 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.c @@ -0,0 +1,313 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief Set the FLEXCOMM mode . */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; + +/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; + +/*! @brief Array to map FLEXCOMM instance number to base address. */ +static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) +{ + if (periph == FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if (periph <= FLEXCOMM_PERIPH_I2S_TX) + { + return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false; + } + else if (periph == FLEXCOMM_PERIPH_I2S_RX) + { + return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false; + } + else + { + return false; + } +} + +/* Get the index corresponding to the FLEXCOMM */ +uint32_t FLEXCOMM_GetInstance(void *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) + { + if ((uint32_t)base == s_flexcommBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +/* Changes FLEXCOMM mode */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) +{ + /* Check whether peripheral type is present */ + if (!FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock) + { + base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) +{ + int idx = FLEXCOMM_GetInstance(base); + + if (idx < 0) + { + return kStatus_InvalidArgument; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_flexcommClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Set the FLEXCOMM to given peripheral */ + return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); +} + +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(base); + + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_flexcommIrqHandler[instance] = NULL; + s_flexcommHandle[instance] = handle; + s_flexcommIrqHandler[instance] = handler; +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(FLEXCOMM0) +void FLEXCOMM0_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[0]); + s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM1) +void FLEXCOMM1_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[1]); + s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM2) +void FLEXCOMM2_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[2]); + s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM3) +void FLEXCOMM3_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[3]); + s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM4) +void FLEXCOMM4_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[4]); + s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#endif + +#if defined(FLEXCOMM5) +void FLEXCOMM5_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[5]); + s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM6) +void FLEXCOMM6_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[6]); + s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM7) +void FLEXCOMM7_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[7]); + s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM8) +void FLEXCOMM8_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[8]); + s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM9) +void FLEXCOMM9_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[9]); + s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.h new file mode 100644 index 00000000000..74318e351cb --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_flexcomm.h @@ -0,0 +1,79 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXCOMM_H_ +#define _FSL_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version 2.0.0. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief FLEXCOMM peripheral modes. */ +typedef enum +{ + FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ + FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ + FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ + FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ + FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ +} FLEXCOMM_PERIPH_T; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); + +/*! @brief Array with IRQ number for each FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/*! @brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base); + +/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); + +/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle); + +/*@}*/ + +#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.c new file mode 100644 index 00000000000..5f087c7bc80 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.c @@ -0,0 +1,71 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_fmeas.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.fmeas" +#endif + + +/*! @brief Target clock counter value. + * According to user manual, 2 has to be subtracted from captured value (CAPVAL). */ +#define TARGET_CLOCK_COUNT(base) \ + ((uint32_t)( \ + ((((SYSCON_Type *)base)->FREQMECTRL & SYSCON_FREQMECTRL_CAPVAL_MASK) >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) - 2)) + +/*! @brief Reference clock counter value. */ +#define REFERENCE_CLOCK_COUNT ((uint32_t)((SYSCON_FREQMECTRL_CAPVAL_MASK >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) + 1)) + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate) +{ + uint32_t targetClockCount = TARGET_CLOCK_COUNT(base); + uint64_t clkrate = 0; + + if (targetClockCount > 0) + { + clkrate = (((uint64_t)targetClockCount) * (uint64_t)refClockRate) / REFERENCE_CLOCK_COUNT; + } + + return (uint32_t)clkrate; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.h new file mode 100644 index 00000000000..15921375f62 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_fmeas.h @@ -0,0 +1,114 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FMEAS_H_ +#define _FSL_FMEAS_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup fmeas + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines LPC Frequency Measure driver version 2.0.0. + * + * Change log: + * - Version 2.0.0 + * - initial version + */ +#define FSL_FMEAS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name FMEAS Functional Operation + * @{ + */ + +/*! + * @brief Starts a frequency measurement cycle. + * + * @param base : SYSCON peripheral base address. + */ +static inline void FMEAS_StartMeasure(SYSCON_Type *base) +{ + base->FREQMECTRL = 0; + base->FREQMECTRL = (1UL << 31); +} + +/*! + * @brief Indicates when a frequency measurement cycle is complete. + * + * @param base : SYSCON peripheral base address. + * @return true if a measurement cycle is active, otherwise false. + */ +static inline bool FMEAS_IsMeasureComplete(SYSCON_Type *base) +{ + return (bool)((base->FREQMECTRL & (1UL << 31)) == 0); +} + +/*! + * @brief Returns the computed value for a frequency measurement cycle + * + * @param base : SYSCON peripheral base address. + * @param refClockRate : Reference clock rate used during the frequency measurement cycle. + * + * @return Frequency in Hz. + */ +uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_FMEAS_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.c new file mode 100644 index 00000000000..e772da018b6 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.c @@ -0,0 +1,321 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gint.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gint" +#endif + + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to GINT bases for each instance. */ +static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Clocks for each instance. */ +static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Resets for each instance. */ +static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; + +/* @brief Irq number for each instance */ +static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; + +/*! @brief Callback function array for GINT(s). */ +static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GINT_GetInstance(GINT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) + { + if (s_gintBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gintBases)); + + return instance; +} + +void GINT_Init(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + s_gintCallback[instance] = NULL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_gintClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the peripheral */ + RESET_PeripheralReset(s_gintResets[instance]); +} + +void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); + + /* Save callback pointer */ + s_gintCallback[instance] = callback; +} + +void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + *comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT); + *trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT); + *callback = s_gintCallback[instance]; +} + +void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) +{ + base->PORT_POL[port] = polarityMask; + base->PORT_ENA[port] = enableMask; +} + +void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) +{ + *polarityMask = base->PORT_POL[port]; + *enableMask = base->PORT_ENA[port]; +} + +void GINT_EnableCallback(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + /* If GINT is configured in "AND" mode a spurious interrupt is generated. + Clear status and pending interrupt before enabling the irq in NVIC. */ + GINT_ClrStatus(base); + NVIC_ClearPendingIRQ(s_gintIRQ[instance]); + EnableIRQ(s_gintIRQ[instance]); +} + +void GINT_DisableCallback(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + DisableIRQ(s_gintIRQ[instance]); + GINT_ClrStatus(base); + NVIC_ClearPendingIRQ(s_gintIRQ[instance]); +} + +void GINT_Deinit(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + /* Cleanup */ + GINT_DisableCallback(base); + s_gintCallback[instance] = NULL; + + /* Reset the peripheral */ + RESET_PeripheralReset(s_gintResets[instance]); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the peripheral clock */ + CLOCK_DisableClock(s_gintClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(GINT0) +void GINT0_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[0] != NULL) + { + s_gintCallback[0](); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT1) +void GINT1_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[1] != NULL) + { + s_gintCallback[1](); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT2) +void GINT2_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[2] != NULL) + { + s_gintCallback[2](); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT3) +void GINT3_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[3] != NULL) + { + s_gintCallback[3](); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT4) +void GINT4_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[4] != NULL) + { + s_gintCallback[4](); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT5) +void GINT5_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[5] != NULL) + { + s_gintCallback[5](); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT6) +void GINT6_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[6] != NULL) + { + s_gintCallback[6](); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(GINT7) +void GINT7_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[7] != NULL) + { + s_gintCallback[7](); + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.h new file mode 100644 index 00000000000..f010600bed7 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gint.h @@ -0,0 +1,248 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_GINT_H_ +#define _FSL_GINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/*! @brief GINT combine inputs type */ +typedef enum _gint_comb +{ + kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ + kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ +} gint_comb_t; + +/*! @brief GINT trigger type */ +typedef enum _gint_trig +{ + kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ + kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ +} gint_trig_t; + +/* @brief GINT port type */ +typedef enum _gint_port +{ + kGINT_Port0 = 0U, + kGINT_Port1 = 1U, +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) + kGINT_Port2 = 2U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) + kGINT_Port3 = 3U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) + kGINT_Port4 = 4U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) + kGINT_Port5 = 5U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) + kGINT_Port6 = 6U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) + kGINT_Port7 = 7U, +#endif +} gint_port_t; + +/*! @brief GINT Callback function. */ +typedef void (*gint_cb_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize GINT peripheral. + + * This function initializes the GINT peripheral and enables the clock. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_Init(GINT_Type *base); + +/*! + * @brief Setup GINT peripheral control parameters. + + * This function sets the control parameters of GINT peripheral. + * + * @param base Base address of the GINT peripheral. + * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. + * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. + * @param callback This function is called when configured group interrupt is generated. + * + * @retval None. + */ +void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); + +/*! + * @brief Get GINT peripheral control parameters. + + * This function returns the control parameters of GINT peripheral. + * + * @param base Base address of the GINT peripheral. + * @param comb Pointer to store combine input value. + * @param trig Pointer to store trigger value. + * @param callback Pointer to store callback function. + * + * @retval None. + */ +void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); + +/*! + * @brief Configure GINT peripheral pins. + + * This function enables and controls the polarity of enabled pin(s) of a given port. + * + * @param base Base address of the GINT peripheral. + * @param port Port number. + * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * @param enableMask Each bit position selects if the corresponding pin is enabled or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * @retval None. + */ +void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); + +/*! + * @brief Get GINT peripheral pin configuration. + + * This function returns the pin configuration of a given port. + * + * @param base Base address of the GINT peripheral. + * @param port Port number. + * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding + enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled + or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * @retval None. + */ +void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_EnableCallback(GINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected GINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void GINT_DisableCallback(GINT_Type *base); + +/*! + * @brief Clear GINT status. + + * This function clears the GINT status bit. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +static inline void GINT_ClrStatus(GINT_Type *base) +{ + base->CTRL |= GINT_CTRL_INT_MASK; +} + +/*! + * @brief Get GINT status. + + * This function returns the GINT status. + * + * @param base Base address of the GINT peripheral. + * + * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. + */ +static inline uint32_t GINT_GetStatus(GINT_Type *base) +{ + return (base->CTRL & GINT_CTRL_INT_MASK); +} + +/*! + * @brief Deinitialize GINT peripheral. + + * This function disables the GINT clock. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_Deinit(GINT_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_GINT_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.c new file mode 100644 index 00000000000..12bf49db792 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.c @@ -0,0 +1,87 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* +* Prototypes +************ ******************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) +{ + if (config->pinDirection == kGPIO_DigitalInput) + { + base->DIR[port] &= ~(1U << pin); + } + else + { + /* Set default output value */ + if (config->outputLogic == 0U) + { + base->CLR[port] = (1U << pin); + } + else + { + base->SET[port] = (1U << pin); + } + /* Set pin direction */ + base->DIR[port] |= 1U << pin; + } +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.h new file mode 100644 index 00000000000..9ae8cce2652 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_gpio.h @@ -0,0 +1,355 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _LPC_GPIO_H_ +#define _LPC_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPC GPIO driver version 2.1.1. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/*! @brief LPC GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused. + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + +/*! + * @brief Initializes the GPIO peripheral. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortInit. + */ +static inline void GPIO_Init(GPIO_Type *base, uint32_t port) +{ + GPIO_PortInit(base, port); +} + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} +/*@}*/ +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the GPIO PIN. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return (uint32_t)base->B[port][pin]; +} + +/*! + * @brief Reads the current input value of the GPIO PIN. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return GPIO_PinRead(base, port, pin); +} +/*@}*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->SET[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortSet(base, port, mask); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->CLR[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortClear(base, port, mask); +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->NOT[port] = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortToggle. + */ +static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortToggle(base, port, mask); +} +/*@}*/ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + */ +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->PIN[port]; +} + +/*! + * @brief Reads the current input value of the whole GPIO port. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortRead + */ +static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) +{ + return GPIO_PortRead(base, port); +} + +/*@}*/ +/*! @name GPIO Mask Operations */ +/*@{*/ + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->MASK[port] = mask; +} + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedSet. + */ +static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortMaskedSet(base, port, mask); +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param output GPIO port output value. + */ +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) +{ + base->MPIN[port] = output; +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedWrite. + */ +static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output) +{ + GPIO_PortMaskedWrite(base, port, output); +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @retval masked GPIO port value + */ +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->MPIN[port]; +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedRead. + */ +static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port) +{ + return GPIO_PortMaskedRead(base, port); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.c new file mode 100644 index 00000000000..b7ee6929fed --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.c @@ -0,0 +1,1514 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_i2c.h" +#include "fsl_flexcomm.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" +#endif + + +/*! @brief Common sets of flags used by the driver. */ +enum _i2c_flag_constants +{ + kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK, + kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); +static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); +static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); +static uint32_t I2C_SlavePollPending(I2C_Type *base); +static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); +static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); +static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, + i2c_slave_handle_t *handle, + const void *txData, + size_t txSize, + void *rxData, + size_t rxSize, + uint32_t eventMask); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map i2c instance number to base address. */ +static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2C peripheral base address. + * @return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base) +{ + int i; + for (i = 0; i < FSL_FEATURE_SOC_I2C_COUNT; i++) + { + if ((uint32_t)base == s_i2cBaseAddrs[i]) + { + return i; + } + } + assert(false); + return 0; +} + +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + masterConfig->enableMaster = true; + masterConfig->baudRate_Bps = 100000U; + masterConfig->enableTimeout = false; +} + +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + I2C_MasterEnable(base, masterConfig->enableMaster); + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); +} + +void I2C_MasterDeinit(I2C_Type *base) +{ + I2C_MasterEnable(base, false); +} + +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t scl, divider; + uint32_t best_scl, best_div; + uint32_t err, best_err; + + best_err = 0; + + for (scl = 9; scl >= 2; scl--) + { + /* calculated ideal divider value for given scl */ + divider = srcClock_Hz / (baudRate_Bps * scl * 2u); + + /* adjust it if it is out of range */ + divider = (divider > 0x10000u) ? 0x10000 : divider; + + /* calculate error */ + err = srcClock_Hz - (baudRate_Bps * scl * 2u * divider); + if ((err < best_err) || (best_err == 0)) + { + best_div = divider; + best_scl = scl; + best_err = err; + } + + if ((err == 0) || (divider >= 0x10000u)) + { + /* either exact value was found + or divider is at its max (it would even greater in the next iteration for sure) */ + break; + } + } + + base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1); + base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl - 2u) | I2C_MSTTIME_MSTSCLHIGH(best_scl - 2u); +} + +static uint32_t I2C_PendingStatusWait(I2C_Type *base) +{ + uint32_t status; + +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; +#endif + + do + { + status = I2C_GetStatusFlags(base); +#if I2C_WAIT_TIMEOUT + } while (((status & I2C_STAT_MSTPENDING_MASK) == 0) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); +#endif + + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + return status; +} + +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result; + result = I2C_PendingStatusWait(base); + if (result == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Write Address and RW bit to data register */ + base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u); + /* Start the transfer */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + + return kStatus_Success; +} + +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result; + result = I2C_PendingStatusWait(base); + if (result == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + return kStatus_Success; +} + +status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) +{ + uint32_t status; + uint32_t master_state; + status_t err; + + const uint8_t *buf = (const uint8_t *)(uintptr_t)txBuff; + + assert(txBuff); + + err = kStatus_Success; + while (txSize) + { + status = I2C_PendingStatusWait(base); + +#if I2C_WAIT_TIMEOUT + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + + if (status & I2C_STAT_MSTARBLOSS_MASK) + { + return kStatus_I2C_ArbitrationLost; + } + + if (status & I2C_STAT_MSTSTSTPERR_MASK) + { + return kStatus_I2C_StartStopError; + } + + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + switch (master_state) + { + case I2C_STAT_MSTCODE_TXREADY: + /* ready to send next byte */ + base->MSTDAT = *buf++; + txSize--; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + break; + + case I2C_STAT_MSTCODE_NACKADR: + case I2C_STAT_MSTCODE_NACKDAT: + /* slave nacked the last byte */ + err = kStatus_I2C_Nak; + break; + + default: + /* unexpected state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + if (err != kStatus_Success) + { + return err; + } + } + + status = I2C_PendingStatusWait(base); + +#if I2C_WAIT_TIMEOUT + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + + if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0) + { + if (!(flags & kI2C_TransferNoStopFlag)) + { + /* Initiate stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + if (status & I2C_STAT_MSTARBLOSS_MASK) + { + return kStatus_I2C_ArbitrationLost; + } + + if (status & I2C_STAT_MSTSTSTPERR_MASK) + { + return kStatus_I2C_StartStopError; + } + + return kStatus_Success; +} + +status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) +{ + uint32_t status = 0; + uint32_t master_state; + status_t err; + + uint8_t *buf = (uint8_t *)(rxBuff); + + assert(rxBuff); + + err = kStatus_Success; + while (rxSize) + { + status = I2C_PendingStatusWait(base); + +#if I2C_WAIT_TIMEOUT + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + + if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) + { + break; + } + + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + switch (master_state) + { + case I2C_STAT_MSTCODE_RXREADY: + /* ready to send next byte */ + *(buf++) = base->MSTDAT; + if (--rxSize) + { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + else + { + if ((flags & kI2C_TransferNoStopFlag) == 0) + { + /* initiate NAK and stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + status = I2C_PendingStatusWait(base); + +#if I2C_WAIT_TIMEOUT + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } +#endif + } + } + break; + + case I2C_STAT_MSTCODE_NACKADR: + case I2C_STAT_MSTCODE_NACKDAT: + /* slave nacked the last byte */ + err = kStatus_I2C_Nak; + break; + + default: + /* unexpected state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + if (err != kStatus_Success) + { + return err; + } + } + + if (status & I2C_STAT_MSTARBLOSS_MASK) + { + return kStatus_I2C_ArbitrationLost; + } + + if (status & I2C_STAT_MSTSTSTPERR_MASK) + { + return kStatus_I2C_StartStopError; + } + + return kStatus_Success; +} + +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + uint32_t subaddress; + uint8_t subaddrBuf[4]; + int i; + + assert(xfer); + + /* If repeated start is requested, send repeated start. */ + if (!(xfer->flags & kI2C_TransferNoStartFlag)) + { + if (xfer->subaddressSize) + { + result = I2C_MasterStart(base, xfer->slaveAddress, kI2C_Write); + if (result == kStatus_Success) + { + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = xfer->subaddressSize - 1; i >= 0; i--) + { + subaddrBuf[i] = subaddress & 0xff; + subaddress >>= 8; + } + /* Send subaddress. */ + result = I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, kI2C_TransferNoStopFlag); + if ((result == kStatus_Success) && (xfer->direction == kI2C_Read)) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); + } + } + } + else if (xfer->flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); + } + else + { + result = I2C_MasterStart(base, xfer->slaveAddress, xfer->direction); + } + } + + if (result == kStatus_Success) + { + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + { + /* Transmit data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + else + { + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) + { + /* Receive Data. */ + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + } + } + + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; +} + +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(handle); + + /* Clear out the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferHandleIRQ, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + EnableIRQ(s_i2cIRQ[instance]); +} + +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result; + + assert(handle); + assert(xfer); + assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != kIdleState) + { + return kStatus_I2C_Busy; + } + + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + + /* Prepare transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + /* Clear error flags. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Enable I2C internal IRQ sources. */ + I2C_EnableInterrupts(base, kI2C_MasterIrqFlags); + + return result; +} + +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + *count = handle->transferCount; + return kStatus_Success; +} + +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + uint32_t status; + uint32_t master_state; + + if (handle->state != kIdleState) + { + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + + /* Wait until module is ready */ + status = I2C_PendingStatusWait(base); + +#if I2C_WAIT_TIMEOUT + if (status == kStatus_I2C_Timeout) + { + /* Reset handle to idle state. */ + handle->state = kIdleState; + return kStatus_I2C_Timeout; + } +#endif + + /* Get the state of the I2C module */ + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if (master_state != I2C_STAT_MSTCODE_IDLE) + { + /* Send a stop command to finalize the transfer. */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + + /* Wait until the STOP is completed */ + status = I2C_PendingStatusWait(base); + if (status == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* Reset handle. */ + handle->state = kIdleState; + } + return kStatus_Success; +} + +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param handle Master nonblocking driver handle. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + struct _i2c_master_transfer *transfer; + + handle->transfer = *xfer; + transfer = &(handle->transfer); + + handle->transferCount = 0; + handle->remainingBytes = transfer->dataSize; + handle->buf = (uint8_t *)transfer->data; + handle->remainingSubaddr = 0; + + if (transfer->flags & kI2C_TransferNoStartFlag) + { + /* Start condition shall be ommited, switch directly to next phase */ + if (transfer->dataSize == 0) + { + handle->state = kStopState; + } + else if (handle->transfer.direction == kI2C_Write) + { + handle->state = kTransmitDataState; + } + else if (handle->transfer.direction == kI2C_Read) + { + handle->state = kReceiveDataState; + } + else + { + return kStatus_I2C_InvalidParameter; + } + } + else + { + if (transfer->subaddressSize != 0) + { + int i; + uint32_t subaddress; + + if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) + { + return kStatus_I2C_InvalidParameter; + } + + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = xfer->subaddressSize - 1; i >= 0; i--) + { + handle->subaddrBuf[i] = subaddress & 0xff; + subaddress >>= 8; + } + handle->remainingSubaddr = transfer->subaddressSize; + } + handle->state = kStartState; + } + + return kStatus_Success; +} + +/*! + * @brief Execute states until FIFOs are exhausted. + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_I2C_ArbitrationLost + * @retval #kStatus_I2C_Nak + */ +static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t master_state; + struct _i2c_master_transfer *transfer; + status_t err; + + transfer = &(handle->transfer); + + *isDone = false; + + status = I2C_GetStatusFlags(base); + + if (status & I2C_STAT_MSTARBLOSS_MASK) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); + return kStatus_I2C_ArbitrationLost; + } + + if (status & I2C_STAT_MSTSTSTPERR_MASK) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); + return kStatus_I2C_StartStopError; + } + + if ((status & I2C_STAT_MSTPENDING_MASK) == 0) + { + return kStatus_I2C_Busy; + } + + /* Get the state of the I2C module */ + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) + { + /* Slave NACKed last byte, issue stop and return error */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + return kStatus_I2C_Nak; + } + + err = kStatus_Success; + switch (handle->state) + { + case kStartState: + if (handle->remainingSubaddr) + { + /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = kTransmitSubaddrState; + } + else if (transfer->direction == kI2C_Write) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = handle->remainingBytes ? kTransmitDataState : kStopState; + } + else + { + base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; + handle->state = handle->remainingBytes ? kReceiveDataState : kStopState; + } + /* Send start condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + break; + + case kTransmitSubaddrState: + if (master_state != I2C_STAT_MSTCODE_TXREADY) + { + return kStatus_I2C_UnexpectedState; + } + + /* Most significant subaddress byte comes first */ + base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + if (--(handle->remainingSubaddr)) + { + /* There are still subaddress bytes to be transmitted */ + break; + } + if (handle->remainingBytes) + { + /* There is data to be transferred, if there is write to read turnaround it is necessary to perform + * repeated start */ + handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; + } + else + { + /* No more data, schedule stop condition */ + handle->state = kStopState; + } + break; + + case kTransmitDataState: + if (master_state != I2C_STAT_MSTCODE_TXREADY) + { + return kStatus_I2C_UnexpectedState; + } + base->MSTDAT = *(handle->buf)++; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + if (--handle->remainingBytes == 0) + { + /* No more data, schedule stop condition */ + handle->state = kStopState; + } + handle->transferCount++; + break; + + case kReceiveDataState: + if (master_state != I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + *(handle->buf)++ = base->MSTDAT; + if (--handle->remainingBytes) + { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + else + { + /* No more data expected, issue NACK and STOP right away */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + } + handle->transferCount++; + break; + + case kStopState: + if (transfer->flags & kI2C_TransferNoStopFlag) + { + /* Stop condition is omitted, we are done */ + *isDone = true; + handle->state = kIdleState; + break; + } + /* Send stop condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + break; + + case kWaitForCompletionState: + *isDone = true; + handle->state = kIdleState; + break; + + case kIdleState: + default: + /* State machine shall not be invoked again once it enters the idle state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + return err; +} + +void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (!handle) + { + return; + } + + result = I2C_RunTransferStateMachine(base, handle, &isDone); + + if (isDone || (result != kStatus_Success)) + { + /* Restore handle to idle state. */ + handle->state = kIdleState; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + + /* Invoke callback. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +/*! + * @brief Sets the hardware slave state machine to reset + * + * Per documentation, the only the state machine is reset, the configuration settings remain. + * + * @param base The I2C peripheral base address. + */ +static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) +{ + I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ +} + +/*! + * @brief Compute CLKDIV + * + * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. + * This setting is used by hardware during slave clock stretching. + * + * @param base The I2C peripheral base address. + * @return status of the operation + */ +static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) +{ + uint32_t dataSetupTime_ns; + + switch (busSpeed) + { + case kI2C_SlaveStandardMode: + dataSetupTime_ns = 250u; + break; + + case kI2C_SlaveFastMode: + dataSetupTime_ns = 100u; + break; + + case kI2C_SlaveFastModePlus: + dataSetupTime_ns = 50u; + break; + + case kI2C_SlaveHsMode: + dataSetupTime_ns = 10u; + break; + + default: + dataSetupTime_ns = 0; + break; + } + + if (0 == dataSetupTime_ns) + { + return kStatus_InvalidArgument; + } + + /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ + *divVal = srcClock_Hz / 1000u; + *divVal = (*divVal) * dataSetupTime_ns; + *divVal = (*divVal) / 1000000u; + + if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) + { + *divVal = I2C_CLKDIV_DIVVAL_MASK; + } + + return kStatus_Success; +} + +/*! + * @brief Poll wait for the SLVPENDING flag. + * + * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. + * + * @param base The I2C peripheral base address. + * @return status register at time the SLVPENDING bit is read as set + */ +static uint32_t I2C_SlavePollPending(I2C_Type *base) +{ + uint32_t stat; + +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; +#endif + do + { + stat = base->STAT; +#if I2C_WAIT_TIMEOUT + } while ((0u == (stat & I2C_STAT_SLVPENDING_MASK)) && (--waitTimes)); + + if (waitTimes == 0u) + { + return kStatus_I2C_Timeout; + } +#else + } while (0u == (stat & I2C_STAT_SLVPENDING_MASK)); +#endif + + return stat; +} + +/*! + * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). + * + * Sets the event type to transfer structure and invokes the event callback, if it has been + * enabled by eventMask. + * + * @param base The I2C peripheral base address. + * @param handle The I2C slave handle for non-blocking APIs. + * @param event The I2C slave event to invoke. + */ +static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) +{ + handle->transfer.event = event; + if ((handle->callback) && (handle->transfer.eventMask & event)) + { + handle->callback(base, &handle->transfer, handle->userData); + + /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ + if (false == handle->isBusy) + { + if (((handle->transfer.txData) && (handle->transfer.txSize)) || + ((handle->transfer.rxData) && (handle->transfer.rxSize))) + { + handle->isBusy = true; + } + } + + /* Clear the transferred count now that we have a new buffer. */ + if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) + { + handle->transfer.transferredCount = 0; + } + } +} + +/*! + * @brief Handle slave address match event. + * + * Called by Slave interrupt routine to ACK or NACK the matched address. + * It also determines master direction (read or write). + * + * @param base The I2C peripheral base address. + * @return true if the matched address is ACK'ed + * @return false if the matched address is NACK'ed + */ +static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) +{ + uint8_t addressByte0; + + addressByte0 = (uint8_t)base->SLVDAT; + + /* store the matched address */ + handle->transfer.receivedAddress = addressByte0; + + /* R/nW */ + if (addressByte0 & 1u) + { + /* if we have no data in this transfer, call callback to get new */ + if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); + } + + /* NACK if we have no data in this transfer. */ + if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + return false; + } + + /* master wants to read, so slave transmit is next state */ + handle->slaveFsm = kI2C_SlaveFsmTransmit; + } + else + { + /* if we have no receive buffer in this transfer, call callback to get new */ + if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); + } + + /* NACK if we have no data in this transfer */ + if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + return false; + } + + /* master wants write, so slave receive is next state */ + handle->slaveFsm = kI2C_SlaveFsmReceive; + } + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + return true; +} + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. + * @param txSize Size of txData buffer in bytes. + * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL + * if slave TX only. + * @param rxSize Size of rxData buffer in bytes. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, + i2c_slave_handle_t *handle, + const void *txData, + size_t txSize, + void *rxData, + size_t rxSize, + uint32_t eventMask) +{ + status_t status; + + assert(handle); + + status = kStatus_Success; + + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + status = kStatus_I2C_Busy; + } + + /* Save transfer into handle. */ + handle->transfer.txData = (const uint8_t *)(uintptr_t)txData; + handle->transfer.txSize = txSize; + handle->transfer.rxData = (uint8_t *)rxData; + handle->transfer.rxSize = rxSize; + handle->transfer.transferredCount = 0; + handle->transfer.eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; + handle->isBusy = true; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* Clear w1c flags. */ + base->STAT |= 0u; + + /* Enable I2C internal IRQ sources. */ + I2C_EnableInterrupts(base, kI2C_SlaveIrqFlags); + + return status; +} + +status_t I2C_SlaveSetSendBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); +} + +status_t I2C_SlaveSetReceiveBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); +} + +void I2C_SlaveSetAddress(I2C_Type *base, + i2c_slave_address_register_t addressRegister, + uint8_t address, + bool addressDisable) +{ + base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); +} + +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + i2c_slave_config_t mySlaveConfig = {0}; + + /* default config enables slave address 0 match to general I2C call address zero */ + mySlaveConfig.enableSlave = true; + mySlaveConfig.address1.addressDisable = true; + mySlaveConfig.address2.addressDisable = true; + mySlaveConfig.address3.addressDisable = true; + + *slaveConfig = mySlaveConfig; +} + +status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) +{ + status_t status; + uint32_t divVal = 0; + + /* configure data setup time used when slave stretches clock */ + status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); + if (kStatus_Success != status) + { + return status; + } + + FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + + /* I2C Clock Divider register */ + base->CLKDIV = divVal; + + /* set Slave address */ + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, + slaveConfig->address0.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, + slaveConfig->address1.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, + slaveConfig->address2.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, + slaveConfig->address3.addressDisable); + + /* set Slave address 0 qual */ + base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); + + /* set Slave enable */ + base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); + + return status; +} + +void I2C_SlaveDeinit(I2C_Type *base) +{ + I2C_SlaveEnable(base, false); +} + +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + const uint8_t *buf = txBuff; + uint32_t stat; + bool slaveAddress; + bool slaveTransmit; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Get slave machine state */ + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); + + /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ + if (!(slaveAddress || slaveTransmit)) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + if (slaveAddress) + { + /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* send bytes up to txSize */ + while (txSize) + { + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); + + if (!slaveTransmit) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + /* Write 8 bits of data to the SLVDAT register */ + base->SLVDAT = I2C_SLVDAT_DATA(*buf); + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* advance counters and pointers for next data */ + buf++; + txSize--; + + if (txSize) + { + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + return kStatus_Success; +} + +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + uint8_t *buf = rxBuff; + uint32_t stat; + bool slaveAddress; + bool slaveReceive; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Get slave machine state */ + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); + + /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ + if (!(slaveAddress || slaveReceive)) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + if (slaveAddress) + { + /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* receive bytes up to rxSize */ + while (rxSize) + { + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); + + if (!slaveReceive) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + /* Read 8 bits of data from the SLVDAT register */ + *buf = (uint8_t)base->SLVDAT; + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* advance counters and pointers for next data */ + buf++; + rxSize--; + + if (rxSize) + { + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + return kStatus_Success; +} + +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(handle); + + /* Clear out the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* initialize fsm */ + handle->slaveFsm = kI2C_SlaveFsmAddressMatch; + + /* store pointer to handle into transfer struct */ + handle->transfer.handle = handle; + + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_SlaveTransferHandleIRQ, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); + EnableIRQ(s_i2cIRQ[instance]); +} + +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); +} + +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); + + /* Set the SLVEN bit to 0 in the CFG register. */ + I2C_SlaveEnable(base, false); + + handle->isBusy = false; + handle->transfer.txSize = 0; + handle->transfer.rxSize = 0; +} + +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) +{ + uint32_t i2cStatus = base->STAT; + + if (i2cStatus & I2C_STAT_SLVDESEL_MASK) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); + I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); + } + + /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ + if (i2cStatus & I2C_STAT_SLVPENDING_MASK) + { + bool slaveAddress = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); + + if (slaveAddress) + { + I2C_SlaveAddressIRQ(base, handle); + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); + } + else + { + switch (handle->slaveFsm) + { + case kI2C_SlaveFsmReceive: + { + bool slaveReceive = + (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); + + if (slaveReceive) + { + /* if we have no receive buffer in this transfer, call callback to get new */ + if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); + } + + /* receive a byte */ + if ((handle->transfer.rxData) && (handle->transfer.rxSize)) + { + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + *(handle->transfer.rxData) = (uint8_t)base->SLVDAT; + (handle->transfer.rxSize)--; + (handle->transfer.rxData)++; + (handle->transfer.transferredCount)++; + } + + /* is this last transaction for this transfer? allow next transaction */ + if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) + { + handle->isBusy = false; + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); + } + } + else + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + } + } + break; + + case kI2C_SlaveFsmTransmit: + { + bool slaveTransmit = + (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); + + if (slaveTransmit) + { + /* if we have no data in this transfer, call callback to get new */ + if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); + } + + /* transmit a byte */ + if ((handle->transfer.txData) && (handle->transfer.txSize)) + { + base->SLVDAT = *(handle->transfer.txData); + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + (handle->transfer.txSize)--; + (handle->transfer.txData)++; + (handle->transfer.transferredCount)++; + } + + /* is this last transaction for this transfer? allow next transaction */ + if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) + { + handle->isBusy = false; + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); + } + } + else + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + } + } + break; + + default: + /* incorrect state, slv_abort()? */ + break; + } + } + } +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.h new file mode 100644 index 00000000000..8afb082c07e --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c.h @@ -0,0 +1,1067 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define I2C_CFG_MASK 0x1f + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! @file */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version 2.0.3. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/*! @brief Timeout times for waiting flag. */ +#ifndef I2C_WAIT_TIMEOUT +#define I2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/* definitions for MSTCODE bits in I2C Status register STAT */ +#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ +#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ +#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */ +#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */ +#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */ + +/* definitions for SLVSTATE bits in I2C Status register STAT */ +#define I2C_STAT_SLVST_ADDR (0) +#define I2C_STAT_SLVST_RX (1) +#define I2C_STAT_SLVST_TX (2) + +/*! @brief I2C status return codes. */ +enum _i2c_status +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ + kStatus_I2C_Nak = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_I2C_InvalidParameter = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ + kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ + kStatus_I2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ + kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), + kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 10), /*!< Timeout poling status flags. */ +}; + +/*! @} */ + +/*! + * @addtogroup i2c_master_driver + * @{ + */ + +/*! + * @brief I2C master peripheral flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_master_flags +{ + kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ + kI2C_MasterArbitrationLostFlag = + I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */ + kI2C_MasterStartStopErrorFlag = + I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */ +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0U, /*!< Master transmit. */ + kI2C_Read = 1U /*!< Master receive. */ +} i2c_direction_t; + +/*! + * @brief Structure with settings to initialize the I2C master module. + * + * This structure holds configuration settings for the I2C peripheral. To initialize this + * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ + bool enableTimeout; /*!< Enable internal timeout function. */ +} i2c_master_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +/*! @brief I2C master transfer typedef */ +typedef struct _i2c_master_transfer i2c_master_transfer_t; + +/*! @brief I2C master handle typedef */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to I2C_MasterTransferCreateHandle(). + * + * @param base The I2C peripheral base address. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_i2c_master_transfer::flags field. + */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i2c_transfer_states +{ + kIdleState = 0, + kTransmitSubaddrState, + kTransmitDataState, + kReceiveDataState, + kReceiveLastDataState, + kStartState, + kStopState, + kWaitForCompletionState +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. + */ +struct _i2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available + options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ + i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint32_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint32_t remainingSubaddr; + uint8_t subaddrBuf[4]; + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @} */ + +/*! + * @addtogroup i2c_slave_driver + * @{ + */ + +/*! +* @brief I2C slave peripheral flags. +* +* @note These enums are meant to be OR'd together to form a bit mask. +*/ +enum _i2c_slave_flags +{ + kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ + kI2C_SlaveNotStretching = + I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */ + kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */ + kI2C_SaveDeselected = + I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */ +}; + +/*! @brief I2C slave address register. */ +typedef enum _i2c_slave_address_register +{ + kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ + kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ + kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ + kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ +} i2c_slave_address_register_t; + +/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ +typedef struct _i2c_slave_address +{ + uint8_t address; /*!< 7-bit Slave address SLVADR. */ + bool addressDisable; /*!< Slave address disable SADISABLE. */ +} i2c_slave_address_t; + +/*! @brief I2C slave address match options. */ +typedef enum _i2c_slave_address_qual_mode +{ + kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ + kI2C_QualModeExtend = + 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ +} i2c_slave_address_qual_mode_t; + +/*! @brief I2C slave bus speed options. */ +typedef enum _i2c_slave_bus_speed +{ + kI2C_SlaveStandardMode = 0U, + kI2C_SlaveFastMode = 1U, + kI2C_SlaveFastModePlus = 2U, + kI2C_SlaveHsMode = 3U, +} i2c_slave_bus_speed_t; + +/*! + * @brief Structure with settings to initialize the I2C slave module. + * + * This structure holds configuration settings for the I2C slave peripheral. To initialize this + * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i2c_slave_config +{ + i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ + i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ + uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ + i2c_slave_bus_speed_t + busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must + provide sufficient data setup time to the master before releasing the stretched clock. + This is accomplished by inserting one clock time of CLKDIV at that point. + The #busSpeed value is used to configure CLKDIV + such that one clock time is greater than the tSU;DAT value noted + in the I2C bus specification for the I2C mode that is being used. + If the #busSpeed mode is unknown at compile time, use the longest data setup time + kI2C_SlaveStandardMode (250 ns) */ + bool enableSlave; /*!< Enable slave mode. */ +} i2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ + kI2C_SlaveDeselectedEvent = + 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ + + /*! Bit mask of all available events. */ + kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | + kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C slave transfer structure */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ + i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint8_t *rxData; /*!< Transfer buffer for receive data */ + const uint8_t *txData; /*!< Transfer buffer for transmit data */ + size_t txSize; /*!< Transfer size */ + size_t rxSize; /*!< Transfer size */ + size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ +} i2c_slave_transfer_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the I2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the I2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief I2C slave software finite state machine states. + */ +typedef enum _i2c_slave_fsm +{ + kI2C_SlaveFsmAddressMatch = 0u, + kI2C_SlaveFsmReceive = 2u, + kI2C_SlaveFsmTransmit = 3u, +} i2c_slave_fsm_t; + +/*! + * @brief I2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _i2c_slave_handle +{ + volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ + volatile bool isBusy; /*!< Whether transfer is busy. */ + volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ + i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup i2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I2C master peripheral. + * + * This function provides the following default configuration for the I2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableTimeout = false; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I2C master peripheral. + * + * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The I2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! +* @brief Deinitializes the I2C master peripheral. +* + * This function disables the I2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2C peripheral base address. + * @return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the I2C master peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +static inline void I2C_MasterReset(I2C_Type *base) +{ +} + +/*! + * @brief Enables or disables the I2C module as master. + * + * @param base The I2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified I2C as master. + */ +static inline void I2C_MasterEnable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; + } + else + { + base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; + } +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the I2C status flags. + * + * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i2c_master_flags + */ +static inline uint32_t I2C_GetStatusFlags(I2C_Type *base) +{ + return base->STAT; +} + +/*! + * @brief Clears the I2C master status flag state. + * + * The following status register flags can be cleared: + * - #kI2C_MasterArbitrationLostFlag + * - #kI2C_MasterStartStopErrorFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * I2C_GetStatusFlags(). + * @see _i2c_master_flags. + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Allow clearing just master status flags */ + base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); +} + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the I2C master interrupt requests. + * + * @param base The I2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) +{ + base->INTENSET = interruptMask; +} + +/*! + * @brief Disables the I2C master interrupt requests. + * + * @param base The I2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) +{ + base->INTENCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I2C master interrupt requests. + * + * @param base The I2C peripheral base address. + * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) +{ + return base->INTSTAT; +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The I2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @param base The I2C peripheral base address. + * @param srcClock_Hz I2C functional clock frequency in Hertz. + * @param baudRate_Bps Requested bus frequency in bits per second. + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The I2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) +{ + /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ + return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); +} + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + return I2C_MasterStart(base, address, direction); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I2C_Nak. + * + * @param base The I2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * @retval kStatus_Success Data was sent successfully. + * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The I2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. + * + * @param base The I2C peripheral base address. + * @param[out] handle Pointer to the I2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @param xfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval #kStatus_I2C_Busy + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I2C peripheral's IRQ priority. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_I2C_Timeout Timeout during polling for flags. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); + +/*@}*/ + +/*! @} */ /* end of i2c_master_driver */ + +/*! + * @addtogroup i2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I2C slave peripheral. + * + * This function provides the following default configuration for the I2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0.disable = false; + * slaveConfig->address0.address = 0u; + * slaveConfig->address1.disable = true; + * slaveConfig->address2.disable = true; + * slaveConfig->address3.disable = true; + * slaveConfig->busSpeed = kI2C_SlaveStandardMode; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a + * address0.address member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #i2c_slave_config_t. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the I2C slave peripheral. + * + * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user + * provided configuration. + * + * @param base The I2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide + * enough + * data setup time for master when slave stretches the clock. + */ +status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); + +/*! + * @brief Configures Slave Address n register. + * + * This function writes new value to Slave Address register. + * + * @param base The I2C peripheral base address. + * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. + * @param address The slave address to be stored to the address register for matching. + * @param addressDisable Disable matching of the specified address register. + */ +void I2C_SlaveSetAddress(I2C_Type *base, + i2c_slave_address_register_t addressRegister, + uint8_t address, + bool addressDisable); + +/*! +* @brief Deinitializes the I2C slave peripheral. +* + * This function disables the I2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Enables or disables the I2C module as slave. + * + * @param base The I2C peripheral base address. + * @param enable True to enable or flase to disable. + */ +static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) +{ + /* Set or clear the SLVEN bit in the CFG register. */ + base->CFG = I2C_CFG_SLVEN(enable); +} + +/*@}*/ /* end of Slave initialization and deinitialization */ + +/*! @name Slave status */ +/*@{*/ + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: + * - slave deselected flag + * + * Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * I2C_SlaveGetStatusFlags(). + * @see _i2c_slave_flags. + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Allow clearing just slave status flags */ + base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; +} + +/*@}*/ /* end of Slave status */ + +/*! @name Slave bus operations */ +/*@{*/ + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * @param base The I2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @return kStatus_Success Data has been sent. + * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * @param base The I2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @return kStatus_Success Data has been received. + * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*@}*/ /* end of Slave bus operations */ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. + * + * @param base The I2C peripheral base address. + * @param[out] handle Pointer to the I2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. + * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Starts accepting master read from slave requests. + * + * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param transfer Pointer to #i2c_slave_transfer_t structure. + * @param txData Pointer to data to send to master. + * @param txSize Size of txData in bytes. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetSendBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); + +/*! + * @brief Starts accepting master write to slave requests. + * + * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param transfer Pointer to #i2c_slave_transfer_t structure. + * @param rxData Pointer to data to store data from master. + * @param rxSize Size of rxData in bytes. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetReceiveBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. + * + * @param base The I2C peripheral base address. + * @param transfer The I2C slave transfer. + * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) +{ + return transfer->receivedAddress; +} + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @retval kStatus_Success + * @retval #kStatus_I2C_Idle + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*@}*/ /* end of Slave non-blocking */ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); + +/*@}*/ /* end of Slave IRQ handler */ + +/*! @} */ /* end of i2c_slave_driver */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2C_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.c new file mode 100644 index 00000000000..f8de0ab241d --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.c @@ -0,0 +1,581 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_i2c_dma.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" +#endif + + +/*transfer = *xfer; + transfer = &(handle->transfer); + + handle->transferCount = 0; + handle->remainingBytesDMA = 0; + handle->buf = (uint8_t *)transfer->data; + handle->remainingSubaddr = 0; + + if (transfer->flags & kI2C_TransferNoStartFlag) + { + /* Start condition shall be ommited, switch directly to next phase */ + if (transfer->dataSize == 0) + { + handle->state = kStopState; + } + else if (handle->transfer.direction == kI2C_Write) + { + handle->state = xfer->dataSize = kTransmitDataState; + } + else if (handle->transfer.direction == kI2C_Read) + { + handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState; + } + else + { + return kStatus_I2C_InvalidParameter; + } + } + else + { + if (transfer->subaddressSize != 0) + { + int i; + uint32_t subaddress; + + if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) + { + return kStatus_I2C_InvalidParameter; + } + + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = xfer->subaddressSize - 1; i >= 0; i--) + { + handle->subaddrBuf[i] = subaddress & 0xff; + subaddress >>= 8; + } + handle->remainingSubaddr = transfer->subaddressSize; + } + + handle->state = kStartState; + } + + return kStatus_Success; +} + +static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + int transfer_size; + dma_transfer_config_t xferConfig; + + /* Update transfer count */ + handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data; + + /* Check if there is anything to be transferred at all */ + if (handle->remainingBytesDMA == 0) + { + /* No data to be transferrred, disable DMA */ + base->MSTCTL = 0; + return; + } + + /* Calculate transfer size */ + transfer_size = handle->remainingBytesDMA; + if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT) + { + transfer_size = I2C_MAX_DMA_TRANSFER_COUNT; + } + + switch (handle->transfer.direction) + { + case kI2C_Write: + DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size, + kDMA_MemoryToPeripheral, NULL); + break; + + case kI2C_Read: + DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size, + kDMA_PeripheralToMemory, NULL); + break; + + default: + /* This should never happen */ + assert(0); + break; + } + + DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + DMA_StartTransfer(handle->dmaHandle); + + handle->remainingBytesDMA -= transfer_size; + handle->buf += transfer_size; +} + +/*! + * @brief Execute states until the transfer is done. + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_I2C_ArbitrationLost + * @retval #kStatus_I2C_Nak + */ +static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t master_state; + struct _i2c_master_transfer *transfer; + dma_transfer_config_t xferConfig; + status_t err; + uint32_t start_flag = 0; + + transfer = &(handle->transfer); + + *isDone = false; + + status = I2C_GetStatusFlags(base); + + if (status & I2C_STAT_MSTARBLOSS_MASK) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_ArbitrationLost; + } + + if (status & I2C_STAT_MSTSTSTPERR_MASK) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_StartStopError; + } + + if ((status & I2C_STAT_MSTPENDING_MASK) == 0) + { + return kStatus_I2C_Busy; + } + + /* Get the state of the I2C module */ + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) + { + /* Slave NACKed last byte, issue stop and return error */ + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + return kStatus_I2C_Nak; + } + + err = kStatus_Success; + + if (handle->state == kStartState) + { + /* set start flag for later use */ + start_flag = I2C_MSTCTL_MSTSTART_MASK; + + if (handle->remainingSubaddr) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = kTransmitSubaddrState; + } + else if (transfer->direction == kI2C_Write) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + if (transfer->dataSize == 0) + { + /* No data to be transferred, initiate start and schedule stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + handle->state = kStopState; + return err; + } + handle->state = kTransmitDataState; + } + else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0)) + { + base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; + if (transfer->dataSize == 1) + { + /* The very last byte is always received by means of SW */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + handle->state = kReceiveLastDataState; + return err; + } + handle->state = kReceiveDataState; + } + else + { + handle->state = kIdleState; + err = kStatus_I2C_UnexpectedState; + return err; + } + } + + switch (handle->state) + { + case kTransmitSubaddrState: + if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) + { + return kStatus_I2C_UnexpectedState; + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + + /* Prepare and submit DMA transfer. */ + DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t), + handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); + DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + DMA_StartTransfer(handle->dmaHandle); + handle->remainingSubaddr = 0; + if (transfer->dataSize) + { + /* There is data to be transferred, if there is write to read turnaround it is necessary to perform + * repeated start */ + handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; + } + else + { + /* No more data, schedule stop condition */ + handle->state = kStopState; + } + break; + + case kTransmitDataState: + if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) + { + return kStatus_I2C_UnexpectedState; + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + handle->remainingBytesDMA = handle->transfer.dataSize; + + I2C_RunDMATransfer(base, handle); + + /* Schedule stop condition */ + handle->state = kStopState; + break; + + case kReceiveDataState: + if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag)) + { + return kStatus_I2C_UnexpectedState; + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + handle->remainingBytesDMA = handle->transfer.dataSize - 1; + + I2C_RunDMATransfer(base, handle); + + /* Schedule reception of last data byte */ + handle->state = kReceiveLastDataState; + break; + + case kReceiveLastDataState: + if (master_state != I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + + ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT; + handle->transferCount++; + + /* No more data expected, issue NACK and STOP right away */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + break; + + case kStopState: + if (transfer->flags & kI2C_TransferNoStopFlag) + { + /* Stop condition is omitted, we are done */ + *isDone = true; + handle->state = kIdleState; + break; + } + /* Send stop condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = kWaitForCompletionState; + break; + + case kWaitForCompletionState: + *isDone = true; + handle->state = kIdleState; + break; + + case kStartState: + case kIdleState: + default: + /* State machine shall not be invoked again once it enters the idle state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + return err; +} + +void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (!handle) + { + return; + } + + result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); + + if (isDone || (result != kStatus_Success)) + { + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, + I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); + + /* Invoke callback. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData) +{ + i2c_master_dma_private_handle_t *dmaPrivateHandle; + + /* Don't do anything if we don't have a valid handle. */ + if (!handle) + { + return; + } + + dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; + I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); +} + +void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *dmaHandle) +{ + uint32_t instance; + + assert(handle); + assert(dmaHandle); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Set the user callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferDMAHandleIRQ, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, + I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); + EnableIRQ(s_i2cIRQ[instance]); + + /* Set the handle for DMA. */ + handle->dmaHandle = dmaHandle; + + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + DMA_SetCallback(dmaHandle, (dma_callback)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); +} + +status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result; + + assert(handle); + assert(xfer); + assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != kIdleState) + { + return kStatus_I2C_Busy; + } + + /* Prepare transfer state machine. */ + result = I2C_InitTransferStateMachineDMA(base, handle, xfer); + + /* Clear error flags. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Enable I2C internal IRQ sources */ + I2C_EnableInterrupts(base, + I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK); + + return result; +} + +status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + *count = handle->transferCount; + return kStatus_Success; +} + +void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + uint32_t status; + uint32_t master_state; + + if (handle->state != kIdleState) + { + DMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA */ + base->MSTCTL = 0; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, + I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); + + /* Wait until module is ready */ + do + { + status = I2C_GetStatusFlags(base); + } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); + + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Get the state of the I2C module */ + master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if (master_state != I2C_STAT_MSTCODE_IDLE) + { + /* Send a stop command to finalize the transfer. */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + + /* Wait until module is ready */ + do + { + status = I2C_GetStatusFlags(base); + } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); + + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + } + + /* Reset the state to idle. */ + handle->state = kIdleState; + } +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.h new file mode 100644 index 00000000000..536a8ef3870 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2c_dma.h @@ -0,0 +1,146 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_DMA_H_ +#define _FSL_I2C_DMA_H_ + +#include "fsl_i2c.h" +#include "fsl_dma.h" + +/*! + * @addtogroup i2c_dma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C DMA driver version 2.0.3. */ +#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ +#define I2C_MAX_DMA_TRANSFER_COUNT 1024 + +/*! @brief I2C master dma handle typedef. */ +typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; + +/*! @brief I2C master dma transfer callback typedef. */ +typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, + i2c_master_dma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C master dma transfer structure. */ +struct _i2c_master_dma_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint32_t remainingSubaddr; + uint8_t subaddrBuf[4]; + dma_handle_t *dmaHandle; /*!< The DMA handler used. */ + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name I2C Block DMA Transfer Operation + * @{ + */ + +/*! + * @brief Init the I2C handle which is used in transcational functions + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param callback pointer to user callback function + * @param userData user param passed to the callback function + * @param dmaHandle DMA handle pointer + */ +void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *dmaHandle); + +/*! + * @brief Performs a master dma non-blocking transfer on the I2C bus + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param xfer pointer to transfer structure of i2c_master_transfer_t + * @retval kStatus_Success Sucessully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ +status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Get master transfer status during a dma non-blocking transfer + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a master dma non-blocking transfer in a early time + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + */ +void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ +#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.c new file mode 100644 index 00000000000..4f1f0c53496 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.c @@ -0,0 +1,836 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_i2s.h" +#include "fsl_flexcomm.h" +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" +#endif + +/* TODO - absent in device header files, should be there */ +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) + +/*! @brief I2S states. */ +enum _i2s_state +{ + kI2S_StateIdle = 0x0, /*!< Not performing transfer */ + kI2S_StateTx, /*!< Performing transmit */ + kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ + kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ + kI2S_StateRx, /*!< Performing receive */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void I2S_Config(I2S_Type *base, const i2s_config_t *config); +static void I2S_TxEnable(I2S_Type *base, bool enable); +static void I2S_RxEnable(I2S_Type *base, bool enable); +static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); + +/******************************************************************************* + * Code + ******************************************************************************/ + +void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) +{ + uint32_t cfg = 0U; + uint32_t trig = 0U; + + FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); + I2S_Config(base, config); + + /* Configure FIFO */ + + cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ + cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ + cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ + cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ + trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ + trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ + + base->FIFOCFG = cfg; + base->FIFOTRIG = trig; +} + +void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) +{ + uint32_t cfg = 0U; + uint32_t trig = 0U; + + FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); + I2S_Config(base, config); + + /* Configure FIFO */ + + cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ + cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ + cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ + trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ + trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ + + base->FIFOCFG = cfg; + base->FIFOTRIG = trig; +} + +void I2S_TxGetDefaultConfig(i2s_config_t *config) +{ + config->masterSlave = kI2S_MasterSlaveNormalMaster; + config->mode = kI2S_ModeI2sClassic; + config->rightLow = false; + config->leftJust = false; + config->pdmData = false; + config->sckPol = false; + config->wsPol = false; + config->divider = 1U; + config->oneChannel = false; + config->dataLength = 16U; + config->frameLength = 32U; + config->position = 0U; + config->watermark = 4U; + config->txEmptyZero = true; + config->pack48 = false; +} + +void I2S_RxGetDefaultConfig(i2s_config_t *config) +{ + config->masterSlave = kI2S_MasterSlaveNormalSlave; + config->mode = kI2S_ModeI2sClassic; + config->rightLow = false; + config->leftJust = false; + config->pdmData = false; + config->sckPol = false; + config->wsPol = false; + config->divider = 1U; + config->oneChannel = false; + config->dataLength = 16U; + config->frameLength = 32U; + config->position = 0U; + config->watermark = 4U; + config->txEmptyZero = false; + config->pack48 = false; +} + +static void I2S_Config(I2S_Type *base, const i2s_config_t *config) +{ + assert(config); + + uint32_t cfg1 = 0U; + uint32_t cfg2 = 0U; + + /* set master/slave configuration */ + cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); + + /* set I2S mode */ + cfg1 |= I2S_CFG1_MODE(config->mode); + + /* set right low (channel swap) */ + cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); + + /* set data justification */ + cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); + + /* set source to PDM dmic */ + cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); + + /* set SCLK polarity */ + cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); + + /* set WS polarity */ + cfg1 |= I2S_CFG1_WS_POL(config->wsPol); + + /* set mono mode */ + cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); + + /* set data length */ + cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U); + + /* set frame length */ + cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U); + + /* set data position of this channel pair within the frame */ + cfg2 |= I2S_CFG2_POSITION(config->position); + + /* write to registers */ + base->CFG1 = cfg1; + base->CFG2 = cfg2; + + /* set the clock divider */ + base->DIV = I2S_DIV_DIV(config->divider - 1U); +} + +void I2S_Deinit(I2S_Type *base) +{ + /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ +} + +static void I2S_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + I2S_EnableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); + I2S_Enable(base); + } + else + { + I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); + I2S_Disable(base); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + } +} + +static void I2S_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + I2S_EnableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); + I2S_Enable(base); + } + else + { + I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); + I2S_Disable(base); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + } +} + +static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) +{ + assert(transfer->data); + if (!transfer->data) + { + return kStatus_InvalidArgument; + } + + assert(transfer->dataSize > 0U); + if (transfer->dataSize <= 0U) + { + return kStatus_InvalidArgument; + } + + if (handle->dataLength == 4U) + { + /* No alignment and data length requirements */ + } + else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) + { + assert((((uint32_t)transfer->data) % 2U) == 0U); + if ((((uint32_t)transfer->data) % 2U) != 0U) + { + /* Data not 2-bytes aligned */ + return kStatus_InvalidArgument; + } + + assert((transfer->dataSize % 2U) == 0U); + if ((transfer->dataSize % 2U) != 0U) + { + /* Data not in pairs of left/right channel bytes */ + return kStatus_InvalidArgument; + } + } + else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) + { + assert((((uint32_t)transfer->data) % 4U) == 0U); + if ((((uint32_t)transfer->data) % 4U) != 0U) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + + assert((transfer->dataSize % 4U) == 0U); + if ((transfer->dataSize % 4U) != 0U) + { + /* Data lenght not multiply of 4 */ + return kStatus_InvalidArgument; + } + } + else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) + { + assert((transfer->dataSize % 6U) == 0U); + if ((transfer->dataSize % 6U) != 0U) + { + /* Data lenght not multiply of 6 */ + return kStatus_InvalidArgument; + } + + assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); + if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + } + else /* if (handle->dataLength >= 25U) */ + { + assert((((uint32_t)transfer->data) % 4U) == 0U); + if ((((uint32_t)transfer->data) % 4U) != 0U) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + + if (handle->oneChannel) + { + assert((transfer->dataSize % 4U) == 0U); + if ((transfer->dataSize % 4U) != 0U) + { + /* Data lenght not multiply of 4 */ + return kStatus_InvalidArgument; + } + } + else + { + assert((transfer->dataSize % 8U) == 0U); + if ((transfer->dataSize % 8U) != 0U) + { + /* Data lenght not multiply of 8 */ + return kStatus_InvalidArgument; + } + } + } + + return kStatus_Success; +} + +void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) +{ + assert(handle); + + /* Clear out the handle */ + memset(handle, 0U, sizeof(*handle)); + + /* Save callback and user data */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Remember some items set previously by configuration */ + handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); + handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); + handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; + handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); + + handle->useFifo48H = false; + + /* Register IRQ handling */ + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); +} + +status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) +{ + assert(handle); + if (!handle) + { + return kStatus_InvalidArgument; + } + + status_t result; + + result = I2S_ValidateBuffer(handle, &transfer); + if (result != kStatus_Success) + { + return result; + } + + if (handle->i2sQueue[handle->queueUser].dataSize) + { + /* Previously prepared buffers not processed yet */ + return kStatus_I2S_Busy; + } + + handle->state = kI2S_StateTx; + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); + I2S_TxEnable(base, true); + + return kStatus_Success; +} + +void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) +{ + assert(handle); + + /* Disable I2S operation and interrupts */ + I2S_TxEnable(base, false); + + /* Reset state */ + handle->state = kI2S_StateIdle; + + /* Clear transfer queue */ + memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); + handle->queueDriver = 0U; + handle->queueUser = 0U; +} + +void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) +{ + assert(handle); + + /* Clear out the handle */ + memset(handle, 0U, sizeof(*handle)); + + /* Save callback and user data */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Remember some items set previously by configuration */ + handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); + handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); + handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; + handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); + + handle->useFifo48H = false; + + /* Register IRQ handling */ + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); +} + +status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) +{ + assert(handle); + if (!handle) + { + return kStatus_InvalidArgument; + } + + status_t result; + + result = I2S_ValidateBuffer(handle, &transfer); + if (result != kStatus_Success) + { + return result; + } + + if (handle->i2sQueue[handle->queueUser].dataSize) + { + /* Previously prepared buffers not processed yet */ + return kStatus_I2S_Busy; + } + + handle->state = kI2S_StateRx; + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); + I2S_RxEnable(base, true); + + return kStatus_Success; +} + +void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) +{ + assert(handle); + + /* Disable I2S operation and interrupts */ + I2S_RxEnable(base, false); + + /* Reset state */ + handle->state = kI2S_StateIdle; + + /* Clear transfer queue */ + memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); + handle->queueDriver = 0U; + handle->queueUser = 0U; +} + +status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) +{ + assert(handle); + if (!handle) + { + return kStatus_InvalidArgument; + } + + assert(count); + if (!count) + { + return kStatus_InvalidArgument; + } + + if (handle->state == kI2S_StateIdle) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->transferCount; + + return kStatus_Success; +} + +status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) +{ + assert(handle); + if (!handle) + { + return kStatus_InvalidArgument; + } + + assert(count); + if (!count) + { + return kStatus_InvalidArgument; + } + + if (handle->state == kI2S_StateIdle) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->errorCount; + + return kStatus_Success; +} + +void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) +{ + uint32_t intstat = base->FIFOINTSTAT; + uint32_t data; + + if (intstat & I2S_FIFOINTSTAT_TXERR_MASK) + { + handle->errorCount++; + + /* Clear TX error interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); + } + + if (intstat & I2S_FIFOINTSTAT_TXLVL_MASK) + { + if (handle->state == kI2S_StateTx) + { + /* Send data */ + + while ((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) && + (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) + { + /* Write output data */ + if (handle->dataLength == 4U) + { + data = *(handle->i2sQueue[handle->queueDriver].data); + base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); + handle->i2sQueue[handle->queueDriver].data++; + handle->transferCount++; + handle->i2sQueue[handle->queueDriver].dataSize--; + } + else if (handle->dataLength <= 8U) + { + data = *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data); + base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + } + else if (handle->dataLength <= 16U) + { + base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + } + else if (handle->dataLength <= 24U) + { + if (handle->pack48) + { + if (handle->useFifo48H) + { + base->FIFOWR48H = *((volatile uint16_t *)(handle->i2sQueue[handle->queueDriver].data)); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + handle->useFifo48H = false; + } + else + { + base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + handle->useFifo48H = true; + } + } + else + { + data = (uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++)); + data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 8U; + data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 16U; + if (handle->useFifo48H) + { + base->FIFOWR48H = data; + handle->useFifo48H = false; + } + else + { + base->FIFOWR = data; + handle->useFifo48H = true; + } + handle->transferCount += 3U; + handle->i2sQueue[handle->queueDriver].dataSize -= 3U; + } + } + else /* if (handle->dataLength <= 32U) */ + { + base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + } + + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* Actual data buffer sent out, switch to a next one */ + handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; + + /* Notify user */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); + } + + /* Check if the next buffer contains anything to send */ + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* Everything has been written to FIFO */ + handle->state = kI2S_StateTxWaitToWriteDummyData; + break; + } + } + } + } + else if (handle->state == kI2S_StateTxWaitToWriteDummyData) + { + /* Write dummy data */ + if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) + { + if (handle->useFifo48H) + { + base->FIFOWR48H = 0U; + handle->useFifo48H = false; + } + else + { + base->FIFOWR = 0U; + base->FIFOWR48H = 0U; + } + } + else + { + base->FIFOWR = 0U; + } + + /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ + base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; + handle->state = kI2S_StateTxWaitForEmptyFifo; + } + else if (handle->state == kI2S_StateTxWaitForEmptyFifo) + { + /* FIFO, including additional dummy data, has been emptied now, + * all relevant data should have been output from peripheral */ + + /* Stop transfer */ + I2S_Disable(base); + I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + + /* Reset state */ + handle->state = kI2S_StateIdle; + + /* Notify user */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); + } + } + else + { + /* Do nothing */ + } + + /* Clear TX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); + } +} + +void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) +{ + uint32_t intstat = base->FIFOINTSTAT; + uint32_t data; + + if (intstat & I2S_FIFOINTSTAT_RXERR_MASK) + { + handle->errorCount++; + + /* Clear RX error interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); + } + + if (intstat & I2S_FIFOINTSTAT_RXLVL_MASK) + { + while ((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) && (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) + { + /* Read input data */ + if (handle->dataLength == 4U) + { + data = base->FIFORD; + *(handle->i2sQueue[handle->queueDriver].data) = ((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU); + handle->i2sQueue[handle->queueDriver].data++; + handle->transferCount++; + handle->i2sQueue[handle->queueDriver].dataSize--; + } + else if (handle->dataLength <= 8U) + { + data = base->FIFORD; + *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = ((data >> 8U) & 0xFF00U) | (data & 0xFFU); + handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + } + else if (handle->dataLength <= 16U) + { + data = base->FIFORD; + *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + } + else if (handle->dataLength <= 24U) + { + if (handle->pack48) + { + if (handle->useFifo48H) + { + data = base->FIFORD48H; + handle->useFifo48H = false; + + *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data; + handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + } + else + { + data = base->FIFORD; + handle->useFifo48H = true; + + *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + } + } + else + { + if (handle->useFifo48H) + { + data = base->FIFORD48H; + handle->useFifo48H = false; + } + else + { + data = base->FIFORD; + handle->useFifo48H = true; + } + + *(handle->i2sQueue[handle->queueDriver].data++) = data & 0xFFU; + *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 8U) & 0xFFU; + *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 16U) & 0xFFU; + handle->transferCount += 3U; + handle->i2sQueue[handle->queueDriver].dataSize -= 3U; + } + } + else /* if (handle->dataLength <= 32U) */ + { + data = base->FIFORD; + *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; + handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + } + + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* Actual data buffer filled with input data, switch to a next one */ + handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; + + /* Notify user */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); + } + + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* No other buffer prepared to receive data into */ + + /* Disable I2S operation and interrupts */ + I2S_Disable(base); + I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + + /* Reset state */ + handle->state = kI2S_StateIdle; + + /* Notify user */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); + } + + /* Clear RX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); + + return; + } + } + } + + /* Clear RX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); + } +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.h new file mode 100644 index 00000000000..67d6b1bb124 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s.h @@ -0,0 +1,490 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2S_H_ +#define _FSL_I2S_H_ + +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i2s_driver + * @{ + */ + +/*! @file */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2S driver version 2.0.1. + * + * Current version: 2.0.1 + * + * Change log: + * - Version 2.0.1 + * - Unify component full name to FLEXCOMM I2S(DMA) Driver + * - Version 2.0.0 + * - initial version + */ +#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +#ifndef I2S_NUM_BUFFERS + +/*! @brief Number of buffers . */ +#define I2S_NUM_BUFFERS (4) + +#endif + +/*! @brief I2S status codes. */ +enum _i2s_status +{ + kStatus_I2S_BufferComplete = + MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ + kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ + kStatus_I2S_Busy = + MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ +}; + +/*! + * @brief I2S flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +typedef enum _i2s_flags +{ + kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ + kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ + kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ + kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ +} i2s_flags_t; + +/*! @brief Master / slave mode. */ +typedef enum _i2s_master_slave +{ + kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ + kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ + kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ + kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ +} i2s_master_slave_t; + +/*! @brief I2S mode. */ +typedef enum _i2s_mode +{ + kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ + kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ + kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ + kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ +} i2s_mode_t; + +/*! @brief I2S configuration structure. */ +typedef struct _i2s_config +{ + i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ + i2s_mode_t mode; /*!< I2S mode */ + bool rightLow; /*!< Right channel data in low portion of FIFO */ + bool leftJust; /*!< Left justify data in FIFO */ + bool pdmData; /*!< Data source is the D-Mic subsystem */ + bool sckPol; /*!< SCK polarity */ + bool wsPol; /*!< WS polarity */ + uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ + bool oneChannel; /*!< true mono, false stereo */ + uint8_t dataLength; /*!< Data length (4 - 32) */ + uint16_t frameLength; /*!< Frame width (4 - 512) */ + uint16_t position; /*!< Data position in the frame */ + uint8_t watermark; /*!< FIFO trigger level */ + bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ + bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit + values) */ +} i2s_config_t; + +/*! @brief Buffer to transfer from or receive audio data into. */ +typedef struct _i2s_transfer +{ + volatile uint8_t *data; /*!< Pointer to data buffer. */ + volatile size_t dataSize; /*!< Buffer size in bytes. */ +} i2s_transfer_t; + +/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ +typedef struct _i2s_handle i2s_handle_t; + +/*! + * @brief Callback function invoked from transactional API + * on completion of a single buffer transfer. + * + * @param base I2S base pointer. + * @param handle pointer to I2S transaction. + * @param completionStatus status of the transaction. + * @param userData optional pointer to user arguments data. + */ +typedef void (*i2s_transfer_callback_t)(I2S_Type *base, + i2s_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! @brief Members not to be accessed / modified outside of the driver. */ +struct _i2s_handle +{ + uint32_t state; /*!< State of transfer */ + i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ + void *userData; /*!< Application data passed to callback */ + bool oneChannel; /*!< true mono, false stereo */ + uint8_t dataLength; /*!< Data length (4 - 32) */ + bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit + values) */ + bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ + volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ + volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ + volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ + volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ + volatile uint32_t transferCount; /*!< Number of bytes transferred */ + volatile uint8_t watermark; /*!< FIFO trigger level */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S transmission using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_TxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the I2S driver. + * + * @param base I2S base pointer. + * @param config pointer to I2S configuration structure. + */ +void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); + +/*! + * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S receive using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_RxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the I2S driver. + * + * @param base I2S base pointer. + * @param config pointer to I2S configuration structure. + */ +void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); + +/*! + * @brief Sets the I2S Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_TxInit(). + * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified + * before calling I2S_TxInit(). + * Example: + @code + i2s_config_t config; + I2S_TxGetDefaultConfig(&config); + @endcode + * + * Default values: + * @code + * config->masterSlave = kI2S_MasterSlaveNormalMaster; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = true; + * config->pack48 = false; + * @endcode + * + * @param config pointer to I2S configuration structure. + */ +void I2S_TxGetDefaultConfig(i2s_config_t *config); + +/*! + * @brief Sets the I2S Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_RxInit(). + * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified + * before calling I2S_RxInit(). + * Example: + @code + i2s_config_t config; + I2S_RxGetDefaultConfig(&config); + @endcode + * + * Default values: + * @code + * config->masterSlave = kI2S_MasterSlaveNormalSlave; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = false; + * config->pack48 = false; + * @endcode + * + * @param config pointer to I2S configuration structure. + */ +void I2S_RxGetDefaultConfig(i2s_config_t *config); + +/*! + * @brief De-initializes the I2S peripheral. + * + * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit + * or I2S_RxInit is called to enable the clock. + * + * @param base I2S base pointer. + */ +void I2S_Deinit(I2S_Type *base); + +/*! @} */ + +/*! + * @name Non-blocking API + * @{ + */ + +/*! + * @brief Initializes handle for transfer of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); + +/*! + * @brief Begins or queue sending of the given data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts sending of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Initializes handle for reception of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); + +/*! + * @brief Begins or queue reception of data into given buffer. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. + */ +status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts receiving of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param[out] count number of bytes transferred so far by the non-blocking transaction. + * + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); + +/*! + * @brief Returns number of buffer underruns or overruns. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. + * + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); + +/*! @} */ + +/*! + * @name Enable / disable + * @{ + */ + +/*! + * @brief Enables I2S operation. + * + * @param base I2S base pointer. + */ +static inline void I2S_Enable(I2S_Type *base) +{ + base->CFG1 |= I2S_CFG1_MAINENABLE(1U); +} + +/*! + * @brief Disables I2S operation. + * + * @param base I2S base pointer. + */ +static inline void I2S_Disable(I2S_Type *base) +{ + base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2S FIFO interrupts. + * + * @param base I2S base pointer. + * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) +{ + base->FIFOINTENSET = interruptMask; +} + +/*! + * @brief Disables I2S FIFO interrupts. + * + * @param base I2S base pointer. + * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) +{ + base->FIFOINTENCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I2S FIFO interrupts. + * + * @param base I2S base pointer. + * + * @return A bitmask composed of #i2s_flags_t enumerators OR'd together + * to indicate the set of enabled interrupts. + */ +static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) +{ + return base->FIFOINTENSET; +} + +/*! + * @brief Invoked from interrupt handler when transmit FIFO level decreases. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Invoked from interrupt handler when receive FIFO level decreases. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); + +/*! @} */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2S_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.c new file mode 100644 index 00000000000..04bf7f0c516 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.c @@ -0,0 +1,636 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dma.h" +#include "fsl_i2s_dma.h" +#include "fsl_flexcomm.h" +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" +#endif + + +#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) +#define DMA_DESCRIPTORS (2U) + +/*i2sQueue[handle->queueUser].dataSize) + { + /* Previously prepared buffers not processed yet, reject request */ + return kStatus_I2S_Busy; + } + + /* Enqueue data */ + privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; + privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + return kStatus_Success; +} + +static uint32_t I2S_GetInstance(I2S_Type *base) +{ + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) + { + if ((uint32_t)base == s_I2sBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0U; +} + +static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) +{ + DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); +} + +static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) +{ + if (handle->state != kI2S_DmaStateIdle) + { + DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); + } +} + +void I2S_TxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData) +{ + assert(handle); + assert(dmaHandle); + + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + + memset(handle, 0U, sizeof(*handle)); + handle->state = kI2S_DmaStateIdle; + handle->dmaHandle = dmaHandle; + handle->completionCallback = callback; + handle->userData = userData; + + memset(privateHandle, 0U, sizeof(*privateHandle)); + privateHandle->base = base; + privateHandle->handle = handle; + + DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); +} + +status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) +{ + status_t status; + + I2S_DisableDMAInterrupts(handle); + + /* Enqueue transfer buffer */ + status = I2S_EnqueueUserBuffer(base, handle, transfer); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + + /* Initialize DMA transfer */ + if (handle->state == kI2S_DmaStateIdle) + { + handle->state = kI2S_DmaStateTx; + status = I2S_StartTransferDMA(base, handle); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + } + + I2S_AddTransferDMA(base, handle); + I2S_EnableDMAInterrupts(handle); + + return kStatus_Success; +} + +void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + assert(handle); + assert(handle->dmaHandle); + + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + + I2S_DisableDMAInterrupts(handle); + + /* Abort operation */ + DMA_AbortTransfer(handle->dmaHandle); + + if (handle->state == kI2S_DmaStateTx) + { + /* Wait until all transmitted data get out of FIFO */ + while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) + { + } + /* The last piece of valid data can be still being transmitted from I2S at this moment */ + + /* Write additional data to FIFO */ + base->FIFOWR = 0U; + while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) + { + } + /* At this moment the additional data are out of FIFO, starting being transmitted. + * This means the preceding valid data has been just transmitted and we can stop I2S. */ + I2S_TxEnableDMA(base, false); + } + else + { + I2S_RxEnableDMA(base, false); + } + + I2S_Disable(base); + + /* Reset state */ + handle->state = kI2S_DmaStateIdle; + + /* Clear transfer queue */ + memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue)); + handle->queueDriver = 0U; + handle->queueUser = 0U; + + /* Clear internal state */ + memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue)); + memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes)); + privateHandle->enqueuedBytesStart = 0U; + privateHandle->enqueuedBytesEnd = 0U; + privateHandle->dmaDescriptorsUsed = 0U; + privateHandle->descriptor = 0U; + privateHandle->queueDescriptor = 0U; + privateHandle->intA = false; +} + +void I2S_RxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData) +{ + I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); +} + +status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) +{ + status_t status; + + I2S_DisableDMAInterrupts(handle); + + /* Enqueue transfer buffer */ + status = I2S_EnqueueUserBuffer(base, handle, transfer); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + + /* Initialize DMA transfer */ + if (handle->state == kI2S_DmaStateIdle) + { + handle->state = kI2S_DmaStateRx; + status = I2S_StartTransferDMA(base, handle); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + } + + I2S_AddTransferDMA(base, handle); + I2S_EnableDMAInterrupts(handle); + + return kStatus_Success; +} + +static void I2S_TxEnableDMA(I2S_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + } +} + +static void I2S_RxEnableDMA(I2S_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + } +} + +static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) +{ + assert(transfer); + + uint16_t transferBytes; + + if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES)) + { + transferBytes = DMA_MAX_TRANSFER_BYTES; + } + else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) + { + transferBytes = transfer->dataSize / 2U; + if ((transferBytes % 4U) != 0U) + { + transferBytes -= (transferBytes % 4U); + } + } + else + { + transferBytes = transfer->dataSize; + } + + return transferBytes; +} + +static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + status_t status; + dma_transfer_config_t xferConfig = {0}; + i2s_dma_private_handle_t *privateHandle; + volatile i2s_transfer_t *transfer; + uint16_t transferBytes; + uint32_t instance; + int i; + dma_descriptor_t *descriptor; + dma_descriptor_t *nextDescriptor; + dma_xfercfg_t xfercfg; + + instance = I2S_GetInstance(base); + privateHandle = &(s_DmaPrivateHandle[instance]); + transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); + + transferBytes = I2S_GetTransferBytes(transfer); + + /* Prepare transfer of data via initial DMA transfer descriptor */ + DMA_PrepareTransfer( + &xferConfig, (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)(&(base->FIFORD))), + (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)(&(base->FIFOWR)) : (uint32_t)transfer->data), sizeof(uint32_t), + transferBytes, (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory, + (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); + + /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ + privateHandle->dmaDescriptorsUsed = 1U; + privateHandle->intA = false; + + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; + privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; + + transfer->dataSize -= transferBytes; + transfer->data += transferBytes; + + if (transfer->dataSize == 0U) + { + transfer->data = NULL; + privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; + } + + /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes */ + for (i = 0; i < DMA_DESCRIPTORS; i++) + { + descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]); + nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)]); + + xfercfg.valid = true; + xfercfg.reload = true; + xfercfg.swtrig = false; + xfercfg.clrtrig = false; + xfercfg.intA = false; + xfercfg.intB = false; + xfercfg.byteWidth = sizeof(uint32_t); + xfercfg.srcInc = 0U; + xfercfg.dstInc = 0U; + xfercfg.transferCount = 8U; + + DMA_CreateDescriptor(descriptor, &xfercfg, + ((handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)(uint32_t)(&(base->FIFORD))), + ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)(&(base->FIFOWR)) : (void *)&s_DummyBufferRx), + (void *)nextDescriptor); + } + + /* Submit and start initial DMA transfer */ + + if (handle->state == kI2S_DmaStateTx) + { + I2S_TxEnableDMA(base, true); + } + else + { + I2S_RxEnableDMA(base, true); + } + + status = DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + if (status != kStatus_Success) + { + return status; + } + + DMA_StartTransfer(handle->dmaHandle); + + I2S_Enable(base); + return kStatus_Success; +} + +static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + dma_xfercfg_t xfercfg; + volatile i2s_transfer_t *transfer; + uint16_t transferBytes; + uint32_t instance; + i2s_dma_private_handle_t *privateHandle; + dma_descriptor_t *descriptor; + dma_descriptor_t *nextDescriptor; + uint32_t srcAddr = 0, destAddr = 0; + + instance = I2S_GetInstance(base); + privateHandle = &(s_DmaPrivateHandle[instance]); + + while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) + { + transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); + + if (transfer->dataSize == 0U) + { + /* Nothing to be added */ + return; + } + + /* Determine currently configured descriptor and the other which it will link to */ + descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); + privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; + nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); + + transferBytes = I2S_GetTransferBytes(transfer); + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; + privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; + + /* Configure descriptor */ + + xfercfg.valid = true; + xfercfg.reload = true; + xfercfg.swtrig = false; + xfercfg.clrtrig = false; + xfercfg.intA = privateHandle->intA; + xfercfg.intB = !privateHandle->intA; + xfercfg.byteWidth = sizeof(uint32_t); + xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U; + xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U; + xfercfg.transferCount = transferBytes / sizeof(uint32_t); + srcAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)&(base->FIFORD)); + destAddr = ((handle->state == kI2S_DmaStateTx) ? (uint32_t)&(base->FIFOWR) : (uint32_t)transfer->data); + + DMA_CreateDescriptor(descriptor, &xfercfg, (void *)srcAddr, (void *)destAddr, (void *)nextDescriptor); + + /* Advance internal state */ + + privateHandle->dmaDescriptorsUsed++; + privateHandle->intA = !privateHandle->intA; + + transfer->dataSize -= transferBytes; + transfer->data += transferBytes; + if (transfer->dataSize == 0U) + { + transfer->data = NULL; + privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; + } + } +} + +void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) +{ + i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; + i2s_dma_handle_t *i2sHandle = privateHandle->handle; + I2S_Type *base = privateHandle->base; + + if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle)) + { + return; + } + + if (privateHandle->dmaDescriptorsUsed > 0U) + { + /* Finished descriptor, decrease amount of data to be processed */ + + i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -= + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; + i2sHandle->i2sQueue[i2sHandle->queueDriver].data += + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; + privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; + + privateHandle->dmaDescriptorsUsed--; + + if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) + { + /* Entire user buffer sent or received - advance to next one */ + i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL; + i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS; + + /* Notify user about buffer completion */ + if (i2sHandle->completionCallback) + { + (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); + } + } + } + + if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) + { + /* All user buffers processed */ + I2S_TransferAbortDMA(base, i2sHandle); + + /* Notify user about completion of the final buffer */ + if (i2sHandle->completionCallback) + { + (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_Done, i2sHandle->userData); + } + } + else + { + /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ + I2S_AddTransferDMA(base, i2sHandle); + } +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.h new file mode 100644 index 00000000000..05d69147290 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_i2s_dma.h @@ -0,0 +1,187 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2S_DMA_H_ +#define _FSL_I2S_DMA_H_ + +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +#include "fsl_dma.h" +#include "fsl_i2s.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i2s_dma_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2S DMA driver version 2.0.1. */ +#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Members not to be accessed / modified outside of the driver. */ +typedef struct _i2s_dma_handle i2s_dma_handle_t; + +/*! + * @brief Callback function invoked from DMA API on completion. + * + * @param base I2S base pointer. + * @param handle pointer to I2S transaction. + * @param completionStatus status of the transaction. + * @param userData optional pointer to user arguments data. + */ +typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, + i2s_dma_handle_t *handle, + status_t completionStatus, + void *userData); + +struct _i2s_dma_handle +{ + uint32_t state; /*!< Internal state of I2S DMA transfer */ + i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ + void *userData; /*!< Application data passed to callback */ + dma_handle_t *dmaHandle; /*!< DMA handle */ + volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ + volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ + volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! @} */ + +/*! + * @name DMA API + * @{ + */ + +/*! + * @brief Initializes handle for transfer of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param dmaHandle pointer to dma handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Begins or queue sending of the given data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts transfer of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); + +/*! + * @brief Initializes handle for reception of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param dmaHandle pointer to dma handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Begins or queue reception of data into given buffer. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers + * which are not full. + */ +status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Invoked from DMA interrupt handler. + * + * @param handle pointer to DMA handle structure. + * @param userData argument for user callback. + * @param transferDone if transfer was done. + * @param tcds + */ +void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @} */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.c new file mode 100644 index 00000000000..d671da93fe8 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.c @@ -0,0 +1,108 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_inputmux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux" +#endif + + +/******************************************************************************* + * Code + ******************************************************************************/ + +void INPUTMUX_Init(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_EnableClock(kCLOCK_Sct); + CLOCK_EnableClock(kCLOCK_Dma); +#else + CLOCK_EnableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) +{ + uint32_t pmux_id; + uint32_t output_id; + + /* extract pmux to be used */ + pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; + /* extract function number */ + output_id = ((uint32_t)(connection)) & 0xffffU; + /* programm signal */ + *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id; +} + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) +{ + uint32_t ena_id; + uint32_t bit_offset; + + /* extract enable register to be used */ + ena_id = ((uint32_t)(signal)) >> ENA_SHIFT; + /* extract enable bit offset */ + bit_offset = ((uint32_t)(signal)) & 0xfU; + /* set signal */ + if (enable) + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1U << bit_offset); + } + else + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1U << bit_offset); + } +} +#endif + +void INPUTMUX_Deinit(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_DisableClock(kCLOCK_Sct); + CLOCK_DisableClock(kCLOCK_Dma); +#else + CLOCK_DisableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.h new file mode 100644 index 00000000000..cdfda5bd6a0 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux.h @@ -0,0 +1,123 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_INPUTMUX_H_ +#define _FSL_INPUTMUX_H_ + +#include "fsl_inputmux_connections.h" +#include "fsl_common.h" + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! @file */ +/*! @file fsl_inputmux_connections.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Group interrupt driver version for SDK */ +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + /*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base); + +/*! + * @brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param index Destination peripheral to attach the signal to. + * @param connection Selects connection. + * + * @retval None. +*/ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * @brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param signal Enable signal register id and bit offset. + * @param enable Selects enable or disable. + * + * @retval None. +*/ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); +#endif + +/*! + * @brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux_connections.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux_connections.h new file mode 100644 index 00000000000..23e9cfe9dc2 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_inputmux_connections.h @@ -0,0 +1,183 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016, NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define PINTSEL_PMUX_ID 0xC0U +#define DMA_TRIG0_PMUX_ID 0xE0U +#define DMA_OTRIG_PMUX_ID 0x160U +#define FREQMEAS_PMUX_ID 0x180U +#define PMUX_SHIFT 20U + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< Frequency measure. */ + kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_WdtOscToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_MainClkToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToFreqmeas = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToFreqmeas = 7U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToFreqmeas = 8U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + /*!< Pin Interrupt. */ + kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + /*!< DMA ITRIG. */ + kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_ADC0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + /*!< DMA OTRIG. */ + kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaChannel19_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), +} inputmux_connection_t; + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_iocon.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_iocon.h new file mode 100644 index 00000000000..a577a7eece8 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_iocon.h @@ -0,0 +1,207 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_IOCON_H_ +#define _FSL_IOCON_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_iocon + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" +#endif + + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOCON driver version 2.0.0. */ +#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/** + * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format + */ +typedef struct _iocon_group +{ + uint32_t port : 8; /* Pin port */ + uint32_t pin : 8; /* Pin number */ + uint32_t ionumber : 8; /* IO number */ + uint32_t modefunc : 16; /* Function and mode */ +} iocon_group_t; + +/** + * @brief IOCON function and mode selection definitions + * @note See the User Manual for specific modes and functions supported by the various pins. + */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */ +#define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */ +#define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << 6) /*!< I2C Slew Rate Control */ +#define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */ +#define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */ +#define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */ +#define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */ +#define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */ +#define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */ +#define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */ +#define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */ +#define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */ +#define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */ +#define IOCON_CLKDIV(div) \ + ((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#else +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ +#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ +#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << 5) /*!< I2C Slew Rate Control */ +#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */ +#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ +#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ +#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ +#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ +#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ +#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ +#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */ +#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ +#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ +#define IOCON_CLKDIV(div) \ + ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif +#if defined(__cplusplus) +extern "C" { +#endif + +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param ionumber : GPIO number to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) +{ + base->PIO[ionumber] = modefunc; +} +#else +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) +{ + base->PIO[port][pin] = modefunc; +} +#endif + +/** + * @brief Set all I/O Control pin muxing + * @param base : The base of IOCON peripheral on the chip + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) +{ + uint32_t i; + + for (i = 0; i < arrayLength; i++) + { +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) + IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); +#else + IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); +#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ + } +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mailbox.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mailbox.h new file mode 100644 index 00000000000..df10337c5dc --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mailbox.h @@ -0,0 +1,210 @@ +/* + * The Clear BSD License + * Copyright(C) NXP Semiconductors, 2014 + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_MAILBOX_H_ +#define _FSL_MAILBOX_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mailbox + * @{ + */ + +/*! @file */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mailbox" +#endif + + +/*! @name Driver version */ +/*@{*/ +/*! @brief MAILBOX driver version 2.0.0. */ +#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief CPU ID. + */ +typedef enum _mailbox_cpu_id +{ + kMAILBOX_CM0Plus = 0, + kMAILBOX_CM4 +} mailbox_cpu_id_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @name MAILBOX initialization + * @{ + */ + +/*! + * @brief Initializes the MAILBOX module. + * + * This function enables the MAILBOX clock only. + * + * @param base MAILBOX peripheral base address. + */ +static inline void MAILBOX_Init(MAILBOX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Mailbox); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief De-initializes the MAILBOX module. + * + * This function disables the MAILBOX clock only. + * + * @param base MAILBOX peripheral base address. + */ +static inline void MAILBOX_Deinit(MAILBOX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Mailbox); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/* @} */ + +/*! + * @brief Set data value in the mailbox based on the CPU ID. + * + * @param base MAILBOX peripheral base address. + * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. + * @param mboxData Data to send in the mailbox. + * + * @note Sets a data value to send via the MAILBOX to the other core. + */ +static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData) +{ + assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); + base->MBOXIRQ[cpu_id].IRQ = mboxData; +} + +/*! + * @brief Get data in the mailbox based on the CPU ID. + * + * @param base MAILBOX peripheral base address. + * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. + * + * @return Current mailbox data. + */ +static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id) +{ + assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); + return base->MBOXIRQ[cpu_id].IRQ; +} + +/*! + * @brief Set data bits in the mailbox based on the CPU ID. + * + * @param base MAILBOX peripheral base address. + * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. + * @param mboxSetBits Data bits to set in the mailbox. + * + * @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will + * do nothing. Only sets bits selected with a 1 in it's bit position. + */ +static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits) +{ + assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); + base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits; +} + +/*! + * @brief Clear data bits in the mailbox based on the CPU ID. + * + * @param base MAILBOX peripheral base address. + * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4. + * @param mboxClrBits Data bits to clear in the mailbox. + * + * @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will + * do nothing. Only clears bits selected with a 1 in it's bit position. + */ +static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits) +{ + assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); + base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits; +} + +/*! + * @brief Get MUTEX state and lock mutex + * + * @param base MAILBOX peripheral base address. + * + * @return See note + * + * @note Returns '1' if the mutex was taken or '0' if another resources has the + * mutex locked. Once a mutex is taken, it can be returned with the MAILBOX_SetMutex() + * function. + */ +static inline uint32_t MAILBOX_GetMutex(MAILBOX_Type *base) +{ + return (base->MUTEX & MAILBOX_MUTEX_EX_MASK); +} + +/*! + * @brief Set MUTEX state + * + * @param base MAILBOX peripheral base address. + * + * @note Sets mutex state to '1' and allows other resources to get the mutex. + */ +static inline void MAILBOX_SetMutex(MAILBOX_Type *base) +{ + base->MUTEX = MAILBOX_MUTEX_EX_MASK; +} + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /* _FSL_MAILBOX_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.c new file mode 100644 index 00000000000..1aa5f00cd0c --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.c @@ -0,0 +1,145 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_mrt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mrt" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Multi-Rate timer peripheral base address + * + * @return The MRT instance + */ +static uint32_t MRT_GetInstance(MRT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to MRT bases for each instance. */ +static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to MRT clocks for each instance. */ +static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; +#else +/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t MRT_GetInstance(MRT_Type *base) +{ + uint32_t instance; + uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < mrtArrayCount; instance++) + { + if (s_mrtBases[instance] == base) + { + break; + } + } + + assert(instance < mrtArrayCount); + + return instance; +} + +void MRT_Init(MRT_Type *base, const mrt_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the MRT clock */ + CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module */ + RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); + +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) + /* Set timer operating mode */ + base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); +#endif +} + +void MRT_Deinit(MRT_Type *base) +{ + /* Stop all the timers */ + MRT_StopTimer(base, kMRT_Channel_0); + MRT_StopTimer(base, kMRT_Channel_1); +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) + MRT_StopTimer(base, kMRT_Channel_2); +#endif +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) + MRT_StopTimer(base, kMRT_Channel_3); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the MRT clock*/ + CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t newValue = count; + if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad)) + { + /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ + newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; + } + + /* Update the timer interval value */ + base->CHANNEL[channel].INTVAL = newValue; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.h new file mode 100644 index 00000000000..c435e97e1fa --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_mrt.h @@ -0,0 +1,391 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_MRT_H_ +#define _FSL_MRT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mrt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of MRT channels */ +typedef enum _mrt_chnl +{ + kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ + kMRT_Channel_1, /*!< MRT channel number 1 */ + kMRT_Channel_2, /*!< MRT channel number 2 */ + kMRT_Channel_3 /*!< MRT channel number 3 */ +} mrt_chnl_t; + +/*! @brief List of MRT timer modes */ +typedef enum _mrt_timer_mode +{ + kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ + kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ + kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ +} mrt_timer_mode_t; + +/*! @brief List of MRT interrupts */ +typedef enum _mrt_interrupt_enable +{ + kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ +} mrt_interrupt_enable_t; + +/*! @brief List of MRT status flags */ +typedef enum _mrt_status_flags +{ + kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ + kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ +} mrt_status_flags_t; + +/*! + * @brief MRT configuration structure + * + * This structure holds the configuration settings for the MRT peripheral. To initialize this + * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _mrt_config +{ + bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ +} mrt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the MRT clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the MRT driver. + * + * @param base Multi-Rate timer peripheral base address + * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. + */ +void MRT_Init(MRT_Type *base, const mrt_config_t *config); + +/*! + * @brief Gate the MRT clock + * + * @param base Multi-Rate timer peripheral base address + */ +void MRT_Deinit(MRT_Type *base); + +/*! + * @brief Fill in the MRT config struct with the default settings + * + * The default values are: + * @code + * config->enableMultiTask = false; + * @endcode + * @param config Pointer to user's MRT config structure. + */ +static inline void MRT_GetDefaultConfig(mrt_config_t *config) +{ + assert(config); +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) + /* Use hardware status operating mode */ + config->enableMultiTask = false; +#endif +} + +/*! + * @brief Sets up an MRT channel mode. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Channel that is being configured. + * @param mode Timer mode to use for the channel. + */ +static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t reg = base->CHANNEL[channel].CTRL; + + /* Clear old value */ + reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; + /* Add the new mode */ + reg |= mode; + + base->CHANNEL[channel].CTRL = reg; +} + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the MRT interrupt. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CTRL |= mask; +} + +/*! + * @brief Disables the selected MRT interrupt. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CTRL &= ~mask; +} + +/*! + * @brief Gets the enabled MRT interrupts. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the MRT status flags + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::mrt_status_flags_t + */ +static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); +} + +/*! + * @brief Clears the MRT status flags. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::mrt_status_flags_t + */ +static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Used to update the timer period in units of count. + * + * The new value will be immediately loaded or will be loaded at the end of the current time + * interval. For one-shot interrupt mode the new value will be immediately loaded. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + * @param immediateLoad true: Load the new value immediately into the TIMER register; + * false: Load the new value at the end of current timer interval + */ +void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return base->CHANNEL[channel].TIMER; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, counts down to 0 and + * depending on the timer mode it will either load the respective start value again or stop. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + * @param count Timer period in units of ticks + */ +static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + /* Write the timer interval value */ + base->CHANNEL[channel].INTVAL = count; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops the timer from counting. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + */ +static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + /* Stop the timer immediately */ + base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; +} + +/*! @}*/ + +/*! + * @name Get & release channel + * @{ + */ + +/*! + * @brief Find the available channel. + * + * This function returns the lowest available channel number. + * + * @param base Multi-Rate timer peripheral base address + */ +static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) +{ + return base->IDLE_CH; +} + +#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) +/*! + * @brief Release the channel when the timer is using the multi-task mode. + * + * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for + * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as + * long as it is needed and release it by calling this function. This removes the need to ask for + * an available channel for every use. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + */ +static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) +{ + assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t reg = base->CHANNEL[channel].STAT; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; + reg |= MRT_CHANNEL_STAT_INUSE_MASK; + + base->CHANNEL[channel].STAT = reg; +} +#endif + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_MRT_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.c new file mode 100644 index 00000000000..ad3a4aaaceb --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.c @@ -0,0 +1,541 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pint.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pint" +#endif + + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; + +/*! @brief Callback function array for PINT(s). */ +static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +void PINT_Init(PINT_Type *base) +{ + uint32_t i; + uint32_t pmcfg; + + assert(base); + + pmcfg = 0; + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + + /* Disable all bit slices */ + for (i = 0; i < PINT_PIN_INT_COUNT; i++) + { + pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) + /* Enable the peripheral clock */ + CLOCK_EnableClock(kCLOCK_GpioInt); + + /* Reset the peripheral */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) + /* Enable the peripheral clock */ + CLOCK_EnableClock(kCLOCK_Gpio0); + + /* Reset the peripheral */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#else + /* Enable the peripheral clock */ + CLOCK_EnableClock(kCLOCK_Pint); + + /* Reset the peripheral */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE && FSL_FEATURE_CLOCK_HAS_NO_GPIOINT_CLOCK_SOURCE*/ + + /* Disable all pattern match bit slices */ + base->PMCFG = pmcfg; +} + +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) +{ + assert(base); + + /* Clear Rise and Fall flags first */ + PINT_PinInterruptClrRiseFlag(base, intr); + PINT_PinInterruptClrFallFlag(base, intr); + + /* select level or edge sensitive */ + base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U); + + /* enable rising or level interrupt */ + if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) + { + base->SIENR = 1U << intr; + } + else + { + base->CIENR = 1U << intr; + } + + /* Enable falling or select high level */ + if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + { + base->SIENF = 1U << intr; + } + else + { + base->CIENF = 1U << intr; + } + + s_pintCallback[intr] = callback; +} + +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) +{ + uint32_t mask; + bool level; + + assert(base); + + *enable = kPINT_PinIntEnableNone; + level = false; + + mask = 1U << pintr; + if (base->ISEL & mask) + { + /* Pin interrupt is level sensitive */ + level = true; + } + + if (base->IENR & mask) + { + if (level) + { + /* Level interrupt is enabled */ + *enable = kPINT_PinIntEnableLowLevel; + } + else + { + /* Rising edge interrupt */ + *enable = kPINT_PinIntEnableRiseEdge; + } + } + + if (base->IENF & mask) + { + if (level) + { + /* Level interrupt is active high */ + *enable = kPINT_PinIntEnableHighLevel; + } + else + { + /* Either falling or both edge */ + if (*enable == kPINT_PinIntEnableRiseEdge) + { + /* Rising and faling edge */ + *enable = kPINT_PinIntEnableBothEdges; + } + else + { + /* Falling edge */ + *enable = kPINT_PinIntEnableFallEdge; + } + } + } + + *callback = s_pintCallback[pintr]; +} + +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t pmcfg; + + assert(base); + + src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U); + cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U); + + /* Input source selection for selected bit slice */ + base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift); + + /* Bit slice configuration */ + pmcfg = base->PMCFG; + pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift); + + /* If end point is true, enable the bits */ + if (bslice != 7U) + { + if (cfg->end_point) + { + pmcfg |= (0x1U << bslice); + } + else + { + pmcfg &= ~(0x1U << bslice); + } + } + + base->PMCFG = pmcfg; + + /* Save callback pointer */ + s_pintCallback[bslice] = cfg->callback; +} + +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + + assert(base); + + src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U); + cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U); + + cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift); + cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift); + + if (bslice == 7U) + { + cfg->end_point = true; + } + else + { + cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice; + } + cfg->callback = s_pintCallback[bslice]; +} + +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) +{ + uint32_t pmctrl; + uint32_t pmstatus; + uint32_t pmsrc; + + pmctrl = PINT->PMCTRL; + pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; + if (pmstatus) + { + /* Reset Pattern match engine detection logic */ + pmsrc = base->PMSRC; + base->PMSRC = pmsrc; + } + return (pmstatus); +} + +void PINT_EnableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + PINT_PinInterruptClrStatusAll(base); + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + EnableIRQ(s_pintIRQ[i]); + } +} + +void PINT_DisableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + DisableIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + } +} + +void PINT_Deinit(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + /* Cleanup */ + PINT_DisableCallback(base); + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) + /* Reset the peripheral */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); + + /* Disable the peripheral clock */ + CLOCK_DisableClock(kCLOCK_GpioInt); +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) + /* Reset the peripheral */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); + + /* Disable the peripheral clock */ + CLOCK_DisableClock(kCLOCK_Gpio0); +#else + /* Reset the peripheral */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); + + /* Disable the peripheral clock */ + CLOCK_DisableClock(kCLOCK_Pint); +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ +} + +/* IRQ handler functions overloading weak symbols in the startup */ +void PIN_INT0_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt0] != NULL) + { + s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); + } + if((PINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +void PIN_INT1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt1] != NULL) + { + s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); + } + if((PINT->ISEL & 0x2U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) +void PIN_INT2_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt2] != NULL) + { + s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); + } + if((PINT->ISEL & 0x4U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) +void PIN_INT3_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt3] != NULL) + { + s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); + } + if((PINT->ISEL & 0x8U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) +void PIN_INT4_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt4] != NULL) + { + s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); + } + if((PINT->ISEL & 0x10U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT5_DAC1_IRQHandler(void) +#else +void PIN_INT5_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt5] != NULL) + { + s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); + } + if((PINT->ISEL & 0x20U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT6_USART3_IRQHandler(void) +#else +void PIN_INT6_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt6] != NULL) + { + s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); + } + if((PINT->ISEL & 0x40U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT7_USART4_IRQHandler(void) +#else +void PIN_INT7_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt7] != NULL) + { + s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); + } + if((PINT->ISEL & 0x80U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.h new file mode 100644 index 00000000000..9733f836b71 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_pint.h @@ -0,0 +1,572 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_PINT_H_ +#define _FSL_PINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ +/*@}*/ + +/* Number of interrupt line supported by PINT */ +#define PINT_PIN_INT_COUNT 8U + +/* Number of input sources supported by PINT */ +#define PINT_INPUT_COUNT 8U + +/* PININT Bit slice source register bits */ +#define PININT_BITSLICE_SRC_START 8U +#define PININT_BITSLICE_SRC_MASK 7U + +/* PININT Bit slice configuration register bits */ +#define PININT_BITSLICE_CFG_START 8U +#define PININT_BITSLICE_CFG_MASK 7U +#define PININT_BITSLICE_ENDP_MASK 7U + +#define PINT_PIN_INT_LEVEL 0x10U +#define PINT_PIN_INT_EDGE 0x00U +#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U +#define PINT_PIN_INT_RISE 0x01U +#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) +#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) +#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + +/*! @brief PINT Pin Interrupt enable type */ +typedef enum _pint_pin_enable +{ + kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ + kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ + kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ + kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ + kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ + kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ +} pint_pin_enable_t; + +/*! @brief PINT Pin Interrupt type */ +typedef enum _pint_int +{ + kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ +#endif +} pint_pin_int_t; + +/*! @brief PINT Pattern Match bit slice input source type */ +typedef enum _pint_pmatch_input_src +{ + kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ + kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ + kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ + kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ + kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ + kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ + kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ +} pint_pmatch_input_src_t; + +/*! @brief PINT Pattern Match bit slice type */ +typedef enum _pint_pmatch_bslice +{ + kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ +#endif +} pint_pmatch_bslice_t; + +/*! @brief PINT Pattern Match configuration type */ +typedef enum _pint_pmatch_bslice_cfg +{ + kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ + kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ + kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ + kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ + kPINT_PatternMatchHigh = 4U, /*!< High level */ + kPINT_PatternMatchLow = 5U, /*!< Low level */ + kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ + kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ +} pint_pmatch_bslice_cfg_t; + +/*! @brief PINT Callback function. */ +typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); + +typedef struct _pint_pmatch_cfg +{ + pint_pmatch_input_src_t bs_src; + pint_pmatch_bslice_cfg_t bs_cfg; + bool end_point; + pint_cb_t callback; +} pint_pmatch_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Init(PINT_Type *base); + +/*! + * @brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param intr Pin interrupt. + * @param enable Selects detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); + +/*! + * @brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * @param enable Pointer to store the detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); + +/*! + * @brief Clear Selected pin interrupt status. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + base->IST = (1U << pintr); +} + +/*! + * @brief Get Selected pin interrupt status. + + * This function returns the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->IST & (1U << pintr)) ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupts status. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrStatusAll(PINT_Type *base) +{ + base->IST = PINT_IST_PSTAT_MASK; +} + +/*! + * @brief Get all pin interrupts status. + + * This function returns the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the status of corresponding pin interrupt. + * = 0 No pin interrupt request. = 1 Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) +{ + return (base->IST); +} + +/*! + * @brief Clear Selected pin interrupt fall flag. + + * This function clears the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->FALL = (1U << pintr); +} + +/*! + * @brief Get selected pin interrupt fall flag. + + * This function returns the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->FALL & (1U << pintr)) ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt fall flags. + + * This function clears the fall flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) +{ + base->FALL = PINT_FALL_FDET_MASK; +} + +/*! + * @brief Get all pin interrupt fall flags. + + * This function returns the fall flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. + * 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) +{ + return (base->FALL); +} + +/*! + * @brief Clear Selected pin interrupt rise flag. + + * This function clears the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->RISE = (1U << pintr); +} + +/*! + * @brief Get selected pin interrupt rise flag. + + * This function returns the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->RISE & (1U << pintr)) ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt rise flags. + + * This function clears the rise flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) +{ + base->RISE = PINT_RISE_RDET_MASK; +} + +/*! + * @brief Get all pin interrupt rise flags. + + * This function returns the rise flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. + * 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) +{ + return (base->RISE); +} + +/*! + * @brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get pattern match bit slice status. + + * This function returns the status of selected bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * + * @retval status = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) +{ + return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (0x1U << bslice)) >> bslice; +} + +/*! + * @brief Get status of all pattern match bit slices. + + * This function returns the status of all bit slices. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the match status of corresponding bit slice. + * = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) +{ + return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; +} + +/*! + * @brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * @param base Base address of the PINT peripheral. + * + * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); + +/*! + * @brief Enable pattern match function. + + * This function enables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Disable pattern match function. + + * This function disables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Enable RXEV output. + + * This function enables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Disable RXEV output. + + * This function disables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_EnableCallback(PINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void PINT_DisableCallback(PINT_Type *base); + +/*! + * @brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Deinit(PINT_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_PINT_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.c new file mode 100644 index 00000000000..128de353cdf --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.c @@ -0,0 +1,46 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016, NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_common.h" +#include "fsl_power.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.power" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Empty file since implementation is in header file and power library */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.h new file mode 100644 index 00000000000..64ea4053713 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_power.h @@ -0,0 +1,256 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016, NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_POWER_H_ +#define _FSL_POWER_H_ + +#include "fsl_common.h" + +/*! @addtogroup power */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 2.0.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot)) +#define PDRCFG0 0x0U +#define PDRCFG1 0x1U + +typedef enum pd_bits +{ + kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U), + kPDRUNCFG_PD_FLASH = MAKE_PD_BITS(PDRCFG0, 5U), + kPDRUNCFG_PD_TEMPS = MAKE_PD_BITS(PDRCFG0, 6U), + kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U), + kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U), + kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U), + kPDRUNCFG_PD_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 11U), + kPDRUNCFG_LP_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 12U), + kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U), + kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U), + kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U), + kPDRUNCFG_PD_RAMX = MAKE_PD_BITS(PDRCFG0, 16U), + kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U), + kPDRUNCFG_PD_VDDHV_ENA = MAKE_PD_BITS(PDRCFG0, 18U), + kPDRUNCFG_PD_VD7_ENA = MAKE_PD_BITS(PDRCFG0, 19U), + kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U), + kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U), + kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U), + kPDRUNCFG_PD_VREFP_SW = MAKE_PD_BITS(PDRCFG0, 23U), + kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U), + + kPDRUNCFG_PD_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 28U), + kPDRUNCFG_SEL_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 29U), + + /* + This enum member has no practical meaning,it is used to avoid MISRA issue, + user should not trying to use it. + */ + kPDRUNCFG_ForceUnsigned = 0x80000000U +} pd_bit_t; + +/* Power mode configuration API parameter */ +typedef enum _power_mode_config +{ + kPmu_Sleep = 0U, + kPmu_Deep_Sleep = 1U, + kPmu_Deep_PowerDown = 2U, +} power_mode_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! +* @name Power Configuration +* @{ +*/ + +/*! + * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral + * + * @param en peripheral for which to enable the PDRUNCFG bit + * @return none + */ +static inline void POWER_EnablePD(pd_bit_t en) +{ + /* PDRUNCFGSET */ + SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU)); +} + +/*! + * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral + * + * @param en peripheral for which to disable the PDRUNCFG bit + * @return none + */ +static inline void POWER_DisablePD(pd_bit_t en) +{ + /* PDRUNCFGCLR */ + SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU)); +} + +/*! + * @brief API to enable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_EnableDeepSleep(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to disable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_DisableDeepSleep(void) +{ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to power down flash controller. + * + * @return none + */ +static inline void POWER_PowerDownFlash(void) +{ + /* note, we retain flash trim to make waking back up faster */ + SYSCON->PDRUNCFGSET[0] = + SYSCON_PDRUNCFG_LP_VDDFLASH_MASK | SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK | SYSCON_PDRUNCFG_PD_FLASH_BG_MASK; + + /* TURN OFF clock for Flash Controller (only needed for FLASH programming, will be turned on by ROM API) */ + CLOCK_DisableClock(kCLOCK_Flash); + + /* TURN OFF clock for Flash Accelerator */ + CLOCK_DisableClock(kCLOCK_Fmc); +} + +/*! + * @brief API to power up flash controller. + * + * @return none + */ +static inline void POWER_PowerUpFlash(void) +{ + SYSCON->PDRUNCFGCLR[0] = SYSCON_PDRUNCFG_LP_VDDFLASH_MASK | SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK; + + /* TURN ON clock for flash Accelerator */ + CLOCK_EnableClock(kCLOCK_Fmc); + + /* TURN ON clock for flash Controller */ + CLOCK_EnableClock(kCLOCK_Flash); +} + +/*! + * @brief Power Library API to enter different power mode. + * + * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep + * @return none + */ +void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd); + +/*! + * @brief Power Library API to enter sleep mode. + * + * @return none + */ +void POWER_EnterSleep(void); + +/*! + * @brief Power Library API to enter deep sleep mode. + * + * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep + * @return none + */ +void POWER_EnterDeepSleep(uint64_t exclude_from_pd); + +/*! + * @brief Power Library API to enter deep power down mode. + * + * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode, + * but this is has no effect as the voltages are cut off. + * @return none + */ +void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd); + +/*! + * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. + * + * @param freq - The desired frequency at which the part would like to operate, + * note that the voltage and flash wait states should be set before changing frequency + * @return none + */ +void POWER_SetVoltageForFreq(uint32_t freq); + +/*! + * @brief Power Library API to choose low power regulation and set the voltage for the desired operating frequency. + * + * @param freq - The desired frequency at which the part would like to operate, + * note only 12MHz and 48Mhz are supported + * @return none + */ +void POWER_SetLowPowerVoltageForFreq(uint32_t freq); + +/*! + * @brief Power Library API to return the library version. + * + * @return version number of the power library + */ +uint32_t POWER_GetLibVersion(void); + +/* @} */ + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /* _FSL_POWER_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.c new file mode 100644 index 00000000000..da1822e5e03 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.c @@ -0,0 +1,178 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016, NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) + +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1u << bitPos; + + assert(bitPos < 32u); + + /* ASYNC_SYSCON registers have offset 1024 */ + if (regIndex >= SYSCON_PRESETCTRL_COUNT) + { + /* reset register is in ASYNC_SYSCON */ + + /* set bit */ + ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask; + /* wait until it reads 0b1 */ + while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) + { + } + } + else + { + /* reset register is in SYSCON */ + + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask)) + { + } + } +} + +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1u << bitPos; + + assert(bitPos < 32u); + + /* ASYNC_SYSCON registers have offset 1024 */ + if (regIndex >= SYSCON_PRESETCTRL_COUNT) + { + /* reset register is in ASYNC_SYSCON */ + + /* clear bit */ + ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) + { + } + } + else + { + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask)) + { + } + } +} + +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +void RESET_SetSlaveCoreReset(void) +{ + uint32_t cpuctrl = (SYSCON->CPUCTRL & ~0x7F80U) | 0xC0C48000U; + + /* CM4 is the master. */ + if (cpuctrl & SYSCON_CPUCTRL_MASTERCPU_MASK) + { + SYSCON->CPUCTRL = cpuctrl | SYSCON_CPUCTRL_CM0RSTEN_MASK; + } + /* CM0 is the master. */ + else + { + SYSCON->CPUCTRL = cpuctrl | SYSCON_CPUCTRL_CM4RSTEN_MASK; + } +} + +void RESET_ClearSlaveCoreReset(void) +{ + uint32_t cpuctrl = (SYSCON->CPUCTRL & ~0x7F80U) | 0xC0C48000U; + + /* CM4 is the master. */ + if (cpuctrl & SYSCON_CPUCTRL_MASTERCPU_MASK) + { + SYSCON->CPUCTRL = cpuctrl & ~SYSCON_CPUCTRL_CM0RSTEN_MASK; + } + /* CM0 is the master. */ + else + { + SYSCON->CPUCTRL = cpuctrl & ~SYSCON_CPUCTRL_CM4RSTEN_MASK; + } +} + +void RESET_SlaveCoreReset(uint32_t bootAddr, uint32_t bootStackPointer) +{ + volatile uint32_t i = 10U; + + SYSCON->CPSTACK = bootStackPointer; + SYSCON->CPBOOT = bootAddr; + + RESET_SetSlaveCoreReset(); + while(i--){} + RESET_ClearSlaveCoreReset(); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.h new file mode 100644 index 00000000000..19142d12005 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_reset.h @@ -0,0 +1,231 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016, NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.0.0. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ + kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ + kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */ + kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ + kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ + kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ + kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ + kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kDMIC_RST_SHIFT_RSTn = 65536 | 19U, /**< Digital microphone interface reset control */ + kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */ + kUSB_RST_SHIFT_RSTn = 65536 | 25U, /**< USB reset control */ + kCT32B0_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B0 reset control */ + kCT32B1_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B1 reset control */ + kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */ + kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define DMA_RSTS \ + { \ + kDMA_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ +#define DMIC_RSTS \ + { \ + kDMIC_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GINT_RSTS \ + { \ + kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ + } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ +#define GPIO_RSTS \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define IOCON_RSTS \ + { \ + kIOCON_RST_SHIFT_RSTn \ + } /* Reset bits for IOCON peripheral */ +#define FLASH_RSTS \ + { \ + kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define SCT_RSTS \ + { \ + kSCT0_RST_SHIFT_RSTn \ + } /* Reset bits for SCT peripheral */ +#define CTIMER_RSTS \ + { \ + kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \ + kCT32B4_RST_SHIFT_RSTn \ + } /* Reset bits for TIMER peripheral */ +#define USB_RSTS \ + { \ + kUSB_RST_SHIFT_RSTn \ + } /* Reset bits for USB peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define WWDT_RSTS \ + { \ + kWWDT_RST_SHIFT_RSTn \ + } /* Reset bits for WWDT peripheral */ + +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Set slave core to reset state and hold. + */ +void RESET_SetSlaveCoreReset(void); + +/*! + * @brief Release slave core from reset state. + */ +void RESET_ClearSlaveCoreReset(void); + +/*! + * @brief Reset slave core with the boot entry. + */ +void RESET_SlaveCoreReset(uint32_t bootAddr, uint32_t bootStackPointer); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.c new file mode 100644 index 00000000000..38b7aa595cb --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.c @@ -0,0 +1,300 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" +#endif + +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + return false; + } + + return true; +} + +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Number of days from begin of the non Leap-year*/ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +void RTC_Init(RTC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the RTC peripheral clock */ + CLOCK_EnableClock(kCLOCK_Rtc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Make sure the reset bit is cleared */ + base->CTRL &= ~RTC_CTRL_SWRESET_MASK; + +#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) + /* Make sure the RTC OSC is powered up */ + base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; +#endif +} + +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Return error if the time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + base->COUNT = RTC_ConvertDatetimeToSeconds(datetime); + + return kStatus_Success; +} + +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0; + + seconds = base->COUNT; + RTC_ConvertSecondsToDatetime(seconds, datetime); +} + +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0; + uint32_t currSeconds = 0; + + /* Return error if the alarm time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); + + /* Get the current time */ + currSeconds = base->COUNT; + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* Set alarm in seconds*/ + base->MATCH = alarmSeconds; + + return kStatus_Success; +} + +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0; + + /* Get alarm in seconds */ + alarmSeconds = base->MATCH; + + RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.h new file mode 100644 index 00000000000..7e885db6d83 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_rtc.h @@ -0,0 +1,344 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RTC_H_ +#define _FSL_RTC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rtc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of RTC interrupts */ +typedef enum _rtc_interrupt_enable +{ + kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/ + kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/ +} rtc_interrupt_enable_t; + +/*! @brief List of RTC flags */ +typedef enum _rtc_status_flags +{ + kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/ + kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/ +} rtc_status_flags_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} rtc_datetime_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the RTC clock and enables the RTC oscillator. + * + * @note This API should be called at the beginning of the application using the RTC driver. + * + * @param base RTC peripheral base address + */ +void RTC_Init(RTC_Type *base); + +/*! + * @brief Stop the timer and gate the RTC clock + * + * @param base RTC peripheral base address + */ +static inline void RTC_Deinit(RTC_Type *base) +{ + /* Stop the RTC timer */ + base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the module clock */ + CLOCK_DisableClock(kCLOCK_Rtc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! @}*/ + +/*! + * @name Current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function as writes to the RTC + * seconds register will fail if the RTC counter is running. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details to set are stored + * + * @return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); + +/*! + * @brief Gets the RTC time and stores it in the given time structure. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details are stored. + */ +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); + +/*! + * @brief Sets the RTC alarm time + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * @param base RTC peripheral base address + * @param alarmTime Pointer to structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); + +/*! + * @brief Returns the RTC alarm time. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the alarm date and time details are stored. + */ +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); + +/*! @}*/ + +/*! + * @brief Enable the RTC high resolution timer and set the wake-up time. + * + * @param base RTC peripheral base address + * @param wakeupValue The value to be loaded into the RTC WAKE register + */ +static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) +{ + /* Enable the 1kHz RTC timer */ + base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; + + /* Set the start count value into the wake-up timer */ + base->WAKE = wakeupValue; +} + +/*! + * @brief Read actual RTC counter value. + * + * @param base RTC peripheral base address + */ +static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) +{ + /* Read wake-up counter */ + return RTC_WAKE_VAL(base->WAKE); +} + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + uint32_t reg = base->CTRL; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); + reg |= mask; + + base->CTRL = reg; +} + +/*! + * @brief Disables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + uint32_t reg = base->CTRL; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask); + + base->CTRL = reg; +} + +/*! + * @brief Gets the enabled RTC interrupts. + * + * @param base RTC peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) +{ + return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK)); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the RTC status flags + * + * @param base RTC peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) +{ + return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK)); +} + +/*! + * @brief Clears the RTC status flags. + * + * @param base RTC peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) +{ + uint32_t reg = base->CTRL; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); + + /* Write 1 to the flags we wish to clear */ + reg |= mask; + + base->CTRL = reg; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the RTC time counter. + * + * After calling this function, the timer counter increments once a second provided SR[TOF] or + * SR[TIF] are not set. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StartTimer(RTC_Type *base) +{ + base->CTRL |= RTC_CTRL_RTC_EN_MASK; +} + +/*! + * @brief Stops the RTC time counter. + * + * RTC's seconds register can be written to only when the timer is stopped. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StopTimer(RTC_Type *base) +{ + base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; +} + +/*! @}*/ + +/*! + * @brief Performs a software reset on the RTC module. + * + * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. + * + * @param base RTC peripheral base address + */ +static inline void RTC_Reset(RTC_Type *base) +{ + base->CTRL |= RTC_CTRL_SWRESET_MASK; + base->CTRL &= ~RTC_CTRL_SWRESET_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_RTC_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.c new file mode 100644 index 00000000000..fb6b97ff615 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.c @@ -0,0 +1,559 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sctimer.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sctimer" +#endif + +/*! @brief Typedef for interrupt handler. */ +typedef void (*sctimer_isr_t)(SCT_Type *base); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base SCTimer peripheral base address + * + * @return The SCTimer instance + */ +static uint32_t SCTIMER_GetInstance(SCT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to SCT bases for each instance. */ +static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to SCT clocks for each instance. */ +static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; +#else +/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_sctResets[] = SCT_RSTS; +#endif + +/*!< @brief SCTimer event Callback function. */ +static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; + +/*!< @brief Keep track of SCTimer event number */ +static uint32_t s_currentEvent; + +/*!< @brief Keep track of SCTimer state number */ +static uint32_t s_currentState; + +/*!< @brief Keep track of SCTimer match/capture register number */ +static uint32_t s_currentMatch; + +/*! @brief Pointer to SCTimer IRQ handler */ +static sctimer_isr_t s_sctimerIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SCTIMER_GetInstance(SCT_Type *base) +{ + uint32_t instance; + uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < sctArrayCount; instance++) + { + if (s_sctBases[instance] == base) + { + break; + } + } + + assert(instance < sctArrayCount); + + return instance; +} + +status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) +{ + assert(config); + uint32_t i; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SCTimer clock*/ + CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module */ + RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); + + /* Setup the counter operation */ + base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | + SCT_CONFIG_UNIFY(config->enableCounterUnify); + + /* Write to the control register, clear the counter and keep the counters halted */ + base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | + SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK; + + if (!(config->enableCounterUnify)) + { + base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | + SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK; + } + + /* Initial state of channel output */ + base->OUTPUT = config->outInitState; + + /* Clear the global variables */ + s_currentEvent = 0; + s_currentState = 0; + s_currentMatch = 0; + + /* Clear the callback array */ + for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) + { + s_eventCallback[i] = NULL; + } + + /* Save interrupt handler */ + s_sctimerIsr = SCTIMER_EventHandleIRQ; + + return kStatus_Success; +} + +void SCTIMER_Deinit(SCT_Type *base) +{ + /* Halt the counters */ + base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the SCTimer clock*/ + CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void SCTIMER_GetDefaultConfig(sctimer_config_t *config) +{ + assert(config); + + /* SCT operates as a unified 32-bit counter */ + config->enableCounterUnify = true; + /* System clock clocks the entire SCT module */ + config->clockMode = kSCTIMER_System_ClockMode; + /* This is used only by certain clock modes */ + config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + /* Up count mode only for the unified counter */ + config->enableBidirection_l = false; + /* Up count mode only for Counte_H */ + config->enableBidirection_h = false; + /* Prescale factor of 1 */ + config->prescale_l = 0; + /* Prescale factor of 1 for Counter_H*/ + config->prescale_h = 0; + /* Clear outputs */ + config->outInitState = 0; +} + +status_t SCTIMER_SetupPwm(SCT_Type *base, + const sctimer_pwm_signal_param_t *pwmParams, + sctimer_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint32_t *event) +{ + assert(pwmParams); + assert(srcClock_Hz); + assert(pwmFreq_Hz); + assert(pwmParams->output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + uint32_t period, pulsePeriod = 0; + uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1); + uint32_t periodEvent = 0, pulseEvent = 0; + uint32_t reg; + + /* This function will create 2 events, return an error if we do not have enough events available */ + if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS) + { + return kStatus_Fail; + } + + if (pwmParams->dutyCyclePercent == 0) + { + return kStatus_Fail; + } + + /* Set unify bit to operate in 32-bit counter mode */ + base->CONFIG |= SCT_CONFIG_UNIFY_MASK; + + /* Use bi-directional mode for center-aligned PWM */ + if (mode == kSCTIMER_CenterAlignedPwm) + { + base->CTRL |= SCT_CTRL_BIDIR_L_MASK; + } + + /* Calculate PWM period match value */ + if (mode == kSCTIMER_EdgeAlignedPwm) + { + period = (sctClock / pwmFreq_Hz) - 1; + } + else + { + period = sctClock / (pwmFreq_Hz * 2); + } + + /* Calculate pulse width match value */ + pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100; + + /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ + if (pwmParams->dutyCyclePercent >= 100) + { + pulsePeriod = period + 2; + } + + /* Schedule an event when we reach the PWM period */ + SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent); + + /* Schedule an event when we reach the pulse width */ + SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent); + + /* Reset the counter when we reach the PWM period */ + SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent); + + /* Return the period event to the user */ + *event = periodEvent; + + /* For high-true level */ + if (pwmParams->level == kSCTIMER_HighTrue) + { + /* Set the initial output level to low which is the inactive state */ + base->OUTPUT &= ~(1U << pwmParams->output); + + if (mode == kSCTIMER_EdgeAlignedPwm) + { + /* Set the output when we reach the PWM period */ + SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent); + /* Clear the output when we reach the PWM pulse value */ + SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); + } + else + { + /* Clear the output when we reach the PWM pulse event */ + SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); + /* Reverse output when down counting */ + reg = base->OUTPUTDIRCTRL; + reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); + reg |= (1U << (2 * pwmParams->output)); + base->OUTPUTDIRCTRL = reg; + } + } + /* For low-true level */ + else + { + /* Set the initial output level to high which is the inactive state */ + base->OUTPUT |= (1U << pwmParams->output); + + if (mode == kSCTIMER_EdgeAlignedPwm) + { + /* Clear the output when we reach the PWM period */ + SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent); + /* Set the output when we reach the PWM pulse value */ + SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); + } + else + { + /* Set the output when we reach the PWM pulse event */ + SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); + /* Reverse output when down counting */ + reg = base->OUTPUTDIRCTRL; + reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); + reg |= (1U << (2 * pwmParams->output)); + base->OUTPUTDIRCTRL = reg; + } + } + + return kStatus_Success; +} + +void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) + +{ + assert(dutyCyclePercent > 0); + assert(output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + uint32_t periodMatchReg, pulseMatchReg; + uint32_t pulsePeriod = 0, period; + + /* Retrieve the match register number for the PWM period */ + periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; + + /* Retrieve the match register number for the PWM pulse period */ + pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; + + period = base->SCTMATCH[periodMatchReg]; + + /* Calculate pulse width match value */ + pulsePeriod = (period * dutyCyclePercent) / 100; + + /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent >= 100) + { + pulsePeriod = period + 2; + } + + /* Stop the counter before updating match register */ + SCTIMER_StopTimer(base, kSCTIMER_Counter_L); + + /* Update dutycycle */ + base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod); + base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod); + + /* Restart the counter */ + SCTIMER_StartTimer(base, kSCTIMER_Counter_L); +} + +status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, + sctimer_event_t howToMonitor, + uint32_t matchValue, + uint32_t whichIO, + sctimer_counter_t whichCounter, + uint32_t *event) +{ + uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT); + uint32_t currentCtrlVal = howToMonitor; + + /* Return an error if we have hit the limit in terms of number of events created */ + if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS) + { + return kStatus_Fail; + } + + /* IO only mode */ + if (combMode == 0x2U) + { + base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO); + } + /* Match mode only */ + else if (combMode == 0x1U) + { + /* Return an error if we have hit the limit in terms of number of number of match registers */ + if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + return kStatus_Fail; + } + + currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch); + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); + base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); + } + else + { + /* Select the counter, no need for this if operating in 32-bit mode */ + currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); + base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); + base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); + } + base->EVENT[s_currentEvent].CTRL = currentCtrlVal; + /* Increment the match register number */ + s_currentMatch++; + } + /* Use both Match & IO */ + else + { + /* Return an error if we have hit the limit in terms of number of number of match registers */ + if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + return kStatus_Fail; + } + + currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO); + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); + base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); + } + else + { + /* Select the counter, no need for this if operating in 32-bit mode */ + currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); + base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); + base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); + } + base->EVENT[s_currentEvent].CTRL = currentCtrlVal; + /* Increment the match register number */ + s_currentMatch++; + } + + /* Enable the event in the current state */ + base->EVENT[s_currentEvent].STATE = (1U << s_currentState); + + /* Return the event number */ + *event = s_currentEvent; + + /* Increment the event number */ + s_currentEvent++; + + return kStatus_Success; +} + +void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) +{ + /* Enable event in the current state */ + base->EVENT[event].STATE |= (1U << s_currentState); +} + +status_t SCTIMER_IncreaseState(SCT_Type *base) +{ + /* Return an error if we have hit the limit in terms of states used */ + if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES) + { + return kStatus_Fail; + } + + s_currentState++; + + return kStatus_Success; +} + +uint32_t SCTIMER_GetCurrentState(SCT_Type *base) +{ + return s_currentState; +} + +void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + uint32_t reg; + + /* Set the same event to set and clear the output */ + base->OUT[whichIO].CLR |= (1U << event); + base->OUT[whichIO].SET |= (1U << event); + + /* Set the conflict resolution to toggle output */ + reg = base->RES; + reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO)); + reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO)); + base->RES = reg; +} + +status_t SCTIMER_SetupCaptureAction(SCT_Type *base, + sctimer_counter_t whichCounter, + uint32_t *captureRegister, + uint32_t event) +{ + /* Return an error if we have hit the limit in terms of number of capture/match registers used */ + if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + return kStatus_Fail; + } + + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + /* Set the bit to enable event */ + base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event); + + /* Set this resource to be a capture rather than match */ + base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch); + } + else + { + /* Set bit to enable event */ + base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event); + + /* Set this resource to be a capture rather than match */ + base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch); + } + + /* Return the match register number */ + *captureRegister = s_currentMatch; + + /* Increase the match register number */ + s_currentMatch++; + + return kStatus_Success; +} + +void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) +{ + s_eventCallback[event] = callback; +} + +void SCTIMER_EventHandleIRQ(SCT_Type *base) +{ + uint32_t eventFlag = SCT0->EVFLAG; + /* Only clear the flags whose interrupt field is enabled */ + uint32_t clearFlag = (eventFlag & SCT0->EVEN); + uint32_t mask = eventFlag; + int i = 0; + + /* Invoke the callback for certain events */ + for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++) + { + if (mask & 0x1) + { + if (s_eventCallback[i] != NULL) + { + s_eventCallback[i](); + } + } + mask >>= 1; + } + + /* Clear event interrupt flag */ + SCT0->EVFLAG = clearFlag; +} + +void SCT0_IRQHandler(void) +{ + s_sctimerIsr(SCT0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.h new file mode 100644 index 00000000000..4274aa8068b --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_sctimer.h @@ -0,0 +1,834 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SCTIMER_H_ +#define _FSL_SCTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief SCTimer PWM operation modes */ +typedef enum _sctimer_pwm_mode +{ + kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ + kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ +} sctimer_pwm_mode_t; + +/*! @brief SCTimer counters when working as two independent 16-bit counters */ +typedef enum _sctimer_counter +{ + kSCTIMER_Counter_L = 0U, /*!< Counter L */ + kSCTIMER_Counter_H /*!< Counter H */ +} sctimer_counter_t; + +/*! @brief List of SCTimer input pins */ +typedef enum _sctimer_input +{ + kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ + kSCTIMER_Input_1, /*!< SCTIMER input 1 */ + kSCTIMER_Input_2, /*!< SCTIMER input 2 */ + kSCTIMER_Input_3, /*!< SCTIMER input 3 */ + kSCTIMER_Input_4, /*!< SCTIMER input 4 */ + kSCTIMER_Input_5, /*!< SCTIMER input 5 */ + kSCTIMER_Input_6, /*!< SCTIMER input 6 */ + kSCTIMER_Input_7 /*!< SCTIMER input 7 */ +} sctimer_input_t; + +/*! @brief List of SCTimer output pins */ +typedef enum _sctimer_out +{ + kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ + kSCTIMER_Out_1, /*!< SCTIMER output 1 */ + kSCTIMER_Out_2, /*!< SCTIMER output 2 */ + kSCTIMER_Out_3, /*!< SCTIMER output 3 */ + kSCTIMER_Out_4, /*!< SCTIMER output 4 */ + kSCTIMER_Out_5, /*!< SCTIMER output 5 */ + kSCTIMER_Out_6, /*!< SCTIMER output 6 */ + kSCTIMER_Out_7, /*!< SCTIMER output 7 */ + kSCTIMER_Out_8, /*!< SCTIMER output 8 */ + kSCTIMER_Out_9 /*!< SCTIMER output 9 */ +} sctimer_out_t; + +/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ +typedef enum _sctimer_pwm_level_select +{ + kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ + kSCTIMER_HighTrue /*!< High true pulses */ +} sctimer_pwm_level_select_t; + +/*! @brief Options to configure a SCTimer PWM signal */ +typedef struct _sctimer_pwm_signal_param +{ + sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ + sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 1 to 100 + 100 = always active signal (100% duty cycle).*/ +} sctimer_pwm_signal_param_t; + +/*! @brief SCTimer clock mode options */ +typedef enum _sctimer_clock_mode +{ + kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ + kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ + kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ + kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ +} sctimer_clock_mode_t; + +/*! @brief SCTimer clock select options */ +typedef enum _sctimer_clock_select +{ + kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ + kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ + kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ + kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ + kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ + kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ + kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ + kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ + kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ + kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ + kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ + kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ + kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ + kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ + kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ + kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ +} sctimer_clock_select_t; + +/*! + * @brief SCTimer output conflict resolution options. + * + * Specifies what action should be taken if multiple events dictate that a given output should be + * both set and cleared at the same time + */ +typedef enum _sctimer_conflict_resolution +{ + kSCTIMER_ResolveNone = 0U, /*!< No change */ + kSCTIMER_ResolveSet, /*!< Set output */ + kSCTIMER_ResolveClear, /*!< Clear output */ + kSCTIMER_ResolveToggle /*!< Toggle output */ +} sctimer_conflict_resolution_t; + +/*! @brief List of SCTimer event types */ +typedef enum _sctimer_event +{ + kSCTIMER_InputLowOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_MatchEventOnly = + (1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_InputLowEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_InputLowAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighOrMatchEvent = + (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighEvent = + (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighAndMatchEvent = + (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT) +} sctimer_event_t; + +/*! @brief SCTimer callback typedef. */ +typedef void (*sctimer_event_callback_t)(void); + +/*! @brief List of SCTimer interrupts */ +typedef enum _sctimer_interrupt_enable +{ + kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ + kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ + kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ + kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ + kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ + kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ + kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ + kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ + kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ + kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ + kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ + kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ + kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ +} sctimer_interrupt_enable_t; + +/*! @brief List of SCTimer flags */ +typedef enum _sctimer_status_flags +{ + kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ + kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ + kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ + kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ + kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ + kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ + kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ + kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ + kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ + kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ + kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ + kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ + kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ + kSCTIMER_BusErrorLFlag = + (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ + kSCTIMER_BusErrorHFlag = + (1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ +} sctimer_status_flags_t; + +/*! + * @brief SCTimer configuration structure + * + * This structure holds the configuration settings for the SCTimer peripheral. To initialize this + * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _sctimer_config +{ + bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; + false: SCT operates as two 16-bit counters */ + sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ + sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ + bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter + false: Up count mode only for the L or unified counter */ + bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter + false: Up count mode only for the H or unified counter. + This field is used only if the enableCounterUnify is set + to false */ + uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ + uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. + This field is used only if the enableCounterUnify is set + to false */ + uint8_t outInitState; /*!< Defines the initial output value */ +} sctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SCTimer driver. + * + * @param base SCTimer peripheral base address + * @param config Pointer to the user configuration structure. + * + * @return kStatus_Success indicates success; Else indicates failure. + */ +status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); + +/*! + * @brief Gates the SCTimer clock. + * + * @param base SCTimer peripheral base address + */ +void SCTIMER_Deinit(SCT_Type *base); + +/*! + * @brief Fills in the SCTimer configuration structure with the default settings. + * + * The default values are: + * @code + * config->enableCounterUnify = true; + * config->clockMode = kSCTIMER_System_ClockMode; + * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + * config->enableBidirection_l = false; + * config->enableBidirection_h = false; + * config->prescale_l = 0; + * config->prescale_h = 0; + * config->outInitState = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void SCTIMER_GetDefaultConfig(sctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This + * function will create 2 events; one of the events will trigger on match with the pulse value + * and the other will trigger when the counter matches the PWM period. The PWM period event is + * also used as a limit event to reset the counter or change direction. Both events are enabled + * for the same state. The state number can be retrieved by calling the function + * SCTIMER_GetCurrentStateNumber(). + * The counter is set to operate as one 32-bit counter (unify bit is set to 1). + * The counter operates in bi-directional mode when generating a center-aligned PWM. + * + * @note When setting PWM output from multiple output pins, they all should use the same PWM mode + * i.e all PWM's should be either edge-aligned or center-aligned. + * When using this API, the PWM signal frequency of all the initialized channels must be the same. + * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the + * API's pwmFreq_Hz. + * + * @param base SCTimer peripheral base address + * @param pwmParams PWM parameters to configure the output + * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz SCTimer counter clock in Hz + * @param event Pointer to a variable where the PWM period event number is stored + * + * @return kStatus_Success on success + * kStatus_Fail If we have hit the limit in terms of number of events created or if + * an incorrect PWM dutycylce is passed in. + */ +status_t SCTIMER_SetupPwm(SCT_Type *base, + const sctimer_pwm_signal_param_t *pwmParams, + sctimer_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint32_t *event); + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @param base SCTimer peripheral base address + * @param output The output to configure + * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 + * @param event Event number associated with this PWM signal. This was returned to the user by the + * function SCTIMER_SetupPwm(). + */ +void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) +{ + base->EVEN |= mask; +} + +/*! + * @brief Disables the selected SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) +{ + base->EVEN &= ~mask; +} + +/*! + * @brief Gets the enabled SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) +{ + return (base->EVEN & 0xFFFFU); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the SCTimer status flags. + * + * @param base SCTimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::sctimer_status_flags_t + */ +static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) +{ + uint32_t statusFlags = 0; + + /* Add the recorded events */ + statusFlags = (base->EVFLAG & 0xFFFFU); + + /* Add bus error flags */ + statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); + + return statusFlags; +} + +/*! + * @brief Clears the SCTimer status flags. + * + * @param base SCTimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::sctimer_status_flags_t + */ +static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) +{ + /* Write to the flag registers */ + base->EVFLAG = (mask & 0xFFFFU); + base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the SCTimer counter. + * + * @param base SCTimer peripheral base address + * @param countertoStart SCTimer counter to start; if unify mode is set then function always + * writes to HALT_L bit + */ +static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart) +{ + /* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L)) + { + base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); + } + else + { + /* Start H counter */ + base->CTRL &= ~(SCT_CTRL_HALT_H_MASK); + } +} + +/*! + * @brief Halts the SCTimer counter. + * + * @param base SCTimer peripheral base address + * @param countertoStop SCTimer counter to stop; if unify mode is set then function always + * writes to HALT_L bit + */ +static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop) +{ + /* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L)) + { + base->CTRL |= (SCT_CTRL_HALT_L_MASK); + } + else + { + /* Stop H counter */ + base->CTRL |= (SCT_CTRL_HALT_H_MASK); + } +} + +/*! @}*/ + +/*! + * @name Functions to create a new event and manage the state logic + * @{ + */ + +/*! + * @brief Create an event that is triggered on a match or IO and schedule in current state. + * + * This function will configure an event using the options provided by the user. If the event type uses + * the counter match, then the function will set the user provided match value into a match register + * and put this match register number into the event control register. + * The event is enabled for the current state and the event number is increased by one at the end. + * The function returns the event number; this event number can be used to configure actions to be + * done when this event is triggered. + * + * @param base SCTimer peripheral base address + * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t + * @param matchValue The match value that will be programmed to a match register + * @param whichIO The input or output that will be involved in event triggering. This field + * is ignored if the event type is "match only" + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as we have only 1 unified counter; hence ignored. + * @param event Pointer to a variable where the new event number is stored + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of events created or + if we have reached the limit in terms of number of match registers + */ +status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, + sctimer_event_t howToMonitor, + uint32_t matchValue, + uint32_t whichIO, + sctimer_counter_t whichCounter, + uint32_t *event); + +/*! + * @brief Enable an event in the current state. + * + * This function will allow the event passed in to trigger in the current state. The event must + * be created earlier by either calling the function SCTIMER_SetupPwm() or function + * SCTIMER_CreateAndScheduleEvent() . + * + * @param base SCTimer peripheral base address + * @param event Event number to enable in the current state + * + */ +void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); + +/*! + * @brief Increase the state by 1 + * + * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new + * state. + * + * @param base SCTimer peripheral base address + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of states used + + */ +status_t SCTIMER_IncreaseState(SCT_Type *base); + +/*! + * @brief Provides the current state + * + * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). + * + * @param base SCTimer peripheral base address + * + * @return The current state + */ +uint32_t SCTIMER_GetCurrentState(SCT_Type *base); + +/*! @}*/ + +/*! + * @name Actions to take in response to an event + * @{ + */ + +/*! + * @brief Setup capture of the counter value on trigger of a selected event + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * @param captureRegister Pointer to a variable where the capture register number will be returned. User + * can read the captured value from this register when the specified event is triggered. + * @param event Event number that will trigger the capture + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of match/capture registers available + */ +status_t SCTIMER_SetupCaptureAction(SCT_Type *base, + sctimer_counter_t whichCounter, + uint32_t *captureRegister, + uint32_t event); + +/*! + * @brief Receive noticification when the event trigger an interrupt. + * + * If the interrupt for the event is enabled by the user, then a callback can be registered + * which will be invoked when the event is triggered + * + * @param base SCTimer peripheral base address + * @param event Event number that will trigger the interrupt + * @param callback Function to invoke when the event is triggered + */ + +void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); + +/*! + * @brief Transition to the specified state. + * + * This transition will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param nextState The next state SCTimer will transition to + * @param event Event number that will trigger the state transition + */ +static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) +{ + uint32_t reg = base->EVENT[event].CTRL; + + reg &= ~(SCT_EVENT_CTRL_STATEV_MASK); + /* Load the STATEV value when the event occurs to be the next state */ + reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK; + + base->EVENT[event].CTRL = reg; +} + +/*! + * @brief Set the Output. + * + * This output will be set when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to set + * @param event Event number that will trigger the output change + */ +static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + base->OUT[whichIO].SET |= (1U << event); +} + +/*! + * @brief Clear the Output. + * + * This output will be cleared when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to clear + * @param event Event number that will trigger the output change + */ +static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + base->OUT[whichIO].CLR |= (1U << event); +} + +/*! + * @brief Toggle the output level. + * + * This change in the output level is triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to toggle + * @param event Event number that will trigger the output change + */ +void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); + +/*! + * @brief Limit the running counter. + * + * The counter is limited when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * @param event Event number that will trigger the counter to be limited + */ +static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event); + } + else + { + base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event); + } +} + +/*! + * @brief Stop the running counter. + * + * The counter is stopped when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * @param event Event number that will trigger the counter to be stopped + */ +static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->STOP |= SCT_STOP_STOPMSK_L(1U << event); + } + else + { + base->STOP |= SCT_STOP_STOPMSK_H(1U << event); + } +} + +/*! + * @brief Re-start the stopped counter. + * + * The counter will re-start when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * @param event Event number that will trigger the counter to re-start + */ +static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->START |= SCT_START_STARTMSK_L(1U << event); + } + else + { + base->START |= SCT_START_STARTMSK_H(1U << event); + } +} + +/*! + * @brief Halt the running counter. + * + * The counter is disabled (halted) when the event number that is passed in by the user is + * triggered. When the counter is halted, all further events are disabled. The HALT condition + * can only be removed by calling the SCTIMER_StartTimer() function. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this + * field has no meaning as only the Counter_L bits are used. + * @param event Event number that will trigger the counter to be halted + */ +static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ + if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + { + base->HALT |= SCT_HALT_HALTMSK_L(1U << event); + } + else + { + base->HALT |= SCT_HALT_HALTMSK_H(1U << event); + } +} + +#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) +/*! + * @brief Generate a DMA request. + * + * DMA request will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param dmaNumber The DMA request to generate + * @param event Event number that will trigger the DMA request + */ +static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) +{ + if (dmaNumber == 0) + { + base->DMA0REQUEST |= (1U << event); + } + else + { + base->DMA1REQUEST |= (1U << event); + } +} +#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ + +/*! + * @brief SCTimer interrupt handler. + * + * @param base SCTimer peripheral base address. + */ +void SCTIMER_EventHandleIRQ(SCT_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.c new file mode 100644 index 00000000000..8c50edc7a03 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.c @@ -0,0 +1,864 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_spi.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" +#endif + +/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ +#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) + +/* Convert transfer count to transfer bytes. dataWidth is a + * range <0,15>. Range <8,15> represents 2B transfer */ +#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) +#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief internal SPI config array */ +static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; + +/*! @brief Array to map SPI instance number to base address. */ +static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_spiIRQ[] = SPI_IRQS; + +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the FLEXCOMM */ +uint32_t SPI_GetInstance(SPI_Type *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_SPI_COUNT; i++) + { + if ((uint32_t)base == s_spiBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = SPI_GetInstance(base); + s_dummyData[instance] = dummyData; +} + +void *SPI_GetConfig(SPI_Type *base) +{ + int32_t instance; + instance = SPI_GetInstance(base); + if (instance < 0) + { + return NULL; + } + return &g_configs[instance]; +} + +void SPI_MasterGetDefaultConfig(spi_master_config_t *config) +{ + assert(NULL != config); + + config->enableLoopback = false; + config->enableMaster = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->baudRate_Bps = 500000U; + config->dataWidth = kSPI_Data8Bits; + config->sselNum = kSPI_Ssel0; + config->txWatermark = kSPI_TxFifo0; + config->rxWatermark = kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; + config->delayConfig.preDelay = 0U; + config->delayConfig.postDelay = 0U; + config->delayConfig.frameDelay = 0U; + config->delayConfig.transferDelay = 0U; +} + +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) +{ + int32_t result = 0, instance = 0; + uint32_t tmp; + + /* assert params */ + assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to SPI mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + assert(kStatus_Success == result); + if (kStatus_Success != result) + { + return result; + } + + /* set divider */ + result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + /* get instance number */ + instance = SPI_GetInstance(base); + assert(instance >= 0); + + /* configure SPI mode */ + tmp = base->CFG; + tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); + /* phase */ + tmp |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmp |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmp |= SPI_CFG_LSBF(config->direction); + /* master mode */ + tmp |= SPI_CFG_MASTER(1); + /* loopback */ + tmp |= SPI_CFG_LOOP(config->enableLoopback); + /* configure active level for all CS */ + tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmp; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + g_configs[instance].sselNum = config->sselNum; + /* enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmp; + + /* Set the delay configuration. */ + SPI_SetTransferDelay(base, &config->delayConfig); + /* Set the dummy data. */ + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableMaster); + return kStatus_Success; +} + +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) +{ + assert(NULL != config); + + config->enableSlave = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->dataWidth = kSPI_Data8Bits; + config->txWatermark = kSPI_TxFifo0; + config->rxWatermark = kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; +} + +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) +{ + int32_t result = 0, instance; + uint32_t tmp; + + /* assert params */ + assert(!((NULL == base) || (NULL == config))); + if ((NULL == base) || (NULL == config)) + { + return kStatus_InvalidArgument; + } + /* configure flexcomm to SPI, enable clock gate */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + assert(kStatus_Success == result); + if (kStatus_Success != result) + { + return result; + } + + instance = SPI_GetInstance(base); + + /* configure SPI mode */ + tmp = base->CFG; + tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK | + SPI_SSELPOL_MASK); + /* phase */ + tmp |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmp |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmp |= SPI_CFG_LSBF(config->direction); + /* configure active level for all CS */ + tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmp; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + /* empty and enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmp; + + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableSlave); + return kStatus_Success; +} + +void SPI_Deinit(SPI_Type *base) +{ + /* Assert arguments */ + assert(NULL != base); + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | + SPI_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); + base->CFG &= ~(SPI_CFG_ENABLE_MASK); +} + +void SPI_EnableTxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; + } +} + +void SPI_EnableRxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; + } +} + +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t tmp; + + /* assert params */ + assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); + if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* calculate baudrate */ + tmp = (srcClock_Hz / baudrate_Bps) - 1; + if (tmp > 0xFFFF) + { + return kStatus_SPI_BaudrateNotSupport; + } + base->DIV &= ~SPI_DIV_DIVVAL_MASK; + base->DIV |= SPI_DIV_DIVVAL(tmp); + return kStatus_Success; +} + +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) +{ + uint32_t control = 0; + int32_t instance; + + /* check params */ + assert(NULL != base); + /* get and check instance */ + instance = SPI_GetInstance(base); + assert(!(instance < 0)); + if (instance < 0) + { + return; + } + + /* set data width */ + control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth); + /* set sssel */ + control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); + /* mask configFlags */ + control |= (configFlags & SPI_FIFOWR_FLAGS_MASK); + /* control should not affect lower 16 bits */ + assert(!(control & 0xFFFF)); + base->FIFOWR = data | control; +} + +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData) +{ + int32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + /* get flexcomm instance by 'base' param */ + instance = SPI_GetInstance(base); + assert(!(instance < 0)); + if (instance < 0) + { + return kStatus_InvalidArgument; + } + + memset(handle, 0, sizeof(*handle)); + /* Initialize the handle */ + if (base->CFG & SPI_CFG_MASTER_MASK) + { + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_MasterTransferHandleIRQ, handle); + } + else + { + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_SlaveTransferHandleIRQ, handle); + } + + handle->dataWidth = g_configs[instance].dataWidth; + /* in slave mode, the sselNum is not important */ + handle->sselNum = g_configs[instance].sselNum; + handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base); + handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base); + handle->callback = callback; + handle->userData = userData; + + /* Enable SPI NVIC */ + EnableIRQ(s_spiIRQ[instance]); + + return kStatus_Success; +} + +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) +{ + int32_t instance; + uint32_t tx_ctrl = 0, last_ctrl = 0; + uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; + uint32_t toReceiveCount = 0; + uint8_t *txData, *rxData; + uint32_t fifoDepth; + + /* check params */ + // assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + fifoDepth = SPI_FIFO_DEPTH(base); + txData = xfer->txData; + rxData = xfer->rxData; + txRemainingBytes = txData ? xfer->dataSize : 0; + rxRemainingBytes = rxData ? xfer->dataSize : 0; + + instance = SPI_GetInstance(base); + assert(instance >= 0); + dataWidth = g_configs[instance].dataWidth; + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); + if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) + { + return kStatus_InvalidArgument; + } + + /* clear tx/rx errors and empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* select slave to talk with */ + tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); + /* set width of data - range asserted at entry */ + tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); + /* delay for frames */ + tx_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; + /* end of transfer */ + last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; + /* last index of loop */ + while (txRemainingBytes || rxRemainingBytes || toReceiveCount) + { + /* if rxFIFO is not empty */ + if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (rxRemainingBytes) + { + *(rxData++) = tmp32; + rxRemainingBytes--; + /* read 16 bits at once */ + if (dataWidth > 8) + { + *(rxData++) = tmp32 >> 8; + rxRemainingBytes--; + } + } + /* decrease number of data expected to receive */ + toReceiveCount -= 1; + } + /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) && + ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)))) + { + /* txBuffer is not empty */ + if (txRemainingBytes) + { + tmp32 = *(txData++); + txRemainingBytes--; + /* write 16 bit at once */ + if (dataWidth > 8) + { + tmp32 |= ((uint32_t)(*(txData++))) << 8U; + txRemainingBytes--; + } + if (!txRemainingBytes) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); + /* last transfer */ + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + toReceiveCount += 1; + } + } + /* wait if TX FIFO of previous transfer is not empty */ + while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) + { + } + return kStatus_Success; +} + +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) +{ + /* check params */ + assert( + !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); + if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) + { + return kStatus_InvalidArgument; + } + + /* Check if SPI is busy */ + if (handle->state == kStatus_SPI_Busy) + { + return kStatus_SPI_Busy; + } + + /* Set the handle information */ + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + /* set count */ + handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0; + handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0; + handle->totalByteCount = xfer->dataSize; + /* other options */ + handle->toReceiveCount = 0; + handle->configFlags = xfer->configFlags; + /* Set the SPI state to busy */ + handle->state = kStatus_SPI_Busy; + /* clear FIFOs when transfer starts */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; + return kStatus_Success; +} + +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + /* SPI transfer blocking. */ + status = SPI_MasterTransferBlocking(base, &tempXfer); + + return status; +} + +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the PCS pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); + + return status; +} + +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kStatus_SPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->rxRemainingBytes; + return kStatus_Success; +} + +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupt requests*/ + base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); + /* Empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + + handle->state = kStatus_SPI_Idle; + handle->txRemainingBytes = 0; + handle->rxRemainingBytes = 0; +} + +static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) +{ + uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32; + bool loopContinue; + uint32_t fifoDepth; + /* Get flexcomm instance by 'base' param */ + uint32_t instance = SPI_GetInstance(base); + + /* check params */ + assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); + + fifoDepth = SPI_FIFO_DEPTH(base); + /* select slave to talk with */ + tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum)); + /* set width of data */ + tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); + /* delay for frames */ + tx_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; + /* end of transfer */ + last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; + do + { + loopContinue = false; + + /* rxFIFO is not empty */ + if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (handle->rxRemainingBytes) + { + /* low byte must go first */ + *(handle->rxData++) = tmp32; + handle->rxRemainingBytes--; + /* read 16 bits at once */ + if (handle->dataWidth > kSPI_Data8Bits) + { + *(handle->rxData++) = tmp32 >> 8; + handle->rxRemainingBytes--; + } + } + /* decrease number of data expected to receive */ + handle->toReceiveCount -= 1; + loopContinue = true; + } + + /* - txFIFO is not full + * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO + * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer + */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) && + ((handle->txRemainingBytes) || + (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)))) + { + /* txBuffer is not empty */ + if (handle->txRemainingBytes) + { + /* low byte must go first */ + tmp32 = *(handle->txData++); + handle->txRemainingBytes--; + /* write 16 bit at once */ + if (handle->dataWidth > kSPI_Data8Bits) + { + tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; + handle->txRemainingBytes--; + } + /* last transfer */ + if (!handle->txRemainingBytes) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); + /* last transfer */ + if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + /* increase number of expected data to receive */ + handle->toReceiveCount += 1; + loopContinue = true; + } + } while (loopContinue); +} + +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) +{ + assert((NULL != base) && (NULL != handle)); + + /* IRQ behaviour: + * - first interrupt is triggered by empty txFIFO. The transfer function + * then tries empty rxFIFO and fill txFIFO interleaved that results to + * strategy to process as many items as possible. + * - the next IRQs can be: + * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. + * txIRQ from empty txFIFO which requires to refill txFIFO. + * - last interrupt is triggered by empty txFIFO. The last state is + * known by empty rxBuffer and txBuffer. If there is nothing to receive + * or send - both operations have been finished and interrupts can be + * disabled. + */ + + /* Data to send or read or expected to receive */ + if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount)) + { + /* Transmit or receive data */ + SPI_TransferHandleIRQInternal(base, handle); + /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and + * enable txIRQ to confirm when txFIFO becomes empty */ + if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount)) + { + base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; + } + else + { + uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); + /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, + * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ + if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount)) + { + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; + } + /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. + * Cannot clear rxFIFO, txFIFO might be still active */ + if (rxRemainingCount == 0) + { + if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) && + (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1); + } + } + /* Expected to receive less data than rxLevel value, we have to update rxLevel */ + else + { + if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1); + } + } + } + } + else + { + /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; + base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | + SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); + /* set idle state and call user callback */ + handle->state = kStatus_SPI_Idle; + if (handle->callback) + { + (handle->callback)(base, handle, handle->state, handle->userData); + } + } +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.h new file mode 100644 index 00000000000..126792d486b --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi.h @@ -0,0 +1,751 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SPI_H_ +#define _FSL_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/*! + * @addtogroup spi_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI driver version 2.0.2. */ +#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t s_dummyData[]; + +#ifndef SPI_DUMMYDATA +/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define SPI_DUMMYDATA (0xFFU) +#endif + +#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF) +#define SPI_CTRLMASK (0xFFFF0000) + +#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000) +#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16)) +#define SPI_DEASSERT_ALL (0xF0000) + +#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) + +#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) +#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief SPI transfer option.*/ +typedef enum _spi_xfer_option +{ + kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ + kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ +} spi_xfer_option_t; + +/*! @brief SPI data shifter direction options.*/ +typedef enum _spi_shift_direction +{ + kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ + kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ +} spi_shift_direction_t; + +/*! @brief SPI clock polarity configuration.*/ +typedef enum _spi_clock_polarity +{ + kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ + kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ +} spi_clock_polarity_t; + +/*! @brief SPI clock phase configuration.*/ +typedef enum _spi_clock_phase +{ + kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first + * cycle of a data transfer. */ + kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the + * first cycle of a data transfer. */ +} spi_clock_phase_t; + +/*! @brief txFIFO watermark values */ +typedef enum _spi_txfifo_watermark +{ + kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ + kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ + kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ + kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ + kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ + kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ + kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ + kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ +} spi_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _spi_rxfifo_watermark +{ + kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ + kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ + kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ + kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ + kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ + kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ + kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ + kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ +} spi_rxfifo_watermark_t; + +/*! @brief Transfer data width */ +typedef enum _spi_data_width +{ + kSPI_Data4Bits = 3, /*!< 4 bits data width */ + kSPI_Data5Bits = 4, /*!< 5 bits data width */ + kSPI_Data6Bits = 5, /*!< 6 bits data width */ + kSPI_Data7Bits = 6, /*!< 7 bits data width */ + kSPI_Data8Bits = 7, /*!< 8 bits data width */ + kSPI_Data9Bits = 8, /*!< 9 bits data width */ + kSPI_Data10Bits = 9, /*!< 10 bits data width */ + kSPI_Data11Bits = 10, /*!< 11 bits data width */ + kSPI_Data12Bits = 11, /*!< 12 bits data width */ + kSPI_Data13Bits = 12, /*!< 13 bits data width */ + kSPI_Data14Bits = 13, /*!< 14 bits data width */ + kSPI_Data15Bits = 14, /*!< 15 bits data width */ + kSPI_Data16Bits = 15, /*!< 16 bits data width */ +} spi_data_width_t; + +/*! @brief Slave select */ +typedef enum _spi_ssel +{ + kSPI_Ssel0 = 0, /*!< Slave select 0 */ + kSPI_Ssel1 = 1, /*!< Slave select 1 */ + kSPI_Ssel2 = 2, /*!< Slave select 2 */ + kSPI_Ssel3 = 3, /*!< Slave select 3 */ +} spi_ssel_t; + +/*! @brief ssel polarity */ +typedef enum _spi_spol +{ + kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), + kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), + kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), + kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), + kSPI_SpolActiveAllHigh = + (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), + kSPI_SpolActiveAllLow = 0, +} spi_spol_t; + +/*! + * @brief SPI delay time configure structure. + * Note: + * The DLY register controls several programmable delays related to SPI signalling, + * it stands for how many SPI clock time will be inserted. + * The maxinun value of these delay time is 15. + */ +typedef struct _spi_delay_config +{ + uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ + uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ + uint8_t frameDelay; /*!< Delay between frame to frame. */ + uint8_t transferDelay; /*!< Delay between transfer to transfer. */ +} spi_delay_config_t; + +/*! @brief SPI master user configure structure.*/ +typedef struct _spi_master_config +{ + bool enableLoopback; /*!< Enable loopback for test purpose */ + bool enableMaster; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_ssel_t sselNum; /*!< Slave select number */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + spi_delay_config_t delayConfig; /*!< Delay configuration. */ +} spi_master_config_t; + +/*! @brief SPI slave user configure structure.*/ +typedef struct _spi_slave_config +{ + bool enableSlave; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +} spi_slave_config_t; + +/*! @brief SPI transfer status.*/ +enum _spi_status +{ + kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ + kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ + kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ + kStatus_SPI_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */ +}; + +/*! @brief SPI interrupt sources.*/ +enum _spi_interrupt_enable +{ + kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ + kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ +}; + +/*! @brief SPI status flags.*/ +enum _spi_statusflags +{ + kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ + kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ + kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ + kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ +}; + +/*! @brief SPI transfer structure */ +typedef struct _spi_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ + size_t dataSize; /*!< Transfer bytes */ +} spi_transfer_t; + +/*! @brief SPI half-duplex(master only) transfer structure */ +typedef struct _spi_half_duplex_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + size_t txDataSize; /*!< Transfer bytes for transmit */ + size_t rxDataSize; /*!< Transfer bytes */ + uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ + bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for + deassert. */ + bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ +} spi_half_duplex_transfer_t; + +/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ +typedef struct _spi_config +{ + spi_data_width_t dataWidth; + spi_ssel_t sselNum; +} spi_config_t; + +/*! @brief Master handle type */ +typedef struct _spi_master_handle spi_master_handle_t; + +/*! @brief Slave handle type */ +typedef spi_master_handle_t spi_slave_handle_t; + +/*! @brief SPI master callback for finished transmit */ +typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI slave callback for finished transmit */ +typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI transfer handle structure */ +struct _spi_master_handle +{ + uint8_t *volatile txData; /*!< Transfer buffer */ + uint8_t *volatile rxData; /*!< Receive buffer */ + volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ + volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ + volatile size_t toReceiveCount; /*!< Receive data remaining in bytes */ + size_t totalByteCount; /*!< A number of transfer bytes */ + volatile uint32_t state; /*!< SPI internal state */ + spi_master_callback_t callback; /*!< SPI callback */ + void *userData; /*!< Callback parameter */ + uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ + uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ + uint32_t configFlags; /*!< Additional option to control transfer */ + spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +}; + +#if defined(__cplusplus) +extern "C" { +#endif +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @brief Returns instance number for SPI peripheral base address. */ +uint32_t SPI_GetInstance(SPI_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + @code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config); + +/*! + * @brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to master configuration structure + * @param srcClock_Hz Source clock frequency. + */ +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + @code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + @endcode + * + * @param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); + +/*! + * @brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + @code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to slave configuration structure + */ +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); + +/*! + * @brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * @param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base); + +/*! + * @brief Enable or disable the SPI Master or Slave + * @param base SPI base pointer + * @param enable or disable ( true = enable, false = disable) + */ +static inline void SPI_Enable(SPI_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= SPI_CFG_ENABLE_MASK; + } + else + { + base->CFG &= ~SPI_CFG_ENABLE_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the status flag. + * + * @param base SPI base pointer + * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. + */ +static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFOSTAT; +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENSET = irqs; +} + +/*! + * @brief Disables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENCLR = irqs; +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DMA request from SPI txFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableTxDMA(SPI_Type *base, bool enable); + +/*! + * @brief Enables the DMA request from SPI rxFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableRxDMA(SPI_Type *base, bool enable); + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ +/*! + * @brief Returns the configurations. + * + * @param base SPI peripheral address. + * @return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ +void *SPI_GetConfig(SPI_Type *base); + +/*! + * @brief Sets the baud rate for SPI transfer. This is only used in master. + * + * @param base SPI base pointer + * @param baudrate_Bps baud rate needed in Hz. + * @param srcClock_Hz SPI source clock frequency in Hz. + */ +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Writes a data into the SPI data register. + * + * @param base SPI base pointer + * @param data needs to be write. + * @param configFlags transfer configuration options @ref spi_xfer_option_t + */ +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); + +/*! + * @brief Gets a data from the SPI data register. + * + * @param base SPI base pointer + * @return Data in the register. + */ +static inline uint32_t SPI_ReadData(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFORD; +} + +/*! + * @brief Set delay time for transfer. + * the delay uint is SPI clock time, maximum value is 0xF. + * @param base SPI base pointer + * @param config configuration for delay option @ref spi_delay_config_t. + */ +static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) +{ + assert(NULL != base); + assert(NULL != config); + base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | + SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); +} + +/*! + * @brief Set up the dummy data. + * + * @param base SPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData); + +/*! + * @brief Transfers a block of data using a polling method. + * + * @param base SPI base pointer + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * @param base SPI base pointer + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); + +/*! + * @brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Interrupts the handler for the SPI. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Initializes the SPI slave handle. + * + * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, + spi_slave_handle_t *handle, + spi_slave_callback_t callback, + void *userData) +{ + return SPI_MasterTransferCreateHandle(base, handle, callback, userData); +} + +/*! + * @brief Performs a non-blocking SPI slave interrupt transfer. + * + * @note The API returns immediately after the transfer initialization is finished. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferNonBlocking(base, handle, xfer); +} + +/*! + * @brief Gets the slave transfer count. + * + * This function gets the slave transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); +} + +/*! + * @brief SPI slave aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. + */ +static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); +} + +/*! + * @brief Interrupts a handler for the SPI slave. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_slave_handle_t structure which stores the transfer state + */ +static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferHandleIRQ(base, handle); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_H_*/ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.c new file mode 100644 index 00000000000..f28c0b070fd --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.c @@ -0,0 +1,526 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_spi_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" +#endif + +/*configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0; + *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0; +} + +static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) +{ + *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum))); + /* set width of data - range asserted at entry */ + *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); +} + +static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) +{ + if (config->dataWidth > kSPI_Data8Bits) + { + *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1] << 8U) | (xfer->txData[xfer->dataSize - 2])); + } + else + { + *txLastWord = xfer->txData[xfer->dataSize - 1]; + } + XferToFifoWR(xfer, txLastWord); + SpiConfigToFifoWR(config, txLastWord); +} + +static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) +{ + uint32_t instance = SPI_GetInstance(base); + dummy->word = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + XferToFifoWR(xfer, &dummy->word); + XferToFifoWR(xfer, &dummy->lastWord); + SpiConfigToFifoWR(spi_config_p, &dummy->word); + SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); + /* Clear the end of transfer bit for continue word transfer. */ + dummy->word &= (uint32_t)(~kSPI_FrameAssert); +} + +status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + int32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + instance = SPI_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + /* Set spi base to handle */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle */ + handle->state = kSPI_Idle; + + /* Set handle to global state */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + /* Install callback for Tx dma channel */ + DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); + DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); + + return kStatus_Success; +} + +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + int32_t instance; + status_t result = kStatus_Success; + spi_config_t *spi_config_p; + + assert(!((NULL == handle) || (NULL == xfer))); + if ((NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + + /* Byte size is zero. */ + assert(!(xfer->dataSize == 0)); + if (xfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + /* cannot get instance from base address */ + instance = SPI_GetInstance(base); + assert(!(instance < 0)); + if (instance < 0) + { + return kStatus_InvalidArgument; + } + + /* Check if the device is busy */ + if (handle->state == kSPI_Busy) + { + return kStatus_SPI_Busy; + } + else + { + uint32_t tmp; + dma_transfer_config_t xferConfig = {0}; + spi_config_p = (spi_config_t *)SPI_GetConfig(base); + + handle->state = kStatus_SPI_Busy; + handle->transferSize = xfer->dataSize; + + /* receive */ + SPI_EnableRxDMA(base, true); + if (xfer->rxData) + { + DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->rxData, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); + } + else + { + DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), &s_rxDummy, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); + } + DMA_SubmitTransfer(handle->rxHandle, &xferConfig); + handle->rxInProgress = true; + DMA_StartTransfer(handle->rxHandle); + + /* transmit */ + SPI_EnableTxDMA(base, true); + + if (xfer->configFlags & kSPI_FrameAssert) + { + PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); + } + + if (xfer->txData) + { + /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma + * descriptor to send the last data. + */ + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) + { + dma_xfercfg_t tmp_xfercfg = {0}; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], + ((void *)((uint32_t)&base->FIFOWR)), NULL); + + DMA_PrepareTransfer( + &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice. */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_MemoryToPeripheral, NULL); + DMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + } + else + { + /* Setup tx dummy data. */ + SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) + { + dma_xfercfg_t tmp_xfercfg = {0}; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, + (void *)((uint32_t)&base->FIFOWR), NULL); + /* Use common API to setup first descriptor */ + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + } + + handle->txInProgress = true; + tmp = 0; + XferToFifoWR(xfer, &tmp); + SpiConfigToFifoWR(spi_config_p, &tmp); + + /* Setup the control info. + * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. + * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR + * will push the data and the current control bits into the FIFO. + */ + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) + { + *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); + } + else + { + /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ + tmp &= (uint32_t)(~kSPI_FrameAssert); + *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); + } + + DMA_StartTransfer(handle->txHandle); + } + + return result; +} + +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferDMA(base, handle, &tempXfer); + + return status; +} + +static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* change the state */ + spiHandle->rxInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = kSPI_Idle; + if (spiHandle->callback) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* change the state */ + spiHandle->txInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = kSPI_Idle; + if (spiHandle->callback) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + assert(NULL != handle); + + /* Stop tx transfer first */ + DMA_AbortTransfer(handle->txHandle); + /* Then rx transfer */ + DMA_AbortTransfer(handle->rxHandle); + + /* Set the handle state */ + handle->txInProgress = false; + handle->rxInProgress = false; + handle->state = kSPI_Idle; +} + +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); + + *count = handle->transferSize - bytes; + + return kStatus_Success; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.h new file mode 100644 index 00000000000..73f016d40ac --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_spi_dma.h @@ -0,0 +1,234 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SPI_DMA_H_ +#define _FSL_SPI_DMA_H_ + +#include "fsl_dma.h" +#include "fsl_spi.h" + +/*! + * @addtogroup spi_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI DMA driver version 2.0.2. */ +#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +typedef struct _spi_dma_handle spi_dma_handle_t; + +/*! @brief SPI DMA callback called at the end of transfer. */ +typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ +struct _spi_dma_handle +{ + volatile bool txInProgress; /*!< Send transfer finished */ + volatile bool rxInProgress; /*!< Receive transfer finished */ + dma_handle_t *txHandle; /*!< DMA handler for SPI send */ + dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI tranfer */ + spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ + uint32_t state; /*!< Internal state of SPI DMA transfer */ + size_t transferSize; /*!< Bytes need to be transfer */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DMA Transactional + * @{ + */ + +/*! + * @brief Initialize the SPI master DMA handle. + * + * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle); + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI base pointer + * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * @param transfer A pointer to the spi_half_duplex_transfer_t structure. + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Initialize the SPI slave DMA handle. + * + * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferDMA(base, handle, xfer); +} + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); + +/*! + * @brief Gets the master DMA transfer remaining bytes. + * + * This function gets the master DMA transfer remaining bytes. + * + * @param base SPI peripheral base address. + * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * @param count A number of bytes transferred by the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + SPI_MasterTransferAbortDMA(base, handle); +} + +/*! + * @brief Gets the slave DMA transfer remaining bytes. + * + * This function gets the slave DMA transfer remaining bytes. + * + * @param base SPI peripheral base address. + * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * @param count A number of bytes transferred by the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCountDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.c new file mode 100644 index 00000000000..1117fac7786 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.c @@ -0,0 +1,718 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_flexcomm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" +#endif + + +enum _usart_transfer_states +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief IRQ name array */ +static const IRQn_Type s_usartIRQ[] = USART_IRQS; + +/*! @brief Array to map USART instance number to base address. */ +static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the USART */ +uint32_t USART_GetInstance(USART_Type *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++) + { + if ((uint32_t)base == s_usartBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +{ + size_t size; + + /* Check arguments */ + assert(NULL != handle); + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + return size; +} + +static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) +{ + bool full; + + /* Check arguments */ + assert(NULL != handle); + + if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + /* ring buffer is ready we can start receiving data */ + base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +} + +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + + if (handle->rxState == kUSART_RxIdle) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; + } + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) +{ + int result; + + /* check arguments */ + assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to USART mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); + if (kStatus_Success != result) + { + return result; + } + + /* setup baudrate */ + result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + + if (config->enableTx) + { + /* empty and enable txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; + } + + /* empty and enable rxFIFO */ + if (config->enableRx) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; + } + /* setup configuration and enable USART */ + base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | + USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK; + return kStatus_Success; +} + +void USART_Deinit(USART_Type *base) +{ + /* Check arguments */ + assert(NULL != base); + while (!(base->STAT & USART_STAT_TXIDLE_MASK)) + { + } + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | + USART_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); + base->CFG &= ~(USART_CFG_ENABLE_MASK); +} + +void USART_GetDefaultConfig(usart_config_t *config) +{ + /* Check arguments */ + assert(NULL != config); + + /* Set always all members ! */ + config->baudRate_Bps = 115200U; + config->parityMode = kUSART_ParityDisabled; + config->stopBitCount = kUSART_OneStopBit; + config->bitCountPerChar = kUSART_8BitsPerChar; + config->loopback = false; + config->enableRx = false; + config->enableTx = false; + config->txWatermark = kUSART_TxFifo0; + config->rxWatermark = kUSART_RxFifo1; +} + +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; + uint32_t osrval, brgval, diff, baudrate; + + /* check arguments */ + assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); + if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* + * Smaller values of OSR can make the sampling position within a data bit less accurate and may + * potentially cause more noise errors or incorrect data. + */ + for (osrval = best_osrval; osrval >= 8; osrval--) + { + brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1; + if (brgval > 0xFFFF) + { + continue; + } + baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1)); + diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate; + if (diff < best_diff) + { + best_diff = diff; + best_osrval = osrval; + best_brgval = brgval; + } + } + + /* value over range */ + if (best_brgval > 0xFFFF) + { + return kStatus_USART_BaudrateNotSupport; + } + + base->OSR = best_osrval; + base->BRG = best_brgval; + return kStatus_Success; +} + +void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return; + } + /* Check whether txFIFO is enabled */ + if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) + { + return; + } + for (; length > 0; length--) + { + /* Loop until txFIFO get some space for new data */ + while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) + { + } + base->FIFOWR = *data; + data++; + } + /* Wait to finish transfer */ + while (!(base->STAT & USART_STAT_TXIDLE_MASK)) + { + } +} + +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) +{ + uint32_t status; + + /* check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + + /* Check whether rxFIFO is enabled */ + if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK)) + { + return kStatus_Fail; + } + for (; length > 0; length--) + { + /* loop until rxFIFO have some data to read */ + while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) + { + } + /* check receive status */ + status = base->STAT; + if (status & USART_STAT_FRAMERRINT_MASK) + { + base->STAT |= USART_STAT_FRAMERRINT_MASK; + return kStatus_USART_FramingError; + } + if (status & USART_STAT_PARITYERRINT_MASK) + { + base->STAT |= USART_STAT_PARITYERRINT_MASK; + return kStatus_USART_ParityError; + } + if (status & USART_STAT_RXNOISEINT_MASK) + { + base->STAT |= USART_STAT_RXNOISEINT_MASK; + return kStatus_USART_NoiseError; + } + /* check rxFIFO status */ + if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + return kStatus_USART_RxError; + } + + *data = base->FIFORD; + data++; + } + return kStatus_Success; +} + +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData) +{ + int32_t instance = 0; + + /* Check 'base' */ + assert(!((NULL == base) || (NULL == handle))); + if ((NULL == base) || (NULL == handle)) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + /* Set the TX/RX state. */ + handle->rxState = kUSART_RxIdle; + handle->txState = kUSART_TxIdle; + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base); + handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base); + + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle); + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_usartIRQ[instance]); + + return kStatus_Success; +} + +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); + if ((0 == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kUSART_TxBusy == handle->txState) + { + return kStatus_USART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kUSART_TxBusy; + /* Enable transmiter interrupt. */ + base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK; + } + return kStatus_Success; +} + +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupts */ + base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; + /* Empty txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; + + handle->txDataSize = 0; + handle->txState = kUSART_TxIdle; +} + +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if (kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); + if ((0 == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + if (kUSART_RxBusy == handle->rxState) + { + return kStatus_USART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = DisableGlobalIRQ(); + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = USART_TransferGetRxRingBufferLength(handle); + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + bytesToReceive -= bytesToCopy; + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUSART_RxBusy; + } + /* Enable IRQ if previously enabled. */ + EnableGlobalIRQ(regPrimask); + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUSART_RxBusy; + + /* Enable RX interrupt. */ + base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK; + } + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + } + return kStatus_Success; +} + +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable interrupts */ + base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; + /* Empty rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + } + + handle->rxDataSize = 0U; + handle->rxState = kUSART_RxIdle; +} + +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if (kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer); + bool sendEnabled = handle->txDataSize; + + /* If RX overrun. */ + if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) + { + /* Clear rx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxError, handle->userData); + } + } + while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) || + (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))) + { + /* Receive data */ + if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) + { + /* Receive to app bufffer if app buffer is present */ + if (handle->rxDataSize) + { + *handle->rxData = base->FIFORD; + handle->rxDataSize--; + handle->rxData++; + receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer)); + if (!handle->rxDataSize) + { + if (!handle->rxRingBuffer) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; + } + handle->rxState = kUSART_RxIdle; + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Otherwise receive to ring buffer if ring buffer is present */ + else + { + if (handle->rxRingBuffer) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); + } + } + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD; + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + } + /* Send data */ + if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) + { + base->FIFOWR = *handle->txData; + handle->txDataSize--; + handle->txData++; + sendEnabled = handle->txDataSize != 0; + if (!sendEnabled) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; + handle->txState = kUSART_TxIdle; + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } + } + } + } + + /* ring buffer is not used */ + if (NULL == handle->rxRingBuffer) + { + /* restore if rx transfer ends and rxLevel is different from default value */ + if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); + } + /* decrease level if rx transfer is bellow */ + if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1))) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1)); + } + } +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.h new file mode 100644 index 00000000000..9deb377f147 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart.h @@ -0,0 +1,667 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_USART_H_ +#define _FSL_USART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART driver version 2.0.1. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) +#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief Error codes for the USART driver. */ +enum _usart_status +{ + kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ + kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ + kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ + kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ + kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ + kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ + kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ + kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ + kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ + kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ + kStatus_USART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ +}; + +/*! @brief USART parity mode. */ +typedef enum _usart_parity_mode +{ + kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} usart_parity_mode_t; + +/*! @brief USART stop bit count. */ +typedef enum _usart_stop_bit_count +{ + kUSART_OneStopBit = 0U, /*!< One stop bit */ + kUSART_TwoStopBit = 1U, /*!< Two stop bits */ +} usart_stop_bit_count_t; + +/*! @brief USART data size. */ +typedef enum _usart_data_len +{ + kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ + kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ +} usart_data_len_t; + +/*! @brief txFIFO watermark values */ +typedef enum _usart_txfifo_watermark +{ + kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ + kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ + kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ + kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ + kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ + kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ + kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ + kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ +} usart_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _usart_rxfifo_watermark +{ + kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ + kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ + kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ + kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ + kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ + kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ + kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ + kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ +} usart_rxfifo_watermark_t; + +/*! + * @brief USART interrupt configuration structure, default settings all disabled. + */ +enum _usart_interrupt_enable +{ + kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), + kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), + kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), + kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), +}; + +/*! + * @brief USART status flags. + * + * This provides constants for the USART status flags for use in the USART functions. + */ +enum _usart_flags +{ + kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ + kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ + kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ + kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ + kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ + kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ +}; + +/*! @brief USART configuration structure. */ +typedef struct _usart_config +{ + uint32_t baudRate_Bps; /*!< USART baud rate */ + usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ + bool loopback; /*!< Enable peripheral loopback */ + bool enableRx; /*!< Enable RX */ + bool enableTx; /*!< Enable TX */ + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +} usart_config_t; + +/*! @brief USART transfer structure. */ +typedef struct _usart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} usart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_handle usart_handle_t; + +/*! @brief USART transfer callback function. */ +typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); + +/*! @brief USART handle structure. */ +struct _usart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + usart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< USART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ + + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! @brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * @code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_InvalidArgument USART base address is not valid + * @retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * @param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config); + +/*! + * @brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * @code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param baudrate_Bps USART baudrate to be set. + * @param srcClock_Hz USART clock source freqency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get USART status flags. + * + * This function get all USART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _usart_flags. To check a specific status, + * compare the return value with enumerators in @ref _usart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) + * { + * ... + * } + * @endcode + * + * @param base USART peripheral base address. + * @return USART status flags which are ORed by the enumerators in the _usart_flags. + */ +static inline uint32_t USART_GetStatusFlags(USART_Type *base) +{ + return base->FIFOSTAT; +} + +/*! + * @brief Clear USART status flags. + * + * This function clear supported USART status flags + * Flags that can be cleared or set are: + * kUSART_TxError + * kUSART_RxError + * For example: + * @code + * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) + * @endcode + * + * @param base USART peripheral base address. + * @param mask status flags to be cleared. + */ +static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) +{ + /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ + base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables USART interrupts according to the provided mask. + * + * This function enables the USART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENSET = mask & 0xF; +} + +/*! + * @brief Disables USART interrupts according to a provided mask. + * + * This function disables the USART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENCLR = mask & 0xF; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return base->FIFOINTENSET; +} + +/*! +* @brief Enable DMA for Tx +*/ +static inline void USART_EnableTxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); + } +} + +/*! +* @brief Enable DMA for Rx +*/ +static inline void USART_EnableRxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); + } +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Writes to the FIFOWR register. + * + * This function writes data to the txFIFO directly. The upper layer must ensure + * that txFIFO has space for data to write before calling this function. + * + * @param base USART peripheral base address. + * @param data The byte to write. + */ +static inline void USART_WriteByte(USART_Type *base, uint8_t data) +{ + base->FIFOWR = data; +} + +/*! + * @brief Reads the FIFORD register directly. + * + * This function reads data from the rxFIFO directly. The upper layer must + * ensure that the rxFIFO is not empty before calling this function. + * + * @param base USART peripheral base address. + * @return The byte read from USART data register. + */ +static inline uint8_t USART_ReadByte(USART_Type *base) +{ + return base->FIFORD; +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @param base USART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base USART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * @retval kStatus_USART_ParityError Noise error happened while receiving data. + * @retval kStatus_USART_NoiseError Framing error happened while receiving data. + * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * @retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the @ref kStatus_USART_TxIdle as status parameter. + * + * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure. See #usart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, + usart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to USART TX register. + * + * This function gets the number of bytes that have been written to USART TX + * register by interrupt method. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure, see #usart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_USART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.c new file mode 100644 index 00000000000..6f900e3aca4 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.c @@ -0,0 +1,270 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_dma.h" +#include "fsl_flexcomm.h" +#include "fsl_usart_dma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" +#endif + +/*base, false); + + usartPrivateHandle->handle->txState = kUSART_TxIdle; + + if (usartPrivateHandle->handle->callback) + { + usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle, + usartPrivateHandle->handle->userData); + } +} + +static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) +{ + assert(handle); + assert(param); + + usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; + + /* Disable UART RX DMA. */ + USART_EnableRxDMA(usartPrivateHandle->base, false); + + usartPrivateHandle->handle->rxState = kUSART_RxIdle; + + if (usartPrivateHandle->handle->callback) + { + usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, + usartPrivateHandle->handle->userData); + } +} + +status_t USART_TransferCreateHandleDMA(USART_Type *base, + usart_dma_handle_t *handle, + usart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + int32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + /* assign 'base' and 'handle' */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + /* set tx/rx 'idle' state */ + handle->rxState = kUSART_RxIdle; + handle->txState = kUSART_TxIdle; + + handle->callback = callback; + handle->userData = userData; + + handle->rxDmaHandle = rxDmaHandle; + handle->txDmaHandle = txDmaHandle; + + /* Configure TX. */ + if (txDmaHandle) + { + DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxDmaHandle) + { + DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); + } + + return kStatus_Success; +} + +status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) +{ + assert(handle); + assert(handle->txDmaHandle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + dma_transfer_config_t xferConfig; + status_t status; + + /* If previous TX not finished. */ + if (kUSART_TxBusy == handle->txState) + { + status = kStatus_USART_TxBusy; + } + else + { + handle->txState = kUSART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Enable DMA request from txFIFO */ + USART_EnableTxDMA(base, true); + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, xfer->data, ((void *)((uint32_t)&base->FIFOWR)), sizeof(uint8_t), + xfer->dataSize, kDMA_MemoryToPeripheral, NULL); + + /* Submit transfer. */ + DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + DMA_StartTransfer(handle->txDmaHandle); + + status = kStatus_Success; + } + + return status; +} + +status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) +{ + assert(handle); + assert(handle->rxDmaHandle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + dma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if (kUSART_RxBusy == handle->rxState) + { + status = kStatus_USART_RxBusy; + } + else + { + handle->rxState = kUSART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Enable DMA request from rxFIFO */ + USART_EnableRxDMA(base, true); + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->data, sizeof(uint8_t), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); + + /* Submit transfer. */ + DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + DMA_StartTransfer(handle->rxDmaHandle); + + status = kStatus_Success; + } + + return status; +} + +void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->txDmaHandle); + handle->txState = kUSART_TxIdle; +} + +void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + handle->rxState = kUSART_RxIdle; +} + +status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(handle->rxDmaHandle); + assert(count); + + if (kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.h new file mode 100644 index 00000000000..029f815dd48 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_usart_dma.h @@ -0,0 +1,187 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_USART_DMA_H_ +#define _FSL_USART_DMA_H_ + +#include "fsl_common.h" +#include "fsl_dma.h" +#include "fsl_usart.h" + +/*! + * @addtogroup usart_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART dma driver version 2.0.1. */ +#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_dma_handle usart_dma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, + usart_dma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief UART DMA handle +*/ +struct _usart_dma_handle +{ + USART_Type *base; /*!< UART peripheral base address. */ + + usart_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name DMA transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle which is used in transactional functions. + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txDmaHandle User-requested DMA handle for TX DMA transfer. + * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t USART_TransferCreateHandleDMA(USART_Type *base, + usart_dma_handle_t *handle, + usart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART DMA transfer structure. See #usart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_USART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer USART DMA transfer structure. See #usart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_USART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * @param base USART peripheral base address + * @param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); + +/*! + * @brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * @param base USART peripheral base address + * @param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.c new file mode 100644 index 00000000000..5c14d2ebf33 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.c @@ -0,0 +1,180 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_utick.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.utick" +#endif + + +/* Typedef for interrupt handler. */ +typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base UTICK peripheral base address + * + * @return The UTICK instance + */ +static uint32_t UTICK_GetInstance(UTICK_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UTICK handle. */ +static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; +/* Array of UTICK peripheral base address. */ +static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; +/* Array of UTICK IRQ number. */ +static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of UTICK clock name. */ +static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/* UTICK ISR for transactional APIs. */ +static utick_isr_t s_utickIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t UTICK_GetInstance(UTICK_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) + { + if (s_utickBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_utickBases)); + + return instance; +} + +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) +{ + uint32_t instance; + + /* Get instance from peripheral base address. */ + instance = UTICK_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_utickHandle[instance] = cb; + EnableDeepSleepIRQ(s_utickIRQ[instance]); + base->CTRL = count | UTICK_CTRL_REPEAT(mode); +} + +void UTICK_Init(UTICK_Type *base) +{ + /* Enable utick clock */ + CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); + /* Power up Watchdog oscillator*/ + POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); + s_utickIsr = UTICK_HandleIRQ; +} + +void UTICK_Deinit(UTICK_Type *base) +{ + /* Turn off utick */ + base->CTRL = 0; + /* Disable utick clock */ + CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); +} + +uint32_t UTICK_GetStatusFlags(UTICK_Type *base) +{ + return (base->STAT); +} + +void UTICK_ClearStatusFlags(UTICK_Type *base) +{ + base->STAT = UTICK_STAT_INTR_MASK; +} + +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) +{ + UTICK_ClearStatusFlags(base); + if (cb) + { + cb(); + } +} + +#if defined(UTICK0) +void UTICK0_DriverIRQHandler(void) +{ + s_utickIsr(UTICK0, s_utickHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#if defined(UTICK1) +void UTICK1_DriverIRQHandler(void) +{ + s_utickIsr(UTICK1, s_utickHandle[1]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#if defined(UTICK2) +void UTICK2_DriverIRQHandler(void) +{ + s_utickIsr(UTICK2, s_utickHandle[2]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.h new file mode 100644 index 00000000000..5cc3791b463 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_utick.h @@ -0,0 +1,144 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_UTICK_H_ +#define _FSL_UTICK_H_ + +#include "fsl_common.h" +/*! + * @addtogroup utick + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief UTICK driver version 2.0.0. */ +#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief UTICK timer operational mode. */ +typedef enum _utick_mode +{ + kUTICK_Onetime = 0x0U, /*!< Trigger once*/ + kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ +} utick_mode_t; + +/*! @brief UTICK callback function. */ +typedef void (*utick_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! +* @brief Initializes an UTICK by turning its bus clock on +* +*/ +void UTICK_Init(UTICK_Type *base); + +/*! + * @brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * @param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base); +/*! + * @brief Get Status Flags. + * + * This returns the status flag + * + * @param base UTICK peripheral base address. + * @return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base); +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * @param base UTICK peripheral base address. + * @return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base); + +/*! + * @brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * @param base UTICK peripheral base address. + * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * @return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); +/*! + * @brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base UTICK peripheral base address. + * @param cb callback scheduled for this instance of UTICK + * @return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.c new file mode 100644 index 00000000000..c793559492a --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.c @@ -0,0 +1,203 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_wwdt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wwdt" +#endif + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base WWDT peripheral base address + * + * @return The WWDT instance + */ +static uint32_t WWDT_GetInstance(WWDT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to WWDT bases for each instance. */ +static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to WWDT clocks for each instance. */ +static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) +/*! @brief Pointers to WWDT resets for each instance. */ +static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WWDT_GetInstance(WWDT_Type *base) +{ + uint32_t instance; + uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < wwdtArrayCount; instance++) + { + if (s_wwdtBases[instance] == base) + { + break; + } + } + + assert(instance < wwdtArrayCount); + + return instance; +} + +/******************************************************************************* + * Code + ******************************************************************************/ + +void WWDT_GetDefaultConfig(wwdt_config_t *config) +{ + assert(config); + + /* Enable the watch dog */ + config->enableWwdt = true; + /* Disable the watchdog timeout reset */ + config->enableWatchdogReset = false; + /* Disable the watchdog protection for updating the timeout value */ + config->enableWatchdogProtect = false; + /* Do not lock the watchdog oscillator */ + config->enableLockOscillator = false; + /* Windowing is not in effect */ + config->windowValue = 0xFFFFFFU; + /* Set the timeout value to the max */ + config->timeoutValue = 0xFFFFFFU; + /* No warning is provided */ + config->warningValue = 0; +} + +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + uint32_t timeDelay = 0U; + uint32_t srcClock_Hz = 0U; + +#if defined(FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE) && FSL_FEATURE_WWDT_HAS_LPOSC_CLOCK_SOURCE + srcClock_Hz = CLOCK_GetFreq(kCLOCK_LPOsc); +#else + srcClock_Hz = CLOCK_GetFreq(kCLOCK_WdtOsc); +#endif + + timeDelay = (SystemCoreClock / srcClock_Hz + 1) * 3; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the WWDT clock */ + CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) + /* Reset the WWDT module */ + RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); +#endif + + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | + WWDT_MOD_LOCK(config->enableLockOscillator); + /* Set configruation */ + base->TC = WWDT_TC_COUNT(config->timeoutValue); + base->MOD |= value; + base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); + base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); + WWDT_Refresh(base); + /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ + if((base->MOD & WWDT_MOD_WDPROTECT_MASK) == 0U) + { + /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ + while (timeDelay--) + { + __NOP(); + } + base->MOD |= WWDT_MOD_WDPROTECT(config->enableWatchdogProtect); + } +} + +void WWDT_Deinit(WWDT_Type *base) +{ + WWDT_Disable(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the WWDT clock */ + CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void WWDT_Refresh(WWDT_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); +} + +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) +{ + /* Clear the WDINT bit so that we don't accidentally clear it */ + uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); + + /* Clear timeout by writing a zero */ + if (mask & kWWDT_TimeoutFlag) + { + reg &= ~WWDT_MOD_WDTOF_MASK; + } + + /* Clear warning interrupt flag by writing a one */ + if (mask & kWWDT_WarningFlag) + { + reg |= WWDT_MOD_WDINT_MASK; + } + + base->MOD = reg; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.h new file mode 100644 index 00000000000..938be6a8604 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/drivers/fsl_wwdt.h @@ -0,0 +1,287 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_WWDT_H_ +#define _FSL_WWDT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wwdt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WWDT driver version 2.0.0. */ +#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name Refresh sequence */ +/*@{*/ +#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ +#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ +/*@}*/ + +/*! @brief Describes WWDT configuration structure. */ +typedef struct _wwdt_config +{ + bool enableWwdt; /*!< Enables or disables WWDT */ + bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset + false: Watchdog timeout will not cause a chip reset */ + bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be + changed after counter is below warning & window values + false: Disable watchdog protect; timeout value can be changed + at any time */ + bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented + Once set, this bit can only be cleared by a reset + false: Do not lock oscillator */ + uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ + uint32_t timeoutValue; /*!< Timeout value */ + uint32_t warningValue; /*!< Watchdog time counter value that will generate a + warning interrupt. Set this to 0 for no warning */ + +} wwdt_config_t; + +/*! + * @brief WWDT status flags. + * + * This structure contains the WWDT status flags for use in the WWDT functions. + */ +enum _wwdt_status_flags_t +{ + kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ + kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WWDT Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes WWDT configure sturcture. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * @code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * @endcode + * + * @param config Pointer to WWDT config structure. + * @see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config); + +/*! + * @brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * @code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * @endcode + * + * @param base WWDT peripheral base address + * @param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); + +/*! + * @brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * @param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base); + +/* @} */ + +/*! + * @name WWDT Functional Operation + * @{ + */ + +/*! + * @brief Enables the WWDT module. + * + * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; + * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run + * permanently. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Enable(WWDT_Type *base) +{ + base->MOD |= WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Disables the WWDT module. + * + * This function write value into WWDT_MOD register to disable the WWDT. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Disable(WWDT_Type *base) +{ + base->MOD &= ~WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Gets all WWDT status flags. + * + * This function gets all status flags. + * + * Example for getting Timeout Flag: + * @code + * uint32_t status; + * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; + * @endcode + * @param base WWDT peripheral base address + * @return The status flags. This is the logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) +{ + return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); +} + +/*! + * @brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * @code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * @endcode + * @param base WWDT peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); + +/*! + * @brief Set the WWDT warning value. + * + * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog + * interrupt. When the watchdog timer counter is no longer greater than the value defined by + * WARNINT, an interrupt will be generated after the subsequent WDCLK. + * + * @param base WWDT peripheral base address + * @param warningValue WWDT warning value. + */ +static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) +{ + base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); +} + +/*! + * @brief Set the WWDT timeout value. + * + * This function sets the timeout value. Every time a feed sequence occurs the value in the TC + * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be + * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. + * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change + * the timeout value before the watchdog counter is below the warning and window values + * will cause a watchdog reset and set the WDTOF flag. + * + * @param base WWDT peripheral base address + * @param timeoutCount WWDT timeout value, count of WWDT clock tick. + */ +static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) +{ + base->TC = WWDT_TC_COUNT(timeoutCount); +} + +/*! + * @brief Sets the WWDT window value. + * + * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. + * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog + * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer + * value) so windowing is not in effect. + * + * @param base WWDT peripheral base address + * @param windowValue WWDT window value. + */ +static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) +{ + base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); +} + +/*! + * @brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/fsl_device_registers.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/fsl_device_registers.h new file mode 100644 index 00000000000..18ee36a30c2 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/fsl_device_registers.h @@ -0,0 +1,70 @@ +/* + * The Clear BSD License + * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_LPC54114J256BD64_cm4) || defined(CPU_LPC54114J256UK49_cm4)) + +#define LPC54114_cm4_SERIES + +/* CMSIS-style register definitions */ +#include "LPC54114_cm4.h" +/* CPU specific feature definitions */ +#include "LPC54114_cm4_features.h" + +#elif (defined(CPU_LPC54114J256BD64_cm0plus) || defined(CPU_LPC54114J256UK49_cm0plus)) + +#define LPC54114_cm0plus_SERIES + +/* CMSIS-style register definitions */ +#include "LPC54114_cm0plus.h" +/* CPU specific feature definitions */ +#include "LPC54114_cm0plus_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_flash.ld b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_flash.ld new file mode 100644 index 00000000000..d4139e668f9 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_flash.ld @@ -0,0 +1,234 @@ +/* +** ################################################################### +** Processors: LPC54114J256_cm0plus +** +** Compiler: GNU C Compiler +** Reference manual: LPC54114 Series Reference Manual, Rev. 0 , 11/2016 +** Version: rev. 1.0, 2016-11-02 +** Build: b161214 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x20010000, LENGTH = 0x000000C0 + m_text (RX) : ORIGIN = 0x200100C0, LENGTH = 0x0000FF3F + m_data (RW) : ORIGIN = 0x20020000, LENGTH = 0x00007FFF - RPMSG_SHMEM_SIZE + rpmsg_sh_mem (RW) : ORIGIN = 0x20026800, LENGTH = RPMSG_SHMEM_SIZE +} + +/* Define output sections */ +SECTIONS +{ + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_ram.ld b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_ram.ld new file mode 100644 index 00000000000..ff6068634ba --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm0plus_ram.ld @@ -0,0 +1,264 @@ +/* +** ################################################################### +** Processors: LPC54114J256_cm0plus +** +** Compiler: GNU C Compiler +** Reference manual: LPC54114 Series Reference Manual, Rev. 0 , 11/2016 +** Version: rev. 1.0, 2016-11-02 +** Build: b161214 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** The Clear BSD License +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright (c) 2016 - 2017 , NXP +** All rights reserved. +** +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x20010000, LENGTH = 0x000000C0 + m_text (RX) : ORIGIN = 0x200100C0, LENGTH = 0x0000FF3F + m_data (RW) : ORIGIN = 0x20020000, LENGTH = 0x00007FFF - RPMSG_SHMEM_SIZE + rpmsg_sh_mem (RW) : ORIGIN = 0x20026800, LENGTH = RPMSG_SHMEM_SIZE +} + +/* Define output sections */ +SECTIONS +{ + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm4_ram.ld b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm4_ram.ld new file mode 100644 index 00000000000..2c00abef81f --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/LPC54114J256_cm4_ram.ld @@ -0,0 +1,257 @@ +/* +** ################################################################### +** Processors: LPC54114J256_cm4 +** +** Compiler: GNU C Compiler +** Reference manual: LPC54114 Series Reference Manual, Rev. 0 , 11/2016 +** Version: rev. 1.0, 2016-11-02 +** Build: b161214 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** The Clear BSD License +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright (c) 2016 - 2017 , NXP +** All rights reserved. +** +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x20000000, LENGTH = 0x000000E0 + m_text (RX) : ORIGIN = 0x200000E0, LENGTH = 0x0001FF20 + m_data (RW) : ORIGIN = 0x20020000, LENGTH = 0x00008000 +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/SConscript b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/SConscript new file mode 100644 index 00000000000..76e31c367b5 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = Split(''' +startup_LPC54114_cm4.s +''') + +group = DefineGroup('Libraries', src, depend = [''], LIBS=['libpower_cm4_hardabi'], LIBPATH=[cwd]) + +Return('group') diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm0plus.S b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm0plus.S new file mode 100644 index 00000000000..d79fe51d77e --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm0plus.S @@ -0,0 +1,644 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_LPC54114_cm0plus.S */ +/* @purpose: CMSIS Cortex-M0 Core Device Startup File */ +/* LPC54114_cm0plus */ +/* @version: 1.0 */ +/* @date: 2016-11-2 */ +/* @build: b161214 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* The Clear BSD License */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2017 NXP */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted (subject to the limitations in the disclaimer below) provided */ +/* that the following conditions are met: */ +/* */ +/* 1. Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* 2. Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* 3. Neither the name of the copyright holder nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE.*/ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long WDT_BOD_IRQHandler /* Watchdog Timer, Brownout detect */ + .long DMA0_IRQHandler /* DMA controller interrupt */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1 or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, FLEXCOMM) */ + .long ADC0_SEQA_IRQHandler /* ADC0 sequence A completion */ + .long ADC0_SEQB_IRQHandler /* ADC0 sequence B completion */ + .long ADC0_THCMP_IRQHandler /* ADC0 threshold compare and error. */ + .long DMIC0_IRQHandler /* RTC alarm and wake-up interrupts */ + .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long IOH_IRQHandler /* IOH interrupt */ + .long MAILBOX_IRQHandler /* Mailbox interrupt */ + .size __Vectors, . - __Vectors + + + + .text + .thumb +#ifndef SLAVEBOOT +rel_vals: + .long 0xE000ED00 /* cpu_id */ + .long 0x40000800 /* cpu_ctrl */ + .long 0x40000804 /* coproc_boot */ + .long 0x40000808 /* coproc_stack */ + .short 0x0FFF + .short 0x0C24 +#endif +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: +#ifndef SLAVEBOOT +/* Both the M0+ and M4 core come via this shared startup code, + * but the M0+ and M4 core have different vector tables. + * Determine if the core executing this code is the master or + * the slave and handle each core state individually. */ + +shared_boot_entry: + ldr r6, =rel_vals + + /* Flag for slave core (0) */ + movs r4, 0 + movs r5, 1 + + /* Determine which core (M0+ or M4) this code is running on */ + /* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */ +get_current_core_id: + ldr r0, [r6, #0] + ldr r1, [r0] /* r1 = CPU ID status */ + lsrs r1, r1, #4 /* Right justify 12 CPU ID bits */ + ldrh r2, [r6, #16] /* Mask for CPU ID bits */ + ands r2, r1, r2 /* r2 = ARM COrtex CPU ID */ + ldrh r3, [r6, #18] /* Mask for CPU ID bits */ + cmp r3, r2 /* Core ID matches M4 identifier */ + bne get_master_status + mov r4, r5 /* Set flag for master core (1) */ + + /* Determine if M4 core is the master or slave */ + /* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */ +get_master_status: + ldr r0, [r6, #4] + ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */ + + ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */ + + /* Select boot based on selected master core and core ID */ + +select_boot: + eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */ + + bne slave_boot + b normal_boot + + /* Slave boot */ +slave_boot: + ldr r0, [r6, #8] + ldr r2, [r0] /* r1 = SYSCON co-processor boot address */ + + cmp r2, #0 /* Slave boot address = 0 (not set up)? */ + + beq cpu_sleep + ldr r0, [r6, #12] + ldr r1, [r0] /* r5 = SYSCON co-processor stack address */ + + mov sp, r1 /* Update slave CPU stack pointer */ + + /* Be sure to update VTOR for the slave MCU to point to the */ + /* slave vector table in boot memory */ + bx r2 /* Jump to slave boot address */ + + /* Slave isn't yet setup for system boot from the master */ + /* so sleep until the master sets it up and then reboots it */ +cpu_sleep: + mov sp, r5 /* Will force exception if something happens */ +cpu_sleep_wfi: + wfi /* Sleep forever until master reboots */ + b cpu_sleep_wfi +#endif /* defined(SLAVEBOOT) */ + +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ +normal_boot: +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC0 + +.LC1: + subs r3, 4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .LC1 +.LC0: + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + subs r2, r1 + ble .LC3 + + movs r0, 0 +.LC2: + str r0, [r1, r2] + subs r2, 4 + bge .LC2 +.LC3: +#endif /* __STARTUP_CLEAR_BSS */ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + + .align 1 + .thumb_func + .weak ADC0_SEQA_IRQHandler + .type ADC0_SEQA_IRQHandler, %function +ADC0_SEQA_IRQHandler: + ldr r0,=ADC0_SEQA_DriverIRQHandler + bx r0 + .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_SEQB_IRQHandler + .type ADC0_SEQB_IRQHandler, %function +ADC0_SEQB_IRQHandler: + ldr r0,=ADC0_SEQB_DriverIRQHandler + bx r0 + .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_THCMP_IRQHandler + .type ADC0_THCMP_IRQHandler, %function +ADC0_THCMP_IRQHandler: + ldr r0,=ADC0_THCMP_DriverIRQHandler + bx r0 + .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler + + .align 1 + .thumb_func + .weak DMIC0_IRQHandler + .type DMIC0_IRQHandler, %function +DMIC0_IRQHandler: + ldr r0,=DMIC0_DriverIRQHandler + bx r0 + .size DMIC0_IRQHandler, . - DMIC0_IRQHandler + + .align 1 + .thumb_func + .weak HWVAD0_IRQHandler + .type HWVAD0_IRQHandler, %function +HWVAD0_IRQHandler: + ldr r0,=HWVAD0_DriverIRQHandler + bx r0 + .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak IOH_IRQHandler + .type IOH_IRQHandler, %function +IOH_IRQHandler: + ldr r0,=IOH_DriverIRQHandler + bx r0 + .size IOH_IRQHandler, . - IOH_IRQHandler + + .align 1 + .thumb_func + .weak MAILBOX_IRQHandler + .type MAILBOX_IRQHandler, %function +MAILBOX_IRQHandler: + ldr r0,=MAILBOX_DriverIRQHandler + bx r0 + .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect */ + def_irq_handler DMA0_DriverIRQHandler /* DMA controller */ + def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ + def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ + def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ + def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ + def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ + def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ + def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ + def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ + def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ + def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ + def_irq_handler ADC0_SEQA_DriverIRQHandler /* ADC0 sequence A completion. */ + def_irq_handler ADC0_SEQB_DriverIRQHandler /* ADC0 sequence B completion. */ + def_irq_handler ADC0_THCMP_DriverIRQHandler /* ADC0 threshold compare and error. */ + def_irq_handler DMIC0_DriverIRQHandler /* Digital microphone and DMIC subsystem */ + def_irq_handler HWVAD0_DriverIRQHandler /* Hardware Voice sActivity Detector */ + def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ + def_irq_handler USB0_DriverIRQHandler /* USB device */ + def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ + def_irq_handler IOH_DriverIRQHandler /* IOH */ + def_irq_handler MAILBOX_DriverIRQHandler /* Mailbox interrupt (present on selected devices) */ + + .end diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm4.S b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm4.S new file mode 100644 index 00000000000..886df39fa8c --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/gcc/startup_LPC54114_cm4.S @@ -0,0 +1,767 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_LPC54114_cm4.S */ +/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ +/* LPC54114_cm4 */ +/* @version: 1.0 */ +/* @date: 2016-11-2 */ +/* @build: b161214 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* The Clear BSD License */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2017 NXP */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted (subject to the limitations in the disclaimer below) provided */ +/* that the following conditions are met: */ +/* */ +/* 1. Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* 2. Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* 3. Neither the name of the copyright holder nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE.*/ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long WDT_BOD_IRQHandler /* Watchdog Timer, Brownout detect */ + .long DMA0_IRQHandler /* DMA controller interrupt */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1 or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, FLEXCOMM) */ + .long ADC0_SEQA_IRQHandler /* ADC0 sequence A completion */ + .long ADC0_SEQB_IRQHandler /* ADC0 sequence B completion */ + .long ADC0_THCMP_IRQHandler /* ADC0 threshold compare and error. */ + .long DMIC0_IRQHandler /* RTC alarm and wake-up interrupts */ + .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long IOH_IRQHandler /* IOH interrupt */ + .long MAILBOX_IRQHandler /* Mailbox interrupt */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long 0 /* Reserved interrupt */ + .long SPIFI0_IRQHandler /* SPI flash interface */ + .size __Vectors, . - __Vectors + + + + .text + .thumb +#ifndef SLAVEBOOT +rel_vals: + .long 0xE000ED00 /* cpu_id */ + .long 0x40000800 /* cpu_ctrl */ + .long 0x40000804 /* coproc_boot */ + .long 0x40000808 /* coproc_stack */ + .short 0x0FFF + .short 0x0C24 +#endif +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: +#ifndef SLAVEBOOT +/* Both the M0+ and M4 core come via this shared startup code, + * but the M0+ and M4 core have different vector tables. + * Determine if the core executing this code is the master or + * the slave and handle each core state individually. */ + +shared_boot_entry: + ldr r6, =rel_vals + + /* Flag for slave core (0) */ + movs r4, 0 + movs r5, 1 + + /* Determine which core (M0+ or M4) this code is running on */ + /* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */ +get_current_core_id: + ldr r0, [r6, #0] + ldr r1, [r0] /* r1 = CPU ID status */ + lsrs r1, r1, #4 /* Right justify 12 CPU ID bits */ + ldrh r2, [r6, #16] /* Mask for CPU ID bits */ + ands r2, r1, r2 /* r2 = ARM COrtex CPU ID */ + ldrh r3, [r6, #18] /* Mask for CPU ID bits */ + cmp r3, r2 /* Core ID matches M4 identifier */ + bne get_master_status + mov r4, r5 /* Set flag for master core (1) */ + + /* Determine if M4 core is the master or slave */ + /* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */ +get_master_status: + ldr r0, [r6, #4] + ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */ + + ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */ + + /* Select boot based on selected master core and core ID */ + +select_boot: + eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */ + + bne slave_boot + b normal_boot + + /* Slave boot */ +slave_boot: + ldr r0, [r6, #8] + ldr r2, [r0] /* r1 = SYSCON co-processor boot address */ + + cmp r2, #0 /* Slave boot address = 0 (not set up)? */ + + beq cpu_sleep + ldr r0, [r6, #12] + ldr r1, [r0] /* r5 = SYSCON co-processor stack address */ + + mov sp, r1 /* Update slave CPU stack pointer */ + + /* Be sure to update VTOR for the slave MCU to point to the */ + /* slave vector table in boot memory */ + bx r2 /* Jump to slave boot address */ + + /* Slave isn't yet setup for system boot from the master */ + /* so sleep until the master sets it up and then reboots it */ +cpu_sleep: + mov sp, r5 /* Will force exception if something happens */ +cpu_sleep_wfi: + wfi /* Sleep forever until master reboots */ + b cpu_sleep_wfi +#endif /* defined(SLAVEBOOT) */ + +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ +normal_boot: +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + ldr r0,=entry + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + ldr r0,=MemManage_Handler + bx r0 + .size MemManage_Handler, . - MemManage_Handler + + .align 1 + .thumb_func + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + ldr r0,=BusFault_Handler + bx r0 + .size BusFault_Handler, . - BusFault_Handler + + .align 1 + .thumb_func + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + ldr r0,=UsageFault_Handler + bx r0 + .size UsageFault_Handler, . - UsageFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + ldr r0,=DebugMon_Handler + bx r0 + .size DebugMon_Handler, . - DebugMon_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + + .align 1 + .thumb_func + .weak ADC0_SEQA_IRQHandler + .type ADC0_SEQA_IRQHandler, %function +ADC0_SEQA_IRQHandler: + ldr r0,=ADC0_SEQA_DriverIRQHandler + bx r0 + .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_SEQB_IRQHandler + .type ADC0_SEQB_IRQHandler, %function +ADC0_SEQB_IRQHandler: + ldr r0,=ADC0_SEQB_DriverIRQHandler + bx r0 + .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_THCMP_IRQHandler + .type ADC0_THCMP_IRQHandler, %function +ADC0_THCMP_IRQHandler: + ldr r0,=ADC0_THCMP_DriverIRQHandler + bx r0 + .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler + + .align 1 + .thumb_func + .weak DMIC0_IRQHandler + .type DMIC0_IRQHandler, %function +DMIC0_IRQHandler: + ldr r0,=DMIC0_DriverIRQHandler + bx r0 + .size DMIC0_IRQHandler, . - DMIC0_IRQHandler + + .align 1 + .thumb_func + .weak HWVAD0_IRQHandler + .type HWVAD0_IRQHandler, %function +HWVAD0_IRQHandler: + ldr r0,=HWVAD0_DriverIRQHandler + bx r0 + .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak IOH_IRQHandler + .type IOH_IRQHandler, %function +IOH_IRQHandler: + ldr r0,=IOH_DriverIRQHandler + bx r0 + .size IOH_IRQHandler, . - IOH_IRQHandler + + .align 1 + .thumb_func + .weak MAILBOX_IRQHandler + .type MAILBOX_IRQHandler, %function +MAILBOX_IRQHandler: + ldr r0,=MAILBOX_DriverIRQHandler + bx r0 + .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler + + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + + .align 1 + .thumb_func + .weak SPIFI0_IRQHandler + .type SPIFI0_IRQHandler, %function +SPIFI0_IRQHandler: + ldr r0,=SPIFI0_DriverIRQHandler + bx r0 + .size SPIFI0_IRQHandler, . - SPIFI0_IRQHandler +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect */ + def_irq_handler DMA0_DriverIRQHandler /* DMA controller */ + def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ + def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ + def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ + def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ + def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ + def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ + def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ + def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ + def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C) */ + def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ + def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ + def_irq_handler ADC0_SEQA_DriverIRQHandler /* ADC0 sequence A completion. */ + def_irq_handler ADC0_SEQB_DriverIRQHandler /* ADC0 sequence B completion. */ + def_irq_handler ADC0_THCMP_DriverIRQHandler /* ADC0 threshold compare and error. */ + def_irq_handler DMIC0_DriverIRQHandler /* Digital microphone and DMIC subsystem */ + def_irq_handler HWVAD0_DriverIRQHandler /* Hardware Voice Activity Detector */ + def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ + def_irq_handler USB0_DriverIRQHandler /* USB device */ + def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ + def_irq_handler IOH_DriverIRQHandler /* IOH */ + def_irq_handler MAILBOX_DriverIRQHandler /* Mailbox interrupt (present on selected devices) */ + def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ + def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ + def_irq_handler SPIFI0_DriverIRQHandler /* SPI flash interface */ + + .end diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf new file mode 100644 index 00000000000..3eb7d6eeb89 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus.icf @@ -0,0 +1,124 @@ +/* +** ################################################################### +** Processors: LPC54114J256BD64_M0P +** LPC54114J256UK49_M0P +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b161227 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +define symbol m_interrupts_start = 0x20010000; +define symbol m_interrupts_end = 0x200100BF; + +define symbol m_text_start = 0x200100C0; +define symbol m_text_end = 0x2001FFFF; + +if (isdefinedsymbol(__use_shmem__)) { +define symbol m_data_start = 0x20020000; +define symbol m_data_end = 0x200267FF; + +define exported symbol rpmsg_sh_mem_start = 0x20026800; +define exported symbol rpmsg_sh_mem_end = 0x20027FFF; +} else { +define symbol m_data_start = 0x20020000; +define symbol m_data_end = 0x20027FFF; +} + +define symbol m_sramx_start = 0x04000000; +define symbol m_sramx_end = 0x04007FFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0800; +} + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region SRAMX_region = mem:[from m_sramx_start to m_sramx_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +if (isdefinedsymbol(__use_shmem__)) { +define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { +do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in SRAMX_region { section sramx }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { +place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf new file mode 100644 index 00000000000..bc8768da393 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm0plus_ram.icf @@ -0,0 +1,120 @@ +/* +** ################################################################### +** Processors: LPC54114J256BD64_M0P +** LPC54114J256UK49_M0P +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b161227 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +define symbol m_interrupts_start = 0x20010000; +define symbol m_interrupts_end = 0x200100BF; + +define symbol m_text_start = 0x200100C0; +define symbol m_text_end = 0x2001FFFF; + +if (isdefinedsymbol(__use_shmem__)) { +define exported symbol rpmsg_sh_mem_start = 0x20026800; +define exported symbol rpmsg_sh_mem_end = 0x20027FFF; +define symbol m_data_start = 0x20020000; +define symbol m_data_end = 0x200267FF; +} else { +define symbol m_data_start = 0x20020000; +define symbol m_data_end = 0x20027FFF; +} + +define symbol m_sramx_start = 0x04000000; +define symbol m_sramx_end = 0x04007FFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0800; +} + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region SRAMX_region = mem:[from m_sramx_start to m_sramx_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { +define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit }; +do not initialize { section rpmsg_sh_mem_section }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in SRAMX_region { section sramx }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { +place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf new file mode 100644 index 00000000000..fb096f80b2e --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/LPC54114J256_cm4_ram.icf @@ -0,0 +1,99 @@ +/* +** ################################################################### +** Processors: LPC54114J256BD64_M4 +** LPC54114J256UK49_M4 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b161227 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x20000000; +define symbol m_interrupts_end = 0x200000DF; + +define symbol m_text_start = 0x200000E0; +define symbol m_text_end = 0x20020000; + + +define symbol m_data_start = 0x20020000; +define symbol m_data_end = 0x20008000; + + +define symbol m_stack_start = 0x04000000; +define symbol m_stack_end = 0x04007FFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0800; +} + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region CSTACK_region = mem:[from m_stack_start to m_stack_end]; + + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/SConscript b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/SConscript new file mode 100644 index 00000000000..d89e9d26996 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = Split(''' +startup_LPC54114_cm4.s +''') + +group = DefineGroup('Libraries', src, depend = [''], LIBS=['iar_lib_power'], LIBPATH=[cwd]) + +Return('group') diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm0plus.s b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm0plus.s new file mode 100644 index 00000000000..594b30c6794 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm0plus.s @@ -0,0 +1,473 @@ +;/***************************************************************************** +; * @file: startup_LPC54114_cm0plus.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * LPC54114_cm0plus +; * @version: 1.0 +; * @date: 2016-4-29 +; *---------------------------------------------------------------------------- +; * +; * The Clear BSD License +; * Copyright 1997 - 2016 Freescale Semiconductor. +; * Copyright 2016 - 2017 NXP +; * +; * All rights reserved. +; * +; Redistribution and use in source and binary forms, with or without modification, +; are permitted (subject to the limitations in the disclaimer below) provided +; that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ; DMA controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) + DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD IOH_IRQHandler ; IOH + DCD MAILBOX_IRQHandler ; Mailbox interrupt (present on selected devices) +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + +#if !defined(SLAVEBOOT) + DATA +cpu_id EQU 0xE000ED00 ; CPUID Base Register (System control block register) +cpu_ctrl EQU 0x40000800 +coproc_boot EQU 0x40000804 +coproc_stack EQU 0x40000808 +rel_vals + DC32 cpu_id, cpu_ctrl, coproc_boot, coproc_stack + DC16 0xFFF, 0xC24 +#endif + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +; Reset Handler - shared for both cores +Reset_Handler + +#if !defined(SLAVEBOOT) +; Both the M0+ and M4 core come via this shared startup code, + ; but the M0+ and M4 core have different vector tables. + ; Determine if the core executing this code is the master or + ; the slave and handle each core state individually. +shared_boot_entry + LDR r6, =rel_vals + MOVS r4, #0 ; Flag for slave core (0) + MOVS r5, #1 + + ; Determine which core (M0+ or M4) this code is running on + ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) +get_current_core_id + LDR r0, [r6, #0] + LDR r1, [r0] ; r1 = CPU ID status + LSRS r1, r1, #4 ; Right justify 12 CPU ID bits + LDRH r2, [r6, #16] ; Mask for CPU ID bits + ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID + LDRH r3, [r6, #18] ; Mask for CPU ID bits + CMP r3, r2 ; Core ID matches M4 identifier + BNE get_master_status + MOV r4, r5 ; Set flag for master core (1) + + ; Determine if M4 core is the master or slave + ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) +get_master_status + LDR r0, [r6, #4] + LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status + ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) + + ; Select boot based on selected master core and core ID +select_boot + EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) + BNE slave_boot + B normal_boot + + ; Slave boot +slave_boot + LDR r0, [r6, #8] + LDR r2, [r0] ; r1 = SYSCON co-processor boot address + CMP r2, #0 ; Slave boot address = 0 (not set up)? + BEQ cpu_sleep + LDR r0, [r6, #12] + LDR r1, [r0] ; r5 = SYSCON co-processor stack address + MOV sp, r1 ; Update slave CPU stack pointer + ; Be sure to update VTOR for the slave MCU to point to the + ; slave vector table in boot memory + BX r2 ; Jump to slave boot address + + ; Slave isn't yet setup for system boot from the master + ; so sleep until the master sets it up and then reboots it +cpu_sleep + MOV sp, r5 ; Will force exception if something happens +cpu_sleep_wfi + WFI ; Sleep forever until master reboots + B cpu_sleep_wfi +#endif ; defined(SLAVEBOOT) + + ; Normal boot for master/slave +normal_boot + LDR r0, =SystemInit + BLX r0 + LDR r0, =__iar_program_start + BX r0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + PUBWEAK ADC0_SEQA_IRQHandler + PUBWEAK ADC0_SEQA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQA_IRQHandler + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + PUBWEAK ADC0_SEQB_IRQHandler + PUBWEAK ADC0_SEQB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQB_IRQHandler + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + PUBWEAK ADC0_THCMP_IRQHandler + PUBWEAK ADC0_THCMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_THCMP_IRQHandler + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + PUBWEAK DMIC0_IRQHandler + PUBWEAK DMIC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMIC0_IRQHandler + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + PUBWEAK HWVAD0_IRQHandler + PUBWEAK HWVAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HWVAD0_IRQHandler + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + PUBWEAK IOH_IRQHandler + PUBWEAK IOH_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +IOH_IRQHandler + LDR R0, =IOH_DriverIRQHandler + BX R0 + PUBWEAK MAILBOX_IRQHandler + PUBWEAK MAILBOX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MAILBOX_IRQHandler + LDR R0, =MAILBOX_DriverIRQHandler + BX R0 +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +IOH_DriverIRQHandler +MAILBOX_DriverIRQHandler +DefaultISR + B . + + END diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm4.s b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm4.s new file mode 100644 index 00000000000..9ef5d34e866 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/iar/startup_LPC54114_cm4.s @@ -0,0 +1,571 @@ +;/***************************************************************************** +; * @file: startup_LPC54114_cm4.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * LPC54114_cm4 +; * @version: 1.0 +; * @date: 2016-4-29 +; *---------------------------------------------------------------------------- +; * +; * The Clear BSD License +; * Copyright 1997 - 2016 Freescale Semiconductor. +; * Copyright 2016 - 2017 NXP +; * +; * All rights reserved. +; * +; Redistribution and use in source and binary forms, with or without modification, +; are permitted (subject to the limitations in the disclaimer below) provided +; that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ; DMA controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) + DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD IOH_IRQHandler ; IOH + DCD MAILBOX_IRQHandler ; Mailbox interrupt (present on selected devices) + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD Reserved54_IRQHandler ; Reserved interrupt + DCD SPIFI0_IRQHandler ; SPI flash interface +__Vectors_End + +; Code Read Protection Level (CRP) +; <0xFFFFFFFF=> Disabled +; <0x4E697370=> NO_ISP +; <0x12345678=> CRP1 +; <0x87654321=> CRP2 +; <0x43218765=> CRP3 + +#if !defined NO_CRP + SECTION .crp:CODE +__CRP + DCD 0xFFFFFFFF +__CRP_End +#endif + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + SECTION .intvec:CODE:NOROOT(2) +#if !defined(SLAVEBOOT) + DATA +cpu_id EQU 0xE000ED00 ; CPUID Base Register (System control block register) +cpu_ctrl EQU 0x40000800 +coproc_boot EQU 0x40000804 +coproc_stack EQU 0x40000808 +rel_vals + DC32 cpu_id, cpu_ctrl, coproc_boot, coproc_stack + DC16 0xFFF, 0xC24 +#endif + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +; Reset Handler - shared for both cores +Reset_Handler + +#if !defined(SLAVEBOOT) +; Both the M0+ and M4 core come via this shared startup code, + ; but the M0+ and M4 core have different vector tables. + ; Determine if the core executing this code is the master or + ; the slave and handle each core state individually. +shared_boot_entry + LDR r6, =rel_vals + MOVS r4, #0 ; Flag for slave core (0) + MOVS r5, #1 + + ; Determine which core (M0+ or M4) this code is running on + ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) +get_current_core_id + LDR r0, [r6, #0] + LDR r1, [r0] ; r1 = CPU ID status + LSRS r1, r1, #4 ; Right justify 12 CPU ID bits + LDRH r2, [r6, #16] ; Mask for CPU ID bits + ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID + LDRH r3, [r6, #18] ; Mask for CPU ID bits + CMP r3, r2 ; Core ID matches M4 identifier + BNE get_master_status + MOV r4, r5 ; Set flag for master core (1) + + ; Determine if M4 core is the master or slave + ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) +get_master_status + LDR r0, [r6, #4] + LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status + ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) + + ; Select boot based on selected master core and core ID +select_boot + EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave) + BNE slave_boot + B normal_boot + + ; Slave boot +slave_boot + LDR r0, [r6, #8] + LDR r2, [r0] ; r1 = SYSCON co-processor boot address + CMP r2, #0 ; Slave boot address = 0 (not set up)? + BEQ cpu_sleep + LDR r0, [r6, #12] + LDR r1, [r0] ; r5 = SYSCON co-processor stack address + MOV sp, r1 ; Update slave CPU stack pointer + ; Be sure to update VTOR for the slave MCU to point to the + ; slave vector table in boot memory + BX r2 ; Jump to slave boot address + + ; Slave isn't yet setup for system boot from the master + ; so sleep until the master sets it up and then reboots it +cpu_sleep + MOV sp, r5 ; Will force exception if something happens +cpu_sleep_wfi + WFI ; Sleep forever until master reboots + B cpu_sleep_wfi +#endif ; defined(SLAVEBOOT) + + ; Normal boot for master/slave +normal_boot + LDR r0, =SystemInit + BLX r0 + LDR r0, =__iar_program_start + BX r0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + PUBWEAK ADC0_SEQA_IRQHandler + PUBWEAK ADC0_SEQA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQA_IRQHandler + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + PUBWEAK ADC0_SEQB_IRQHandler + PUBWEAK ADC0_SEQB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQB_IRQHandler + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + PUBWEAK ADC0_THCMP_IRQHandler + PUBWEAK ADC0_THCMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_THCMP_IRQHandler + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + PUBWEAK DMIC0_IRQHandler + PUBWEAK DMIC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMIC0_IRQHandler + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + PUBWEAK HWVAD0_IRQHandler + PUBWEAK HWVAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HWVAD0_IRQHandler + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + PUBWEAK IOH_IRQHandler + PUBWEAK IOH_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +IOH_IRQHandler + LDR R0, =IOH_DriverIRQHandler + BX R0 + PUBWEAK MAILBOX_IRQHandler + PUBWEAK MAILBOX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MAILBOX_IRQHandler + LDR R0, =MAILBOX_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + PUBWEAK Reserved54_IRQHandler + PUBWEAK Reserved54_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved54_IRQHandler + LDR R0, =Reserved54_DriverIRQHandler + BX R0 + PUBWEAK SPIFI0_IRQHandler + PUBWEAK SPIFI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPIFI0_IRQHandler + LDR R0, =SPIFI0_DriverIRQHandler + BX R0 +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +IOH_DriverIRQHandler +MAILBOX_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +Reserved54_DriverIRQHandler +SPIFI0_DriverIRQHandler +DefaultISR + B . + + END diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.c new file mode 100644 index 00000000000..25777b8729c --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.c @@ -0,0 +1,108 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fsl_common.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" + +#ifdef SDK_PRIMARY_CORE +/* Address of RAM, where the image for core1 should be copied */ +#define CORE1_BOOT_ADDRESS (void *)0x20010000 + +#if defined(__CC_ARM) +extern uint32_t Image$$CORE1_REGION$$Base; +extern uint32_t Image$$CORE1_REGION$$Length; +#define CORE1_IMAGE_START &Image$$CORE1_REGION$$Base +#elif defined(__ICCARM__) +extern unsigned char core1_image_start[]; +#define CORE1_IMAGE_START core1_image_start +#endif +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Clock rate on the CLKIN pin */ +const uint32_t ExtClockIn = BOARD_EXTCLKINRATE; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +status_t BOARD_InitDebugConsole(void) +{ + status_t result; + + /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); + + RESET_PeripheralReset(BOARD_DEBUG_UART_RST); + result = DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM, + BOARD_DEBUG_UART_CLK_FREQ); + assert(kStatus_Success == result); + return result; +} + +#ifdef SDK_PRIMARY_CORE +/* Start the secondary core. */ +void BOARD_StartSecondaryCore(void) +{ +/* Calculate size of the secondary core image - not required on MCUXpresso. MCUXpresso copies the image to RAM during + * startup + * automatically */ +#if (defined(__CC_ARM) || defined(__ICCARM__)) +#if defined(__CC_ARM) + uint32_t core1_image_size = (uint32_t)&Image$$CORE1_REGION$$Length; +#elif defined(__ICCARM__) +#pragma section = "__sec_core" + uint32_t core1_image_size = (uint32_t)__section_end("__sec_core") - (uint32_t)&core1_image_start; +#endif + + /* Copy core1 application from FLASH to RAM. Primary core code is executed from FLASH, Secondary from RAM + * for maximal effectivity.*/ + memcpy(CORE1_BOOT_ADDRESS, (void *)CORE1_IMAGE_START, core1_image_size); +#endif + /* Boot source for Core 1 from RAM */ + SYSCON->CPBOOT = SYSCON_CPBOOT_BOOTADDR(*(uint32_t *)((uint8_t *)CORE1_BOOT_ADDRESS + 0x4)); + SYSCON->CPSTACK = SYSCON_CPSTACK_STACKADDR(*(uint32_t *)CORE1_BOOT_ADDRESS); + + uint32_t temp = SYSCON->CPUCTRL; + temp |= 0xc0c48000U; + SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CM0RSTEN_MASK | SYSCON_CPUCTRL_CM0CLKEN_MASK; + SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CM0CLKEN_MASK) & (~SYSCON_CPUCTRL_CM0RSTEN_MASK); +} +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.h new file mode 100644 index 00000000000..69c03d0a4c8 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/board.h @@ -0,0 +1,147 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "LPCXPRESSO54114" + +#define BOARD_EXTCLKINRATE (0) + +/*! @brief The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0 +#define BOARD_DEBUG_UART_INSTANCE 0U +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFreq(kCLOCK_Flexcomm0) +#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0 +#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn + +#define BOARD_DEBUG_SPI_CLK_FREQ 12000000 + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE 115200 +#endif /* BOARD_DEBUG_UART_BAUDRATE */ + +#ifndef BOARD_LED_RED_GPIO +#define BOARD_LED_RED_GPIO GPIO +#endif +#define BOARD_LED_RED_GPIO_PORT 0U +#ifndef BOARD_LED_RED_GPIO_PIN +#define BOARD_LED_RED_GPIO_PIN 29U +#endif +#ifndef BOARD_LED_GREEN_GPIO +#define BOARD_LED_GREEN_GPIO GPIO +#endif +#define BOARD_LED_GREEN_GPIO_PORT 1U +#ifndef BOARD_LED_GREEN_GPIO_PIN +#define BOARD_LED_GREEN_GPIO_PIN 10U +#endif +#ifndef BOARD_LED_BLUE_GPIO +#define BOARD_LED_BLUE_GPIO GPIO +#endif +#define BOARD_LED_BLUE_GPIO_PORT 1U +#ifndef BOARD_LED_BLUE_GPIO_PIN +#define BOARD_LED_BLUE_GPIO_PIN 9U +#endif + +/* Board led color mapping */ +#define LOGIC_LED_ON 0U +#define LOGIC_LED_OFF 1U + +#define LED_RED_INIT(output) \ + GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_RED */ +#define LED_RED_ON() \ + GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ + 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */ +#define LED_RED_OFF() \ + GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ + 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */ +#define LED_RED_TOGGLE() \ + GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ + 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */ + +#define LED_GREEN_INIT(output) \ + GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_GREEN */ +#define LED_GREEN_ON() \ + GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ + 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */ +#define LED_GREEN_OFF() \ + GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ + 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */ +#define LED_GREEN_TOGGLE() \ + GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ + 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */ + +#define LED_BLUE_INIT(output) \ + GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_BLUE */ +#define LED_BLUE_ON() \ + GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ + 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */ +#define LED_BLUE_OFF() \ + GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ + 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */ +#define LED_BLUE_TOGGLE() \ + GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ + 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +status_t BOARD_InitDebugConsole(void); + +#ifdef SDK_PRIMARY_CORE +void BOARD_StartSecondaryCore(void); +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.c new file mode 100644 index 00000000000..8a0b6bce73b --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.c @@ -0,0 +1,195 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Setup voltage for the fastest of the clock outputs + * + * 3. Set up wait states of the flash. + * + * 4. Set up all dividers. + * + * 5. Set up all selectors to provide selected clocks. + */ + +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!ClocksProfile +product: Clocks v1.0 +processor: LPC54114J256 +mcu_data: ksdk2_0 +processor_version: 1.1.0 +board: LPCXpresso54114 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockFROHF48M(); +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF48M +outputs: +- {id: System_clock.outFreq, value: 48 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF48M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq(48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} +sources: +- {id: SYSCON.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +} + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.h new file mode 100644 index 00000000000..57f92cb504c --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/clock_config.h @@ -0,0 +1,142 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions +******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ +#define BOARD_BootClockRUN BOARD_BootClockFROHF48M + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.c new file mode 100644 index 00000000000..06f66846262 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.c @@ -0,0 +1,16 @@ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v1.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Included files + ******************************************************************************/ +#include "peripherals.h" + +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.h new file mode 100644 index 00000000000..ca5e934dac6 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/peripherals.h @@ -0,0 +1,16 @@ +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ + +#endif /* _PERIPHERALS_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.c new file mode 100644 index 00000000000..fe309216aea --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.c @@ -0,0 +1,124 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v3.0 +processor: LPC54114J256 +mcu_data: ksdk2_0 +processor_version: 0.0.13 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'} +- pin_list: + - {pin_num: '31', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI, pin_signal: PIO0_0/FC0_RXD_SDA_MOSI/FC3_CTS_SDA_SSEL0/CTIMER0_CAP0/SCT0_OUT3, mode: inactive, invert: disabled, + glitch_filter: disabled, slew_rate: standard, open_drain: disabled} + - {pin_num: '32', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO, pin_signal: PIO0_1/FC0_TXD_SCL_MISO/FC3_RTS_SCL_SSEL1/CTIMER0_CAP1/SCT0_OUT1, mode: inactive, invert: disabled, + glitch_filter: disabled, slew_rate: standard, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the undefined */ +void BOARD_InitPins(void) +{ + /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin0_config = (/* Pin is configured as FC0_RXD_SDA_MOSI */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN0 (coords: 31) is configured as FC0_RXD_SDA_MOSI */ + IOCON_PinMuxSet(IOCON, 0U, 0U, port0_pin0_config); + + const uint32_t port0_pin1_config = (/* Pin is configured as FC0_TXD_SCL_MISO */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN1 (coords: 32) is configured as FC0_TXD_SCL_MISO */ + IOCON_PinMuxSet(IOCON, 0U, 1U, port0_pin1_config); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.h new file mode 100644 index 00000000000..339c1d672a1 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/project_template/pin_mux.h @@ -0,0 +1,94 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_DIGITAL_EN 0x80u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_INPFILT_OFF 0x0100u /*!<@brief Input filter disabled */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M0P */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.c new file mode 100644 index 00000000000..5b2b15244fb --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.c @@ -0,0 +1,366 @@ +/* +** ################################################################### +** Processors: LPC54114J256BD64_cm0plus +** LPC54114J256UK49_cm0plus +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b161227 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** The Clear BSD License +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-04-29) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file LPC54114_cm0plus + * @version 1.0 + * @date 2016-04-29 + * @brief Device specific configuration file for LPC54114_cm0plus + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#define NVALMAX (0x100) +#define PVALMAX (0x20) +#define MVALMAX (0x8000) +#define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0 */ +#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ +#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P) + +extern void *__Vectors; + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, + 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; + +static uint32_t GetWdtOscFreq(void) +{ + uint8_t freq_sel, div_sel; + div_sel = ((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1) << 1; + freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; + return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); +} + +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC) +{ + uint32_t n, x, i; + + /* Find NDec */ + switch (NDEC) + { + case 0xFFF: + n = 0; + break; + case 0x302: + n = 1; + break; + case 0x202: + n = 2; + break; + default: + x = 0x080; + n = 0xFFFFFFFF; + for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--) + { + x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); + if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) + { + /* Decoded value of NDEC */ + n = i; + } + } + break; + } + return n; +} + +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC) +{ + uint32_t p, x, i; + /* Find PDec */ + switch (PDEC) + { + case 0xFF: + p = 0; + break; + case 0x62: + p = 1; + break; + case 0x42: + p = 2; + break; + default: + x = 0x10; + p = 0xFFFFFFFF; + for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--) + { + x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF); + if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) + { + /* Decoded value of PDEC */ + p = i; + } + } + break; + } + return p; +} + +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC) +{ + uint32_t m, i, x; + + /* Find MDec */ + switch (MDEC) + { + case 0xFFFFF: + m = 0; + break; + case 0x18003: + m = 1; + break; + case 0x10003: + m = 2; + break; + default: + x = 0x04000; + m = 0xFFFFFFFF; + for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--) + { + x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); + if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) + { + /* Decoded value of MDEC */ + m = i; + } + } + break; + } + return m; +} + +/* Get predivider (N) from PLL NDEC setting */ +static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0) + { + /* Decode NDEC value to get (N) pre divider */ + preDiv = pllDecodeN(nDecReg & 0x3FF); + if (preDiv == 0) + { + preDiv = 1; + } + } + /* Adjusted by 1, directi is used to bypass */ + return preDiv; +} + +/* Get postdivider (P) from PLL PDEC setting */ +static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) +{ + uint32_t postDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0) + { + /* Decode PDEC value to get (P) post divider */ + postDiv = 2 * pllDecodeP(pDecReg & 0x7F); + if (postDiv == 0) + { + postDiv = 2; + } + } + /* Adjusted by 1, directo is used to bypass */ + return postDiv; +} + +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) +{ + uint32_t mMult = 1; + + /* Decode MDEC value to get (M) multiplier */ + mMult = pllDecodeM(mDecReg & 0x1FFFF); + /* Extra multiply by 2 needed? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0) + { + mMult = mMult << 1; + } + if (mMult == 0) + { + mMult = 1; + } + return mMult; +} + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit(void) +{ + SCB->VTOR = (uint32_t)&__Vectors; + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate(void) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + uint64_t workRate; + + switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) + { + case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ + switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLK_FRO_12MHZ; + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLK_CLK_IN; + break; + case 0x02: /* Watchdog oscillator (wdt_clk) */ + clkRate = GetWdtOscFreq(); + break; + default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */ + if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) + { + clkRate = CLK_FRO_96MHZ; + } + else + { + clkRate = CLK_FRO_48MHZ; + } + break; + } + break; + case 0x02: /* System PLL clock (pll_clk)*/ + switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLK_FRO_12MHZ; + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLK_CLK_IN; + break; + case 0x02: /* Watchdog oscillator (wdt_clk) */ + clkRate = GetWdtOscFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLK_RTC_32K_CLK; + break; + default: + break; + } + if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0) + { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC); + postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* If using the SS, use the multiplier */ + if (SYSCON->SYSPLLSSCTRL1 & SYSCON_SYSPLLSSCTRL1_PD_MASK) + { + /* MDEC used for rate */ + workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0); + } + else + { + /* SS multipler used for rate */ + workRate = 0; + /* Adjust by fractional */ + workRate = workRate + ((clkRate * (uint64_t)((SYSCON->SYSPLLSSCTRL1 & 0x7FF) >> 0)) / 0x800); + } + clkRate = workRate / ((uint64_t)postdiv); + } + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLK_RTC_32K_CLK; + break; + default: + break; + } + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.h new file mode 100644 index 00000000000..fa2b8c10124 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm0plus.h @@ -0,0 +1,136 @@ +/* +** ################################################################### +** Processors: LPC54114J256BD64_cm0plus +** LPC54114J256UK49_cm0plus +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b161227 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** The Clear BSD License +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-04-29) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file LPC54114_cm0plus + * @version 1.0 + * @date 2016-04-29 + * @brief Device specific configuration file for LPC54114_cm0plus (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC54114_cm0plus_H_ +#define _SYSTEM_LPC54114_cm0plus_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ +#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC54114_cm0plus_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.c new file mode 100644 index 00000000000..b9b519540d7 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.c @@ -0,0 +1,374 @@ +/* +** ################################################################### +** Processors: LPC54114J256BD64_cm4 +** LPC54114J256UK49_cm4 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b161227 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** The Clear BSD License +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-04-29) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file LPC54114_cm4 + * @version 1.0 + * @date 2016-04-29 + * @brief Device specific configuration file for LPC54114_cm4 (implementation + * file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#define NVALMAX (0x100) +#define PVALMAX (0x20) +#define MVALMAX (0x8000) +#define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0 */ +#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ +#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P) + +extern void *__Vectors; + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, + 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; + +static uint32_t GetWdtOscFreq(void) +{ + uint8_t freq_sel, div_sel; + div_sel = ((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1) << 1; + freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; + return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); +} + +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC) +{ + uint32_t n, x, i; + + /* Find NDec */ + switch (NDEC) + { + case 0xFFF: + n = 0; + break; + case 0x302: + n = 1; + break; + case 0x202: + n = 2; + break; + default: + x = 0x080; + n = 0xFFFFFFFF; + for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--) + { + x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); + if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) + { + /* Decoded value of NDEC */ + n = i; + } + } + break; + } + return n; +} + +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC) +{ + uint32_t p, x, i; + /* Find PDec */ + switch (PDEC) + { + case 0xFF: + p = 0; + break; + case 0x62: + p = 1; + break; + case 0x42: + p = 2; + break; + default: + x = 0x10; + p = 0xFFFFFFFF; + for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--) + { + x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF); + if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) + { + /* Decoded value of PDEC */ + p = i; + } + } + break; + } + return p; +} + +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC) +{ + uint32_t m, i, x; + + /* Find MDec */ + switch (MDEC) + { + case 0xFFFFF: + m = 0; + break; + case 0x18003: + m = 1; + break; + case 0x10003: + m = 2; + break; + default: + x = 0x04000; + m = 0xFFFFFFFF; + for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--) + { + x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); + if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) + { + /* Decoded value of MDEC */ + m = i; + } + } + break; + } + return m; +} + +/* Get predivider (N) from PLL NDEC setting */ +static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0) + { + /* Decode NDEC value to get (N) pre divider */ + preDiv = pllDecodeN(nDecReg & 0x3FF); + if (preDiv == 0) + { + preDiv = 1; + } + } + /* Adjusted by 1, directi is used to bypass */ + return preDiv; +} + +/* Get postdivider (P) from PLL PDEC setting */ +static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) +{ + uint32_t postDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0) + { + /* Decode PDEC value to get (P) post divider */ + postDiv = 2 * pllDecodeP(pDecReg & 0x7F); + if (postDiv == 0) + { + postDiv = 2; + } + } + /* Adjusted by 1, directo is used to bypass */ + return postDiv; +} + +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) +{ + uint32_t mMult = 1; + + /* Decode MDEC value to get (M) multiplier */ + mMult = pllDecodeM(mDecReg & 0x1FFFF); + /* Extra multiply by 2 needed? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0) + { + mMult = mMult << 1; + } + if (mMult == 0) + { + mMult = 1; + } + return mMult; +} + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit(void) +{ +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) || (defined(__VFP_FP__) && !defined(__SOFTFP__)) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + SCB->VTOR = (uint32_t)&__Vectors; +/* Optionally enable RAM banks that may be off by default at reset */ +#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK; +#endif + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate(void) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + uint64_t workRate; + + switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) + { + case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ + switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLK_FRO_12MHZ; + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLK_CLK_IN; + break; + case 0x02: /* Watchdog oscillator (wdt_clk) */ + clkRate = GetWdtOscFreq(); + break; + default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */ + if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) + { + clkRate = CLK_FRO_96MHZ; + } + else + { + clkRate = CLK_FRO_48MHZ; + } + break; + } + break; + case 0x02: /* System PLL clock (pll_clk)*/ + switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLK_FRO_12MHZ; + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLK_CLK_IN; + break; + case 0x02: /* Watchdog oscillator (wdt_clk) */ + clkRate = GetWdtOscFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLK_RTC_32K_CLK; + break; + default: + break; + } + if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0) + { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC); + postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* If using the SS, use the multiplier */ + if (SYSCON->SYSPLLSSCTRL1 & SYSCON_SYSPLLSSCTRL1_PD_MASK) + { + /* MDEC used for rate */ + workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0); + } + else + { + /* SS multipler used for rate */ + workRate = 0; + /* Adjust by fractional */ + workRate = workRate + ((clkRate * (uint64_t)((SYSCON->SYSPLLSSCTRL1 & 0x7FF) >> 0)) / 0x800); + } + clkRate = workRate / ((uint64_t)postdiv); + } + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLK_RTC_32K_CLK; + break; + default: + break; + } + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.h new file mode 100644 index 00000000000..33000bd751b --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/system_LPC54114_cm4.h @@ -0,0 +1,136 @@ +/* +** ################################################################### +** Processors: LPC54114J256BD64_cm4 +** LPC54114J256UK49_cm4 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b161227 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** The Clear BSD License +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-04-29) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file LPC54114_cm4 + * @version 1.0 + * @date 2016-04-29 + * @brief Device specific configuration file for LPC54114_cm4 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC54114_cm4_H_ +#define _SYSTEM_LPC54114_cm4_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ +#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC54114_cm4_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/template/RTE_Device.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/template/RTE_Device.h new file mode 100644 index 00000000000..f065c275ce1 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/template/RTE_Device.h @@ -0,0 +1,224 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +/* UART Select, UART0-UART7. */ +/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins +in the application for enabling according instance. */ +#define RTE_USART0 0 +#define RTE_USART0_DMA_EN 0 +#define RTE_USART1 0 +#define RTE_USART1_DMA_EN 0 +#define RTE_USART2 0 +#define RTE_USART2_DMA_EN 0 +#define RTE_USART3 0 +#define RTE_USART3_DMA_EN 0 +#define RTE_USART4 0 +#define RTE_USART4_DMA_EN 0 +#define RTE_USART5 0 +#define RTE_USART5_DMA_EN 0 +#define RTE_USART6 0 +#define RTE_USART6_DMA_EN 0 +#define RTE_USART7 0 +#define RTE_USART7_DMA_EN 0 + +/* USART configuration. */ +#define USART_RX_BUFFER_LEN 64 +#define USART0_RX_BUFFER_ENABLE 0 +#define USART1_RX_BUFFER_ENABLE 0 +#define USART2_RX_BUFFER_ENABLE 0 +#define USART3_RX_BUFFER_ENABLE 0 +#define USART4_RX_BUFFER_ENABLE 0 +#define USART5_RX_BUFFER_ENABLE 0 +#define USART6_RX_BUFFER_ENABLE 0 +#define USART7_RX_BUFFER_ENABLE 0 + +#define RTE_USART0_DMA_TX_CH 1 +#define RTE_USART0_DMA_TX_DMA_BASE DMA0 +#define RTE_USART0_DMA_RX_CH 0 +#define RTE_USART0_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART1_DMA_TX_CH 3 +#define RTE_USART1_DMA_TX_DMA_BASE DMA0 +#define RTE_USART1_DMA_RX_CH 2 +#define RTE_USART1_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART2_DMA_TX_CH 5 +#define RTE_USART2_DMA_TX_DMA_BASE DMA0 +#define RTE_USART2_DMA_RX_CH 4 +#define RTE_USART2_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART3_DMA_TX_CH 7 +#define RTE_USART3_DMA_TX_DMA_BASE DMA0 +#define RTE_USART3_DMA_RX_CH 6 +#define RTE_USART3_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART4_DMA_TX_CH 9 +#define RTE_USART4_DMA_TX_DMA_BASE DMA0 +#define RTE_USART4_DMA_RX_CH 8 +#define RTE_USART4_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART5_DMA_TX_CH 11 +#define RTE_USART5_DMA_TX_DMA_BASE DMA0 +#define RTE_USART5_DMA_RX_CH 10 +#define RTE_USART5_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART6_DMA_TX_CH 13 +#define RTE_USART6_DMA_TX_DMA_BASE DMA0 +#define RTE_USART6_DMA_RX_CH 12 +#define RTE_USART6_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART7_DMA_TX_CH 15 +#define RTE_USART7_DMA_TX_DMA_BASE DMA0 +#define RTE_USART7_DMA_RX_CH 14 +#define RTE_USART7_DMA_RX_DMA_BASE DMA0 + +/* I2C Select, I2C0 -I2C7*/ +/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins +in the application for enabling according instance. */ +#define RTE_I2C0 0 +#define RTE_I2C0_DMA_EN 0 +#define RTE_I2C1 0 +#define RTE_I2C1_DMA_EN 0 +#define RTE_I2C2 0 +#define RTE_I2C2_DMA_EN 0 +#define RTE_I2C3 0 +#define RTE_I2C3_DMA_EN 0 +#define RTE_I2C4 0 +#define RTE_I2C4_DMA_EN 0 +#define RTE_I2C5 0 +#define RTE_I2C5_DMA_EN 0 +#define RTE_I2C6 0 +#define RTE_I2C6_DMA_EN 0 +#define RTE_I2C7 0 +#define RTE_I2C7_DMA_EN 0 + +/*I2C configuration*/ +#define RTE_I2C0_Master_DMA_BASE DMA0 +#define RTE_I2C0_Master_DMA_CH 1 + +#define RTE_I2C1_Master_DMA_BASE DMA0 +#define RTE_I2C1_Master_DMA_CH 3 + +#define RTE_I2C2_Master_DMA_BASE DMA0 +#define RTE_I2C2_Master_DMA_CH 5 + +#define RTE_I2C3_Master_DMA_BASE DMA0 +#define RTE_I2C3_Master_DMA_CH 7 + +#define RTE_I2C4_Master_DMA_BASE DMA0 +#define RTE_I2C4_Master_DMA_CH 9 + +#define RTE_I2C5_Master_DMA_BASE DMA0 +#define RTE_I2C5_Master_DMA_CH 11 + +#define RTE_I2C6_Master_DMA_BASE DMA0 +#define RTE_I2C6_Master_DMA_CH 13 + +#define RTE_I2C7_Master_DMA_BASE DMA0 +#define RTE_I2C7_Master_DMA_CH 15 + +/* SPI select, SPI0 - SPI7.*/ +/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins +in the application for enabling according instance. */ +#define RTE_SPI0 0 +#define RTE_SPI0_DMA_EN 0 +#define RTE_SPI1 0 +#define RTE_SPI1_DMA_EN 0 +#define RTE_SPI2 0 +#define RTE_SPI2_DMA_EN 0 +#define RTE_SPI3 0 +#define RTE_SPI3_DMA_EN 0 +#define RTE_SPI4 0 +#define RTE_SPI4_DMA_EN 0 +#define RTE_SPI5 0 +#define RTE_SPI5_DMA_EN 0 +#define RTE_SPI6 0 +#define RTE_SPI6_DMA_EN 0 +#define RTE_SPI7 0 +#define RTE_SPI7_DMA_EN 0 + + +/* SPI configuration. */ +#define RTE_SPI0_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI0_DMA_TX_CH 1 +#define RTE_SPI0_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI0_DMA_RX_CH 0 +#define RTE_SPI0_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI1_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI1_DMA_TX_CH 3 +#define RTE_SPI1_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI1_DMA_RX_CH 2 +#define RTE_SPI1_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI2_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI2_DMA_TX_CH 5 +#define RTE_SPI2_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI2_DMA_RX_CH 4 +#define RTE_SPI2_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI3_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI3_DMA_TX_CH 7 +#define RTE_SPI3_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI3_DMA_RX_CH 6 +#define RTE_SPI3_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI4_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI4_DMA_TX_CH 9 +#define RTE_SPI4_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI4_DMA_RX_CH 8 +#define RTE_SPI4_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI5_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI5_DMA_TX_CH 11 +#define RTE_SPI5_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI5_DMA_RX_CH 10 +#define RTE_SPI5_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI6_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI6_DMA_TX_CH 13 +#define RTE_SPI6_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI6_DMA_RX_CH 12 +#define RTE_SPI6_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI7_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI7_DMA_TX_CH 15 +#define RTE_SPI7_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI7_DMA_RX_CH 14 +#define RTE_SPI7_DMA_RX_DMA_BASE DMA0 + +#endif /* __RTE_DEVICE_H */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/SConscript b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/SConscript new file mode 100644 index 00000000000..1b3c8a32588 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/SConscript @@ -0,0 +1,13 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = [] + +CPPDEFINES = ['SDK_DEBUGCONSOLE=0'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_assert.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_assert.c new file mode 100644 index 00000000000..a249b645613 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_assert.c @@ -0,0 +1,59 @@ +/* +* The Clear BSD License +* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* All rights reserved. +* +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted (subject to the limitations in the disclaimer below) provided +* that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of the copyright holder nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_common.h" +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); + for (;;) + { + __BKPT(0); + } +} +#elif(defined(__GNUC__)) +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); + for (;;) + { + __BKPT(0); + } +} +#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ +#endif /* NDEBUG */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.c new file mode 100644 index 00000000000..30c762f5e71 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.c @@ -0,0 +1,366 @@ +/* + * This is a modified version of the file printf.c, which was distributed + * by Motorola as part of the M5407C3BOOT.zip package used to initialize + * the M5407C3 evaluation board. + * + * Copyright: + * 1999-2000 MOTOROLA, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Motorola, Inc. This + * software is provided on an "AS IS" basis and without warranty. + * + * To the maximum extent permitted by applicable law, MOTOROLA + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY + * ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Motorola assumes no responsibility for the maintenance and support + * of this software + + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#if defined(__CC_ARM) +#include +#endif + +#include "fsl_debug_console.h" +#include "fsl_debug_console_conf.h" +#include "fsl_log.h" +#include "fsl_str.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief This is a printf call back function which is used to relocate the log to buffer + * or print the log immediately when the local buffer is full. + * + * @param[in] buf Buffer to store log. + * @param[in] indicator Buffer index. + * @param[in] val Target character to store. + * @param[in] len length of the character + * + */ +#if SDK_DEBUGCONSOLE +static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq) +{ + assert(device != DEBUG_CONSOLE_DEVICE_TYPE_NONE); + + return LOG_Init(baseAddr, device, baudRate, clkSrcFreq); +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Deinit(void) +{ + /* LOG deinit */ + LOG_Deinit(); + + return kStatus_Success; +} + +status_t DbgConsole_Flush(void) +{ + /* wait log and io idle */ + return LOG_WaitIdle(); +} + +#if SDK_DEBUGCONSOLE +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Printf(const char *fmt_s, ...) +{ + va_list ap; + int logLength = 0U, result = 0U; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {0U}; + + va_start(ap, fmt_s); + /* format print log first */ + logLength = StrFormatPrintf(fmt_s, ap, printBuf, DbgConsole_RelocateLog); + /* print log */ + result = LOG_Push((uint8_t *)printBuf, logLength); + + va_end(ap); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Putchar(int ch) +{ + /* print char */ + return LOG_Push((uint8_t *)&ch, 1U); +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Scanf(char *fmt_ptr, ...) +{ + va_list ap; + int result; + char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {0U}; + + /* scanf log */ + LOG_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN); + /* get va_list */ + va_start(ap, fmt_ptr); + /* format scanf log */ + result = StrFormatScanf(scanfBuf, fmt_ptr, ap); + + va_end(ap); + + return result; +} + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +status_t DbgConsole_TryGetchar(char *ch) +{ + if (NULL != ch) + { + return LOG_TryReadCharacter((uint8_t *)ch); + } + + return kStatus_Fail; +} +#endif + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Getchar(void) +{ + uint8_t ch; + + /* Get char */ + LOG_ReadCharacter(&ch); + + return ch; +} + +static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len) +{ + int i = 0; + + for (i = 0; i < len; i++) + { + if ((*indicator + 1) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) + { + LOG_Push((uint8_t *)buf, *indicator); + *indicator = 0U; + } + + buf[*indicator] = val; + (*indicator)++; + } +} + +#endif /* SDK_DEBUGCONSOLE */ + +/*************Code to support toolchain's printf, scanf *******************************/ +/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ +#if (defined(__ICCARM__)) +#if defined(SDK_DEBUGCONSOLE_UART) +#pragma weak __write +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + if (buffer == 0) + { + /* + * This means that we should flush internal buffers. Since we don't we just return. + * (Remember, "handle" == -1 means that all handles should be flushed.) + */ + return 0; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return ((size_t)-1); + } + + /* Send data. */ + LOG_Push((uint8_t *)buffer, 1U); + + return size; +} + +#pragma weak __read +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return ((size_t)-1); + } + + /* Receive data.*/ + LOG_ReadLine(buffer, size); + + return size; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* support LPC Xpresso with RedLib */ +#elif(defined(__REDLIB__)) + +#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)) +int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) +{ + if (buffer == 0) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + LOG_Push((uint8_t *)buffer, size); + + return 0; +} + +int __attribute__((weak)) __sys_readc(void) +{ + char tmp; + + /* Receive data. */ + LOG_ReadCharacter((uint8_t *)&tmp); + + return tmp; +} +#endif + +/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ +#elif(defined(__GNUC__)) + +#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ + (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)))) + +int __attribute__((weak)) _write(int handle, char *buffer, int size) +{ + if (buffer == 0) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + LOG_Push((uint8_t *)buffer, size); + + return size; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int size) +{ + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Receive data. */ + return LOG_ReadLine((uint8_t *)buffer, size); +} +#endif + +/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ +#elif defined(__CC_ARM) +#if defined(SDK_DEBUGCONSOLE_UART) +struct __FILE +{ + int handle; + /* + * Whatever you require here. If the only file you are using is standard output using printf() for debugging, + * no file handling is required. + */ +}; + +/* FILE is typedef in stdio.h. */ +#pragma weak __stdout +#pragma weak __stdin +FILE __stdout; +FILE __stdin; + +#pragma weak fputc +int fputc(int ch, FILE *f) +{ + /* Send data. */ + return LOG_Push((uint8_t *)(&ch), 1); +} + +#pragma weak fgetc +int fgetc(FILE *f) +{ + char ch; + + /* Receive data. */ + LOG_ReadCharacter((uint8_t *)&ch); + + return ch; +} +#endif /* SDK_DEBUGCONSOLE_UART */ +#endif /* __ICCARM__ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.h new file mode 100644 index 00000000000..14dd3a0c2d8 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console.h @@ -0,0 +1,207 @@ +/* + * The Clear BSD License + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Debug console shall provide input and output functions to scan and print formatted data. + * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" + * - [flags] :'-', '+', '#', ' ', '0' + * - [width]: number (0,1...) + * - [.precision]: number (0,1...) + * - [length]: do not support + * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' + * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" + * - [*]: is supported. + * - [width]: number (0,1...) + * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') + * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' + */ + +#ifndef _FSL_DEBUGCONSOLE_H_ +#define _FSL_DEBUGCONSOLE_H_ + +#include "fsl_common.h" +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Definition to select sdk or toolchain printf, scanf. */ +#ifndef SDK_DEBUGCONSOLE +#define SDK_DEBUGCONSOLE 1U +#endif + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. */ +#ifndef SDK_DEBUGCONSOLE_UART +/* mcux will handle this macro, not define it here */ +#if (!defined(__MCUXPRESSO)) +#define SDK_DEBUGCONSOLE_UART +#endif +#endif + +#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) +#include +#endif + +#if SDK_DEBUGCONSOLE /* Select printf, scanf, putchar, getchar of SDK version. */ +#define PRINTF DbgConsole_Printf +#define SCANF DbgConsole_Scanf +#define PUTCHAR DbgConsole_Putchar +#define GETCHAR DbgConsole_Getchar +#else /* Select printf, scanf, putchar, getchar of toolchain. */ +#define PRINTF printf +#define SCANF scanf +#define PUTCHAR putchar +#define GETCHAR getchar +#endif /* SDK_DEBUGCONSOLE */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + +/*! + * @brief Initializes the peripheral used for debug messages. + * + * Call this function to enable debug log messages to be output via the specified peripheral, + * frequency of peripheral source clock, and base address at the specified baud rate. + * After this function has returned, stdout and stdin are connected to the selected peripheral. + * + * @param baseAddr Indicates the address of the peripheral used to send debug messages. + * @param baudRate The desired baud rate in bits per second. + * @param device Low level device type for the debug console, can be one of the following. + * @arg DEBUG_CONSOLE_DEVICE_TYPE_UART, + * @arg DEBUG_CONSOLE_DEVICE_TYPE_LPUART, + * @arg DEBUG_CONSOLE_DEVICE_TYPE_LPSCI, + * @arg DEBUG_CONSOLE_DEVICE_TYPE_USBCDC. + * @param clkSrcFreq Frequency of peripheral source clock. + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + * @retval kStatus_Fail Execution failure + * @retval kStatus_InvalidArgument Invalid argument existed + */ +status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq); + +/*! + * @brief De-initializes the peripheral used for debug messages. + * + * Call this function to disable debug log messages to be output via the specified peripheral + * base address and at the specified baud rate. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_Deinit(void); + +#if SDK_DEBUGCONSOLE +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Printf(const char *fmt_s, ...); + +/*! + * @brief Writes a character to stdout. + * + * Call this function to write a character to stdout. + * + * @param ch Character to be written. + * @return Returns the character written. + */ +int DbgConsole_Putchar(int ch); + +/*! + * @brief Reads formatted data from the standard input stream. + * + * Call this function to read formatted data from the standard input stream. + * + * @param fmt_ptr Format control string. + * @return Returns the number of fields successfully converted and assigned. + */ +int DbgConsole_Scanf(char *fmt_ptr, ...); + +/*! + * @brief Reads a character from standard input. + * + * Call this function to read a character from standard input. + * + * @return Returns the character read. + */ +int DbgConsole_Getchar(void); + +/*! + * @brief Debug console flush log. + * + * Call this function to wait the buffer empty and io idle before. + * If interrupt transfer is using, make sure the global IRQ is enable before call this function + * This function should be called when + * 1, before enter power down mode + * 2, log is required to print to terminal immediately + * @return Indicates whether wait idle was successful or not. + */ +status_t DbgConsole_Flush(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief Debug console try to get char + * This function provide a api which will not block current task, if character is + * avaliable return it , otherwise return fail. + * @param ch the address of char to receive + * @return Indicates get char was successful or not. + */ +status_t DbgConsole_TryGetchar(char *ch); +#endif + +#endif /* SDK_DEBUGCONSOLE */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console_conf.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console_conf.h new file mode 100644 index 00000000000..7dfad4207d4 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_debug_console_conf.h @@ -0,0 +1,160 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ +#define _FSL_DEBUG_CONSOLE_CONF_H_ + +/****************Debug console configuration********************/ + +/*! @brief If Non-blocking mode is needed, please define it at project setting, +* otherwise blocking mode is the default transfer mode. +* Warning: If you want to use non-blocking transfer,please make sure the corresponding +* IO interrupt is enable, otherwise there is no output. +* And non-blocking is combine with buffer, no matter bare-metal or rtos. +*/ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically +* when +* non-blocking transfer is using, +* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. +* If it is configured too small, log maybe missed , because the log will not be +* buffered if the buffer is full, and the print will return immediately with -1. +* And this value should be multiple of 4 to meet memory alignment. +* +*/ +#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN +#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ + +/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when +* non-blocking transfer is using, +* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. +* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. +* And this value should be multiple of 4 to meet memory alignment. +* +*/ +#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN +#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ + +#else +#define DEBUG_CONSOLE_TRANSFER_BLOCKING +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log +* length can not bigger than this value. +* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if +* the buffer is too big and current task stack size not big enough. +*/ +#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN +#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) +#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ + +/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log +* length can not bigger than this value. +* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. +*/ +#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN +#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) +#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ + +/*! @brief Debug console synchronization +* User should not change these macro for synchronization mode, but add the +* corresponding synchronization mechanism per different software environment. +* Such as, if another RTOS is used, +* add: +* #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 +* in this configuration file and implement the synchronization in fsl.log.c. +*/ +/*! @brief synchronization for baremetal software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 +/*! @brief synchronization for freertos software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 + +/*! @brief RTOS synchronization mechanism disable +* If not defined, default is enable, to avoid multitask log print mess. +* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c +* If synchronization is disabled, log maybe messed on terminal. +*/ +#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#ifdef FSL_RTOS_FREE_RTOS +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* FSL_RTOS_FREE_RTOS */ +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ + +/*! @brief echo function support +* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO +* at your project setting. +*/ +#ifndef DEBUG_CONSOLE_ENABLE_ECHO +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 +#else +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 +#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ + +/*********************************************************************/ + +/***************Debug console other configuration*********************/ +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ +#ifndef BOARD_USE_VIRTUALCOM +#define BOARD_USE_VIRTUALCOM 0U +#endif +/*******************************************************************/ + +#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.c new file mode 100644 index 00000000000..10cb9bece7a --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.c @@ -0,0 +1,186 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_notifier.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle, + notifier_user_config_t **configs, + uint8_t configsNumber, + notifier_callback_config_t *callbacks, + uint8_t callbacksNumber, + notifier_user_function_t userFunction, + void *userData) +{ + /* Check input parameter - at least one configuration is required and userFunction must exist */ + if ((configs == NULL) || (configsNumber == 0U) || (userFunction == NULL)) + { + return kStatus_Fail; + } + /* Initialize handle structure */ + memset(notifierHandle, 0, sizeof(notifier_handle_t)); + /* Store references to user-defined configurations */ + notifierHandle->configsTable = configs; + notifierHandle->configsNumber = configsNumber; + /* Store references to user-defined callback configurations */ + if (callbacks != NULL) + { + notifierHandle->callbacksTable = callbacks; + notifierHandle->callbacksNumber = callbacksNumber; + /* If all callbacks return success, then the errorCallbackIndex is callbacksNumber */ + notifierHandle->errorCallbackIndex = callbacksNumber; + } + notifierHandle->userFunction = userFunction; + notifierHandle->userData = userData; + + return kStatus_Success; +} + +status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy) +{ + uint8_t currentStaticCallback = 0U; /* Index to array of statically registered call-backs */ + status_t returnCode = kStatus_Success; /* Function return */ + + notifier_notification_block_t notifyBlock; /* Callback notification block */ + notifier_callback_config_t *callbackConfig; /* Pointer to callback configuration */ + + /* Set errorcallbackindex as callbacksNumber, which means no callback error now */ + notifierHandle->errorCallbackIndex = notifierHandle->callbacksNumber; + + /* Requested configuration availability check */ + if (configIndex >= notifierHandle->configsNumber) + { + return kStatus_OutOfRange; + } + + /* Initialization of local variables from the Notifier handle structure */ + + notifyBlock.policy = policy; + notifyBlock.targetConfig = notifierHandle->configsTable[configIndex]; + notifyBlock.notifyType = kNOTIFIER_NotifyBefore; + + /* From all statically registered call-backs... */ + for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; currentStaticCallback++) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + /* ...notify only those which asked to be called before the configuration switch */ + if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackBefore) + { + /* In case that call-back returned error code mark it, store the call-back handle and eventually cancel + * the configuration switch */ + if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success) + { + returnCode = kStatus_NOTIFIER_ErrorNotificationBefore; + notifierHandle->errorCallbackIndex = currentStaticCallback; + /* If not forcing configuration switch, call all already notified call-backs to revert their state + * as the switch is canceled */ + if (policy != kNOTIFIER_PolicyForcible) + { + break; + } + } + } + } + + /* Set configuration */ + + /* In case that any call-back returned error code and policy doesn't force the configuration set, go to after + * switch call-backs */ + if ((policy == kNOTIFIER_PolicyForcible) || (returnCode == kStatus_Success)) + { + returnCode = notifierHandle->userFunction(notifierHandle->configsTable[configIndex], notifierHandle->userData); + if (returnCode != kStatus_Success) + { + return returnCode; + } + /* Update current configuration index */ + notifierHandle->currentConfigIndex = configIndex; + notifyBlock.notifyType = kNOTIFIER_NotifyAfter; + /* From all statically registered call-backs... */ + for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; + currentStaticCallback++) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + /* ...notify only those which asked to be called after the configruation switch */ + if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackAfter) + { + /* In case that call-back returned error code mark it and store the call-back handle */ + if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success) + { + returnCode = kStatus_NOTIFIER_ErrorNotificationAfter; + notifierHandle->errorCallbackIndex = currentStaticCallback; + if (policy != kNOTIFIER_PolicyForcible) + { + break; + } + } + } + } + } + else + { + /* End of unsuccessful switch */ + notifyBlock.notifyType = kNOTIFIER_NotifyRecover; + while (currentStaticCallback--) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackBefore) + { + callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData); + } + } + } + + return returnCode; +} + +uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle) +{ + return notifierHandle->errorCallbackIndex; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.h new file mode 100644 index 00000000000..5c930d98127 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_notifier.h @@ -0,0 +1,263 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_NOTIFIER_H_ +#define _FSL_NOTIFIER_H_ + +#include "fsl_common.h" +/*! + * @addtogroup notifier + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Notifier error codes. + * + * Used as return value of Notifier functions. + */ +enum _notifier_status +{ + kStatus_NOTIFIER_ErrorNotificationBefore = + MAKE_STATUS(kStatusGroup_NOTIFIER, 0), /*!< An error occurs during send "BEFORE" notification. */ + kStatus_NOTIFIER_ErrorNotificationAfter = + MAKE_STATUS(kStatusGroup_NOTIFIER, 1), /*!< An error occurs during send "AFTER" notification. */ +}; + +/*! + * @brief Notifier policies. + * + * Defines whether the user function execution is forced or not. + * For kNOTIFIER_PolicyForcible, the user function is executed regardless of the callback results, + * while kNOTIFIER_PolicyAgreement policy is used to exit NOTIFIER_SwitchConfig() + * when any of the callbacks returns error code. + * See also NOTIFIER_SwitchConfig() description. + */ +typedef enum _notifier_policy +{ + kNOTIFIER_PolicyAgreement, /*!< NOTIFIER_SwitchConfig() method is exited when any of the callbacks returns error + code. */ + kNOTIFIER_PolicyForcible, /*!< The user function is executed regardless of the results. */ +} notifier_policy_t; + +/*! @brief Notification type. Used to notify registered callbacks */ +typedef enum _notifier_notification_type +{ + kNOTIFIER_NotifyRecover = 0x00U, /*!< Notify IP to recover to previous work state. */ + kNOTIFIER_NotifyBefore = 0x01U, /*!< Notify IP that configuration setting is going to change. */ + kNOTIFIER_NotifyAfter = 0x02U, /*!< Notify IP that configuration setting has been changed. */ +} notifier_notification_type_t; + +/*! + * @brief The callback type, which indicates kinds of notification the callback handles. + * + * Used in the callback configuration structure (notifier_callback_config_t) + * to specify when the registered callback is called during configuration switch initiated by the + * NOTIFIER_SwitchConfig(). + * Callback can be invoked in following situations. + * - Before the configuration switch (Callback return value can affect NOTIFIER_SwitchConfig() + * execution. See the NOTIFIER_SwitchConfig() and notifier_policy_t documentation). + * - After an unsuccessful attempt to switch configuration + * - After a successful configuration switch + */ +typedef enum _notifier_callback_type +{ + kNOTIFIER_CallbackBefore = 0x01U, /*!< Callback handles BEFORE notification. */ + kNOTIFIER_CallbackAfter = 0x02U, /*!< Callback handles AFTER notification. */ + kNOTIFIER_CallbackBeforeAfter = 0x03U, /*!< Callback handles BEFORE and AFTER notification. */ +} notifier_callback_type_t; + +/*! @brief Notifier user configuration type. + * + * Reference of the user defined configuration is stored in an array; the notifier switches between these configurations + * based on this array. + */ +typedef void notifier_user_config_t; + +/*! @brief Notifier user function prototype + * Use this function to execute specific operations in configuration switch. + * Before and after this function execution, different notification is sent to registered callbacks. + * If this function returns any error code, NOTIFIER_SwitchConfig() exits. + * + * @param targetConfig target Configuration. + * @param userData Refers to other specific data passed to user function. + * @return An error code or kStatus_Success. + */ +typedef status_t (*notifier_user_function_t)(notifier_user_config_t *targetConfig, void *userData); + +/*! @brief notification block passed to the registered callback function. */ +typedef struct _notifier_notification_block +{ + notifier_user_config_t *targetConfig; /*!< Pointer to target configuration. */ + notifier_policy_t policy; /*!< Configure transition policy. */ + notifier_notification_type_t notifyType; /*!< Configure notification type. */ +} notifier_notification_block_t; + +/*! + * @brief Callback prototype. + * + * Declaration of a callback. It is common for registered callbacks. + * Reference to function of this type is part of the notifier_callback_config_t callback configuration structure. + * Depending on callback type, function of this prototype is called (see NOTIFIER_SwitchConfig()) + * before configuration switch, after it or in both use cases to notify about + * the switch progress (see notifier_callback_type_t). When called, the type of the notification + * is passed as a parameter along with the reference to the target configuration structure (see notifier_notification_block_t) + * and any data passed during the callback registration. + * When notified before the configuration switch, depending on the configuration switch policy (see + * notifier_policy_t), the callback may deny the execution of the user function by returning an error code different + * than kStatus_Success (see NOTIFIER_SwitchConfig()). + * + * @param notify Notification block. + * @param data Callback data. Refers to the data passed during callback registration. Intended to + * pass any driver or application data such as internal state information. + * @return An error code or kStatus_Success. + */ +typedef status_t (*notifier_callback_t)(notifier_notification_block_t *notify, void *data); + +/*! + * @brief Callback configuration structure. + * + * This structure holds the configuration of callbacks. + * Callbacks of this type are expected to be statically allocated. + * This structure contains the following application-defined data. + * callback - pointer to the callback function + * callbackType - specifies when the callback is called + * callbackData - pointer to the data passed to the callback. + */ +typedef struct _notifier_callback_config +{ + notifier_callback_t callback; /*!< Pointer to the callback function. */ + notifier_callback_type_t callbackType; /*!< Callback type. */ + void *callbackData; /*!< Pointer to the data passed to the callback. */ +} notifier_callback_config_t; + +/*! + * @brief Notifier handle structure. + * + * Notifier handle structure. Contains data necessary for the Notifier proper function. + * Stores references to registered configurations, callbacks, information about their numbers, + * user function, user data, and other internal data. + * NOTIFIER_CreateHandle() must be called to initialize this handle. + */ +typedef struct _notifier_handle +{ + notifier_user_config_t **configsTable; /*!< Pointer to configure table. */ + uint8_t configsNumber; /*!< Number of configurations. */ + notifier_callback_config_t *callbacksTable; /*!< Pointer to callback table. */ + uint8_t callbacksNumber; /*!< Maximum number of callback configurations. */ + uint8_t errorCallbackIndex; /*!< Index of callback returns error. */ + uint8_t currentConfigIndex; /*!< Index of current configuration. */ + notifier_user_function_t userFunction; /*!< User function. */ + void *userData; /*!< User data passed to user function. */ +} notifier_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Creates a Notifier handle. + * + * @param notifierHandle A pointer to the notifier handle. + * @param configs A pointer to an array with references to all configurations which is handled by the Notifier. + * @param configsNumber Number of configurations. Size of the configuration array. + * @param callbacks A pointer to an array of callback configurations. + * If there are no callbacks to register during Notifier initialization, use NULL value. + * @param callbacksNumber Number of registered callbacks. Size of the callbacks array. + * @param userFunction User function. + * @param userData User data passed to user function. + * @return An error Code or kStatus_Success. + */ +status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle, + notifier_user_config_t **configs, + uint8_t configsNumber, + notifier_callback_config_t *callbacks, + uint8_t callbacksNumber, + notifier_user_function_t userFunction, + void *userData); + +/*! + * @brief Switches the configuration according to a pre-defined structure. + * + * This function sets the system to the target configuration. Before transition, + * the Notifier sends notifications to all callbacks registered to the callback table. + * Callbacks are invoked in the following order: All registered callbacks are notified + * ordered by index in the callbacks array. The same order is used for before and after switch notifications. + * The notifications before the configuration switch can be used to obtain confirmation about + * the change from registered callbacks. If any registered callback denies the + * configuration change, further execution of this function depends on the notifier policy: the + * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement). + * When configuration change is forced, the result of the before switch notifications are ignored. If an + * agreement is required, if any callback returns an error code, further notifications + * before switch notifications are cancelled and all already notified callbacks are re-invoked. + * The index of the callback which returned error code during pre-switch notifications is stored + * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it. + * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase + * the error occurred is returned when NOTIFIER_SwitchConfig() exits. + * @param notifierHandle pointer to notifier handle + * @param configIndex Index of the target configuration. + * @param policy Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible. + * + * @return An error code or kStatus_Success. + * + */ +status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy); + +/*! + * @brief This function returns the last failed notification callback. + * + * This function returns an index of the last callback that failed during the configuration switch while + * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully + * value equal to callbacks number is returned. The returned value represents an index in the array of + * static call-backs. + * + * @param notifierHandle Pointer to the notifier handle + * @return Callback Index of the last failed callback or value equal to callbacks count. + */ +uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_NOTIFIER_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.c new file mode 100644 index 00000000000..e8030ea68b7 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.c @@ -0,0 +1,651 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * POSIX getopt for Windows + * Code given out at the 1985 UNIFORUM conference in Dallas. + * + * From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985 + * Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET + * Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP + * Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix + * From: std-unix@ut-sally.UUCP (Moderator, John Quarterman) + * Newsgroups: mod.std.unix + * Subject: public domain AT&T getopt source + * Message-ID: <3352@ut-sally.UUCP> + * Date: 3 Nov 85 19:34:15 GMT + * Date-Received: 4 Nov 85 12:25:09 GMT + * Organization: IEEE/P1003 Portable Operating System Environment Committee + * Lines: 91 + * Approved: jsq@ut-sally.UUC + * Here's something you've all been waiting for: the AT&T public domain + * source for getopt(3). It is the code which was given out at the 1985 + * UNIFORUM conference in Dallas. I obtained it by electronic mail + * directly from AT&T. The people there assure me that it is indeed + * in the public domain + * There is no manual page. That is because the one they gave out at + * UNIFORUM was slightly different from the current System V Release 2 + * manual page. The difference apparently involved a note about the + * famous rules 5 and 6, recommending using white space between an option + * and its first argument, and not grouping options that have arguments. + * Getopt itself is currently lenient about both of these things White + * space is allowed, but not mandatory, and the last option in a group can + * have an argument. That particular version of the man page evidently + * has no official existence, and my source at AT&T did not send a copy. + * The current SVR2 man page reflects the actual behavor of this getopt. + * However, I am not about to post a copy of anything licensed by AT&T. + */ + +#include +#include "fsl_shell.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define KEY_ESC (0x1BU) +#define KET_DEL (0x7FU) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static int32_t HelpCommand(p_shell_context_t context, int32_t argc, char **argv); /*!< help command */ + +static int32_t ExitCommand(p_shell_context_t context, int32_t argc, char **argv); /*!< exit command */ + +static int32_t ParseLine(const char *cmd, uint32_t len, char *argv[SHELL_MAX_ARGS]); /*!< parse line command */ + +static int32_t StrCompare(const char *str1, const char *str2, int32_t count); /*!< compare string command */ + +static void ProcessCommand(p_shell_context_t context, const char *cmd); /*!< process a command */ + +static void GetHistoryCommand(p_shell_context_t context, uint8_t hist_pos); /*!< get commands history */ + +static void AutoComplete(p_shell_context_t context); /*!< auto complete command */ + +static uint8_t GetChar(p_shell_context_t context); /*!< get a char from communication interface */ + +static int32_t StrLen(const char *str); /*!< get string length */ + +static char *StrCopy(char *dest, const char *src, int32_t count); /*!< string copy */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static const shell_command_context_t xHelpCommand = {"help", "\r\n\"help\": Lists all the registered commands\r\n", + HelpCommand, 0}; + +static const shell_command_context_t xExitCommand = {"exit", "\r\n\"exit\": Exit program\r\n", ExitCommand, 0}; + +static shell_command_context_list_t g_RegisteredCommands; + +static char g_paramBuffer[SHELL_BUFFER_SIZE]; + +/******************************************************************************* + * Code + ******************************************************************************/ +void SHELL_Init( + p_shell_context_t context, send_data_cb_t send_cb, recv_data_cb_t recv_cb, printf_data_t shell_printf, char *prompt) +{ + assert(send_cb != NULL); + assert(recv_cb != NULL); + assert(prompt != NULL); + assert(shell_printf != NULL); + + /* Memset for context */ + memset(context, 0, sizeof(shell_context_struct)); + context->send_data_func = send_cb; + context->recv_data_func = recv_cb; + context->printf_data_func = shell_printf; + context->prompt = prompt; + + SHELL_RegisterCommand(&xHelpCommand); + SHELL_RegisterCommand(&xExitCommand); +} + +int32_t SHELL_Main(p_shell_context_t context) +{ + uint8_t ch; + int32_t i; + + if (!context) + { + return -1; + } + + context->exit = false; + context->printf_data_func("\r\nSHELL (build: %s)\r\n", __DATE__); + context->printf_data_func("Copyright (c) 2017 NXP Semiconductor\r\n"); + context->printf_data_func(context->prompt); + + while (1) + { + if (context->exit) + { + break; + } + ch = GetChar(context); + /* If error occured when getting a char, continue to receive a new char. */ + if ((uint8_t)(-1) == ch) + { + continue; + } + /* Special key */ + if (ch == KEY_ESC) + { + context->stat = kSHELL_Special; + continue; + } + else if (context->stat == kSHELL_Special) + { + /* Function key */ + if (ch == '[') + { + context->stat = kSHELL_Function; + continue; + } + context->stat = kSHELL_Normal; + } + else if (context->stat == kSHELL_Function) + { + context->stat = kSHELL_Normal; + + switch ((uint8_t)ch) + { + /* History operation here */ + case 'A': /* Up key */ + GetHistoryCommand(context, context->hist_current); + if (context->hist_current < (context->hist_count - 1)) + { + context->hist_current++; + } + break; + case 'B': /* Down key */ + GetHistoryCommand(context, context->hist_current); + if (context->hist_current > 0) + { + context->hist_current--; + } + break; + case 'D': /* Left key */ + if (context->c_pos) + { + context->printf_data_func("\b"); + context->c_pos--; + } + break; + case 'C': /* Right key */ + if (context->c_pos < context->l_pos) + { + context->printf_data_func("%c", context->line[context->c_pos]); + context->c_pos++; + } + break; + default: + break; + } + continue; + } + /* Handle tab key */ + else if (ch == '\t') + { +#if SHELL_AUTO_COMPLETE + /* Move the cursor to the beginning of line */ + for (i = 0; i < context->c_pos; i++) + { + context->printf_data_func("\b"); + } + /* Do auto complete */ + AutoComplete(context); + /* Move position to end */ + context->c_pos = context->l_pos = StrLen(context->line); +#endif + continue; + } +#if SHELL_SEARCH_IN_HIST + /* Search command in history */ + else if ((ch == '`') && (context->l_pos == 0) && (context->line[0] == 0x00)) + { + } +#endif + /* Handle backspace key */ + else if ((ch == KET_DEL) || (ch == '\b')) + { + /* There must be at last one char */ + if (context->c_pos == 0) + { + continue; + } + + context->l_pos--; + context->c_pos--; + + if (context->l_pos > context->c_pos) + { + memmove(&context->line[context->c_pos], &context->line[context->c_pos + 1], + context->l_pos - context->c_pos); + context->line[context->l_pos] = 0; + context->printf_data_func("\b%s \b", &context->line[context->c_pos]); + + /* Reset position */ + for (i = context->c_pos; i <= context->l_pos; i++) + { + context->printf_data_func("\b"); + } + } + else /* Normal backspace operation */ + { + context->printf_data_func("\b \b"); + context->line[context->l_pos] = 0; + } + continue; + } + else + { + } + + /* Input too long */ + if (context->l_pos >= (SHELL_BUFFER_SIZE - 1)) + { + context->l_pos = 0; + } + + /* Handle end of line, break */ + if ((ch == '\r') || (ch == '\n')) + { + static char endoflinechar = 0U; + + if ((endoflinechar != 0U) && (endoflinechar != ch)) + { + continue; + } + else + { + endoflinechar = ch; + context->printf_data_func("\r\n"); + /* If command line is NULL, will start a new transfer */ + if (0U == StrLen(context->line)) + { + context->printf_data_func(context->prompt); + continue; + } + ProcessCommand(context, context->line); + /* Reset all params */ + context->c_pos = context->l_pos = 0; + context->hist_current = 0; + context->printf_data_func(context->prompt); + memset(context->line, 0, sizeof(context->line)); + continue; + } + } + + /* Normal character */ + if (context->c_pos < context->l_pos) + { + memmove(&context->line[context->c_pos + 1], &context->line[context->c_pos], + context->l_pos - context->c_pos); + context->line[context->c_pos] = ch; + context->printf_data_func("%s", &context->line[context->c_pos]); + /* Move the cursor to new position */ + for (i = context->c_pos; i < context->l_pos; i++) + { + context->printf_data_func("\b"); + } + } + else + { + context->line[context->l_pos] = ch; + context->printf_data_func("%c", ch); + } + + ch = 0; + context->l_pos++; + context->c_pos++; + } + return 0; +} + +static int32_t HelpCommand(p_shell_context_t context, int32_t argc, char **argv) +{ + uint8_t i = 0; + + for (i = 0; i < g_RegisteredCommands.numberOfCommandInList; i++) + { + context->printf_data_func(g_RegisteredCommands.CommandList[i]->pcHelpString); + } + return 0; +} + +static int32_t ExitCommand(p_shell_context_t context, int32_t argc, char **argv) +{ + /* Skip warning */ + context->printf_data_func("\r\nSHELL exited\r\n"); + context->exit = true; + return 0; +} + +static void ProcessCommand(p_shell_context_t context, const char *cmd) +{ + static const shell_command_context_t *tmpCommand = NULL; + static const char *tmpCommandString; + int32_t argc; + char *argv[SHELL_BUFFER_SIZE]; + uint8_t flag = 1; + uint8_t tmpCommandLen; + uint8_t tmpLen; + uint8_t i = 0; + + tmpLen = StrLen(cmd); + argc = ParseLine(cmd, tmpLen, argv); + + if ((tmpCommand == NULL) && (argc > 0)) + { + for (i = 0; i < g_RegisteredCommands.numberOfCommandInList; i++) + { + tmpCommand = g_RegisteredCommands.CommandList[i]; + tmpCommandString = tmpCommand->pcCommand; + tmpCommandLen = StrLen(tmpCommandString); + /* Compare with space or end of string */ + if ((cmd[tmpCommandLen] == ' ') || (cmd[tmpCommandLen] == 0x00)) + { + if (StrCompare(tmpCommandString, argv[0], tmpCommandLen) == 0) + { + /* support commands with optional number of parameters */ + if (tmpCommand->cExpectedNumberOfParameters == SHELL_OPTIONAL_PARAMS) + { + flag = 0; + } + else if ((tmpCommand->cExpectedNumberOfParameters == 0) && (argc == 1)) + { + flag = 0; + } + else if (tmpCommand->cExpectedNumberOfParameters > 0) + { + if ((argc - 1) == tmpCommand->cExpectedNumberOfParameters) + { + flag = 0; + } + } + else + { + flag = 1; + } + break; + } + } + } + } + + if ((tmpCommand != NULL) && (flag == 1U)) + { + context->printf_data_func( + "\r\nIncorrect command parameter(s). Enter \"help\" to view a list of available commands.\r\n\r\n"); + tmpCommand = NULL; + } + else if (tmpCommand != NULL) + { + tmpLen = StrLen(cmd); + /* Compare with last command. Push back to history buffer if different */ + if (tmpLen != StrCompare(cmd, context->hist_buf[0], StrLen(cmd))) + { + for (i = SHELL_HIST_MAX - 1; i > 0; i--) + { + memset(context->hist_buf[i], '\0', SHELL_BUFFER_SIZE); + tmpLen = StrLen(context->hist_buf[i - 1]); + StrCopy(context->hist_buf[i], context->hist_buf[i - 1], tmpLen); + } + memset(context->hist_buf[0], '\0', SHELL_BUFFER_SIZE); + tmpLen = StrLen(cmd); + StrCopy(context->hist_buf[0], cmd, tmpLen); + if (context->hist_count < SHELL_HIST_MAX) + { + context->hist_count++; + } + } + tmpCommand->pFuncCallBack(context, argc, argv); + tmpCommand = NULL; + } + else + { + context->printf_data_func( + "\r\nCommand not recognised. Enter 'help' to view a list of available commands.\r\n\r\n"); + tmpCommand = NULL; + } +} + +static void GetHistoryCommand(p_shell_context_t context, uint8_t hist_pos) +{ + uint8_t i; + uint32_t tmp; + + if (context->hist_buf[0][0] == '\0') + { + context->hist_current = 0; + return; + } + if (hist_pos >= SHELL_HIST_MAX) + { + hist_pos = SHELL_HIST_MAX - 1; + } + tmp = StrLen(context->line); + /* Clear current if have */ + if (tmp > 0) + { + memset(context->line, '\0', tmp); + for (i = 0; i < tmp; i++) + { + context->printf_data_func("\b \b"); + } + } + + context->l_pos = StrLen(context->hist_buf[hist_pos]); + context->c_pos = context->l_pos; + StrCopy(context->line, context->hist_buf[hist_pos], context->l_pos); + context->printf_data_func(context->hist_buf[hist_pos]); +} + +static void AutoComplete(p_shell_context_t context) +{ + int32_t len; + int32_t minLen; + uint8_t i = 0; + const shell_command_context_t *tmpCommand = NULL; + const char *namePtr; + const char *cmdName; + + minLen = 0; + namePtr = NULL; + + if (!StrLen(context->line)) + { + return; + } + context->printf_data_func("\r\n"); + /* Empty tab, list all commands */ + if (context->line[0] == '\0') + { + HelpCommand(context, 0, NULL); + return; + } + /* Do auto complete */ + for (i = 0; i < g_RegisteredCommands.numberOfCommandInList; i++) + { + tmpCommand = g_RegisteredCommands.CommandList[i]; + cmdName = tmpCommand->pcCommand; + if (StrCompare(context->line, cmdName, StrLen(context->line)) == 0) + { + if (minLen == 0) + { + namePtr = cmdName; + minLen = StrLen(namePtr); + /* Show possible matches */ + context->printf_data_func("%s\r\n", cmdName); + continue; + } + len = StrCompare(namePtr, cmdName, StrLen(namePtr)); + if (len < 0) + { + len = len * (-1); + } + if (len < minLen) + { + minLen = len; + } + } + } + /* Auto complete string */ + if (namePtr) + { + StrCopy(context->line, namePtr, minLen); + } + context->printf_data_func("%s%s", context->prompt, context->line); + return; +} + +static char *StrCopy(char *dest, const char *src, int32_t count) +{ + char *ret = dest; + int32_t i = 0; + + for (i = 0; i < count; i++) + { + dest[i] = src[i]; + } + + return ret; +} + +static int32_t StrLen(const char *str) +{ + int32_t i = 0; + + while (*str) + { + str++; + i++; + } + return i; +} + +static int32_t StrCompare(const char *str1, const char *str2, int32_t count) +{ + while (count--) + { + if (*str1++ != *str2++) + { + return *(unsigned char *)(str1 - 1) - *(unsigned char *)(str2 - 1); + } + } + return 0; +} + +static int32_t ParseLine(const char *cmd, uint32_t len, char *argv[SHELL_MAX_ARGS]) +{ + uint32_t argc; + char *p; + uint32_t position; + + /* Init params */ + memset(g_paramBuffer, '\0', len + 1); + StrCopy(g_paramBuffer, cmd, len); + + p = g_paramBuffer; + position = 0; + argc = 0; + + while (position < len) + { + /* Skip all blanks */ + while (((char)(*p) == ' ') && (position < len)) + { + *p = '\0'; + p++; + position++; + } + /* Process begin of a string */ + if (*p == '"') + { + p++; + position++; + argv[argc] = p; + argc++; + /* Skip this string */ + while ((*p != '"') && (position < len)) + { + p++; + position++; + } + /* Skip '"' */ + *p = '\0'; + p++; + position++; + } + else /* Normal char */ + { + argv[argc] = p; + argc++; + while (((char)*p != ' ') && ((char)*p != '\t') && (position < len)) + { + p++; + position++; + } + } + } + return argc; +} + +int32_t SHELL_RegisterCommand(const shell_command_context_t *command_context) +{ + int32_t result = 0; + + /* If have room in command list */ + if (g_RegisteredCommands.numberOfCommandInList < SHELL_MAX_CMD) + { + g_RegisteredCommands.CommandList[g_RegisteredCommands.numberOfCommandInList++] = command_context; + } + else + { + result = -1; + } + return result; +} + +static uint8_t GetChar(p_shell_context_t context) +{ + uint8_t ch; + +#if SHELL_USE_FILE_STREAM + ch = fgetc(context->STDIN); +#else + context->recv_data_func(&ch, 1U); +#endif + return ch; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.h new file mode 100644 index 00000000000..c1cc6225b65 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_shell.h @@ -0,0 +1,211 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SHELL_H_ +#define _FSL_SHELL_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup SHELL + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Macro to set on/off history feature. */ +#ifndef SHELL_USE_HISTORY +#define SHELL_USE_HISTORY (0U) +#endif + +/*! @brief Macro to set on/off history feature. */ +#ifndef SHELL_SEARCH_IN_HIST +#define SHELL_SEARCH_IN_HIST (1U) +#endif + +/*! @brief Macro to select method stream. */ +#ifndef SHELL_USE_FILE_STREAM +#define SHELL_USE_FILE_STREAM (0U) +#endif + +/*! @brief Macro to set on/off auto-complete feature. */ +#ifndef SHELL_AUTO_COMPLETE +#define SHELL_AUTO_COMPLETE (1U) +#endif + +/*! @brief Macro to set console buffer size. */ +#ifndef SHELL_BUFFER_SIZE +#define SHELL_BUFFER_SIZE (64U) +#endif + +/*! @brief Macro to set maximum arguments in command. */ +#ifndef SHELL_MAX_ARGS +#define SHELL_MAX_ARGS (8U) +#endif + +/*! @brief Macro to set maximum count of history commands. */ +#ifndef SHELL_HIST_MAX +#define SHELL_HIST_MAX (3U) +#endif + +/*! @brief Macro to set maximum count of commands. */ +#ifndef SHELL_MAX_CMD +#define SHELL_MAX_CMD (20U) +#endif + +/*! @brief Macro to bypass arguments check */ +#define SHELL_OPTIONAL_PARAMS (0xFF) + +/*! @brief Shell user send data callback prototype.*/ +typedef void (*send_data_cb_t)(uint8_t *buf, uint32_t len); + +/*! @brief Shell user receiver data callback prototype.*/ +typedef void (*recv_data_cb_t)(uint8_t *buf, uint32_t len); + +/*! @brief Shell user printf data prototype.*/ +typedef int (*printf_data_t)(const char *format, ...); + +/*! @brief A type for the handle special key. */ +typedef enum _fun_key_status +{ + kSHELL_Normal = 0U, /*!< Normal key */ + kSHELL_Special = 1U, /*!< Special key */ + kSHELL_Function = 2U, /*!< Function key */ +} fun_key_status_t; + +/*! @brief Data structure for Shell environment. */ +typedef struct _shell_context_struct +{ + char *prompt; /*!< Prompt string */ + enum _fun_key_status stat; /*!< Special key status */ + char line[SHELL_BUFFER_SIZE]; /*!< Consult buffer */ + uint8_t cmd_num; /*!< Number of user commands */ + uint8_t l_pos; /*!< Total line position */ + uint8_t c_pos; /*!< Current line position */ +#if SHELL_USE_FILE_STREAM + FILE *STDOUT, *STDIN, *STDERR; +#else + send_data_cb_t send_data_func; /*!< Send data interface operation */ + recv_data_cb_t recv_data_func; /*!< Receive data interface operation */ + printf_data_t printf_data_func; +#endif + uint16_t hist_current; /*!< Current history command in hist buff*/ + uint16_t hist_count; /*!< Total history command in hist buff*/ + char hist_buf[SHELL_HIST_MAX][SHELL_BUFFER_SIZE]; /*!< History buffer*/ + bool exit; /*!< Exit Flag*/ +} shell_context_struct, *p_shell_context_t; + +/*! @brief User command function prototype. */ +typedef int32_t (*cmd_function_t)(p_shell_context_t context, int32_t argc, char **argv); + +/*! @brief User command data structure. */ +typedef struct _shell_command_context +{ + const char *pcCommand; /*!< The command that is executed. For example "help". It must be all lower case. */ + char *pcHelpString; /*!< String that describes how to use the command. It should start with the command itself, + and end with "\r\n". For example "help: Returns a list of all the commands\r\n". */ + const cmd_function_t + pFuncCallBack; /*!< A pointer to the callback function that returns the output generated by the command. */ + uint8_t cExpectedNumberOfParameters; /*!< Commands expect a fixed number of parameters, which may be zero. */ +} shell_command_context_t; + +/*! @brief Structure list command. */ +typedef struct _shell_command_context_list +{ + const shell_command_context_t *CommandList[SHELL_MAX_CMD]; /*!< The command table list */ + uint8_t numberOfCommandInList; /*!< The total command in list */ +} shell_command_context_list_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Shell functional operation + * @{ + */ + +/*! +* @brief Enables the clock gate and configures the Shell module according to the configuration structure. +* +* This function must be called before calling all other Shell functions. +* Call operation the Shell commands with user-defined settings. +* The example below shows how to set up the middleware Shell and +* how to call the SHELL_Init function by passing in these parameters. +* This is an example. +* @code +* shell_context_struct user_context; +* SHELL_Init(&user_context, SendDataFunc, ReceiveDataFunc, "SHELL>> "); +* @endcode +* @param context The pointer to the Shell environment and runtime states. +* @param send_cb The pointer to call back send data function. +* @param recv_cb The pointer to call back receive data function. +* @param prompt The string prompt of Shell +*/ +void SHELL_Init(p_shell_context_t context, + send_data_cb_t send_cb, + recv_data_cb_t recv_cb, + printf_data_t shell_printf, + char *prompt); + +/*! + * @brief Shell register command. + * @param command_context The pointer to the command data structure. + * @return -1 if error or 0 if success + */ +int32_t SHELL_RegisterCommand(const shell_command_context_t *command_context); + +/*! + * @brief Main loop for Shell. + * Main loop for Shell; After this function is called, Shell begins to initialize the basic variables and starts to + * work. + * @param context The pointer to the Shell environment and runtime states. + * @return This function does not return until Shell command exit was called. + */ +int32_t SHELL_Main(p_shell_context_t context); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SHELL_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_ucwxp.inf b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_ucwxp.inf new file mode 100644 index 00000000000..e9e9e4f02fd --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/fsl_ucwxp.inf @@ -0,0 +1,104 @@ +[Version] +Signature="$Windows NT$" +Class=Ports +ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} +Provider=%MFGNAME% +LayoutFile=layout.inf +CatalogFile=%MFGFILENAME%.cat +DriverVer=02/16/2011,1.0 + +[Manufacturer] +%MFGNAME%=DeviceList, NTamd64 + +[DestinationDirs] +DefaultDestDir=12 + + +;------------------------------------------------------------------------------ +; Windows 2000/XP/Vista-32bit Sections +;------------------------------------------------------------------------------ + +[DriverInstall.nt] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles.nt +AddReg=DriverInstall.nt.AddReg + +[DriverCopyFiles.nt] +usbser.sys,,,0x20 + +[DriverInstall.nt.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,%DRIVERFILENAME%.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.nt.Services] +AddService=usbser, 0x00000002, DriverService.nt + +[DriverService.nt] +DisplayName=%SERVICE% +ServiceType=1 +StartType=3 +ErrorControl=1 +ServiceBinary=%12%\%DRIVERFILENAME%.sys + +;------------------------------------------------------------------------------ +; Vista-64bit Sections +;------------------------------------------------------------------------------ + +[DriverInstall.NTamd64] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles.NTamd64 +AddReg=DriverInstall.NTamd64.AddReg + +[DriverCopyFiles.NTamd64] +%DRIVERFILENAME%.sys,,,0x20 + +[DriverInstall.NTamd64.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,%DRIVERFILENAME%.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTamd64.Services] +AddService=usbser, 0x00000002, DriverService.NTamd64 + +[DriverService.NTamd64] +DisplayName=%SERVICE% +ServiceType=1 +StartType=3 +ErrorControl=1 +ServiceBinary=%12%\%DRIVERFILENAME%.sys + + +;------------------------------------------------------------------------------ +; Vendor and Product ID Definitions +;------------------------------------------------------------------------------ +; When developing your USB device, the VID and PID used in the PC side +; application program and the firmware on the microcontroller must match. +; Modify the below line to use your VID and PID. Use the format as shown below. +; Note: One INF file can be used for multiple devices with different VID and PIDs. +; For each supported device, append ",USB\VID_xxxx&PID_yyyy" to the end of the line. +;------------------------------------------------------------------------------ +[SourceDisksFiles] +[SourceDisksNames] +[DeviceList] +%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_0300 +%DESCRIPTION%=DriverInstall, USB\VID_1FC9&PID_0800&MI_00 + +[DeviceList.NTamd64] +%DESCRIPTION% = DriverInstall, USB\VID_1FC9&PID_0300 +%DESCRIPTION% = DriverInstall, USB\VID_1FC9&PID_0800&MI_00 + + +;------------------------------------------------------------------------------ +; String Definitions +;------------------------------------------------------------------------------ +;Modify these strings to customize your device +;------------------------------------------------------------------------------ +[Strings] +MFGFILENAME="CDC" +DRIVERFILENAME ="usbser" +MFGNAME="NXP" +INSTDISK="NXP CDC Driver Installer" +DESCRIPTION="Virtual Com Port" +SERVICE="NXP Virtual COM Driver" + diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.c new file mode 100644 index 00000000000..434564150d8 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.c @@ -0,0 +1,815 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "fsl_io.h" +#include "fsl_debug_console_conf.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* check avaliable device */ +#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT != 0)) +#define DEBUG_CONSOLE_IO_UART +#endif + +#if (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT != 0)) +#define DEBUG_CONSOLE_IO_IUART +#endif + +#if (defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT != 0)) +#define DEBUG_CONSOLE_IO_LPUART +#endif + +#if (defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT != 0)) +#define DEBUG_CONSOLE_IO_LPSCI +#endif + +#if ((defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT != 0)) && \ + (defined(BOARD_USE_VIRTUALCOM) && (BOARD_USE_VIRTUALCOM != 0))) +#define DEBUG_CONSOLE_IO_USBCDC +#endif + +#if (defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT != 0)) +#define DEBUG_CONSOLE_IO_FLEXCOMM +#endif + +#if (defined(FSL_FEATURE_SOC_VFIFO_COUNT) && (FSL_FEATURE_SOC_VFIFO_COUNT != 0)) +#define DEBUG_CONSOLE_IO_VUSART +#endif + +/* If none of above io is supported, enable the swo for debug console, or swo can be enabled by define + * DEBUG_CONSOLE_IO_SWO directly */ +#if (!defined(DEBUG_CONSOLE_IO_SWO) && !defined(DEBUG_CONSOLE_IO_UART) && !defined(DEBUG_CONSOLE_IO_IUART) && \ +!defined(DEBUG_CONSOLE_IO_LPUART) && \ + !defined(DEBUG_CONSOLE_IO_LPSCI) && !defined(DEBUG_CONSOLE_IO_USBCDC) && \ +!defined(DEBUG_CONSOLE_IO_FLEXCOMM) && \ + !defined(DEBUG_CONSOLE_IO_VUSART)) +#define DEBUG_CONSOLE_IO_SWO +#endif + +/* configuration for debug console device */ +/* If new device is required as the low level device for debug console, + * Add the #elif branch and add the preprocessor macro to judge whether + * this kind of device exist in this SOC. */ +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) +#include "fsl_uart.h" +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static uart_handle_t s_ioUartHandler; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART */ + +#if defined DEBUG_CONSOLE_IO_LPUART +#include "fsl_lpuart.h" +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static lpuart_handle_t s_ioLpuartHandler; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_IO_LPUART */ + +#if defined DEBUG_CONSOLE_IO_LPSCI +#include "fsl_lpsci.h" +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static lpsci_handle_t s_ioLpsciHandler; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_IO_LPSCI */ + +#if defined DEBUG_CONSOLE_IO_USBCDC +#include "usb_device_config.h" +#include "usb.h" +#include "usb_device_cdc_acm.h" +#include "usb_device_ch9.h" +#include "virtual_com.h" +#endif /* DEBUG_CONSOLE_IO_USBCDC */ + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) +#include "fsl_usart.h" +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static usart_handle_t s_ioUsartHandler; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART */ + +#if defined DEBUG_CONSOLE_IO_SWO +#include "fsl_swo.h" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Debug console IO state information. */ +static io_state_t s_debugConsoleIO = { + .ioBase = NULL, + .ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE, +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + .callBack = NULL, +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) +static void UART_Callback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData) +{ + bool tx = false, rx = false; + size_t size = 0U; + + if (status == kStatus_UART_RxIdle) + { + rx = true; + size = handle->txDataSizeAll; + } + + if (status == kStatus_UART_TxIdle) + { + tx = true; + size = handle->txDataSizeAll; + } + + /* inform the buffer layer that transfer is complete */ + if (s_debugConsoleIO.callBack != NULL) + { + /* call buffer callback function */ + s_debugConsoleIO.callBack(&size, rx, tx); + } +} +#endif /* defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART */ + +#if defined DEBUG_CONSOLE_IO_LPSCI +static void LPSCI_Callback(UART0_Type *base, lpsci_handle_t *handle, status_t status, void *userData) +{ + bool tx = false, rx = false; + size_t size = 0U; + + if (status == kStatus_LPSCI_RxIdle) + { + rx = true; + size = handle->txDataSizeAll; + } + + if (status == kStatus_LPSCI_TxIdle) + { + tx = true; + size = handle->txDataSizeAll; + } + + /* inform the buffer layer that transfer is complete */ + if (s_debugConsoleIO.callBack != NULL) + { + /* call buffer callback function */ + s_debugConsoleIO.callBack(&size, rx, tx); + } +} +#endif /* DEBUG_CONSOLE_IO_LPSCI */ + +#if defined DEBUG_CONSOLE_IO_LPUART +static void LPUART_Callback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData) +{ + bool tx = false, rx = false; + size_t size = 0U; + + if (status == kStatus_LPUART_RxIdle) + { + rx = true; + size = handle->txDataSizeAll; + } + + if (status == kStatus_LPUART_TxIdle) + { + tx = true; + size = handle->txDataSizeAll; + } + + /* inform the buffer layer that transfer is complete */ + if (s_debugConsoleIO.callBack != NULL) + { + /* call buffer callback function */ + s_debugConsoleIO.callBack(&size, rx, tx); + } +} +#endif /* DEBUG_CONSOLE_IO_LPUART */ + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) +static void USART_Callback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData) +{ + bool tx = false, rx = false; + size_t size = 0U; + + if (status == kStatus_USART_RxIdle) + { + rx = true; + size = handle->txDataSizeAll; + } + + if (status == kStatus_USART_TxIdle) + { + tx = true; + size = handle->txDataSizeAll; + } + + /* inform the buffer layer that transfer is complete */ + if (s_debugConsoleIO.callBack != NULL) + { + /* call buffer callback function */ + s_debugConsoleIO.callBack(&size, rx, tx); + } +} +#endif /* defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART */ +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer) +{ + assert(NULL != io); + + /* record device type/base */ + s_debugConsoleIO.ioType = io->ioType; + s_debugConsoleIO.ioBase = (void *)(io->ioBase); + + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: + { + uart_config_t uart_config; + UART_GetDefaultConfig(&uart_config); + uart_config.baudRate_Bps = baudRate; + /* Enable clock and initial UART module follow user configure structure. */ + UART_Init((UART_Type *)s_debugConsoleIO.ioBase, &uart_config, clkSrcFreq); + UART_EnableTx(s_debugConsoleIO.ioBase, true); + UART_EnableRx(s_debugConsoleIO.ioBase, true); +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + s_debugConsoleIO.callBack = io->callBack; + /* create handler for interrupt transfer */ + UART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUartHandler, UART_Callback, NULL); + /* start ring buffer */ + UART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUartHandler, ringBuffer, + DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); +#endif + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: + { + lpuart_config_t lpuart_config; + LPUART_GetDefaultConfig(&lpuart_config); + lpuart_config.baudRate_Bps = baudRate; + /* Enable clock and initial UART module follow user configure structure. */ + LPUART_Init((LPUART_Type *)s_debugConsoleIO.ioBase, &lpuart_config, clkSrcFreq); + LPUART_EnableTx(s_debugConsoleIO.ioBase, true); + LPUART_EnableRx(s_debugConsoleIO.ioBase, true); +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + s_debugConsoleIO.callBack = io->callBack; + /* create handler for interrupt transfer */ + LPUART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, LPUART_Callback, NULL); + /* start ring buffer */ + LPUART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, ringBuffer, + DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); +#endif + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: + { + lpsci_config_t lpsci_config; + LPSCI_GetDefaultConfig(&lpsci_config); + lpsci_config.baudRate_Bps = baudRate; + /* Enable clock and initial UART module follow user configure structure. */ + LPSCI_Init((UART0_Type *)s_debugConsoleIO.ioBase, &lpsci_config, clkSrcFreq); + LPSCI_EnableTx(s_debugConsoleIO.ioBase, true); + LPSCI_EnableRx(s_debugConsoleIO.ioBase, true); +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + s_debugConsoleIO.callBack = io->callBack; + /* create handler for interrupt transfer */ + LPSCI_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, LPSCI_Callback, NULL); + /* start ring buffer */ + LPSCI_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, ringBuffer, + DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); +#endif + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_USBCDC + case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: + { + s_debugConsoleIO.ioBase = USB_VcomInit(); + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_FLEXCOMM + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + { + usart_config_t usart_config; + USART_GetDefaultConfig(&usart_config); + usart_config.baudRate_Bps = baudRate; + /* Enable clock and initial UART module follow user configure structure. */ + USART_Init((USART_Type *)s_debugConsoleIO.ioBase, &usart_config, clkSrcFreq); +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + s_debugConsoleIO.callBack = io->callBack; + /* create handler for interrupt transfer */ + USART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUsartHandler, USART_Callback, NULL); + /* start ring buffer */ + USART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler, ringBuffer, + DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); +#endif + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_VUSART + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: + { + usart_config_t usart_config; + USART_GetDefaultConfig(&usart_config); + usart_config.baudRate_Bps = baudRate; + usart_config.enableRx = true; + usart_config.enableTx = true; + /* Enable rx fifo for user's continously input */ + usart_config.fifoConfig.enableRxFifo = true; + usart_config.fifoConfig.rxFifoSize = 8; + /* Enable clock and initial UART module follow user configure structure. */ + USART_Init((USART_Type *)s_debugConsoleIO.ioBase, &usart_config, clkSrcFreq); +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + s_debugConsoleIO.callBack = io->callBack; + /* create handler for interrupt transfer */ + USART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUsartHandler, USART_Callback, NULL); + /* start ring buffer */ + USART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler, ringBuffer, + DEBUG_CONSOLE_RECEIVE_BUFFER_LEN); +#endif + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_SWO + case DEBUG_CONSOLE_DEVICE_TYPE_SWO: + SWO_Init((uint32_t)s_debugConsoleIO.ioBase, baudRate, clkSrcFreq); + break; +#endif + default: + break; + } +} + +status_t IO_Deinit(void) +{ + if (s_debugConsoleIO.ioType == DEBUG_CONSOLE_DEVICE_TYPE_NONE) + { + return kStatus_Success; + } + + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* stop ring buffer */ + UART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioUartHandler); +#endif + /* Disable UART module. */ + UART_Deinit((UART_Type *)s_debugConsoleIO.ioBase); + + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* stop ring buffer */ + LPSCI_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpsciHandler); +#endif + /* Disable LPSCI module. */ + LPSCI_Deinit((UART0_Type *)s_debugConsoleIO.ioBase); + + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* stop ring buffer */ + LPUART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpuartHandler); +#endif + /* Disable LPUART module. */ + LPUART_Deinit((LPUART_Type *)s_debugConsoleIO.ioBase); + + break; +#endif +#if defined DEBUG_CONSOLE_IO_USBCDC + case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: + /* Disable USBCDC module. */ + USB_VcomDeinit(s_debugConsoleIO.ioBase); + break; +#endif +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* stop ring buffer */ + USART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler); +#endif + /* deinit IO */ + USART_Deinit((USART_Type *)s_debugConsoleIO.ioBase); + + break; +#endif + +#if defined DEBUG_CONSOLE_IO_SWO + + case DEBUG_CONSOLE_DEVICE_TYPE_SWO: + SWO_Deinit((uint32_t)s_debugConsoleIO.ioBase); + break; +#endif + default: + s_debugConsoleIO.ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE; + break; + } + + s_debugConsoleIO.ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE; + + return kStatus_Success; +} + +status_t IO_WaitIdle(void) +{ + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + /* wait transfer complete flag */ + while (!(UART_GetStatusFlags(s_debugConsoleIO.ioBase) & kUART_TransmissionCompleteFlag)) + { + } + + break; +#endif + +#if (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: + /* wait transfer complete flag */ + while (!(UART_GetStatusFlag(s_debugConsoleIO.ioBase, kUART_TxCompleteFlag))) + { + } + + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: + /* wait transfer complete flag */ + while (!(LPSCI_GetStatusFlags(s_debugConsoleIO.ioBase) & kLPSCI_TransmissionCompleteFlag)) + { + } + + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: + /* wait transfer complete flag */ + while (!(LPUART_GetStatusFlags(s_debugConsoleIO.ioBase) & kLPUART_TransmissionCompleteFlag)) + { + } + break; +#endif + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: + /* wait transfer complete flag */ + while (!(USART_GetStatusFlags(s_debugConsoleIO.ioBase) & kUSART_TxFifoEmptyFlag)) + { + } + break; +#endif + default: + break; + } + + return kStatus_Success; +} + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + +status_t IO_Transfer(uint8_t *ch, size_t size, bool tx) +{ + status_t status = kStatus_Fail; + + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: + { + uart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + /* transfer data */ + if (tx) + { + status = UART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer); + } + else + { + status = UART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer, NULL); + } + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: + { + lpsci_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + /* transfer data */ + if (tx) + { + status = LPSCI_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer); + } + else + { + status = LPSCI_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer, NULL); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: + { + lpuart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + /* transfer data */ + if (tx) + { + status = LPUART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer); + } + else + { + status = + LPUART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer, NULL); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_USBCDC + case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: + { + if (tx) + { + USB_VcomWriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + USB_VcomReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: + { + usart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + /* transfer data */ + if (tx) + { + status = USART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer); + } + else + { + status = USART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer, NULL); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_SWO + case DEBUG_CONSOLE_DEVICE_TYPE_SWO: + status = SWO_SendBlocking((uint32_t)s_debugConsoleIO.ioBase, ch, size); + break; +#endif + default: + break; + } + + return status; +} + +status_t IO_TryReceiveCharacter(uint8_t *ch) +{ + status_t status = kStatus_Fail; + uint32_t size = 1U; + + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: + { + uart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + if (UART_TransferGetRxRingBufferLength(&s_ioUartHandler) >= size) + { + /* transfer data */ + status = UART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer, NULL); + } + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: + { + lpsci_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + if (LPSCI_TransferGetRxRingBufferLength(&s_ioLpsciHandler) >= size) + { + /* transfer data */ + status = LPSCI_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer, NULL); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: + { + lpuart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + if (LPUART_TransferGetRxRingBufferLength(s_debugConsoleIO.ioBase, &s_ioLpuartHandler) >= size) + { + /* transfer data */ + status = + LPUART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer, NULL); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_USBCDC + case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: + break; +#endif + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: + { + usart_transfer_t transfer = {0U}; + transfer.data = ch; + transfer.dataSize = size; + if (USART_TransferGetRxRingBufferLength(&s_ioUsartHandler) >= size) + { + /* transfer data */ + status = USART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer, NULL); + } + } + break; +#endif + default: + break; + } + + return status; +} + +#else + +status_t IO_Transfer(uint8_t *ch, size_t size, bool tx) +{ + status_t status = kStatus_Success; + switch (s_debugConsoleIO.ioType) + { +#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART) + case DEBUG_CONSOLE_DEVICE_TYPE_UART: + case DEBUG_CONSOLE_DEVICE_TYPE_IUART: + { + if (tx) + { + UART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + status = UART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif +#if defined DEBUG_CONSOLE_IO_LPSCI + case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI: + { + if (tx) + { + LPSCI_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + status = LPSCI_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_LPUART + case DEBUG_CONSOLE_DEVICE_TYPE_LPUART: + { + if (tx) + { + LPUART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + status = LPUART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_USBCDC + case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC: + { + if (tx) + { + USB_VcomWriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + status = USB_VcomReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif + +#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART) + case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM: + case DEBUG_CONSOLE_DEVICE_TYPE_VUSART: + { + if (tx) + { + USART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size); + } + else + { + status = USART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size); + } + } + break; +#endif + +#if defined DEBUG_CONSOLE_IO_SWO + case DEBUG_CONSOLE_DEVICE_TYPE_SWO: + status = SWO_SendBlocking((uint32_t)s_debugConsoleIO.ioBase, ch, size); + break; +#endif + default: + status = kStatus_Fail; + break; + } + + return status; +} + +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.h new file mode 100644 index 00000000000..396f66c70f3 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/fsl_io.h @@ -0,0 +1,140 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _FSL_IO_H +#define _FSL_IO_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief define a notify callback for IO +* @param size , transfer data size. +* @param rx, indicate a rx transfer is success. +* @param tx, indicate a tx transfer is success. +*/ +typedef void (*notify)(size_t *size, bool rx, bool tx); + +/*! @brief State structure storing io. */ +typedef struct io_State +{ + void *ioBase; /*!< Base of the IP register. */ + uint8_t ioType; /*!< device type */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + notify callBack; /*!< define the callback function for buffer */ +#endif + +} io_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief io init function. + * + * Call this function to init IO. + * + * @param io configuration pointer + * @param baudRate baud rate + * @param clkSrcFreq clock freq + * @param ringbuffer used to receive character + */ +void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer); + +/*! + * @brief Deinit IO. + * + * Call this function to Deinit IO. + * + * @return deinit status + */ +status_t IO_Deinit(void); + +/*! + * @brief io transfer function. + * + * Call this function to transfer log. + * Print log: + * @code + * IO_Transfer(ch, size, true); + * @endcode + * Scanf log: + * @code + * IO_Transfer(ch, size, false); + * @endcode + * + * @param ch transfer buffer pointer + * @param size transfer size + * @param tx indicate the transfer is TX or RX + */ +status_t IO_Transfer(uint8_t *ch, size_t size, bool tx); + +/*! + * @brief io wait idle. + * + * Call this function to wait the io idle + * + * @return Indicates whether wait idle was successful or not. + */ +status_t IO_WaitIdle(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief io try to receive one character. + * + * Call this function try to receive character + * @param ch the address of char to receive + * @return Indicates try getchar was successful or not. + */ +status_t IO_TryReceiveCharacter(uint8_t *ch); +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_IO_H */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.c new file mode 100644 index 00000000000..c1360a2c9f2 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.c @@ -0,0 +1,121 @@ +/* + * The Clear BSD License + * Copyright 2018 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "fsl_swo.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* SWO encoding protocol definition */ +#ifndef FSL_DEBUG_CONSOLE_SWO_PROTOCOL +#define FSL_DEBUG_CONSOLE_SWO_PROTOCOL kSWO_ProtocolNrz +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +status_t SWO_Init(uint32_t port, uint32_t baudRate, uint32_t clkSrcFreq) +{ + assert(baudRate <= clkSrcFreq); + assert((clkSrcFreq / baudRate) <= TPI_ACPR_PRESCALER_Msk); + assert((TPI->DEVID & (kSWO_ProtocolNrz | kSWO_ProtocolManchester)) != 0U); + + uint32_t prescaler = clkSrcFreq / baudRate - 1U; + + /* enable the ITM and DWT units */ + CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk; + + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) == 0U) + { + return kStatus_Fail; + } + /* Lock access */ + ITM->LAR = 0xC5ACCE55U; + /* Disable ITM */ + ITM->TER &= ~(1U << port); + ITM->TCR = 0U; + /* select SWO encoding protocol */ + TPI->SPPR = FSL_DEBUG_CONSOLE_SWO_PROTOCOL; + /* select asynchronous clock prescaler */ + TPI->ACPR = prescaler & 0xFFFFU; + /* allow unprivilege access */ + ITM->TPR = 0U; + /* enable ITM */ + ITM->TCR = + ITM_TCR_ITMENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_TraceBusID_Msk | ITM_TCR_SWOENA_Msk | ITM_TCR_DWTENA_Msk; + /* enable the port bits */ + ITM->TER = 1U << port; + + return kStatus_Success; +} + +void SWO_Deinit(uint32_t port) +{ + /* disable ITM */ + ITM->TER &= ~(1U << port); +} + +status_t SWO_SendBlocking(uint32_t port, uint8_t *ch, size_t size) +{ + assert(ch != NULL); + assert((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0U); + assert((ITM->TER & (1U << port)) != 0U); + + uint16_t *strAddr = (uint16_t *)ch; + + while (size) + { + /* wait FIFO ready */ + while (ITM->PORT[port].u32 == 0U) + { + } + + if (size >= 2U) + { + size -= 2U; + ITM->PORT[port].u16 = *strAddr; + } + else + { + size -= 1U; + ITM->PORT[port].u8 = *((uint8_t *)strAddr); + } + strAddr++; + } + + return kStatus_Success; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.h new file mode 100644 index 00000000000..94cd6516828 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/io/swo/fsl_swo.h @@ -0,0 +1,101 @@ +/* + * The Clear BSD License + * Copyright 2018 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _FSL_SWO_H_ +#define _FSL_SWO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* swo protocol */ +enum _swo_protocol +{ + kSWO_ProtocolManchester = 1U, /*!< SWO manchester protocol */ + kSWO_ProtocolNrz = 2U, /*!< SWO UART/NRZ protocol */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief io init function. + * + * Call this function to init SWO. + * + * @param port port used to transfer data + * @param baudRate SWO clock + * @param clkSrcFreq core clock frequency + */ +status_t SWO_Init(uint32_t port, uint32_t baudRate, uint32_t clkSrcFreq); + +/*! + * @brief Deinit IO. + * + * Call this function to Deinit SWO. + * + * @param port port to deinit. + * @return deinit status + */ +void SWO_Deinit(uint32_t port); + +/*! + * @brief io transfer function. + * + * Call this function to print log. + * + * @param port port used to transfer data + * @param ch transfer buffer pointer + * @param size transfer size + */ +status_t SWO_SendBlocking(uint32_t port, uint8_t *ch, size_t size); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_SWO_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.c new file mode 100644 index 00000000000..e36832d36d1 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.c @@ -0,0 +1,587 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "fsl_log.h" +#include "fsl_debug_console_conf.h" +#include "fsl_io.h" +#ifdef FSL_RTOS_FREE_RTOS +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef BACKSPACE +/*! @brief character backspace ASCII value */ +#define BACKSPACE 127 +#endif + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief increase pop member */ +#define LOG_CHECK_BUFFER_INDEX_OVERFLOW(index) \ + { \ + if (index >= DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN) \ + { \ + index -= DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; \ + } \ + \ +\ +} + +/*! @brief get current runing environment is ISR or not */ +#ifdef __CA7_REV +#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel() +#else +#define IS_RUNNING_IN_ISR() __get_IPSR() +#endif /* __CA7_REV */ + +#else +#define IS_RUNNING_IN_ISR() (0U) +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/* define for rtos */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) +/* metex semaphore */ +#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) (mutex = xSemaphoreCreateMutex()) + +#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) \ + \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + xSemaphoreGive(mutex); \ + } \ + \ +} + +#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \ + \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + xSemaphoreTake(mutex, portMAX_DELAY); \ + } \ + \ +} + +#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \ + \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + result = xSemaphoreTake(mutex, 0U); \ + } \ + else \ + { \ + result = 1U; \ + } \ + \ +} + +/* Binary semaphore */ +#define LOG_CREATE_BINARY_SEMAPHORE(binary) (binary = xSemaphoreCreateBinary()) +#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (xSemaphoreTake(binary, portMAX_DELAY)) +#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (xSemaphoreGiveFromISR(binary, NULL)) + +#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) + +#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) +#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) +#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) +#define LOG_CREATE_BINARY_SEMAPHORE(binary) +#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \ + \ +{ \ + while (!binary) \ + ; \ + binary = false; \ + \ +\ +} +#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true) +#else +#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) +#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/* add other implementation here +*such as : +* #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_xxx) +*/ + +#else + +#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) +#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) +#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) +#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) +#define LOG_CREATE_BINARY_SEMAPHORE(binary) +#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief Define the buffer +* The total buffer size should be calucate as (BUFFER_SUPPORT_LOG_LENGTH + 1) * BUFFER_SUPPORT_LOG_NUM * 4 +*/ +typedef struct _log_buffer +{ + volatile uint16_t totalIndex; /*!< indicate the total usage of the buffer */ + volatile uint16_t pushIndex; /*!< indicate the next push index */ + volatile uint16_t popIndex; /*!< indicate the pop index */ + uint8_t txBuf[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; /*!< buffer to store printf log */ + + uint8_t rxBuf[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; /*!< buffer to store scanf log */ +} log_buffer_t; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/* A global log buffer */ +static log_buffer_t s_log_buffer; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/* lock definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static SemaphoreHandle_t s_logPushSemaphore = NULL; +static SemaphoreHandle_t s_logReadSemaphore = NULL; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +static SemaphoreHandle_t s_logPopSemaphore = NULL; +static SemaphoreHandle_t s_logReadWaitSemaphore = NULL; + +#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + +static volatile bool s_logReadWaitSemaphore = false; /* transferred event from ISR for bare-metal + interrupt */ + +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +#else +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/******************************************************************************* +* Prototypes +******************************************************************************/ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief callback function for IO layer to notify LOG + * + * @param size last transfer data size + * @param receive indicate a RX transfer + * @param transmit indicate a TX transfer + * + */ +static void LOG_Transferred(size_t *size, bool receive, bool transmit); + +/*! + * @brief log push function + * + * @param buf target buffer + * @param size log size + * + */ +static int LOG_BufPush(uint8_t *buf, size_t size); + +/*! + * @brief Get next avaliable log + * + * @param next avaliable size + * @return next avaliable address + */ +static uint8_t *LOG_BufGetNextAvaliableLog(size_t *size); + +/*! + * @brief buf pop + * + * @param size log size popped and next available log size + * @return next avaliable address + */ +static uint8_t *LOG_BufPop(size_t *size); + +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*! + * @brief read one character + * + * @param ch character address + * @return indicate the read status + * + */ +static status_t LOG_ReadOneCharacter(uint8_t *ch); + +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION +/*! + * @brief echo one character + * + * @param ch character address + * @param isGetchar flag to distinguish getchar from scanf + * @param index special for scanf to support backspace + * @return indicate the read status + * + */ +static status_t LOG_EchoCharacter(uint8_t *ch, bool isGetChar, int *index); +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq) +{ + io_state_t io; + /* init io */ + io.ioBase = (void *)baseAddr; + io.ioType = device; + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* memset the global queue */ + memset(&s_log_buffer, 0U, sizeof(s_log_buffer)); + /* init callback for NON-BLOCKING */ + io.callBack = LOG_Transferred; + /* io init function */ + IO_Init(&io, baudRate, clkSrcFreq, s_log_buffer.rxBuf); + /* Debug console buffer push lock create */ + LOG_CREATE_MUTEX_SEMAPHORE(s_logPushSemaphore); + /* Debug console get/scanf mutex lock create */ + LOG_CREATE_MUTEX_SEMAPHORE(s_logReadSemaphore); +#else + IO_Init(&io, baudRate, clkSrcFreq, NULL); +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + + /* Debug console lock create */ + LOG_CREATE_MUTEX_SEMAPHORE(s_logPopSemaphore); + LOG_CREATE_BINARY_SEMAPHORE(s_logReadWaitSemaphore); + + return kStatus_Success; +} + +void LOG_Deinit(void) +{ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* memset the global queue */ + memset(&s_log_buffer, 0U, sizeof(s_log_buffer)); +#endif /*DEBUG_CONSOLE_TRANSFER_NON_BLOCKING*/ + /* Deinit IO */ + IO_Deinit(); +} + +status_t LOG_WaitIdle(void) +{ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* wait buffer empty */ + while (!(s_log_buffer.totalIndex == 0U)) + ; +#endif /*DEBUG_CONSOLE_TRANSFER_NON_BLOCKING*/ + /* wait IO idle */ + IO_WaitIdle(); + + return kStatus_Success; +} + +int LOG_Push(uint8_t *buf, size_t size) +{ + assert(buf != NULL); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + /* push to buffer */ + LOG_BufPush(buf, size); + buf = LOG_BufGetNextAvaliableLog(&size); +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + /* pop log */ + return LOG_Pop(buf, size); +} + +int LOG_Pop(uint8_t *buf, size_t size) +{ + uint8_t getLock = 0U; + + if ((0 != size) && (NULL != buf)) + { + /* take POP lock, should be non-blocking */ + LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(s_logPopSemaphore, getLock); + + if (getLock) + { + /* call IO transfer function */ + if (IO_Transfer(buf, size, true) != kStatus_Success) + { + size = 0U; + } + /* release POP lock */ + LOG_GIVE_MUTEX_SEMAPHORE(s_logPopSemaphore); + } + } + + return size; +} + +int LOG_ReadLine(uint8_t *buf, size_t size) +{ + assert(buf != NULL); + + int i = 0; + + /* take mutex lock function */ + LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logReadSemaphore); + + for (i = 0; i < size; i++) + { + /* recieve one char every time */ + if (LOG_ReadOneCharacter(&buf[i]) != kStatus_Success) + { + return -1; + } +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + LOG_EchoCharacter(&buf[i], false, &i); +#endif + /* analysis data */ + if ((buf[i] == '\r') || (buf[i] == '\n')) + { + /* End of Line. */ + if (i == 0) + { + buf[i] = '\0'; + i = -1; + } + else + { + break; + } + } + } + /* get char should not add '\0'*/ + if (i == size) + { + buf[i] = '\0'; + } + else + { + buf[i + 1] = '\0'; + } + + /* release mutex lock function */ + LOG_GIVE_MUTEX_SEMAPHORE(s_logReadSemaphore); + + return i; +} + +int LOG_ReadCharacter(uint8_t *ch) +{ + assert(ch != NULL); + int ret = 0; + + /* take mutex lock function */ + LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logReadSemaphore); + /* read one character */ + if (LOG_ReadOneCharacter(ch) == kStatus_Success) + { + ret = 1; +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + LOG_EchoCharacter(ch, true, NULL); +#endif + } + else + { + ret = -1; + } + + /* release mutex lock function */ + LOG_GIVE_MUTEX_SEMAPHORE(s_logReadSemaphore); + + return ret; +} + +static status_t LOG_ReadOneCharacter(uint8_t *ch) +{ + /* recieve one char every time */ + if (IO_Transfer(ch, 1U, false) != kStatus_Success) + { + return kStatus_Fail; + } + + /* wait release from ISR */ + LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(s_logReadWaitSemaphore); + + return kStatus_Success; +} + +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION +static status_t LOG_EchoCharacter(uint8_t *ch, bool isGetChar, int *index) +{ + /* Due to scanf take \n and \r as end of string,should not echo */ + if (((*ch != '\r') && (*ch != '\n')) || (isGetChar)) + { + /* recieve one char every time */ + if (IO_Transfer(ch, 1U, true) != kStatus_Success) + { + return kStatus_Fail; + } + } + + if (!isGetChar) + { + if ((*index > 0) && (*ch == BACKSPACE)) + { + *index -= 2; + } + } + + return kStatus_Success; +} +#endif + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +static int LOG_BufPush(uint8_t *buf, size_t size) +{ + uint32_t pushIndex = 0U, i = 0U; + bool pushAvaliable = false; + + /* take mutex lock function */ + LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logPushSemaphore); + if (size <= (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - s_log_buffer.totalIndex)) + { + /* get push index */ + pushIndex = s_log_buffer.pushIndex; + s_log_buffer.pushIndex += size; + /* check index overflow */ + LOG_CHECK_BUFFER_INDEX_OVERFLOW(s_log_buffer.pushIndex); + /* update push/total index value */ + s_log_buffer.totalIndex += size; + pushAvaliable = true; + } + /* release mutex lock function */ + LOG_GIVE_MUTEX_SEMAPHORE(s_logPushSemaphore); + + /* check the buffer if have enough space to store the log */ + if (pushAvaliable) + { + for (i = size; i > 0; i--) + { + /* copy log to buffer, the buffer only support a fixed length argument, if the log argument + is longer than the fixed length, the left argument will be losed */ + s_log_buffer.txBuf[pushIndex] = *buf++; + /* increase index */ + pushIndex++; + /* check index overflow */ + LOG_CHECK_BUFFER_INDEX_OVERFLOW(pushIndex); + } + } + else + { + size = 0U; + } + + return size; +} + +static uint8_t *LOG_BufGetNextAvaliableLog(size_t *size) +{ + uint16_t popIndex = s_log_buffer.popIndex; + + /* get avaliable size */ + if (s_log_buffer.totalIndex > (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - popIndex)) + { + *size = (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - popIndex); + } + else + { + *size = s_log_buffer.totalIndex; + } + + /* return address */ + return (&(s_log_buffer.txBuf[popIndex])); +} + +static uint8_t *LOG_BufPop(size_t *size) +{ + if (s_log_buffer.totalIndex >= *size) + { + /* decrease the log total member */ + s_log_buffer.totalIndex -= *size; + /* there is more log in the queue to be pushed */ + if (s_log_buffer.totalIndex > 0U) + { + /* update the pop index */ + s_log_buffer.popIndex += *size; + /* check index overflow */ + LOG_CHECK_BUFFER_INDEX_OVERFLOW(s_log_buffer.popIndex); + + return LOG_BufGetNextAvaliableLog(size); + } + else + { + /* reset push and pop */ + s_log_buffer.popIndex = 0U; + s_log_buffer.pushIndex = 0U; + *size = 0U; + } + } + + return NULL; +} + +static void LOG_Transferred(size_t *size, bool receive, bool transmit) +{ + uint8_t *addr = NULL; + + if (transmit) + { + addr = LOG_BufPop(size); + /* continue pop log from buffer */ + LOG_Pop(addr, *size); + } + + if (receive) + { + /* release from ISR */ + LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_logReadWaitSemaphore); + } +} +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +status_t LOG_TryReadCharacter(uint8_t *ch) +{ + if (NULL != ch) + { + return IO_TryReceiveCharacter(ch); + } + return kStatus_Fail; +} +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.h new file mode 100644 index 00000000000..87f4c8a7b81 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/log/fsl_log.h @@ -0,0 +1,146 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _FSL_LOG_H +#define _FSL_LOG_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/************************************************************************************************* + * Prototypes + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Initializes + * + * Call this function to init the buffer + * @param baseAddr, device base address + * @param device, device type + * @param baudRate, device communicate baudrate + * @param clkSrcFreq, device source clock freq + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + * @retval kStatus_Fail Execution failure + */ +status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq); + +/*! + * @brief De-Initializes + * + * Call this function to deinit the buffer + * + * @return Indicates whether Deinit was successful or not. + */ +void LOG_Deinit(void); + +/*! + * @brief log push interface + * + * Call this function to print log + * @param fmt, buffer pointer + * @param size, avaliable size + * @return indicate the push size + * @retval-1 indicate buffer is full or transfer fail. + * @retval size return the push log size. + */ +int LOG_Push(uint8_t *buf, size_t size); + +/*! + * @brief log read one line function + * + * Call this function to print log + * @param fmt, buffer pointer + * @param size, avaliable size + * @reutrn the number of the recieved character + */ +int LOG_ReadLine(uint8_t *buf, size_t size); + +/*! + * @brief log read one character function + * + * Call this function to GETCHAR + * @param ch receive address + * @reutrn the number of the recieved character + */ +int LOG_ReadCharacter(uint8_t *ch); + +/*! + * @brief wait log and io idle + * + * Call this function to wait log buffer empty and io idle before enter low power mode. + * @return Indicates whether wait idle was successful or not. + */ +status_t LOG_WaitIdle(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief log try read one character + * Call this function to check character avaliable or not, if not return fail, otherwise return it. + * @param ch the address of char to receive + * @return Indicates try getchar was successful or not. + */ +status_t LOG_TryReadCharacter(uint8_t *ch); +#endif + +/*! + * @brief log pop function + * + * Call this function to pop log from buffer. + * @param buf buffer address to pop + * @param size log size to pop + * @return pop log size. + */ +int LOG_Pop(uint8_t *buf, size_t size); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.c new file mode 100644 index 00000000000..d34e41a3ad0 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.c @@ -0,0 +1,1327 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include +#include +#include +#include "fsl_str.h" +#include "fsl_debug_console_conf.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The overflow value.*/ +#ifndef HUGE_VAL +#define HUGE_VAL (99.e99) +#endif /* HUGE_VAL */ + +#if SCANF_FLOAT_ENABLE +static double fnum = 0.0; +#endif /* SCANF_FLOAT_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE +/*! @brief Specification modifier flags for printf. */ +enum _debugconsole_printf_flag +{ + kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ + kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ + kPRINTF_Space = 0x04U, /*!< Space Flag. */ + kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ + kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ + kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ + kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ + kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ + kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ +}; +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Specification modifier flags for scanf. */ +enum _debugconsole_scanf_flag +{ + kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ + kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ + kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ + kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ + kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ + kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ + kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ + kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ +#if SCANF_ADVANCED_ENABLE + kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ + kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ + kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ + kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ +#endif /* SCANF_ADVANCED_ENABLE */ +#if PRINTF_FLOAT_ENABLE + kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ +#endif /*PRINTF_FLOAT_ENABLE */ + kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ +}; + +/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ +#if defined(__CC_ARM) +#pragma diag_suppress 1256 +#endif /* __CC_ARM */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Scanline function which ignores white spaces. + * + * @param[in] s The address of the string pointer to update. + * @return String without white spaces. + */ +static uint32_t ScanIgnoreWhiteSpace(const char **s); + +/*! + * @brief Converts a radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] neg Polarity of the number. + * @param[in] radix The radix to be converted to. + * @param[in] use_caps Used to identify %x/X output format. + + * @return Length of the converted string. + */ +static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps); + +#if PRINTF_FLOAT_ENABLE +/*! + * @brief Converts a floating radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] radix The radix to be converted to. + * @param[in] precision_width Specify the precision width. + + * @return Length of the converted string. + */ +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width); +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! +* + */ +double modf(double input_dbl, double *intpart_ptr); + +/*************Code for process formatted data*******************************/ + +static uint32_t ScanIgnoreWhiteSpace(const char **s) +{ + uint8_t count = 0; + uint8_t c; + + c = **s; + while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) + { + count++; + (*s)++; + c = **s; + } + return count; +} + +static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps) +{ +#if PRINTF_ADVANCED_ENABLE + int64_t a; + int64_t b; + int64_t c; + + uint64_t ua; + uint64_t ub; + uint64_t uc; +#else + int32_t a; + int32_t b; + int32_t c; + + uint32_t ua; + uint32_t ub; + uint32_t uc; +#endif /* PRINTF_ADVANCED_ENABLE */ + + int32_t nlen; + char *nstrp; + + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + + if (neg) + { +#if PRINTF_ADVANCED_ENABLE + a = *(int64_t *)nump; +#else + a = *(int32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (a == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (a != 0) + { +#if PRINTF_ADVANCED_ENABLE + b = (int64_t)a / (int64_t)radix; + c = (int64_t)a - ((int64_t)b * (int64_t)radix); + if (c < 0) + { + uc = (uint64_t)c; + c = (int64_t)(~uc) + 1 + '0'; + } +#else + b = a / radix; + c = a - (b * radix); + if (c < 0) + { + uc = (uint32_t)c; + c = (uint32_t)(~uc) + 1 + '0'; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + else + { +#if PRINTF_ADVANCED_ENABLE + ua = *(uint64_t *)nump; +#else + ua = *(uint32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (ua == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (ua != 0) + { +#if PRINTF_ADVANCED_ENABLE + ub = (uint64_t)ua / (uint64_t)radix; + uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix); +#else + ub = ua / (uint32_t)radix; + uc = ua - (ub * (uint32_t)radix); +#endif /* PRINTF_ADVANCED_ENABLE */ + + if (uc < 10) + { + uc = uc + '0'; + } + else + { + uc = uc - 10 + (use_caps ? 'A' : 'a'); + } + ua = ub; + *nstrp++ = (char)uc; + ++nlen; + } + } + return nlen; +} + +#if PRINTF_FLOAT_ENABLE +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width) +{ + int32_t a; + int32_t b; + int32_t c; + int32_t i; + uint32_t uc; + double fa; + double dc; + double fb; + double r; + double fractpart; + double intpart; + + int32_t nlen; + char *nstrp; + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + r = *(double *)nump; + if (!r) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + fractpart = modf((double)r, (double *)&intpart); + /* Process fractional part. */ + for (i = 0; i < precision_width; i++) + { + fractpart *= radix; + } + if (r >= 0) + { + fa = fractpart + (double)0.5; + if (fa >= pow(10, precision_width)) + { + intpart++; + } + } + else + { + fa = fractpart - (double)0.5; + if (fa <= -pow(10, precision_width)) + { + intpart--; + } + } + for (i = 0; i < precision_width; i++) + { + fb = fa / (int32_t)radix; + dc = (fa - (int64_t)fb * (int32_t)radix); + c = (int32_t)dc; + if (c < 0) + { + uc = (uint32_t)c; + c = (int32_t)(~uc) + 1 + '0'; + } + else + { + c = c + '0'; + } + fa = fb; + *nstrp++ = (char)c; + ++nlen; + } + *nstrp++ = (char)'.'; + ++nlen; + a = (int32_t)intpart; + if (a == 0) + { + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) + { + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + uc = (uint32_t)c; + c = (int32_t)(~uc) + 1 + '0'; + } + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + return nlen; +} +#endif /* PRINTF_FLOAT_ENABLE */ + +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) +{ + /* va_list ap; */ + char *p; + int32_t c; + + char vstr[33]; + char *vstrp = NULL; + int32_t vlen = 0; + + int32_t done; + int32_t count = 0; + + uint32_t field_width; + uint32_t precision_width; + char *sval; + int32_t cval; + bool use_caps; + uint8_t radix = 0; + +#if PRINTF_ADVANCED_ENABLE + uint32_t flags_used; + int32_t schar, dschar; + int64_t ival; + uint64_t uval = 0; + bool valid_precision_width; +#else + int32_t ival; + uint32_t uval = 0; +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_FLOAT_ENABLE + double fval; +#endif /* PRINTF_FLOAT_ENABLE */ + + /* Start parsing apart the format string and display appropriate formats and data. */ + for (p = (char *)fmt; (c = *p) != 0; p++) + { + /* + * All formats begin with a '%' marker. Special chars like + * '\n' or '\t' are normally converted to the appropriate + * character by the __compiler__. Thus, no need for this + * routine to account for the '\' character. + */ + if (c != '%') + { + cb(buf, &count, c, 1); + /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ + continue; + } + + use_caps = true; + +#if PRINTF_ADVANCED_ENABLE + /* First check for specification modifier flags. */ + flags_used = 0; + done = false; + while (!done) + { + switch (*++p) + { + case '-': + flags_used |= kPRINTF_Minus; + break; + case '+': + flags_used |= kPRINTF_Plus; + break; + case ' ': + flags_used |= kPRINTF_Space; + break; + case '0': + flags_used |= kPRINTF_Zero; + break; + case '#': + flags_used |= kPRINTF_Pound; + break; + default: + /* We've gone one char too far. */ + --p; + done = true; + break; + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + + /* Next check for minimum field width. */ + field_width = 0; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + field_width = (field_width * 10) + (c - '0'); + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + field_width = (uint32_t)va_arg(ap, uint32_t); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + /* Next check for the width and precision field separator. */ + precision_width = 6; +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = false; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (*++p == '.') + { + /* Must get precision field width, if present. */ + precision_width = 0; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + precision_width = (precision_width * 10) + (c - '0'); +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = true; +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + precision_width = (uint32_t)va_arg(ap, uint32_t); + valid_precision_width = true; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + } + else + { + /* We've gone one char too far. */ + --p; + } +#if PRINTF_ADVANCED_ENABLE + /* + * Check for the length modifier. + */ + switch (/* c = */ *++p) + { + case 'h': + if (*++p != 'h') + { + flags_used |= kPRINTF_LengthShortInt; + --p; + } + else + { + flags_used |= kPRINTF_LengthChar; + } + break; + case 'l': + if (*++p != 'l') + { + flags_used |= kPRINTF_LengthLongInt; + --p; + } + else + { + flags_used |= kPRINTF_LengthLongLongInt; + } + break; + default: + /* we've gone one char too far */ + --p; + break; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + /* Now we're ready to examine the format. */ + c = *++p; + { + if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') || + (c == 'b') || (c == 'p') || (c == 'u')) + { + if ((c == 'd') || (c == 'i')) + { +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + ival = (int64_t)va_arg(ap, int64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + ival = (int32_t)va_arg(ap, int32_t); + } + vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (ival < 0) + { + schar = '-'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Plus) + { + schar = '+'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Space) + { + schar = ' '; + ++vlen; + } + else + { + schar = 0; + } + } + } + dschar = false; + /* Do the ZERO pad. */ + if (flags_used & kPRINTF_Zero) + { + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + } + } + /* The string was built in reverse order, now display in correct order. */ + if ((!dschar) && schar) + { + cb(buf, &count, schar, 1); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + +#if PRINTF_FLOAT_ENABLE + if ((c == 'f') || (c == 'F')) + { + fval = (double)va_arg(ap, double); + vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + if (fval < 0) + { + schar = '-'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Plus) + { + schar = '+'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Space) + { + schar = ' '; + ++vlen; + } + else + { + schar = 0; + } + } + } + dschar = false; + if (flags_used & kPRINTF_Zero) + { + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + } + } + if ((!dschar) && schar) + { + cb(buf, &count, schar, 1); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#endif /* PRINTF_FLOAT_ENABLE */ + if ((c == 'X') || (c == 'x')) + { + if (c == 'x') + { + use_caps = false; + } +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + dschar = false; + if (flags_used & kPRINTF_Zero) + { + if (flags_used & kPRINTF_Pound) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + dschar = true; + } + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + if (flags_used & kPRINTF_Pound) + { + vlen += 2; + } + cb(buf, &count, ' ', field_width - vlen); + if (flags_used & kPRINTF_Pound) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + dschar = true; + } + } + } + + if ((flags_used & kPRINTF_Pound) && (!dschar)) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + vlen += 2; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) + { +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + + if (c == 'o') + { + radix = 8; + } + else if (c == 'b') + { + radix = 2; + } + else if (c == 'p') + { + radix = 16; + } + else + { + radix = 10; + } + + vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Zero) + { + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if !PRINTF_ADVANCED_ENABLE + cb(buf, &count, ' ', field_width - vlen); +#endif /* !PRINTF_ADVANCED_ENABLE */ + if (vstrp != NULL) + { + while (*vstrp) + { + cb(buf, &count, *vstrp--, 1); + } + } +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Minus) + { + cb(buf, &count, ' ', field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + else if (c == 'c') + { + cval = (char)va_arg(ap, uint32_t); + cb(buf, &count, cval, 1); + } + else if (c == 's') + { + sval = (char *)va_arg(ap, char *); + if (sval) + { +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + vlen = precision_width; + } + else + { + vlen = strlen(sval); + } +#else + vlen = strlen(sval); +#endif /* PRINTF_ADVANCED_ENABLE */ +#if PRINTF_ADVANCED_ENABLE + if (!(flags_used & kPRINTF_Minus)) +#endif /* PRINTF_ADVANCED_ENABLE */ + { + cb(buf, &count, ' ', field_width - vlen); + } + +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + while ((*sval) && (vlen > 0)) + { + cb(buf, &count, *sval++, 1); + vlen--; + } + /* In case that vlen sval is shorter than vlen */ + vlen = precision_width - vlen; + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + while (*sval) + { + cb(buf, &count, *sval++, 1); + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Minus) + { + cb(buf, &count, ' ', field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + } + else + { + cb(buf, &count, c, 1); + } + } + } + + return count; +} + +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) +{ + uint8_t base; + int8_t neg; + /* Identifier for the format string. */ + char *c = format; + char temp; + char *buf; + /* Flag telling the conversion specification. */ + uint32_t flag = 0; + /* Filed width for the matching input streams. */ + uint32_t field_width; + /* How many arguments are assigned except the suppress. */ + uint32_t nassigned = 0; + /* How many characters are read from the input streams. */ + uint32_t n_decode = 0; + + int32_t val; + + const char *s; + /* Identifier for the input string. */ + const char *p = line_ptr; + + /* Return EOF error before any conversion. */ + if (*p == '\0') + { + return -1; + } + + /* Decode directives. */ + while ((*c) && (*p)) + { + /* Ignore all white-spaces in the format strings. */ + if (ScanIgnoreWhiteSpace((const char **)&c)) + { + n_decode += ScanIgnoreWhiteSpace(&p); + } + else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%'))) + { + /* Ordinary characters. */ + c++; + if (*p == *c) + { + n_decode++; + p++; + c++; + } + else + { + /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. + * However, it is deserted now. */ + break; + } + } + else + { + /* convernsion specification */ + c++; + /* Reset. */ + flag = 0; + field_width = 0; + base = 0; + + /* Loop to get full conversion specification. */ + while ((*c) && (!(flag & kSCANF_DestMask))) + { + switch (*c) + { +#if SCANF_ADVANCED_ENABLE + case '*': + if (flag & kSCANF_Suppress) + { + /* Match failure. */ + return nassigned; + } + flag |= kSCANF_Suppress; + c++; + break; + case 'h': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + + if (c[1] == 'h') + { + flag |= kSCANF_LengthChar; + c++; + } + else + { + flag |= kSCANF_LengthShortInt; + } + c++; + break; + case 'l': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + + if (c[1] == 'l') + { + flag |= kSCANF_LengthLongLongInt; + c++; + } + else + { + flag |= kSCANF_LengthLongInt; + } + c++; + break; +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + case 'L': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + flag |= kSCANF_LengthLongLongDouble; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (field_width) + { + /* Match failure. */ + return nassigned; + } + do + { + field_width = field_width * 10 + *c - '0'; + c++; + } while ((*c >= '0') && (*c <= '9')); + break; + case 'd': + base = 10; + flag |= kSCANF_TypeSinged; + flag |= kSCANF_DestInt; + c++; + break; + case 'u': + base = 10; + flag |= kSCANF_DestInt; + c++; + break; + case 'o': + base = 8; + flag |= kSCANF_DestInt; + c++; + break; + case 'x': + case 'X': + base = 16; + flag |= kSCANF_DestInt; + c++; + break; + case 'i': + base = 0; + flag |= kSCANF_DestInt; + c++; + break; +#if SCANF_FLOAT_ENABLE + case 'a': + case 'A': + case 'e': + case 'E': + case 'f': + case 'F': + case 'g': + case 'G': + flag |= kSCANF_DestFloat; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case 'c': + flag |= kSCANF_DestChar; + if (!field_width) + { + field_width = 1; + } + c++; + break; + case 's': + flag |= kSCANF_DestString; + c++; + break; + default: + return nassigned; + } + } + + if (!(flag & kSCANF_DestMask)) + { + /* Format strings are exhausted. */ + return nassigned; + } + + if (!field_width) + { + /* Large than length of a line. */ + field_width = 99; + } + + /* Matching strings in input streams and assign to argument. */ + switch (flag & kSCANF_DestMask) + { + case kSCANF_DestChar: + s = (const char *)p; + buf = va_arg(args_ptr, char *); + while ((field_width--) && (*p)) + { + if (!(flag & kSCANF_Suppress)) + { + *buf++ = *p++; + } + else + { + p++; + } + n_decode++; + } + + if ((!(flag & kSCANF_Suppress)) && (s != p)) + { + nassigned++; + } + break; + case kSCANF_DestString: + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + buf = va_arg(args_ptr, char *); + while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') && + (*p != '\r') && (*p != '\v') && (*p != '\f')) + { + if (flag & kSCANF_Suppress) + { + p++; + } + else + { + *buf++ = *p++; + } + n_decode++; + } + + if ((!(flag & kSCANF_Suppress)) && (s != p)) + { + /* Add NULL to end of string. */ + *buf = '\0'; + nassigned++; + } + break; + case kSCANF_DestInt: + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + val = 0; + if ((base == 0) || (base == 16)) + { + if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) + { + base = 16; + if (field_width >= 1) + { + p += 2; + n_decode += 2; + field_width -= 2; + } + } + } + + if (base == 0) + { + if (s[0] == '0') + { + base = 8; + } + else + { + base = 10; + } + } + + neg = 1; + switch (*p) + { + case '-': + neg = -1; + n_decode++; + p++; + field_width--; + break; + case '+': + neg = 1; + n_decode++; + p++; + field_width--; + break; + default: + break; + } + + while ((*p) && (field_width--)) + { + if ((*p <= '9') && (*p >= '0')) + { + temp = *p - '0'; + } + else if ((*p <= 'f') && (*p >= 'a')) + { + temp = *p - 'a' + 10; + } + else if ((*p <= 'F') && (*p >= 'A')) + { + temp = *p - 'A' + 10; + } + else + { + temp = base; + } + + if (temp >= base) + { + break; + } + else + { + val = base * val + temp; + } + p++; + n_decode++; + } + val *= neg; + if (!(flag & kSCANF_Suppress)) + { +#if SCANF_ADVANCED_ENABLE + switch (flag & kSCANF_LengthMask) + { + case kSCANF_LengthChar: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed char *) = (signed char)val; + } + else + { + *va_arg(args_ptr, unsigned char *) = (unsigned char)val; + } + break; + case kSCANF_LengthShortInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed short *) = (signed short)val; + } + else + { + *va_arg(args_ptr, unsigned short *) = (unsigned short)val; + } + break; + case kSCANF_LengthLongInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed long int *) = (signed long int)val; + } + else + { + *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val; + } + break; + case kSCANF_LengthLongLongInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed long long int *) = (signed long long int)val; + } + else + { + *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val; + } + break; + default: + /* The default type is the type int. */ + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } + break; + } +#else + /* The default type is the type int. */ + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } +#endif /* SCANF_ADVANCED_ENABLE */ + nassigned++; + } + break; +#if SCANF_FLOAT_ENABLE + case kSCANF_DestFloat: + n_decode += ScanIgnoreWhiteSpace(&p); + fnum = strtod(p, (char **)&s); + + if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL)) + { + break; + } + + n_decode += (int)(s) - (int)(p); + p = s; + if (!(flag & kSCANF_Suppress)) + { + if (flag & kSCANF_LengthLongLongDouble) + { + *va_arg(args_ptr, double *) = fnum; + } + else + { + *va_arg(args_ptr, float *) = (float)fnum; + } + nassigned++; + } + break; +#endif /* SCANF_FLOAT_ENABLE */ + default: + return nassigned; + } + } + } + return nassigned; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.h new file mode 100644 index 00000000000..47d835edf9a --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/str/fsl_str.h @@ -0,0 +1,92 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _FSL_STR_H +#define _FSL_STR_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief A function pointer which is used when format printf log. + */ +typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len); + +/*! + * @brief This function outputs its parameters according to a formatted string. + * + * @note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * @param[in] fmt_ptr Format string for printf. + * @param[in] args_ptr Arguments to printf. + * @param[in] buf pointer to the buffer + * @param cb print callbck function pointer + * + * @return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb); + +/*! + * @brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * @param[in] line_ptr The input line of ASCII data. + * @param[in] format Format first points to the format string. + * @param[in] args_ptr The list of parameters. + * + * @return Number of input items converted and assigned. + * @retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_STR_H */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.c new file mode 100644 index 00000000000..f6692488484 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.c @@ -0,0 +1,42 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "usb_device_config.h" +#include "usb.h" +#include "usb_device.h" + +#if USB_DEVICE_CONFIG_CDC_ACM +#include "usb_device_cdc_acm.h" + +#endif diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.h new file mode 100644 index 00000000000..20f1faff861 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_cdc_acm.h @@ -0,0 +1,112 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_DEVICE_CDC_ACM_H_ +#define _USB_DEVICE_CDC_ACM_H_ 1 +/******************************************************************************* +* Definitions +******************************************************************************/ + +#define USB_DEVICE_CONFIG_CDC_ACM_MAX_INSTANCE (1) + +#define USB_DEVICE_CONFIG_CDC_COMM_CLASS_CODE (0x02) +#define USB_DEVICE_CONFIG_CDC_DATA_CLASS_CODE (0x0A) + +/* Class specific request Codes */ +#define USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND (0x00) +#define USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE (0x01) +#define USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE (0x02) +#define USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE (0x03) +#define USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE (0x04) +#define USB_DEVICE_CDC_REQUEST_SET_AUX_LINE_STATE (0x10) +#define USB_DEVICE_CDC_REQUEST_SET_HOOK_STATE (0x11) +#define USB_DEVICE_CDC_REQUEST_PULSE_SETUP (0x12) +#define USB_DEVICE_CDC_REQUEST_SEND_PULSE (0x13) +#define USB_DEVICE_CDC_REQUEST_SET_PULSE_TIME (0x14) +#define USB_DEVICE_CDC_REQUEST_RING_AUX_JACK (0x15) +#define USB_DEVICE_CDC_REQUEST_SET_LINE_CODING (0x20) +#define USB_DEVICE_CDC_REQUEST_GET_LINE_CODING (0x21) +#define USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE (0x22) +#define USB_DEVICE_CDC_REQUEST_SEND_BREAK (0x23) +#define USB_DEVICE_CDC_REQUEST_SET_RINGER_PARAMS (0x30) +#define USB_DEVICE_CDC_REQUEST_GET_RINGER_PARAMS (0x31) +#define USB_DEVICE_CDC_REQUEST_SET_OPERATION_PARAM (0x32) +#define USB_DEVICE_CDC_REQUEST_GET_OPERATION_PARAM (0x33) +#define USB_DEVICE_CDC_REQUEST_SET_LINE_PARAMS (0x34) +#define USB_DEVICE_CDC_REQUEST_GET_LINE_PARAMS (0x35) +#define USB_DEVICE_CDC_REQUEST_DIAL_DIGITS (0x36) +#define USB_DEVICE_CDC_REQUEST_SET_UNIT_PARAMETER (0x37) +#define USB_DEVICE_CDC_REQUEST_GET_UNIT_PARAMETER (0x38) +#define USB_DEVICE_CDC_REQUEST_CLEAR_UNIT_PARAMETER (0x39) +#define USB_DEVICE_CDC_REQUEST_GET_PROFILE (0x3A) +#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS (0x40) +#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_POW_PATTER_FILTER (0x41) +#define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_POW_PATTER_FILTER (0x42) +#define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_PACKET_FILTER (0x43) +#define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_STATISTIC (0x44) +#define USB_DEVICE_CDC_REQUEST_SET_ATM_DATA_FORMAT (0x50) +#define USB_DEVICE_CDC_REQUEST_GET_ATM_DEVICE_STATISTICS (0x51) +#define USB_DEVICE_CDC_REQUEST_SET_ATM_DEFAULT_VC (0x52) +#define USB_DEVICE_CDC_REQUEST_GET_ATM_VC_STATISTICS (0x53) +#define USB_DEVICE_CDC_REQUEST_MDLM_SPECIFIC_REQUESTS_MASK (0x7F) + +#define USB_DEVICE_CDC_REQUEST_GET_ABSTRACT_STATE (0x23) +#define USB_DEVICE_CDC_REQUEST_GET_COUNTRY_SETTING (0x24) +#define USB_DEVICE_CDC_REQUEST_SET_ABSTRACT_STATE (0x25) +#define USB_DEVICE_CDC_REQUEST_SET_COUNTRY_SETTING (0x26) +/* Class Specific Notification Codes */ +#define USB_DEVICE_CDC_REQUEST_NETWORK_CONNECTION_NOTIF (0x00) +#define USB_DEVICE_CDC_REQUEST_RESPONSE_AVAIL_NOTIF (0x01) +#define USB_DEVICE_CDC_REQUEST_AUX_JACK_HOOK_STATE_NOTIF (0x08) +#define USB_DEVICE_CDC_REQUEST_RING_DETECT_NOTIF (0x09) +#define USB_DEVICE_CDC_REQUEST_SERIAL_STATE_NOTIF (0x20) +#define USB_DEVICE_CDC_REQUEST_CALL_STATE_CHANGE_NOTIF (0x28) +#define USB_DEVICE_CDC_REQUEST_LINE_STATE_CHANGE_NOTIF (0x29) +#define USB_DEVICE_CDC_REQUEST_CONNECTION_SPEED_CHANGE_NOTIF (0x2A) +/* Communications Feature Selector Codes */ +#define USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE (0x01) +#define USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING (0x02) +/* Control Signal Bitmap Values */ +#define USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION (0x02) +#define USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE (0x01) +/* UART State Bitmap Values */ +#define USB_DEVICE_CDC_UART_STATE_RX_CARRIER (0x01) +#define USB_DEVICE_CDC_UART_STATE_TX_CARRIER (0x02) +#define USB_DEVICE_CDC_UART_STATE_BREAK (0x04) +#define USB_DEVICE_CDC_UART_STATE_RING_SIGNAL (0x08) +#define USB_DEVICE_CDC_UART_STATE_FRAMING (0x10) +#define USB_DEVICE_CDC_UART_STATE_PARITY (0x20) +#define USB_DEVICE_CDC_UART_STATE_OVERRUN (0x40) + +#endif /* _USB_DEVICE_CDC_ACM_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.c new file mode 100644 index 00000000000..b8ee92b9e80 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.c @@ -0,0 +1,947 @@ +/* + * The Clear BSD License + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "usb_device_config.h" +#include "usb.h" + +#include "usb_device.h" +#include "usb_device_dci.h" +#include "usb_device_ch9.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Standard request callback function typedef. + * + * This function is used to handle the standard request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_standard_request_callback_t)(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); + +/******************************************************************************* +* Prototypes +******************************************************************************/ +/*! + * @brief Get the setup packet buffer. + * + * The function is used to get the setup packet buffer to save the setup packet data. + * + * @param handle The device handle. + * @param setupBuffer It is an OUT parameter, return the setup buffer address to the caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceGetSetupBuffer(usb_device_handle handle, usb_setup_struct_t **setupBuffer); + +/*! + * @brief Handle the class request. + * + * The function is used to handle the class request. + * + * @param handle The device handle. + * @param setup The setup packet buffer address. + * @param length It is an OUT parameter, return the data length need to be sent to host. + * @param buffer It is an OUT parameter, return the data buffer address. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceProcessClassRequest(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer); + +/*! + * @brief Get the buffer to save the class specific data sent from host. + * + * The function is used to get the buffer to save the class specific data sent from host. + * The function will be called when the device receives a setup pakcet, and the host needs to send data to the device in + * the data stage. + * + * @param handle The device handle. + * @param setup The setup packet buffer address. + * @param length Pass the length the host needs to sent. + * @param buffer It is an OUT parameter, return the data buffer address to save the host's data. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceGetClassReceiveBuffer(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer); + +/* standard request */ +/*! + * @brief Get the descritpor. + * + * The function is used to get the descritpor, including the device descritpor, configuration descriptor, and string + * descriptor, etc. + * + * @param handle The device handle. + * @param setup The setup packet buffer address. + * @param length It is an OUT parameter, return the data length need to be sent to host. + * @param buffer It is an OUT parameter, return the data buffer address. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceGetDescriptor(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer); + +/*! + * @brief Set the device configuration. + * + * The function is used to set the device configuration. + * + * @param handle The device handle. + * @param configure The configuration value. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceSetConfigure(usb_device_handle handle, uint8_t configure); + +/*! + * @brief Get the device configuration. + * + * The function is used to get the device configuration. + * + * @param handle The device handle. + * @param configure It is an OUT parameter, save the current configuration value. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceGetConfigure(usb_device_handle handle, uint8_t *configure); + +/*! + * @brief Set an interface alternate setting. + * + * The function is used to set an interface alternate setting. + * + * @param handle The device handle. + * @param interface The interface index. + * @param alternateSetting The new alternate setting value. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceSetInterface(usb_device_handle handle, uint8_t interface, uint8_t alternateSetting); + +/*! + * @brief Get an interface alternate setting. + * + * The function is used to get an interface alternate setting. + * + * @param handle The device handle. + * @param interface The interface index. + * @param alternateSetting It is an OUT parameter, save the new alternate setting value of the interface. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceGetInterface(usb_device_handle handle, uint8_t interface, uint8_t *alternateSetting); + +/*! + * @brief Configure a specified endpoint status. + * + * The function is used to configure a specified endpoint status, idle or halt. + * + * @param handle The device handle. + * @param endpointAddress The endpoint address, the BIT7 is the direction, 0 - USB_OUT, 1 - USB_IN. + * @param status The new status of the endpoint, 0 - idle, 1 - halt. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceConfigureEndpointStatus(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t status); + +/*! + * @brief Configure the device remote wakeup feature. + * + * The function is used to configure the device remote wakeup feature, enable or disbale the remote wakeup feature. + * + * @param handle The device handle. + * @param enable The new feature value of the device remote wakeup, 0 - disable, 1 - enable. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceConfigureRemoteWakeup(usb_device_handle handle, uint8_t enable); + +static usb_status_t USB_DeviceCh9GetStatus(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9SetClearFeature(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9SetAddress(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9GetDescriptor(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9GetConfiguration(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9SetConfiguration(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9GetInterface(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9SetInterface(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); +static usb_status_t USB_DeviceCh9SynchFrame(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* The function list to handle the standard request. */ +static const usb_standard_request_callback_t s_UsbDeviceStandardRequest[] = { + USB_DeviceCh9GetStatus, + USB_DeviceCh9SetClearFeature, + (usb_standard_request_callback_t)NULL, + USB_DeviceCh9SetClearFeature, + (usb_standard_request_callback_t)NULL, + USB_DeviceCh9SetAddress, + USB_DeviceCh9GetDescriptor, + (usb_standard_request_callback_t)NULL, /* USB_DeviceCh9SetDescriptor */ + USB_DeviceCh9GetConfiguration, + USB_DeviceCh9SetConfiguration, + USB_DeviceCh9GetInterface, + USB_DeviceCh9SetInterface, + USB_DeviceCh9SynchFrame, +}; + +/* + * The internal global variable. + * This variable is used in: + * get status request + * get configuration request + * get interface request + * set interface request + * get sync frame request + */ +static uint16_t s_UsbDeviceStandardRx; + +/******************************************************************************* +* Code +******************************************************************************/ +/*! + * @brief Handle get status request. + * + * This function is used to handle get status request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9GetStatus(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state)) + { + return error; + } + + if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE) + { + /* Get the device status */ + error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusDevice, &s_UsbDeviceStandardRx); + s_UsbDeviceStandardRx = s_UsbDeviceStandardRx & USB_GET_STATUS_DEVICE_MASK; + s_UsbDeviceStandardRx = USB_SHORT_TO_LITTLE_ENDIAN(s_UsbDeviceStandardRx); + /* The device status length must be USB_DEVICE_STATUS_SIZE. */ + *length = USB_DEVICE_STATUS_SIZE; + } + else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_INTERFACE) + { + /* Get the interface status */ + error = kStatus_USB_Success; + s_UsbDeviceStandardRx = 0U; + /* The interface status length must be USB_INTERFACE_STATUS_SIZE. */ + *length = USB_INTERFACE_STATUS_SIZE; + } + else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) + { + /* Get the endpoint status */ + usb_device_endpoint_status_struct_t endpointStatus; + endpointStatus.endpointAddress = (uint8_t)setup->wIndex; + endpointStatus.endpointStatus = kUSB_DeviceEndpointStateIdle; + error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusEndpoint, &endpointStatus); + s_UsbDeviceStandardRx = endpointStatus.endpointStatus & USB_GET_STATUS_ENDPOINT_MASK; + s_UsbDeviceStandardRx = USB_SHORT_TO_LITTLE_ENDIAN(s_UsbDeviceStandardRx); + /* The endpoint status length must be USB_INTERFACE_STATUS_SIZE. */ + *length = USB_ENDPOINT_STATUS_SIZE; + } + else + { + } + *buffer = (uint8_t *)&s_UsbDeviceStandardRx; + + return error; +} + +/*! + * @brief Handle set or clear device feature request. + * + * This function is used to handle set or clear device feature request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9SetClearFeature(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + uint8_t isSet = 0U; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state)) + { + return error; + } + + /* Identify the request is set or clear the feature. */ + if (USB_REQUEST_STANDARD_SET_FEATURE == setup->bRequest) + { + isSet = 1U; + } + + if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_DEVICE) + { + /* Set or Clear the device featrue. */ + if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP == setup->wValue) + { + /* Set or Clear the device remote wakeup featrue. */ + error = USB_DeviceConfigureRemoteWakeup(handle, isSet); + } +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) && \ + (defined(USB_DEVICE_CONFIG_EHCI_TEST_MODE) && (USB_DEVICE_CONFIG_EHCI_TEST_MODE > 0U)) + else if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE == setup->wValue) + { + state = kUSB_DeviceStateTestMode; + error = USB_DeviceSetStatus(classHandle->handle, kUSB_DeviceStatusDeviceState, &state); + } +#endif + else + { + } + } + else if ((setup->bmRequestType & USB_REQUEST_TYPE_RECIPIENT_MASK) == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) + { + /* Set or Clear the endpoint featrue. */ + if (USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT == setup->wValue) + { + if (USB_CONTROL_ENDPOINT == (setup->wIndex & USB_ENDPOINT_NUMBER_MASK)) + { + /* Set or Clear the control endpoint status(halt or not). */ + if (isSet) + { + USB_DeviceStallEndpoint(handle, (uint8_t)setup->wIndex); + } + else + { + USB_DeviceUnstallEndpoint(handle, (uint8_t)setup->wIndex); + } + } + + /* Set or Clear the endpoint status featrue. */ + error = USB_DeviceConfigureEndpointStatus(handle, setup->wIndex, isSet); + } + else + { + } + } + else + { + } + + return error; +} + +/*! + * @brief Handle set address request. + * + * This function is used to handle set address request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state. + */ +static usb_status_t USB_DeviceCh9SetAddress(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddressing != state) && (kUSB_DeviceStateAddress != state) && + (kUSB_DeviceStateDefault != state)) + { + return error; + } + + if (kUSB_DeviceStateAddressing != state) + { + /* If the device address is not setting, pass the address and the device state will change to + * kUSB_DeviceStateAddressing internally. */ + state = setup->wValue & 0xFFU; + error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, &state); + } + else + { + /* If the device address is setting, set device address and the address will be write into the controller + * internally. */ + error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL); + /* And then change the device state to kUSB_DeviceStateAddress. */ + if (kStatus_USB_Success == error) + { + state = kUSB_DeviceStateAddress; + error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + } + } + + return error; +} + +/*! + * @brief Handle get descriptor request. + * + * This function is used to handle get descriptor request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9GetDescriptor(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state) && + (kUSB_DeviceStateDefault != state)) + { + return kStatus_USB_InvalidRequest; + } + + return USB_DeviceGetDescriptor(handle, setup, length, buffer); +} + +/*! + * @brief Handle get current configuration request. + * + * This function is used to handle get current configuration request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9GetConfiguration(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddress != state) && ((kUSB_DeviceStateConfigured != state))) + { + return kStatus_USB_InvalidRequest; + } + + *length = USB_CONFIGURE_SIZE; + *buffer = (uint8_t *)&s_UsbDeviceStandardRx; + return USB_DeviceGetConfigure(handle, (uint8_t *)&s_UsbDeviceStandardRx); +} + +/*! + * @brief Handle set current configuration request. + * + * This function is used to handle set current configuration request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9SetConfiguration(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if ((kUSB_DeviceStateAddress != state) && (kUSB_DeviceStateConfigured != state)) + { + return kStatus_USB_InvalidRequest; + } + + /* The device state is changed to kUSB_DeviceStateConfigured */ + state = kUSB_DeviceStateConfigured; + USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + if (!setup->wValue) + { + /* If the new configuration is zero, the device state is changed to kUSB_DeviceStateAddress */ + state = kUSB_DeviceStateAddress; + USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + } + + return USB_DeviceSetConfigure(handle, setup->wValue); +} + +/*! + * @brief Handle get the alternate setting of a interface request. + * + * This function is used to handle get the alternate setting of a interface request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9GetInterface(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if (state != kUSB_DeviceStateConfigured) + { + return error; + } + *length = USB_INTERFACE_SIZE; + *buffer = (uint8_t *)&s_UsbDeviceStandardRx; + + return USB_DeviceGetInterface(handle, setup->wIndex & 0xFFU, (uint8_t *)&s_UsbDeviceStandardRx); +} + +/*! + * @brief Handle set the alternate setting of a interface request. + * + * This function is used to handle set the alternate setting of a interface request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9SetInterface(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if (state != kUSB_DeviceStateConfigured) + { + return kStatus_USB_InvalidRequest; + } + + return USB_DeviceSetInterface(handle, (setup->wIndex & 0xFFU), (setup->wValue & 0xFFU)); +} + +/*! + * @brief Handle get sync frame request. + * + * This function is used to handle get sync frame request. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @retval kStatus_USB_Success The requst is handled successfully. + * @retval kStatus_USB_InvalidRequest The request can not be handle in current device state, + * or, the request is unsupported. + */ +static usb_status_t USB_DeviceCh9SynchFrame(usb_device_handle handle, + usb_setup_struct_t *setup, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if (state != kUSB_DeviceStateConfigured) + { + return error; + } + + s_UsbDeviceStandardRx = setup->wIndex; + /* Get the sync frame value */ + error = USB_DeviceGetStatus(handle, kUSB_DeviceStatusSynchFrame, &s_UsbDeviceStandardRx); + *buffer = (uint8_t *)&s_UsbDeviceStandardRx; + *length = sizeof(s_UsbDeviceStandardRx); + + return error; +} + +/*! + * @brief Send the reponse to the host. + * + * This function is used to send the reponse to the host. + * + * There are two cases this function will be called. + * Case one when a setup packet is received in control endpoint callback function: + * 1. If there is not data phase in the setup transfer, the function will prime an IN transfer with the data + * length is zero for status phase. + * 2. If there is an IN data phase, the function will prime an OUT transfer with the actual length to need to + * send for data phase. And then prime an IN transfer with the data length is zero for status phase. + * 3. If there is an OUT data phase, the function will prime an IN transfer with the actual length to want to + * receive for data phase. + * + * Case two when is not a setup packet received in control endpoint callback function: + * 1. The function will prime an IN transfer with data length is zero for status phase. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param setup The pointer of the setup packet. + * @param error The error code returned from the standard request fucntion. + * @param stage The stage of the control transfer. + * @param buffer It is an out parameter, is used to save the buffer address to response the host's request. + * @param length It is an out parameter, the data length. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceControlCallbackFeedback(usb_device_handle handle, + usb_setup_struct_t *setup, + usb_status_t error, + usb_device_control_read_write_sequence_t stage, + uint8_t **buffer, + uint32_t *length) +{ + usb_status_t errorCode = kStatus_USB_Error; + uint8_t direction = USB_IN; + + if (kStatus_USB_InvalidRequest == error) + { + /* Stall the control pipe when the request is unsupported. */ + if ((!((setup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_STANDARD)) && + ((setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT) && (setup->wLength) && + (kUSB_DeviceControlPipeSetupStage == stage)) + { + direction = USB_OUT; + } + errorCode = USB_DeviceStallEndpoint( + handle, + (USB_CONTROL_ENDPOINT) | (uint8_t)((uint32_t)direction << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); + } + else + { + if (*length > setup->wLength) + { + *length = setup->wLength; + } + errorCode = USB_DeviceSendRequest(handle, (USB_CONTROL_ENDPOINT), *buffer, *length); + + if ((kStatus_USB_Success == errorCode) && + (USB_REQUEST_TYPE_DIR_IN == (setup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK))) + { + errorCode = USB_DeviceRecvRequest(handle, (USB_CONTROL_ENDPOINT), (uint8_t *)NULL, 0U); + } + } + return errorCode; +} + +/*! + * @brief Control endpoint callback function. + * + * This callback function is used to notify uplayer the tranfser result of a transfer. + * This callback pointer is passed when a sepcified endpoint initialied by calling API USB_DeviceInitEndpoint. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The result of a transfer, includes transfer buffer, transfer length and whether is in setup + * phase for control pipe. + * @param callbackParam The paramter for this callback. It is same with + * usb_device_endpoint_callback_struct_t::callbackParam. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceControlCallback(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam) +{ + usb_setup_struct_t *deviceSetup; + uint8_t *setupOutBuffer; + uint8_t *buffer = (uint8_t *)NULL; + uint32_t length = 0U; + usb_status_t error = kStatus_USB_InvalidRequest; + uint8_t state; + + if (USB_UNINITIALIZED_VAL_32 == message->length) + { + return error; + } + + USB_DeviceGetSetupBuffer(handle, &deviceSetup); + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + + if (message->isSetup) + { + if ((USB_SETUP_PACKET_SIZE != message->length) || (NULL == message->buffer)) + { + /* If a invalid setup is received, the control pipes should be de-init and init again. + * Due to the IP can not meet this require, it is revesed for feature. + */ + /* + USB_DeviceDeinitEndpoint(handle, + USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); + USB_DeviceDeinitEndpoint(handle, + USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); + USB_DeviceControlPipeInit(handle); + */ + return error; + } + /* Receive a setup request */ + usb_setup_struct_t *setup = (usb_setup_struct_t *)(message->buffer); + /* Copy the setup packet to the application buffer */ + deviceSetup->wValue = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wValue); + deviceSetup->wIndex = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wIndex); + deviceSetup->wLength = USB_SHORT_FROM_LITTLE_ENDIAN(setup->wLength); + deviceSetup->bRequest = setup->bRequest; + deviceSetup->bmRequestType = setup->bmRequestType; + + if ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_MASK) == USB_REQUEST_TYPE_TYPE_STANDARD) + { + /* Handle the standard request */ + if (s_UsbDeviceStandardRequest[deviceSetup->bRequest] != (usb_standard_request_callback_t)NULL) + { + error = s_UsbDeviceStandardRequest[deviceSetup->bRequest](handle, deviceSetup, &buffer, &length); + } + } + else + { + if ((deviceSetup->wLength) && + ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT)) + { + /* Class or vendor request with the OUT data phase. */ + if ((deviceSetup->wLength) && + ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS)) + { + /* Get data buffer to receive the data from the host. */ + length = deviceSetup->wLength; + error = USB_DeviceGetClassReceiveBuffer(handle, deviceSetup, &length, &setupOutBuffer); + length = 0U; + } + else + { + } + if (kStatus_USB_Success == error) + { + /* Prime an OUT transfer */ + error = USB_DeviceRecvRequest(handle, USB_CONTROL_ENDPOINT, setupOutBuffer, deviceSetup->wLength); + return error; + } + } + else + { + /* Class or vendor request with the IN data phase. */ + if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS)) + { + /* Get data buffer to response the host. */ + error = USB_DeviceProcessClassRequest(handle, deviceSetup, &length, &buffer); + } + else + { + } + } + } + /* Send the reponse to the host. */ + error = USB_DeviceControlCallbackFeedback(handle, deviceSetup, error, kUSB_DeviceControlPipeSetupStage, &buffer, + &length); + } + else if (kUSB_DeviceStateAddressing == state) + { + /* Set the device address to controller. */ + error = s_UsbDeviceStandardRequest[deviceSetup->bRequest](handle, deviceSetup, &buffer, &length); + } +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)) && \ + (defined(USB_DEVICE_CONFIG_EHCI_TEST_MODE) && (USB_DEVICE_CONFIG_EHCI_TEST_MODE > 0U)) + else if (kUSB_DeviceStateTestMode == state) + { + uint8_t portTestControl = (uint8_t)(deviceSetup->wIndex >> 8); + /* Set the controller.into test mode. */ + error = USB_DeviceSetStatus(handle, kUSB_DeviceStatusTestMode, &portTestControl); + } +#endif + else if ((message->length) && (deviceSetup->wLength) && + ((deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_OUT)) + { + if (((deviceSetup->bmRequestType & USB_REQUEST_TYPE_TYPE_CLASS) == USB_REQUEST_TYPE_TYPE_CLASS)) + { + /* Data received in OUT phase, and notify the class driver. */ + error = USB_DeviceProcessClassRequest(handle, deviceSetup, &message->length, &message->buffer); + } + else + { + } + /* Send the reponse to the host. */ + error = USB_DeviceControlCallbackFeedback(handle, deviceSetup, error, kUSB_DeviceControlPipeDataStage, &buffer, + &length); + } + else + { + } + return error; +} + +/*! + * @brief Control endpoint initialization function. + * + * This callback function is used to initialize the control pipes. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param param The up layer handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceControlPipeInit(usb_device_handle handle) +{ + usb_device_endpoint_init_struct_t epInitStruct; + usb_device_endpoint_callback_struct_t endpointCallback; + usb_status_t error; + + endpointCallback.callbackFn = USB_DeviceControlCallback; + endpointCallback.callbackParam = handle; + + epInitStruct.zlt = 1U; + epInitStruct.transferType = USB_ENDPOINT_CONTROL; + epInitStruct.endpointAddress = USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + epInitStruct.maxPacketSize = USB_CONTROL_MAX_PACKET_SIZE; + /* Initialize the control IN pipe */ + error = USB_DeviceInitEndpoint(handle, &epInitStruct, &endpointCallback); + + if (kStatus_USB_Success != error) + { + return error; + } + epInitStruct.endpointAddress = USB_CONTROL_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + /* Initialize the control OUT pipe */ + error = USB_DeviceInitEndpoint(handle, &epInitStruct, &endpointCallback); + + if (kStatus_USB_Success != error) + { + USB_DeviceDeinitEndpoint(handle, + USB_CONTROL_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)); + return error; + } + + return kStatus_USB_Success; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.h new file mode 100644 index 00000000000..0d964c800f4 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_ch9.h @@ -0,0 +1,112 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_DEVICE_CH9_H__ +#define __USB_DEVICE_CH9_H__ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! + * @addtogroup usb_device_ch9 + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines USB device status size when the host request to get device status */ +#define USB_DEVICE_STATUS_SIZE (0x02U) + +/*! @brief Defines USB device interface status size when the host request to get interface status */ +#define USB_INTERFACE_STATUS_SIZE (0x02U) + +/*! @brief Defines USB device endpoint status size when the host request to get endpoint status */ +#define USB_ENDPOINT_STATUS_SIZE (0x02U) + +/*! @brief Defines USB device configuration size when the host request to get current configuration */ +#define USB_CONFIGURE_SIZE (0X01U) + +/*! @brief Defines USB device interface alternate setting size when the host request to get interface alternate setting + */ +#define USB_INTERFACE_SIZE (0X01U) + +/*! @brief Defines USB device status mask */ +#define USB_GET_STATUS_DEVICE_MASK (0x03U) + +/*! @brief Defines USB device interface status mask */ +#define USB_GET_STATUS_INTERFACE_MASK (0x03U) + +/*! @brief Defines USB device endpoint status mask */ +#define USB_GET_STATUS_ENDPOINT_MASK (0x03U) + +/*! @brief Control read and write sequence */ +typedef enum _usb_device_control_read_write_sequence +{ + kUSB_DeviceControlPipeSetupStage = 0U, /*!< Setup stage */ + kUSB_DeviceControlPipeDataStage, /*!< Data stage */ + kUSB_DeviceControlPipeStatusStage, /*!< status stage */ +} usb_device_control_read_write_sequence_t; + +/******************************************************************************* +* API +******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initialize the control pipes. + * + * The function is used to initialize the control pipes. This function should be called when event + * kUSB_DeviceEventBusReset is received. + * + * @param handle The device handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceControlPipeInit(usb_device_handle handle); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __USB_DEVICE_CH9_H__ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_config.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_config.h new file mode 100644 index 00000000000..b9a5620e9bd --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_config.h @@ -0,0 +1,183 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 - 2018 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_DEVICE_CONFIG_H_ +#define _USB_DEVICE_CONFIG_H_ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! + * @name Hardware instance define + * @{ + */ + +/*! @brief KHCI instance count */ +#define USB_DEVICE_CONFIG_KHCI (0U) + +/*! @brief EHCI instance count */ +#define USB_DEVICE_CONFIG_EHCI (0U) + +/*! @brief LPC USB IP3511 FS instance count */ +#define USB_DEVICE_CONFIG_LPCIP3511FS (1U) + +/*! @brief LPC USB IP3511 HS instance count */ +#define USB_DEVICE_CONFIG_LPCIP3511HS (0U) + +/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/ +#define USB_DEVICE_CONFIG_NUM \ + (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI + USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) + +/* @} */ + +/*! + * @addtogroup usb_device_configuration + * @{ + */ + +/*! + * @name class instance define + * @{ + */ + +/*! @brief HID instance count */ +#define USB_DEVICE_CONFIG_HID (0U) + +/*! @brief CDC ACM instance count */ +#define USB_DEVICE_CONFIG_CDC_ACM (1U) + +/*! @brief MSC instance count */ +#define USB_DEVICE_CONFIG_MSC (0U) + +/*! @brief Audio instance count */ +#define USB_DEVICE_CONFIG_AUDIO (0U) + +/*! @brief PHDC instance count */ +#define USB_DEVICE_CONFIG_PHDC (0U) + +/*! @brief Video instance count */ +#define USB_DEVICE_CONFIG_VIDEO (0U) + +/*! @brief CCID instance count */ +#define USB_DEVICE_CONFIG_CCID (0U) + +/*! @brief Printer instance count */ +#define USB_DEVICE_CONFIG_PRINTER (0U) + +/*! @brief DFU instance count */ +#define USB_DEVICE_CONFIG_DFU (0U) + +/* @} */ + +/*! @brief Whether device is self power. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_SELF_POWER (1U) + +/*! @brief How many endpoints are supported in the stack. */ +#define USB_DEVICE_CONFIG_ENDPOINTS (4U) + +/*! @brief Whether the device task is enabled. */ +#define USB_DEVICE_CONFIG_USE_TASK (0U) + +/*! @brief How many the notification message are supported when the device task is enabled. */ +#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U) + +/*! @brief Whether test mode enabled. */ +#define USB_DEVICE_CONFIG_USB20_TEST_MODE (0U) + +/*! @brief Whether device CV test is enabled. */ +#define USB_DEVICE_CONFIG_CV_TEST (0U) + +/*! @brief Whether device compliance test is enabled. If the macro is enabled, + the test mode and CV test macroes will be set.*/ +#define USB_DEVICE_CONFIG_COMPLIANCE_TEST (0U) + +#if ((defined(USB_DEVICE_CONFIG_COMPLIANCE_TEST)) && (USB_DEVICE_CONFIG_COMPLIANCE_TEST > 0U)) + +/*! @brief Undefine the marco USB_DEVICE_CONFIG_USB20_TEST_MODE. */ +#undef USB_DEVICE_CONFIG_USB20_TEST_MODE +/*! @brief Undefine the marco USB_DEVICE_CONFIG_CV_TEST. */ +#undef USB_DEVICE_CONFIG_CV_TEST + +/*! @brief enable the test mode. */ +#define USB_DEVICE_CONFIG_USB20_TEST_MODE (1U) + +/*! @brief enable the CV test */ +#define USB_DEVICE_CONFIG_CV_TEST (1U) + +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) + +/*! @brief The MAX buffer length for the KHCI DMA workaround.*/ +#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U) +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! @brief How many the DTD are supported. */ +#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U) + +/*! @brief Whether the EHCI ID pin detect feature enabled. */ +#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U) +#endif + +/*! @brief Whether the keep alive feature enabled. */ +#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U) + +/*! @brief Whether the transfer buffer is cache-enabled or not. */ +#ifndef USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE +#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U) +#endif +/*! @brief Whether the low power mode is enabled or not. */ +#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U) + +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! @brief Whether device remote wakeup supported. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) + +/*! @brief Whether LPM is supported. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_LPM_L1 (0U) +#else +/*! @brief The device remote wakeup is unsupported. */ +#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) +#endif + +/*! @brief Whether the device detached feature is enabled or not. */ +#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U) + +/*! @brief Whether handle the USB bus error. */ +#define USB_DEVICE_CONFIG_ERROR_HANDLING (0U) + +/* @} */ + +#endif /* _USB_DEVICE_CONFIG_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.c new file mode 100644 index 00000000000..8271e58a8ba --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.c @@ -0,0 +1,482 @@ +/* + * The Clear BSD License + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "usb_device_config.h" +#include "usb.h" +#include "usb_device.h" + +#include "usb_device_cdc_acm.h" + +#include "usb_device_descriptor.h" + +/******************************************************************************* +* Variables +******************************************************************************/ +uint8_t g_currentConfigure = 0; +uint8_t g_interface[USB_CDC_VCOM_INTERFACE_COUNT]; + +/* Define device descriptor */ +uint8_t g_UsbDeviceDescriptor[USB_DESCRIPTOR_LENGTH_DEVICE] = { + /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_LENGTH_DEVICE, + /* DEVICE Descriptor Type */ + USB_DESCRIPTOR_TYPE_DEVICE, + /* USB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). */ + USB_SHORT_GET_LOW(USB_DEVICE_SPECIFIC_BCD_VERSION), USB_SHORT_GET_HIGH(USB_DEVICE_SPECIFIC_BCD_VERSION), + /* Class code (assigned by the USB-IF). */ + USB_DEVICE_CLASS, + /* Subclass code (assigned by the USB-IF). */ + USB_DEVICE_SUBCLASS, + /* Protocol code (assigned by the USB-IF). */ + USB_DEVICE_PROTOCOL, + /* Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid) */ + USB_CONTROL_MAX_PACKET_SIZE, + /* Vendor ID (assigned by the USB-IF) */ + 0xC9U, 0x1FU, + /* Product ID (assigned by the manufacturer) */ + 0x94, 0x00, + /* Device release number in binary-coded decimal */ + USB_SHORT_GET_LOW(USB_DEVICE_DEMO_BCD_VERSION), USB_SHORT_GET_HIGH(USB_DEVICE_DEMO_BCD_VERSION), + /* Index of string descriptor describing manufacturer */ + 0x01, + /* Index of string descriptor describing product */ + 0x02, + /* Index of string descriptor describing the device's serial number */ + 0x00, + /* Number of possible configurations */ + USB_DEVICE_CONFIGURATION_COUNT, +}; + +/* Define configuration descriptor */ +uint8_t g_UsbDeviceConfigurationDescriptor[USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL] = { + /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_LENGTH_CONFIGURE, + /* CONFIGURATION Descriptor Type */ + USB_DESCRIPTOR_TYPE_CONFIGURE, + /* Total length of data returned for this configuration. */ + USB_SHORT_GET_LOW(USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL), + USB_SHORT_GET_HIGH(USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL), + /* Number of interfaces supported by this configuration */ + USB_CDC_VCOM_INTERFACE_COUNT, + /* Value to use as an argument to the SetConfiguration() request to select this configuration */ + USB_CDC_VCOM_CONFIGURE_INDEX, + /* Index of string descriptor describing this configuration */ + 0, + /* Configuration characteristics D7: Reserved (set to one) D6: Self-powered D5: Remote Wakeup D4...0: Reserved + (reset to zero) */ + (USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK) | + (USB_DEVICE_CONFIG_SELF_POWER << USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT) | + (USB_DEVICE_CONFIG_REMOTE_WAKEUP << USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT), + /* Maximum power consumption of the USB * device from the bus in this specific * configuration when the device is + fully * operational. Expressed in 2 mA units * (i.e., 50 = 100 mA). */ + USB_DEVICE_MAX_POWER, + + /* Communication Interface Descriptor */ + USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_COMM_INTERFACE_INDEX, 0x00, + USB_CDC_VCOM_ENDPOINT_CIC_COUNT, USB_CDC_VCOM_CIC_CLASS, USB_CDC_VCOM_CIC_SUBCLASS, USB_CDC_VCOM_CIC_PROTOCOL, + 0x00, /* Interface Description String Index*/ + + /* CDC Class-Specific descriptor */ + USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC, /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ + USB_CDC_HEADER_FUNC_DESC, 0x10, + 0x01, /* USB Class Definitions for Communications the Communication specification version 1.10 */ + + USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG, /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ + USB_CDC_CALL_MANAGEMENT_FUNC_DESC, + 0x01, /*Bit 0: Whether device handle call management itself 1, Bit 1: Whether device can send/receive call + management information over a Data Class Interface 0 */ + 0x01, /* Indicates multiplexed commands are handled via data interface */ + + USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT, /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ + USB_CDC_ABSTRACT_CONTROL_FUNC_DESC, + 0x06, /* Bit 0: Whether device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and + Get_Comm_Feature 0, Bit 1: Whether device supports the request combination of Set_Line_Coding, + Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State 1, Bit ... */ + + USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC, /* Size of this descriptor in bytes */ + USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE, /* CS_INTERFACE Descriptor Type */ + USB_CDC_UNION_FUNC_DESC, 0x00, /* The interface number of the Communications or Data Class interface */ + 0x01, /* Interface number of subordinate interface in the Union */ + + /*Notification Endpoint descriptor */ + USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT | (USB_IN << 7U), + USB_ENDPOINT_INTERRUPT, USB_SHORT_GET_LOW(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE), + USB_SHORT_GET_HIGH(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE), FS_CDC_VCOM_INTERRUPT_IN_INTERVAL, + + /* Data Interface Descriptor */ + USB_DESCRIPTOR_LENGTH_INTERFACE, USB_DESCRIPTOR_TYPE_INTERFACE, USB_CDC_VCOM_DATA_INTERFACE_INDEX, 0x00, + USB_CDC_VCOM_ENDPOINT_DIC_COUNT, USB_CDC_VCOM_DIC_CLASS, USB_CDC_VCOM_DIC_SUBCLASS, USB_CDC_VCOM_DIC_PROTOCOL, + 0x00, /* Interface Description String Index*/ + + /*Bulk IN Endpoint descriptor */ + USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_BULK_IN_ENDPOINT | (USB_IN << 7U), + USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_IN_PACKET_SIZE), + USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_IN_PACKET_SIZE), 0x00, /* The polling interval value is every 0 Frames */ + + /*Bulk OUT Endpoint descriptor */ + USB_DESCRIPTOR_LENGTH_ENDPOINT, USB_DESCRIPTOR_TYPE_ENDPOINT, USB_CDC_VCOM_BULK_OUT_ENDPOINT | (USB_OUT << 7U), + USB_ENDPOINT_BULK, USB_SHORT_GET_LOW(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE), + USB_SHORT_GET_HIGH(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE), 0x00, /* The polling interval value is every 0 Frames */ +}; + +/* Define string descriptor */ +uint8_t g_UsbDeviceString0[USB_DESCRIPTOR_LENGTH_STRING0] = {sizeof(g_UsbDeviceString0), USB_DESCRIPTOR_TYPE_STRING, + 0x09, 0x04}; + +uint8_t g_UsbDeviceString1[USB_DESCRIPTOR_LENGTH_STRING1] = { + sizeof(g_UsbDeviceString1), + USB_DESCRIPTOR_TYPE_STRING, + 'N', + 0x00U, + 'X', + 0x00U, + 'P', + 0x00U, + ' ', + 0x00U, + 'S', + 0x00U, + 'E', + 0x00U, + 'M', + 0x00U, + 'I', + 0x00U, + 'C', + 0x00U, + 'O', + 0x00U, + 'N', + 0x00U, + 'D', + 0x00U, + 'U', + 0x00U, + 'C', + 0x00U, + 'T', + 0x00U, + 'O', + 0x00U, + 'R', + 0x00U, + 'S', + 0x00U, +}; + +uint8_t g_UsbDeviceString2[USB_DESCRIPTOR_LENGTH_STRING2] = {sizeof(g_UsbDeviceString2), + USB_DESCRIPTOR_TYPE_STRING, + 'M', + 0, + 'C', + 0, + 'U', + 0, + ' ', + 0, + 'V', + 0, + 'I', + 0, + 'R', + 0, + 'T', + 0, + 'U', + 0, + 'A', + 0, + 'L', + 0, + ' ', + 0, + 'C', + 0, + 'O', + 0, + 'M', + 0, + ' ', + 0, + 'D', + 0, + 'E', + 0, + 'M', + 0, + 'O', + 0}; + +uint8_t *g_UsbDeviceStringDescriptorArray[USB_DEVICE_STRING_COUNT] = {g_UsbDeviceString0, g_UsbDeviceString1, + g_UsbDeviceString2}; + +/* Define string descriptor size */ +uint32_t g_UsbDeviceStringDescriptorLength[USB_DEVICE_STRING_COUNT] = { + sizeof(g_UsbDeviceString0), sizeof(g_UsbDeviceString1), sizeof(g_UsbDeviceString2)}; +usb_language_t g_UsbDeviceLanguage[USB_DEVICE_LANGUAGE_COUNT] = {{ + g_UsbDeviceStringDescriptorArray, g_UsbDeviceStringDescriptorLength, (uint16_t)0x0409, +}}; + +usb_language_list_t g_UsbDeviceLanguageList = { + g_UsbDeviceString0, sizeof(g_UsbDeviceString0), g_UsbDeviceLanguage, USB_DEVICE_LANGUAGE_COUNT, +}; + +/******************************************************************************* +* Code +******************************************************************************/ +/*! + * @brief Get the descritpor. + * + * The function is used to get the descritpor, including the device descritpor, configuration descriptor, and string + * descriptor, etc. + * + * @param handle The device handle. + * @param setup The setup packet buffer address. + * @param length It is an OUT parameter, return the data length need to be sent to host. + * @param buffer It is an OUT parameter, return the data buffer address. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetDescriptor(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer) +{ + uint8_t descriptorType = (uint8_t)((setup->wValue & 0xFF00U) >> 8U); + uint8_t descriptorIndex = (uint8_t)((setup->wValue & 0x00FFU)); + usb_status_t ret = kStatus_USB_Success; + if (USB_REQUEST_STANDARD_GET_DESCRIPTOR != setup->bRequest) + { + return kStatus_USB_InvalidRequest; + } + switch (descriptorType) + { + case USB_DESCRIPTOR_TYPE_STRING: + { + if (descriptorIndex == 0) + { + *buffer = (uint8_t *)g_UsbDeviceLanguageList.languageString; + *length = g_UsbDeviceLanguageList.stringLength; + } + else + { + uint8_t langId = 0; + uint8_t langIndex = USB_DEVICE_STRING_COUNT; + + for (; langId < USB_DEVICE_LANGUAGE_COUNT; langId++) + { + if (setup->wIndex == g_UsbDeviceLanguageList.languageList[langId].languageId) + { + if (descriptorIndex < USB_DEVICE_STRING_COUNT) + { + langIndex = descriptorIndex; + } + break; + } + } + + if (USB_DEVICE_STRING_COUNT == langIndex) + { + langId = 0; + } + *buffer = (uint8_t *)g_UsbDeviceLanguageList.languageList[langId].string[langIndex]; + *length = g_UsbDeviceLanguageList.languageList[langId].length[langIndex]; + } + } + break; + case USB_DESCRIPTOR_TYPE_DEVICE: + { + *buffer = g_UsbDeviceDescriptor; + *length = USB_DESCRIPTOR_LENGTH_DEVICE; + } + break; + case USB_DESCRIPTOR_TYPE_CONFIGURE: + { + *buffer = g_UsbDeviceConfigurationDescriptor; + *length = USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL; + } + break; + default: + ret = kStatus_USB_InvalidRequest; + break; + } /* End Switch */ + return ret; +} + +/*! + * @brief Set the device configuration. + * + * The function is used to set the device configuration. + * + * @param handle The device handle. + * @param configure The configuration value. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceSetConfigure(usb_device_handle handle, uint8_t configure) +{ + if (!configure) + { + return kStatus_USB_Error; + } + g_currentConfigure = configure; + return USB_DeviceCallback(handle, kUSB_DeviceEventSetConfiguration, &configure); +} + +/*! + * @brief Get the device configuration. + * + * The function is used to get the device configuration. + * + * @param handle The device handle. + * @param configure It is an OUT parameter, save the current configuration value. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetConfigure(usb_device_handle handle, uint8_t *configure) +{ + *configure = g_currentConfigure; + return kStatus_USB_Success; +} + +/*! + * @brief Set an interface alternate setting. + * + * The function is used to set an interface alternate setting. + * + * @param handle The device handle. + * @param interface The interface index. + * @param alternateSetting The new alternate setting value. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceSetInterface(usb_device_handle handle, uint8_t interface, uint8_t alternateSetting) +{ + g_interface[interface] = alternateSetting; + return USB_DeviceCallback(handle, kUSB_DeviceEventSetInterface, &interface); +} + +/*! + * @brief Get an interface alternate setting. + * + * The function is used to get an interface alternate setting. + * + * @param handle The device handle. + * @param interface The interface index. + * @param alternateSetting It is an OUT parameter, save the new alternate setting value of the interface. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetInterface(usb_device_handle handle, uint8_t interface, uint8_t *alternateSetting) +{ + *alternateSetting = g_interface[interface]; + return kStatus_USB_Success; +} + +/*! + * @brief USB device set speed function. + * + * This function sets the speed of the USB device. + * + * Due to the difference of HS and FS descriptors, the device descriptors and configurations need to be updated to match + * current speed. + * As the default, the device descriptors and configurations are configured by using FS parameters for both EHCI and + * KHCI. + * When the EHCI is enabled, the application needs to call this fucntion to update device by using current speed. + * The updated information includes endpoint max packet size, endpoint interval, etc. + * + * @param handle The USB device handle. + * @param speed Speed type. USB_SPEED_HIGH/USB_SPEED_FULL/USB_SPEED_LOW. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceSetSpeed(usb_device_handle handle, uint8_t speed) +{ + usb_descriptor_union_t *ptr1; + usb_descriptor_union_t *ptr2; + + ptr1 = (usb_descriptor_union_t *)(&g_UsbDeviceConfigurationDescriptor[0]); + ptr2 = (usb_descriptor_union_t *)(&g_UsbDeviceConfigurationDescriptor[USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL - 1]); + + while (ptr1 < ptr2) + { + if (ptr1->common.bDescriptorType == USB_DESCRIPTOR_TYPE_ENDPOINT) + { + if (USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU)) + { + if (USB_SPEED_HIGH == speed) + { + ptr1->endpoint.bInterval = HS_CDC_VCOM_INTERRUPT_IN_INTERVAL; + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE, + ptr1->endpoint.wMaxPacketSize); + } + else + { + ptr1->endpoint.bInterval = FS_CDC_VCOM_INTERRUPT_IN_INTERVAL; + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE, + ptr1->endpoint.wMaxPacketSize); + } + } + else if (USB_CDC_VCOM_BULK_IN_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU)) + { + if (USB_SPEED_HIGH == speed) + { + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_IN_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); + } + else + { + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_IN_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); + } + } + else if (USB_CDC_VCOM_BULK_OUT_ENDPOINT == (ptr1->endpoint.bEndpointAddress & 0x0FU)) + { + if (USB_SPEED_HIGH == speed) + { + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(HS_CDC_VCOM_BULK_OUT_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); + } + else + { + USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(FS_CDC_VCOM_BULK_OUT_PACKET_SIZE, ptr1->endpoint.wMaxPacketSize); + } + } + else + { + } + } + ptr1 = (usb_descriptor_union_t *)((uint8_t *)ptr1 + ptr1->common.bLength); + } + return kStatus_USB_Success; +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.h new file mode 100644 index 00000000000..5b8c8084a26 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/usb_device_descriptor.h @@ -0,0 +1,203 @@ +/* + * The Clear BSD License + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _USB_DEVICE_DESCRIPTOR_H_ +#define _USB_DEVICE_DESCRIPTOR_H_ 1 + +/******************************************************************************* +* Definitions +******************************************************************************/ +#define USB_DEVICE_SPECIFIC_BCD_VERSION (0x0200) +#define USB_DEVICE_DEMO_BCD_VERSION (0x0101U) + +/* Communication Class Codes */ +#define CDC_COMM_CLASS (0x02) +/* Data Class Codes */ +#define CDC_DATA_CLASS (0x0A) + +/* Communication Class SubClass Codes */ +#define USB_CDC_DIRECT_LINE_CONTROL_MODEL (0x01) +#define USB_CDC_ABSTRACT_CONTROL_MODEL (0x02) +#define USB_CDC_TELEPHONE_CONTROL_MODEL (0x03) +#define USB_CDC_MULTI_CHANNEL_CONTROL_MODEL (0x04) +#define USB_CDC_CAPI_CONTROL_MOPDEL (0x05) +#define USB_CDC_ETHERNET_NETWORKING_CONTROL_MODEL (0x06) +#define USB_CDC_ATM_NETWORKING_CONTROL_MODEL (0x07) +#define USB_CDC_WIRELESS_HANDSET_CONTROL_MODEL (0x08) +#define USB_CDC_DEVICE_MANAGEMENT (0x09) +#define USB_CDC_MOBILE_DIRECT_LINE_MODEL (0x0A) +#define USB_CDC_OBEX (0x0B) +#define USB_CDC_ETHERNET_EMULATION_MODEL (0x0C) + +/* Communication Class Protocol Codes */ +#define USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL (0x00) /*also for Data Class Protocol Code */ +#define USB_CDC_AT_250_PROTOCOL (0x01) +#define USB_CDC_AT_PCCA_101_PROTOCOL (0x02) +#define USB_CDC_AT_PCCA_101_ANNEX_O (0x03) +#define USB_CDC_AT_GSM_7_07 (0x04) +#define USB_CDC_AT_3GPP_27_007 (0x05) +#define USB_CDC_AT_TIA_CDMA (0x06) +#define USB_CDC_ETHERNET_EMULATION_PROTOCOL (0x07) +#define USB_CDC_EXTERNAL_PROTOCOL (0xFE) +#define USB_CDC_VENDOR_SPECIFIC (0xFF) /*also for Data Class Protocol Code */ + +/* Data Class Protocol Codes */ +#define USB_CDC_PYHSICAL_INTERFACE_PROTOCOL (0x30) +#define USB_CDC_HDLC_PROTOCOL (0x31) +#define USB_CDC_TRANSPARENT_PROTOCOL (0x32) +#define USB_CDC_MANAGEMENT_PROTOCOL (0x50) +#define USB_CDC_DATA_LINK_Q931_PROTOCOL (0x51) +#define USB_CDC_DATA_LINK_Q921_PROTOCOL (0x52) +#define USB_CDC_DATA_COMPRESSION_V42BIS (0x90) +#define USB_CDC_EURO_ISDN_PROTOCOL (0x91) +#define USB_CDC_RATE_ADAPTION_ISDN_V24 (0x92) +#define USB_CDC_CAPI_COMMANDS (0x93) +#define USB_CDC_HOST_BASED_DRIVER (0xFD) +#define USB_CDC_UNIT_FUNCTIONAL (0xFE) + +/* Descriptor SubType in Communications Class Functional Descriptors */ +#define USB_CDC_HEADER_FUNC_DESC (0x00) +#define USB_CDC_CALL_MANAGEMENT_FUNC_DESC (0x01) +#define USB_CDC_ABSTRACT_CONTROL_FUNC_DESC (0x02) +#define USB_CDC_DIRECT_LINE_FUNC_DESC (0x03) +#define USB_CDC_TELEPHONE_RINGER_FUNC_DESC (0x04) +#define USB_CDC_TELEPHONE_REPORT_FUNC_DESC (0x05) +#define USB_CDC_UNION_FUNC_DESC (0x06) +#define USB_CDC_COUNTRY_SELECT_FUNC_DESC (0x07) +#define USB_CDC_TELEPHONE_MODES_FUNC_DESC (0x08) +#define USB_CDC_TERMINAL_FUNC_DESC (0x09) +#define USB_CDC_NETWORK_CHANNEL_FUNC_DESC (0x0A) +#define USB_CDC_PROTOCOL_UNIT_FUNC_DESC (0x0B) +#define USB_CDC_EXTENSION_UNIT_FUNC_DESC (0x0C) +#define USB_CDC_MULTI_CHANNEL_FUNC_DESC (0x0D) +#define USB_CDC_CAPI_CONTROL_FUNC_DESC (0x0E) +#define USB_CDC_ETHERNET_NETWORKING_FUNC_DESC (0x0F) +#define USB_CDC_ATM_NETWORKING_FUNC_DESC (0x10) +#define USB_CDC_WIRELESS_CONTROL_FUNC_DESC (0x11) +#define USB_CDC_MOBILE_DIRECT_LINE_FUNC_DESC (0x12) +#define USB_CDC_MDLM_DETAIL_FUNC_DESC (0x13) +#define USB_CDC_DEVICE_MANAGEMENT_FUNC_DESC (0x14) +#define USB_CDC_OBEX_FUNC_DESC (0x15) +#define USB_CDC_COMMAND_SET_FUNC_DESC (0x16) +#define USB_CDC_COMMAND_SET_DETAIL_FUNC_DESC (0x17) +#define USB_CDC_TELEPHONE_CONTROL_FUNC_DESC (0x18) +#define USB_CDC_OBEX_SERVICE_ID_FUNC_DESC (0x19) + +/* usb descritpor length */ +#define USB_DESCRIPTOR_LENGTH_CONFIGURATION_ALL (67) +#define USB_DESCRIPTOR_LENGTH_CDC_HEADER_FUNC (5) +#define USB_DESCRIPTOR_LENGTH_CDC_CALL_MANAG (5) +#define USB_DESCRIPTOR_LENGTH_CDC_ABSTRACT (4) +#define USB_DESCRIPTOR_LENGTH_CDC_UNION_FUNC (5) + +#define USB_DEVICE_CONFIGURATION_COUNT (1) +#define USB_DEVICE_STRING_COUNT (3) +#define USB_DEVICE_LANGUAGE_COUNT (1) + +#define USB_CDC_VCOM_CONFIGURE_INDEX (1) + +#define USB_CDC_VCOM_ENDPOINT_CIC_COUNT (1) +#define USB_CDC_VCOM_ENDPOINT_DIC_COUNT (2) +#define USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT (1) +#define USB_CDC_VCOM_BULK_IN_ENDPOINT (2) +#define USB_CDC_VCOM_BULK_OUT_ENDPOINT (3) +#define USB_CDC_VCOM_INTERFACE_COUNT (2) +#define USB_CDC_VCOM_COMM_INTERFACE_INDEX (0) +#define USB_CDC_VCOM_DATA_INTERFACE_INDEX (1) + +#define HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE (16) +#define FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE (16) +#define HS_CDC_VCOM_INTERRUPT_IN_INTERVAL (0x07) /* 2^(7-1) = 8ms */ +#define FS_CDC_VCOM_INTERRUPT_IN_INTERVAL (0x08) +#define HS_CDC_VCOM_BULK_IN_PACKET_SIZE (512) +#define FS_CDC_VCOM_BULK_IN_PACKET_SIZE (64) +#define HS_CDC_VCOM_BULK_OUT_PACKET_SIZE (512) +#define FS_CDC_VCOM_BULK_OUT_PACKET_SIZE (64) + +#define USB_DESCRIPTOR_LENGTH_STRING0 (4) +#define USB_DESCRIPTOR_LENGTH_STRING1 (38) +#define USB_DESCRIPTOR_LENGTH_STRING2 (42) + +#define USB_DESCRIPTOR_TYPE_CDC_CS_INTERFACE (0x24) +#define USB_DESCRIPTOR_TYPE_CDC_CS_ENDPOINT (0x25) + +#define USB_DEVICE_CLASS (0x02) +#define USB_DEVICE_SUBCLASS (0x00) +#define USB_DEVICE_PROTOCOL (0x00) + +#define USB_DEVICE_MAX_POWER (0x32) + +#define USB_CDC_VCOM_CIC_CLASS (CDC_COMM_CLASS) +#define USB_CDC_VCOM_CIC_SUBCLASS (USB_CDC_ABSTRACT_CONTROL_MODEL) +#define USB_CDC_VCOM_CIC_PROTOCOL (USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL) + +#define USB_CDC_VCOM_DIC_CLASS (CDC_DATA_CLASS) +#define USB_CDC_VCOM_DIC_SUBCLASS (0x00) +#define USB_CDC_VCOM_DIC_PROTOCOL (USB_CDC_NO_CLASS_SPECIFIC_PROTOCOL) + +/******************************************************************************* +* API +******************************************************************************/ +/*! + * @brief USB device callback function. + * + * This function handles the usb device specific requests. + * + * @param handle The USB device handle. + * @param event The USB device event type. + * @param param The parameter of the device specific request. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, void *param); + +/*! + * @brief USB device set speed function. + * + * This function sets the speed of the USB device. + * + * Due to the difference of HS and FS descriptors, the device descriptors and configurations need to be updated to match + * current speed. + * As the default, the device descriptors and configurations are configured by using FS parameters for both EHCI and + * KHCI. + * When the EHCI is enabled, the application needs to call this fucntion to update device by using current speed. + * The updated information includes endpoint max packet size, endpoint interval, etc. + * + * @param handle The USB device handle. + * @param speed Speed type. USB_SPEED_HIGH/USB_SPEED_FULL/USB_SPEED_LOW. + * + * @return A USB error code or kStatus_USB_Success. + */ +extern usb_status_t USB_DeviceSetSpeed(usb_device_handle handle, uint8_t speed); + +#endif /* _USB_DEVICE_DESCRIPTOR_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.c b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.c new file mode 100644 index 00000000000..d9e507fbc61 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.c @@ -0,0 +1,693 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_device_registers.h" +#include "clock_config.h" +#include "board.h" + +#include +#include + +#include "usb_device_config.h" +#include "usb.h" +#include "usb_device.h" + +#include "usb_device_cdc_acm.h" +#include "usb_device_ch9.h" + +#include "usb_device_descriptor.h" +#include "virtual_com.h" +#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U)) +#include "fsl_sysmpu.h" +#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */ +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0) +#include "usb_phy.h" +#endif + +/* Provided by users. */ +extern void USB_DeviceClockInit(void); +extern void USB_DeviceIsrEnable(void); +/******************************************************************************* +* Definitions +******************************************************************************/ + +/******************************************************************************* +* Variables +******************************************************************************/ +/* Data structure of virtual com device */ +usb_cdc_vcom_struct_t s_cdcVcom; + +/* Line codinig of cdc device */ +static uint8_t s_lineCoding[LINE_CODING_SIZE] = { + /* E.g. 0x00,0xC2,0x01,0x00 : 0x0001C200 is 115200 bits per second */ + (LINE_CODING_DTERATE >> 0U) & 0x000000FFU, + (LINE_CODING_DTERATE >> 8U) & 0x000000FFU, + (LINE_CODING_DTERATE >> 16U) & 0x000000FFU, + (LINE_CODING_DTERATE >> 24U) & 0x000000FFU, + LINE_CODING_CHARFORMAT, + LINE_CODING_PARITYTYPE, + LINE_CODING_DATABITS}; + +/* Abstract state of cdc device */ +static uint8_t s_abstractState[COMM_FEATURE_DATA_SIZE] = {(STATUS_ABSTRACT_STATE >> 0U) & 0x00FFU, + (STATUS_ABSTRACT_STATE >> 8U) & 0x00FFU}; + +/* Country code of cdc device */ +static uint8_t s_countryCode[COMM_FEATURE_DATA_SIZE] = {(COUNTRY_SETTING >> 0U) & 0x00FFU, + (COUNTRY_SETTING >> 8U) & 0x00FFU}; + +/* CDC ACM information */ +static usb_cdc_acm_info_t s_usbCdcAcmInfo = {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 0, 0, 0, 0}; + +/* Data buffer for receiving and sending*/ +static uint8_t s_currRecvBuf[DATA_BUFF_SIZE]; +volatile static uint32_t s_recvSize = 0; +volatile static uint32_t s_sendSize = 0; +volatile static uint8_t s_sendComplete = 0; +volatile static uint8_t s_currRecvIndex = 0; +static uint32_t s_usbBulkMaxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE; +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/******************************************************************************* +* Code +******************************************************************************/ +/*! + * @brief Interrupt in pipe callback function. + * + * This function serves as the callback function for interrupt in pipe. + * + * @param handle The USB device handle. + * @param message The endpoint callback message + * @param callbackParam The parameter of the callback. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceCdcAcmInterruptIn(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam) +{ + usb_status_t error = kStatus_USB_Error; + + return error; +} + +/*! + * @brief Bulk in pipe callback function. + * + * This function serves as the callback function for bulk in pipe. + * + * @param handle The USB device handle. + * @param message The endpoint callback message + * @param callbackParam The parameter of the callback. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceCdcAcmBulkIn(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam) +{ + usb_status_t error = kStatus_USB_Error; + + if ((message->length != 0) && (!(message->length % s_usbBulkMaxPacketSize))) + { + /* If the last packet is the size of endpoint, then send also zero-ended packet, + ** meaning that we want to inform the host that we do not have any additional + ** data, so it can flush the output. + */ + USB_DeviceSendRequest(handle, USB_CDC_VCOM_BULK_IN_ENDPOINT, NULL, 0); + } + else if ((1 == s_cdcVcom.attach) && (1 == s_cdcVcom.startTransactions)) + { + if ((message->buffer != NULL) || ((message->buffer == NULL) && (message->length == 0))) + { + /* User: add your own code for send complete event */ + s_sendComplete = 1; +#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ + defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ + defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) + USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK; +#endif + } + } + else if ((0 == s_sendComplete) && (1 == s_cdcVcom.attach) && (0 == s_cdcVcom.startTransactions)) + { + s_sendComplete = 1; + } + else + { + } + return error; +} + +/*! + * @brief Bulk out pipe callback function. + * + * This function serves as the callback function for bulk out pipe. + * + * @param handle The USB device handle. + * @param message The endpoint callback message + * @param callbackParam The parameter of the callback. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceCdcAcmBulkOut(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam) +{ + usb_status_t error = kStatus_USB_Error; + if (USB_UNINITIALIZED_VAL_32 == message->length) + { + s_recvSize = 0xFFFFFFFFU; + } + else if ((1 == s_cdcVcom.attach) && (1 == s_cdcVcom.startTransactions)) + { + s_recvSize = message->length; +#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ + defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ + defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) + USB0->INTEN |= USB_INTEN_SOFTOKEN_MASK; +#endif + if (!s_recvSize) + { +#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ + defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ + defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) + USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK; +#endif + } + } + else + { + } + return error; +} + +/*! + * @brief Get the setup packet buffer. + * + * This function provides the buffer for setup packet. + * + * @param handle The USB device handle. + * @param setupBuffer The pointer to the address of setup packet buffer. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetSetupBuffer(usb_device_handle handle, usb_setup_struct_t **setupBuffer) +{ + static uint32_t cdcVcomSetup[2]; + if (NULL == setupBuffer) + { + return kStatus_USB_InvalidParameter; + } + *setupBuffer = (usb_setup_struct_t *)&cdcVcomSetup; + return kStatus_USB_Success; +} + +/*! + * @brief Get the setup packet data buffer. + * + * This function gets the data buffer for setup packet. + * + * @param handle The USB device handle. + * @param setup The pointer to the setup packet. + * @param length The pointer to the length of the data buffer. + * @param buffer The pointer to the address of setup packet data buffer. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetClassReceiveBuffer(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer) +{ + static uint8_t setupOut[8]; + if ((NULL == buffer) || ((*length) > sizeof(setupOut))) + { + return kStatus_USB_InvalidRequest; + } + *buffer = setupOut; + return kStatus_USB_Success; +} + +/*! + * @brief Configure remote wakeup feature. + * + * This function configures the remote wakeup feature. + * + * @param handle The USB device handle. + * @param enable 1: enable, 0: disable. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceConfigureRemoteWakeup(usb_device_handle handle, uint8_t enable) +{ + return kStatus_USB_InvalidRequest; +} + +/*! + * @brief CDC class specific callback function. + * + * This function handles the CDC class specific requests. + * + * @param handle The USB device handle. + * @param setup The pointer to the setup packet. + * @param length The pointer to the length of the data buffer. + * @param buffer The pointer to the address of setup packet data buffer. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceProcessClassRequest(usb_device_handle handle, + usb_setup_struct_t *setup, + uint32_t *length, + uint8_t **buffer) +{ + usb_status_t error = kStatus_USB_InvalidRequest; + + usb_cdc_acm_info_t *acmInfo = &s_usbCdcAcmInfo; + uint32_t len; + uint16_t *uartBitmap; + if (setup->wIndex != USB_CDC_VCOM_COMM_INTERFACE_INDEX) + { + return error; + } + + switch (setup->bRequest) + { + case USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND: + break; + case USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE: + break; + case USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE: + if (USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE == setup->wValue) + { + *buffer = s_abstractState; + } + else if (USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING == setup->wValue) + { + *buffer = s_countryCode; + } + else + { + } + error = kStatus_USB_Success; + break; + case USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE: + if (USB_DEVICE_CDC_FEATURE_ABSTRACT_STATE == setup->wValue) + { + *buffer = s_abstractState; + *length = COMM_FEATURE_DATA_SIZE; + } + else if (USB_DEVICE_CDC_FEATURE_COUNTRY_SETTING == setup->wValue) + { + *buffer = s_countryCode; + *length = COMM_FEATURE_DATA_SIZE; + } + else + { + } + error = kStatus_USB_Success; + break; + case USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE: + break; + case USB_DEVICE_CDC_REQUEST_GET_LINE_CODING: + *buffer = s_lineCoding; + *length = LINE_CODING_SIZE; + error = kStatus_USB_Success; + break; + case USB_DEVICE_CDC_REQUEST_SET_LINE_CODING: + *buffer = s_lineCoding; + error = kStatus_USB_Success; + break; + case USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE: + { + acmInfo->dteStatus = setup->wValue; + /* activate/deactivate Tx carrier */ + if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION) + { + acmInfo->uartState |= USB_DEVICE_CDC_UART_STATE_TX_CARRIER; + } + else + { + acmInfo->uartState &= (uint16_t)~USB_DEVICE_CDC_UART_STATE_TX_CARRIER; + } + + /* activate carrier and DTE */ + if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) + { + acmInfo->uartState |= USB_DEVICE_CDC_UART_STATE_RX_CARRIER; + } + else + { + acmInfo->uartState &= (uint16_t)~USB_DEVICE_CDC_UART_STATE_RX_CARRIER; + } + + /* Indicates to DCE if DTE is present or not */ + acmInfo->dtePresent = (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) ? true : false; + + /* Initialize the serial state buffer */ + acmInfo->serialStateBuf[0] = NOTIF_REQUEST_TYPE; /* bmRequestType */ + acmInfo->serialStateBuf[1] = USB_DEVICE_CDC_REQUEST_SERIAL_STATE_NOTIF; /* bNotification */ + acmInfo->serialStateBuf[2] = 0x00; /* wValue */ + acmInfo->serialStateBuf[3] = 0x00; + acmInfo->serialStateBuf[4] = 0x00; /* wIndex */ + acmInfo->serialStateBuf[5] = 0x00; + acmInfo->serialStateBuf[6] = UART_BITMAP_SIZE; /* wLength */ + acmInfo->serialStateBuf[7] = 0x00; + /* Notifiy to host the line state */ + acmInfo->serialStateBuf[4] = setup->wIndex; + /* Lower byte of UART BITMAP */ + uartBitmap = (uint16_t *)&acmInfo->serialStateBuf[NOTIF_PACKET_SIZE + UART_BITMAP_SIZE - 2]; + *uartBitmap = acmInfo->uartState; + len = (uint32_t)(NOTIF_PACKET_SIZE + UART_BITMAP_SIZE); + error = USB_DeviceSendRequest(handle, USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT, acmInfo->serialStateBuf, len); + + /* Update status */ + if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_CARRIER_ACTIVATION) + { + /* To do: CARRIER_ACTIVATED */ + } + else + { + /* To do: CARRIER_DEACTIVATED */ + } + if (acmInfo->dteStatus & USB_DEVICE_CDC_CONTROL_SIG_BITMAP_DTE_PRESENCE) + { + /* DTE_ACTIVATED */ + if (1 == s_cdcVcom.attach) + { + s_cdcVcom.startTransactions = 1; +#if defined(FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED) && (FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED > 0U) && \ + defined(USB_DEVICE_CONFIG_KEEP_ALIVE_MODE) && (USB_DEVICE_CONFIG_KEEP_ALIVE_MODE > 0U) && \ + defined(FSL_FEATURE_USB_KHCI_USB_RAM) && (FSL_FEATURE_USB_KHCI_USB_RAM > 0U) + USB0->INTEN &= ~USB_INTEN_SOFTOKEN_MASK; +#endif + } + } + else + { + /* DTE_DEACTIVATED */ + if (1 == s_cdcVcom.attach) + { + s_cdcVcom.startTransactions = 0; + } + } + } + break; + case USB_DEVICE_CDC_REQUEST_SEND_BREAK: + break; + default: + break; + } + + return error; +} + +/*! + * @brief USB device callback function. + * + * This function handles the usb device specific requests. + * + * @param handle The USB device handle. + * @param event The USB device event type. + * @param param The parameter of the device specific request. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceCallback(usb_device_handle handle, uint32_t event, void *param) +{ + usb_status_t error = kStatus_USB_Error; + uint8_t *temp8 = (uint8_t *)param; + + switch (event) + { + case kUSB_DeviceEventBusReset: + { + USB_DeviceControlPipeInit(s_cdcVcom.deviceHandle); + s_cdcVcom.attach = 0; +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0)) || \ + (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + if (kStatus_USB_Success == + USB_DeviceGetStatus(s_cdcVcom.deviceHandle, kUSB_DeviceStatusSpeed, &s_cdcVcom.speed)) + { + USB_DeviceSetSpeed(handle, s_cdcVcom.speed); + } +#endif + } + break; + case kUSB_DeviceEventSetConfiguration: + if (param) + { + s_cdcVcom.attach = 1; + s_cdcVcom.currentConfiguration = *temp8; + if (USB_CDC_VCOM_CONFIGURE_INDEX == (*temp8)) + { + usb_device_endpoint_init_struct_t epInitStruct; + usb_device_endpoint_callback_struct_t endpointCallback; + + /* Initiailize endpoint for interrupt pipe */ + endpointCallback.callbackFn = USB_DeviceCdcAcmInterruptIn; + endpointCallback.callbackParam = handle; + + epInitStruct.zlt = 0; + epInitStruct.transferType = USB_ENDPOINT_INTERRUPT; + epInitStruct.endpointAddress = USB_CDC_VCOM_INTERRUPT_IN_ENDPOINT | + (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + if (USB_SPEED_HIGH == s_cdcVcom.speed) + { + epInitStruct.maxPacketSize = HS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE; + } + else + { + epInitStruct.maxPacketSize = FS_CDC_VCOM_INTERRUPT_IN_PACKET_SIZE; + } + + USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback); + + /* Initiailize endpoints for bulk pipe */ + endpointCallback.callbackFn = USB_DeviceCdcAcmBulkIn; + endpointCallback.callbackParam = handle; + + epInitStruct.zlt = 0; + epInitStruct.transferType = USB_ENDPOINT_BULK; + epInitStruct.endpointAddress = + USB_CDC_VCOM_BULK_IN_ENDPOINT | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + if (USB_SPEED_HIGH == s_cdcVcom.speed) + { + epInitStruct.maxPacketSize = HS_CDC_VCOM_BULK_IN_PACKET_SIZE; + } + else + { + epInitStruct.maxPacketSize = FS_CDC_VCOM_BULK_IN_PACKET_SIZE; + } + + USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback); + + endpointCallback.callbackFn = USB_DeviceCdcAcmBulkOut; + endpointCallback.callbackParam = handle; + + epInitStruct.zlt = 0; + epInitStruct.transferType = USB_ENDPOINT_BULK; + epInitStruct.endpointAddress = + USB_CDC_VCOM_BULK_OUT_ENDPOINT | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + if (USB_SPEED_HIGH == s_cdcVcom.speed) + { + epInitStruct.maxPacketSize = HS_CDC_VCOM_BULK_OUT_PACKET_SIZE; + } + else + { + epInitStruct.maxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE; + } + + USB_DeviceInitEndpoint(s_cdcVcom.deviceHandle, &epInitStruct, &endpointCallback); + + if (USB_SPEED_HIGH == s_cdcVcom.speed) + { + s_usbBulkMaxPacketSize = HS_CDC_VCOM_BULK_OUT_PACKET_SIZE; + } + else + { + s_usbBulkMaxPacketSize = FS_CDC_VCOM_BULK_OUT_PACKET_SIZE; + } + } + } + break; + default: + break; + } + + return error; +} + +/*! + * @brief USB configure endpoint function. + * + * This function configure endpoint status. + * + * @param handle The USB device handle. + * @param ep Endpoint address. + * @param status A flag to indicate whether to stall the endpoint. 1: stall, 0: unstall. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceConfigureEndpointStatus(usb_device_handle handle, uint8_t ep, uint8_t status) +{ + if (status) + { + return USB_DeviceStallEndpoint(handle, ep); + } + else + { + return USB_DeviceUnstallEndpoint(handle, ep); + } +} + +/* See virtual_com.h for documentation of this function. */ +void USB_VcomWriteBlocking(usb_device_handle baseAddr, const uint8_t *buf, size_t count) +{ + while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1)) + { + __NOP(); + }; + USB_DeviceSendRequest((usb_device_handle)baseAddr, USB_CDC_VCOM_BULK_IN_ENDPOINT, (uint8_t *)buf, count); + while (!s_sendComplete) + { + __NOP(); + }; + s_sendComplete = 0; +} + +/* See virtual_com.h for documentation of this function. */ +status_t USB_VcomReadBlocking(usb_device_handle baseAddr, uint8_t *buf, size_t count) +{ + status_t error = kStatus_Success; + size_t bufIndex = 0U, bytesToReceive = 0U; + assert(count != 0U); + + /* Waiting for the USB ready. */ + while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1)) + { + __NOP(); + }; + + do + { + /* If no receive request. */ + if (s_recvSize <= 0) + { + if (kStatus_USB_Success != + USB_DeviceRecvRequest(baseAddr, USB_CDC_VCOM_BULK_OUT_ENDPOINT, s_currRecvBuf, s_usbBulkMaxPacketSize)) + { + return kStatus_Fail; + } + s_currRecvIndex = 0; + } + /* Waiting for data received by virtual com. */ + while (s_recvSize <= 0) + { + __NOP(); + }; + + /* When receive request is error. */ + if (0xFFFFFFFFU == s_recvSize) + { + /* Waiting for the USB ready and transfer started. */ + while ((s_cdcVcom.attach != 1) || (s_cdcVcom.startTransactions != 1)) + { + __NOP(); + }; + s_recvSize = 0; + } + else + { + bytesToReceive = MIN(count, s_recvSize); + memcpy((void *)&buf[bufIndex], s_currRecvBuf + s_currRecvIndex, bytesToReceive); + count -= bytesToReceive; + s_recvSize -= bytesToReceive; + bufIndex += bytesToReceive; + s_currRecvIndex += bytesToReceive; + } + } while (0U != count); + return error; +} + +/* See virtual_com.h for documentation of this function. */ +usb_device_handle USB_VcomInit(void) +{ + usb_device_handle deviceHandle = NULL; + + USB_DeviceClockInit(); + +#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U)) + SYSMPU_Enable(SYSMPU, 0); +#endif /* FSL_FEATURE_SOC_SYSMPU_COUNT */ + + s_cdcVcom.speed = USB_SPEED_FULL; + s_cdcVcom.attach = 0; + s_cdcVcom.deviceHandle = NULL; + + if (kStatus_USB_Success != USB_DeviceInit(CONTROLLER_ID, USB_DeviceCallback, &s_cdcVcom.deviceHandle)) + { + deviceHandle = NULL; + } + else + { + deviceHandle = s_cdcVcom.deviceHandle; + USB_DeviceIsrEnable(); + USB_DeviceRun(s_cdcVcom.deviceHandle); + } + return deviceHandle; +} + +/* See virtual_com.h for documentation of this function. */ +void USB_VcomDeinit(usb_device_handle deviceHandle) +{ + USB_DeviceStop(deviceHandle); + USB_DeviceDeinit(deviceHandle); + s_cdcVcom.deviceHandle = NULL; +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0) + USB_EhciPhyDeinit(CONTROLLER_ID); +#endif +#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0) + CLOCK_DisableUsbfs0Clock(); +#endif +#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U) + /* enable USB IP clock, user code. */ + CLOCK_DisableClock(kCLOCK_Usbd0); +#endif /* USB_DEVICE_CONFIG_LPCIP3511FS */ + +#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U) +/* enable USB IP clock,user code. */ +#endif /* USB_DEVICE_CONFIG_LPCIP3511HS */ +} diff --git a/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.h b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.h new file mode 100644 index 00000000000..37ea3051f8b --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/LPC54114/utilities/virtual_com.h @@ -0,0 +1,175 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _USB_CDC_VCOM_H_ +#define _USB_CDC_VCOM_H_ 1 + +#include "usb_device_descriptor.h" +#include "fsl_common.h" + +/******************************************************************************* +* Definitions +******************************************************************************/ +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0) +#define CONTROLLER_ID kUSB_ControllerEhci0 +#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE +#endif /* USB_DEVICE_CONFIG_EHCI */ + +#if defined(USB_DEVICE_CONFIG_KHCI) && (USB_DEVICE_CONFIG_KHCI > 0) +#define CONTROLLER_ID kUSB_ControllerKhci0 +#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE +#endif /* USB_DEVICE_CONFIG_KHCI */ + +#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U) +#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0 +#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE +#endif /* USB_DEVICE_CONFIG_LPCIP3511FS */ + +#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U) +#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0 +#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE +#endif /* USB_DEVICE_CONFIG_LPCIP3511HS */ + +#if defined(USB_DEVICE_CONFIG_LPCIP3511FS) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U) +#define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0 +#define DATA_BUFF_SIZE FS_CDC_VCOM_BULK_OUT_PACKET_SIZE + +#endif + +#if defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U) +#define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0 +#define DATA_BUFF_SIZE HS_CDC_VCOM_BULK_OUT_PACKET_SIZE +#endif + +#define USB_DEVICE_INTERRUPT_PRIORITY (3U) + +/* Currently configured line coding */ +#define LINE_CODING_SIZE (0x07) +#define LINE_CODING_DTERATE (115200) +#define LINE_CODING_CHARFORMAT (0x00) +#define LINE_CODING_PARITYTYPE (0x00) +#define LINE_CODING_DATABITS (0x08) + +/* Communications feature */ +#define COMM_FEATURE_DATA_SIZE (0x02) +#define STATUS_ABSTRACT_STATE (0x0000) +#define COUNTRY_SETTING (0x0000) + +/* Notification of serial state */ +#define NOTIF_PACKET_SIZE (0x08) +#define UART_BITMAP_SIZE (0x02) +#define NOTIF_REQUEST_TYPE (0xA1) + +/* Define the types for application */ +typedef struct _usb_cdc_vcom_struct +{ + usb_device_handle deviceHandle; /* USB device handle. */ + volatile uint8_t attach; /* A flag to indicate whether a usb device is attached. 1: attached, 0: not attached */ + uint8_t speed; /* Speed of USB device. USB_SPEED_FULL/USB_SPEED_LOW/USB_SPEED_HIGH. */ + volatile uint8_t + startTransactions; /* A flag to indicate whether a CDC device is ready to transmit and receive data. */ + uint8_t currentConfiguration; /* Current configuration value. */ + uint8_t currentInterfaceAlternateSetting + [USB_CDC_VCOM_INTERFACE_COUNT]; /* Current alternate setting value for each interface. */ +} usb_cdc_vcom_struct_t; + +/* Define the infomation relates to abstract control model */ +typedef struct _usb_cdc_acm_info +{ + uint8_t serialStateBuf[NOTIF_PACKET_SIZE + UART_BITMAP_SIZE]; /* Serial state buffer of the CDC device to notify the + serial state to host. */ + bool dtePresent; /* A flag to indicate whether DTE is present. */ + uint16_t breakDuration; /* Length of time in milliseconds of the break signal */ + uint8_t dteStatus; /* Status of data terminal equipment */ + uint8_t currentInterface; /* Current interface index. */ + uint16_t uartState; /* UART state of the CDC device. */ +} usb_cdc_acm_info_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Application initialization function. + * + * This function initializes the application. + * + * @return pointer to USB device handle. + */ +usb_device_handle USB_VcomInit(void); + +/*! + * @brief Application initialization function. + * + * This function initializes the application. + * + * @return pointer to USB device handle. + */ +void USB_VcomDeinit(usb_device_handle deviceHandle); + +/*! + * @brief USB recive data from host using a blocking method. + * + * This function recives data from host by usb cdc protocol + * @param baseAddr pointer to USB device handle. + * @param buf pointer to the data. + * @param count size of the transfer. + * + * @return A USB error code or kStatus_USB_Success. + */ +status_t USB_VcomReadBlocking(usb_device_handle baseAddr, uint8_t *buf, size_t count); + +/*! + * @brief USB recive 'count' number of data from host using a blocking method. + * + * This function recives data from host by usb cdc protocol + * @param baseAddr pointer to USB device handle. + * @param buf pointer to the data. + * @param count size of the transfer. + * + * @return A USB error code or kStatus_USB_Success. + */ +status_t USB_VcomReadPolling(usb_device_handle baseAddr, uint8_t *buf, size_t count); + +/*! + * @brief USB send data to host using a blocking method. + * + * This function sends data to host by usb cdc protocol + * @param baseAddr pointer to USB device handle. + * @param buf pointer to the data. + * @param count size of the transfer. + * + * @return None. + */ +void USB_VcomWriteBlocking(usb_device_handle baseAddr, const uint8_t *buf, size_t count); + +#endif /* _USB_CDC_VCOM_H_ */ diff --git a/bsp/lpc54114-lite/Libraries/devices/SConscript b/bsp/lpc54114-lite/Libraries/devices/SConscript new file mode 100644 index 00000000000..4c815c49b83 --- /dev/null +++ b/bsp/lpc54114-lite/Libraries/devices/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/lpc54114-lite/README.md b/bsp/lpc54114-lite/README.md new file mode 100644 index 00000000000..7247a6f08c2 --- /dev/null +++ b/bsp/lpc54114-lite/README.md @@ -0,0 +1,108 @@ +# LPC54114-Lite 开发板 BSP 说明 + +## 简介 + +本文档为 LPC54114-Lite 开发板的 BSP (板级支持包) 说明，LPC54114-Lite 开发板即 NXP LPC54110 Board 开发板。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +LPC54114-Lite 开发板由万利电子提供，双核高性能，专注语音应用的测试开发板卡。 + +开发板外观如下图所示： + +![LPC54114-Lite](figures/LPC54114-Lite(LPC54110).jpg) + +该开发板常用**板载资源**如下： + +- MCU：LPC54114J256BD64 Cortex-M4/M0+ 双核 MCU ，主频 100MHz，256KB FLASH ，192KB RAM +- 外部 FLASH：型号 MD25D16SIG，16MBIT +- 常用外设 + - LED：8 个，LD4-LD7（绿色，PIO0_30、PIO0_29、PIO0_26、PIO0_25），LD8-LD11（红色，PIO0_22、PIO0_21、PIO0_19、PIO0_15） + - 按键：4 个，PB2-PB5（PIO1_8、PIO1_9、PIO1_10、PIO1_11） +- 常用接口：USB、TF、音频接口 +- 调试接口：SWD + +LPC54114-Lite 开发板的更多详细信息请参考万利电子 [开发板用户手册](http://www.manley.com.cn/web/admin_ml32/pic/down/LPC54110%BF%AA%B7%A2%B0%E5%D3%C3%BB%A7%CA%D6%B2%E1.pdf)，[点击此处详见更多资料](http://www.manley.com.cn/web/product_detail.asp?pro=326)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +|**板载外设** |**支持情况**|**备注** | +| ----------------- | :----------: | ------------------------------------- | +| SPI Flash | 支持 |- | +| SPI TF 卡 | 支持 |- | +| I2C 温度传感器
(PCT2075DP) | 支持 |- | +| I2S 音频输入 / 输出接口
(WM8904) | 暂不支持 |- | +| PDM 数字麦克风
(SPH0641LM4H) | 暂不支持 |- | +|**片上外设** |**支持情况**|**备注** | +| GPIO | 支持 | PIO0_0 ... PIO1_31 ---> PIN: 0, 1...63 | +| UART | 支持 | UART0 | +| SPI | 支持 | 暂时只支持SPI2 | +| I2C | 支持 | 暂时只支持I2C4 | +| ADC | 暂不支持 | 即将支持 | +| PWM | 暂不支持 | 即将支持 | +| USB Device | 暂不支持 | 即将支持 | +| IWG | 暂不支持 | 即将支持 | +|**板外外设** |**支持情况**|**备注** | +| Arduino 扩展接口 | 暂不支持 |- | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用 Micro USB 数据线连接开发板 CN1 到 PC（注意：需要下载安装 mbedSerial 驱动，使用 MDK5 需要安装 LPC54114 相关的 pack）。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 CMSIS-DAP 仿真器下载程序，在通过 Micro USB 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，看到编号为 LD4 的这颗绿色 LED 在闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 3.1.1 build Nov 19 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +## 注意事项 + +- 需要下载并安装 mbedSerial 驱动 +- 若使用 MDK5，则需要下载所使用的 pack +- BSP 仅支持 M4 内核 + +## 联系人信息 + +维护人: + +- [yangjie](https://github.com/yangjie11) \ No newline at end of file diff --git a/bsp/lpc54114-lite/SConscript b/bsp/lpc54114-lite/SConscript new file mode 100644 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/lpc54114-lite/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/lpc54114-lite/SConstruct b/bsp/lpc54114-lite/SConstruct new file mode 100644 index 00000000000..ab84f82f3ca --- /dev/null +++ b/bsp/lpc54114-lite/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-%s.%s' % (rtconfig.BOARD_NAME, rtconfig.TARGET_EXT) + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) + +if rtconfig.PLATFORM == 'armcc': + # overwrite cflags, because cflags has '--C99' + env['CXXCOM'] = env['$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES'] + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/lpc54114-lite/applications/SConscript b/bsp/lpc54114-lite/applications/SConscript new file mode 100644 index 00000000000..04f04dd5435 --- /dev/null +++ b/bsp/lpc54114-lite/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/lpc54114-lite/applications/main.c b/bsp/lpc54114-lite/applications/main.c new file mode 100644 index 00000000000..5c13ff51661 --- /dev/null +++ b/bsp/lpc54114-lite/applications/main.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2015-07-29 Arda.Fu first implementation + */ +#include +#include + +#define LED4_PIN 30 /* PIO0_30 */ + +int main(void) +{ + /* user app entry */ + rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED4_PIN, !rt_pin_read(LED4_PIN)); + rt_thread_delay(1000); + } +} diff --git a/bsp/lpc54114-lite/applications/mnt.c b/bsp/lpc54114-lite/applications/mnt.c new file mode 100644 index 00000000000..7942e159edb --- /dev/null +++ b/bsp/lpc54114-lite/applications/mnt.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include + +#if defined(RT_USING_DFS) +#include +#include +#endif + +#define BSP_FLASH_MOUNT_PATH "/mnt/flash" +#define BSP_SDCARD_MOUNT_PATH "/mnt/sd" + +int mnt_init(void) +{ +#if defined(BSP_USING_SPIFLASH) + if(dfs_mount("flash0", BSP_FLASH_MOUNT_PATH, "elm", 0, 0) != 0) + { + rt_kprintf("spi flash mount '%s' failed.\n", BSP_FLASH_MOUNT_PATH); + } +#endif + +#if defined(BSP_USING_SDCARD) + if(dfs_mount("sd0", BSP_SDCARD_MOUNT_PATH, "elm", 0, 0) != 0) + { + rt_kprintf("sdcard mount '%s' failed.\n", BSP_SDCARD_MOUNT_PATH); + } +#endif + + return 0; +} +INIT_APP_EXPORT(mnt_init); diff --git a/bsp/lpc54114-lite/drivers/Kconfig b/bsp/lpc54114-lite/drivers/Kconfig new file mode 100644 index 00000000000..e6166386633 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/Kconfig @@ -0,0 +1,38 @@ +# LPC54110 bsp Config +menu "LPC54110 Bsp Config" + + menu "Select uart drivers" + config BSP_USING_UART0 + bool "Enable UART0" + default y + endmenu + + menu "Select spi bus drivers" + config BSP_USING_SPI2 + bool "Enable SPI2" + default y + endmenu + + menu "Select i2c bus drivers" + config BSP_USING_I2C4 + bool "Enable I2C4" + default y + endmenu + + config BSP_USING_ROMFS + bool "Enable ROMFS" + select RT_USING_DFS + select RT_USING_DFS_ROMFS + default y + + config BSP_USING_SDCARD + bool "Enable SDCARD" + select BSP_USING_SPI2 + default y + + config BSP_USING_SPIFLASH + bool "Enable SPI Flash" + select BSP_USING_SPI2 + default y + +endmenu diff --git a/bsp/lpc54114-lite/drivers/SConscript b/bsp/lpc54114-lite/drivers/SConscript new file mode 100644 index 00000000000..1bdfeedc1cd --- /dev/null +++ b/bsp/lpc54114-lite/drivers/SConscript @@ -0,0 +1,34 @@ +from building import * + +cwd = GetCurrentDir() + +src = Split(""" +board.c +clock_config.c +drv_gpio.c +""") + +CPPPATH = [cwd] + +# add driver code +if GetDepend('BSP_USING_UART0'): + src = src + ['drv_uart.c'] + +if GetDepend('BSP_USING_SPI2'): + src = src + ['drv_spi.c'] + +if GetDepend('BSP_USING_I2C4'): + src = src + ['drv_i2c.c'] + +if GetDepend('BSP_USING_ROMFS'): + src = src + ['drv_romfs.c'] + +if GetDepend('BSP_USING_SDCARD'): + src = src + ['drv_sdcard.c'] + +if GetDepend('BSP_USING_SPIFLASH'): + src = src + ['drv_spi_flash.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/lpc54114-lite/drivers/board.c b/bsp/lpc54114-lite/drivers/board.c new file mode 100644 index 00000000000..61652d1c789 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/board.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + * 2010-02-04 Magicoe ported to LPC17xx + * 2010-05-02 Aozima update CMSIS to 130 + * 2017-08-02 XiaoYang porting to LPC54608 bsp + */ + +#include +#include + +#include "board.h" +#include "clock_config.h" +#include "drv_uart.h" + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial LPC54xx board. + */ +void rt_hw_board_init() +{ + /* Hardware Initialization */ + CLOCK_EnableClock(kCLOCK_InputMux); + CLOCK_EnableClock(kCLOCK_Iocon); + + /* NVIC Configuration */ +#define NVIC_VTOR_MASK 0x3FFFFF80 +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x00000000 */ + SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); +#endif + + BOARD_BootClockFROHF48M(); + /* init systick 1 systick = 1/(100M / 100) 100��systick = 1s*/ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + /* initialization board with RT-Thread Components */ + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +void MemManage_Handler(void) +{ + extern void HardFault_Handler(void); + + rt_kprintf("Memory Fault!\n"); + HardFault_Handler(); +} diff --git a/bsp/lpc54114-lite/drivers/board.h b/bsp/lpc54114-lite/drivers/board.h new file mode 100644 index 00000000000..78c6d7c8c30 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/board.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2010-02-04 Magicoe add board.h to LPC176x bsp + * 2013-12-18 Bernard porting to LPC4088 bsp + * 2017-08-02 XiaoYang porting to LPC54608 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include + +// + +#ifdef __CC_ARM +extern int Image$$RTT_HEAP$$ZI$$Base; +extern int Image$$RTT_HEAP$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) +#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) +#else +extern int heap_start; +extern int heap_end; +#define HEAP_BEGIN (&heap_start) +#define HEAP_END (&heap_end) +#endif +//#define HEAP_END (void*)(0x20000000 + 0x28000) + +extern void rt_hw_board_init(void); +#endif diff --git a/bsp/lpc54114-lite/drivers/clock_config.c b/bsp/lpc54114-lite/drivers/clock_config.c new file mode 100644 index 00000000000..8cd74cb213b --- /dev/null +++ b/bsp/lpc54114-lite/drivers/clock_config.c @@ -0,0 +1,188 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Setup voltage for the fastest of the clock outputs + * + * 3. Set up wait states of the flash. + * + * 4. Set up all dividers. + * + * 5. Set up all selectors to provide selected clocks. + */ + +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!ClocksProfile +product: Clocks v1.0 +processor: LPC54114J256 +package_id: LPC54114J256BD64 +mcu_data: ksdk2_0 +processor_version: 1.1.0 +board: LPCXpresso54114 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF48M +outputs: +- {id: System_clock.outFreq, value: 48 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF48M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq(48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} +sources: +- {id: SYSCON.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +} + diff --git a/bsp/lpc54114-lite/drivers/clock_config.h b/bsp/lpc54114-lite/drivers/clock_config.h new file mode 100644 index 00000000000..7d909e20e1e --- /dev/null +++ b/bsp/lpc54114-lite/drivers/clock_config.h @@ -0,0 +1,124 @@ +/* + * The Clear BSD License + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ +#define BOARD_BootClockRUN BOARD_BootClockFROHF48M + + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/lpc54114-lite/drivers/drv_gpio.c b/bsp/lpc54114-lite/drivers/drv_gpio.c new file mode 100644 index 00000000000..2e1b4de609f --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_gpio.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-30 yangjie The first version for LPC54114 + */ + +#include +#include +#include + +#include "fsl_gpio.h" +#include "LPC54114_cm4.h" +#include "core_cm4.h" +#include "fsl_inputmux.h" +#include "fsl_pint.h" +#include "fsl_iocon.h" + +#ifdef RT_USING_PIN + +#define get_port(x) (x / 32) +#define get_pin(x) (x % 32) +#define PIN_MAX_VAL 63 +#define IRQ_MAX_VAL 8 + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +/* Configure pin mode. pin 0~63 means PIO0_0 ~ PIO1_31 */ +static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + int portx, piny, dir; + uint32_t pin_cfg; + + if(pin > PIN_MAX_VAL) + return; + + portx = get_port(pin); + piny = get_pin(pin); + + switch(mode) + { + case PIN_MODE_OUTPUT: + dir = kGPIO_DigitalOutput; + pin_cfg = IOCON_FUNC0 | IOCON_DIGITAL_EN; + break; + case PIN_MODE_OUTPUT_OD: + dir = kGPIO_DigitalOutput; + pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN; + break; + + case PIN_MODE_INPUT: + dir = kGPIO_DigitalInput; + pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN; + break; + case PIN_MODE_INPUT_PULLUP: + dir = kGPIO_DigitalInput; + pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP; + break; + case PIN_MODE_INPUT_PULLDOWN: + dir = kGPIO_DigitalInput; + pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN; + break; + default: break; + } + + CLOCK_EnableClock(kCLOCK_Iocon); + + IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg); + GPIO_PortInit(GPIO, portx); + + gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 0}; + GPIO_PinInit(GPIO, portx, piny, &pin_config); + + CLOCK_DisableClock(kCLOCK_Iocon); +} + +static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + int portx, piny; + portx = get_port(pin); + piny = get_pin(pin); + + if(pin > PIN_MAX_VAL) + return; + + GPIO_PinWrite(GPIO, portx, piny, value); +} + +static int lpc_pin_read(rt_device_t dev, rt_base_t pin) +{ + int portx, piny, value; + + if(pin > PIN_MAX_VAL) + return RT_ERROR; + + portx = get_port(pin); + piny = get_pin(pin); + + value = (int)(GPIO_PinRead(GPIO, portx, piny)); + + return value; +} + +static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status) +{ + int irqno = 0; + for(irqno = 0; irqno < IRQ_MAX_VAL; irqno ++) + { + if((irqno) == pintr) + { + break; + } + } + + if(irqno >= IRQ_MAX_VAL) + return; + + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void callback(pint_pin_int_t pintr, uint32_t pmatch_status) +{ + pin_irq_hdr(pintr, pmatch_status); +} + +static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i; + + if(pin > PIN_MAX_VAL) + return RT_ERROR; + + portx = get_port(pin); + piny = get_pin(pin); + + switch (mode) + { + case PIN_IRQ_MODE_RISING: + trigger_mode = kPINT_PinIntEnableRiseEdge; + break; + case PIN_IRQ_MODE_FALLING: + trigger_mode = kPINT_PinIntEnableFallEdge; + break; + case PIN_IRQ_MODE_RISING_FALLING: + trigger_mode = kPINT_PinIntEnableBothEdges; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + trigger_mode = kPINT_PinIntEnableHighLevel; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + trigger_mode = kPINT_PinIntEnableLowLevel; + break; + } + + /* Get inputmux_connection_t */ + pintsel = (pin + (0xC0U << 20)); + + for(i = 0; i < IRQ_MAX_VAL; i++) + { + if(pin_irq_hdr_tab[i].pin == -1) + { + pin_initx = kPINT_PinInt0 + i; + pin_irq_hdr_tab[i].pin = pin; + pin_irq_hdr_tab[i].mode = trigger_mode; + pin_irq_hdr_tab[i].hdr = hdr; + pin_irq_hdr_tab[i].args = args; + break; + } + } + + if(i >= IRQ_MAX_VAL) + return RT_ERROR; + + /* open clk */ + CLOCK_EnableClock(kCLOCK_InputMux); + CLOCK_EnableClock(kCLOCK_Iocon); + + /* AttachSignal */ + INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel); + pin_cfg = ((IOCON->PIO[portx][piny] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(0) /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */ + | IOCON_PIO_DIGIMODE(1) /* Select Analog/Digital mode.: Digital mode. */ + | IOCON_PIO_FILTEROFF(0)); /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */ + + IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg); + + /* PINT_PinInterruptConfig */ + PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback); + + CLOCK_DisableClock(kCLOCK_InputMux); + CLOCK_DisableClock(kCLOCK_Iocon); + + return RT_EOK; +} + +static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + int i; + + if(pin > PIN_MAX_VAL) + return RT_ERROR; + + for(i = 0; i < IRQ_MAX_VAL; i++) + { + if(pin_irq_hdr_tab[i].pin == pin) + { + pin_irq_hdr_tab[i].pin = -1; + pin_irq_hdr_tab[i].hdr = RT_NULL; + pin_irq_hdr_tab[i].mode = 0; + pin_irq_hdr_tab[i].args = RT_NULL; + break; + } + } + return RT_EOK; +} + +static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + int irqn_type, i; + + if(pin > PIN_MAX_VAL) + return RT_ERROR; + + for(i = 0; i < IRQ_MAX_VAL; i++) + { + if(pin_irq_hdr_tab[i].pin == pin) + { + switch(i) + { + case 0: irqn_type = PIN_INT0_IRQn; break; + case 1: irqn_type = PIN_INT1_IRQn; break; + case 2: irqn_type = PIN_INT2_IRQn; break; + case 3: irqn_type = PIN_INT3_IRQn; break; + case 4: irqn_type = PIN_INT4_IRQn; break; + case 5: irqn_type = PIN_INT5_IRQn; break; + case 6: irqn_type = PIN_INT6_IRQn; break; + case 7: irqn_type = PIN_INT7_IRQn; break; + default:break; + } + if(enabled) + { + /* PINT_EnableCallback */ + PINT_PinInterruptClrStatusAll(PINT); + NVIC_ClearPendingIRQ((IRQn_Type)irqn_type); + PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)(kPINT_PinInt0 + i)); + EnableIRQ((IRQn_Type)irqn_type); + } + else + { + /* PINT_DisableCallback */ + DisableIRQ((IRQn_Type)irqn_type); + PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)(kPINT_PinInt0 + i)); + NVIC_ClearPendingIRQ((IRQn_Type)irqn_type); + } + break; + } + } + + if(i >= IRQ_MAX_VAL) + return RT_ERROR; + + return RT_EOK; +} + +const static struct rt_pin_ops _lpc_pin_ops = +{ + lpc_pin_mode, + lpc_pin_write, + lpc_pin_read, + lpc_pin_attach_irq, + lpc_pin_detach_irq, + lpc_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + int result; + PINT_Init(PINT); + result = rt_device_pin_register("pin", &_lpc_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif diff --git a/bsp/lpc54114-lite/drivers/drv_gpio.h b/bsp/lpc54114-lite/drivers/drv_gpio.h new file mode 100644 index 00000000000..0c98e822984 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_gpio.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-30 yangjie add drv_gpio.h to this bsp + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +extern int rt_hw_pin_init(void); + +#endif diff --git a/bsp/lpc54114-lite/drivers/drv_i2c.c b/bsp/lpc54114-lite/drivers/drv_i2c.c new file mode 100644 index 00000000000..74047129f8f --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_i2c.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "drv_i2c.h" + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "fsl_i2c.h" + +struct lpc_i2c +{ + struct rt_i2c_bus_device bus; + + I2C_Type *base; + + char *device_name; +}; + +static uint32_t get_i2c_freq(I2C_Type *base) +{ + uint32_t freq = 0; + +#if defined(BSP_USING_I2C4) + if(base == I2C4) + { + freq = CLOCK_GetFreq(kCLOCK_Flexcomm4); + } +#endif + + return freq; +} + +static rt_size_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + rt_size_t ret = (0); + + rt_uint32_t index = 0; + struct lpc_i2c *lpc_i2c = RT_NULL; + struct rt_i2c_msg *msg = RT_NULL; + i2c_master_transfer_t xfer = {0}; + + RT_ASSERT(bus != RT_NULL); + + lpc_i2c = (struct lpc_i2c *)bus; + + for(index = 0; index < num; index++) + { + msg = &msgs[index]; + + xfer.slaveAddress = msg->addr; + xfer.flags = kI2C_TransferDefaultFlag; + xfer.subaddress = 0; + xfer.subaddressSize = 1; + xfer.data = msg->buf; + xfer.dataSize = msg->len; + + if (msg->flags & RT_I2C_RD) + { + xfer.direction = kI2C_Read; + } + else + { + xfer.direction = kI2C_Write; + } + + if(I2C_MasterTransferBlocking(lpc_i2c->base, &xfer) != kStatus_Success) + { + rt_kprintf("i2c bus write failed, i2c bus stop!\n"); + goto exit; + } + } + + ret = index; + +exit: + return ret; +} + +static rt_size_t slave_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + return 0; +} + +static rt_err_t i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t cmd, rt_uint32_t arg) +{ + return RT_EOK; +} + +static const struct rt_i2c_bus_device_ops ops = +{ + master_xfer, + slave_xfer, + i2c_bus_control, +}; + +#if defined(BSP_USING_I2C4) +static struct lpc_i2c i2c4 = {0}; +#endif + +int rt_hw_i2c_init(void) +{ + CLOCK_EnableClock(kCLOCK_Iocon); + +#if defined(BSP_USING_I2C4) + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); + RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn); + + i2c4.base = I2C4; + i2c4.device_name = "i2c4"; + i2c4.bus.ops = &ops; + + IOCON_PinMuxSet(IOCON, 1, 1, IOCON_MODE_PULLUP | IOCON_FUNC5 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + IOCON_PinMuxSet(IOCON, 1, 2, IOCON_MODE_PULLUP | IOCON_FUNC5 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + + i2c_master_config_t masterConfig; + + I2C_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = 100*1000U; + + I2C_MasterInit(I2C4, &masterConfig, get_i2c_freq(I2C4)); + + rt_i2c_bus_device_register(&i2c4.bus, i2c4.device_name); +#endif + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_i2c_init); diff --git a/bsp/lpc54114-lite/drivers/drv_i2c.h b/bsp/lpc54114-lite/drivers/drv_i2c.h new file mode 100644 index 00000000000..468ac3c0dc9 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_i2c.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#include +#include + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/lpc54114-lite/drivers/drv_romfs.c b/bsp/lpc54114-lite/drivers/drv_romfs.c new file mode 100644 index 00000000000..7c444af03fa --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_romfs.c @@ -0,0 +1,65 @@ +/* Generated by mkromfs. Edit with caution. */ +#include +#include + +static const rt_uint8_t _romfs_root_license[] = +{ + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x41, 0x70, 0x61, 0x63, 0x68, 0x65, 0x20, 0x4c, 0x69, 0x63, 0x65, 0x6e, 0x73, 0x65, 0x0d, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x56, 0x65, 0x72, 0x73, 0x69, 0x6f, 0x6e, 0x20, 0x32, 0x2e, 0x30, 0x2c, 0x20, 0x4a, 0x61, 0x6e, 0x75, 0x61, 0x72, 0x79, 0x20, 0x32, 0x30, 0x30, 0x34, 0x0d, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x61, 0x70, 0x61, 0x63, 0x68, 0x65, 0x2e, 0x6f, 0x72, 0x67, 0x2f, 0x6c, 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sizeof(_romfs_root_mnt_flash__keep) / sizeof(_romfs_root_mnt_flash__keep[0])} +}; + +static const rt_uint8_t _romfs_root_mnt_sd__keep[] = +{ + 0x2e, 0x6b, 0x65, 0x65, 0x70, 0x20, 0x0d, 0x0a +}; + +static const struct romfs_dirent _romfs_root_mnt_sd[] = +{ + {ROMFS_DIRENT_FILE, ".keep", (rt_uint8_t *)_romfs_root_mnt_sd__keep, sizeof(_romfs_root_mnt_sd__keep) / sizeof(_romfs_root_mnt_sd__keep[0])} +}; + +static const rt_uint8_t _romfs_root_mnt_tmp__keep[] = +{ + 0x2e, 0x6b, 0x65, 0x65, 0x70, 0x20, 0x0d, 0x0a +}; + +static const struct romfs_dirent _romfs_root_mnt_tmp[] = +{ + {ROMFS_DIRENT_FILE, ".keep", (rt_uint8_t *)_romfs_root_mnt_tmp__keep, sizeof(_romfs_root_mnt_tmp__keep) / sizeof(_romfs_root_mnt_tmp__keep[0])} +}; + +static const struct romfs_dirent _romfs_root_mnt[] = +{ + {ROMFS_DIRENT_DIR, "flash", (rt_uint8_t *)_romfs_root_mnt_flash, sizeof(_romfs_root_mnt_flash) / sizeof(_romfs_root_mnt_flash[0])}, + {ROMFS_DIRENT_DIR, "sd", (rt_uint8_t *)_romfs_root_mnt_sd, sizeof(_romfs_root_mnt_sd) / sizeof(_romfs_root_mnt_sd[0])}, + {ROMFS_DIRENT_DIR, "tmp", (rt_uint8_t *)_romfs_root_mnt_tmp, sizeof(_romfs_root_mnt_tmp) / sizeof(_romfs_root_mnt_tmp[0])} +}; + +static const struct romfs_dirent _romfs_root[] = +{ + {ROMFS_DIRENT_FILE, "license", (rt_uint8_t *)_romfs_root_license, sizeof(_romfs_root_license) / sizeof(_romfs_root_license[0])}, + {ROMFS_DIRENT_DIR, "mnt", (rt_uint8_t *)_romfs_root_mnt, sizeof(_romfs_root_mnt) / sizeof(_romfs_root_mnt[0])} +}; + +const struct romfs_dirent romfs_root = +{ + ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0]) +}; + +#include +int rt_hw_romfs_init(void) +{ + dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root); + + return 0; +} +INIT_EXPORT(rt_hw_romfs_init, "4.end"); diff --git a/bsp/lpc54114-lite/drivers/drv_sdcard.c b/bsp/lpc54114-lite/drivers/drv_sdcard.c new file mode 100644 index 00000000000..3ef5081aa74 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_sdcard.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "drv_sdcard.h" +#include "drv_spi.h" +#include "spi_msd.h" + +#define RT_SDCARD_CS_PIN (3) + +int rt_hw_sdcard_init(void) +{ + rt_err_t ret; + + ret = lpc_spi_bus_attach_device("spi2", "spi21", RT_SDCARD_CS_PIN); + if(ret != RT_EOK) + { + return ret; + } + + ret = msd_init("sd0", "spi21"); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_sdcard_init); diff --git a/bsp/lpc54114-lite/drivers/drv_sdcard.h b/bsp/lpc54114-lite/drivers/drv_sdcard.h new file mode 100644 index 00000000000..1ba77cf2b2b --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_sdcard.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_SDCARD_H__ +#define __DRV_SDCARD_H__ + +#include +#include + +int rt_hw_sdcard_init(void); + +#endif diff --git a/bsp/lpc54114-lite/drivers/drv_spi.c b/bsp/lpc54114-lite/drivers/drv_spi.c new file mode 100644 index 00000000000..0843e0baab2 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_spi.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "drv_spi.h" + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "fsl_spi.h" + +struct lpc_spi +{ + SPI_Type *base; + struct rt_spi_configuration *cfg; +}; + +static uint32_t get_spi_freq(SPI_Type *base) +{ + uint32_t freq = 0; + +#if defined(BSP_USING_SPI2) + if(base == SPI2) + { + freq = CLOCK_GetFreq(kCLOCK_Flexcomm2); + } +#endif + + return freq; +} + +static rt_err_t spi_init(SPI_Type *base, struct rt_spi_configuration *cfg) +{ + spi_master_config_t masterConfig = {0}; + + RT_ASSERT(cfg != RT_NULL); + + if(cfg->data_width != 8 && cfg->data_width != 16) + { + return (-RT_EINVAL); + } + + SPI_MasterGetDefaultConfig(&masterConfig); + + if(cfg->max_hz > 12*1000*1000) + { + cfg->max_hz = 12*1000*1000; + } + masterConfig.baudRate_Bps = cfg->max_hz; + + if(cfg->data_width == 8) + { + masterConfig.dataWidth = kSPI_Data8Bits; + } + else if(cfg->data_width == 16) + { + masterConfig.dataWidth = kSPI_Data16Bits; + } + + if(cfg->mode & RT_SPI_MSB) + { + masterConfig.direction = kSPI_MsbFirst; + } + else + { + masterConfig.direction = kSPI_LsbFirst; + } + + if(cfg->mode & RT_SPI_CPHA) + { + masterConfig.phase = kSPI_ClockPhaseSecondEdge; + } + else + { + masterConfig.phase = kSPI_ClockPhaseFirstEdge; + } + + if(cfg->mode & RT_SPI_CPOL) + { + masterConfig.polarity = kSPI_ClockPolarityActiveLow; + } + else + { + masterConfig.polarity = kSPI_ClockPolarityActiveHigh; + } + + masterConfig.txWatermark = kSPI_TxFifo0, + masterConfig.rxWatermark = kSPI_RxFifo1, + + // masterConfig.sselNum = kSPI_Ssel3; + SPI_MasterInit(base, &masterConfig, get_spi_freq(base)); + + return RT_EOK; +} + +rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) +{ + rt_err_t ret = RT_EOK; + + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, PIN_HIGH); + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; +} + +static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + rt_err_t ret = RT_EOK; + struct lpc_spi *spi = RT_NULL; + + RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(device != RT_NULL); + + spi = (struct lpc_spi *)(device->bus->parent.user_data); + spi->cfg = cfg; + ret = spi_init(spi->base, cfg); + + return ret; +} + +static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + spi_transfer_t transfer = {0}; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + + struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); + struct lpc_sw_spi_cs *cs = device->parent.user_data; + + if(message->cs_take) + { + rt_pin_write(cs->pin, PIN_LOW); + } + + transfer.dataSize = message->length; + transfer.rxData = (uint8_t *)(message->recv_buf); + transfer.txData = (uint8_t *)(message->send_buf); + transfer.configFlags |= kSPI_FrameAssert; + + SPI_MasterTransferBlocking(spi->base, &transfer); + + if(message->cs_release) + { + rt_pin_write(cs->pin, PIN_HIGH); + } + + return message->length; +} + +#if defined(BSP_USING_SPI2) +static struct lpc_spi spi2 = {0}; +static struct rt_spi_bus spi2_bus = {0}; +#endif + +static struct rt_spi_ops lpc_spi_ops = +{ + configure, + spixfer +}; + +int rt_hw_spi_init(void) +{ + CLOCK_EnableClock(kCLOCK_Iocon); + +#if defined(BSP_USING_SPI2) + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); + RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn); + + spi2.base = SPI2; + spi2.cfg = RT_NULL; + spi2_bus.parent.user_data = &spi2; + + IOCON_PinMuxSet(IOCON, 0, 8, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_MOSI */ + IOCON_PinMuxSet(IOCON, 0, 9, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_MISO */ + IOCON_PinMuxSet(IOCON, 0, 10, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_SCK */ + + rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops); +#endif + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/lpc54114-lite/drivers/drv_spi.h b/bsp/lpc54114-lite/drivers/drv_spi.h new file mode 100644 index 00000000000..c269cb98925 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_spi.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include + +struct lpc_sw_spi_cs +{ + rt_uint32_t pin; +}; + +int rt_hw_spi_init(void); +rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); + +#endif diff --git a/bsp/lpc54114-lite/drivers/drv_spi_flash.c b/bsp/lpc54114-lite/drivers/drv_spi_flash.c new file mode 100644 index 00000000000..65433ce30cd --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_spi_flash.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "drv_spi.h" +#include "drv_spi_flash.h" + +#include "rtthread.h" +#include "rtdevice.h" +#include "spi_flash.h" +#include "spi_flash_sfud.h" + +#define RT_SPI_FLASH_CS_PIN (2) + +int rt_hw_flash_init(void) +{ + rt_err_t result; + + result = lpc_spi_bus_attach_device("spi2", "spi20", RT_SPI_FLASH_CS_PIN); + if(result != RT_EOK) + { + return result; + } + + if(rt_sfud_flash_probe("flash0", "spi20") == RT_NULL) + { + return RT_ERROR; + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_flash_init); diff --git a/bsp/lpc54114-lite/drivers/drv_spi_flash.h b/bsp/lpc54114-lite/drivers/drv_spi_flash.h new file mode 100644 index 00000000000..f3c71e06c2a --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_spi_flash.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-11-08 ZYH the first version + */ +#ifndef __DRV_SPI_FLASH_H_ +#define __DRV_SPI_FLASH_H_ + +int rt_hw_w25qxx_init(void); + +#endif diff --git a/bsp/lpc54114-lite/drivers/drv_uart.c b/bsp/lpc54114-lite/drivers/drv_uart.c new file mode 100644 index 00000000000..fc0999d4a44 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_uart.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-05-18 Bernard The first version for LPC40xx + * 2014-12-16 RT_learning The first version for LPC5410x + * 2017-08-01 XiaoYang The first version for LPC546xx + * 2018-11-30 yangjie The first version for LPC54114 + */ + +#include +#include +#include + +#include "fsl_usart.h" +#include "fsl_common.h" +#include "fsl_iocon.h" + +struct lpc_uart +{ + USART_Type *UART; + IRQn_Type UART_IRQn; +}; + +static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct lpc_uart *uart; + usart_config_t u0_config; + + RT_ASSERT(serial != RT_NULL); + uart = (struct lpc_uart *)serial->parent.user_data; + + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kUSART_ParityDisabled; + * config.stopBitCount = kUSART_OneStopBit; + * config.loopback = false; + * config.enableTx = false; + * config.enableRx = false; + */ + USART_GetDefaultConfig(&u0_config); + + u0_config.baudRate_Bps = cfg->baud_rate; + u0_config.parityMode = kUSART_ParityDisabled, + u0_config.stopBitCount = kUSART_OneStopBit, + u0_config.bitCountPerChar = kUSART_8BitsPerChar, + u0_config.loopback = false, + u0_config.txWatermark = kUSART_TxFifo0, + u0_config.rxWatermark = kUSART_RxFifo1, + u0_config.enableTx = true; + u0_config.enableRx = true; + + USART_Init(uart->UART, &u0_config, CLOCK_GetFreq(kCLOCK_Flexcomm0)); + + return RT_EOK; +} + +static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct lpc_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct lpc_uart *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + USART_DisableInterrupts(uart->UART, kUSART_RxLevelInterruptEnable); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + USART_EnableInterrupts(uart->UART, kUSART_RxLevelInterruptEnable); + break; + } + + return RT_EOK; +} + +static int lpc_putc(struct rt_serial_device *serial, char c) +{ + struct lpc_uart *uart; + + uart = (struct lpc_uart *)serial->parent.user_data; + + while (!(kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(uart->UART))); + + USART_WriteByte(uart->UART, c); + + return 1; +} + +static int lpc_getc(struct rt_serial_device *serial) +{ + struct lpc_uart *uart; + + uart = (struct lpc_uart *)serial->parent.user_data; + if (kUSART_RxFifoNotEmptyFlag & USART_GetStatusFlags(uart->UART)) + { + return USART_ReadByte(uart->UART); + } + else + return -1; +} + +static const struct rt_uart_ops lpc_uart_ops = +{ + lpc_configure, + lpc_control, + lpc_putc, + lpc_getc, +}; + +#define PORT0_IDX 0u /*!< Port index */ +#define PIN0_IDX 0u /*!< Pin number for pin 0 */ +#define PIN1_IDX 1u /*!< Pin number for pin 1 */ + +/* UART0 device driver structure */ +struct lpc_uart uart0 = +{ + USART0, + FLEXCOMM0_IRQn, +}; +struct rt_serial_device serial0; + +void FLEXCOMM0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +int rt_hw_uart_init(void) +{ + struct lpc_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef BSP_USING_UART0 + + uart = &uart0; + + serial0.ops = &lpc_uart_ops; + serial0.config = config; + serial0.parent.user_data = uart; + + /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); + + /* reset FLEXCOMM for USART */ + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + + /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin0_config = ((IOCON->PIO[PORT0_IDX][PIN0_IDX] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(1) /* Selects pin function: PORT00 (pin 31) is configured as FC0_RXD_SDA_MOSI. */ + | IOCON_PIO_DIGIMODE(1)); /* Select Analog/Digital mode : Digital mode. */ + + IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN0_IDX, port0_pin0_config); /* PORT0 PIN0 (coords: 31) is configured as FC0_RXD_SDA_MOSI */ + + const uint32_t port0_pin1_config = ((IOCON->PIO[PORT0_IDX][PIN1_IDX] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(1) /* Selects pin function: PORT01 (pin 32) is configured as FC0_TXD_SCL_MISO. */ + | IOCON_PIO_DIGIMODE(1)); /* Select Analog/Digital mode : Digital mode. */ + + IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN1_IDX, port0_pin1_config); /* PORT0 PIN1 (coords: 32) is configured as FC0_TXD_SCL_MISO */ + + /* Enable RX interrupt. */ + USART_EnableInterrupts(uart->UART, kUSART_RxLevelInterruptEnable | kUSART_RxErrorInterruptEnable); + EnableIRQ(uart->UART_IRQn); + + CLOCK_DisableClock(kCLOCK_Iocon); + + /* register UART0 device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + uart); + +#endif + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/lpc54114-lite/drivers/drv_uart.h b/bsp/lpc54114-lite/drivers/drv_uart.h new file mode 100644 index 00000000000..e066448d24f --- /dev/null +++ b/bsp/lpc54114-lite/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-30 yangjie add drv_uart.h to this bsp + */ + +#ifndef DRV_UART_H_ +#define DRV_UART_H_ + +extern int rt_hw_uart_init(void); + +#endif diff --git a/bsp/lpc54114-lite/drivers/linker_scripts/link.icf b/bsp/lpc54114-lite/drivers/linker_scripts/link.icf new file mode 100644 index 00000000000..b3f169d4a29 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/linker_scripts/link.icf @@ -0,0 +1,138 @@ +/* +** ################################################################### +** Processors: LPC54114J256BD64_M4 +** LPC54114J256UK49_M4 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b161227 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000000DF; + +define symbol m_text_start = 0x000000E0; +define symbol m_text_end = 0x0002FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +if (isdefinedsymbol(__use_shmem__)) { +define exported symbol rpmsg_sh_mem_start = 0x20026800; +define exported symbol rpmsg_sh_mem_end = 0x20027FFF; +} + +define symbol m_sramx_start = 0x04000000; +define symbol m_sramx_end = 0x04007FFF; + +define exported symbol core1_image_start = 0x00030000; +define exported symbol core1_image_end = 0x0003FFFF; + +define symbol __crp_start__ = 0x000002FC; +define symbol __crp_end__ = 0x000002FF; + +define symbol __ram_iap_start__ = 0x2000FFE0; +define symbol __ram_iap_end__ = 0x2000FFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0800; +} + +define exported symbol __RTT_HEAP_END = m_data_end; +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end] + - mem:[from __crp_start__ to __crp_end__]; +define region DATA_region = mem:[from m_data_start to m_data_end] + - mem:[from __ram_iap_start__-__size_cstack__ to __ram_iap_end__]; +define region CSTACK_region = mem:[from __ram_iap_start__-__size_cstack__ to __ram_iap_start__-1]; +define region SRAMX_region = mem:[from m_sramx_start to m_sramx_end]; +define region CRP_region = mem:[from __crp_start__ to __crp_end__]; +if (isdefinedsymbol(__use_shmem__)) { +define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block SEC_CORE_IMAGE_WBLOCK { section __sec_core }; + +initialize by copy { readwrite }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { +do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in SRAMX_region { section sramx }; +place in CSTACK_region { block CSTACK }; +place in CRP_region { section .crp }; +if (isdefinedsymbol(__use_shmem__)) { +place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block SEC_CORE_IMAGE_WBLOCK }; diff --git a/bsp/lpc54114-lite/drivers/linker_scripts/link.lds b/bsp/lpc54114-lite/drivers/linker_scripts/link.lds new file mode 100644 index 00000000000..e1fb7acd66e --- /dev/null +++ b/bsp/lpc54114-lite/drivers/linker_scripts/link.lds @@ -0,0 +1,255 @@ +/* +** ################################################################### +** Processors: LPC54114J256_cm4 +** +** Compiler: GNU C Compiler +** Reference manual: LPC54114 Series Reference Manual, Rev. 0 , 11/2016 +** Version: rev. 1.0, 2016-11-02 +** Build: b161214 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; +RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x000000E4 + m_text (RX) : ORIGIN = 0x000000E4, LENGTH = 0x0002FF1C + m_core1_image (RX) : ORIGIN = 0x00030000, LENGTH = 0x00010000 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + rpmsg_sh_mem (RW) : ORIGIN = 0x20026800, LENGTH = RPMSG_SHMEM_SIZE +} + +/* Define output sections */ +SECTIONS +{ + /* section for storing the secondary core image */ + .m0code : + { + . = ALIGN(4) ; + KEEP (*(.m0code)) + *(.m0code*) + . = ALIGN(4) ; + } > m_core1_image + + /* NOINIT section for rpmsg_sh_mem */ + .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) + { + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + } > rpmsg_sh_mem + + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .RTT_HEAP : + { + heap_start = .; + . = ALIGN(8); + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + PROVIDE(heap_end = ORIGIN(m_data) + LENGTH(m_data)); + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + +} + diff --git a/bsp/lpc54114-lite/drivers/linker_scripts/link.scf b/bsp/lpc54114-lite/drivers/linker_scripts/link.scf new file mode 100644 index 00000000000..661f422fdd1 --- /dev/null +++ b/bsp/lpc54114-lite/drivers/linker_scripts/link.scf @@ -0,0 +1,123 @@ +#! armcc -E +/* +** ################################################################### +** Processors: LPC54114J256BD64_cm4 +** LPC54114J256UK49_cm4 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC5411x User manual Rev. 1.0 16 February 2016 +** Version: rev. 1.0, 2016-04-29 +** Build: b160526 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted (subject to the limitations in the disclaimer below) provided +** that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x000000E0 + +#define m_text_start 0x000000E0 +#define m_text_size 0x0002FF20 + +#define m_core1_image_start 0x00030000 +#define m_core1_image_size 0x00010000 + +#if (defined(__use_shmem__)) +#define m_rpmsg_sh_mem_start 0x20026800 +#define m_rpmsg_sh_mem_size 0x00001800 +#endif + +#define m_data_start 0x20000000 +#define m_data_size 0x00010000 + +#define m_sramx_start 0x04000000 +#define m_sramx_size 0x00008000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define RTT_HEAP_LENGTH (m_data_size - ImageLength(RW_m_data) - ImageLength(ARM_LIB_HEAP) - ImageLength(ARM_LIB_STACK)) + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + ER_m_sramx m_sramx_start m_sramx_size { ; SRAMX memory + * (sramx) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP ((ImageLimit(RW_m_data) == m_data_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + RTT_HEAP +0 EMPTY RTT_HEAP_LENGTH { + } + + +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif +} + +LR_CORE1_IMAGE m_core1_image_start { + CORE1_REGION m_core1_image_start m_core1_image_size { + *(M0CODE) + } +} + diff --git a/bsp/lpc54114-lite/figures/LPC54114-Lite(LPC54110).jpg b/bsp/lpc54114-lite/figures/LPC54114-Lite(LPC54110).jpg new file mode 100644 index 00000000000..f77f6b5848b Binary files /dev/null and b/bsp/lpc54114-lite/figures/LPC54114-Lite(LPC54110).jpg differ diff --git a/bsp/lpc54114-lite/project.ewd b/bsp/lpc54114-lite/project.ewd new file mode 100644 index 00000000000..03349840c29 --- /dev/null +++ b/bsp/lpc54114-lite/project.ewd @@ -0,0 +1,2966 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY 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$PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\time.c + + + diff --git a/bsp/lpc54114-lite/project.eww b/bsp/lpc54114-lite/project.eww new file mode 100644 index 00000000000..c2cb02eb1e8 --- /dev/null +++ b/bsp/lpc54114-lite/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/lpc54114-lite/project.uvoptx b/bsp/lpc54114-lite/project.uvoptx new file mode 100644 index 00000000000..688904474e4 --- /dev/null +++ b/bsp/lpc54114-lite/project.uvoptx @@ -0,0 +1,1624 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\..\components\finsh\finsh_token.c + finsh_token.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 9 + 109 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\libc.c + libc.c + 0 + 0 + + + 9 + 110 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 9 + 111 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\stdio.c + stdio.c + 0 + 0 + + + 9 + 112 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\stubs.c + stubs.c + 0 + 0 + + + 9 + 113 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\time.c + time.c + 0 + 0 + + + 9 + 114 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\gmtime_r.c + gmtime_r.c + 0 + 0 + + + + diff --git a/bsp/lpc54114-lite/project.uvprojx b/bsp/lpc54114-lite/project.uvprojx new file mode 100644 index 00000000000..9effdcbdcfa --- /dev/null +++ b/bsp/lpc54114-lite/project.uvprojx @@ -0,0 +1,1076 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-lpc54114 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + LPC54114J256BD64:M4 + NXP + Keil.LPC54000_DFP.2.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00028000) IRAM2(0x04000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0LPC5411x_256 -FS00 -FL040000 -FP0($$Device:LPC54114J256BD64$Flash\LPC5411x_256.FLM)) + 0 + $$Device:LPC54114J256BD64$LPCOpen\lpc5411x\chip_5411x\inc\chip.h + + + + + + + + + + $$Device:LPC54114J256BD64$SVD\LPC54114_cm4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-lpc54114 + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 0 + 0x4000000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + SDK_DEBUGCONSOLE=0, CPU_LPC54114, CORE_M4, RT_USING_ARM_LIBC, CPU_LPC54114J256BD64_cm4=1 + + applications;.;drivers;Libraries\CMSIS\Include;Libraries\devices\LPC54114\drivers;Libraries\devices\LPC54114\utilities;Libraries\devices\LPC54114;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\dfs\filesystems\romfs;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\drivers\linker_scripts\link.scf + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + mnt.c + 1 + applications\mnt.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + clock_config.c + 1 + drivers\clock_config.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + drv_spi.c + 1 + drivers\drv_spi.c + + + drv_i2c.c + 1 + drivers\drv_i2c.c + + + drv_sdcard.c + 1 + drivers\drv_sdcard.c + + + drv_spi_flash.c + 1 + drivers\drv_spi_flash.c + + + + + Libraries + + + fsl_adc.c + 1 + Libraries\devices\LPC54114\drivers\fsl_adc.c + + + fsl_clock.c + 1 + Libraries\devices\LPC54114\drivers\fsl_clock.c + + + fsl_common.c + 1 + Libraries\devices\LPC54114\drivers\fsl_common.c + + + fsl_crc.c + 1 + Libraries\devices\LPC54114\drivers\fsl_crc.c + + + fsl_ctimer.c + 1 + Libraries\devices\LPC54114\drivers\fsl_ctimer.c + + + fsl_dma.c + 1 + Libraries\devices\LPC54114\drivers\fsl_dma.c + + + fsl_dmic.c + 1 + Libraries\devices\LPC54114\drivers\fsl_dmic.c + + + fsl_dmic_dma.c + 1 + Libraries\devices\LPC54114\drivers\fsl_dmic_dma.c + + + fsl_flashiap.c + 1 + Libraries\devices\LPC54114\drivers\fsl_flashiap.c + + + fsl_flexcomm.c + 1 + Libraries\devices\LPC54114\drivers\fsl_flexcomm.c + + + fsl_fmeas.c + 1 + Libraries\devices\LPC54114\drivers\fsl_fmeas.c + + + fsl_gint.c + 1 + Libraries\devices\LPC54114\drivers\fsl_gint.c + + + fsl_gpio.c + 1 + Libraries\devices\LPC54114\drivers\fsl_gpio.c + + + fsl_i2c.c + 1 + Libraries\devices\LPC54114\drivers\fsl_i2c.c + + + fsl_i2c_dma.c + 1 + Libraries\devices\LPC54114\drivers\fsl_i2c_dma.c + + + fsl_i2s.c + 1 + Libraries\devices\LPC54114\drivers\fsl_i2s.c + + + fsl_i2s_dma.c + 1 + Libraries\devices\LPC54114\drivers\fsl_i2s_dma.c + + + fsl_inputmux.c + 1 + Libraries\devices\LPC54114\drivers\fsl_inputmux.c + + + fsl_mrt.c + 1 + Libraries\devices\LPC54114\drivers\fsl_mrt.c + + + fsl_pint.c + 1 + Libraries\devices\LPC54114\drivers\fsl_pint.c + + + fsl_power.c + 1 + Libraries\devices\LPC54114\drivers\fsl_power.c + + + fsl_reset.c + 1 + Libraries\devices\LPC54114\drivers\fsl_reset.c + + + fsl_rtc.c + 1 + Libraries\devices\LPC54114\drivers\fsl_rtc.c + + + fsl_sctimer.c + 1 + Libraries\devices\LPC54114\drivers\fsl_sctimer.c + + + fsl_spi.c + 1 + Libraries\devices\LPC54114\drivers\fsl_spi.c + + + fsl_spi_dma.c + 1 + Libraries\devices\LPC54114\drivers\fsl_spi_dma.c + + + fsl_usart.c + 1 + Libraries\devices\LPC54114\drivers\fsl_usart.c + + + fsl_usart_dma.c + 1 + Libraries\devices\LPC54114\drivers\fsl_usart_dma.c + + + fsl_utick.c + 1 + Libraries\devices\LPC54114\drivers\fsl_utick.c + + + fsl_wwdt.c + 1 + Libraries\devices\LPC54114\drivers\fsl_wwdt.c + + + startup_LPC54114_cm4.s + 2 + Libraries\devices\LPC54114\arm\startup_LPC54114_cm4.s + + + system_LPC54114_cm4.c + 1 + Libraries\devices\LPC54114\system_LPC54114_cm4.c + + + keil_lib_power.lib + 4 + Libraries\devices\LPC54114\arm\keil_lib_power.lib + + + + + Kernel + + + clock.c + 1 + ..\..\src\clock.c + + + components.c + 1 + ..\..\src\components.c + + + cpu.c + 1 + ..\..\src\cpu.c + + + device.c + 1 + ..\..\src\device.c + + + idle.c + 1 + ..\..\src\idle.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + irq.c + 1 + ..\..\src\irq.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + mem.c + 1 + ..\..\src\mem.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + object.c + 1 + ..\..\src\object.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + signal.c + 1 + ..\..\src\signal.c + + + thread.c + 1 + ..\..\src\thread.c + + + timer.c + 1 + ..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + + + Filesystem + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + poll.c + 1 + ..\..\components\dfs\src\poll.c + + + select.c + 1 + ..\..\components\dfs\src\select.c + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c + + + dfs_elm.c + 1 + ..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + ff.c + 1 + ..\..\components\dfs\filesystems\elmfat\ff.c + + + ccsbcs.c + 1 + ..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c + + + dfs_romfs.c + 1 + ..\..\components\dfs\filesystems\romfs\dfs_romfs.c + + + romfs.c + 1 + ..\..\components\dfs\filesystems\romfs\romfs.c + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + i2c_core.c + 1 + ..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\components\drivers\i2c\i2c_dev.c + + + i2c-bit-ops.c + 1 + ..\..\components\drivers\i2c\i2c-bit-ops.c + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\components\drivers\spi\spi_dev.c + + + spi_msd.c + 1 + ..\..\components\drivers\spi\spi_msd.c + + + spi_flash_sfud.c + 1 + ..\..\components\drivers\spi\spi_flash_sfud.c + + + sfud.c + 1 + ..\..\components\drivers\spi\sfud\src\sfud.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + symbol.c + 1 + ..\..\components\finsh\symbol.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + stubs.c + 1 + ..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\components\libc\compilers\armlibc\time.c + + + gmtime_r.c + 1 + ..\..\components\libc\compilers\common\gmtime_r.c + + + + + + + + + + + + + + diff --git a/bsp/lpc54114-lite/rtconfig.h b/bsp/lpc54114-lite/rtconfig.h new file mode 100644 index 00000000000..c68f41b1de5 --- /dev/null +++ b/bsp/lpc54114-lite/rtconfig.h @@ -0,0 +1,199 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x30102 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +#define RT_USING_SPI +#define RT_USING_SPI_MSD +#define RT_USING_SFUD +#define RT_SFUD_USING_FLASH_INFO_TABLE + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* ARM CMSIS */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_LPC54114 + +/* LPC54110 Bsp Config */ + +/* Select uart drivers */ + +#define BSP_USING_UART0 + +/* Select spi bus drivers */ + +#define BSP_USING_SPI2 + +/* Select i2c bus drivers */ + +#define BSP_USING_I2C4 +#define BSP_USING_ROMFS +#define BSP_USING_SDCARD +#define BSP_USING_SPIFLASH + +#endif diff --git a/bsp/lpc54114-lite/rtconfig.py b/bsp/lpc54114-lite/rtconfig.py new file mode 100644 index 00000000000..19f452a405a --- /dev/null +++ b/bsp/lpc54114-lite/rtconfig.py @@ -0,0 +1,135 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' +BOARD_NAME = 'lpc54114' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'D:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'D:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'g++' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections -mfpu=fpv4-sp-d16 -mfloat-abi=hard' + CFLAGS = DEVICE + ' -g -Wall -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__STARTUP_CLEAR_BSS' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,ResetISR -T drivers\linker_scripts\link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread_' + \ + BOARD_NAME + '.map --scatter \drivers\linker_scripts\link.scf' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' # + ' -D' + PART_TYPE + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "\drivers\linker_scripts\link.icf"' + LFLAGS += ' --entry __iar_program_start' + #LFLAGS += ' --silent' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/lpc54114-lite/template.ewp b/bsp/lpc54114-lite/template.ewp new file mode 100644 index 00000000000..cc4966fe811 --- /dev/null +++ b/bsp/lpc54114-lite/template.ewp @@ -0,0 +1,2074 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/lpc54114-lite/template.eww b/bsp/lpc54114-lite/template.eww new file mode 100644 index 00000000000..bd036bb4c98 --- /dev/null +++ b/bsp/lpc54114-lite/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/lpc54114-lite/template.uvoptx b/bsp/lpc54114-lite/template.uvoptx new file mode 100644 index 00000000000..c745aeab3c7 --- /dev/null +++ b/bsp/lpc54114-lite/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-lpc54114 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0LPC5411x_256.FLM -FS00 -FL040000 -FP0($$Device:LPC54114J256BD64$Flash\LPC5411x_256.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0LPC5411x_256 -FS00 -FL040000 -FP0($$Device:LPC54114J256BD64$Flash\LPC5411x_256.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 5000000 + + + + + diff --git a/bsp/lpc54114-lite/template.uvprojx b/bsp/lpc54114-lite/template.uvprojx new file mode 100644 index 00000000000..d4e92382a7a --- /dev/null +++ b/bsp/lpc54114-lite/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-lpc54114 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + LPC54114J256BD64:M4 + NXP + Keil.LPC54000_DFP.2.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00028000) IRAM2(0x04000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0LPC5411x_256 -FS00 -FL040000 -FP0($$Device:LPC54114J256BD64$Flash\LPC5411x_256.FLM)) + 0 + $$Device:LPC54114J256BD64$LPCOpen\lpc5411x\chip_5411x\inc\chip.h + + + + + + + + + + $$Device:LPC54114J256BD64$SVD\LPC54114_cm4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-lpc54114 + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 0 + 0x4000000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + CPU_LPC54608, CPU_LPC54608J512ET180=1 + + . + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\drivers\linker_scripts\link.scf + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + + + + + + + + diff --git a/bsp/lpc54608-LPCXpresso/.config b/bsp/lpc54608-LPCXpresso/.config index 5aff9d0e48e..85046e050d5 100644 --- a/bsp/lpc54608-LPCXpresso/.config +++ b/bsp/lpc54608-LPCXpresso/.config @@ -136,6 +136,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/lpc54608-LPCXpresso/rtconfig.h b/bsp/lpc54608-LPCXpresso/rtconfig.h index 7738810b58b..46855f77139 100644 --- a/bsp/lpc54608-LPCXpresso/rtconfig.h +++ b/bsp/lpc54608-LPCXpresso/rtconfig.h @@ -95,6 +95,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN diff --git a/bsp/lpc824/rtconfig.h b/bsp/lpc824/rtconfig.h index 1426427b8d4..ccc1a76d439 100644 --- a/bsp/lpc824/rtconfig.h +++ b/bsp/lpc824/rtconfig.h @@ -128,6 +128,7 @@ // Using Serial // Using Serial //#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // // diff --git a/bsp/ls1cdev/.config b/bsp/ls1cdev/.config index e51b00e78e2..30d3540c581 100644 --- a/bsp/ls1cdev/.config +++ b/bsp/ls1cdev/.config @@ -133,6 +133,7 @@ CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_USING_CAN=y # CONFIG_RT_CAN_USING_HDR is not set # CONFIG_RT_USING_HWTIMER is not set diff --git a/bsp/ls1cdev/Kconfig b/bsp/ls1cdev/Kconfig index 23ecbb31902..262e2e51845 100644 --- a/bsp/ls1cdev/Kconfig +++ b/bsp/ls1cdev/Kconfig @@ -27,6 +27,9 @@ if RT_USING_SERIAL config RT_USING_UART2 bool "Using RT_USING_UART2" default y +config RT_USING_UART1 + bool "Using RT_USING_UART1" + default y config RT_UART_RX_BUFFER_SIZE int "The rx buffer size" @@ -80,4 +83,26 @@ config RT_CAN_USING_HDR default y endif +choice + prompt "Touch format" + default NO_TOUCH + + config NO_TOUCH + bool "with no touch" + +if RT_USING_RTGUI + config XPT2046_USING_TOUCH + bool "with XPT2046 touch" +endif + + config TINA_USING_TOUCH + bool "with TINA touch" +endchoice + +if RT_USING_RTC +config RT_RTC_NAME + string "RT_RTC_NAME" + default "RTC" +endif + \ No newline at end of file diff --git a/bsp/ls1cdev/applications/main.c b/bsp/ls1cdev/applications/main.c index c3d6bbd31b4..fac004d8321 100644 --- a/bsp/ls1cdev/applications/main.c +++ b/bsp/ls1cdev/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,5 +12,6 @@ int main(int argc, char** argv) { + return 0; } diff --git a/bsp/ls1cdev/drivers/SConscript b/bsp/ls1cdev/drivers/SConscript index 2363e655a89..3e76809efb4 100644 --- a/bsp/ls1cdev/drivers/SConscript +++ b/bsp/ls1cdev/drivers/SConscript @@ -5,10 +5,6 @@ src = Glob('*.c') CPPPATH = [cwd] - -if GetDepend('RT_USING_RTGUI') == False: - SrcRemove(src, 'touch.c') - group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) objs = [] diff --git a/bsp/ls1cdev/drivers/board.c b/bsp/ls1cdev/drivers/board.c index a7100a04c43..b4b8403b49c 100644 --- a/bsp/ls1cdev/drivers/board.c +++ b/bsp/ls1cdev/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,13 +29,6 @@ extern void rt_hw_cache_init(void); extern void invalidate_writeback_dcache_all(void); extern void invalidate_icache_all(void); - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - /** * This is the timer interrupt service routine. */ diff --git a/bsp/ls1cdev/drivers/board.h b/bsp/ls1cdev/drivers/board.h index 8124eae7a5a..35c53f2a067 100644 --- a/bsp/ls1cdev/drivers/board.h +++ b/bsp/ls1cdev/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -20,7 +16,7 @@ void rt_hw_board_init(void); /* 32M SDRAM */ -#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024) -#define CPU_HZ (252 * 1000000) +#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024) +#define CPU_HZ (252 * 1000000) #endif diff --git a/bsp/ls1cdev/drivers/display_controller.c b/bsp/ls1cdev/drivers/display_controller.c index a09fe0269f4..d77299b66b5 100644 --- a/bsp/ls1cdev/drivers/display_controller.c +++ b/bsp/ls1cdev/drivers/display_controller.c @@ -1,59 +1,44 @@ /* - * File :display_controller.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes * 2011-08-09 lgnq first version for LS1B DC * 2015-07-06 chinesebear modified for loongson 1c * 2018-01-06 sundm75 modified for smartloong */ + #include -#include #include "display_controller.h" #include "../../libraries/ls1c_pwm.h" #include "../../libraries/ls1c_public.h" #include "../../libraries/ls1c_gpio.h" #include "../../libraries/ls1c_pin.h" -#ifdef RT_USING_RTGUI - +#if (defined PKG_USING_GUIENGINE) || (defined RT_USING_RTGUI) struct vga_struct vga_mode[] = { - {/*"480x272_60.00"*/ 111000, 480, 482, 523, 525, 272, 274, 284, 286, }, - {/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, }, - {/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, }, - {/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, }, - {/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, }, - {/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, }, - {/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, }, - {/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, }, - {/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, }, - {/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, }, - {/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, }, - {/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, }, - {/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, }, - {/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, }, - {/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, }, - {/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, }, - {/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, }, - {/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, }, - {/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, }, + {/*"480x272_60.00"*/ 111000, 480, 482, 523, 525, 272, 274, 284, 286, }, + {/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, }, + {/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, }, + {/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, }, + {/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, }, + {/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, }, + {/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, }, + {/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, }, + {/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, }, + {/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, }, + {/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, }, + {/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, }, + {/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, }, + {/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, }, + {/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, }, + {/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, }, + {/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, }, + {/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, }, + {/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, }, }; ALIGN(16) @@ -64,174 +49,174 @@ static void pwminit(void) { pwm_info_t pwm_info; pwm_info.gpio = LS1C_PWM0_GPIO06; // pwm引脚位gpio06 - pwm_info.mode = PWM_MODE_NORMAL; // 正常模式--连续输出pwm波形 - pwm_info.duty = 0.85; // pwm占空比 85% - pwm_info.period_ns = 5*1000*1000; // pwm周期5ms + pwm_info.mode = PWM_MODE_NORMAL; // 正常模式--连续输出pwm波形 + pwm_info.duty = 0.85; // pwm占空比 85% + pwm_info.period_ns = 5*1000*1000; // pwm周期5ms - /*pwm初始化，初始化后立即产生pwm波形*/ - pwm_init(&pwm_info); + /*pwm初始化，初始化后立即产生pwm波形*/ + pwm_init(&pwm_info); - /* 使能pwm */ - pwm_enable(&pwm_info); + /* 使能pwm */ + pwm_enable(&pwm_info); } int caclulate_freq(rt_uint32_t XIN, rt_uint32_t PCLK) { - rt_uint32_t divider_int; - rt_uint32_t needed_pixclk; - rt_uint32_t pll_clk, pix_div; - rt_uint32_t regval; - - - pll_clk = PLL_FREQ; // 读CPU的 PLL及SDRAM 分频系数 - pll_clk =( pll_clk>>8 )& 0xff; - pll_clk = XIN * pll_clk / 4 ; - pix_div = PLL_DIV_PARAM;//读CPU的 CPU/CAMERA/DC 分频系数 - pix_div = (pix_div>>24)&0xff; - rt_kprintf("old pll_clk=%d, pix_div=%d\n", pll_clk, pix_div); - - divider_int = pll_clk/(1000000) *PCLK/1000; - if(divider_int%1000>=500) - divider_int = divider_int/1000+1; - else - divider_int = divider_int/1000; - rt_kprintf("divider_int = %d\n", divider_int); - - /* check whether divisor is too small. */ - if (divider_int < 1) { - rt_kprintf("Warning: clock source is too slow.Try smaller resolution\n"); - divider_int = 1; - } - else if(divider_int > 100) { - rt_kprintf("Warning: clock source is too fast.Try smaller resolution\n"); - divider_int = 100; - } - /* 配置分频寄存器 */ - { - rt_uint32_t regval = 0; - regval = PLL_DIV_PARAM; - /*首先需要把分频使能位清零 */ - regval &= ~0x80000030; //PIX_DIV_VALID PIX_SEL 置0 - regval &= ~(0x3f<<24); //PIX_DIV 清零 - regval |= divider_int << 24; - PLL_DIV_PARAM = regval; - regval |= 0x80000030; //PIX_DIV_VALID PIX_SEL 置1 - PLL_DIV_PARAM = regval; - } - rt_kprintf("new PLL_FREQ=0x%x, PLL_DIV_PARAM=0x%x\n", PLL_FREQ, PLL_DIV_PARAM); - rt_thread_delay(10); - return 0; + rt_uint32_t divider_int; + rt_uint32_t needed_pixclk; + rt_uint32_t pll_clk, pix_div; + rt_uint32_t regval; + + + pll_clk = PLL_FREQ; // 读CPU的 PLL及SDRAM 分频系数 + pll_clk =( pll_clk>>8 )& 0xff; + pll_clk = XIN * pll_clk / 4 ; + pix_div = PLL_DIV_PARAM;//读CPU的 CPU/CAMERA/DC 分频系数 + pix_div = (pix_div>>24)&0xff; + rt_kprintf("old pll_clk=%d, pix_div=%d\n", pll_clk, pix_div); + + divider_int = pll_clk/(1000000) *PCLK/1000; + if(divider_int%1000>=500) + divider_int = divider_int/1000+1; + else + divider_int = divider_int/1000; + rt_kprintf("divider_int = %d\n", divider_int); + + /* check whether divisor is too small. */ + if (divider_int < 1) { + rt_kprintf("Warning: clock source is too slow.Try smaller resolution\n"); + divider_int = 1; + } + else if(divider_int > 100) { + rt_kprintf("Warning: clock source is too fast.Try smaller resolution\n"); + divider_int = 100; + } + /* 配置分频寄存器 */ + { + rt_uint32_t regval = 0; + regval = PLL_DIV_PARAM; + /*首先需要把分频使能位清零 */ + regval &= ~0x80000030; //PIX_DIV_VALID PIX_SEL 置0 + regval &= ~(0x3f<<24); //PIX_DIV 清零 + regval |= divider_int << 24; + PLL_DIV_PARAM = regval; + regval |= 0x80000030; //PIX_DIV_VALID PIX_SEL 置1 + PLL_DIV_PARAM = regval; + } + rt_kprintf("new PLL_FREQ=0x%x, PLL_DIV_PARAM=0x%x\n", PLL_FREQ, PLL_DIV_PARAM); + rt_thread_delay(10); + return 0; } static rt_err_t rt_dc_init(rt_device_t dev) { - int i, out, mode=-1; - int val; - - rt_kprintf("PWM initied\n"); - /* Set the back light PWM. */ - pwminit(); - - for (i=0; itype = RT_Device_Class_Graphic; - dc->init = rt_dc_init; - dc->open = RT_NULL; - dc->close = RT_NULL; - dc->control = rt_dc_control; - dc->user_data = (void*)&_dc_info; - - /* register Display Controller device to RT-Thread */ - rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR); - - rt_device_init(dc); + rt_device_t dc = rt_malloc(sizeof(struct rt_device)); + if (dc == RT_NULL) + { + rt_kprintf("dc == RT_NULL\n"); + return; /* no memory yet */ + } + + _dc_info.bits_per_pixel = 16; + _dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P; + _dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR; + _dc_info.width = FB_XSIZE; + _dc_info.height = FB_YSIZE; + + /* init device structure */ + dc->type = RT_Device_Class_Graphic; + dc->init = rt_dc_init; + dc->open = RT_NULL; + dc->close = RT_NULL; + dc->control = rt_dc_control; + dc->user_data = (void*)&_dc_info; + + /* register Display Controller device to RT-Thread */ + rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR); + + rt_device_init(dc); } #include diff --git a/bsp/ls1cdev/drivers/display_controller.h b/bsp/ls1cdev/drivers/display_controller.h index ad252a9c2fe..39f6ae8d527 100644 --- a/bsp/ls1cdev/drivers/display_controller.h +++ b/bsp/ls1cdev/drivers/display_controller.h @@ -1,11 +1,7 @@ /* - * File : display_controller.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -20,7 +16,7 @@ #include #include "ls1c.h" -#define DC_BASE 0xBC301240 //Display Controller +#define DC_BASE 0xBC301240 //Display Controller /* Frame Buffer registers */ #define DC_FB_CONFIG __REG32(DC_BASE + 0x000) @@ -51,9 +47,9 @@ struct vga_struct { - long pclk; - int hr,hss,hse,hfl; - int vr,vss,vse,vfl; + long pclk; + int hr,hss,hse,hfl; + int vr,vss,vse,vfl; }; #endif diff --git a/bsp/ls1cdev/drivers/drv_can.c b/bsp/ls1cdev/drivers/drv_can.c index 92095d06699..42745e438b4 100644 --- a/bsp/ls1cdev/drivers/drv_can.c +++ b/bsp/ls1cdev/drivers/drv_can.c @@ -1,21 +1,7 @@ /* - * File : drv_can.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -119,6 +105,7 @@ static rt_err_t setfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_config } return RT_EOK; } + static void bxcan0_filter_init(struct rt_can_device *can) { struct ls1c_bxcan *pbxcan; @@ -249,7 +236,6 @@ static void bxcan1_hw_init(void) } #endif - static rt_err_t configure(struct rt_can_device *can, struct can_configure *cfg) { CAN_TypeDef *pbxcan; @@ -444,7 +430,7 @@ void ls1c_can0_irqhandler(int irq, void *param) rt_kprintf("\r\nCan0 int TX happened!\r\n"); } /*数据溢出中断*/ - else if (( status & CAN_IR_TI) == CAN_IR_DOI) + else if (( status & CAN_IR_DOI) == CAN_IR_DOI) { rt_hw_can_isr(&bxcan0, RT_CAN_EVENT_RXOF_IND); rt_kprintf("\r\nCan0 int RX OF happened!\r\n"); @@ -484,7 +470,7 @@ void ls1c_can1_irqhandler(int irq, void *param) rt_kprintf("\r\nCan1 int TX happened!\r\n"); } /*数据溢出中断*/ - else if (( status & CAN_IR_TI) == CAN_IR_DOI) + else if (( status & CAN_IR_DOI) == CAN_IR_DOI) { rt_hw_can_isr(&bxcan1, RT_CAN_EVENT_RXOF_IND); rt_kprintf("\r\nCan1 int RX OF happened!\r\n"); @@ -515,7 +501,7 @@ int ls1c_bxcan_init(void) rt_kprintf("\r\ncan0 register! \r\n"); rt_hw_interrupt_install(LS1C_CAN0_IRQ,( rt_isr_handler_t)bxcan0data.irq , RT_NULL, "can0"); - rt_hw_interrupt_umask(LS1C_CAN0_IRQ); + rt_hw_interrupt_umask(LS1C_CAN0_IRQ); #endif #ifdef USING_BXCAN1 bxcan1.config.baud_rate = CAN250kBaud; diff --git a/bsp/ls1cdev/drivers/drv_can.h b/bsp/ls1cdev/drivers/drv_can.h index 0d846dee256..7d5d1604d45 100644 --- a/bsp/ls1cdev/drivers/drv_can.h +++ b/bsp/ls1cdev/drivers/drv_can.h @@ -1,21 +1,7 @@ /* - * File : bxcan.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/drv_gpio.c b/bsp/ls1cdev/drivers/drv_gpio.c index 3a21b54a335..5afdae5caaa 100644 --- a/bsp/ls1cdev/drivers/drv_gpio.c +++ b/bsp/ls1cdev/drivers/drv_gpio.c @@ -1,21 +1,7 @@ /* - * File : drv_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/drv_gpio.h b/bsp/ls1cdev/drivers/drv_gpio.h index ab67d9f32ab..33fc0f18ede 100644 --- a/bsp/ls1cdev/drivers/drv_gpio.h +++ b/bsp/ls1cdev/drivers/drv_gpio.h @@ -1,21 +1,7 @@ /* - * File : drv_gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/drv_i2c.c b/bsp/ls1cdev/drivers/drv_i2c.c index 998f0f6ec35..374b625c709 100644 --- a/bsp/ls1cdev/drivers/drv_i2c.c +++ b/bsp/ls1cdev/drivers/drv_i2c.c @@ -1,25 +1,11 @@ /* - * File : drv_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2017-11-14 Ϊ first version + * 2017-11-14 勤为本 first version */ #include @@ -30,8 +16,8 @@ #include "../libraries/ls1c_delay.h" -#define LS1C_I2C_SCL (57) // gpio57 -#define LS1C_I2C_SDA (56) // gpio56 +#define LS1C_I2C_SCL (51) // gpio57 +#define LS1C_I2C_SDA (50) // gpio56 #define LS1C_SET_GPIO_MODE @@ -104,8 +90,8 @@ static const struct rt_i2c_bit_ops bit_ops = { .udelay = ls1c_udelay, - .delay_us = 20, // ֵΪ(us) - .timeout = 10, // λΪtick + .delay_us = 20, // 此值为周期(us) + .timeout = 10, // 单位为tick }; @@ -118,7 +104,7 @@ int ls1c_i2c_init(void) ls1c_i2c_gpio_init(); - rt_i2c_bit_add_bus(&bus, "i2c2"); + rt_i2c_bit_add_bus(&bus, "i2c3"); return RT_EOK; } diff --git a/bsp/ls1cdev/drivers/drv_i2c.h b/bsp/ls1cdev/drivers/drv_i2c.h index 6d07039c2e9..cbacdbb0f53 100644 --- a/bsp/ls1cdev/drivers/drv_i2c.h +++ b/bsp/ls1cdev/drivers/drv_i2c.h @@ -1,34 +1,17 @@ /* - * File : drv_i2c.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2017-11-14 Ϊ first version + * 2017-11-14 勤为本 first version */ #ifndef LS1C_DRV_I2C_H #define LS1C_DRV_I2C_H - int ls1c_i2c_init(void); - - #endif diff --git a/bsp/ls1cdev/drivers/drv_pwm.c b/bsp/ls1cdev/drivers/drv_pwm.c new file mode 100644 index 00000000000..779a7e52b9a --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_pwm.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-04 Sundm75 the first version + */ +#include +#include +#include + +#include +#include + +#include "ls1c.h" +#include "../libraries/ls1c_public.h" +#include "../libraries/ls1c_regs.h" +#include "../libraries/ls1c_clock.h" +#include "../libraries/ls1c_pwm.h" +#include "../libraries/ls1c_pin.h" + +#define PWM_CHANNEL_MAX (4) /* 0-3*/ + +#ifdef RT_USING_PWM + +struct rt_ls1c_pwm +{ + struct rt_device_pwm parent; + + rt_uint32_t period[PWM_CHANNEL_MAX]; + rt_uint32_t pulse[PWM_CHANNEL_MAX]; +}; + +static struct rt_ls1c_pwm _ls1c_pwm_device; + +static rt_err_t set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + rt_err_t result = RT_EOK; + struct rt_ls1c_pwm *ls1c_pwm_device = (struct rt_ls1c_pwm *)device; + + if (configuration->channel > (PWM_CHANNEL_MAX - 1)) + { + result = -RT_EIO; + goto _exit; + } + + rt_kprintf("drv_pwm.c set channel %d: period: %d, pulse: %d\n", configuration->channel, configuration->period, configuration->pulse); + + ls1c_pwm_device->period[configuration->channel] = configuration->period; + ls1c_pwm_device->pulse[configuration->channel] = configuration->pulse; + +_exit: + return result; +} + +static rt_err_t get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + rt_err_t result = RT_EOK; + struct rt_ls1c_pwm *ls1c_pwm_device = (struct rt_ls1c_pwm *)device; + + if (configuration->channel > (PWM_CHANNEL_MAX - 1)) + { + result = -RT_EIO; + goto _exit; + } + + configuration->period = ls1c_pwm_device->period[configuration->channel]; + configuration->pulse = ls1c_pwm_device->pulse[configuration->channel]; + rt_kprintf("drv_pwm.c get channel %d: period: %d, pulse: %d\n", configuration->channel, configuration->period, configuration->pulse); + +_exit: + return result; +} + +static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg) +{ + rt_err_t result = RT_EOK; + struct rt_pwm_configuration * configuration = (struct rt_pwm_configuration *)arg; + + rt_kprintf("drv_pwm.c control cmd: %d. \n", cmd); + + if (cmd == PWM_CMD_ENABLE) + { + rt_kprintf("PWM_CMD_ENABLE\n"); + + pwm_info_t pwm_info; + switch ( configuration->channel) + { + case 0: + pwm_info.gpio = LS1C_PWM0_GPIO06; + //pwm_info.gpio = LS1C_PWM0_GPIO04; + break; + case 1: + pwm_info.gpio = LS1C_PWM1_GPIO92; + //pwm_info.gpio = LS1C_PWM1_GPIO05; + break; + case 2: + pwm_info.gpio = LS1C_PWM2_GPIO52; + //pwm_info.gpio = LS1C_PWM2_GPIO46; + break; + case 3: + pwm_info.gpio = LS1C_PWM3_GPIO47; + //pwm_info.gpio = LS1C_PWM3_GPIO53; + break; + default: + break; + } + pwm_info.mode = PWM_MODE_NORMAL; + pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period ); + pwm_info.period_ns = configuration->period; + pwm_init(&pwm_info); + pwm_enable(&pwm_info); + } + else if (cmd == PWM_CMD_DISABLE) + { + rt_kprintf("PWM_CMD_DISABLE\n"); + pwm_info_t pwm_info; + switch ( configuration->channel) + { + case 0: + pwm_info.gpio = LS1C_PWM0_GPIO06; + //pwm_info.gpio = LS1C_PWM0_GPIO04; + break; + case 1: + pwm_info.gpio = LS1C_PWM1_GPIO92; + //pwm_info.gpio = LS1C_PWM1_GPIO05; + break; + case 2: + pwm_info.gpio = LS1C_PWM2_GPIO52; + //pwm_info.gpio = LS1C_PWM2_GPIO46; + break; + case 3: + pwm_info.gpio = LS1C_PWM3_GPIO47; + //pwm_info.gpio = LS1C_PWM3_GPIO53; + break; + default: + break; + } + pwm_info.mode = PWM_MODE_NORMAL; + pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period ); + pwm_info.period_ns = configuration->period; + pwm_init(&pwm_info); + pwm_disable(&pwm_info); + } + else if (cmd == PWM_CMD_SET) + { + rt_kprintf("PWM_CMD_SET\n"); + result = set(device, (struct rt_pwm_configuration *)arg); + } + else if (cmd == PWM_CMD_GET) + { + rt_kprintf("PWM_CMD_GET\n"); + result = get(device, (struct rt_pwm_configuration *)arg); + } + + return result; +} + +static const struct rt_pwm_ops pwm_ops = +{ + control, +}; + +int rt_hw_pwm_init(void) +{ + int ret = RT_EOK; + + /* add pwm initial. */ + + ret = rt_device_pwm_register(&_ls1c_pwm_device.parent, "pwm", &pwm_ops, RT_NULL); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif /*RT_USING_PWM*/ diff --git a/bsp/ls1cdev/drivers/drv_pwm.h b/bsp/ls1cdev/drivers/drv_pwm.h new file mode 100644 index 00000000000..427ba0c6194 --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_pwm.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-04 Sundm75 the first version + */ + +#ifndef LS1C_DRV_PWM_H +#define LS1C_DRV_PWM_H + +int ls1c_pwm_init(void); + +#endif /*DRV_CAN_H_*/ diff --git a/bsp/ls1cdev/drivers/drv_rtc.c b/bsp/ls1cdev/drivers/drv_rtc.c new file mode 100644 index 00000000000..0569992c61b --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_rtc.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-05 sundm75 first version + */ + +/* Includes ------------------------------------------------------------------*/ +#include "board.h" +#include "drv_rtc.h" +#include + +#include "../libraries/ls1c_regs.h" +#include "../libraries/ls1c_rtc.h" + +//#define RT_RTC_DEBUG + +#if defined(RT_USING_RTC) +#ifdef RT_RTC_DEBUG +#define rtc_debug(format,args...) rt_kprintf(format, ##args) +#else +#define rtc_debug(format,args...) +#endif + +static struct rt_device rtc; + +RTC_TypeDef * RTC_Handler; + +static time_t get_timestamp(void) +{ + struct tm tm_new = {0}; + RTC_TimeTypeDef rtcDate; + + RTC_GetTime(RTC_Handler, &rtcDate); + + tm_new.tm_sec = rtcDate.Seconds; + tm_new.tm_min = rtcDate.Minutes; + tm_new.tm_hour = rtcDate.Hours; + + tm_new.tm_mday = rtcDate.Date; + tm_new.tm_mon = rtcDate.Month- 1; + tm_new.tm_year = rtcDate.Year + 2000 - 1900; + + return mktime(&tm_new); +} + +static int set_timestamp(time_t timestamp) +{ + struct tm *p_tm; + RTC_TimeTypeDef rtcDate; + + p_tm = localtime(×tamp); + + rtcDate.Seconds= p_tm->tm_sec ; + rtcDate.Minutes= p_tm->tm_min ; + rtcDate.Hours= p_tm->tm_hour; + + rtcDate.Date= p_tm->tm_mday; + rtcDate.Month= p_tm->tm_mon + 1; + rtcDate.Year= p_tm->tm_year + 1900 - 2000; + + RTC_SetTime(RTC_Handler, &rtcDate); + rt_kprintf("\r\nrtcDate is %d.%d.%d - %d:%d:%d",rtcDate.Year, rtcDate.Month, rtcDate.Date, rtcDate.Hours, rtcDate.Minutes, rtcDate.Seconds); + return RT_EOK; +} + +rt_uint8_t RTC_Init(void) +{ + RTC_Handler = RTC; + return 0; +} + +static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + if (dev->rx_indicate != RT_NULL) + { + /* Open Interrupt */ + } + + return RT_EOK; +} + +static rt_size_t rt_rtc_read( + rt_device_t dev, + rt_off_t pos, + void* buffer, + rt_size_t size) +{ + + return 0; +} + + /** + * This function configure RTC device. + * + * @param dev, pointer to device descriptor. + * @param cmd, RTC control command. + * + * @return the error code. + */ +static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t result; + RT_ASSERT(dev != RT_NULL); + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + + *(rt_uint32_t *)args = get_timestamp(); + rtc_debug("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + { + result = set_timestamp(*(rt_uint32_t *)args); + rtc_debug("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); + } + break; + } + + return result; +} + + /** + * This function register RTC device. + * + * @param device, pointer to device descriptor. + * @param name, device name. + * @param flag, configuration flags. + * + * @return the error code. + */ +rt_err_t rt_hw_rtc_register( + rt_device_t device, + const char *name, + rt_uint32_t flag) +{ + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_RTC; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = RT_NULL; + device->open = rt_rtc_open; + device->close = RT_NULL; + device->read = rt_rtc_read; + device->write = RT_NULL; + device->control = rt_rtc_control; + device->user_data = RT_NULL; /* no private */ + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); +} + + /** + * This function initialize RTC module related hardware and register RTC device to kernel. + * + * @param none. + * + * @return the error code. + */ +int rt_hw_rtc_init(void) +{ + RTC_Init(); + /* register rtc device */ + rt_hw_rtc_register(&rtc, RT_RTC_NAME, 0); + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_rtc_init); +#endif + + + + diff --git a/bsp/ls1cdev/drivers/drv_rtc.h b/bsp/ls1cdev/drivers/drv_rtc.h new file mode 100644 index 00000000000..cea8ebe6330 --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_rtc.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-05 sundm75 first version + */ + +#ifndef __DRV_RTC_H__ +#define __DRV_RTC_H__ + +#include +#include + +int rt_hw_rtc_init(void); + +#endif diff --git a/bsp/ls1cdev/drivers/drv_spi.h b/bsp/ls1cdev/drivers/drv_spi.h index 94fbb580974..8b1aa315be5 100644 --- a/bsp/ls1cdev/drivers/drv_spi.h +++ b/bsp/ls1cdev/drivers/drv_spi.h @@ -1,25 +1,11 @@ /* - * File : drv_spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2017-11-02 Ϊ first version + * 2017-11-02 勤为本 first version */ #ifndef LS1C_DRV_SPI_H @@ -43,9 +29,9 @@ struct ls1c_spi_cs /* - * ʼעо1cspi - * @SPI SPIߣLS1C_SPI_0 LS1C_SPI_1 - * @spi_bus_name + * 初始化并注册龙芯1c的spi总线 + * @SPI SPI总线，比如LS1C_SPI_0， LS1C_SPI_1 + * @spi_bus_name 总线名字 * @ret */ rt_err_t ls1c_spi_bus_register(rt_uint8_t SPI, const char *spi_bus_name); diff --git a/bsp/ls1cdev/drivers/drv_touch.c b/bsp/ls1cdev/drivers/drv_touch.c new file mode 100644 index 00000000000..e4fc69967e3 --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_touch.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-02-08 Zhangyihong the first version + */ + +#include +#include + +#include + +#include "drv_touch.h" +#ifdef TINA_USING_TOUCH +#if (defined PKG_USING_GUIENGINE) || (defined RT_USING_RTGUI) +#include +#include +#endif +#define BSP_TOUCH_SAMPLE_HZ (50) +static rt_list_t driver_list; + +extern void touch_down(void); +extern void touch_mo(void); +extern void touch_up(void); + +void rt_touch_drivers_register(touch_drv_t drv) +{ + rt_list_insert_before(&driver_list, &drv->list); +} + +static void post_down_event(rt_uint16_t x, rt_uint16_t y, rt_tick_t ts) +{ +#if (defined PKG_USING_GUIENGINE) || (defined RT_USING_RTGUI) + struct rtgui_event_mouse emouse; + + emouse.parent.sender = RT_NULL; + emouse.wid = RT_NULL; + + emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; + emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_DOWN; + emouse.x = x; + emouse.y = y; +#ifdef PKG_USING_GUIENGINE + emouse.ts = rt_tick_get(); + emouse.id = ts; +#endif + rtgui_server_post_event(&emouse.parent, sizeof(emouse)); + rt_kprintf("touch down x:%d,y%d,id:%d\r\n", x, y, ts); + touch_down(); +#endif +} + +static void post_motion_event(rt_uint16_t x, rt_uint16_t y, rt_tick_t ts) +{ +#if (defined PKG_USING_GUIENGINE) || (defined RT_USING_RTGUI) + struct rtgui_event_mouse emouse; + + emouse.parent.sender = RT_NULL; + emouse.wid = RT_NULL; + + emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_DOWN; + emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION; + emouse.x = x; + emouse.y = y; +#ifdef PKG_USING_GUIENGINE + emouse.ts = rt_tick_get(); + emouse.id = ts; +#endif + rtgui_server_post_event(&emouse.parent, sizeof(emouse)); + rt_kprintf("touch motion x:%d,y%d,id:%d\r\n", x, y, ts); + touch_mo(); +#endif +} + +static void post_up_event(rt_uint16_t x, rt_uint16_t y, rt_tick_t ts) +{ +#if (defined PKG_USING_GUIENGINE) || (defined RT_USING_RTGUI) + struct rtgui_event_mouse emouse; + + emouse.parent.sender = RT_NULL; + emouse.wid = RT_NULL; + + emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; + emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_UP; + emouse.x = x; + emouse.y = y; +#ifdef PKG_USING_GUIENGINE + emouse.ts = rt_tick_get(); + emouse.id = ts; +#endif + rtgui_server_post_event(&emouse.parent, sizeof(emouse)); + rt_kprintf("touch up x:%d,y%d,id:%d\r\n", x, y, ts); + touch_up(); +#endif +} + +static void touch_thread_entry(void *parameter) +{ + touch_drv_t touch = (touch_drv_t)parameter; + struct touch_message msg; + rt_tick_t emouse_id = 0; + touch->ops->isr_enable(RT_TRUE); + while (1) + { + + if (rt_sem_take(touch->isr_sem, RT_WAITING_FOREVER) != RT_EOK) + { + continue; + } + if (touch->ops->read_point(&msg) != RT_EOK) + { + touch->ops->isr_enable(RT_TRUE); + continue; + } + switch (msg.event) + { + case TOUCH_EVENT_UP: + post_up_event(msg.x, msg.y, emouse_id); + break; + case TOUCH_EVENT_DOWN: + emouse_id = rt_tick_get(); + post_down_event(msg.x, msg.y, emouse_id); + break; + case TOUCH_EVENT_MOVE: + post_motion_event(msg.x, msg.y, emouse_id); + break; + default: + break; + } + rt_thread_delay(RT_TICK_PER_SECOND / BSP_TOUCH_SAMPLE_HZ); + touch->ops->isr_enable(RT_TRUE); + } +} + +int rt_touch_driver_init(void) +{ + rt_kprintf("\r\n%s \r\n", __FUNCTION__); + rt_list_init(&driver_list); + return 0; +} +INIT_BOARD_EXPORT(rt_touch_driver_init); + +static struct rt_i2c_bus_device *i2c_bus = RT_NULL; +static int rt_touch_thread_init(void) +{ + rt_list_t *l; + touch_drv_t current_driver; + rt_thread_t tid = RT_NULL; + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find("i2c1"); + RT_ASSERT(i2c_bus); + current_driver = RT_NULL; + if (rt_device_open((rt_device_t)i2c_bus, RT_DEVICE_OFLAG_RDWR) != RT_EOK) + return -1; + for (l = driver_list.next; l != &driver_list; l = l->next) + { + if (rt_list_entry(l, struct touch_drivers, list)->probe(i2c_bus)) + { + current_driver = rt_list_entry(l, struct touch_drivers, list); + break; + } + } + if (current_driver == RT_NULL) + { + rt_kprintf("no touch screen or do not have driver\r\n"); + rt_device_close((rt_device_t)i2c_bus); + return -1; + } + current_driver->ops->init(i2c_bus); + rt_kprintf("touch screen found driver\r\n"); + tid = rt_thread_create("touch", touch_thread_entry, current_driver, 2048, 27, 20); + if (tid == RT_NULL) + { + current_driver->ops->deinit(); + rt_device_close((rt_device_t)i2c_bus); + return -1; + } + rt_thread_startup(tid); + return 0; +} + +static void touch_init_thread_entry(void *parameter) +{ + rt_touch_thread_init(); +} +static int touc_bg_init(void) +{ + rt_thread_t tid = RT_NULL; + tid = rt_thread_create("touchi", touch_init_thread_entry, RT_NULL, 2048, 28, 20); + if (tid == RT_NULL) + { + return -1; + } + rt_thread_startup(tid); + return 0; +} +INIT_APP_EXPORT(touc_bg_init); + + +#endif diff --git a/bsp/ls1cdev/drivers/drv_touch.h b/bsp/ls1cdev/drivers/drv_touch.h new file mode 100644 index 00000000000..ffb7cbadb6b --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_touch.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-02-08 Zhangyihong the first version + */ +#ifndef __DRV_TOUCH_H__ +#define __DRV_TOUCH_H__ + +#include "rtthread.h" +#include "rtdevice.h" + +#define TOUCH_EVENT_UP (0x01) +#define TOUCH_EVENT_DOWN (0x02) +#define TOUCH_EVENT_MOVE (0x03) +#define TOUCH_EVENT_NONE (0x80) + +struct touch_message +{ + rt_uint16_t x; + rt_uint16_t y; + rt_uint8_t event; +}; +typedef struct touch_message *touch_msg_t; + +struct touch_ops +{ + void (* isr_enable)(rt_bool_t); + rt_err_t (* read_point)(touch_msg_t); + void (* init)(struct rt_i2c_bus_device *); + void (* deinit)(void); +}; +typedef struct touch_ops *touch_ops_t; + +struct touch_drivers +{ + rt_list_t list; + unsigned char address; + rt_bool_t (*probe)(struct rt_i2c_bus_device *i2c_bus); + rt_sem_t isr_sem; + touch_ops_t ops; + void *user_data; +}; +typedef struct touch_drivers *touch_drv_t; + +extern void rt_touch_drivers_register(touch_drv_t drv); + +#endif diff --git a/bsp/ls1cdev/drivers/drv_touch_gt9xx.c b/bsp/ls1cdev/drivers/drv_touch_gt9xx.c new file mode 100644 index 00000000000..3a6f9de5cd4 --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_touch_gt9xx.c @@ -0,0 +1,408 @@ +/* + * File : drv_touch_gt9xx.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2018-02-08 Zhangyihong the first version + * 2018-04-03 XY gt9xx for 1024 * 600 + * 2018-10-11 sundm75 ls1c for 480 * 272 + */ +#include "rtthread.h" + +#include "drv_touch.h" +#include "string.h" +#include "ls1c_gpio.h" +#include "ls1c.h" +#include "ls1c_pin.h" + +#ifdef TINA_USING_TOUCH + +#define TP_INT_PIN (89) +#define TP_RESET_PIN (87) +#define LED_PIN (52) + + +#define gt9xx_READ_XY_REG 0x814E /* 坐标寄存器 当前检测到的触摸情况 */ +#define gt9xx_CLEARBUF_REG 0x814E /* 清除坐标寄存器 */ +#define gt9xx_CONFIG_REG 0x8047 /* 配置参数寄存器 */ +#define gt9xx_COMMAND_REG 0x8040 /* 实时命令 */ +#define gt9xx_PRODUCT_ID_REG 0x8140 /* productid */ +#define gt9xx_VENDOR_ID_REG 0x814A /* 当前模组选项信息 */ +#define gt9xx_CONFIG_VERSION_REG 0x8047 /* 配置文件版本号 */ +#define gt9xx_CONFIG_CHECKSUM_REG 0x80FF /* 配置文件校验码 */ +#define gt9xx_FIRMWARE_VERSION_REG 0x8144 /* 固件版本号 */ + +#define IIC_RETRY_NUM 1 + +void touch_down(void); +void touch_mo(void); +void touch_up(void); + +static struct rt_i2c_bus_device *gt9xx_i2c_bus; +static void gt9xx_isr_enable(rt_bool_t enable); +static rt_err_t gt9xx_read_point(touch_msg_t msg); +static void gt9xx_init(struct rt_i2c_bus_device *i2c_bus); +static void gt9xx_deinit(void); +static int gt9xx_read_xy(void); + +static gpio_direction_output( int pin, int level) +{ + gpio_init(pin, gpio_mode_output); + gpio_set(pin, level); +} +static gpio_direction_input(int pin) +{ + gpio_init(pin, gpio_mode_input); +} +static gpio_irq_enable( int pin) +{ + int touch_irq = LS1C_GPIO_TO_IRQ(TP_INT_PIN); + rt_hw_interrupt_umask(touch_irq); +} +static gpio_irq_disable(int pin) +{ + int touch_irq = LS1C_GPIO_TO_IRQ(TP_INT_PIN); + rt_hw_interrupt_mask(touch_irq); +} +static gpio_set_value(int pin, int level) +{ + gpio_set(pin, level); +} +struct touch_ops gt9xx_ops = +{ + gt9xx_isr_enable, + gt9xx_read_point, + gt9xx_init, + gt9xx_deinit, +}; + +static struct touch_drivers gt9xx_driver; +extern struct lcd_config lcd_config; + +static rt_uint8_t gt9xx_config[186]; + +static int gt9xx_read(struct rt_i2c_bus_device *i2c_bus, rt_uint16_t addr, rt_uint8_t *buffer, rt_size_t length) +{ + int ret = -1; + int retries = 0; + rt_uint8_t tmp_buf[2]; + + struct rt_i2c_msg msgs[] = + { + { + .addr = gt9xx_driver.address, + .flags = RT_I2C_WR, + .len = 2, + .buf = tmp_buf, + }, + { + .addr = gt9xx_driver.address, + .flags = RT_I2C_RD, + .len = length, + .buf = buffer, + }, + }; + + tmp_buf[0] = (rt_uint8_t)(addr >> 8); + tmp_buf[1] = (rt_uint8_t)(addr); + + while (retries < IIC_RETRY_NUM) + { + ret = rt_i2c_transfer(i2c_bus, msgs, 2); + ret = rt_i2c_transfer(i2c_bus, msgs, 2); + ret = rt_i2c_transfer(i2c_bus, msgs, 2); + ret = rt_i2c_transfer(i2c_bus, msgs, 2); + if (ret == 2)break; + retries++; + } + + if (retries >= IIC_RETRY_NUM) + { + rt_kprintf("%s i2c read error: %d\n", __func__, ret); + return -1; + } + + return ret; +} + +static void gt9xx_write(struct rt_i2c_bus_device *i2c_bus, rt_uint16_t addr, rt_uint8_t *buffer, rt_size_t length) +{ + + rt_uint8_t *send_buffer = rt_malloc(length + 2); + + RT_ASSERT(send_buffer); + + send_buffer[0] = (rt_uint8_t)(addr >> 8); + send_buffer[1] = (rt_uint8_t)(addr); + memcpy(send_buffer + 2, buffer, length); + + struct rt_i2c_msg msgs[] = + { + { + .addr = gt9xx_driver.address, + .flags = RT_I2C_WR, + .len = length + 2, + .buf = send_buffer, + } + }; + + length = rt_i2c_transfer(i2c_bus, msgs, 1); + rt_free(send_buffer); + send_buffer = RT_NULL; +} + +static void gt9xx_isr_enable(rt_bool_t enable) +{ + if (enable) + { + gpio_irq_enable( TP_INT_PIN); + } + else + { + gpio_irq_disable( TP_INT_PIN); + } +} + +static rt_err_t gt9xx_read_point(touch_msg_t msg) +{ + rt_uint8_t buf[8]; + rt_uint8_t clean = 0; + static rt_uint8_t s_tp_down = 0; + + gt9xx_read(gt9xx_i2c_bus, gt9xx_READ_XY_REG, buf, 8); + gt9xx_write(gt9xx_i2c_bus, gt9xx_CLEARBUF_REG, &clean, 1); + if ((buf[0] & 0x80) == 0) + { + if (s_tp_down) + { + s_tp_down = 0; + msg->event = TOUCH_EVENT_UP; + return RT_EOK; + } + msg->event = TOUCH_EVENT_NONE; + return RT_EOK; + } + msg->x = ((rt_uint16_t)buf[3] << 8) | buf[2]; + msg->y = ((rt_uint16_t)buf[5] << 8) | buf[4]; + if (s_tp_down) + { + msg->event = TOUCH_EVENT_MOVE; + return RT_EOK; + } + msg->event = TOUCH_EVENT_DOWN; + s_tp_down = 1; + + return RT_EOK; +} + +void gt9xx_touch_isr(int irq, void *param) +{ + gpio_irq_disable(TP_INT_PIN); + rt_sem_release(gt9xx_driver.isr_sem); +} + +static void gt9xx_set_address(rt_uint8_t address) +{ + pin_set_purpose(TP_INT_PIN, PIN_PURPOSE_OTHER); + pin_set_purpose(TP_RESET_PIN, PIN_PURPOSE_OTHER); + gpio_direction_output( TP_INT_PIN, 0); + gpio_direction_output( TP_RESET_PIN, 0); + if (address == 0x5D) + { + rt_thread_delay(30); + gpio_set_value( TP_RESET_PIN, 1); + rt_thread_delay(300); + pin_set_purpose(TP_INT_PIN, PIN_PURPOSE_OTHER); + gpio_direction_input(TP_INT_PIN); + rt_thread_delay(10); + } + else + { + gpio_set_value( TP_INT_PIN, 1); + gpio_set_value( TP_RESET_PIN, 0); + rt_thread_delay(30); + gpio_set_value( TP_RESET_PIN, 1); + gpio_set_value( TP_INT_PIN, 1); + rt_thread_delay(30); + gpio_set_value( TP_INT_PIN, 0); + rt_thread_delay(30); + gpio_set_value( TP_INT_PIN, 1); + } +} + +static void gt9xx_soft_reset(struct rt_i2c_bus_device *i2c_bus) +{ + rt_uint8_t buf = 2; + gt9xx_write(i2c_bus, gt9xx_COMMAND_REG, &buf, 1); +} + +static void gt9xx_init(struct rt_i2c_bus_device *i2c_bus) +{ + rt_uint8_t id = 0; + int touch_irq = LS1C_GPIO_TO_IRQ(TP_INT_PIN); + + gt9xx_driver.isr_sem = rt_sem_create("gt9xx", 0, RT_IPC_FLAG_FIFO); + RT_ASSERT(gt9xx_driver.isr_sem); + + gt9xx_i2c_bus = i2c_bus; + gt9xx_set_address(gt9xx_driver.address); + + gt9xx_read(i2c_bus, gt9xx_CONFIG_VERSION_REG, &id, 1); + rt_kprintf("\r\nGT9xx Config version:0x%02X\r\n", id); + + gt9xx_read(i2c_bus, gt9xx_VENDOR_ID_REG, &id, 1); + rt_kprintf("\r\nGT9xx sensor id:0x%02X\r\n", id); + + gpio_set_irq_type( TP_INT_PIN, IRQ_TYPE_EDGE_RISING); + gpio_irq_disable( TP_INT_PIN); + + rt_hw_interrupt_install(touch_irq, gt9xx_touch_isr, RT_NULL, "touch"); + + rt_thread_delay(RT_TICK_PER_SECOND / 5); + gpio_init(LED_PIN, gpio_mode_output); +} + +static int gt9xx_write_config(void) +{ + int i; + rt_uint8_t config_checksum = 0; + gt9xx_set_address(gt9xx_driver.address); + //Add sth... + gt9xx_config[5] = 0x05; + gt9xx_config[6] = 0x0C; + for (i = 0; i < sizeof(gt9xx_config) - 2; i++) + { + config_checksum += gt9xx_config[i]; + } + gt9xx_config[184] = (~config_checksum) + 1; + gt9xx_config[185] = 0x01; + gt9xx_write(gt9xx_i2c_bus, gt9xx_CONFIG_REG, gt9xx_config, sizeof(gt9xx_config)); + return 0; +} +MSH_CMD_EXPORT(gt9xx_write_config,please read first); + +static int gt9xx_read_config(void) +{ + int i; + rt_uint8_t buf[8]; + rt_uint8_t clean = 0; + gt9xx_read(gt9xx_i2c_bus, gt9xx_CONFIG_VERSION_REG, gt9xx_config, sizeof(gt9xx_config)); + gt9xx_config[sizeof(gt9xx_config)-1] = 1; + + rt_kprintf("\n"); + for(i = 0; i < sizeof(gt9xx_config); i++) + { + rt_kprintf("0x%02X,",gt9xx_config[i]); + if((i+1)%8 == 0) + { + rt_kprintf("\n"); + } + } + rt_kprintf("\n"); + return 0; +} +MSH_CMD_EXPORT(gt9xx_read_config,read gt9xx config); +static int gt9xx_read_xy(void) +{ + int i; + rt_uint8_t buf[8]; + rt_uint8_t clean = 0; + rt_uint16_t x,y; + + gt9xx_read(gt9xx_i2c_bus, gt9xx_READ_XY_REG, buf, 8); + gt9xx_write(gt9xx_i2c_bus, gt9xx_CLEARBUF_REG, &clean, 1); + x = ((rt_uint16_t)buf[3] << 8) | buf[2]; + y = ((rt_uint16_t)buf[5] << 8) | buf[4]; + rt_kprintf("\n814e= 0x%02x; 814f= 0x%02x;\n x1 : %d, y1 : %d\n", buf[0], buf[1], x, y); + + rt_kprintf("\n"); + return 0; +} +MSH_CMD_EXPORT(gt9xx_read_xy,read gt9xx xy); + +static rt_bool_t gt9xx_probe(struct rt_i2c_bus_device *i2c_bus) +{ + rt_uint8_t buffer[5] = { 0 }; + + gt9xx_set_address(gt9xx_driver.address); + gt9xx_soft_reset(i2c_bus); + rt_thread_delay(10); + gt9xx_read(i2c_bus, gt9xx_PRODUCT_ID_REG, buffer, 4); + buffer[4] = '\0'; + if (buffer[0] == '9' && buffer[1] == '1' && buffer[2] == '1') + { + rt_kprintf("Found chip gt911\r\n"); + return RT_TRUE; + } + else if (buffer[0] == '9' && buffer[1] == '1' && buffer[2] == '4' && buffer[3] == '7') + { + rt_kprintf("Found chip gt9147\r\n"); + return RT_TRUE; + } + else if (buffer[0] == '9' && buffer[1] == '1' && buffer[2] == '5' && buffer[3] == '7') + { + rt_kprintf("Found chip gt9157\r\n"); + return RT_TRUE; + } + else + { + rt_kprintf("Uknow chip :"); + rt_kprintf("%d%d%d%d\r\n",buffer[0], buffer[1] , buffer[2], buffer[3]); + return RT_TRUE; + } + return RT_FALSE; +} + +static void gt9xx_deinit(void) +{ + rt_sem_delete(gt9xx_driver.isr_sem); +} + +static int gt9xx_driver_register(void) +{ + rt_kprintf("\r\n%s \r\n", __FUNCTION__); + gt9xx_driver.address = 0x5D; + gt9xx_driver.probe = gt9xx_probe; + gt9xx_driver.ops = >9xx_ops; + gt9xx_driver.user_data = RT_NULL; + rt_touch_drivers_register(>9xx_driver); + return 0; +} +INIT_ENV_EXPORT(gt9xx_driver_register); + +void touch_down(void) +{ + gpio_set(LED_PIN, gpio_level_low); +} + +void touch_mo(void) +{ + if (0 == (gpio_get(LED_PIN))) + gpio_set(LED_PIN, gpio_level_high); + else + gpio_set(LED_PIN, gpio_level_low); +} + +void touch_up(void) +{ + gpio_set(LED_PIN, gpio_level_high); +} + + +#endif diff --git a/bsp/ls1cdev/drivers/drv_uart.c b/bsp/ls1cdev/drivers/drv_uart.c index de0fe1f852e..4abca756543 100644 --- a/bsp/ls1cdev/drivers/drv_uart.c +++ b/bsp/ls1cdev/drivers/drv_uart.c @@ -1,21 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -131,7 +117,7 @@ static void uart_irq_handler(int vector, void *param) } -static const struct rt_uart_ops stm32_uart_ops = +static const struct rt_uart_ops ls1c_uart_ops = { ls1c_uart_configure, ls1c_uart_control, @@ -146,6 +132,15 @@ struct rt_uart_ls1c uart2 = LS1C_UART2_IRQ, }; struct rt_serial_device serial2; +#endif /* RT_USING_UART2 */ + +#if defined(RT_USING_UART1) +struct rt_uart_ls1c uart1 = +{ + LS1C_UART1, + LS1C_UART1_IRQ, +}; +struct rt_serial_device serial1; #endif /* RT_USING_UART1 */ void rt_hw_uart_init(void) @@ -156,7 +151,7 @@ void rt_hw_uart_init(void) #ifdef RT_USING_UART2 uart = &uart2; - serial2.ops = &stm32_uart_ops; + serial2.ops = &ls1c_uart_ops; serial2.config = config; pin_set_purpose(36, PIN_PURPOSE_OTHER); @@ -166,12 +161,34 @@ void rt_hw_uart_init(void) rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial2, "UART2"); - /* register UART1 device */ + /* register UART2 device */ rt_hw_serial_register(&serial2, "uart2", //RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); +#endif /* RT_USING_UART2 */ + +#ifdef RT_USING_UART1 + uart = &uart1; + + serial1.ops = &ls1c_uart_ops; + serial1.config = config; + + pin_set_purpose(2, PIN_PURPOSE_OTHER); + pin_set_purpose(3, PIN_PURPOSE_OTHER); + pin_set_remap(2, PIN_REMAP_FOURTH); + pin_set_remap(3, PIN_REMAP_FOURTH); + + rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial1, "UART1"); + + /* register UART1 device */ + rt_hw_serial_register(&serial1, + "uart1", + //RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); #endif /* RT_USING_UART1 */ + } diff --git a/bsp/ls1cdev/drivers/drv_uart.h b/bsp/ls1cdev/drivers/drv_uart.h index 2c6553bffdc..4e3fb631944 100644 --- a/bsp/ls1cdev/drivers/drv_uart.h +++ b/bsp/ls1cdev/drivers/drv_uart.h @@ -1,21 +1,7 @@ /* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/hw_i2c.c b/bsp/ls1cdev/drivers/hw_i2c.c index 6d427701ed4..1f63df1ab99 100644 --- a/bsp/ls1cdev/drivers/hw_i2c.c +++ b/bsp/ls1cdev/drivers/hw_i2c.c @@ -1,24 +1,10 @@ /* - * File :hw_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes * 2018-01-04 Sundm75 the first version */ @@ -40,31 +26,31 @@ rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus, rt_uint32_t num) { struct ls1c_i2c_bus * i2c_bus = (struct ls1c_i2c_bus *)bus; - ls1c_i2c_info_t i2c_info; + ls1c_i2c_info_t i2c_info; struct rt_i2c_msg *msg; int i; rt_int32_t ret = RT_EOK; i2c_info.clock = 50000; // 50kb/s - i2c_info.I2Cx = i2c_bus->u32Module; - i2c_init(&i2c_info); - + i2c_info.I2Cx = i2c_bus->u32Module; + i2c_init(&i2c_info); + for (i = 0; i < num; i++) { msg = &msgs[i]; if (msg->flags == RT_I2C_RD) { - i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_READ); - i2c_receive_ack(&i2c_info); - i2c_receive_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); - i2c_send_stop(&i2c_info); - } + i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_READ); + i2c_receive_ack(&i2c_info); + i2c_receive_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); + i2c_send_stop(&i2c_info); + } else if(msg->flags == RT_I2C_WR) { - i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_WRITE); - i2c_receive_ack(&i2c_info); - i2c_send_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); - i2c_send_stop(&i2c_info); - } + i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_WRITE); + i2c_receive_ack(&i2c_info); + i2c_send_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); + i2c_send_stop(&i2c_info); + } ret++; } return ret; diff --git a/bsp/ls1cdev/drivers/hw_i2c.h b/bsp/ls1cdev/drivers/hw_i2c.h index 1bd4e991ede..cc3e25506f7 100644 --- a/bsp/ls1cdev/drivers/hw_i2c.h +++ b/bsp/ls1cdev/drivers/hw_i2c.h @@ -1,21 +1,7 @@ /* - * File : hw_i2c.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/SConscript b/bsp/ls1cdev/drivers/net/SConscript index 1eea3171de6..7e5532099ef 100644 --- a/bsp/ls1cdev/drivers/net/SConscript +++ b/bsp/ls1cdev/drivers/net/SConscript @@ -5,6 +5,12 @@ src = Glob('*.c') CPPPATH = [cwd] +if GetDepend('RT_USING_LWIP') == False: + SrcRemove(src, 'mii.c') + SrcRemove(src, 'synopGMAC.c') + SrcRemove(src, 'synopGMAC_Dev.c') + SrcRemove(src, 'synopGMAC_plat.c') + group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/ls1cdev/drivers/net/mii.c b/bsp/ls1cdev/drivers/net/mii.c index b53592f87ef..43ade097cf4 100644 --- a/bsp/ls1cdev/drivers/net/mii.c +++ b/bsp/ls1cdev/drivers/net/mii.c @@ -1,21 +1,7 @@ /* - * File : mii.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/mii.h b/bsp/ls1cdev/drivers/net/mii.h index cbdd3d5cef5..24563834ec4 100644 --- a/bsp/ls1cdev/drivers/net/mii.h +++ b/bsp/ls1cdev/drivers/net/mii.h @@ -1,21 +1,7 @@ /* - * File : mii.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/synopGMAC.c b/bsp/ls1cdev/drivers/net/synopGMAC.c index 3ddc1af583b..8fe991e538d 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC.c +++ b/bsp/ls1cdev/drivers/net/synopGMAC.c @@ -1,21 +1,7 @@ /* - * File : synopGMAC.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/synopGMAC.h b/bsp/ls1cdev/drivers/net/synopGMAC.h index d4d06e6a65f..e244c148929 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC.h @@ -1,21 +1,7 @@ /* - * File : synopGMAC.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_Dev.c b/bsp/ls1cdev/drivers/net/synopGMAC_Dev.c index 6c5b4a2cdea..a41038f35ce 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_Dev.c +++ b/bsp/ls1cdev/drivers/net/synopGMAC_Dev.c @@ -1,33 +1,7 @@ -/** \file - * This file defines the synopsys GMAC device dependent functions. - * Most of the operations on the GMAC device are available in this file. - * Functions for initiliasing and accessing MAC/DMA/PHY registers and the DMA descriptors - * are encapsulated in this file. The functions are platform/host/OS independent. - * These functions in turn use the low level device dependent (HAL) functions to - * access the register space. - * \internal - * ------------------------REVISION HISTORY--------------------------------- - * Synopsys 01/Aug/2007 Created - */ - /* - * File : synopGMAC_Dev.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h b/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h index 25c7814a16e..74bc850d865 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_Dev.h @@ -1,32 +1,7 @@ -/**\file - * This file defines the function prototypes for the Synopsys GMAC device and the - * Marvell 88E1011/88E1011S integrated 10/100/1000 Gigabit Ethernet Transceiver. - * Since the phy register mapping are standardised, the phy register map and the - * bit definitions remain the same for other phy as well. - * This also defines some of the Ethernet related parmeters. - * \internal - * -----------------------------REVISION HISTORY------------------------------------ - * Synopsys 01/Aug/2007 Created - */ - /* - * File : synopGMAC_Dev.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_Host.h b/bsp/ls1cdev/drivers/net/synopGMAC_Host.h index 05f289c8c78..e6d31d551df 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_Host.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_Host.h @@ -1,21 +1,7 @@ /* - * File : synopGMAC_Host.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_debug.h b/bsp/ls1cdev/drivers/net/synopGMAC_debug.h index 9e65d1d9457..9766587e1a3 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_debug.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_debug.h @@ -1,21 +1,7 @@ /* - * File : synopGMAC_debug.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_network_interface.h b/bsp/ls1cdev/drivers/net/synopGMAC_network_interface.h index e93ab6a66e7..8ded91d359d 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_network_interface.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_network_interface.h @@ -1,30 +1,7 @@ -/** \file - * Header file for the nework dependent functionality. - * The function prototype listed here are linux dependent. - * - * \internal - * ---------------------------REVISION HISTORY------------------- - * Synopsys 01/Aug/2007 Created - */ - /* - * File : synopGMAC_network_interface.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_plat.c b/bsp/ls1cdev/drivers/net/synopGMAC_plat.c index 8f70ad99d7e..3dfbe077d73 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_plat.c +++ b/bsp/ls1cdev/drivers/net/synopGMAC_plat.c @@ -1,34 +1,7 @@ -/**\file - * This file defines the wrapper for the platform/OS related functions - * The function definitions needs to be modified according to the platform - * and the Operating system used. - * This file should be handled with greatest care while porting the driver - * to a different platform running different operating system other than - * Linux 2.6.xx. - * \internal - * ----------------------------REVISION HISTORY----------------------------- - * Synopsys 01/Aug/2007 Created - */ - - /* - * File : synopGMAC_plat.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_plat.h b/bsp/ls1cdev/drivers/net/synopGMAC_plat.h index 1b1283f2fc3..cec64737464 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_plat.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_plat.h @@ -1,33 +1,7 @@ -/**\file - * This file serves as the wrapper for the platform/OS dependent functions - * It is needed to modify these functions accordingly based on the platform and the - * OS. Whenever the synopsys GMAC driver ported on to different platform, this file - * should be handled at most care. - * The corresponding function definitions for non-inline functions are available in - * synopGMAC_plat.c file. - * \internal - * -------------------------------------REVISION HISTORY--------------------------- - * Synopsys 01/Aug/2007 Created - */ - /* - * File : synopGMAC_plat.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/net/synopGMAC_types.h b/bsp/ls1cdev/drivers/net/synopGMAC_types.h index d808bec8464..88504eebf79 100644 --- a/bsp/ls1cdev/drivers/net/synopGMAC_types.h +++ b/bsp/ls1cdev/drivers/net/synopGMAC_types.h @@ -1,21 +1,7 @@ /* - * File : synopGMAC_types.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) chinesebear + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/drivers/touch.c b/bsp/ls1cdev/drivers/touch.c index 249e7682bf6..37a4b192138 100644 --- a/bsp/ls1cdev/drivers/touch.c +++ b/bsp/ls1cdev/drivers/touch.c @@ -1,21 +1,7 @@ /* - * File : touch.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -32,7 +18,7 @@ #include "drv_spi.h" #include "touch.h" -#ifdef RT_USING_RTGUI +#ifdef XPT2046_USING_TOUCH #include #include @@ -40,8 +26,9 @@ #include #include -//Ļ Ҫ _ILI_HORIZONTAL_DIRECTION_ -//Ļ Ҫ _ILI_HORIZONTAL_DIRECTION_ + +//竖屏幕 不需要 _ILI_HORIZONTAL_DIRECTION_ +//横屏幕 需要 _ILI_HORIZONTAL_DIRECTION_ //#define _ILI_HORIZONTAL_DIRECTION_ @@ -57,7 +44,7 @@ TOUCH INT: 84 */ #define IS_TOUCH_UP() gpio_get(TOUCH_INT_PIN) -#define led_gpio 52 // led1ָʾ +#define led_gpio 52 // led1指示 #define DUMMY 0x00 @@ -97,7 +84,7 @@ s A2-A0 MODE SER/DFR PD1-PD0 #define TOUCH_MSR_Y (START | MEASURE_Y | MODE_12BIT | DIFFERENTIAL | POWER_MODE0) -/* ¶XPT2046 Ĵλ*/ +/* 以下定义XPT2046 的触摸屏位置*/ #if defined(_ILI_HORIZONTAL_DIRECTION_) #define MIN_X_DEFAULT 2047 #define MAX_X_DEFAULT 47 @@ -117,7 +104,7 @@ s A2-A0 MODE SER/DFR PD1-PD0 #define SH 10 // Valve value -/*궨 */ +/*宏定义 */ #define TOUCH_SPI_X SPI1 #define TOUCH_INT_PIN 84 #define TOUCH_CS_PIN 49 @@ -126,21 +113,21 @@ s A2-A0 MODE SER/DFR PD1-PD0 #define TOUCH_MOSI_PIN 48 -/*ṹ彫ҪõĶд*/ +/*创建结构体将需要用到的东西进行打包*/ struct rtgui_touch_device { - struct rt_device parent; /* ע豸*/ + struct rt_device parent; /* 用于注册设备*/ - rt_uint16_t x, y; /* ¼ȡλֵ */ + rt_uint16_t x, y; /* 记录读取到的位置值 */ - rt_bool_t calibrating; /* У׼־ */ - rt_touch_calibration_func_t calibration_func;/* ָ */ + rt_bool_t calibrating; /* 触摸校准标志 */ + rt_touch_calibration_func_t calibration_func;/* 触摸函数 函数指针 */ - rt_uint16_t min_x, max_x; /* У׼ X С ֵ */ - rt_uint16_t min_y, max_y; /* У׼ Y С ֵ */ + rt_uint16_t min_x, max_x; /* 校准后 X 方向最小 最大值 */ + rt_uint16_t min_y, max_y; /* 校准后 Y 方向最小 最大值 */ - struct rt_spi_device * spi_device; /* SPI 豸 ͨ */ - struct rt_event event; /* ¼ͬڡжϡ */ + struct rt_spi_device * spi_device; /* SPI 设备 用于通信 */ + struct rt_event event; /* 事件同步，用于“笔中断” */ }; static struct rtgui_touch_device *touch = RT_NULL; @@ -230,14 +217,14 @@ static void rtgui_touch_calculate(void) /* read touch */ { rt_uint8_t i, j, k, min; - rt_uint16_t temp; + rt_uint16_t temp; rt_uint16_t tmpxy[2][SAMP_CNT]; rt_uint8_t send_buffer[1]; rt_uint8_t recv_buffer[2]; for(i=0; ispi_device, send_buffer, 1, recv_buffer, 2); + touch_send_then_recv(touch->spi_device, send_buffer, 1, recv_buffer, 2); rt_kprintf("touch x: %d ",(recv_buffer[0]*256|recv_buffer[1])>>4); #if defined(_ILI_HORIZONTAL_DIRECTION_) tmpxy[1][i] = (recv_buffer[0]<<8)|recv_buffer[1] ; @@ -249,7 +236,7 @@ static void rtgui_touch_calculate(void) #endif send_buffer[0] = TOUCH_MSR_Y; touch_send_then_recv(touch->spi_device, send_buffer, 1, recv_buffer, 2); - rt_kprintf("touch y: %d \n",(recv_buffer[0]*256|recv_buffer[1])>>4); + rt_kprintf("touch y: %d \n",(recv_buffer[0]*256|recv_buffer[1])>>4); #if defined(_ILI_HORIZONTAL_DIRECTION_) tmpxy[0][i] = (recv_buffer[0]<<8)|recv_buffer[1] ; @@ -259,46 +246,46 @@ static void rtgui_touch_calculate(void) tmpxy[1][i] >>= 4; #endif } - /*ٴδ򿪴ж*/ + /*再次打开触摸中断*/ send_buffer[0] = 1 << 7; - touch_send_then_recv(touch->spi_device, send_buffer, 1, recv_buffer, 2); + touch_send_then_recv(touch->spi_device, send_buffer, 1, recv_buffer, 2); touch_send_then_recv(touch->spi_device, send_buffer, 1, recv_buffer, 2); /* calculate average */ - { - rt_uint32_t total_x = 0; - rt_uint32_t total_y = 0; - for(k=0; k<2; k++) - { - // sorting the ADC value - for(i=0; i tmpxy[k][j]) - min=j; - } - temp = tmpxy[k][i]; - tmpxy[k][i] = tmpxy[k][min]; - tmpxy[k][min] = temp; - } - //check value for Valve value - if((tmpxy[k][SAMP_CNT_DIV2+1]-tmpxy[k][SAMP_CNT_DIV2-2]) > SH) - { - return; - } - } - total_x=tmpxy[0][SAMP_CNT_DIV2-2]+tmpxy[0][SAMP_CNT_DIV2-1]+tmpxy[0][SAMP_CNT_DIV2]+tmpxy[0][SAMP_CNT_DIV2+1]; - total_y=tmpxy[1][SAMP_CNT_DIV2-2]+tmpxy[1][SAMP_CNT_DIV2-1]+tmpxy[1][SAMP_CNT_DIV2]+tmpxy[1][SAMP_CNT_DIV2+1]; - //calculate average value - touch->x=total_x>>2; - touch->y=total_y>>2; + { + rt_uint32_t total_x = 0; + rt_uint32_t total_y = 0; + for(k=0; k<2; k++) + { + // sorting the ADC value + for(i=0; i tmpxy[k][j]) + min=j; + } + temp = tmpxy[k][i]; + tmpxy[k][i] = tmpxy[k][min]; + tmpxy[k][min] = temp; + } + //check value for Valve value + if((tmpxy[k][SAMP_CNT_DIV2+1]-tmpxy[k][SAMP_CNT_DIV2-2]) > SH) + { + return; + } + } + total_x=tmpxy[0][SAMP_CNT_DIV2-2]+tmpxy[0][SAMP_CNT_DIV2-1]+tmpxy[0][SAMP_CNT_DIV2]+tmpxy[0][SAMP_CNT_DIV2+1]; + total_y=tmpxy[1][SAMP_CNT_DIV2-2]+tmpxy[1][SAMP_CNT_DIV2-1]+tmpxy[1][SAMP_CNT_DIV2]+tmpxy[1][SAMP_CNT_DIV2+1]; + //calculate average value + touch->x=total_x>>2; + touch->y=total_y>>2; rt_kprintf("touch->x:%d touch->y:%d\r\n", touch->x, touch->y); } /* calculate average */ } /* read touch */ /* if it's not in calibration status */ - /*ֵ*/ + /*触摸值缩放*/ if (touch->calibrating != RT_TRUE) { if (touch->max_x > touch->min_x) @@ -322,19 +309,19 @@ static void rtgui_touch_calculate(void) } } #include "ls1c_regs.h" -#define TOUCH_INT_EN __REG32(LS1C_INT4_EN) +#define TOUCH_INT_EN __REG32(LS1C_INT4_EN) rt_inline void touch_int_cmd(rt_bool_t NewState) { - if(NewState == RT_TRUE) - { - //TOUCH_INT_EN |= (1<<(TOUCH_INT_PIN-64)); - reg_set_one_bit(LS1C_INT4_EN, 1<<(TOUCH_INT_PIN-64)); - } - else - { - //TOUCH_INT_EN &=(~ (1<<(TOUCH_INT_PIN-64))); - reg_clr_one_bit(LS1C_INT4_EN, 1<<(TOUCH_INT_PIN-64)); - } + if(NewState == RT_TRUE) + { + //TOUCH_INT_EN |= (1<<(TOUCH_INT_PIN-64)); + reg_set_one_bit(LS1C_INT4_EN, 1<<(TOUCH_INT_PIN-64)); + } + else + { + //TOUCH_INT_EN &=(~ (1<<(TOUCH_INT_PIN-64))); + reg_clr_one_bit(LS1C_INT4_EN, 1<<(TOUCH_INT_PIN-64)); + } } @@ -342,29 +329,29 @@ void ls1c_touch_irqhandler(void) /* TouchScreen */ { if(gpio_get(TOUCH_INT_PIN)==0) { - /* º */ - if (gpio_level_low == gpio_get(led_gpio)) - gpio_set(led_gpio, gpio_level_high); - else - gpio_set(led_gpio, gpio_level_low); - touch_int_cmd(RT_FALSE); - rt_event_send(&touch->event, 1); + /* 触摸屏按下后操作 */ + if (gpio_level_low == gpio_get(led_gpio)) + gpio_set(led_gpio, gpio_level_high); + else + gpio_set(led_gpio, gpio_level_low); + touch_int_cmd(RT_FALSE); + rt_event_send(&touch->event, 1); } } -/*ܽųʼжϴSPI1 CS0 豸*/ +/*管脚初始化，配置中断打开SPI1 CS0 设备*/ rt_inline void touch_init(void) -{ - unsigned int touch_int_gpio = TOUCH_INT_PIN; // ж +{ + unsigned int touch_int_gpio = TOUCH_INT_PIN; // 触摸屏中断 int touch_irq = LS1C_GPIO_TO_IRQ(touch_int_gpio); - // ʼж + // 初始化按键中断 gpio_set_irq_type(touch_int_gpio, IRQ_TYPE_EDGE_FALLING); rt_hw_interrupt_install(touch_irq, ls1c_touch_irqhandler, RT_NULL, "touch"); rt_hw_interrupt_umask(touch_irq); gpio_init(touch_int_gpio, gpio_mode_input); - // ʼled + // 初始化led gpio_init(led_gpio, gpio_mode_output); gpio_set(led_gpio, gpio_level_high); } @@ -374,9 +361,9 @@ rt_inline void touch_init(void) static rt_err_t rtgui_touch_init (rt_device_t dev) { rt_uint8_t send; - rt_uint8_t recv_buffer[2]; + rt_uint8_t recv_buffer[2]; struct rtgui_touch_device * touch_device = (struct rtgui_touch_device *)dev; - + touch_init(); rt_kprintf("touch_init ...\n"); send = START | DIFFERENTIAL | POWER_MODE0; @@ -433,7 +420,7 @@ static void touch_thread_entry(void *parameter) while(1) { - /* յж¼ */ + /* 接收到触摸中断事件 */ if(rt_event_recv(&touch->event, 1, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, @@ -445,7 +432,7 @@ static void touch_thread_entry(void *parameter) { if (IS_TOUCH_UP()) { - /* ̧ */ + /* 触摸笔抬起 */ /* touch up */ emouse.button = (RTGUI_MOUSE_BUTTON_LEFT |RTGUI_MOUSE_BUTTON_UP); @@ -461,14 +448,14 @@ static void touch_thread_entry(void *parameter) if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) { - /* У׼ */ + /* 触摸校准处理 */ /* callback function */ touch->calibration_func(emouse.x, emouse.y); - + } else { - /* uiʹ */ + /* 向ui发送触摸坐标 */ rtgui_server_post_event(&emouse.parent, sizeof(struct rtgui_event_mouse)); } rt_kprintf("touch up: (%d, %d)\n", emouse.x, emouse.y); @@ -503,7 +490,7 @@ static void touch_thread_entry(void *parameter) emouse.x = touch->x; emouse.y = touch->y; _set_mouse_position(emouse.x, emouse.y); - /* */ + /* 光标跟随 */ /* init mouse button */ emouse.button = (RTGUI_MOUSE_BUTTON_LEFT |RTGUI_MOUSE_BUTTON_DOWN); @@ -519,7 +506,7 @@ static void touch_thread_entry(void *parameter) { touch_previous.x = touch->x; touch_previous.y = touch->y; - /* uiʹ */ + /* 向ui发送触摸坐标 */ rtgui_server_post_event(&emouse.parent, sizeof(struct rtgui_event_mouse)); if(touch_down == RT_FALSE) { @@ -545,24 +532,24 @@ static void touch_thread_entry(void *parameter) rt_err_t rtgui_touch_hw_init(const char * spi_device_name) { - rt_uint32_t arg[2]; - struct rt_device * spi_device; - struct rt_thread * touch_thread; - rt_err_t err; - - rt_kprintf("spi1 cs0 start...\n"); - spi_device = rt_device_find("spi10"); - if(spi_device == RT_NULL) - { - rt_kprintf("Did not find spi1, exit thread....\n"); - return; - } - err = rt_device_open(spi_device, RT_DEVICE_OFLAG_RDWR); - if(err != RT_EOK) - { - rt_kprintf("Open spi1 failed %08X, exit thread....\n", err); - return; - } + rt_uint32_t arg[2]; + struct rt_device * spi_device; + struct rt_thread * touch_thread; + rt_err_t err; + + rt_kprintf("spi1 cs0 start...\n"); + spi_device = rt_device_find("spi10"); + if(spi_device == RT_NULL) + { + rt_kprintf("Did not find spi1, exit thread....\n"); + return; + } + err = rt_device_open(spi_device, RT_DEVICE_OFLAG_RDWR); + if(err != RT_EOK) + { + rt_kprintf("Open spi1 failed %08X, exit thread....\n", err); + return; + } /* config spi */ { @@ -573,7 +560,7 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name) rt_spi_configure((struct rt_spi_device *)spi_device, &cfg); } - touch = (struct rtgui_touch_device*)rt_malloc (sizeof(struct rtgui_touch_device)); + touch = (struct rtgui_touch_device*)rt_malloc (sizeof(struct rtgui_touch_device)); if (touch == RT_NULL) return RT_ENOMEM; /* no memory yet */ /* clear device structure */ @@ -597,7 +584,7 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name) /* register touch device to RT-Thread */ rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR); - + touch_thread = rt_thread_create("touch_thread", touch_thread_entry, RT_NULL, diff --git a/bsp/ls1cdev/drivers/touch.h b/bsp/ls1cdev/drivers/touch.h index 0892d2858f2..5dac8335109 100644 --- a/bsp/ls1cdev/drivers/touch.h +++ b/bsp/ls1cdev/drivers/touch.h @@ -1,21 +1,7 @@ /* - * File : touch.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/libraries/ls1c_can.c b/bsp/ls1cdev/libraries/ls1c_can.c index f113e60990d..437ef3ba84c 100644 --- a/bsp/ls1cdev/libraries/ls1c_can.c +++ b/bsp/ls1cdev/libraries/ls1c_can.c @@ -1,21 +1,7 @@ /* - * File : ls1c_can.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,6 +11,7 @@ #include "ls1c.h" #include "ls1c_public.h" #include "ls1c_can.h" +#include "ls1c_delay.h" unsigned char set_reset_mode(CAN_TypeDef* CANx) { @@ -51,7 +38,7 @@ unsigned char set_reset_mode(CAN_TypeDef* CANx) /*检查复位标志*/ status = CANx->MOD; } - rt_kprintf("\r\nSetting SJA1000 into reset mode failed!\r\n"); + printf("\r\nSetting SJA1000 into reset mode failed!\r\n"); return 0; } @@ -77,7 +64,7 @@ static unsigned char set_normal_mode(CAN_TypeDef* CANx) delay_us(10); status = CANx->MOD; } - rt_kprintf("\r\nSetting SJA1000 into normal mode failed!\r\n"); + printf("\r\nSetting SJA1000 into normal mode failed!\r\n"); return 0; } @@ -102,7 +89,7 @@ unsigned char CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) status = CANx->MOD; if( status == 0xFF) { - rt_kprintf("\n Probe can0 failed \r\n"); + printf("\n Probe can0 failed \r\n"); return CAN_InitStatus_Failed; } diff --git a/bsp/ls1cdev/libraries/ls1c_can.h b/bsp/ls1cdev/libraries/ls1c_can.h index 4e27a4b075c..b2b0f8efa88 100644 --- a/bsp/ls1cdev/libraries/ls1c_can.h +++ b/bsp/ls1cdev/libraries/ls1c_can.h @@ -1,22 +1,7 @@ - /* - * File : ls1c_can.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: (Pelican Mode) * Date Author Notes @@ -221,7 +206,7 @@ unsigned char CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); void CAN_Receive(CAN_TypeDef* CANx, CanRxMsg* RxMessage); unsigned char set_reset_mode(CAN_TypeDef* CANx); -unsigned char set_start(CAN_TypeDef* CANx); +unsigned char set_start(CAN_TypeDef* CANx); #endif diff --git a/bsp/ls1cdev/libraries/ls1c_clock.c b/bsp/ls1cdev/libraries/ls1c_clock.c index c038651e8d2..1ae621cbbb4 100644 --- a/bsp/ls1cdev/libraries/ls1c_clock.c +++ b/bsp/ls1cdev/libraries/ls1c_clock.c @@ -1,28 +1,32 @@ -/************************************************************************* +/* + * Copyright (c) 2006-2018, RT-Thread Development Team * - * ʱغ + * SPDX-License-Identifier: Apache-2.0 * - *************************************************************************/ + * Change Logs: + * Date Author Notes + * 2017-09-06 勤为本 first version + */ #include "ls1c_regs.h" #include "ls1c_public.h" -// Ƶ +// 晶振的频率 #define AHB_CLK (24000000) #define APB_CLK (AHB_CLK) -// START_FREQĴbits +// START_FREQ寄存器bits #define M_PLL_SHIFT (8) -#define M_PLL (0xff << M_PLL_SHIFT) // PLLƵϵ +#define M_PLL (0xff << M_PLL_SHIFT) // PLL倍频系数的整数部分 #define FRAC_N_SHIFT (16) -#define FRAC_N (0xff << FRAC_N_SHIFT) // PLLƵϵС +#define FRAC_N (0xff << FRAC_N_SHIFT) // PLL倍频系数的小数部分 #define DIV_SDRAM_SHIFT (0) #define DIV_SDRAM (0x3 << DIV_SDRAM_SHIFT) -// CLK_DIV_PARAMĴbits +// CLK_DIV_PARAM寄存器bits #define DIV_PIX_EN (0x1 << 31) #define DIV_PIX (0x7f << 24) #define DIV_CAM_EN (0x1 << 23) @@ -42,8 +46,8 @@ /* - * ȡPLLƵ - * @ret PLLƵ + * 获取PLL频率 + * @ret PLL频率 */ unsigned long clk_get_pll_rate(void) { @@ -58,8 +62,8 @@ unsigned long clk_get_pll_rate(void) /* - * ȡCPUƵ - * @ret CPUƵ + * 获取CPU频率 + * @ret CPU频率 */ unsigned long clk_get_cpu_rate(void) { @@ -69,8 +73,8 @@ unsigned long clk_get_cpu_rate(void) pll_rate = clk_get_pll_rate(); ctrl = reg_read_32((volatile unsigned int *)LS1C_CLK_DIV_PARAM); - // ѡʱԴ - if (DIV_CPU_SEL & ctrl) // pllƵΪʱź + // 选择时钟来源 + if (DIV_CPU_SEL & ctrl) // pll分频作为时钟信号 { if (DIV_CPU_EN & ctrl) { @@ -81,7 +85,7 @@ unsigned long clk_get_cpu_rate(void) cpu_rate = pll_rate / 2; } } - else // bypassģʽΪʱ + else // bypass模式，晶振作为时钟输入 { cpu_rate = APB_CLK; } @@ -91,8 +95,8 @@ unsigned long clk_get_cpu_rate(void) /* - * ȡDDRƵ - * @ret DDRƵ + * 获取DDR频率 + * @ret DDR频率 */ unsigned long clk_get_ddr_rate(void) { @@ -125,8 +129,8 @@ unsigned long clk_get_ddr_rate(void) /* - * ȡAPBƵ - * @ret APBƵ + * 获取APB频率 + * @ret APB频率 */ unsigned long clk_get_apb_rate(void) { @@ -135,8 +139,8 @@ unsigned long clk_get_apb_rate(void) /* - * ȡDCƵ - * @ret DCƵ + * 获取DC频率 + * @ret DC频率 */ unsigned long clk_get_dc_rate(void) { diff --git a/bsp/ls1cdev/libraries/ls1c_clock.h b/bsp/ls1cdev/libraries/ls1c_clock.h index 82223500224..3cacb7454a6 100644 --- a/bsp/ls1cdev/libraries/ls1c_clock.h +++ b/bsp/ls1cdev/libraries/ls1c_clock.h @@ -1,8 +1,12 @@ -/************************************************************************* +/* + * Copyright (c) 2006-2018, RT-Thread Development Team * - * ʱͷļ + * SPDX-License-Identifier: Apache-2.0 * - *************************************************************************/ + * Change Logs: + * Date Author Notes + * 2017-09-06 Ϊ first version + */ #ifndef __OPENLOONGSON_CLOCK_H diff --git a/bsp/ls1cdev/libraries/ls1c_delay.c b/bsp/ls1cdev/libraries/ls1c_delay.c index 214926e58e7..418a310bf84 100644 --- a/bsp/ls1cdev/libraries/ls1c_delay.c +++ b/bsp/ls1cdev/libraries/ls1c_delay.c @@ -1,4 +1,12 @@ -// ʱԴļ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 Ϊ first version + */ #include "ls1c_clock.h" @@ -12,7 +20,7 @@ */ void delay_ms(int j) { - int k_max = clk_get_cpu_rate()/1000/3; // 1000ʾms3Ϊõľ(ΪڲѭִһҪʱӸ) + int k_max = clk_get_cpu_rate()/1000/92; // 1000ʾmsһΪʵõľֵ int k = k_max; for ( ; j > 0; j--) @@ -33,24 +41,25 @@ void delay_ms(int j) */ void delay_us(int n) { - int count_1us = clk_get_cpu_rate() / 1000000 / 3; // ʱ1usѭ + int count_1us = 252000000 / 1000000 / 84; // ʱ1usѭ + // 252000000ΪcpuƵʣ1000000ʾʱλΪus92Ϊʵõľֵ int count_max; // ʱn΢ѭ int tmp; - // ʱ΢(ע⣬ֶŻģcpuƵʸı˿ҪŻʱcpuƵΪ252Mhz) + // ΢ + count_max = n * count_1us; if (10 >= n) // <=10us { - count_1us -= 35; + count_max = count_max / 3; } else if (100 >= n) // <= 100us { - count_1us -= 6; + count_max = count_max - count_max / 5; } else // > 100us { - count_1us -= 1; + count_max = count_max - count_max / 10; } - count_max = n * count_1us; // ʱ for (tmp = count_max; tmp > 0; tmp--) diff --git a/bsp/ls1cdev/libraries/ls1c_delay.h b/bsp/ls1cdev/libraries/ls1c_delay.h index d6f366de33b..15cc1d43b15 100644 --- a/bsp/ls1cdev/libraries/ls1c_delay.h +++ b/bsp/ls1cdev/libraries/ls1c_delay.h @@ -1,5 +1,12 @@ -// ʱͷļ - +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 Ϊ first version + */ #ifndef __OPENLOONGSON_DELAY_H diff --git a/bsp/ls1cdev/libraries/ls1c_gpio.c b/bsp/ls1cdev/libraries/ls1c_gpio.c index ee073b7c4bd..4bf6b7a20bd 100644 --- a/bsp/ls1cdev/libraries/ls1c_gpio.c +++ b/bsp/ls1cdev/libraries/ls1c_gpio.c @@ -1,4 +1,12 @@ -// װgpioӿ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 勤为本 first version + */ #include "ls1c_public.h" @@ -8,13 +16,13 @@ /* - * ȡָgpioCFGĴ - * @gpio gpio - * @ret CFGĴ + * 获取指定gpio的CFG寄存器 + * @gpio gpio编号 + * @ret CFG寄存器 */ volatile unsigned int *gpio_get_cfg_reg(unsigned int gpio) { - volatile unsigned int *gpio_cfgx = NULL; // GPIO_CFGxĴ + volatile unsigned int *gpio_cfgx = NULL; // GPIO_CFGx寄存器 unsigned int port = GPIO_GET_PORT(gpio); switch (port) @@ -45,13 +53,13 @@ volatile unsigned int *gpio_get_cfg_reg(unsigned int gpio) /* - * ȡָgpioENĴ - * @gpio gpio - * @ret ENĴ + * 获取指定gpio的EN寄存器 + * @gpio gpio编号 + * @ret EN寄存器 */ volatile unsigned int *gpio_get_en_reg(unsigned int gpio) { - volatile unsigned int *gpio_enx = NULL; // GPIO_ENxĴ + volatile unsigned int *gpio_enx = NULL; // GPIO_ENx寄存器 unsigned int port = GPIO_GET_PORT(gpio); switch (port) @@ -81,28 +89,28 @@ volatile unsigned int *gpio_get_en_reg(unsigned int gpio) } /* - * gpioʼ - * @gpio gpioţȡֵΧ[0, 127] - * @mode gpioĹģʽ(롢) + * gpio初始化 + * @gpio gpio引脚，取值范围[0, 127] + * @mode gpio的工作模式(输入、输出) * - * : gpio50ʼΪ + * 例: 将gpio50初始化为输出 * gpio_init(50, gpio_mode_output); */ void gpio_init(unsigned int gpio, gpio_mode_t mode) { - volatile unsigned int *gpio_enx = NULL; // GPIO_ENxĴ + volatile unsigned int *gpio_enx = NULL; // GPIO_ENx寄存器 unsigned int pin = GPIO_GET_PIN(gpio); - // pinΪͨGPIO + // 将pin设为普通GPIO pin_set_purpose(gpio, PIN_PURPOSE_GPIO); - // gpioģʽ(롢) + // 设置gpio工作模式(输入、输出) gpio_enx = gpio_get_en_reg(gpio); - if (gpio_mode_output == mode) // + if (gpio_mode_output == mode) // 输出 { reg_clr_one_bit(gpio_enx, pin); } - else // + else // 输入 { reg_set_one_bit(gpio_enx, pin); } @@ -112,20 +120,20 @@ void gpio_init(unsigned int gpio, gpio_mode_t mode) /* - * ָgpioߵƽ͵ƽ - * @gpio gpioţȡֵΧ[0, 127] - * @level ƽֵ + * 在指定gpio输出高电平或低电平 + * @gpio gpio引脚，取值范围[0, 127] + * @level 电平值 * - * : gpio50͵ƽ + * 例: 在gpio50上输出低电平 * gpio_set(50, gpio_level_low); */ void gpio_set(unsigned int gpio, gpio_level_t level) { - volatile unsigned int *gpio_outx = NULL; // GPIO_OUTxĴ + volatile unsigned int *gpio_outx = NULL; // GPIO_OUTx寄存器 unsigned int port = GPIO_GET_PORT(gpio); unsigned int pin = GPIO_GET_PIN(gpio); - // ȡĴַ + // 获取寄存器地址 switch (port) { case 0: @@ -144,11 +152,11 @@ void gpio_set(unsigned int gpio, gpio_level_t level) gpio_outx = (volatile unsigned int *)LS1C_GPIO_OUT3; break; - default: // ȷijӦߵֱӷ + default: // 正确的程序不应该走到这里，直接返回 return ; } - // + // 输出 if (gpio_level_low == level) { reg_clr_one_bit(gpio_outx, pin); @@ -163,20 +171,20 @@ void gpio_set(unsigned int gpio, gpio_level_t level) /* - * ȡָgpioŵֵ - * @gpio gpioţȡֵΧ[0,127] + * 读取指定gpio引脚的值 + * @gpio gpio引脚，取值范围[0,127] * - * : ȡgpio50ϵֵ + * 例: 读取gpio50引脚上的值 * gpio_level_t level; * level = gpio_get(50); */ unsigned int gpio_get(unsigned int gpio) { - volatile unsigned int *gpio_inx = NULL; // GPIO_INxĴ + volatile unsigned int *gpio_inx = NULL; // GPIO_INx寄存器 unsigned int port = GPIO_GET_PORT(gpio); unsigned int pin = GPIO_GET_PIN(gpio); - // ȡĴַ + // 获取寄存器地址 switch (port) { case 0: @@ -195,28 +203,28 @@ unsigned int gpio_get(unsigned int gpio) gpio_inx = (volatile unsigned int *)LS1C_GPIO_IN3; break; - default: // ̲Ӧߵֱӷ + default: // 正常的流程不应该走到这里，直接返回 return 0; } - // ȡ + // 读取 return reg_get_bit(gpio_inx, pin); } /** - * ж - * @gpio gpio - * @type жϵߵƽ͵ƽش or ½ش + * 设置中断类型 + * @gpio gpio引脚 + * @type 触发中断的条件。高电平触发、低电平触发、上升沿触发 or 下降沿触发 */ void gpio_set_irq_type(unsigned int gpio, gpio_irq_type_t type) { - volatile unsigned int *int_pol = NULL; // жϼѡĴ - volatile unsigned int *int_edge = NULL; // жϱѡĴ + volatile unsigned int *int_pol = NULL; // 中断极性选择寄存器 + volatile unsigned int *int_edge = NULL; // 中断边沿选择寄存器 unsigned int port = GPIO_GET_PORT(gpio); unsigned int pin = GPIO_GET_PIN(gpio); - // ȡĴַ + // 获取寄存器地址 switch (port) { case 0: // GPIO[31:0] @@ -235,7 +243,7 @@ void gpio_set_irq_type(unsigned int gpio, gpio_irq_type_t type) break; } - // ж + // 设置中断类型 switch (type) { case IRQ_TYPE_EDGE_RISING: diff --git a/bsp/ls1cdev/libraries/ls1c_gpio.h b/bsp/ls1cdev/libraries/ls1c_gpio.h index 1609684bd39..c5c9b123126 100644 --- a/bsp/ls1cdev/libraries/ls1c_gpio.h +++ b/bsp/ls1cdev/libraries/ls1c_gpio.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 Ϊ first version + */ #ifndef __OPENLOONGSON_GPIO_H diff --git a/bsp/ls1cdev/libraries/ls1c_i2c.c b/bsp/ls1cdev/libraries/ls1c_i2c.c index 6a1622471c9..11475cf1490 100644 --- a/bsp/ls1cdev/libraries/ls1c_i2c.c +++ b/bsp/ls1cdev/libraries/ls1c_i2c.c @@ -1,21 +1,7 @@ /* - * File : ls1c_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/libraries/ls1c_i2c.h b/bsp/ls1cdev/libraries/ls1c_i2c.h index ada22242fb8..1fb1ef69413 100644 --- a/bsp/ls1cdev/libraries/ls1c_i2c.h +++ b/bsp/ls1cdev/libraries/ls1c_i2c.h @@ -1,21 +1,7 @@ /* - * File : ls1c_i2c.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ls1cdev/libraries/ls1c_pin.c b/bsp/ls1cdev/libraries/ls1c_pin.c index 81f56c0b0c9..0a817abe075 100644 --- a/bsp/ls1cdev/libraries/ls1c_pin.c +++ b/bsp/ls1cdev/libraries/ls1c_pin.c @@ -1,3 +1,13 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 勤为本 first version + */ + // 引脚功能(普通gpio，pwm，复用等)相关接口 diff --git a/bsp/ls1cdev/libraries/ls1c_pin.h b/bsp/ls1cdev/libraries/ls1c_pin.h index c483f5659af..26cc4cac922 100644 --- a/bsp/ls1cdev/libraries/ls1c_pin.h +++ b/bsp/ls1cdev/libraries/ls1c_pin.h @@ -1,3 +1,13 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 Ϊ first version + */ + // Ź(ͨgpiopwmõ)ؽӿ #ifndef __OPENLOONGSON_PIN_H diff --git a/bsp/ls1cdev/libraries/ls1c_public.c b/bsp/ls1cdev/libraries/ls1c_public.c index 3e57e9a50af..3523ced4199 100644 --- a/bsp/ls1cdev/libraries/ls1c_public.c +++ b/bsp/ls1cdev/libraries/ls1c_public.c @@ -1,3 +1,13 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 Ϊ first version + */ + // һЩõġõĽӿ /* diff --git a/bsp/ls1cdev/libraries/ls1c_public.h b/bsp/ls1cdev/libraries/ls1c_public.h index c06aa4dd8a2..5d2390acecd 100644 --- a/bsp/ls1cdev/libraries/ls1c_public.h +++ b/bsp/ls1cdev/libraries/ls1c_public.h @@ -1,4 +1,14 @@ -// һЩõġõĽӿ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 勤为本 first version + */ + +// 一些常用的、共用的接口 #ifndef __OPENLOONGSON_PUBLIC_H #define __OPENLOONGSON_PUBLIC_H @@ -7,7 +17,7 @@ #include -// pmonṩĴӡmain() +// pmon提供的打印函数，见main()函数 struct callvectors { int (*open) (char *, int, int); int (*close) (int); @@ -35,58 +45,58 @@ typedef enum }BOOL; /* - * ָĴָλ1 - * @reg Ĵַ - * @bit Ҫ1һbit + * 将指定寄存器的指定位置1 + * @reg 寄存器地址 + * @bit 需要置1的那一bit */ void reg_set_one_bit(volatile unsigned int *reg, unsigned int bit); /* - * ָĴָλ - * @reg Ĵַ - * @bit Ҫһbit + * 将指定寄存器的指定位清零 + * @reg 寄存器地址 + * @bit 需要清零的那一bit */ void reg_clr_one_bit(volatile unsigned int *reg, unsigned int bit); /* - * ȡָĴָλֵ - * @reg Ĵַ - * @bit Ҫȡֵһbit - * @ret ָλֵ + * 获取指定寄存器的指定位的值 + * @reg 寄存器地址 + * @bit 需要读取值的那一bit + * @ret 指定位的值 */ unsigned int reg_get_bit(volatile unsigned int *reg, unsigned int bit); /* - * Ĵд8bit(һֽ) - * @data д - * @addr Ĵַ + * 向寄存器中写入8bit(一个字节)数据 + * @data 待写入的数据 + * @addr 寄存器地址 */ void reg_write_8(unsigned char data, volatile unsigned char *addr); /* - * ӼĴ8bit(һֽ) - * @addr Ĵַ - * @ret + * 从寄存器读出8bit(一个字节)数据 + * @addr 寄存器地址 + * @ret 读出的数据 */ unsigned char reg_read_8(volatile unsigned char *addr); /* - * Ĵдһ32bit - * @data д - * @addr Ĵַ + * 向寄存器中写一个32bit的数据 + * @data 待写入的数据 + * @addr 寄存器地址 */ void reg_write_32(unsigned int data, volatile unsigned int *addr); /* - * ӼĴһ32bit - * @addr Ĵַ - * @ret + * 从寄存器读出一个32bit数据 + * @addr 寄存器地址 + * @ret 读出的数据 */ unsigned int reg_read_32(volatile unsigned int *addr); diff --git a/bsp/ls1cdev/libraries/ls1c_pwm.c b/bsp/ls1cdev/libraries/ls1c_pwm.c index 01ffc6f3a9e..b91f81c43b4 100644 --- a/bsp/ls1cdev/libraries/ls1c_pwm.c +++ b/bsp/ls1cdev/libraries/ls1c_pwm.c @@ -1,3 +1,13 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 Ϊ first version + */ + // װӲpwmӿ #include "ls1c_public.h" @@ -6,13 +16,9 @@ #include "ls1c_clock.h" #include "ls1c_regs.h" - - // pwm #define PWM_MAX_PERIOD (0xFFFFFF) // ֵ - - /* * gpioȡӦpwmĻַ * @gpio pwm @@ -193,5 +199,3 @@ void pwm_init(pwm_info_t *pwm_info) return ; } - - diff --git a/bsp/ls1cdev/libraries/ls1c_pwm.h b/bsp/ls1cdev/libraries/ls1c_pwm.h index aa9daeeb0c5..865a2ddf1d9 100644 --- a/bsp/ls1cdev/libraries/ls1c_pwm.h +++ b/bsp/ls1cdev/libraries/ls1c_pwm.h @@ -1,3 +1,12 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 Ϊ first version + */ #ifndef __OPENLOONGSON_PWM_H diff --git a/bsp/ls1cdev/libraries/ls1c_regs.h b/bsp/ls1cdev/libraries/ls1c_regs.h index 1f8b60ed177..7947c2bfe00 100644 --- a/bsp/ls1cdev/libraries/ls1c_regs.h +++ b/bsp/ls1cdev/libraries/ls1c_regs.h @@ -1,3 +1,13 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-09-06 勤为本 first version + */ + // 龙芯1c外设寄存器 @@ -139,6 +149,8 @@ #define LS1C_UART10_BASE (0xbfe4ca00) #define LS1C_UART11_BASE (0xbfe4cb00) +//RTC寄存器 +#define LS1C_RTC_BASE (0xbfe64024) #endif diff --git a/bsp/ls1cdev/libraries/ls1c_rtc.c b/bsp/ls1cdev/libraries/ls1c_rtc.c new file mode 100644 index 00000000000..838f6a85c12 --- /dev/null +++ b/bsp/ls1cdev/libraries/ls1c_rtc.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-06 sundm75 first version + */ +#include "ls1c.h" +#include "ls1c_public.h" +#include "ls1c_rtc.h" + +#define LS1C_SEC_OFFSET (4) +#define LS1C_MIN_OFFSET (10) +#define LS1C_HOUR_OFFSET (16) +#define LS1C_DAY_OFFSET (21) +#define LS1C_MONTH_OFFSET (26) + +#define LS1C_SEC_MASK (0x3f) +#define LS1C_MIN_MASK (0x3f) +#define LS1C_HOUR_MASK (0x1f) +#define LS1C_DAY_MASK (0x1f) +#define LS1C_MONTH_MASK (0x3f) +#define LS1C_YEAR_MASK (0xff) + +#define ls1c_get_sec(t) (((t) >> LS1C_SEC_OFFSET) & LS1C_SEC_MASK) +#define ls1c_get_min(t) (((t) >> LS1C_MIN_OFFSET) & LS1C_MIN_MASK) +#define ls1c_get_hour(t) (((t) >> LS1C_HOUR_OFFSET) & LS1C_HOUR_MASK) +#define ls1c_get_day(t) (((t) >> LS1C_DAY_OFFSET) & LS1C_DAY_MASK) +#define ls1c_get_month(t) (((t) >> LS1C_MONTH_OFFSET) & LS1C_MONTH_MASK) + +int RTC_SetTime(RTC_TypeDef *hrtc, RTC_TimeTypeDef *sTime) +{ + + hrtc->SYS_TOYWRITE0 + = (sTime->Month << LS1C_MONTH_OFFSET) + | (sTime->Date << LS1C_DAY_OFFSET) + | (sTime->Hours << LS1C_HOUR_OFFSET) + | (sTime->Minutes << LS1C_MIN_OFFSET) + | (sTime->Seconds << LS1C_SEC_OFFSET); + hrtc->SYS_TOYWRITE1 = sTime->Year % 100; + printf("\r\ntoy_read0 = 0x%x, toy_read1 = 0x%x.\r\n", hrtc->SYS_TOYREAD0, hrtc->SYS_TOYREAD1); + + return 0; +} + +int RTC_GetTime(RTC_TypeDef *hrtc, RTC_TimeTypeDef *sTime) +{ + unsigned long toy_read0, toy_read1; + toy_read0 = hrtc->SYS_TOYREAD0; + toy_read1 = hrtc->SYS_TOYREAD1; + sTime->Seconds = ls1c_get_sec(toy_read0); + sTime->Minutes = ls1c_get_min(toy_read0); + sTime->Hours = ls1c_get_hour(toy_read0); + sTime->Date = ls1c_get_day(toy_read0); + sTime->Month = ls1c_get_month(toy_read0); + sTime->Year = toy_read1 & LS1C_YEAR_MASK; + return 0 ; +} + +unsigned char RTC_IsLeapYear(unsigned int nYear) +{ + if((nYear % 4U) != 0U) + { + return 0U; + } + + if((nYear % 100U) != 0U) + { + return 1U; + } + + if((nYear % 400U) == 0U) + { + return 1U; + } + else + { + return 0U; + } +} + +unsigned char RTC_WeekDayNum(unsigned long nYear, unsigned char nMonth, unsigned char nDay) +{ + unsigned long year = 0U, weekday = 0U; + + year = 2000U + nYear; + + if(nMonth < 3U) + { + /*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/ + weekday = (((23U * nMonth)/9U) + nDay + 4U + year + ((year-1U)/4U) - ((year-1U)/100U) + ((year-1U)/400U)) % 7U; + } + else + { + /*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/ + weekday = (((23U * nMonth)/9U) + nDay + 4U + year + (year/4U) - (year/100U) + (year/400U) - 2U ) % 7U; + } + + return (unsigned char)weekday; +} diff --git a/bsp/ls1cdev/libraries/ls1c_rtc.h b/bsp/ls1cdev/libraries/ls1c_rtc.h new file mode 100644 index 00000000000..dee8000d6b1 --- /dev/null +++ b/bsp/ls1cdev/libraries/ls1c_rtc.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-06 sundm75 first version + */ + + #ifndef __OPENLOONGSON_RTC_H +#define __OPENLOONGSON_RTC_H + + +#define RTC ( (RTC_TypeDef* )LS1C_RTC_BASE) + +typedef struct +{ + unsigned char Year; /*0 ~ 99 */ + unsigned char Month; /*1 ~ 12 */ + unsigned char Date; /*1 ~ 31 */ + unsigned char Hours; /*0 ~ 23 */ + unsigned char Minutes; /*0 ~ 59 */ + unsigned char Seconds; /*0 ~ 59 */ +}RTC_TimeTypeDef; + +typedef struct +{ + unsigned long SYS_TOYWRITE0; + unsigned long SYS_TOYWRITE1; + unsigned long SYS_TOYREAD0; + unsigned long SYS_TOYREAD1; +} RTC_TypeDef; + +int RTC_SetTime(RTC_TypeDef *hrtc, RTC_TimeTypeDef *sTime); +int RTC_GetTime(RTC_TypeDef *hrtc, RTC_TimeTypeDef *sTime); + +unsigned char RTC_IsLeapYear(unsigned int nYear); +unsigned char RTC_WeekDayNum(unsigned long nYear, unsigned char nMonth, unsigned char nDay); + +#endif diff --git a/bsp/ls1cdev/libraries/ls1c_spi.c b/bsp/ls1cdev/libraries/ls1c_spi.c index eff1deb74f3..6ad39d964c0 100644 --- a/bsp/ls1cdev/libraries/ls1c_spi.c +++ b/bsp/ls1cdev/libraries/ls1c_spi.c @@ -1,21 +1,7 @@ /* - * File : ls1c_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -24,7 +10,6 @@ // 硬件spi接口源文件 - #include #include "ls1c_public.h" #include "ls1c_regs.h" @@ -38,7 +23,7 @@ * 获取指定SPI模块的基地址 * @SPIx SPI模块的编号 */ -inline void *ls1c_spi_get_base(unsigned char SPIx) +void *ls1c_spi_get_base(unsigned char SPIx) { void *base = NULL; @@ -67,7 +52,7 @@ inline void *ls1c_spi_get_base(unsigned char SPIx) */ void ls1c_spi_print_all_regs_info(void *spi_base) { - rt_kprintf("[%s] SPCR=0x%x, SPSR=0x%x, SPER=0x%x, SFC_PARAM=0x%x, SFC_SOFTCS=0x%x, SFC_TIMING=0x%x\r\n", + printf("[%s] SPCR=0x%x, SPSR=0x%x, SPER=0x%x, SFC_PARAM=0x%x, SFC_SOFTCS=0x%x, SFC_TIMING=0x%x\r\n", __FUNCTION__, reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET), reg_read_8(spi_base + LS1C_SPI_SPSR_OFFSET), @@ -137,7 +122,7 @@ unsigned int ls1c_spi_get_div(unsigned int max_speed_hz) break; } /* - rt_kprintf("[%s] clk=%ld, max_speed_hz=%d, div_tmp=%d, bit=%d\r\n", + printf("[%s] clk=%ld, max_speed_hz=%d, div_tmp=%d, bit=%d\r\n", __FUNCTION__, clk, max_speed_hz, div_tmp, bit); */ return div_tmp; @@ -229,7 +214,7 @@ void ls1c_spi_set_cs(void *spi_base, unsigned char cs, int new_status) * 等待收发完成 * @spi_base 基地址 */ -inline void ls1c_spi_wait_txrx_done(void *spi_base) +void ls1c_spi_wait_txrx_done(void *spi_base) { int timeout = LS1C_SPI_TX_TIMEOUT; @@ -247,7 +232,7 @@ inline void ls1c_spi_wait_txrx_done(void *spi_base) * 清中断和标志位 * @spi_base 基地址 */ -inline void ls1c_spi_clear(void *spi_base) +void ls1c_spi_clear(void *spi_base) { unsigned char val = 0; @@ -260,7 +245,7 @@ inline void ls1c_spi_clear(void *spi_base) val = reg_read_8(spi_base + LS1C_SPI_SPSR_OFFSET); if (LS1C_SPI_SPSR_WCOL_MASK & val) { - rt_kprintf("[%s] clear register SPSR's wcol!\r\n",__FUNCTION__); // 手册和linux源码中不一样，加个打印看看 + printf("[%s] clear register SPSR's wcol!\r\n"); // 手册和linux源码中不一样，加个打印看看 reg_write_8(val & ~LS1C_SPI_SPSR_WCOL_MASK, spi_base + LS1C_SPI_SPSR_OFFSET); // 写0，linux源码中是写0 // reg_write_8(val | LS1C_SPI_SPSR_WCOL_MASK, spi_base + LS1C_SPI_SPSR_OFFSET); // 写1，按照1c手册，应该写1 } diff --git a/bsp/ls1cdev/libraries/ls1c_spi.h b/bsp/ls1cdev/libraries/ls1c_spi.h index 8046127de77..bd02dd8d176 100644 --- a/bsp/ls1cdev/libraries/ls1c_spi.h +++ b/bsp/ls1cdev/libraries/ls1c_spi.h @@ -1,61 +1,47 @@ /* - * File : ls1c_spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2017-10-23 Ϊ first version + * 2017-10-23 勤为本 first version */ -// Ӳspiӿڵͷļ +// 硬件spi接口的头文件 #ifndef __OPENLOONGSON_SPI_H #define __OPENLOONGSON_SPI_H -// SPIģ +// SPI模块编号 #define LS1C_SPI_0 (0) #define LS1C_SPI_1 (1) -// Ƭѡ +// 片选 #define LS1C_SPI_CS_0 (0) #define LS1C_SPI_CS_1 (1) #define LS1C_SPI_CS_2 (2) #define LS1C_SPI_CS_3 (3) -// ʱӼԺλ +// 时钟极性和相位 #define SPI_CPOL_1 (1) #define SPI_CPOL_0 (0) #define SPI_CPHA_1 (1) #define SPI_CPHA_0 (0) -// Ĵƫ -#define LS1C_SPI_SPCR_OFFSET (0) // ƼĴ -#define LS1C_SPI_SPSR_OFFSET (1) // ״̬Ĵ -#define LS1C_SPI_TxFIFO_OFFSET (2) // ͵ݼĴݼĴƫͬ -#define LS1C_SPI_RxFIFO_OFFSET (2) // յݼĴ뷢ݼĴƫͬ -#define LS1C_SPI_SPER_OFFSET (3) // ⲿĴ -#define LS1C_SPI_SFC_PARAM_OFFSET (4) // ƼĴ -#define LS1C_SPI_SFC_SOFTCS_OFFSET (5) // ƬѡƼĴ -#define LS1C_SPI_SFC_TIMING_OFFSET (6) // ʱƼĴ +// 寄存器偏移 +#define LS1C_SPI_SPCR_OFFSET (0) // 控制寄存器 +#define LS1C_SPI_SPSR_OFFSET (1) // 状态寄存器 +#define LS1C_SPI_TxFIFO_OFFSET (2) // 发送的数据寄存器，与接收数据寄存器的偏移相同 +#define LS1C_SPI_RxFIFO_OFFSET (2) // 接收的数据寄存器，与发送数据寄存器的偏移相同 +#define LS1C_SPI_SPER_OFFSET (3) // 外部寄存器 +#define LS1C_SPI_SFC_PARAM_OFFSET (4) // 参数控制寄存器 +#define LS1C_SPI_SFC_SOFTCS_OFFSET (5) // 片选控制寄存器 +#define LS1C_SPI_SFC_TIMING_OFFSET (6) // 时序控制寄存器 -// ĴSPCRеλ +// 寄存器SPCR中的位域 #define LS1C_SPI_SPCR_SPIE_BIT (7) #define LS1C_SPI_SPCR_SPIE_MASK (0x01 << LS1C_SPI_SPCR_SPIE_BIT) #define LS1C_SPI_SPCR_SPE_BIT (6) @@ -67,75 +53,75 @@ #define LS1C_SPI_SPCR_SPR_BIT (0) #define LS1C_SPI_SPCR_SPR_MASK (0x03 << LS1C_SPI_SPCR_SPR_BIT) -// ĴSPSRеλ +// 寄存器SPSR中的位域 #define LS1C_SPI_SPSR_SPIF_BIT (7) #define LS1C_SPI_SPSR_SPIF_MASK (0x01 << LS1C_SPI_SPSR_SPIF_BIT) #define LS1C_SPI_SPSR_WCOL_BIT (6) #define LS1C_SPI_SPSR_WCOL_MASK (0x01 << LS1C_SPI_SPSR_WCOL_BIT) -// ĴSPERеλ +// 寄存器SPER中的位域 #define LS1C_SPI_SPER_SPRE_BIT (0) #define LS1C_SPI_SPER_SPRE_MASK (0x3 << LS1C_SPI_SPER_SPRE_BIT) -// ĴSFC_SOFTCSλ +// 寄存器SFC_SOFTCS的位域 #define LS1C_SPI_SFC_SOFTCS_CSN_BIT (4) #define LS1C_SPI_SFC_SOFTCS_CSN_MASK (0x0f << LS1C_SPI_SFC_SOFTCS_CSN_BIT) #define LS1C_SPI_SFC_SOFTCS_CSEN_BIT (0) #define LS1C_SPI_SFC_SOFTCS_CSEN_MASK (0x0f << LS1C_SPI_SFC_SOFTCS_CSEN_BIT) -// ͳʱֵ +// 发送超时的门限值 #define LS1C_SPI_TX_TIMEOUT (20000) /* - * ȡָSPIģĻַ - * @SPIx SPIģı + * 获取指定SPI模块的基地址 + * @SPIx SPI模块的编号 */ -inline void *ls1c_spi_get_base(unsigned char SPIx); +void *ls1c_spi_get_base(unsigned char SPIx); /* - * ʱ - * @spi_base ַ - * @max_hz Ƶʣλhz + * 设置时钟 + * @spi_base 基地址 + * @max_hz 最大频率，单位hz */ void ls1c_spi_set_clock(void *spi_base, unsigned long max_hz); /* - * ͨģʽ(ʱӼԺλ) - * @spi_base ַ - * @cpol ʱӼ - * @cpha ʱλ + * 设置通信模式(时钟极性和相位) + * @spi_base 基地址 + * @cpol 时钟极性 + * @cpha 时钟相位 */ void ls1c_spi_set_mode(void *spi_base, unsigned char cpol, unsigned char cpha); /* - * ָƬѡΪָ״̬ - * @spi_base ַ - * @cs Ƭѡ - * @new_status Ƭѡŵ״̬ȡֵΪ01ߵƽ͵ƽ + * 设置指定片选为指定状态 + * @spi_base 基地址 + * @cs 片选 + * @new_status 片选引脚的新状态，取值为0或1，即高电平或低电平 */ void ls1c_spi_set_cs(void *spi_base, unsigned char cs, int new_status); /* - * ָͨSPIͽһֽ - * ע⣬ڶϵͳУ˺Ҫ⡣ - * ֤ںij豸շijֽڵĹУܱлͬʱͬһSPIϵĴ豸ͨ - * Ϊо1cÿ·SPIϿܽвͬĴ豸ͨƵʡģʽȿܲͬ - * @spi_base ַ - * @tx_ch ͵ - * @ret յ + * 通过指定SPI发送接收一个字节 + * 注意，在多任务的系统中，此函数需要互斥。 + * 即保证在和某个从设备收发某个字节的过程中，不能被切换到其它任务同时与另外的在同一个SPI总线上的从设备通信 + * 因为龙芯1c的每路SPI上可能接有不同的从设备，通信频率、模式等可能不同 + * @spi_base 基地址 + * @tx_ch 待发送的数据 + * @ret 收到的数据 */ unsigned char ls1c_spi_txrx_byte(void *spi_base, unsigned char tx_ch); /* - * ӡָSPIģмĴֵ - * @spi_base ַ + * 打印指定SPI模块的所有寄存器的值 + * @spi_base 基地址 */ void ls1c_spi_print_all_regs_info(void *spi_base); diff --git a/bsp/ls1cdev/libraries/ls1c_timer.c b/bsp/ls1cdev/libraries/ls1c_timer.c index 0075e6e3f6b..11cadf18aaf 100644 --- a/bsp/ls1cdev/libraries/ls1c_timer.c +++ b/bsp/ls1cdev/libraries/ls1c_timer.c @@ -1,6 +1,15 @@ + /* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * first version + */ // ӲʱԴ - +#include #include "ls1c_public.h" #include "ls1c_pin.h" #include "ls1c_clock.h" @@ -147,8 +156,6 @@ void timer_stop(timer_info_t *timer_info) return ; } - - /* * ȡʱӳʼڵʱ(ʵּʱ)λns * @timer_info Ӳʱ @@ -172,13 +179,11 @@ unsigned long timer_get_time_ns(timer_info_t *timer_info) */ timer_clk = clk_get_apb_rate(); time_ns = (cntr * 1000 ) / (timer_clk /1000000); -// rt_kprintf("[%s] time_us=%lu, cntr=%d, timer_clk=%d\n", __FUNCTION__, time_ns, cntr, timer_clk); +// printf("[%s] time_us=%lu, cntr=%d, timer_clk=%d\n", __FUNCTION__, time_ns, cntr, timer_clk); return time_ns; } - - /* * ӡtimerؼĴֵ * @timer_info Ӳʱ @@ -188,7 +193,7 @@ void timer_print_regs(timer_info_t *timer_info) unsigned int timer_reg_base = 0; timer_reg_base = timer_get_reg_base(timer_info->timer); - rt_kprintf("CNTR=0x%x, HRC=0x%x, LRC=0x%x, CTRL=0x%x\n", + printf("CNTR=0x%x, HRC=0x%x, LRC=0x%x, CTRL=0x%x\n", reg_read_32((volatile unsigned int *)(timer_reg_base + LS1C_PWM_CNTR)), reg_read_32((volatile unsigned int *)(timer_reg_base + LS1C_PWM_HRC)), reg_read_32((volatile unsigned int *)(timer_reg_base + LS1C_PWM_LRC)), @@ -197,4 +202,100 @@ void timer_print_regs(timer_info_t *timer_info) return ; } +/* + * ʱж + * @timer_info ʱϢ + */ +void timer_int_clr(timer_info_t *timer_info) +{ + unsigned int timer_reg_base = 0; // Ĵַ + unsigned int ctrl ; + + // ж + if (NULL == timer_info) + { + return ; + } + timer_reg_base = timer_get_reg_base(timer_info->timer); // ȡĴַ + ctrl = reg_read_32((volatile unsigned int *)(timer_reg_base + LS1C_PWM_CTRL)); + ctrl = ctrl | (1<timer); // ȡĴַ + ctrl = reg_read_32((volatile unsigned int *)(timer_reg_base + LS1C_PWM_CTRL)); + ctrl = ctrl | (1<time_ns / 1000); // 1000000000Ϊ10000001000 + l_value = MIN(l_value, TIMER_COUNTER_MAX); + h_value = (timer_clk / 1000000) * (timer_info->time_h_ns / 1000); // 1000000000Ϊ10000001000 + h_value = MIN(h_value, l_value); + + // ƼĴϢ + ctrl = (lrc << LS1C_PWM_INT_LRC_EN) + | (hrc << LS1C_PWM_INT_HRC_EN) + | (0 << LS1C_PWM_CNTR_RST) + | (0 << LS1C_PWM_INT_SR) + | (1 << LS1C_PWM_INTEN) + | (1 << LS1C_PWM_SINGLE) + | (1 << LS1C_PWM_OE) + | (1 << LS1C_PWM_CNT_EN); + + // øĴ + timer_reg_base = timer_get_reg_base(timer_info->timer); // ȡĴַ + reg_write_32(0, (volatile unsigned int *)(timer_reg_base + LS1C_PWM_HRC)); + reg_write_32(l_value--, (volatile unsigned int *)(timer_reg_base + LS1C_PWM_LRC)); + reg_write_32(h_value--, (volatile unsigned int *)(timer_reg_base + LS1C_PWM_HRC)); + reg_write_32(0, (volatile unsigned int *)(timer_reg_base + LS1C_PWM_CNTR)); + reg_write_32(ctrl, (volatile unsigned int *)(timer_reg_base + LS1C_PWM_CTRL)); + + return ; +} diff --git a/bsp/ls1cdev/libraries/ls1c_timer.h b/bsp/ls1cdev/libraries/ls1c_timer.h index df38c705f5f..9f3f86d5d5a 100644 --- a/bsp/ls1cdev/libraries/ls1c_timer.h +++ b/bsp/ls1cdev/libraries/ls1c_timer.h @@ -1,3 +1,12 @@ + /* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * first version + */ // Ӳʱͷļ @@ -22,18 +31,16 @@ typedef enum typedef struct { ls1c_timer_t timer; // Ӳʱ - unsigned long time_ns; // ʱʱ + unsigned long time_ns; // Ͷʱʱ + unsigned long time_h_ns; // ߶ʱʱ }timer_info_t; - - /* * ʼʱʼʱ * @timer_info ʱͶʱʱϢ */ void timer_init(timer_info_t *timer_info); - /* * жָʱǷʱ * @timer_info ʱ @@ -41,15 +48,12 @@ void timer_init(timer_info_t *timer_info); */ BOOL timer_is_time_out(timer_info_t *timer_info); - /* * ֹͣʱ * @timer_info ʱ */ void timer_stop(timer_info_t *timer_info); - - /* * ȡʱӳʼڵʱ(ʵּʱ)λns * @timer_info Ӳʱ @@ -57,13 +61,29 @@ void timer_stop(timer_info_t *timer_info); */ unsigned long timer_get_time_ns(timer_info_t *timer_info); - /* * ӡtimerؼĴֵ * @timer_info Ӳʱ */ void timer_print_regs(timer_info_t *timer_info); +/* + * ʱж + * @timer_info ʱϢ + */ +void timer_int_clr(timer_info_t *timer_info); +/* + * ʱ + * @timer_info ʱϢ + */ +void timer_cnt_clr(timer_info_t *timer_info); + +/* + * ʼʱʼж϶ʱ + * @timer_info ʱͶʱʱϢ + * @hrc ж lrc ж Ϊ1򿪣Ϊ0ر +*/ +void timer_int_init(timer_info_t *timer_info, int hrc, int lrc); #endif diff --git a/bsp/ls1cdev/libraries/ls1c_uart.c b/bsp/ls1cdev/libraries/ls1c_uart.c index baa3b6e3ac6..fac2010964a 100644 --- a/bsp/ls1cdev/libraries/ls1c_uart.c +++ b/bsp/ls1cdev/libraries/ls1c_uart.c @@ -1,3 +1,12 @@ + /* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * first version + */ // 串口相关源码 #include diff --git a/bsp/ls1cdev/libraries/ls1c_uart.h b/bsp/ls1cdev/libraries/ls1c_uart.h index 7d630336848..8d017dd7673 100644 --- a/bsp/ls1cdev/libraries/ls1c_uart.h +++ b/bsp/ls1cdev/libraries/ls1c_uart.h @@ -1,3 +1,12 @@ + /* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * first version + */ // 串口相关头文件 diff --git a/bsp/ls1cdev/rtconfig.h b/bsp/ls1cdev/rtconfig.h index 889d051eef9..7e140a731ce 100644 --- a/bsp/ls1cdev/rtconfig.h +++ b/bsp/ls1cdev/rtconfig.h @@ -124,6 +124,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_CAN /* RT_CAN_USING_HDR is not set */ /* RT_USING_HWTIMER is not set */ diff --git a/bsp/mb9bf500r/rtconfig.py b/bsp/mb9bf500r/rtconfig.py index 8b325ab1fc8..24ae26d0ab1 100644 --- a/bsp/mb9bf500r/rtconfig.py +++ b/bsp/mb9bf500r/rtconfig.py @@ -18,8 +18,10 @@ PLATFORM = 'armcc' EXEC_PATH = 'C:/Keil' elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + print('================ERROR============================') + print('Not support iar yet!') + print('=================================================') + exit(0) if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') diff --git a/bsp/mb9bf506r/rtconfig.h b/bsp/mb9bf506r/rtconfig.h index fa8f5a30140..9499045fd18 100644 --- a/bsp/mb9bf506r/rtconfig.h +++ b/bsp/mb9bf506r/rtconfig.h @@ -68,6 +68,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // #define RT_USING_UART0_0 // diff --git a/bsp/mini4020/rtconfig.h b/bsp/mini4020/rtconfig.h index 9385fe0056b..bef31bc1a78 100644 --- a/bsp/mini4020/rtconfig.h +++ b/bsp/mini4020/rtconfig.h @@ -63,6 +63,7 @@ /* SECTION: Device System */ /* Using Device System */ #define RT_USING_DEVICE +#define RT_USING_DEVICE_IPC /* SECTION: Console options */ /* the buffer size of console */ diff --git a/bsp/nrf51822/rtconfig.h b/bsp/nrf51822/rtconfig.h index 8731f29c303..b41bbdadfaf 100644 --- a/bsp/nrf51822/rtconfig.h +++ b/bsp/nrf51822/rtconfig.h @@ -68,6 +68,7 @@ #define RT_USING_DEVICE_IPC // //#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* SECTION: Console options */ #define RT_USING_CONSOLE diff --git a/bsp/nrf52832/rtconfig.h b/bsp/nrf52832/rtconfig.h index b8710f31c83..64349ec5311 100644 --- a/bsp/nrf52832/rtconfig.h +++ b/bsp/nrf52832/rtconfig.h @@ -70,6 +70,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* SECTION: Console options */ #define RT_USING_CONSOLE diff --git a/bsp/nuvoton_m05x/.config b/bsp/nuvoton_m05x/.config index 38716c09424..07830e5c366 100644 --- a/bsp/nuvoton_m05x/.config +++ b/bsp/nuvoton_m05x/.config @@ -104,6 +104,7 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/nuvoton_m05x/rtconfig.h b/bsp/nuvoton_m05x/rtconfig.h index 4d5ab6b2015..db3cc679c8a 100644 --- a/bsp/nuvoton_m05x/rtconfig.h +++ b/bsp/nuvoton_m05x/rtconfig.h @@ -96,6 +96,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/nuvoton_m451/rtconfig.h b/bsp/nuvoton_m451/rtconfig.h index 58cdfdcb24d..cb4868725c3 100644 --- a/bsp/nuvoton_m451/rtconfig.h +++ b/bsp/nuvoton_m451/rtconfig.h @@ -65,6 +65,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* SECTION: Console options */ #define RT_USING_CONSOLE diff --git a/bsp/nuvoton_m487/.config b/bsp/nuvoton_m487/.config new file mode 100644 index 00000000000..2e12793338a --- /dev/null +++ b/bsp/nuvoton_m487/.config @@ -0,0 +1,329 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +# CONFIG_RT_USING_MESSAGEQUEUE is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=1024 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +# CONFIG_DFS_USING_WORKDIR is not set +CONFIG_DFS_FILESYSTEMS_MAX=1 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=32 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=64 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP210 is not set +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=19 +CONFIG_RT_LWIP_PBUF_NUM=0 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=19 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=2920 +CONFIG_RT_LWIP_TCP_WND=2920 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=768 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_DEBUG is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set + +# +# RT-Thread online packages +# + +# +# system packages +# + +# +# RT-Thread GUI Engine +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_IPERF is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set diff --git a/bsp/nuvoton_m487/Kconfig b/bsp/nuvoton_m487/Kconfig new file mode 100644 index 00000000000..1b46858ab66 --- /dev/null +++ b/bsp/nuvoton_m487/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +source "$BSP_DIR/driver/Kconfig" + diff --git a/bsp/nuvoton_m487/README.md b/bsp/nuvoton_m487/README.md new file mode 100644 index 00000000000..ca6e82c859f --- /dev/null +++ b/bsp/nuvoton_m487/README.md @@ -0,0 +1,66 @@ +# NuMaker-PFM-M487 + +## 1. 简介 + +核心板板载主要资源如下： + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| M487JIDAE | +|CPU| ARM Cortex-M4 | +|主频| 192MHz | +|片内SRAM| 160kB | +|片内Flash| 512kB | +|SPI FLASH| W25Q32 | +|PHY| IP101GR | +|Audio Codec| NAU88L25 | + + +## 2. 编译说明 + +板级包支持MDK4工程生成、GCC编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | ---------------------------- | +| MDK4 | 4.73 | +| GCC | GCC 5.4.1 20160919 (release) | + +使用MDK4打开工程需要安装Nu-Link_Keil_Driver + +## 3. 烧写及执行 + +连接好串口，可以使用115200-N-8-1的配置方式连接到设备上。设备使用的串口引脚是：`[Tx:PB13 Rx:PB12]` + +当正确编译产生出rtthread.bin映像文件后，可以使用NU-link或者JLINK下载 + +### 3.1 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | UART0| + +### 4.1 IO在板级支持包中的映射情况 + +| IO号 | 板级包中的定义 | +| -- | -- | +| PH0 | LED_R | +| PH1 | LED_Y | +| PH2 | LED_G | +| PG15 | KEY2 | +| PF11| KEY3 | + +## 5. 联系人信息 + +维护人：[bluebear233](https://github.com/bluebear233) + +## 6. 参考 + +* 板子[数据手册][1] +* 芯片[数据手册][2] + + [1]: http://www.nuvoton.com/resource-files/UM_NuMaker-PFM-M487_User_Manual_EN_Rev1.00.pdf + [2]: http://www.nuvoton.com/resource-files/TRM_M480_Series_EN_Rev1.01.pdf \ No newline at end of file diff --git a/bsp/nuvoton_m487/SConscript b/bsp/nuvoton_m487/SConscript new file mode 100644 index 00000000000..fe0ae941ae9 --- /dev/null +++ b/bsp/nuvoton_m487/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton_m487/SConstruct b/bsp/nuvoton_m487/SConstruct new file mode 100644 index 00000000000..28e42797639 --- /dev/null +++ b/bsp/nuvoton_m487/SConstruct @@ -0,0 +1,35 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-m487.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nuvoton_m487/applications/SConscript b/bsp/nuvoton_m487/applications/SConscript new file mode 100644 index 00000000000..9ffdbcd0f9f --- /dev/null +++ b/bsp/nuvoton_m487/applications/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton_m487/applications/main.c b/bsp/nuvoton_m487/applications/main.c new file mode 100644 index 00000000000..01c276cb28c --- /dev/null +++ b/bsp/nuvoton_m487/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include + +int main(int argc, char** argv) +{ + printf("Hello RT-Thread!\n"); + + return 0; +} diff --git a/bsp/nuvoton_m487/applications/mnt.c b/bsp/nuvoton_m487/applications/mnt.c new file mode 100644 index 00000000000..d528a7424d2 --- /dev/null +++ b/bsp/nuvoton_m487/applications/mnt.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include + +int mnt_init(void) +{ + return 0; +} diff --git a/bsp/nuvoton_m487/driver/Kconfig b/bsp/nuvoton_m487/driver/Kconfig new file mode 100644 index 00000000000..1a4baf536d7 --- /dev/null +++ b/bsp/nuvoton_m487/driver/Kconfig @@ -0,0 +1 @@ + diff --git a/bsp/nuvoton_m487/driver/SConscript b/bsp/nuvoton_m487/driver/SConscript new file mode 100644 index 00000000000..4de25c676a0 --- /dev/null +++ b/bsp/nuvoton_m487/driver/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Split(''' +board.c +drv_uart.c +''') +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton_m487/driver/board.c b/bsp/nuvoton_m487/driver/board.c new file mode 100644 index 00000000000..a80024b0b72 --- /dev/null +++ b/bsp/nuvoton_m487/driver/board.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + +#include +#include +#include +#include "NuMicro.h" +#include "drv_uart.h" +#include "board.h" + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +extern int __ram_top; +#endif + +/** + * This function will initial Clock tree. + */ +static void clock_init(void) +{ + /* Unlock protected registers */ + SYS_UnlockReg(); + + SystemInit(); + + /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */ + PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk); + + /* Enable External XTAL (4~24 MHz) */ + CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); + + /* Waiting for 12MHz clock ready */ + CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk); + + /* Switch HCLK clock source to HXT */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1)); + + /* Set core clock as PLL_CLOCK from PLL */ + CLK_SetCoreClock(FREQ_192MHZ); + + /* Set both PCLK0 and PCLK1 as HCLK/4 */ + CLK->PCLKDIV = CLK_PCLKDIV_PCLK0DIV4 | CLK_PCLKDIV_PCLK1DIV4; + + SystemCoreClockUpdate(); + + /* Lock protected registers */ + SYS_LockReg(); +} + +/** + * This function will initial M487 board. + */ +void rt_hw_board_init(void) +{ + clock_init(); + +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)SRAM_END); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END); +#else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)&__ram_top); +#endif +#endif /* RT_USING_HEAP */ + + rt_hw_uart_init(); + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + NVIC_SetPriorityGrouping(7); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void rt_hw_cpu_reset(void) +{ + SYS_UnlockReg(); + + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} diff --git a/bsp/nuvoton_m487/driver/board.h b/bsp/nuvoton_m487/driver/board.h new file mode 100644 index 00000000000..515ab1bb395 --- /dev/null +++ b/bsp/nuvoton_m487/driver/board.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +// Internal SRAM memory size[Kbytes] <8-64> +#define SRAM_SIZE (160) +#define SRAM_END (0x20000000 + SRAM_SIZE * 1024) + +#define RT_UART_485_MODE 1 +#define RT_UART_FLOW_CTS_CTRL 2 +#define RT_UART_FLOW_RTS_CTRL 3 +#define RT_UART_CLEAR_BUF 4 + +void rt_hw_pdma_init(void); +void rt_hw_uart_handle(void); +void rt_hw_sc_init(void); +void rt_hw_usart_init(void); +void rt_hw_uusart_init(void); +void rt_hw_io_init(void); +void phy_error_led(void); + +unsigned char *eth_get_default_mac(void); +void eth_set_mac(const unsigned char * mac); +void wdt_reload(void); +unsigned int get_uid(void); + +#endif /* BOARD_H_ */ diff --git a/bsp/nuvoton_m487/driver/drv_uart.c b/bsp/nuvoton_m487/driver/drv_uart.c new file mode 100644 index 00000000000..a7ab018f8d0 --- /dev/null +++ b/bsp/nuvoton_m487/driver/drv_uart.c @@ -0,0 +1,405 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + + +#include +#include +#include +#include "NuMicro.h" + +/* Private Define ---------------------------------------------------------------*/ +#define USEING_UART0 //Tx:PB13 Rx:PB12 + +/* Private Typedef --------------------------------------------------------------*/ +struct usart +{ + rt_serial_t dev; + UART_T *usart_base; +}; +typedef struct usart* usart_t; + +/* Private functions ------------------------------------------------------------*/ + + +static rt_err_t usart_gpio_configure(struct rt_serial_device *serial); +static rt_err_t usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t usart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int usart_send(struct rt_serial_device *serial, char c); +static int usart_receive(struct rt_serial_device *serial); +static void rt_hw_uart_register(usart_t uart, UART_T *uart_base, + char *name); +static void uart_isr(usart_t serial); + +/* Private Variables ------------------------------------------------------------*/ +static const struct rt_uart_ops m487_uart_ops = +{ usart_configure, usart_control, usart_send, usart_receive, + RT_NULL }; + +static const struct serial_configure m487_uart_default_config = +RT_SERIAL_CONFIG_DEFAULT; + +#ifdef USEING_UART0 +struct usart uart0; +#endif + +/* Interrupt Handle Funtion ----------------------------------------------------*/ +#ifdef USEING_UART0 +/* 串口0 中断入口 */ +void UART0_IRQHandler(void) +{ + uart_isr(&uart0); +} +#endif + +/** + * 中断处理函数 + */ +static void uart_isr(usart_t serial) +{ + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + // 获取中断事件 + uint32_t u32IntSts= uart_base->INTSTS; + + // 接收中断 + if(u32IntSts & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) + { + rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND); + } + +} + +/** + * 串口端口配置 + */ +static rt_err_t usart_gpio_configure(struct rt_serial_device *serial) +{ + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + switch((uint32_t)uart_base) + { + case UART0_BASE: + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB12MFP_Msk | SYS_GPB_MFPH_PB13MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB12MFP_UART0_RXD | SYS_GPB_MFPH_PB13MFP_UART0_TXD); + break; + + default: + rt_kprintf("unknow uart module\n"); + RT_ASSERT(0); + } + + return RT_EOK; +} + +/** + * 串口配置 + */ +static rt_err_t usart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + uint32_t uart_module = 0; + uint32_t uart_word_len = 0; + uint32_t uart_stop_bit = 0; + uint32_t uart_parity = 0; + IRQn_Type uart_irq_channel = 0; + + switch((uint32_t)uart_base) + { + case UART0_BASE: + uart_module = UART0_MODULE; + uart_irq_channel = UART0_IRQn; + break; + + default: + rt_kprintf("unknow uart module\n"); + RT_ASSERT(0); + } + + /* Enable IP clock */ + CLK_EnableModuleClock(uart_module); + + /* Select IP clock source */ + CLK_SetModuleClock(uart_module, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1)); + + /* check baudrate */ + RT_ASSERT(cfg->baud_rate != 0); + + /* check word len */ + switch(cfg->data_bits) + { + case DATA_BITS_5: + uart_word_len = UART_WORD_LEN_5; + break; + + case DATA_BITS_6: + uart_word_len = UART_WORD_LEN_6; + break; + + case DATA_BITS_7: + uart_word_len = UART_WORD_LEN_7; + break; + + case DATA_BITS_8: + uart_word_len = UART_WORD_LEN_8; + break; + + default: + rt_kprintf("unsupose data len"); + RT_ASSERT(0); + } + + /* check stop bit */ + switch(cfg->stop_bits) + { + case STOP_BITS_1: + uart_stop_bit = UART_STOP_BIT_1; + break; + + case STOP_BITS_2: + uart_stop_bit = UART_STOP_BIT_2; + break; + + default: + rt_kprintf("unsupose stop bit"); + RT_ASSERT(0); + } + + /* check stop bit */ + switch(cfg->parity) + { + case PARITY_NONE: + uart_parity = UART_PARITY_NONE; + break; + + case PARITY_ODD: + uart_parity = UART_PARITY_ODD; + break; + + case PARITY_EVEN: + uart_parity = UART_PARITY_EVEN; + break; + + default: + rt_kprintf("unsupose parity"); + RT_ASSERT(0); + } + + /* Open uart */ + { + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div = 0ul; + + if(uart_base == (UART_T*)UART0 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart_base == (UART_T*)UART1 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart_base == (UART_T*)UART2 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart_base == (UART_T*)UART3 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart_base == (UART_T*)UART4 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart_base == (UART_T*)UART5 ) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + /* Select UART function */ + uart_base->FUNCSEL = UART_FUNCSEL_UART; + + /* Set UART line configuration */ + uart_base->LINE = uart_word_len | uart_stop_bit | uart_parity; + + /* Set UART Rx and RTS trigger level */ + uart_base->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk); + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Set UART baud rate */ + if(cfg->baud_rate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), cfg->baud_rate); + + if(u32Baud_Div > 0xFFFFul) + { + uart_base->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), cfg->baud_rate)); + } + else + { + uart_base->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } + } + + /* config nvic */ + NVIC_EnableIRQ(uart_irq_channel); + + /* config gpio */ + usart_gpio_configure(serial); + + return RT_EOK; +} + +/** + * 串口中断控制 + */ +static rt_err_t usart_control(struct rt_serial_device *serial, + int cmd, void *arg) +{ + rt_err_t result = RT_EOK; + rt_uint32_t flag; + + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + switch ((uint32_t) arg) + { + case RT_DEVICE_FLAG_INT_RX: + flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + UART_DISABLE_INT(uart_base, flag); + break; + case RT_DEVICE_CTRL_SET_INT: + UART_ENABLE_INT(uart_base, flag); + break; + default: + RT_ASSERT(0); + } + break; +// TODO 完善DMA接口 +// case RT_DEVICE_FLAG_DMA_TX: +// USART_DMACmd(dev->usart_base, USART_DMAReq_Tx, ENABLE); +// stm32_uart_tx_dma_configure(dev, RT_TRUE); +// stm32_uart_tx_dma_nvic(dev, RT_TRUE); +// break; + default: + RT_ASSERT(0) + ; + } + + return result; +} + +/** + * 串口发送函数 + */ +static int usart_send(struct rt_serial_device *serial, char c) +{ + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + // 等待FIFO 发送 + while(uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk); + + // 发送字符 + uart_base->DAT = c; + + return 1; +} + +/** + * 串口接收函数 + */ +static int usart_receive(struct rt_serial_device *serial) +{ + // 获取串口基地址 + UART_T *uart_base = ((usart_t)serial)->usart_base; + + // 如果FIFO 为空返回 + if(uart_base->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + { + return -1; + } + + return UART_READ(uart_base); +} + +/** + * @brief 串口设备注册 + * @param uart : UART设备结构体 + * @param uart_base : STM32 UART外设基地址 + * @param name : STM32 UART设备名 + * @param tx_dma_channel : STM32 UART TX的DMA通道基地址(可选) + */ +static void rt_hw_uart_register(usart_t usart, UART_T * uart_base, char *name) +{ + rt_uint32_t flag; + RT_ASSERT(usart != RT_NULL); + RT_ASSERT(uart_base != RT_NULL); + + // 没有定义对应的硬件I2C + if (!(uart_base == UART0 || uart_base == UART1 || uart_base == UART2 + || uart_base == UART3 || uart_base == UART4 || uart_base == UART5)) + { + RT_ASSERT(0); + } + + usart->usart_base = uart_base; + usart->dev.ops = &m487_uart_ops; + usart->dev.config = m487_uart_default_config; + + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; + + rt_hw_serial_register(&usart->dev, name, + flag, RT_NULL); +} + +/** + * 硬件串口注册 + */ +int rt_hw_uart_init(void) +{ +#ifdef USEING_UART0 + rt_hw_uart_register(&uart0, UART0, "uart0"); +#endif + + return 0; +} \ No newline at end of file diff --git a/bsp/nuvoton_m487/driver/drv_uart.h b/bsp/nuvoton_m487/driver/drv_uart.h new file mode 100644 index 00000000000..9eb0077e2fb --- /dev/null +++ b/bsp/nuvoton_m487/driver/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_common_tables.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_common_tables.h new file mode 100644 index 00000000000..8742a569915 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. October 2015 +* $Revision: V.1.4.5 a +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +/* extern const q31_t realCoefAQ31[1024]; */ +/* extern const q31_t realCoefBQ31[1024]; */ +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_const_structs.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_const_structs.h new file mode 100644 index 00000000000..726d06eb692 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_math.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_math.h new file mode 100644 index 00000000000..d33f8a9b3b5 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/arm_math.h @@ -0,0 +1,7154 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 20. October 2015 +* $Revision: V1.4.5 b +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 00000000000..74c49c67def --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc_V6.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc_V6.h new file mode 100644 index 00000000000..cd13240ce36 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_gcc.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 00000000000..bb89fbba9e4 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 00000000000..711dad55170 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0plus.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 00000000000..b04aa390532 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm3.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 00000000000..b4ac4c7b05a --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm4.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 00000000000..dc840ebf222 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm7.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 00000000000..3b7530ad505 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmFunc.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmFunc.h new file mode 100644 index 00000000000..652a48af07a --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmInstr.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmInstr.h new file mode 100644 index 00000000000..f474b0e6f36 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmSimd.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmSimd.h new file mode 100644 index 00000000000..66bf5c2a725 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc000.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 00000000000..514dbd81b9f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc300.h b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 00000000000..8bd18aa318a --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton_m487/libraries/CMSIS/SConscript b/bsp/nuvoton_m487/libraries/CMSIS/SConscript new file mode 100644 index 00000000000..904fca41463 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/CMSIS/SConscript @@ -0,0 +1,16 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +""") + +path = [cwd + '/Include',] + +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/M480.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/M480.h new file mode 100644 index 00000000000..c185641bec9 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/M480.h @@ -0,0 +1,683 @@ +/**************************************************************************//** + * @file M480.h + * @version V1.00 + * @brief M480 peripheral access layer header file. + * This file contains all the peripheral register's definitions, + * bits definitions and memory mapping for NuMicro M480 MCU. + * + * @copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +/** + \mainpage NuMicro M480 Driver Reference Guide + * + * Introduction + * + * This user manual describes the usage of M480 Series MCU device driver + * + * Disclaimer + * + * The Software is furnished "AS IS", without warranty as to performance or results, and + * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all + * warranties, express, implied or otherwise, with regard to the Software, its use, or + * operation, including without limitation any and all warranties of merchantability, fitness + * for a particular purpose, and non-infringement of intellectual property rights. + * + * Important Notice + * + * Nuvoton Products are neither intended nor warranted for usage in systems or equipment, + * any malfunction or failure of which may cause loss of human life, bodily injury or severe + * property damage. Such applications are deemed, "Insecure Usage". + * + * Insecure usage includes, but is not limited to: equipment for surgical implementation, + * atomic energy control instruments, airplane or spaceship instruments, the control or + * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal + * instruments, all types of safety devices, and other applications intended to support or + * sustain life. + * + * All Insecure Usage shall be made at customer's risk, and in the event that third parties + * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify + * the damages and liabilities thus incurred by Nuvoton. + * + * Please note that all data and specifications are subject to change without notice. All the + * trademarks of products and companies mentioned in this datasheet belong to their respective + * owners. + * + * Copyright Notice + * + * Copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved. + */ +#ifndef __M480_H__ +#define __M480_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup CMSIS_Device Device CMSIS Definitions + Configuration of the Cortex-M4 Processor and Core Peripherals + @{ +*/ + +/** + * @details Interrupt Number Definition. + */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ + + /****** M480 Specific Interrupt Numbers ********************************************************/ + + BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ + IRC_IRQn = 1, /*!< Internal RC Interrupt */ + PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ + RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ + CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ + RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ + TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */ + WDT_IRQn = 8, /*!< Watchdog timer Interrupt */ + WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */ + EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ + EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ + EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ + EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ + EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ + EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ + GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ + GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ + GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ + GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ + GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ + GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ + QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ + SPI0_IRQn = 23, /*!< SPI0 Interrupt */ + BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ + EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ + EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ + EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ + BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ + EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ + EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ + EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ + TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ + TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ + TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ + TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ + UART0_IRQn = 36, /*!< UART 0 Interrupt */ + UART1_IRQn = 37, /*!< UART 1 Interrupt */ + I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ + I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ + PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */ + DAC_IRQn = 41, /*!< DAC Interrupt */ + ADC0_IRQn = 42, /*!< ADC0 Interrupt */ + ADC1_IRQn = 43, /*!< ADC1 Interrupt */ + ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ + ADC2_IRQn = 46, /*!< ADC2 Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 Interrupt */ + UART2_IRQn = 48, /*!< UART2 Interrupt */ + UART3_IRQn = 49, /*!< UART3 Interrupt */ + SPI1_IRQn = 51, /*!< SPI1 Interrupt */ + SPI2_IRQn = 52, /*!< SPI2 Interrupt */ + USBD_IRQn = 53, /*!< USB device Interrupt */ + USBH_IRQn = 54, /*!< USB host Interrupt */ + USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ + CAN0_IRQn = 56, /*!< CAN0 Interrupt */ + CAN1_IRQn = 57, /*!< CAN1 Interrupt */ + SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ + SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ + SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ + SPI3_IRQn = 62, /*!< SPI3 Interrupt */ + EMAC_TX_IRQn = 66, /*!< Ethernet MAC TX Interrupt */ + EMAC_RX_IRQn = 67, /*!< Ethernet MAC RX Interrupt */ + SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */ + USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */ + I2S0_IRQn = 68, /*!< I2S0 Interrupt */ + OPA_IRQn = 70, /*!< OPA Interrupt */ + CRPT_IRQn = 71, /*!< CRPT Interrupt */ + GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ + EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ + UART4_IRQn = 74, /*!< UART4 Interrupt */ + UART5_IRQn = 75, /*!< UART5 Interrupt */ + USCI0_IRQn = 76, /*!< USCI0 Interrupt */ + USCI1_IRQn = 77, /*!< USCI1 Interrupt */ + BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ + BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ + SPIM_IRQn = 80, /*!< SPIM Interrupt */ + I2C2_IRQn = 82, /*!< I2C2 Interrupt */ + QEI0_IRQn = 84, /*!< QEI0 Interrupt */ + QEI1_IRQn = 85, /*!< QEI1 Interrupt */ + ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ + ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ + GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ + EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ + SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */ + HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */ + USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */ +} +IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0201UL /*!< Core Revision r2p1 */ +#define __NVIC_PRIO_BITS 4UL /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0UL /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1UL /*!< MPU present or not */ +#ifdef __FPU_PRESENT +#undef __FPU_PRESENT +#define __FPU_PRESENT 1UL /*!< FPU present or not */ +#else +#define __FPU_PRESENT 1UL /*!< FPU present or not */ +#endif + +/*@}*/ /* end of group CMSIS_Device */ + + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_M480.h" /* System include file */ +#include + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* Register definitions */ +/******************************************************************************/ + +#include "sys_reg.h" +#include "clk_reg.h" +#include "fmc_reg.h" +#include "gpio_reg.h" +#include "pdma_reg.h" +#include "timer_reg.h" +#include "wdt_reg.h" +#include "wwdt_reg.h" +#include "rtc_reg.h" +#include "epwm_reg.h" +#include "bpwm_reg.h" +#include "qei_reg.h" +#include "ecap_reg.h" +#include "uart_reg.h" +#include "emac_reg.h" +#include "sc_reg.h" +#include "i2s_reg.h" +#include "spi_reg.h" +#include "qspi_reg.h" +#include "spim_reg.h" +#include "i2c_reg.h" +#include "uuart_reg.h" +#include "uspi_reg.h" +#include "ui2c_reg.h" +#include "can_reg.h" +#include "sdh_reg.h" +#include "ebi_reg.h" +#include "usbd_reg.h" +#include "hsusbd_reg.h" +#include "usbh_reg.h" +#include "hsusbh_reg.h" +#include "otg_reg.h" +#include "hsotg_reg.h" +#include "crc_reg.h" +#include "crypto_reg.h" +#include "eadc_reg.h" +#include "dac_reg.h" +#include "acmp_reg.h" +#include "opa_reg.h" + + +/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base + Memory Mapped Structure for Peripherals + @{ + */ +/* Peripheral and SRAM base address */ +#define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */ +#define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */ +#define APBPERIPH_BASE (PERIPH_BASE + (uint32_t)0x00040000) /*!< APB Base Address */ + +/*!< AHB peripherals */ +#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) +#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) +#define NMI_BASE (AHBPERIPH_BASE + 0x00300UL) +#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) +#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200UL) +#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) +#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) +#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL) +#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) +#define HSUSBH_BASE (AHBPERIPH_BASE + 0x1A000UL) +#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000UL) +#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL) +#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL) +#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL) +#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) +#define HSUSBD_BASE (AHBPERIPH_BASE + 0x19000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) +#define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000UL) + +/*!< APB2 peripherals */ +#define WDT_BASE (APBPERIPH_BASE + 0x00000UL) +#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) +#define OPA_BASE (APBPERIPH_BASE + 0x06000UL) +#define I2S_BASE (APBPERIPH_BASE + 0x08000UL) +#define TIMER0_BASE (APBPERIPH_BASE + 0x10000UL) +#define TIMER1_BASE (APBPERIPH_BASE + 0x10100UL) +#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL) +#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL) +#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) +#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) +#define UART0_BASE (APBPERIPH_BASE + 0x30000UL) +#define UART2_BASE (APBPERIPH_BASE + 0x32000UL) +#define UART4_BASE (APBPERIPH_BASE + 0x34000UL) +#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL) +#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL) +#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL) +#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) +#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) + + +/*!< APB1 peripherals */ +#define RTC_BASE (APBPERIPH_BASE + 0x01000UL) +#define EADC_BASE (APBPERIPH_BASE + 0x03000UL) +#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) +#define USBD_BASE (APBPERIPH_BASE + 0x80000UL) +#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL) +#define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL) +#define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL) +#define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL) +#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL) +#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL) +#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) +#define UART1_BASE (APBPERIPH_BASE + 0x31000UL) +#define UART3_BASE (APBPERIPH_BASE + 0x33000UL) +#define UART5_BASE (APBPERIPH_BASE + 0x35000UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) +#define CAN1_BASE (APBPERIPH_BASE + 0x61000UL) +#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL) +#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) +#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) +#define CRPT_BASE (0x50080000UL) +#define SPIM_BASE (0x40007000UL) + +#define SC0_BASE (APBPERIPH_BASE + 0x50000UL) +#define SC1_BASE (APBPERIPH_BASE + 0x51000UL) +#define SC2_BASE (APBPERIPH_BASE + 0x52000UL) +#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL) +#define DACDBG_BASE (APBPERIPH_BASE + 0x07FECUL) +#define OPA0_BASE (APBPERIPH_BASE + 0x06000UL) + +/*@}*/ /* end of group PERIPHERAL_MEM_MAP */ + + +/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer + The Declaration of Peripherals + @{ + */ + +#define SYS ((SYS_T *) SYS_BASE) +#define CLK ((CLK_T *) CLK_BASE) +#define NMI ((NMI_T *) NMI_BASE) +#define PA ((GPIO_T *) GPIOA_BASE) +#define PB ((GPIO_T *) GPIOB_BASE) +#define PC ((GPIO_T *) GPIOC_BASE) +#define PD ((GPIO_T *) GPIOD_BASE) +#define PE ((GPIO_T *) GPIOE_BASE) +#define PF ((GPIO_T *) GPIOF_BASE) +#define PG ((GPIO_T *) GPIOG_BASE) +#define PH ((GPIO_T *) GPIOH_BASE) +#define GPA ((GPIO_T *) GPIOA_BASE) +#define GPB ((GPIO_T *) GPIOB_BASE) +#define GPC ((GPIO_T *) GPIOC_BASE) +#define GPD ((GPIO_T *) GPIOD_BASE) +#define GPE ((GPIO_T *) GPIOE_BASE) +#define GPF ((GPIO_T *) GPIOF_BASE) +#define GPG ((GPIO_T *) GPIOG_BASE) +#define GPH ((GPIO_T *) GPIOH_BASE) +#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE) +#define PDMA ((PDMA_T *) PDMA_BASE) +#define USBH ((USBH_T *) USBH_BASE) +#define HSUSBH ((HSUSBH_T *) HSUSBH_BASE) +#define EMAC ((EMAC_T *) EMAC_BASE) +#define FMC ((FMC_T *) FMC_BASE) +#define SDH0 ((SDH_T *) SDH0_BASE) +#define SDH1 ((SDH_T *) SDH1_BASE) +#define EBI ((EBI_T *) EBI_BASE) +#define CRC ((CRC_T *) CRC_BASE) +#define TAMPER ((TAMPER_T *) TAMPER_BASE) + +#define WDT ((WDT_T *) WDT_BASE) +#define WWDT ((WWDT_T *) WWDT_BASE) +#define RTC ((RTC_T *) RTC_BASE) +#define EADC ((EADC_T *) EADC_BASE) +#define ACMP01 ((ACMP_T *) ACMP01_BASE) + +#define I2S0 ((I2S_T *) I2S_BASE) +#define USBD ((USBD_T *) USBD_BASE) +#define OTG ((OTG_T *) OTG_BASE) +#define HSUSBD ((HSUSBD_T *)HSUSBD_BASE) +#define HSOTG ((HSOTG_T *) HSOTG_BASE) +#define TIMER0 ((TIMER_T *) TIMER0_BASE) +#define TIMER1 ((TIMER_T *) TIMER1_BASE) +#define TIMER2 ((TIMER_T *) TIMER2_BASE) +#define TIMER3 ((TIMER_T *) TIMER3_BASE) +#define EPWM0 ((EPWM_T *) EPWM0_BASE) +#define EPWM1 ((EPWM_T *) EPWM1_BASE) +#define BPWM0 ((BPWM_T *) BPWM0_BASE) +#define BPWM1 ((BPWM_T *) BPWM1_BASE) +#define ECAP0 ((ECAP_T *) ECAP0_BASE) +#define ECAP1 ((ECAP_T *) ECAP1_BASE) +#define QEI0 ((QEI_T *) QEI0_BASE) +#define QEI1 ((QEI_T *) QEI1_BASE) +#define QSPI0 ((QSPI_T *) QSPI0_BASE) +#define SPI0 ((SPI_T *) SPI0_BASE) +#define SPI1 ((SPI_T *) SPI1_BASE) +#define SPI2 ((SPI_T *) SPI2_BASE) +#define SPI3 ((SPI_T *) SPI3_BASE) +#define UART0 ((UART_T *) UART0_BASE) +#define UART1 ((UART_T *) UART1_BASE) +#define UART2 ((UART_T *) UART2_BASE) +#define UART3 ((UART_T *) UART3_BASE) +#define UART4 ((UART_T *) UART4_BASE) +#define UART5 ((UART_T *) UART5_BASE) +#define I2C0 ((I2C_T *) I2C0_BASE) +#define I2C1 ((I2C_T *) I2C1_BASE) +#define I2C2 ((I2C_T *) I2C2_BASE) +#define SC0 ((SC_T *) SC0_BASE) +#define SC1 ((SC_T *) SC1_BASE) +#define SC2 ((SC_T *) SC2_BASE) +#define CAN0 ((CAN_T *) CAN0_BASE) +#define CAN1 ((CAN_T *) CAN1_BASE) +#define CRPT ((CRPT_T *) CRPT_BASE) +#define SPIM ((volatile SPIM_T *) SPIM_BASE) +#define DAC0 ((DAC_T *) DAC0_BASE) +#define DAC1 ((DAC_T *) DAC1_BASE) +#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */ +#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Configuration Struct */ +#define OPA ((OPA_T *) OPA_BASE) +#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */ +#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */ +#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */ +#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Configuration Struct */ + +/*@}*/ /* end of group ERIPHERAL_DECLARATION */ + +/** @addtogroup IO_ROUTINE I/O Routines + The Declaration of I/O Routines + @{ + */ + +typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type +typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type +typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type + +/** + * @brief Get a 8-bit unsigned value from specified address + * @param[in] addr Address to get 8-bit data from + * @return 8-bit unsigned value stored in specified address + */ +#define M8(addr) (*((vu8 *) (addr))) + +/** + * @brief Get a 16-bit unsigned value from specified address + * @param[in] addr Address to get 16-bit data from + * @return 16-bit unsigned value stored in specified address + * @note The input address must be 16-bit aligned + */ +#define M16(addr) (*((vu16 *) (addr))) + +/** + * @brief Get a 32-bit unsigned value from specified address + * @param[in] addr Address to get 32-bit data from + * @return 32-bit unsigned value stored in specified address + * @note The input address must be 32-bit aligned + */ +#define M32(addr) (*((vu32 *) (addr))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outpw(port,value) *((volatile unsigned int *)(port)) = (value) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inpw(port) (*((volatile unsigned int *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outps(port,value) *((volatile unsigned short *)(port)) = (value) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inps(port) (*((volatile unsigned short *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outpb(port,value) *((volatile unsigned char *)(port)) = (value) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inpb(port) (*((volatile unsigned char *)(port))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outp32(port,value) *((volatile unsigned int *)(port)) = (value) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inp32(port) (*((volatile unsigned int *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outp16(port,value) *((volatile unsigned short *)(port)) = (value) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inp16(port) (*((volatile unsigned short *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outp8(port,value) *((volatile unsigned char *)(port)) = (value) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inp8(port) (*((volatile unsigned char *)(port))) + + +/*@}*/ /* end of group IO_ROUTINE */ + +/******************************************************************************/ +/* Legacy Constants */ +/******************************************************************************/ +/** @addtogroup Legacy_Constants Legacy Constants + Legacy Constants + @{ +*/ + +#ifndef NULL +#define NULL (0) ///< NULL pointer +#endif + +#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value +#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value + +#define ENABLE (1UL) ///< Enable, define to use in API parameters +#define DISABLE (0UL) ///< Disable, define to use in API parameters + +/* Define one bit mask */ +#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer +#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer +#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer +#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer +#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer +#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer +#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer +#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer +#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer +#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer +#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer +#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer +#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer +#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer +#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer +#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer +#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer +#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer +#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer +#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer +#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer +#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer +#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer +#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer +#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer +#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer +#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer +#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer +#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer +#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer +#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer +#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer + +/* Byte Mask Definitions */ +#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer +#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer +#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer +#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer + +#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ +#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ +#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ +#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ + +/*@}*/ /* end of group Legacy_Constants */ + + +/******************************************************************************/ +/* Peripheral header files */ +/******************************************************************************/ +#include "sys.h" +#include "clk.h" + +#include "acmp.h" +#include "dac.h" +#include "emac.h" +#include "uart.h" +#include "usci_spi.h" +#include "gpio.h" +#include "ecap.h" +#include "qei.h" +#include "timer.h" +#include "timer_pwm.h" +#include "pdma.h" +#include "crypto.h" +#include "fmc.h" +#include "spim.h" +#include "i2c.h" +#include "i2s.h" +#include "epwm.h" +#include "eadc.h" +#include "bpwm.h" +#include "wdt.h" +#include "wwdt.h" +#include "opa.h" +#include "crc.h" +#include "ebi.h" +#include "usci_i2c.h" +#include "scuart.h" +#include "sc.h" +#include "spi.h" +#include "qspi.h" +#include "can.h" +#include "rtc.h" +#include "usci_uart.h" +#include "sdh.h" +#include "usbd.h" +#include "hsusbd.h" +#include "otg.h" +#include "hsotg.h" + + +#ifdef __cplusplus +} +#endif + +#endif /* __M480_H__ */ + diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/NuMicro.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/NuMicro.h new file mode 100644 index 00000000000..4566f13ab48 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/NuMicro.h @@ -0,0 +1,15 @@ +/**************************************************************************//** + * @file NuMicro.h + * @version V1.00 + * @brief NuMicro peripheral access layer header file. + * + * @copyright (C) 2017-2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NUMICRO_H__ +#define __NUMICRO_H__ + +#include "M480.h" + +#endif /* __NUMICRO_H__ */ + + diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/acmp_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/acmp_reg.h new file mode 100644 index 00000000000..aa68daf6a50 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/acmp_reg.h @@ -0,0 +1,239 @@ +/**************************************************************************//** + * @file acmp_reg.h + * @version V1.00 + * @brief ACMP register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ACMP_REG_H__ +#define __ACMP_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup ACMP Analog Comparator Controller(ACMP) + Memory Mapped Structure for ACMP Controller +@{ */ + +typedef struct +{ + + + /** + * @var ACMP_T::CTL + * Offset: 0x00~0x04 Analog Comparator 0/1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPEN |Comparator Enable Bit + * | | |0 = Comparator x Disabled. + * | | |1 = Comparator x Enabled. + * |[1] |ACMPIE |Comparator Interrupt Enable Bit + * | | |0 = Comparator x interrupt Disabled. + * | | |1 = Comparator x interrupt Enabled + * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well. + * |[3] |ACMPOINV |Comparator Output Inverse + * | | |0 = Comparator x output inverse Disabled. + * | | |1 = Comparator x output inverse Enabled. + * |[5:4] |NEGSEL |Comparator Negative Input Selection + * | | |00 = ACMPx_N pin. + * | | |01 = Internal comparator reference voltage (CRV). + * | | |10 = Band-gap voltage. + * | | |11 = DAC output. + * |[7:6] |POSSEL |Comparator Positive Input Selection + * | | |00 = Input from ACMPx_P0. + * | | |01 = Input from ACMPx_P1. + * | | |10 = Input from ACMPx_P2. + * | | |11 = Input from ACMPx_P3. + * |[9:8] |INTPOL |Interrupt Condition Polarity Selection + * | | |ACMPIFx will be set to 1 when comparator output edge condition is detected. + * | | |00 = Rising edge or falling edge. + * | | |01 = Rising edge. + * | | |10 = Falling edge. + * | | |11 = Reserved. + * |[12] |OUTSEL |Comparator Output Select + * | | |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output. + * | | |1 = Comparator x output to ACMPx_O pin is from filter output. + * |[15:13] |FILTSEL |Comparator Output Filter Count Selection + * | | |000 = Filter function is Disabled. + * | | |001 = ACMPx output is sampled 1 consecutive PCLK. + * | | |010 = ACMPx output is sampled 2 consecutive PCLKs. + * | | |011 = ACMPx output is sampled 4 consecutive PCLKs. + * | | |100 = ACMPx output is sampled 8 consecutive PCLKs. + * | | |101 = ACMPx output is sampled 16 consecutive PCLKs. + * | | |110 = ACMPx output is sampled 32 consecutive PCLKs. + * | | |111 = ACMPx output is sampled 64 consecutive PCLKs. + * |[16] |WKEN |Power-down Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[17] |WLATEN |Window Latch Mode Enable Bit + * | | |0 = Window Latch Mode Disabled. + * | | |1 = Window Latch Mode Enabled. + * |[18] |WCMPSEL |Window Compare Mode Selection + * | | |0 = Window Compare Mode Disabled. + * | | |1 = Window Compare Mode is Selected. + * |[25:24] |HYSSEL |Hysteresis Mode Selection + * | | |00 = Hysteresis is 0mV. + * | | |01 = Hysteresis is 10mV. + * | | |10 = Hysteresis is 20mV. + * | | |11 = Hysteresis is 30mV. + * |[29:28] |MODESEL |Propagation Delay Mode Selection + * | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA. + * | | |01 = Max propagation delay is 2uS, operation current is 3uA. + * | | |10 = Max propagation delay is 600nS, operation current is 10uA. + * | | |11 = Max propagation delay is 200nS, operation current is 75uA. + * @var ACMP_T::STATUS + * Offset: 0x08 Analog Comparator Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) + * | | |is detected on comparator 0 output. + * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) + * | | |is detected on comparator 1 output. + * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |ACMPO0 |Comparator 0 Output + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[5] |ACMPO1 |Comparator 1 Output + * | | |Synchronized to the PCLK to allow reading by software. + * | | |Cleared when the comparator 1 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |ACMPS0 |Comparator 0 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[13] |ACMPS1 |Comparator 1 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 1 is disabled, i.e. + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[16] |ACMPWO |Comparator Window Output + * | | |This bit shows the output status of window compare mode + * | | |0 = The positive input voltage is outside the window. + * | | |1 = The positive input voltage is in the window. + * @var ACMP_T::VREF + * Offset: 0x0C Analog Comparator Reference Voltage Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CRVCTL |Comparator Reference Voltage Setting + * | | |CRV = CRV source voltage * (1/6+CRVCTL/24). + * |[6] |CRVSSEL |CRV Source Voltage Selection + * | | |0 = VDDA is selected as CRV source voltage. + * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage. + */ + __IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */ + __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */ + +} ACMP_T; + +/** + @addtogroup ACMP_CONST ACMP Bit Field Definition + Constant Definitions for ACMP Controller +@{ */ + +#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */ +#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */ + +#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */ +#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */ + +#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */ +#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */ + +#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */ +#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */ + +#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */ +#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */ + +#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */ +#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */ + +#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */ +#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */ + +#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */ +#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */ + +#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */ +#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */ + +#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */ +#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */ + +#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */ +#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */ + +#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */ +#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */ + +#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */ +#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */ + +#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */ +#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */ + +#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */ +#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */ + +#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */ +#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */ + +#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */ +#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */ + +#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */ +#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */ + +#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */ +#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */ + +#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */ +#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */ + +#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */ +#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */ + +#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */ +#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */ + +#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */ +#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */ + +#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */ +#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */ + +/**@}*/ /* ACMP_CONST */ +/**@}*/ /* end of ACMP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __ACMP_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/bpwm_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/bpwm_reg.h new file mode 100644 index 00000000000..14df066f71e --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/bpwm_reg.h @@ -0,0 +1,1834 @@ +/**************************************************************************//** + * @file bpwm_reg.h + * @version V1.00 + * @brief BPWM register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_REG_H__ +#define __BPWM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM) + Memory Mapped Structure for BPWM Controller +@{ */ + +typedef struct +{ + /** + * @var BCAPDAT_T::RCAPDAT + * Offset: 0x20C BPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the BPWM counter value will be saved in this register. + * @var BCAPDAT_T::FCAPDAT + * Offset: 0x210 BPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the BPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */ +} BCAPDAT_T; + +typedef struct +{ + + + /** + * @var BPWM_T::CTL0 + * Offset: 0x00 BPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt Disabled. + * | | |1 = ICE debug mode counter halt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects BPWM output. + * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var BPWM_T::CTL1 + * Offset: 0x04 BPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0 + * | | |Each bit n controls corresponding BPWM channel n. + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * @var BPWM_T::CLKSRC + * Offset: 0x10 BPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select + * | | |000 = BPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var BPWM_T::CLKPSC + * Offset: 0x14 BPWM Clock Prescale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |BPWM Counter Clock Prescale + * | | |The clock of BPWM counter is decided by clock prescaler + * | | |Each BPWM pair share one BPWM counter clock prescaler + * | | |The clock of BPWM counter is divided by (CLKPSC+ 1) + * @var BPWM_T::CNTEN + * Offset: 0x20 BPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit + * | | |0 = BPWM Counter and clock prescaler stop running. + * | | |1 = BPWM Counter and clock prescaler start running. + * @var BPWM_T::CNTCLR + * Offset: 0x24 BPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0 + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit BPWM counter to 0000H. + * @var BPWM_T::PERIOD + * Offset: 0x30 BPWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |BPWM Period Register + * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period. + * @var BPWM_T::CMPDAT[6] + * Offset: 0x50 BPWM Comparator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPDAT |BPWM Comparator Register + * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. + * @var BPWM_T::CNT + * Offset: 0x90 BPWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |BPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var BPWM_T::WGCTL0 + * Offset: 0xB0 BPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[3:2] |ZPCTL1 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[5:4] |ZPCTL2 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[7:6] |ZPCTL3 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[9:8] |ZPCTL4 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[11:10] |ZPCTL5 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * @var BPWM_T::WGCTL1 + * Offset: 0xB4 BPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * @var BPWM_T::MSKEN + * Offset: 0xB8 BPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * @var BPWM_T::MSK + * Offset: 0xBC BPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[1] |MSKDAT1 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[2] |MSKDAT2 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[3] |MSKDAT3 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[4] |MSKDAT4 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[5] |MSKDAT5 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * @var BPWM_T::POLCTL + * Offset: 0xD4 BPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[1] |PINV1 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[2] |PINV2 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[3] |PINV3 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[4] |PINV4 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[5] |PINV5 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * @var BPWM_T::POEN + * Offset: 0xD8 BPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[1] |POEN1 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[2] |POEN2 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[3] |POEN3 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[4] |POEN4 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[5] |POEN5 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * @var BPWM_T::INTEN + * Offset: 0xE0 BPWM Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When up-down counter type period point means center point. + * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var BPWM_T::INTSTS + * Offset: 0xE8 BPWM Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * @var BPWM_T::EADCTS0 + * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit + * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit + * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved + * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit + * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved. + * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit + * @var BPWM_T::EADCTS1 + * Offset: 0xFC BPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit + * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit + * @var BPWM_T::SSCTL + * Offset: 0x110 BPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit + * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). + * | | |0 = BPWM synchronous start function Disabled. + * | | |1 = BPWM synchronous start function Enabled. + * |[9:8] |SSRC |BPWM Synchronous Start Source Select + * | | |00 = Synchronous start source come from PWM0. + * | | |01 = Synchronous start source come from PWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var BPWM_T::SSTRG + * Offset: 0x114 BPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only) + * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. + * @var BPWM_T::STATUS + * Offset: 0x120 BPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[16] |EADCTRG0 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRG1 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRG2 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRG3 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRG4 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRG5 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * @var BPWM_T::CAPINEN + * Offset: 0x200 BPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * @var BPWM_T::CAPCTL + * Offset: 0x204 BPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var BPWM_T::CAPSTS + * Offset: 0x208 BPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * @var BPWM_T::CAPIEN + * Offset: 0x250 BPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var BPWM_T::CAPIF + * Offset: 0x254 BPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * @var BPWM_T::PBUF + * Offset: 0x304 BPWM PERIOD Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |BPWM Period Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var BPWM_T::CMPBUF[6] + * Offset: 0x31C BPWM CMPDAT 0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */ + __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CMPDAT[6]; /*!< [0x0050] BPWM Comparator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[10]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE7[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE8[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE9[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE10[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE11[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE12[55]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */ + BCAPDAT_T CAPDAT[6]; /*!< [0x020C] BPWM Rising and Falling Capture Data Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE13[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE14[43]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE15[5]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CMPBUF[6]; /*!< [0x031c] BPWM CMPDAT 0~5 Buffer */ + +} BPWM_T; + +/** + @addtogroup BPWM_CONST BPWM Bit Field Definition + Constant Definitions for BPWM Controller +@{ */ + +#define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */ +#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */ + +#define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */ +#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */ + +#define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */ +#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */ + +#define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */ +#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */ + +#define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */ +#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */ + +#define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */ +#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */ + +#define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */ +#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */ + +#define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */ +#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */ + +#define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */ +#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */ + +#define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */ +#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */ + +#define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */ +#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */ + +#define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */ +#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */ + +#define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */ +#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */ + +#define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */ +#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */ + +#define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */ +#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */ + +#define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */ +#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */ +#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */ + +#define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */ +#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */ + +#define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */ +#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */ +#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */ + +#define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */ +#define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */ + +#define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */ +#define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */ + +#define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */ +#define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */ + +#define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */ +#define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */ + +#define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */ +#define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */ + +#define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */ +#define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */ + +#define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */ +#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */ + +#define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */ +#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */ + +#define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */ +#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */ +#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */ +#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */ +#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */ +#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */ +#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */ +#define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */ + +#define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */ +#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */ +#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */ +#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */ +#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */ +#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */ +#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */ +#define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */ + +#define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */ +#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */ +#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */ +#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */ +#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */ +#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */ +#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */ +#define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */ + +#define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */ +#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */ +#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */ +#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */ +#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */ +#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */ +#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */ +#define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */ + +#define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */ +#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */ + +#define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */ +#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */ + +#define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */ +#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */ + +#define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */ +#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */ + +#define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */ +#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */ + +#define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */ +#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */ + +#define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */ +#define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */ + +#define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */ +#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */ + +#define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */ +#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */ + +#define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */ +#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */ + +#define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */ +#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */ + +#define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */ +#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */ + +#define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */ +#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */ + +#define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */ +#define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */ + +#define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */ +#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */ + +#define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */ +#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */ + +#define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */ +#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */ + +#define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */ +#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */ + +#define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */ +#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */ + +#define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */ +#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */ + +#define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */ +#define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */ + +#define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */ +#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */ + +#define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */ +#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */ + +#define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */ +#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */ + +#define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */ +#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */ + +#define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */ +#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */ + +#define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */ +#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */ + +#define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */ +#define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */ + +#define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */ +#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */ + +#define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */ +#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */ +#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */ +#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */ + +#define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */ +#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */ + +#define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */ +#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */ + +#define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */ +#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */ + +#define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */ +#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */ + +#define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */ +#define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */ + +#define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */ +#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */ + +#define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */ +#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */ + +#define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */ +#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */ + +#define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */ +#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */ + +#define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */ +#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */ + +#define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */ +#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */ + +#define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */ +#define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */ + +#define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */ +#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */ + +#define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */ +#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */ +#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */ +#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */ + +#define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */ +#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */ + +#define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */ +#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */ + +#define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */ +#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */ + +#define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */ +#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */ + +#define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */ +#define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */ + +#define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */ +#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */ + +#define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */ +#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */ + +#define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */ +#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */ + +#define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */ +#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */ + +#define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */ +#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */ + +#define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */ +#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */ + +#define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */ +#define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */ + +#define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */ +#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */ +#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */ + +#define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */ +#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */ +#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */ + +#define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */ +#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */ +#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */ + +#define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */ +#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */ +#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */ + +#define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */ +#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */ +#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */ + +#define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */ +#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */ +#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */ + +#define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */ +#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */ + +#define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */ +#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */ + +#define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */ +#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */ + +#define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */ +#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */ + +#define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */ +#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */ + +#define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */ +#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */ + +#define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */ +#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */ + +#define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */ +#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */ + +#define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */ +#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */ + +#define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */ +#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */ + +#define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */ +#define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */ + +#define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */ +#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */ +#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */ +#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */ +#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */ +#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */ +#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */ +#define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */ + +#define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */ +#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */ + +#define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */ +#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */ + +#define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */ +#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */ + +#define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */ +#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */ + +#define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */ +#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */ + +#define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */ +#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */ + +#define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */ +#define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */ + +#define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */ +#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */ + +#define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */ +#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */ + +#define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */ +#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */ + +#define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */ +#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */ + +#define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */ +#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */ + +#define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */ +#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */ + +#define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */ +#define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */ + +#define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */ +#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */ +#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */ +#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */ +#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */ +#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */ +#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */ +#define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */ + +#define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */ +#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */ +#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */ +#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */ +#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */ +#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */ +#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */ +#define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */ + +#define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */ +#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */ + +#define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */ +#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */ + +#define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */ +#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */ + +#define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */ +#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */ + +#define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */ +#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */ + +#define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */ +#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */ + +#define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */ +#define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */ + +#define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */ +#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */ + +#define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */ +#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */ + +#define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */ +#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */ + +#define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */ +#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */ + +#define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */ +#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */ + +#define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */ +#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */ + +#define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */ +#define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */ + +#define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */ +#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */ +#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */ +#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */ +#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */ +#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */ +#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */ +#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */ +#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */ +#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */ +#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */ +#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */ +#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */ +#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */ + +#define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */ +#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */ + +#define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */ +#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */ + +#define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */ +#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */ + +#define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */ +#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */ + +#define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */ +#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */ + +#define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */ +#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */ + +#define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */ +#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */ + +#define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */ +#define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */ + +#define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */ +#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */ + +#define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */ +#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */ + +#define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */ +#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */ + +#define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */ +#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */ + +#define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */ +#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */ + +#define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */ +#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */ + +#define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */ +#define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */ + +#define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */ +#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */ + +#define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */ +#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */ + +#define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */ +#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */ + +#define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */ +#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */ + +#define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */ +#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */ + +#define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */ +#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */ + +#define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */ +#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */ + +/**@}*/ /* BPWM_CONST */ +/**@}*/ /* end of BPWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __BPWM_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/can_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/can_reg.h new file mode 100644 index 00000000000..379e3b2cb8f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/can_reg.h @@ -0,0 +1,758 @@ +/**************************************************************************//** + * @file can_reg.h + * @version V1.00 + * @brief CAN register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CAN_REG_H__ +#define __CAN_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CAN Controller Area Network Controller(CAN) + Memory Mapped Structure for CAN Controller +@{ */ + + +typedef struct +{ + + /** + * @var CAN_IF_T::CREQ + * Offset: 0x20, 0x80 IFn Command Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MessageNumber|Message Number + * | | |0x01-0x20: Valid Message Number, the Message Object in the Message + * | | |RAM is selected for data transfer. + * | | |0x00: Not a valid Message Number, interpreted as 0x20. + * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. + * |[15] |Busy |Busy Flag + * | | |0 = Read/write action has finished. + * | | |1 = Writing to the IFn Command Request Register is in progress + * | | |This bit can only be read by the software. + * @var CAN_IF_T::CMASK + * Offset: 0x24, 0x84 IFn Command Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DAT_B |Access Data Bytes [7:4] + * | | |Write Operation: + * | | |0 = Data Bytes [7:4] unchanged. + * | | |1 = Transfer Data Bytes [7:4] to Message Object. + * | | |Read Operation: + * | | |0 = Data Bytes [7:4] unchanged. + * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register. + * |[1] |DAT_A |Access Data Bytes [3:0] + * | | |Write Operation: + * | | |0 = Data Bytes [3:0] unchanged. + * | | |1 = Transfer Data Bytes [3:0] to Message Object. + * | | |Read Operation: + * | | |0 = Data Bytes [3:0] unchanged. + * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register. + * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation + * | | |0 = TxRqst bit unchanged. + * | | |1 = Set TxRqst bit. + * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored. + * | | |Access New Data Bit when Read Operation. + * | | |0 = NewDat bit remains unchanged. + * | | |1 = Clear NewDat bit in the Message Object. + * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat + * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. + * |[3] |ClrIntPnd |Clear Interrupt Pending Bit + * | | |Write Operation: + * | | |When writing to a Message Object, this bit is ignored. + * | | |Read Operation: + * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged. + * | | |1 = Clear IntPnd bit in the Message Object. + * |[4] |Control |Control Access Control Bits + * | | |Write Operation: + * | | |0 = Control Bits unchanged. + * | | |1 = Transfer Control Bits to Message Object. + * | | |Read Operation: + * | | |0 = Control Bits unchanged. + * | | |1 = Transfer Control Bits to IFn Message Buffer Register. + * |[5] |Arb |Access Arbitration Bits + * | | |Write Operation: + * | | |0 = Arbitration bits unchanged. + * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object. + * | | |Read Operation: + * | | |0 = Arbitration bits unchanged. + * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register. + * |[6] |Mask |Access Mask Bits + * | | |Write Operation: + * | | |0 = Mask bits unchanged. + * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object. + * | | |Read Operation: + * | | |0 = Mask bits unchanged. + * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register. + * |[7] |WR_RD |Write / Read Mode + * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers. + * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register. + * @var CAN_IF_T::MASK1 + * Offset: 0x28, 0x88 IFn Mask 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |Msk |Identifier Mask 15-0 + * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. + * | | |1 = The corresponding identifier bit is used for acceptance filtering. + * @var CAN_IF_T::MASK2 + * Offset: 0x2C, 0x8C IFn Mask 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |Msk |Identifier Mask 28-16 + * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. + * | | |1 = The corresponding identifier bit is used for acceptance filtering. + * |[14] |MDir |Mask Message Direction + * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering. + * | | |1 = The message direction bit (Dir) is used for acceptance filtering. + * |[15] |MXtd |Mask Extended Identifier + * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering. + * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering. + * | | |Note: When 11-bit (standard) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]) + * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered. + * @var CAN_IF_T::ARB1 + * Offset: 0x30, 0x90 IFn Arbitration 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ID |Message Identifier 15-0 + * | | |ID28 - ID0, 29-bit Identifier (Extended Frame) + * | | |ID28 - ID18, 11-bit Identifier (Standard Frame) + * @var CAN_IF_T::ARB2 + * Offset: 0x34, 0x94 IFn Arbitration 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |ID |Message Identifier 28-16 + * | | |ID28 - ID0, 29-bit Identifier (Extended Frame) + * | | |ID28 - ID18, 11-bit Identifier (Standard Frame) + * |[13] |Dir |Message Direction + * | | |0 = Direction is receive. + * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted + * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object. + * | | |1 = Direction is transmit. + * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame + * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one). + * |[14] |Xtd |Extended Identifier + * | | |0 = The 11-bit (standard) Identifier will be used for this Message Object. + * | | |1 = The 29-bit (extended) Identifier will be used for this Message Object. + * |[15] |MsgVal |Message Valid + * | | |0 = The Message Object is ignored by the Message Handler. + * | | |1 = The Message Object is configured and should be considered by the Message Handler. + * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]) + * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. + * @var CAN_IF_T::MCON + * Offset: 0x38, 0x98 IFn Message Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DLC |Data Length Code + * | | |0-8: Data Frame has 0-8 data bytes. + * | | |9-15: Data Frame has 8 data bytes + * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes + * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. + * | | |Data(0): 1st data byte of a CAN Data Frame + * | | |Data(1): 2nd data byte of a CAN Data Frame + * | | |Data(2): 3rd data byte of a CAN Data Frame + * | | |Data(3): 4th data byte of a CAN Data Frame + * | | |Data(4): 5th data byte of a CAN Data Frame + * | | |Data(5): 6th data byte of a CAN Data Frame + * | | |Data(6): 7th data byte of a CAN Data Frame + * | | |Data(7): 8th data byte of a CAN Data Frame + * | | |Note: The Data(0) byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data(7) byte is the last + * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object + * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values. + * |[7] |EoB |End of Buffer + * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer. + * | | |1 = Single Message Object or last Message Object of a FIFO Buffer. + * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer + * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one + * |[8] |TxRqst |Transmit Request + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * |[9] |RmtEn |Remote Enable Bit + * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged. + * | | |1 = At the reception of a Remote Frame, TxRqst is set. + * |[10] |RxIE |Receive Interrupt Enable Bit + * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame. + * | | |1 = IntPnd will be set after a successful reception of a frame. + * |[11] |TxIE |Transmit Interrupt Enable Bit + * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame. + * | | |1 = IntPnd will be set after a successful transmission of a frame. + * |[12] |UMask |Use Acceptance Mask + * | | |0 = Mask ignored. + * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering. + * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one. + * |[13] |IntPnd |Interrupt Pending + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt + * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. + * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive). + * | | |0 = No message lost since last time this bit was reset by the CPU. + * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message. + * |[15] |NewDat |New Data + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_IF_T::DAT_A1 + * Offset: 0x3C, 0x9C IFn Data A1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_0_ |Data Byte 0 + * | | |1st data byte of a CAN Data Frame + * |[15:8] |Data_1_ |Data Byte 1 + * | | |2nd data byte of a CAN Data Frame + * @var CAN_IF_T::DAT_A2 + * Offset: 0x40, 0xA0 IFn Data A2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_2_ |Data Byte 2 + * | | |3rd data byte of CAN Data Frame + * |[15:8] |Data_3_ |Data Byte 3 + * | | |4th data byte of CAN Data Frame + * @var CAN_IF_T::DAT_B1 + * Offset: 0x44, 0xA4 IFn Data B1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_4_ |Data Byte 4 + * | | |5th data byte of CAN Data Frame + * |[15:8] |Data_5_ |Data Byte 5 + * | | |6th data byte of CAN Data Frame + * @var CAN_IF_T::DAT_B2 + * Offset: 0x48, 0xA8 IFn Data B2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data_6_ |Data Byte 6 + * | | |7th data byte of CAN Data Frame. + * |[15:8] |Data_7_ |Data Byte 7 + * | | |8th data byte of CAN Data Frame. + */ + __IO uint32_t CREQ; /*!< [0x0020] IFn Command Request Register */ + __IO uint32_t CMASK; /*!< [0x0024] IFn Command Mask Register */ + __IO uint32_t MASK1; /*!< [0x0028] IFn Mask 1 Register */ + __IO uint32_t MASK2; /*!< [0x002c] IFn Mask 2 Register */ + __IO uint32_t ARB1; /*!< [0x0030] IFn Arbitration 1 Register */ + __IO uint32_t ARB2; /*!< [0x0034] IFn Arbitration 2 Register */ + __IO uint32_t MCON; /*!< [0x0038] IFn Message Control Register */ + __IO uint32_t DAT_A1; /*!< [0x003c] IFn Data A1 Register */ + __IO uint32_t DAT_A2; /*!< [0x0040] IFn Data A2 Register */ + __IO uint32_t DAT_B1; /*!< [0x0044] IFn Data B1 Register */ + __IO uint32_t DAT_B2; /*!< [0x0048] IFn Data B2 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[13]; + /// @endcond //HIDDEN_SYMBOLS +} CAN_IF_T; + + +typedef struct +{ + + + /** + * @var CAN_T::CON + * Offset: 0x00 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |Init |Init Initialization + * | | |0 = Normal Operation. + * | | |1 = Initialization is started. + * |[1] |IE |Module Interrupt Enable Bit + * | | |0 = Function interrupt is Disabled. + * | | |1 = Function interrupt is Enabled. + * |[2] |SIE |Status Change Interrupt Enable Bit + * | | |0 = Disabled - No Status Change Interrupt will be generated. + * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. + * |[3] |EIE |Error Interrupt Enable Bit + * | | |0 = Disabled - No Error Status Interrupt will be generated. + * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt. + * |[5] |DAR |Automatic Re-transmission Disable Bit + * | | |0 = Automatic Retransmission of disturbed messages Enabled. + * | | |1 = Automatic Retransmission Disabled. + * |[6] |CCE |Configuration Change Enable Bit + * | | |0 = No write access to the Bit Timing Register. + * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1). + * |[7] |Test |Test Mode Enable Bit + * | | |0 = Normal Operation. + * | | |1 = Test Mode. + * @var CAN_T::STATUS + * Offset: 0x04 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |LEC |Last Error Code (Type of the Last Error to Occur on the CAN Bus) + * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus + * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error + * | | |The unused code '7' may be written by the CPU to check for updates + * | | |The Error! Reference source not found + * | | |describes the error code. + * |[3] |TxOK |Transmitted a Message Successfully + * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted + * | | |This bit is never reset by the CAN Core. + * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. + * |[4] |RxOK |Received a Message Successfully + * | | |0 = No message has been successfully received since this bit was last reset by the CPU + * | | |This bit is never reset by the CAN Core. + * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering). + * |[5] |EPass |Error Passive (Read Only) + * | | |0 = The CAN Core is error active. + * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification. + * |[6] |EWarn |Error Warning Status (Read Only) + * | | |0 = Both error counters are below the error warning limit of 96. + * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96. + * |[7] |BOff |Bus-off Status (Read Only) + * | | |0 = The CAN module is not in bus-off state. + * | | |1 = The CAN module is in bus-off state. + * @var CAN_T::ERR + * Offset: 0x08 Error Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TEC |Transmit Error Counter + * | | |Actual state of the Transmit Error Counter. Values between 0 and 255. + * |[14:8] |REC |Receive Error Counter + * | | |Actual state of the Receive Error Counter. Values between 0 and 127. + * |[15] |RP |Receive Error Passive + * | | |0 = The Receive Error Counter is below the error passive level. + * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification. + * @var CAN_T::BTIME + * Offset: 0x0C Bit Timing Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |BRP |Baud Rate Prescaler + * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta + * | | |The bit time is built up from a multiple of this quanta + * | | |Valid values for the Baud Rate Prescaler are [0...63] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[7:6] |SJW |(Re)Synchronization Jump Width + * | | |0x0-0x3: Valid programmed values are [0...3] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[11:8] |TSeg1 |Time Segment Before the Sample Point Minus Sync_Seg + * | | |0x01-0x0F: valid values for TSeg1 are [1...15] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used. + * |[14:12] |TSeg2 |Time Segment After Sample Point + * | | |0x0-0x7: Valid values for TSeg2 are [0...7] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * @var CAN_T::IIDR + * Offset: 0x10 Interrupt Identifier Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntId |Interrupt Identifier (Indicates the Source of the Interrupt) + * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order + * | | |An interrupt remains pending until the application software has cleared it + * | | |If IntId is different from 0x0000 and IE (CAN_CON[1]) is set, the IRQ interrupt signal to the EIC is active + * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset. + * | | |The Status Interrupt has the highest priority + * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number. + * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]) + * | | |The Status Interrupt is cleared by reading the Status Register. + * @var CAN_T::TEST + * Offset: 0x14 Test Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |Basic |Basic Mode + * | | |0 = Basic Mode Disabled. + * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. + * |[3] |Silent |Silent Mode + * | | |0 = Normal operation. + * | | |1 = The module is in Silent Mode. + * |[4] |LBack |Loop Back Mode Enable Bit + * | | |0 = Loop Back Mode is Disabled. + * | | |1 = Loop Back Mode is Enabled. + * |[6:5] |Tx |Tx[1:0]: Control of CAN_TX Pin + * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core. + * | | |01 = Sample Point can be monitored at CAN_TX pin. + * | | |10 = CAN_TX pin drives a dominant ('0') value. + * | | |11 = CAN_TX pin drives a recessive ('1') value. + * |[7] |Rx |Monitors the Actual Value of CAN_RX Pin (Read Only) *(1) + * | | |0 = The CAN bus is dominant (CAN_RX = '0'). + * | | |1 = The CAN bus is recessive (CAN_RX = '1'). + * @var CAN_T::BRPE + * Offset: 0x18 Baud Rate Prescaler Extension Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension + * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023 + * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. + * @var CAN_T::TXREQ1 + * Offset: 0x100 Transmission Request Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TxRqst16_1|Transmission Request Bits 16-1 (of All Message Objects) + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * | | |These bits are read only. + * @var CAN_T::TXREQ2 + * Offset: 0x104 Transmission Request Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TxRqst32_17|Transmission Request Bits 32-17 (of All Message Objects) + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * | | |These bits are read only. + * @var CAN_T::NDAT1 + * Offset: 0x120 New Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NewData16_1|New Data Bits 16-1 (of All Message Objects) + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_T::NDAT2 + * Offset: 0x124 New Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NewData32_17|New Data Bits 32-17 (of All Message Objects) + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_T::IPND1 + * Offset: 0x140 Interrupt Pending Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntPnd16_1|Interrupt Pending Bits 16-1 (of All Message Objects) + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * @var CAN_T::IPND2 + * Offset: 0x144 Interrupt Pending Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntPnd32_17|Interrupt Pending Bits 32-17 (of All Message Objects) + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * @var CAN_T::MVLD1 + * Offset: 0x160 Message Valid Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MsgVal16_1|Message Valid Bits 16-1 (of All Message Objects) (Read Only) + * | | |0 = This Message Object is ignored by the Message Handler. + * | | |1 = This Message Object is configured and should be considered by the Message Handler. + * | | |Ex + * | | |CAN_MVLD1[0] means Message object No.1 is valid or not + * | | |If CAN_MVLD1[0] is set, message object No.1 is configured. + * @var CAN_T::MVLD2 + * Offset: 0x164 Message Valid Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MsgVal32_17|Message Valid Bits 32-17 (of All Message Objects) (Read Only) + * | | |0 = This Message Object is ignored by the Message Handler. + * | | |1 = This Message Object is configured and should be considered by the Message Handler. + * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not + * | | |If CAN_MVLD2[15] is set, message object No.32 is configured. + * @var CAN_T::WU_EN + * Offset: 0x168 Wake-up Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WAKUP_EN |Wake-up Enable Bit + * | | |0 = The wake-up function Disabled. + * | | |1 = The wake-up function Enabled. + * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin. + * @var CAN_T::WU_STATUS + * Offset: 0x16C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WAKUP_STS |Wake-up Status + * | | |0 = No wake-up event occurred. + * | | |1 = Wake-up event occurred. + * | | |Note: This bit can be cleared by writing '0'. + */ + __IO uint32_t CON; /*!< [0x0000] Control Register */ + __IO uint32_t STATUS; /*!< [0x0004] Status Register */ + __I uint32_t ERR; /*!< [0x0008] Error Counter Register */ + __IO uint32_t BTIME; /*!< [0x000c] Bit Timing Register */ + __I uint32_t IIDR; /*!< [0x0010] Interrupt Identifier Register */ + __IO uint32_t TEST; /*!< [0x0014] Test Register */ + __IO uint32_t BRPE; /*!< [0x0018] Baud Rate Prescaler Extension Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO CAN_IF_T IF[2]; + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[8]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t TXREQ1; /*!< [0x0100] Transmission Request Register 1 */ + __I uint32_t TXREQ2; /*!< [0x0104] Transmission Request Register 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[6]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t NDAT1; /*!< [0x0120] New Data Register 1 */ + __I uint32_t NDAT2; /*!< [0x0124] New Data Register 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[6]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t IPND1; /*!< [0x0140] Interrupt Pending Register 1 */ + __I uint32_t IPND2; /*!< [0x0144] Interrupt Pending Register 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[6]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t MVLD1; /*!< [0x0160] Message Valid Register 1 */ + __I uint32_t MVLD2; /*!< [0x0164] Message Valid Register 2 */ + __IO uint32_t WU_EN; /*!< [0x0168] Wake-up Enable Control Register */ + __IO uint32_t WU_STATUS; /*!< [0x016c] Wake-up Status Register */ + +} CAN_T; + +/** + @addtogroup CAN_CONST CAN Bit Field Definition + Constant Definitions for CAN Controller +@{ */ + +#define CAN_CON_INIT_Pos (0) /*!< CAN_T::CON: Init Position */ +#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: Init Mask */ + +#define CAN_CON_IE_Pos (1) /*!< CAN_T::CON: IE Position */ +#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */ + +#define CAN_CON_SIE_Pos (2) /*!< CAN_T::CON: SIE Position */ +#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */ + +#define CAN_CON_EIE_Pos (3) /*!< CAN_T::CON: EIE Position */ +#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */ + +#define CAN_CON_DAR_Pos (5) /*!< CAN_T::CON: DAR Position */ +#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */ + +#define CAN_CON_CCE_Pos (6) /*!< CAN_T::CON: CCE Position */ +#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */ + +#define CAN_CON_TEST_Pos (7) /*!< CAN_T::CON: Test Position */ +#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: Test Mask */ + +#define CAN_STATUS_LEC_Pos (0) /*!< CAN_T::STATUS: LEC Position */ +#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ + +#define CAN_STATUS_TXOK_Pos (3) /*!< CAN_T::STATUS: TxOK Position */ +#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TxOK Mask */ + +#define CAN_STATUS_RXOK_Pos (4) /*!< CAN_T::STATUS: RxOK Position */ +#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RxOK Mask */ + +#define CAN_STATUS_EPASS_Pos (5) /*!< CAN_T::STATUS: EPass Position */ +#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPass Mask */ + +#define CAN_STATUS_EWARN_Pos (6) /*!< CAN_T::STATUS: EWarn Position */ +#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWarn Mask */ + +#define CAN_STATUS_BOFF_Pos (7) /*!< CAN_T::STATUS: BOff Position */ +#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOff Mask */ + +#define CAN_ERR_TEC_Pos (0) /*!< CAN_T::ERR: TEC Position */ +#define CAN_ERR_TEC_Msk (0xfful << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */ + +#define CAN_ERR_REC_Pos (8) /*!< CAN_T::ERR: REC Position */ +#define CAN_ERR_REC_Msk (0x7ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */ + +#define CAN_ERR_RP_Pos (15) /*!< CAN_T::ERR: RP Position */ +#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */ + +#define CAN_BTIME_BRP_Pos (0) /*!< CAN_T::BTIME: BRP Position */ +#define CAN_BTIME_BRP_Msk (0x3ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */ + +#define CAN_BTIME_SJW_Pos (6) /*!< CAN_T::BTIME: SJW Position */ +#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */ + +#define CAN_BTIME_TSEG1_Pos (8) /*!< CAN_T::BTIME: TSeg1 Position */ +#define CAN_BTIME_TSEG1_Msk (0xful << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSeg1 Mask */ + +#define CAN_BTIME_TSEG2_Pos (12) /*!< CAN_T::BTIME: TSeg2 Position */ +#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSeg2 Mask */ + +#define CAN_IIDR_IntId_Pos (0) /*!< CAN_T::IIDR: IntId Position */ +#define CAN_IIDR_IntId_Msk (0xfffful << CAN_IIDR_IntId_Pos) /*!< CAN_T::IIDR: IntId Mask */ + +#define CAN_TEST_BASIC_Pos (2) /*!< CAN_T::TEST: Basic Position */ +#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */ + +#define CAN_TEST_SILENT_Pos (3) /*!< CAN_T::TEST: Silent Position */ +#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */ + +#define CAN_TEST_LBACK_Pos (4) /*!< CAN_T::TEST: LBack Position */ +#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBack Mask */ + +#define CAN_TEST_Tx_Pos (5) /*!< CAN_T::TEST: Tx Position */ +#define CAN_TEST_Tx_Msk (0x3ul << CAN_TEST_Tx_Pos) /*!< CAN_T::TEST: Tx Mask */ + +#define CAN_TEST_Rx_Pos (7) /*!< CAN_T::TEST: Rx Position */ +#define CAN_TEST_Rx_Msk (0x1ul << CAN_TEST_Rx_Pos) /*!< CAN_T::TEST: Rx Mask */ + +#define CAN_BRPE_BRPE_Pos (0) /*!< CAN_T::BRPE: BRPE Position */ +#define CAN_BRPE_BRPE_Msk (0xful << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ + +#define CAN_IF_CREQ_MSGNUM_Pos (0) /*!< CAN_IF_T::CREQ: MessageNumber Position*/ +#define CAN_IF_CREQ_MSGNUM_Msk (0x3ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MessageNumber Mask */ + +#define CAN_IF_CREQ_BUSY_Pos (15) /*!< CAN_IF_T::CREQ: Busy Position */ +#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: Busy Mask */ + +#define CAN_IF_CMASK_DATAB_Pos (0) /*!< CAN_IF_T::CMASK: DAT_B Position */ +#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DAT_B Mask */ + +#define CAN_IF_CMASK_DATAA_Pos (1) /*!< CAN_IF_T::CMASK: DAT_A Position */ +#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DAT_A Mask */ + +#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos (2) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Position*/ +#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TxRqst_NewDat Mask */ + +#define CAN_IF_CMASK_CLRINTPND_Pos (3) /*!< CAN_IF_T::CMASK: ClrIntPnd Position */ +#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: ClrIntPnd Mask */ + +#define CAN_IF_CMASK_CONTROL_Pos (4) /*!< CAN_IF_T::CMASK: Control Position */ +#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: Control Mask */ + +#define CAN_IF_CMASK_ARB_Pos (5) /*!< CAN_IF_T::CMASK: Arb Position */ +#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: Arb Mask */ + +#define CAN_IF_CMASK_MASK_Pos (6) /*!< CAN_IF_T::CMASK: Mask Position */ +#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: Mask Mask */ + +#define CAN_IF_CMASK_WRRD_Pos (7) /*!< CAN_IF_T::CMASK: WR_RD Position */ +#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WR_RD Mask */ + +#define CAN_IF_MASK1_Msk_Pos (0) /*!< CAN_IF_T::MASK1: Msk Position */ +#define CAN_IF_MASK1_Msk_Msk (0xfffful << CAN_IF_MASK1_Msk_Pos) /*!< CAN_IF_T::MASK1: Msk Mask */ + +#define CAN_IF_MASK2_Msk_Pos (0) /*!< CAN_IF_T::MASK2: Msk Position */ +#define CAN_IF_MASK2_Msk_Msk (0x1ffful << CAN_IF_MASK2_Msk_Pos) /*!< CAN_IF_T::MASK2: Msk Mask */ + +#define CAN_IF_MASK2_MDIR_Pos (14) /*!< CAN_IF_T::MASK2: MDir Position */ +#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDir Mask */ + +#define CAN_IF_MASK2_MXTD_Pos (15) /*!< CAN_IF_T::MASK2: MXtd Position */ +#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXtd Mask */ + +#define CAN_IF_ARB1_ID_Pos (0) /*!< CAN_IF_T::ARB1: ID Position */ +#define CAN_IF_ARB1_ID_Msk (0xfffful << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */ + +#define CAN_IF_ARB2_ID_Pos (0) /*!< CAN_IF_T::ARB2: ID Position */ +#define CAN_IF_ARB2_ID_Msk (0x1ffful << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */ + +#define CAN_IF_ARB2_DIR_Pos (13) /*!< CAN_IF_T::ARB2: Dir Position */ +#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: Dir Mask */ + +#define CAN_IF_ARB2_XTD_Pos (14) /*!< CAN_IF_T::ARB2: Xtd Position */ +#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: Xtd Mask */ + +#define CAN_IF_ARB2_MSGVAL_Pos (15) /*!< CAN_IF_T::ARB2: MsgVal Position */ +#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MsgVal Mask */ + +#define CAN_IF_MCON_DLC_Pos (0) /*!< CAN_IF_T::MCON: DLC Position */ +#define CAN_IF_MCON_DLC_Msk (0xful << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */ + +#define CAN_IF_MCON_EOB_Pos (7) /*!< CAN_IF_T::MCON: EoB Position */ +#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EoB Mask */ + +#define CAN_IF_MCON_TxRqst_Pos (8) /*!< CAN_IF_T::MCON: TxRqst Position */ +#define CAN_IF_MCON_TxRqst_Msk (0x1ul << CAN_IF_MCON_TxRqst_Pos) /*!< CAN_IF_T::MCON: TxRqst Mask */ + +#define CAN_IF_MCON_RmtEn_Pos (9) /*!< CAN_IF_T::MCON: RmtEn Position */ +#define CAN_IF_MCON_RmtEn_Msk (0x1ul << CAN_IF_MCON_RmtEn_Pos) /*!< CAN_IF_T::MCON: RmtEn Mask */ + +#define CAN_IF_MCON_RXIE_Pos (10) /*!< CAN_IF_T::MCON: RxIE Position */ +#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RxIE Mask */ + +#define CAN_IF_MCON_TXIE_Pos (11) /*!< CAN_IF_T::MCON: TxIE Position */ +#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TxIE Mask */ + +#define CAN_IF_MCON_UMASK_Pos (12) /*!< CAN_IF_T::MCON: UMask Position */ +#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMask Mask */ + +#define CAN_IF_MCON_IntPnd_Pos (13) /*!< CAN_IF_T::MCON: IntPnd Position */ +#define CAN_IF_MCON_IntPnd_Msk (0x1ul << CAN_IF_MCON_IntPnd_Pos) /*!< CAN_IF_T::MCON: IntPnd Mask */ + +#define CAN_IF_MCON_MsgLst_Pos (14) /*!< CAN_IF_T::MCON: MsgLst Position */ +#define CAN_IF_MCON_MsgLst_Msk (0x1ul << CAN_IF_MCON_MsgLst_Pos) /*!< CAN_IF_T::MCON: MsgLst Mask */ + +#define CAN_IF_MCON_NEWDAT_Pos (15) /*!< CAN_IF_T::MCON: NewDat Position */ +#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NewDat Mask */ + +#define CAN_IF_DAT_A1_DATA0_Pos (0) /*!< CAN_IF_T::DAT_A1: Data_0_ Position */ +#define CAN_IF_DAT_A1_DATA0_Msk (0xfful << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DAT_A1: Data_0_ Mask */ + +#define CAN_IF_DAT_A1_DATA1_Pos (8) /*!< CAN_IF_T::DAT_A1: Data_1_ Position */ +#define CAN_IF_DAT_A1_DATA1_Msk (0xfful << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DAT_A1: Data_1_ Mask */ + +#define CAN_IF_DAT_A2_DATA2_Pos (0) /*!< CAN_IF_T::DAT_A2: Data_2_ Position */ +#define CAN_IF_DAT_A2_DATA2_Msk (0xfful << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DAT_A2: Data_2_ Mask */ + +#define CAN_IF_DAT_A2_DATA3_Pos (8) /*!< CAN_IF_T::DAT_A2: Data_3_ Position */ +#define CAN_IF_DAT_A2_DATA3_Msk (0xfful << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DAT_A2: Data_3_ Mask */ + +#define CAN_IF_DAT_B1_DATA4_Pos (0) /*!< CAN_IF_T::DAT_B1: Data_4_ Position */ +#define CAN_IF_DAT_B1_DATA4_Msk (0xfful << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DAT_B1: Data_4_ Mask */ + +#define CAN_IF_DAT_B1_DATA5_Pos (8) /*!< CAN_IF_T::DAT_B1: Data_5_ Position */ +#define CAN_IF_DAT_B1_DATA5_Msk (0xfful << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DAT_B1: Data_5_ Mask */ + +#define CAN_IF_DAT_B2_DATA6_Pos (0) /*!< CAN_IF_T::DAT_B2: Data_6_ Position */ +#define CAN_IF_DAT_B2_DATA6_Msk (0xfful << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DAT_B2: Data_6_ Mask */ + +#define CAN_IF_DAT_B2_DATA7_Pos (8) /*!< CAN_IF_T::DAT_B2: Data_7_ Position */ +#define CAN_IF_DAT_B2_DATA7_Msk (0xfful << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DAT_B2: Data_7_ Mask */ + +#define CAN_TXREQ1_TXRQST16_1_Pos (0) /*!< CAN_T::TXREQ1: TxRqst16_1 Position */ +#define CAN_TXREQ1_TXRQST16_1_Msk (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos) /*!< CAN_T::TXREQ1: TxRqst16_1 Mask */ + +#define CAN_TXREQ2_TXRQST32_17_Pos (0) /*!< CAN_T::TXREQ2: TxRqst32_17 Position */ +#define CAN_TXREQ2_TXRQST32_17_Msk (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos) /*!< CAN_T::TXREQ2: TxRqst32_17 Mask */ + +#define CAN_NDAT1_NewData16_1_Pos (0) /*!< CAN_T::NDAT1: NewData16_1 Position */ +#define CAN_NDAT1_NewData16_1_Msk (0xfffful << CAN_NDAT1_NewData16_1_Pos) /*!< CAN_T::NDAT1: NewData16_1 Mask */ + +#define CAN_NDAT2_NewData32_17_Pos (0) /*!< CAN_T::NDAT2: NewData32_17 Position */ +#define CAN_NDAT2_NewData32_17_Msk (0xfffful << CAN_NDAT2_NewData32_17_Pos) /*!< CAN_T::NDAT2: NewData32_17 Mask */ + +#define CAN_IPND1_IntPnd16_1_Pos (0) /*!< CAN_T::IPND1: IntPnd16_1 Position */ +#define CAN_IPND1_IntPnd16_1_Msk (0xfffful << CAN_IPND1_IntPnd16_1_Pos) /*!< CAN_T::IPND1: IntPnd16_1 Mask */ + +#define CAN_IPND2_IntPnd32_17_Pos (0) /*!< CAN_T::IPND2: IntPnd32_17 Position */ +#define CAN_IPND2_IntPnd32_17_Msk (0xfffful << CAN_IPND2_IntPnd32_17_Pos) /*!< CAN_T::IPND2: IntPnd32_17 Mask */ + +#define CAN_MVLD1_MsgVal16_1_Pos (0) /*!< CAN_T::MVLD1: MsgVal16_1 Position */ +#define CAN_MVLD1_MsgVal16_1_Msk (0xfffful << CAN_MVLD1_MsgVal16_1_Pos) /*!< CAN_T::MVLD1: MsgVal16_1 Mask */ + +#define CAN_MVLD2_MsgVal32_17_Pos (0) /*!< CAN_T::MVLD2: MsgVal32_17 Position */ +#define CAN_MVLD2_MsgVal32_17_Msk (0xfffful << CAN_MVLD2_MsgVal32_17_Pos) /*!< CAN_T::MVLD2: MsgVal32_17 Mask */ + +#define CAN_WU_EN_WAKUP_EN_Pos (0) /*!< CAN_T::WU_EN: WAKUP_EN Position */ +#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */ + +#define CAN_WU_STATUS_WAKUP_STS_Pos (0) /*!< CAN_T::WU_STATUS: WAKUP_STS Position */ +#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */ + +/**@}*/ /* CAN_CONST */ +/**@}*/ /* end of CAN register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CAN_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/clk_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/clk_reg.h new file mode 100644 index 00000000000..3d613b216b2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/clk_reg.h @@ -0,0 +1,1606 @@ +/**************************************************************************//** + * @file clk_reg.h + * @version V1.00 + * @brief CLK register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CLK_REG_H__ +#define __CLK_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CLK System Clock Controller(CLK) + Memory Mapped Structure for CLK Controller +@{ */ + +typedef struct +{ + + + /** + * @var CLK_T::PWRCTL + * Offset: 0x00 System Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTEN |HXT Enable Bit (Write Protect) + * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26] + * | | |When the default clock source is from HXT, this bit is set to 1 automatically. + * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. + * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |LXTEN |LXT Enable Bit (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled. + * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) + * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. + * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect) + * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. + * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC). + * | | |0 = Clock cycles delay Disabled. + * | | |1 = Clock cycles delay Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) + * | | |0 = Power-down mode wake-up interrupt Disabled. + * | | |1 = Power-down mode wake-up interrupt Enabled. + * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status + * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. + * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. + * |[7] |PDEN |System Power-down Enable (Write Protect) + * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. + * | | |When chip wakes up from Power-down mode, this bit is auto cleared + * | | |Users need to set this bit again for next Power-down. + * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. + * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection + * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. + * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI. + * | | |1 = Chip enters Power-down mode after CPU sleep command WFI. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally + * | | |If gain control is enabled, crystal will consume more power than gain control off. + * | | |00 = HXT frequency is lower than from 8 MHz. + * | | |01 = HXT frequency is from 8 MHz to 12 MHz. + * | | |10 = HXT frequency is from 12 MHz to 16 MHz. + * | | |11 = HXT frequency is higher than 16 MHz. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = Select INV type. + * | | |1 = Select GM type. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = HXT Crystal TURBO mode disabled. + * | | |1 = HXT Crystal TURBO mode enabled. + * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect) + * | | |00 = HIRC stable count is 64 clocks. + * | | |01 = HIRC stable count is 24 clocks. + * | | |others = Reserved. + * @var CLK_T::AHBCLK + * Offset: 0x04 AHB Devices Clock Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit + * | | |0 = PDMA peripheral clock Disabled. + * | | |1 = PDMA peripheral clock Enabled. + * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit + * | | |0 = Flash ISP peripheral clock Disabled. + * | | |1 = Flash ISP peripheral clock Enabled. + * |[3] |EBICKEN |EBI Controller Clock Enable Bit + * | | |0 = EBI peripheral clock Disabled. + * | | |1 = EBI peripheral clock Enabled. + * |[5] |EMACCKEN |Ethernet Controller Clock Enable Bit + * | | |0 = Ethernet Controller engine clock Disabled. + * | | |1 = Ethernet Controller engine clock Enabled. + * |[6] |SDH0CKEN |SD0 Controller Clock Enable Bit + * | | |0 = SD0 engine clock Disabled. + * | | |1 = SD0 engine clock Enabled. + * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit + * | | |0 = CRC peripheral clock Disabled. + * | | |1 = CRC peripheral clock Enabled. + * |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit + * | | |0 = HSUSB device controller's clock Disabled. + * | | |1 = HSUSB device controller's clock Enabled. + * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit + * | | |0 = Cryptographic Accelerator clock Disabled. + * | | |1 = Cryptographic Accelerator clock Enabled. + * |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit + * | | |0 = SPIM controller clock Disabled. + * | | |1 = SPIM controller clock Enabled. + * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode + * | | |0 = FMC clock Disabled when chip is under IDLE mode. + * | | |1 = FMC clock Enabled when chip is under IDLE mode. + * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit + * | | |0 = USB HOST peripheral clock Disabled. + * | | |1 = USB HOST peripheral clock Enabled. + * |[17] |SDH1CKEN |SD1 Controller Clock Enable Bit + * | | |0 = SD1 engine clock Disabled. + * | | |1 = SD1 engine clock Enabled. + * @var CLK_T::APBCLK0 + * Offset: 0x08 APB Devices Clock Enable Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) + * | | |0 = Watchdog timer clock Disabled. + * | | |1 = Watchdog timer clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit + * | | |This bit is used to control the RTC APB clock only + * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]) + * | | |It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC). + * | | |0 = RTC clock Disabled. + * | | |1 = RTC clock Enabled. + * |[2] |TMR0CKEN |Timer0 Clock Enable Bit + * | | |0 = Timer0 clock Disabled. + * | | |1 = Timer0 clock Enabled. + * |[3] |TMR1CKEN |Timer1 Clock Enable Bit + * | | |0 = Timer1 clock Disabled. + * | | |1 = Timer1 clock Enabled. + * |[4] |TMR2CKEN |Timer2 Clock Enable Bit + * | | |0 = Timer2 clock Disabled. + * | | |1 = Timer2 clock Enabled. + * |[5] |TMR3CKEN |Timer3 Clock Enable Bit + * | | |0 = Timer3 clock Disabled. + * | | |1 = Timer3 clock Enabled. + * |[6] |CLKOCKEN |CLKO Clock Enable Bit + * | | |0 = CLKO clock Disabled. + * | | |1 = CLKO clock Enabled. + * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit + * | | |0 = Analog comparator 0/1 clock Disabled. + * | | |1 = Analog comparator 0/1 clock Enabled. + * |[8] |I2C0CKEN |I2C0 Clock Enable Bit + * | | |0 = I2C0 clock Disabled. + * | | |1 = I2C0 clock Enabled. + * |[9] |I2C1CKEN |I2C1 Clock Enable Bit + * | | |0 = I2C1 clock Disabled. + * | | |1 = I2C1 clock Enabled. + * |[10] |I2C2CKEN |I2C2 Clock Enable Bit + * | | |0 = I2C2 clock Disabled. + * | | |1 = I2C2 clock Enabled. + * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit + * | | |0 = QSPI0 clock Disabled. + * | | |1 = QSPI0 clock Enabled. + * |[13] |SPI0CKEN |SPI0 Clock Enable Bit + * | | |0 = SPI0 clock Disabled. + * | | |1 = SPI0 clock Enabled. + * |[14] |SPI1CKEN |SPI1 Clock Enable Bit + * | | |0 = SPI1 clock Disabled. + * | | |1 = SPI1 clock Enabled. + * |[15] |SPI2CKEN |SPI2 Clock Enable Bit + * | | |0 = SPI2 clock Disabled. + * | | |1 = SPI2 clock Enabled. + * |[16] |UART0CKEN |UART0 Clock Enable Bit + * | | |0 = UART0 clock Disabled. + * | | |1 = UART0 clock Enabled. + * |[17] |UART1CKEN |UART1 Clock Enable Bit + * | | |0 = UART1 clock Disabled. + * | | |1 = UART1 clock Enabled. + * |[18] |UART2CKEN |UART2 Clock Enable Bit + * | | |0 = UART2 clock Disabled. + * | | |1 = UART2 clock Enabled. + * |[19] |UART3CKEN |UART3 Clock Enable Bit + * | | |0 = UART3 clock Disabled. + * | | |1 = UART3 clock Enabled. + * |[20] |UART4CKEN |UART4 Clock Enable Bit + * | | |0 = UART4 clock Disabled. + * | | |1 = UART4 clock Enabled. + * |[21] |UART5CKEN |UART5 Clock Enable Bit + * | | |0 = UART5 clock Disabled. + * | | |1 = UART5 clock Enabled. + * |[24] |CAN0CKEN |CAN0 Clock Enable Bit + * | | |0 = CAN0 clock Disabled. + * | | |1 = CAN0 clock Enabled. + * |[25] |CAN1CKEN |CAN1 Clock Enable Bit + * | | |0 = CAN1 clock Disabled. + * | | |1 = CAN1 clock Enabled. + * |[26] |OTGCKEN |USB OTG Clock Enable Bit + * | | |0 = USB OTG clock Disabled. + * | | |1 = USB OTG clock Enabled. + * |[27] |USBDCKEN |USB Device Clock Enable Bit + * | | |0 = USB Device clock Disabled. + * | | |1 = USB Device clock Enabled. + * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit + * | | |0 = EADC clock Disabled. + * | | |1 = EADC clock Enabled. + * |[29] |I2S0CKEN |I2S0 Clock Enable Bit + * | | |0 = I2S0 Clock Disabled. + * | | |1 = I2S0 Clock Enabled. + * |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit + * | | |0 = HSUSB OTG clock Disabled. + * | | |1 = HSUSB OTG clock Enabled. + * @var CLK_T::APBCLK1 + * Offset: 0x0C APB Devices Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0CKEN |SC0 Clock Enable Bit + * | | |0 = SC0 clock Disabled. + * | | |1 = SC0 clock Enabled. + * |[1] |SC1CKEN |SC1 Clock Enable Bit + * | | |0 = SC1 clock Disabled. + * | | |1 = SC1 clock Enabled. + * |[2] |SC2CKEN |SC2 Clock Enable Bit + * | | |0 = SC2 clock Disabled. + * | | |1 = SC2 clock Enabled. + * |[6] |SPI3CKEN |SPI3 Clock Enable Bit + * | | |0 = SPI3 clock Disabled. + * | | |1 = SPI3 clock Enabled. + * |[8] |USCI0CKEN |USCI0 Clock Enable Bit + * | | |0 = USCI0 clock Disabled. + * | | |1 = USCI0 clock Enabled. + * |[9] |USCI1CKEN |USCI1 Clock Enable Bit + * | | |0 = USCI1 clock Disabled. + * | | |1 = USCI1 clock Enabled. + * |[12] |DACCKEN |DAC Clock Enable Bit + * | | |0 = DAC clock Disabled. + * | | |1 = DAC clock Enabled. + * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit + * | | |0 = EPWM0 clock Disabled. + * | | |1 = EPWM0 clock Enabled. + * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit + * | | |0 = EPWM1 clock Disabled. + * | | |1 = EPWM1 clock Enabled. + * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit + * | | |0 = BPWM0 clock Disabled. + * | | |1 = BPWM0 clock Enabled. + * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit + * | | |0 = BPWM1 clock Disabled. + * | | |1 = BPWM1 clock Enabled. + * |[22] |QEI0CKEN |QEI0 Clock Enable Bit + * | | |0 = QEI0 clock Disabled. + * | | |1 = QEI0 clock Enabled. + * |[23] |QEI1CKEN |QEI1 Clock Enable Bit + * | | |0 = QEI1 clock Disabled. + * | | |1 = QEI1 clock Enabled. + * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit + * | | |0 = ECAP0 clock Disabled. + * | | |1 = ECAP0 clock Enabled. + * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit + * | | |0 = ECAP1 clock Disabled. + * | | |1 = ECAP1 clock Enabled. + * |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Bit + * | | |0 = OPA clock Disabled. + * | | |1 = OPA clock Enabled. + * @var CLK_T::CLKSEL0 + * Offset: 0x10 Clock Source Select Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset + * | | |Therefore the default value is either 000b or 111b. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from PLL. + * | | |011 = Clock source from LIRC. + * | | |111 = Clock source from HIRC. + * | | |Other = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect) + * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from HXT/2. + * | | |011 = Clock source from HCLK/2. + * | | |111 = Clock source from HIRC/2. + * | | |Note: if SysTick clock source is not from HCLK (i.e + * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[21:20] |SDH0SEL |SD0 Engine Clock Source Selection (Write Protect) + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from HIRC clock. + * |[23:22] |SDH1SEL |SD1 Engine Clock Source Selection (Write Protect) + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from HIRC clock. + * @var CLK_T::CLKSEL1 + * Offset: 0x14 Clock Source Select Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) + * | | |00 = Reserved. + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM0 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM1 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM2 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM3 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[25:24] |UART0SEL |UART0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[27:26] |UART1SEL |UART1 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * @var CLK_T::CLKSEL2 + * Offset: 0x18 Clock Source Select Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EPWM0SEL |EPWM0 Clock Source Selection + * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK0. + * |[1] |EPWM1SEL |EPWM1 Clock Source Selection + * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK1. + * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SPI0SEL |SPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[7:6] |SPI1SEL |SPI1 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[8] |BPWM0SEL |BPWM0 Clock Source Selection + * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK0. + * |[9] |BPWM1SEL |BPWM1 Clock Source Selection + * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK1. + * |[11:10] |SPI2SEL |SPI2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[13:12] |SPI3SEL |SPI3 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * @var CLK_T::CLKSEL3 + * Offset: 0x1C Clock Source Select Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SC0SEL |SC0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[3:2] |SC1SEL |SC0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SC2SEL |SC2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[8] |RTCSEL |RTC Clock Source Selection + * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * |[17:16] |I2S0SEL |I2S0 Clock Source Selection + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from PCLK. + * | | |11 = Clock source from HIRC clock. + * |[25:24] |UART2SEL |UART2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[27:26] |UART3SEL |UART3 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[29:28] |UART4SEL |UART4 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |UART5SEL |UART5 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * @var CLK_T::CLKDIV0 + * Offset: 0x20 Clock Divider Number Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source + * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). + * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock + * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1). + * |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source + * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). + * |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source + * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). + * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source + * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). + * |[31:24] |SDH0DIV |SD0 Clock Divide Number From SD0 Clock Source + * | | |SD0 clock frequency = (SD0 clock source frequency) / (SDH0DIV + 1). + * @var CLK_T::CLKDIV1 + * Offset: 0x24 Clock Divider Number Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source + * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1). + * |[15:8] |SC1DIV |SC1 Clock Divide Number From SC1 Clock Source + * | | |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1). + * |[23:16] |SC2DIV |SC2 Clock Divide Number From SC2 Clock Source + * | | |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1). + * @var CLK_T::CLKDIV3 + * Offset: 0x2C Clock Divider Number Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |EMACDIV |Ethernet Clock Divide Number Form HCLK + * | | |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1). + * |[31:24] |SDH1DIV |SD1 Clock Divide Number From SD1 Clock Source + * | | |SD1 clock frequency = (SD1 clock source frequency) / (SDH1DIV + 1). + * @var CLK_T::CLKDIV4 + * Offset: 0x30 Clock Divider Number Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source + * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). + * |[7:4] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source + * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). + * |[11:8] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source + * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). + * |[15:12] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source + * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). + * @var CLK_T::PCLKDIV + * Offset: 0x34 APB Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |APB0DIV |APB0 Clock Divider + * | | |APB0 clock can be divided from HCLK + * | | |000: PCLK0 = HCLK. + * | | |001: PCLK0 = 1/2 HCLK. + * | | |010: PCLK0 = 1/4 HCLK. + * | | |011: PCLK0 = 1/8 HCLK. + * | | |100: PCLK0 = 1/16 HCLK. + * | | |Others: Reserved. + * |[6:4] |APB1DIV |APB1 Clock Divider + * | | |APB1 clock can be divided from HCLK + * | | |000: PCLK1 = HCLK. + * | | |001: PCLK1 = 1/2 HCLK. + * | | |010: PCLK1 = 1/4 HCLK. + * | | |011: PCLK1 = 1/8 HCLK. + * | | |100: PCLK1 = 1/16 HCLK. + * | | |Others: Reserved. + * @var CLK_T::PLLCTL + * Offset: 0x40 PLL Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |PD |Power-down Mode (Write Protect) + * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. + * | | |0 = PLL is in normal mode. + * | | |1 = PLL is in Power-down mode (default). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock FIN. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect) + * | | |0 = PLL FOUT Enabled. + * | | |1 = PLL FOUT is fixed low. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) + * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). + * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) + * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz). + * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[28] |BANDSEL |PLL Stable Counter Selection (Write Protect) + * | | |0 = PLL low band frequency select. (FVCO range is 200MHz ~ 400MHZ) + * | | |1 = PLL high band frequency select. (FVCO range is 400MHz ~ 500MHZ) + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::STATUS + * Offset: 0x50 Clock Status Monitor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. + * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. + * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) + * | | |0 = Internal PLL clock is not stable or disabled. + * | | |1 = Internal PLL clock is stable and enabled. + * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) + * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. + * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. + * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. + * | | |Note: This bit is read only. + * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) + * | | |This bit is updated when software switches system clock source + * | | |If switch target clock is stable, this bit will be set to 0 + * | | |If switch target clock is not stable, this bit will be set to 1. + * | | |0 = Clock switching success. + * | | |1 = Clock switching failure. + * | | |Note: Write 1 to clear the bit to 0. + * @var CLK_T::CLKOCTL + * Offset: 0x60 Clock Output Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |FREQSEL |Clock Output Frequency Selection + * | | |The formula of output frequency is + * | | |Fout = Fin/2(N+1). + * | | |Fin is the input clock frequency. + * | | |Fout is the frequency of divider output clock. + * | | |N is the 4-bit value of FREQSEL[3:0]. + * |[4] |CLKOEN |Clock Output Enable Bit + * | | |0 = Clock Output function Disabled. + * | | |1 = Clock Output function Enabled. + * |[5] |DIV1EN |Clock Output Divide One Enable Bit + * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. + * | | |1 = Clock Output will output clock with source frequency. + * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit + * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. + * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. + * @var CLK_T::CLKDCTL + * Offset: 0x70 Clock Fail Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. + * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. + * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. + * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. + * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled. + * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled. + * @var CLK_T::CLKDSTS + * Offset: 0x74 Clock Fail Detector Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. + * | | |Note: Write 1 to clear the bit to 0. + * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. + * | | |Note: Write 1 to clear the bit to 0. + * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. + * | | |Note: Write 1 to clear the bit to 0. + * @var CLK_T::CDUPB + * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value + * | | |The bits define the maximum value of frequency range detector window. + * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. + * @var CLK_T::CDLOWB + * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value + * | | |The bits define the minimum value of frequency range detector window. + * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. + * @var CLK_T::PMUCTL + * Offset: 0x90 Power Manager Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. + * | | |000 = Power-down mode is selected. (PD) + * | | |001 = Low leakage Power-down mode is selected (LLPD). + * | | |010 =Fast wake-up Power-down mode is selected (FWPD). + * | | |011 = Reserved. + * | | |100 = Standby Power-down mode 0 is selected (SPD0) (SRAM retention). + * | | |101 = Standby Power-down mode 1 is selected (SPD1). + * | | |110 = Deep Power-down mode is selected (DPD). + * | | |111 = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |WKTMREN |Wake-up Timer Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = Wake-up timer disable at DPD/SPD mode. + * | | |1 = Wake-up timer enabled at DPD/SPD mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode. + * | | |000 = Time-out interval is 128 OSC10K clocks (12.8 ms). + * | | |001 = Time-out interval is 256 OSC10K clocks (25.6 ms). + * | | |010 = Time-out interval is 512 OSC10K clocks (51.2 ms). + * | | |011 = Time-out interval is 1024 OSC10K clocks (102.4ms). + * | | |100 = Time-out interval is 4096 OSC10K clocks (409.6ms). + * | | |101 = Time-out interval is 8192 OSC10K clocks (819.2ms). + * | | |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms). + * | | |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |00 = Wake-up pin disable at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = ACMP wake-up disable at Standby Power-down mode. + * | | |1 = ACMP wake-up enabled at Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode. + * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::PMUSTS + * Offset: 0x94 Power Manager Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINWK |Pin Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0) + * | | |This flag is cleared when DPD mode is entered. + * |[1] |TMRWK |Timer Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out + * | | |This flag is cleared when DPD or SPD mode is entered. + * |[2] |RTCWK |RTC Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened + * | | |This flag is cleared when DPD or SPD mode is entered. + * |[8] |GPAWK |GPA Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins + * | | |This flag is cleared when SPD mode is entered. + * |[9] |GPBWK |GPB Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins + * | | |This flag is cleared when SPD mode is entered. + * |[10] |GPCWK |GPC Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins + * | | |This flag is cleared when SPD mode is entered. + * |[11] |GPDWK |GPD Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins + * | | |This flag is cleared when SPD mode is entered. + * |[12] |LVRWK |LVR Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened + * | | |This flag is cleared when SPD mode is entered. + * |[13] |BODWK |BOD Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened + * | | |This flag is cleared when SPD mode is entered. + * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition + * | | |This flag is cleared when SPD mode is entered. + * |[31] |CLRWK |Clear Wake-up Flag + * | | |0 = No clear. + * | | |1 = Clear all wake-up flag. + * @var CLK_T::LDOCTL + * Offset: 0x98 LDO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18] |PDBIASEN |Power-down Bias Enable Bit + * | | |0 = Reserved. + * | | |1 = Power-down bias enabled. + * | | |Note: This bit should set to 1 before chip enter power-down mode. + * @var CLK_T::SWKDBCTL + * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection + * | | |0000 = Sample wake-up input once per 1 clocks. + * | | |0001 = Sample wake-up input once per 2 clocks. + * | | |0010 = Sample wake-up input once per 4 clocks. + * | | |0011 = Sample wake-up input once per 8 clocks. + * | | |0100 = Sample wake-up input once per 16 clocks. + * | | |0101 = Sample wake-up input once per 32 clocks. + * | | |0110 = Sample wake-up input once per 64 clocks. + * | | |0111 = Sample wake-up input once per 128 clocks. + * | | |1000 = Sample wake-up input once per 256 clocks. + * | | |1001 = Sample wake-up input once per 2*256 clocks. + * | | |1010 = Sample wake-up input once per 4*256 clocks. + * | | |1011 = Sample wake-up input once per 8*256 clocks. + * | | |1100 = Sample wake-up input once per 16*256 clocks. + * | | |1101 = Sample wake-up input once per 32*256 clocks. + * | | |1110 = Sample wake-up input once per 64*256 clocks. + * | | |1111 = Sample wake-up input once per 128*256 clocks. + * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * @var CLK_T::PASWKCTL + * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPA group pin wake-up function disabled. + * | | |1 = GPA group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPA group pin rising edge wake-up function disabled. + * | | |1 = GPA group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPA group pin falling edge wake-up function disabled. + * | | |1 = GPA group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select + * | | |0000 = GPA.0 wake-up function enabled. + * | | |0001 = GPA.1 wake-up function enabled. + * | | |0010 = GPA.2 wake-up function enabled. + * | | |0011 = GPA.3 wake-up function enabled. + * | | |0100 = GPA.4 wake-up function enabled. + * | | |0101 = GPA.5 wake-up function enabled. + * | | |0110 = GPA.6 wake-up function enabled. + * | | |0111 = GPA.7 wake-up function enabled. + * | | |1000 = GPA.8 wake-up function enabled. + * | | |1001 = GPA.9 wake-up function enabled. + * | | |1010 = GPA.10 wake-up function enabled. + * | | |1011 = GPA.11 wake-up function enabled. + * | | |1100 = GPA.12 wake-up function enabled. + * | | |1101 = GPA.13 wake-up function enabled. + * | | |1110 = GPA.14 wake-up function enabled. + * | | |1111 = GPA.15 wake-up function enabled. + * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PBSWKCTL + * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPB group pin wake-up function disabled. + * | | |1 = GPB group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPB group pin rising edge wake-up function disabled. + * | | |1 = GPB group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPB group pin falling edge wake-up function disabled. + * | | |1 = GPB group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select + * | | |0000 = GPB.0 wake-up function enabled. + * | | |0001 = GPB.1 wake-up function enabled. + * | | |0010 = GPB.2 wake-up function enabled. + * | | |0011 = GPB.3 wake-up function enabled. + * | | |0100 = GPB.4 wake-up function enabled. + * | | |0101 = GPB.5 wake-up function enabled. + * | | |0110 = GPB.6 wake-up function enabled. + * | | |0111 = GPB.7 wake-up function enabled. + * | | |1000 = GPB.8 wake-up function enabled. + * | | |1001 = GPB.9 wake-up function enabled. + * | | |1010 = GPB.10 wake-up function enabled. + * | | |1011 = GPB.11 wake-up function enabled. + * | | |1100 = GPB.12 wake-up function enabled. + * | | |1101 = GPB.13 wake-up function enabled. + * | | |1110 = GPB.14 wake-up function enabled. + * | | |1111 = GPB.15 wake-up function enabled. + * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PCSWKCTL + * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPC group pin wake-up function disabled. + * | | |1 = GPC group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPC group pin rising edge wake-up function disabled. + * | | |1 = GPC group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPC group pin falling edge wake-up function disabled. + * | | |1 = GPC group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select + * | | |0000 = GPC.0 wake-up function enabled. + * | | |0001 = GPC.1 wake-up function enabled. + * | | |0010 = GPC.2 wake-up function enabled. + * | | |0011 = GPC.3 wake-up function enabled. + * | | |0100 = GPC.4 wake-up function enabled. + * | | |0101 = GPC.5 wake-up function enabled. + * | | |0110 = GPC.6 wake-up function enabled. + * | | |0111 = GPC.7 wake-up function enabled. + * | | |1000 = GPC.8 wake-up function enabled. + * | | |1001 = GPC.9 wake-up function enabled. + * | | |1010 = GPC.10 wake-up function enabled. + * | | |1011 = GPC.11 wake-up function enabled. + * | | |1100 = GPC.12 wake-up function enabled. + * | | |1101 = GPC.13 wake-up function enabled. + * | | |1110 = GPC.14 wake-up function enabled. + * | | |1111 = GPC.15 wake-up function enabled. + * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PDSWKCTL + * Offset: 0xAC GPD Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPD group pin wake-up function disabled. + * | | |1 = GPD group pin wake-up function enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPD group pin rising edge wake-up function disabled. + * | | |1 = GPD group pin rising edge wake-up function enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPD group pin falling edge wake-up function disabled. + * | | |1 = GPD group pin falling edge wake-up function enabled. + * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select + * | | |0000 = GPD.0 wake-up function enabled. + * | | |0001 = GPD.1 wake-up function enabled. + * | | |0010 = GPD.2 wake-up function enabled. + * | | |0011 = GPD.3 wake-up function enabled. + * | | |0100 = GPD.4 wake-up function enabled. + * | | |0101 = GPD.5 wake-up function enabled. + * | | |0110 = GPD.6 wake-up function enabled. + * | | |0111 = GPD.7 wake-up function enabled. + * | | |1000 = GPD.8 wake-up function enabled. + * | | |1001 = GPD.9 wake-up function enabled. + * | | |1010 = GPD.10 wake-up function enabled. + * | | |1011 = GPD.11 wake-up function enabled. + * | | |1100 = GPD.12 wake-up function enabled. + * | | |1101 = GPD.13 wake-up function enabled. + * | | |1110 = GPD.14 wake-up function enabled. + * | | |1111 = GPD.15 wake-up function enabled. + * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. + * | | |0 = Standby power-down wake-up pin De-bounce function disable. + * | | |1 = Standby power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::IOPDCTL + * Offset: 0xB0 GPIO Standby Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IOHR |GPIO Hold Release + * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status + * | | |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. + * | | |This bit is auto cleared by hardware. + */ + __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ + __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ + __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ + __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */ + __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ + __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ + __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ + __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */ + __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ + __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[1]; + /** @endcond */ + __IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */ + __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ + __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[2]; + /** @endcond */ + __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[3]; + /** @endcond */ + __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE3[3]; + /** @endcond */ + __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE4[3]; + /** @endcond */ + __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ + __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ + __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */ + __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE5[4]; + /** @endcond */ + __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ + __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ + __IO uint32_t LDOCTL; /*!< [0x0098] LDO Control Register */ + __IO uint32_t SWKDBCTL; /*!< [0x009c] Standby Power-down Wake-up De-bounce Control Register */ + __IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */ + __IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */ + __IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */ + __IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */ + __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */ + +} CLK_T; + +/** + @addtogroup CLK_CONST CLK Bit Field Definition + Constant Definitions for CLK Controller +@{ */ + +#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ +#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ + +#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ +#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ + +#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ +#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ + +#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ +#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ + +#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */ +#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */ + +#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ +#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ + +#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ +#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ + +#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ +#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ + +#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ +#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ + +#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ +#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ + +#define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */ +#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */ + +#define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */ +#define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */ + +#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */ +#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */ + +#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ +#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ + +#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ +#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ + +#define CLK_AHBCLK_EMACCKEN_Pos (5) /*!< CLK_T::AHBCLK: EMACCKEN Position */ +#define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /*!< CLK_T::AHBCLK: EMACCKEN Mask */ + +#define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */ +#define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */ + +#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ +#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ + +#define CLK_AHBCLK_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK: HSUSBDCKEN Position */ +#define CLK_AHBCLK_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK: HSUSBDCKEN Mask */ + +#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ +#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ + +#define CLK_AHBCLK_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK: SPIMCKEN Position */ +#define CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK: SPIMCKEN Mask */ + +#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ +#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ + +#define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */ +#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */ + +#define CLK_AHBCLK_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK: SDH1CKEN Position */ +#define CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK: SDH1CKEN Mask */ + +#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ +#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ + +#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ +#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ + +#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ +#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ + +#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ +#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ + +#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ +#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ + +#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ +#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ + +#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ +#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ + +#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ +#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ + +#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ +#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ + +#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ +#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ + +#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ +#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ + +#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ +#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ +#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ +#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ + +#define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ +#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ + +#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ +#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ + +#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ +#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ + +#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ +#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ + +#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ +#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ + +#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ +#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ + +#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ +#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ + +#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ +#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ + +#define CLK_APBCLK0_CAN1CKEN_Pos (25) /*!< CLK_T::APBCLK0: CAN1CKEN Position */ +#define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /*!< CLK_T::APBCLK0: CAN1CKEN Mask */ + +#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ +#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ + +#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ +#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ + +#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ +#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ + +#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ +#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ + +#define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */ +#define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */ + +#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ +#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ + +#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ +#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ + +#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ +#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ + +#define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ +#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ + +#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ +#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ + +#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ +#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ + +#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ +#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ + +#define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ +#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ + +#define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ +#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ + +#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ +#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ + +#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ +#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ + +#define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */ +#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */ + +#define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */ +#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */ + +#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ +#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ + +#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ +#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ + +#define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK_T::APBCLK1: OPACKEN Position */ +#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK_T::APBCLK1: OPACKEN Mask */ + +#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ +#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ + +#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ +#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ + +#if(0) +#define CLK_CLKSEL0_PCLK0SEL_Pos (6) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */ +#define CLK_CLKSEL0_PCLK0SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */ + +#define CLK_CLKSEL0_PCLK1SEL_Pos (7) /*!< CLK_T::CLKSEL0: PCLK1SEL Position */ +#define CLK_CLKSEL0_PCLK1SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK1SEL Mask */ +#endif + +#define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ +#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ + +#define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */ +#define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */ + +#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ +#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ + +#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ +#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ + +#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ +#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ + +#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ +#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ + +#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ +#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ + +#define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ +#define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ + +#define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */ +#define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ + +#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ +#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ + +#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ +#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ + +#define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ +#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ + +#define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ +#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ + +#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ +#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ +#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ +#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ + +#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ +#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ + +#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ +#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ + +#define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */ +#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */ + +#define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ +#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ + +#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ +#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ + +#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ +#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ + +#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ +#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ + +#define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */ +#define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */ + +#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ +#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ + +#define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ +#define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ + +#define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */ +#define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */ + +#define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */ +#define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ + +#define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */ +#define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ + +#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ +#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ + +#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ +#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ + +#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ +#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ + +#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ +#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ + +#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ +#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ + +#define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ +#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ + +#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ +#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ + +#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ +#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ + +#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ +#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ + +#define CLK_CLKDIV3_EMACDIV_Pos (16) /*!< CLK_T::CLKDIV3: EMACDIV Position */ +#define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLK_T::CLKDIV3: EMACDIV Mask */ + +#define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */ +#define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */ + +#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ +#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ + +#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ +#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ + +#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ +#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ + +#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ +#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ + +#define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ +#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ + +#define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ +#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ + +#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ +#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ + +#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ +#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ + +#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ +#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ + +#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ +#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ + +#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ +#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ + +#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ +#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ + +#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ +#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ + +#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ +#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ + +#define CLK_PLLCTL_BANDSEL_Pos (28) /*!< CLK_T::PLLCTL: BANDSEL Position */ +#define CLK_PLLCTL_BANDSEL_Msk (0x1ul << CLK_PLLCTL_BANDSEL_Pos) /*!< CLK_T::PLLCTL: BANDSEL Mask */ + +#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ +#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ + +#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ +#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ + +#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ +#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ + +#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ +#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ + +#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ +#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ + +#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ +#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ + +#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ +#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ + +#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ +#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ + +#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ +#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ + +#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ +#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ + +#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ +#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ + +#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ +#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ + +#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ +#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ + +#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ +#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ + +#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ +#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ + +#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ +#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ + +#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ +#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ + +#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ +#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ + +#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ +#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ + +#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ +#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ + +#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ +#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ + +#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ +#define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ + +#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ +#define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ + +#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ +#define CLK_PMUCTL_WKTMRIS_Msk (0x7ul << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ + +#define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */ +#define CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */ + +#define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ +#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ + +#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ +#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ + +#define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */ +#define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */ + +#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ +#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ + +#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ +#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ + +#define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ +#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ + +#define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ +#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ + +#define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ +#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ + +#define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ +#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ + +#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ +#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ + +#define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ +#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ + +#define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */ +#define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */ + +#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ +#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ + +#define CLK_LDOCTL_PDBIASEN_Pos (18) /*!< CLK_T::LDOCTL: PDBIASEN Position */ +#define CLK_LDOCTL_PDBIASEN_Msk (0x1ul << CLK_LDOCTL_PDBIASEN_Pos) /*!< CLK_T::LDOCTL: PDBIASEN Mask */ + +#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ + +#define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ +#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ + +#define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ +#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ + +#define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ +#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ + +#define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ +#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ + +#define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ +#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ + +#define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ +#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ + +#define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ +#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ + +#define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ +#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ + +#define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ +#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ + +#define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ +#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ + +#define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ +#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ + +#define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ +#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ + +#define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ +#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ + +#define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ +#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ + +#define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ +#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ + +#define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ +#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ + +#define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ +#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ + +#define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ +#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ + +#define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ +#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ + +#define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ +#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ + +#define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ +#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ + +/**@}*/ /* CLK_CONST */ +/**@}*/ /* end of CLK register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CLK_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crc_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crc_reg.h new file mode 100644 index 00000000000..6e12a14285d --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crc_reg.h @@ -0,0 +1,149 @@ +/**************************************************************************//** + * @file crc_reg.h + * @version V1.00 + * @brief CRC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_REG_H__ +#define __CRC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CRC Cyclic Redundancy Check Controller(CRC) + Memory Mapped Structure for CRC Controller +@{ */ + +typedef struct +{ + + + /** + * @var CRC_T::CTL + * Offset: 0x00 CRC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRCEN |CRC Channel Enable Bit + * | | |0 = No effect. + * | | |1 = CRC operation Enabled. + * |[1] |CHKSINIT |Checksum Initialization + * | | |0 = No effect. + * | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value. + * | | |Note: This bit will be cleared automatically. + * |[24] |DATREV |Write Data Bit Order Reverse + * | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register. + * | | |0 = Bit order reversed for CRC write data in Disabled. + * | | |1 = Bit order reversed for CRC write data in Enabled (per byte). + * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. + * |[25] |CHKSREV |Checksum Bit Order Reverse + * | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. + * | | |0 = Bit order reverse for CRC checksum Disabled. + * | | |1 = Bit order reverse for CRC checksum Enabled. + * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. + * |[26] |DATFMT |Write Data 1's Complement + * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register. + * | | |0 = 1's complement for CRC writes data in Disabled. + * | | |1 = 1's complement for CRC writes data in Enabled. + * |[27] |CHKSFMT |Checksum 1's Complement + * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. + * | | |0 = 1's complement for CRC checksum Disabled. + * | | |1 = 1's complement for CRC checksum Enabled. + * |[29:28] |DATLEN |CPU Write Data Length + * | | |This field indicates the write data length. + * | | |00 = Data length is 8-bit mode. + * | | |01 = Data length is 16-bit mode. + * | | |1x = Data length is 32-bit mode. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0] + * |[31:30] |CRCMODE |CRC Polynomial Mode + * | | |This field indicates the CRC operation polynomial mode. + * | | |00 = CRC-CCITT Polynomial mode. + * | | |01 = CRC-8 Polynomial mode. + * | | |10 = CRC-16 Polynomial mode. + * | | |11 = CRC-32 Polynomial mode. + * @var CRC_T::DAT + * Offset: 0x04 CRC Write Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |CRC Write Data Bits + * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. + * @var CRC_T::SEED + * Offset: 0x08 CRC Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |CRC Seed Value + * | | |This field indicates the CRC seed value. + * | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]). + * @var CRC_T::CHECKSUM + * Offset: 0x0C CRC Checksum Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CHECKSUM |CRC Checksum Results + * | | |This field indicates the CRC checksum result. + */ + __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */ + __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */ + __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */ + __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */ + +} CRC_T; + +/** + @addtogroup CRC_CONST CRC Bit Field Definition + Constant Definitions for CRC Controller +@{ */ + +#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */ +#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */ + +#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */ +#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */ + +#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */ +#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */ + +#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */ +#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */ + +#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */ +#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */ + +#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */ +#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */ + +#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */ +#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */ + +#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */ +#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */ + +#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */ +#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */ + +#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */ +#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */ + +#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */ +#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */ + +/**@}*/ /* CRC_CONST */ +/**@}*/ /* end of CRC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CRC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crypto_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crypto_reg.h new file mode 100644 index 00000000000..ae75c9c7cd7 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/crypto_reg.h @@ -0,0 +1,2218 @@ +/**************************************************************************//** + * @file crypto_reg.h + * @version V1.00 + * @brief CRYPTO register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRYPTO_REG_H__ +#define __CRYPTO_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CRPT Cryptographic Accelerator(CRPT) + Memory Mapped Structure for Cryptographic Accelerator +@{ */ + +typedef struct +{ + + /** + * @var CRPT_T::INTEN + * Offset: 0x00 Crypto Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIEN |AES Interrupt Enable Control + * | | |0 = AES interrupt Disabled. + * | | |1 = AES interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. + * |[1] |AESEIEN |AES Error Flag Enable Control + * | | |0 = AES error interrupt flag Disabled. + * | | |1 = AES error interrupt flag Enabled. + * |[8] |TDESIEN |TDES/DES Interrupt Enable Control + * | | |0 = TDES/DES interrupt Disabled. + * | | |1 = TDES/DES interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation. + * |[9] |TDESEIEN |TDES/DES Error Flag Enable Control + * | | |0 = TDES/DES error interrupt flag Disabled. + * | | |1 = TDES/DES error interrupt flag Enabled. + * |[16] |PRNGIEN |PRNG Interrupt Enable Control + * | | |0 = PRNG interrupt Disabled. + * | | |1 = PRNG interrupt Enabled. + * |[22] |ECCIEN |ECC Interrupt Enable Control + * | | |0 = ECC interrupt Disabled. + * | | |1 = ECC interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. + * |[23] |ECCEIEN |ECC Error Interrupt Enable Control + * | | |0 = ECC error interrupt flag Disabled. + * | | |1 = ECC error interrupt flag Enabled. + * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Control + * | | |0 = SHA/HMAC interrupt Disabled. + * | | |1 = SHA/HMAC interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation. + * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Control + * | | |0 = SHA/HMAC error interrupt flag Disabled. + * | | |1 = SHA/HMAC error interrupt flag Enabled. + * @var CRPT_T::INTSTS + * Offset: 0x04 Crypto Interrupt Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIF |AES Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No AES interrupt. + * | | |= AES encryption/decryption done interrupt. + * |[1] |AESEIF |AES Error Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No AES error. + * | | |1 = AES encryption/decryption done interrupt. + * |[8] |TDESIF |TDES/DES Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No TDES/DES interrupt. + * | | |1 = TDES/DES encryption/decryption done interrupt. + * |[9] |TDESEIF |TDES/DES Error Flag + * | | |This bit includes the operating and setting error + * | | |The detailed flag is shown in the CRPT_TDES_STS register + * | | |This includes operating and setting error. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No TDES/DES error. + * | | |1 = TDES/DES encryption/decryption error interrupt. + * |[16] |PRNGIF |PRNG Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No PRNG interrupt. + * | | |1 = PRNG key generation done interrupt. + * |[22] |ECCIF |ECC Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No ECC interrupt. + * | | |1 = ECC operation done interrupt. + * |[23] |ECCEIF |ECC Error Flag + * | | |This register includes operating and setting error. The detail flag is shown in CRPT_ECC_STS register. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No ECC error. + * | | |1 = ECC error interrupt. + * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No SHA/HMAC interrupt. + * | | |1 = SHA/HMAC operation done interrupt. + * |[25] |HMACEIF |SHA/HMAC Error Flag + * | | |This register includes operating and setting error. The detail flag is shown in CRPT_HMAC_STS register. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No SHA/HMAC error. + * | | |1 = SHA/HMAC error interrupt. + * @var CRPT_T::PRNG_CTL + * Offset: 0x08 PRNG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Start PRNG Engine + * | | |0 = Stop PRNG engine. + * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated. + * |[1] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * |[3:2] |KEYSZ |PRNG Generate Key Size + * | | |00 = 64 bits. + * | | |01 = 128 bits. + * | | |10 = 192 bits. + * | | |11 = 256 bits. + * |[8] |BUSY |PRNG Busy (Read Only) + * | | |0 = PRNG engine is idle. + * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. + * @var CRPT_T::PRNG_SEED + * Offset: 0x0C Seed for PRNG + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed for PRNG (Write Only) + * | | |The bits store the seed for PRNG engine. + * @var CRPT_T::PRNG_KEY[8] + * Offset: 0x10 ~ 0x2C PRNG Generated Key0 ~ Key7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::AES_FDBCK[4] + * Offset: 0x50 ~ 0x5C AES Engine Output Feedback Data after Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting. + * @var CRPT_T::TDES_FDBCKH + * Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |TDES/DES Feedback + * | | |The feedback value is 64 bits in size. + * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode + * | | |The feedback register is for CBC, CFB, and OFB mode. + * | | |TDES/DES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to this register in the same channel operation + * | | |Then can continue the operation with the original setting. + * @var CRPT_T::TDES_FDBCKL + * Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |TDES/DES Feedback + * | | |The feedback value is 64 bits in size. + * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode + * | | |The feedback register is for CBC, CFB, and OFB mode. + * | | |TDES/DES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to this register in the same channel operation + * | | |Then can continue the operation with the original setting. + * @var CRPT_T::AES_CTL + * Offset: 0x100 AES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |AES Engine Start + * | | |0 = No effect. + * | | |1 = Start AES engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it's read back. + * |[1] |STOP |AES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop AES engine. + * | | |Note: This bit is always 0 when it's read back. + * |[3:2] |KEYSZ |AES Key Size + * | | |This bit defines three different key size for AES operation. + * | | |2'b00 = 128 bits key. + * | | |2'b01 = 192 bits key. + * | | |2'b10 = 256 bits key. + * | | |2'b11 = Reserved. + * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. + * |[5] |DMALAST |AES Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. + * | | |This bit is always 0 when it's read back. Must be written again once START is triggered. + * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |AES Engine DMA Enable Control + * | | |0 = AES DMA engine Disabled. + * | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN. + * | | |1 = AES_DMA engine Enabled. + * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[15:8] |OPMODE |AES Engine Operation Modes + * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). + * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). + * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). + * |[16] |ENCRPT |AES Encryption/Decryption + * | | |0 = AES engine executes decryption operation. + * | | |1 = AES engine executes encryption operation. + * |[22] |OUTSWAP |AES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |AES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[25:24] |CHANNEL |AES Engine Working Channel + * | | |00 = Current control register setting is for channel 0. + * | | |01 = Current control register setting is for channel 1. + * | | |10 = Current control register setting is for channel 2. + * | | |11 = Current control register setting is for channel 3. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRPT_AES_CTL[31] and "10110" to CRPT_AES_CTL[30:26] is to unprotect the AES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = Protect the content of the AES key from reading + * | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |And the key content would be cleared as well. + * @var CRPT_T::AES_STS + * Offset: 0x104 AES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |AES Engine Busy + * | | |0 = The AES engine is idle or finished. + * | | |1 = The AES engine is under processing. + * |[8] |INBUFEMPTY|AES Input Buffer Empty + * | | |0 = There are some data in input buffer waiting for the AES engine to process. + * | | |1 = AES input buffer is empty + * | | |Software needs to feed data to the AES engine + * | | |Otherwise, the AES engine will be pending to wait for input data. + * |[9] |INBUFFULL |AES Input Buffer Full Flag + * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. + * | | |1 = AES input buffer is full + * | | |Software cannot feed data to the AES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |AES Input Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during feeding data to the AES engine. + * |[12] |CNTERR |CRPT_AESn_CNT Setting Error + * | | |0 = No error in CRPT_AESn_CNT setting. + * | | |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode. + * |[16] |OUTBUFEMPTY|AES Out Buffer Empty + * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = AES output buffer is empty + * | | |Software cannot get data from CRPT_AES_DATOUT + * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. + * |[17] |OUTBUFFULL|AES Out Buffer Full Flag + * | | |0 = AES output buffer is not full. + * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT + * | | |Otherwise, the AES engine will be pending since the output buffer is full. + * |[18] |OUTBUFERR |AES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during getting the result from AES engine. + * |[20] |BUSERR |AES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and AES engine. + * @var CRPT_T::AES_DATIN + * Offset: 0x108 AES Engine Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |AES Engine Input Port + * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. + * @var CRPT_T::AES_DATOUT + * Offset: 0x10C AES Engine Data Output Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |AES Engine Output Port + * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRPT_T::AES0_KEY[8] + * Offset: 0x110 ~ 0x12C AES Key Word 0 ~ 7 Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES0_IV[4] + * Offset: 0x130 ~ 0x13C AES Initial Vector Word 0 ~ 3 Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES0_SADDR + * Offset: 0x140 AES DMA Source Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES0_DADDR + * Offset: 0x144 AES DMA Destination Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES0_CNT + * Offset: 0x148 AES Byte Count Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::AES1_KEY[8] + * Offset: 0x14C ~ 0x168 AES Key Word 0 ~ 7 Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES1_IV[4] + * Offset: 0x16C ~ 0x178 AES Initial Vector Word 0 ~ 3 Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES1_SADDR + * Offset: 0x17C AES DMA Source Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES1_DADDR + * Offset: 0x180 AES DMA Destination Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES1_CNT + * Offset: 0x184 AES Byte Count Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::AES2_KEY[8] + * Offset: 0x188 ~ 0x1A4 AES Key Word 0 ~ 7 Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES2_IV[4] + * Offset: 0x1A8 ~ 0x1B4 AES Initial Vector Word 0 ~ 3 Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES2_SADDR + * Offset: 0x1B8 AES DMA Source Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES2_DADDR + * Offset: 0x1BC AES DMA Destination Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES2_CNT + * Offset: 0x1C0 AES Byte Count Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::AES3_KEY[8] + * Offset: 0x1C4 ~ 0x1E0 AES Key Word 0 ~ 7 Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |n = 0, 1..3. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES3_IV[4] + * Offset: 0x1E4 ~ 0x1F0 AES Initial Vector Word 0 ~ 3 Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |n = 0, 1..3. + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES3_SADDR + * Offset: 0x1F4 AES DMA Source Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES3_DADDR + * Offset: 0x1F8 AES DMA Destination Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. + * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. + * @var CRPT_T::AES3_CNT + * Offset: 0x1FC AES Byte Count Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block + * | | |Operations that are less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * @var CRPT_T::TDES_CTL + * Offset: 0x200 TDES/DES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |TDES/DES Engine Start + * | | |0 = No effect. + * | | |1 = Start TDES/DES engine. The flag BUSY would be set. + * | | |Note: The bit is always 0 when it's read back. + * |[1] |STOP |TDES/DES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop TDES/DES engine. + * | | |Note: The bit is always 0 when it's read back. + * |[2] |TMODE |TDES/DES Engine Operating Mode + * | | |0 = Set DES mode for TDES/DES engine. + * | | |1 = Set Triple DES mode for TDES/DES engine. + * |[3] |3KEYS |TDES/DES Key Number + * | | |0 = Select KEY1 and KEY2 in TDES/DES engine. + * | | |1 = Triple keys in TDES/DES engine Enabled. + * |[5] |DMALAST |TDES/DES Engine Start for the Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set as feeding in last block of data. + * |[6] |DMACSCAD |TDES/DES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |TDES/DES Engine DMA Enable Control + * | | |0 = TDES_DMA engine Disabled. + * | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN. + * | | |1 = TDES_DMA engine Enabled. + * | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[10:8] |OPMODE |TDES/DES Engine Operation Mode + * | | |0x00 = ECB (Electronic Codebook Mode). + * | | |0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |Others = CTR (Counter Mode). + * |[16] |ENCRPT |TDES/DES Encryption/Decryption + * | | |0 = TDES engine executes decryption operation. + * | | |1 = TDES engine executes encryption operation. + * |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap + * | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}. + * | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}. + * |[22] |OUTSWAP |TDES/DES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |TDES/DES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[25:24] |CHANNEL |TDES/DES Engine Working Channel + * | | |00 = Current control register setting is for channel 0. + * | | |01 = Current control register setting is for channel 1. + * | | |10 = Current control register setting is for channel 2. + * | | |11 = Current control register setting is for channel 3. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = This bit is to protect the content of TDES key from reading + * | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |The key content would be cleared as well. + * @var CRPT_T::TDES_STS + * Offset: 0x204 TDES/DES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |TDES/DES Engine Busy + * | | |0 = TDES/DES engine is idle or finished. + * | | |1 = TDES/DES engine is under processing. + * |[8] |INBUFEMPTY|TDES/DES in Buffer Empty + * | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process. + * | | |1 = TDES/DES input buffer is empty + * | | |Software needs to feed data to the TDES/DES engine + * | | |Otherwise, the TDES/DES engine will be pending to wait for input data. + * |[9] |INBUFFULL |TDES/DES in Buffer Full Flag + * | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine. + * | | |1 = TDES input buffer is full + * | | |Software cannot feed data to the TDES/DES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |TDES/DES in Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during feeding data to the TDES/DES engine. + * |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag + * | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT + * | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty. + * |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag + * | | |0 = TDES/DES output buffer is not full. + * | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT + * | | |Otherwise, the TDES/DES engine will be pending since output buffer is full. + * |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during getting test result from TDES/DES engine. + * |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and TDES/DES engine. + * @var CRPT_T::TDES0_KEY1H + * Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY1L + * Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY2H + * Offset: 0x210 TDES Key 2 High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY2L + * Offset: 0x214 TDES Key 2 Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY3H + * Offset: 0x218 TDES Key 3 High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_KEY3L + * Offset: 0x21C TDES Key 3 Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES0_IVH + * Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES0_IVL + * Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES0_SA + * Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES0_DA + * Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES0_CNT + * Offset: 0x230 TDES/DES Byte Count Register for Channel 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::TDES_DATIN + * Offset: 0x234 TDES/DES Engine Input data Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |TDES/DES Engine Input Port + * | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS + * | | |Feed data as INBUFFULL is 0. + * @var CRPT_T::TDES_DATOUT + * Offset: 0x238 TDES/DES Engine Output data Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |TDES/DES Engine Output Port + * | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRPT_T::TDES1_KEY1H + * Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY1L + * Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY2H + * Offset: 0x250 TDES Key 2 High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY2L + * Offset: 0x254 TDES Key 2 Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY3H + * Offset: 0x258 TDES Key 3 High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_KEY3L + * Offset: 0x25C TDES Key 3 Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES1_IVH + * Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES1_IVL + * Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES1_SA + * Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES1_DA + * Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES1_CNT + * Offset: 0x270 TDES/DES Byte Count Register for Channel 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::TDES2_KEY1H + * Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY1L + * Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY2H + * Offset: 0x290 TDES Key 2 High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY2L + * Offset: 0x294 TDES Key 2 Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY3H + * Offset: 0x298 TDES Key 3 High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_KEY3L + * Offset: 0x29C TDES Key 3 Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES2_IVH + * Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES2_IVL + * Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES2_SA + * Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES2_DA + * Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES2_CNT + * Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::TDES3_KEY1H + * Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY1L + * Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 1 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY2H + * Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY2L + * Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 2 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY3H + * Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 High Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_KEY3L + * Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |TDES/DES Key 3 Low Word + * | | |The key registers for TDES/DES algorithm calculation + * | | |The security key for the TDES/DES accelerator is 64 bits + * | | |Thus, it needs two 32-bit registers to store a security key + * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. + * @var CRPT_T::TDES3_IVH + * Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector High Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES3_IVL + * Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |TDES/DES Initial Vector Low Word + * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode + * | | |IV is Nonce counter for TDES/DES engine in CTR mode. + * @var CRPT_T::TDES3_SA + * Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |TDES/DES DMA Source Address + * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. + * | | |CRPT_TDESn_SA can be read and written + * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_SA will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. + * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES3_DA + * Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |TDES/DES DMA Destination Address + * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO + * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. + * | | |CRPT_TDESn_DA can be read and written + * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_DA will be updated later on + * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. + * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. + * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. + * @var CRPT_T::TDES3_CNT + * Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |TDES/DES Byte Count + * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode + * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_TDESn_CNT can be read and written + * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation + * | | |But the value of CRPT_TDESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. + * @var CRPT_T::HMAC_CTL + * Offset: 0x300 SHA/HMAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |SHA/HMAC Engine Start + * | | |0 = No effect. + * | | |1 = Start SHA/HMAC engine. BUSY flag will be set. + * | | |This bit is always 0 when it's read back. + * |[1] |STOP |SHA/HMAC Engine Stop + * | | |0 = No effect. + * | | |1 = Stop SHA/HMAC engine. + * | | |This bit is always 0 when it's read back. + * |[4] |HMACEN |HMAC_SHA Engine Operating Mode + * | | |0 = execute SHA function. + * | | |1 = execute HMAC function. + * |[5] |DMALAST |SHA/HMAC Last Block + * | | |This bit must be set as feeding in last byte of data. + * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Control + * | | |0 = SHA/HMAC DMA engine Disabled. + * | | |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN. + * | | |1 = SHA/HMAC DMA engine Enabled. + * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes + * | | |0x0xx: SHA160 + * | | |0x100: SHA256 + * | | |0x101: SHA224 + * | | |0x110: SHA512 + * | | |0x111: SHA384 + * | | |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1. + * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * @var CRPT_T::HMAC_STS + * Offset: 0x304 SHA/HMAC Status Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |SHA/HMAC Engine Busy + * | | |0 = SHA/HMAC engine is idle or finished. + * | | |1 = SHA/HMAC engine is busy. + * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag + * | | |0 = SHA/HMAC DMA engine is idle or finished. + * | | |1 = SHA/HMAC DMA engine is busy. + * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag + * | | |0 = Show the SHA/HMAC engine access normal. + * | | |1 = Show the SHA/HMAC engine access error. + * |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request + * | | |0 = No effect. + * | | |1 = Request SHA/HMAC Non-DMA mode data input. + * @var CRPT_T::HMAC_DGST[16] + * Offset: 0x308 ~ 0x344 SHA/HMAC Digest Message 0 ~ 15 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Digest Message Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_KEYCNT + * Offset: 0x348 SHA/HMAC Key Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count + * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates + * | | |The register is 32-bit and the maximum byte count is 4G bytes + * | | |It can be read and written. + * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRPT_SHA _KEYCNT will be updated later on + * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation. + * @var CRPT_T::HMAC_SADDR + * Offset: 0x34C SHA/HMAC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |SHA/HMAC DMA Source Address + * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO + * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored. + * | | |CRPT_HMAC_SADDR can be read and written + * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation. + * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START. + * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value. + * @var CRPT_T::HMAC_DMACNT + * Offset: 0x350 SHA/HMAC Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count + * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode + * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_HMAC_DMACNT can be read and written + * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_DMACNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation. + * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data. + * @var CRPT_T::HMAC_DATIN + * Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |SHA/HMAC Engine Input Port + * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS + * | | |Feed data as DATINREQ is 1. + * @var CRPT_T::ECC_CTL + * Offset: 0x800 ECC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |ECC Accelerator Start + * | | |0 = No effect. + * | | |1 = Start ECC accelerator. BUSY flag will be set. + * | | |This bit is always 0 when it's read back. + * | | |ECC accelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |ECC Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort ECC accelerator and make it into idle state. + * | | |This bit is always 0 when it's read back. + * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator. + * |[7] |DMAEN |ECC Accelerator DMA Enable Control + * | | |0 = ECC DMA engine Disabled. + * | | |1 = ECC DMA engine Enabled. + * | | |Only when START and DMAEN are 1, ECC DMA engine will be active + * |[8] |FSEL |Field Selection + * | | |0 = Binary Field (GF(2^m)). + * | | |1 = Prime Field (GF(p)). + * |[10:9] |ECCOP |Point Operation for BF and PF + * | | |00 = Point multiplication :. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]). + * | | |10 = Point addition :. + * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +. + * | | |(POINTX2, POINTY2) + * | | |11 = Point doubling :. + * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1). + * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11 + * |[12:11] |MODOP |Modulus Operation for PF + * | | |00 = Division :. + * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN. + * | | |01 = Multiplication :. + * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN. + * | | |10 = Addition :. + * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN. + * | | |11 = Subtraction :. + * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN. + * | | |MODOP is active only when ECCOP = 01. + * |[16] |LDP1 |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1) + * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user. + * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user. + * |[17] |LDP2 |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2) + * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user. + * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user. + * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve + * | | |0 = The register for CURVEA is not modified by DMA or user. + * | | |1 = The register for CURVEA is modified by DMA or user. + * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve + * | | |0 = The register for CURVEB is not modified by DMA or user. + * | | |1 = The register for CURVEB is modified by DMA or user. + * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve + * | | |0 = The register for CURVEN is not modified by DMA or user. + * | | |1 = The register for CURVEN is modified by DMA or user. + * |[21] |LDK |The Control Signal of Register for SCALARK + * | | |0 = The register for SCALARK is not modified by DMA or user. + * | | |1 = The register for SCALARK is modified by DMA or user. + * |[31:22] |CURVEM |The key length of elliptic curve. + * @var CRPT_T::ECC_STS + * Offset: 0x804 ECC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |ECC Accelerator Busy Flag + * | | |0 = The ECC accelerator is idle or finished. + * | | |1 = The ECC accelerator is under processing and protects all registers. + * | | |Remember to clear ECC interrupt flag after ECC accelerator finished + * |[1] |DMABUSY |ECC DMA Busy Flag + * | | |0 = ECC DMA is idle or finished. + * | | |1 = ECC DMA is busy. + * |[16] |BUSERR |ECC DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and ECC accelerator. + * @var CRPT_T::ECC_X1[18] + * Offset: 0x808 ~ 0x84C ECC The X-coordinate word 0 ~ 17 of the first point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the x-coordinate Value of the First Point (POINTX1) + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_Y1[18] + * Offset: 0x850 ~ 0x894 ECC The Y-coordinate word 0 ~ 17 of the first point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point (POINTY1) + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_X2[18] + * Offset: 0x898 ~ 0x8DC ECC The X-coordinate word 0 ~ 17 of the second point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the x-coordinate Value of the Second Point (POINTX2) + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_Y2[18] + * Offset: 0x8E0 ~ 0x924 ECC The Y-coordinate word 0 ~ 17 of the second point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point (POINTY2) + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_A[18] + * Offset: 0x928 ~ 0x96C ECC The parameter CURVEA word 0 ~ 17 of elliptic curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA) + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_B[18] + * Offset: 0x970 ~ 0x9B4 ECC The parameter CURVEB word 0 ~ 17 of elliptic curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA) + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_N[18] + * Offset: 0x9B8 ~ 0x9FC ECC The parameter CURVEN word 0 ~ 17 of elliptic curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN) + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2^m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_K[18] + * Offset: 0xA00 ~ 0xA44 ECC The scalar SCALARK word0 of point multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK) + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_SADDR + * Offset: 0xA48 ECC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |ECC DMA Source Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between + * | | |SRAM memory space and ECC accelerator. The SADDR keeps the source address of the data + * | | |buffer where the source text is stored. Based on the source address, the ECC accelerator + * | | |can read the DATA and PARAMETER from SRAM memory space and do ECC operation. The start + * | | |of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are + * | | |ignored. SADDR can be read and written. In DMA mode, software must update the CRPT_ECC_SADDR + * | | |before triggering START. + * @var CRPT_T::ECC_DADDR + * Offset: 0xA4C ECC DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |ECC DMA Destination Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator + * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored + * | | |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished + * | | |The start of destination address should be located at word boundary + * | | |That is, bit 1 and 0 of DADDR are ignored + * | | |DADDR can be read and written + * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START + * @var CRPT_T::ECC_STARTREG + * Offset: 0xA50 ECC Starting Address of Updated Registers + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |STARTREG |ECC Starting Address of Updated Registers + * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine + * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG + * | | |For example, we want to updated input data from register CRPT_ECC POINTX1 + * | | |Thus, the value of STARTREG is 0x808. + * @var CRPT_T::ECC_WORDCNT + * Offset: 0xA54 ECC DMA Word Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WORDCNT |ECC DMA Word Count + * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode + * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words + * | | |CRPT_ECC_WORDCNT can be read and written + */ + __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ + __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ + __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ + __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[8]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */ + __I uint32_t TDES_FDBCKH; /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */ + __I uint32_t TDES_FDBCKL; /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[38]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ + __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ + __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ + __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ + __IO uint32_t AES0_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */ + __IO uint32_t AES0_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */ + __IO uint32_t AES0_SADDR; /*!< [0x0140] AES DMA Source Address Register for Channel 0 */ + __IO uint32_t AES0_DADDR; /*!< [0x0144] AES DMA Destination Address Register for Channel 0 */ + __IO uint32_t AES0_CNT; /*!< [0x0148] AES Byte Count Register for Channel 0 */ + __IO uint32_t AES1_KEY[8]; /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1 */ + __IO uint32_t AES1_IV[4]; /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1 */ + __IO uint32_t AES1_SADDR; /*!< [0x017c] AES DMA Source Address Register for Channel 1 */ + __IO uint32_t AES1_DADDR; /*!< [0x0180] AES DMA Destination Address Register for Channel 1 */ + __IO uint32_t AES1_CNT; /*!< [0x0184] AES Byte Count Register for Channel 1 */ + __IO uint32_t AES2_KEY[8]; /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2 */ + __IO uint32_t AES2_IV[4]; /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2 */ + __IO uint32_t AES2_SADDR; /*!< [0x01b8] AES DMA Source Address Register for Channel 2 */ + __IO uint32_t AES2_DADDR; /*!< [0x01bc] AES DMA Destination Address Register for Channel 2 */ + __IO uint32_t AES2_CNT; /*!< [0x01c0] AES Byte Count Register for Channel 2 */ + __IO uint32_t AES3_KEY[8]; /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3 */ + __IO uint32_t AES3_IV[4]; /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3 */ + __IO uint32_t AES3_SADDR; /*!< [0x01f4] AES DMA Source Address Register for Channel 3 */ + __IO uint32_t AES3_DADDR; /*!< [0x01f8] AES DMA Destination Address Register for Channel 3 */ + __IO uint32_t AES3_CNT; /*!< [0x01fc] AES Byte Count Register for Channel 3 */ + __IO uint32_t TDES_CTL; /*!< [0x0200] TDES/DES Control Register */ + __I uint32_t TDES_STS; /*!< [0x0204] TDES/DES Engine Flag */ + __IO uint32_t TDES0_KEY1H; /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY1L; /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY2H; /*!< [0x0210] TDES Key 2 High Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY2L; /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY3H; /*!< [0x0218] TDES Key 3 High Word Register for Channel 0 */ + __IO uint32_t TDES0_KEY3L; /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0 */ + __IO uint32_t TDES0_IVH; /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0 */ + __IO uint32_t TDES0_IVL; /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0 */ + __IO uint32_t TDES0_SA; /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0 */ + __IO uint32_t TDES0_DA; /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0 */ + __IO uint32_t TDES0_CNT; /*!< [0x0230] TDES/DES Byte Count Register for Channel 0 */ + __IO uint32_t TDES_DATIN; /*!< [0x0234] TDES/DES Engine Input data Word Register */ + __I uint32_t TDES_DATOUT; /*!< [0x0238] TDES/DES Engine Output data Word Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TDES1_KEY1H; /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY1L; /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY2H; /*!< [0x0250] TDES Key 2 High Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY2L; /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY3H; /*!< [0x0258] TDES Key 3 High Word Register for Channel 1 */ + __IO uint32_t TDES1_KEY3L; /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1 */ + __IO uint32_t TDES1_IVH; /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1 */ + __IO uint32_t TDES1_IVL; /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1 */ + __IO uint32_t TDES1_SA; /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1 */ + __IO uint32_t TDES1_DA; /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1 */ + __IO uint32_t TDES1_CNT; /*!< [0x0270] TDES/DES Byte Count Register for Channel 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TDES2_KEY1H; /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY1L; /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY2H; /*!< [0x0290] TDES Key 2 High Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY2L; /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY3H; /*!< [0x0298] TDES Key 3 High Word Register for Channel 2 */ + __IO uint32_t TDES2_KEY3L; /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2 */ + __IO uint32_t TDES2_IVH; /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2 */ + __IO uint32_t TDES2_IVL; /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2 */ + __IO uint32_t TDES2_SA; /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2 */ + __IO uint32_t TDES2_DA; /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2 */ + __IO uint32_t TDES2_CNT; /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TDES3_KEY1H; /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY1L; /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY2H; /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY2L; /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY3H; /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3 */ + __IO uint32_t TDES3_KEY3L; /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3 */ + __IO uint32_t TDES3_IVH; /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3 */ + __IO uint32_t TDES3_IVL; /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3 */ + __IO uint32_t TDES3_SA; /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3 */ + __IO uint32_t TDES3_DA; /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3 */ + __IO uint32_t TDES3_CNT; /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */ + __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */ + __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */ + __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */ + __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */ + __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */ + __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[298]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */ + __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */ + __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point */ + __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */ + __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */ + __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */ + __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */ + __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */ + __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */ + __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */ + __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */ + __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */ + __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */ + __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */ + +} CRPT_T; + +/** + @addtogroup CRPT_CONST CRPT Bit Field Definition + Constant Definitions for CRPT Controller +@{ */ + +#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ +#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ + +#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ +#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ + +#define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT_T::INTEN: TDESIEN Position */ +#define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT_T::INTEN: TDESIEN Mask */ + +#define CRPT_INTEN_TDESEIEN_Pos (9) /*!< CRPT_T::INTEN: TDESEIEN Position */ +#define CRPT_INTEN_TDESEIEN_Msk (0x1ul << CRPT_INTEN_TDESEIEN_Pos) /*!< CRPT_T::INTEN: TDESEIEN Mask */ + +#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ +#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ + +#define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */ +#define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */ + +#define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */ +#define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */ + +#define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */ +#define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */ + +#define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */ +#define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */ + +#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ +#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ + +#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ +#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ + +#define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT_T::INTSTS: TDESIF Position */ +#define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT_T::INTSTS: TDESIF Mask */ + +#define CRPT_INTSTS_TDESEIF_Pos (9) /*!< CRPT_T::INTSTS: TDESEIF Position */ +#define CRPT_INTSTS_TDESEIF_Msk (0x1ul << CRPT_INTSTS_TDESEIF_Pos) /*!< CRPT_T::INTSTS: TDESEIF Mask */ + +#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ +#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ + +#define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */ +#define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */ + +#define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */ +#define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */ + +#define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */ +#define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */ + +#define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */ +#define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */ + +#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ +#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ + +#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ +#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ + +#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ +#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */ + +#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ +#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ + +#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ +#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ + +#define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */ +#define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY[8]: KEY Mask */ + +#define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */ +#define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */ + +#define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKH: FDBCK Position */ +#define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask */ + +#define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKL: FDBCK Position */ +#define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask */ + +#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ +#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ + +#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ +#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ + +#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ +#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ + +#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ +#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ + +#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ +#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ + +#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ +#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ + +#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ +#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ + +#define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */ +#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */ + +#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ +#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ + +#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ +#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ + +#define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::AES_CTL: CHANNEL Position */ +#define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT_T::AES_CTL: CHANNEL Mask */ + +#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ +#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ + +#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ +#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ + +#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ +#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ + +#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ +#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ + +#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ +#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ + +#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ +#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ + +#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ +#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ + +#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position */ +#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ + +#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ +#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ + +#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ +#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ + +#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ +#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ + +#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ +#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ + +#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ +#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ + +#define CRPT_AES0_KEYx_KEY_Pos (0) /*!< CRPT_T::AES0_KEY[8]: KEY Position */ +#define CRPT_AES0_KEYx_KEY_Msk (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos) /*!< CRPT_T::AES0_KEY[8]: KEY Mask */ + +#define CRPT_AES0_IVx_IV_Pos (0) /*!< CRPT_T::AES0_IV[4]: IV Position */ +#define CRPT_AES0_IVx_IV_Msk (0xfffffffful << CRPT_AES0_IVx_IV_Pos) /*!< CRPT_T::AES0_IV[4]: IV Mask */ + +#define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES0_SADDR: SADDR Position */ +#define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT_T::AES0_SADDR: SADDR Mask */ + +#define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES0_DADDR: DADDR Position */ +#define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT_T::AES0_DADDR: DADDR Mask */ + +#define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT_T::AES0_CNT: CNT Position */ +#define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT_T::AES0_CNT: CNT Mask */ + +#define CRPT_AES1_KEYx_KEY_Pos (0) /*!< CRPT_T::AES1_KEY[8]: KEY Position */ +#define CRPT_AES1_KEYx_KEY_Msk (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos) /*!< CRPT_T::AES1_KEY[8]: KEY Mask */ + +#define CRPT_AES1_IVx_IV_Pos (0) /*!< CRPT_T::AES1_IV[4]: IV Position */ +#define CRPT_AES1_IVx_IV_Msk (0xfffffffful << CRPT_AES1_IVx_IV_Pos) /*!< CRPT_T::AES1_IV[4]: IV Mask */ + +#define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES1_SADDR: SADDR Position */ +#define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT_T::AES1_SADDR: SADDR Mask */ + +#define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES1_DADDR: DADDR Position */ +#define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT_T::AES1_DADDR: DADDR Mask */ + +#define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT_T::AES1_CNT: CNT Position */ +#define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT_T::AES1_CNT: CNT Mask */ + +#define CRPT_AES2_KEYx_KEY_Pos (0) /*!< CRPT_T::AES2_KEY[8]: KEY Position */ +#define CRPT_AES2_KEYx_KEY_Msk (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos) /*!< CRPT_T::AES2_KEY[8]: KEY Mask */ + +#define CRPT_AES2_IVx_IV_Pos (0) /*!< CRPT_T::AES2_IV[4]: IV Position */ +#define CRPT_AES2_IVx_IV_Msk (0xfffffffful << CRPT_AES2_IVx_IV_Pos) /*!< CRPT_T::AES2_IV[4]: IV Mask */ + +#define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES2_SADDR: SADDR Position */ +#define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT_T::AES2_SADDR: SADDR Mask */ + +#define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES2_DADDR: DADDR Position */ +#define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT_T::AES2_DADDR: DADDR Mask */ + +#define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT_T::AES2_CNT: CNT Position */ +#define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT_T::AES2_CNT: CNT Mask */ + +#define CRPT_AES3_KEYx_KEY_Pos (0) /*!< CRPT_T::AES3_KEY[8]: KEY Position */ +#define CRPT_AES3_KEYx_KEY_Msk (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos) /*!< CRPT_T::AES3_KEY[8]: KEY Mask */ + +#define CRPT_AES3_IVx_IV_Pos (0) /*!< CRPT_T::AES3_IV[4]: IV Position */ +#define CRPT_AES3_IVx_IV_Msk (0xfffffffful << CRPT_AES3_IVx_IV_Pos) /*!< CRPT_T::AES3_IV[4]: IV Mask */ + +#define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES3_SADDR: SADDR Position */ +#define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT_T::AES3_SADDR: SADDR Mask */ + +#define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES3_DADDR: DADDR Position */ +#define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT_T::AES3_DADDR: DADDR Mask */ + +#define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT_T::AES3_CNT: CNT Position */ +#define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT_T::AES3_CNT: CNT Mask */ + +#define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT_T::TDES_CTL: START Position */ +#define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT_T::TDES_CTL: START Mask */ + +#define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT_T::TDES_CTL: STOP Position */ +#define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT_T::TDES_CTL: STOP Mask */ + +#define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT_T::TDES_CTL: TMODE Position */ +#define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT_T::TDES_CTL: TMODE Mask */ + +#define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT_T::TDES_CTL: 3KEYS Position */ +#define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT_T::TDES_CTL: 3KEYS Mask */ + +#define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT_T::TDES_CTL: DMALAST Position */ +#define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT_T::TDES_CTL: DMALAST Mask */ + +#define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::TDES_CTL: DMACSCAD Position */ +#define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT_T::TDES_CTL: DMACSCAD Mask */ + +#define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT_T::TDES_CTL: DMAEN Position */ +#define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT_T::TDES_CTL: DMAEN Mask */ + +#define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT_T::TDES_CTL: OPMODE Position */ +#define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT_T::TDES_CTL: OPMODE Mask */ + +#define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::TDES_CTL: ENCRPT Position */ +#define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT_T::TDES_CTL: ENCRPT Mask */ + +#define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT_T::TDES_CTL: BLKSWAP Position */ +#define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT_T::TDES_CTL: BLKSWAP Mask */ + +#define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::TDES_CTL: OUTSWAP Position */ +#define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT_T::TDES_CTL: OUTSWAP Mask */ + +#define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT_T::TDES_CTL: INSWAP Position */ +#define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT_T::TDES_CTL: INSWAP Mask */ + +#define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::TDES_CTL: CHANNEL Position */ +#define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT_T::TDES_CTL: CHANNEL Mask */ + +#define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::TDES_CTL: KEYUNPRT Position */ +#define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask */ + +#define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::TDES_CTL: KEYPRT Position */ +#define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYPRT Mask */ + +#define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT_T::TDES_STS: BUSY Position */ +#define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT_T::TDES_STS: BUSY Mask */ + +#define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::TDES_STS: INBUFEMPTY Position */ +#define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask */ + +#define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::TDES_STS: INBUFFULL Position */ +#define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT_T::TDES_STS: INBUFFULL Mask */ + +#define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT_T::TDES_STS: INBUFERR Position */ +#define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT_T::TDES_STS: INBUFERR Mask */ + +#define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */ +#define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask */ + +#define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::TDES_STS: OUTBUFFULL Position */ +#define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask */ + +#define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::TDES_STS: OUTBUFERR Position */ +#define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT_T::TDES_STS: OUTBUFERR Mask */ + +#define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT_T::TDES_STS: BUSERR Position */ +#define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT_T::TDES_STS: BUSERR Mask */ + +#define CRPT_TDES0_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxH: KEY Position */ +#define CRPT_TDES0_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos) /*!< CRPT_T::TDES0_KEYxH: KEY Mask */ + +#define CRPT_TDES0_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxL: KEY Position */ +#define CRPT_TDES0_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos) /*!< CRPT_T::TDES0_KEYxL: KEY Mask */ + +#define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT_T::TDES0_IVH: IV Position */ +#define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT_T::TDES0_IVH: IV Mask */ + +#define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT_T::TDES0_IVL: IV Position */ +#define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT_T::TDES0_IVL: IV Mask */ + +#define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES0_SADDR: SADDR Position */ +#define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT_T::TDES0_SADDR: SADDR Mask */ + +#define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES0_DADDR: DADDR Position */ +#define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT_T::TDES0_DADDR: DADDR Mask */ + +#define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT_T::TDES0_CNT: CNT Position */ +#define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT_T::TDES0_CNT: CNT Mask */ + +#define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT_T::TDES_DATIN: DATIN Position */ +#define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT_T::TDES_DATIN: DATIN Mask */ + +#define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::TDES_DATOUT: DATOUT Position */ +#define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT_T::TDES_DATOUT: DATOUT Mask */ + +#define CRPT_TDES1_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxH: KEY Position */ +#define CRPT_TDES1_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos) /*!< CRPT_T::TDES1_KEYxH: KEY Mask */ + +#define CRPT_TDES1_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxL: KEY Position */ +#define CRPT_TDES1_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT_T::TDES1_KEYxL: KEY Mask */ + +#define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT_T::TDES1_IVH: IV Position */ +#define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT_T::TDES1_IVH: IV Mask */ + +#define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT_T::TDES1_IVL: IV Position */ +#define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT_T::TDES1_IVL: IV Mask */ + +#define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES1_SADDR: SADDR Position */ +#define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT_T::TDES1_SADDR: SADDR Mask */ + +#define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES1_DADDR: DADDR Position */ +#define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT_T::TDES1_DADDR: DADDR Mask */ + +#define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT_T::TDES1_CNT: CNT Position */ +#define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT_T::TDES1_CNT: CNT Mask */ + +#define CRPT_TDES2_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxH: KEY Position */ +#define CRPT_TDES2_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos) /*!< CRPT_T::TDES2_KEYxH: KEY Mask */ + +#define CRPT_TDES2_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxL: KEY Position */ +#define CRPT_TDES2_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos) /*!< CRPT_T::TDES2_KEYxL: KEY Mask */ + +#define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT_T::TDES2_IVH: IV Position */ +#define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT_T::TDES2_IVH: IV Mask */ + +#define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT_T::TDES2_IVL: IV Position */ +#define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT_T::TDES2_IVL: IV Mask */ + +#define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES2_SADDR: SADDR Position */ +#define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT_T::TDES2_SADDR: SADDR Mask */ + +#define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES2_DADDR: DADDR Position */ +#define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT_T::TDES2_DADDR: DADDR Mask */ + +#define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT_T::TDES2_CNT: CNT Position */ +#define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT_T::TDES2_CNT: CNT Mask */ + +#define CRPT_TDES3_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxH: KEY Position */ +#define CRPT_TDES3_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos) /*!< CRPT_T::TDES3_KEYxH: KEY Mask */ + +#define CRPT_TDES3_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxL: KEY Position */ +#define CRPT_TDES3_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos) /*!< CRPT_T::TDES3_KEYxL: KEY Mask */ + +#define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT_T::TDES3_IVH: IV Position */ +#define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT_T::TDES3_IVH: IV Mask */ + +#define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT_T::TDES3_IVL: IV Position */ +#define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT_T::TDES3_IVL: IV Mask */ + +#define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES3_SADDR: SADDR Position */ +#define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT_T::TDES3_SADDR: SADDR Mask */ + +#define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES3_DADDR: DADDR Position */ +#define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT_T::TDES3_DADDR: DADDR Mask */ + +#define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT_T::TDES3_CNT: CNT Position */ +#define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT_T::TDES3_CNT: CNT Mask */ + +#define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */ +#define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */ + +#define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */ +#define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */ + +#define CRPT_HMAC_CTL_HMACEN_Pos (4) /*!< CRPT_T::HMAC_CTL: HMACEN Position */ +#define CRPT_HMAC_CTL_HMACEN_Msk (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos) /*!< CRPT_T::HMAC_CTL: HMACEN Mask */ + +#define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */ +#define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */ + +#define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */ +#define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */ + +#define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */ +#define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */ + +#define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */ +#define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */ + +#define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */ +#define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */ + +#define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */ +#define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */ + +#define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */ +#define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */ + +#define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */ +#define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */ + +#define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */ +#define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */ + +#define CRPT_HMAC_DGSTx_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST[16]: DGST Position */ +#define CRPT_HMAC_DGSTx_DGST_Msk (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos) /*!< CRPT_T::HMAC_DGST[16]: DGST Mask */ + +#define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */ +#define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */ + +#define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */ +#define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */ + +#define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */ +#define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */ + +#define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */ +#define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */ + +#define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */ +#define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */ + +#define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */ +#define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */ + +#define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */ +#define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */ + +#define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */ +#define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */ + +#define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */ +#define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */ + +#define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */ +#define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */ + +#define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */ +#define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */ + +#define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */ +#define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */ + +#define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */ +#define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */ + +#define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */ +#define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */ + +#define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */ +#define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */ + +#define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */ +#define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */ + +#define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */ +#define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */ + +#define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */ +#define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */ + +#define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */ +#define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */ + +#define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */ +#define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */ + +#define CRPT_ECC_X1_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1[18]: POINTX1 Position */ +#define CRPT_ECC_X1_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos) /*!< CRPT_T::ECC_X1[18]: POINTX1 Mask */ + +#define CRPT_ECC_Y1_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Position */ +#define CRPT_ECC_Y1_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Mask */ + +#define CRPT_ECC_X2_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2[18]: POINTX2 Position */ +#define CRPT_ECC_X2_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos) /*!< CRPT_T::ECC_X2[18]: POINTX2 Mask */ + +#define CRPT_ECC_Y2_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Position */ +#define CRPT_ECC_Y2_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Mask */ + +#define CRPT_ECC_A_CURVEA_Pos (0) /*!< CRPT_T::ECC_A[18]: CURVEA Position */ +#define CRPT_ECC_A_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_CURVEA_Pos) /*!< CRPT_T::ECC_A[18]: CURVEA Mask */ + +#define CRPT_ECC_B_CURVEB_Pos (0) /*!< CRPT_T::ECC_B[18]: CURVEB Position */ +#define CRPT_ECC_B_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_CURVEB_Pos) /*!< CRPT_T::ECC_B[18]: CURVEB Mask */ + +#define CRPT_ECC_N_CURVEN_Pos (0) /*!< CRPT_T::ECC_N[18]: CURVEN Position */ +#define CRPT_ECC_N_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_CURVEN_Pos) /*!< CRPT_T::ECC_N[18]: CURVEN Mask */ + +#define CRPT_ECC_K_SCALARK_Pos (0) /*!< CRPT_T::ECC_K[18]: SCALARK Position */ +#define CRPT_ECC_K_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_SCALARK_Pos) /*!< CRPT_T::ECC_K[18]: SCALARK Mask */ + +#define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */ +#define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */ + +#define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/ +#define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */ + +#define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position */ +#define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */ + +/**@}*/ /* CRPT_CONST CRYPTO */ +/**@}*/ /* end of CRYPTO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CRYPTO_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/dac_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/dac_reg.h new file mode 100644 index 00000000000..bd151e320d0 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/dac_reg.h @@ -0,0 +1,209 @@ +/**************************************************************************//** + * @file dac_reg.h + * @version V1.00 + * @brief DAC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __DAC_REG_H__ +#define __DAC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup DAC Digital to Analog Converter(DAC) + Memory Mapped Structure for DAC Controller +@{ */ + +typedef struct +{ + + + /** + * @var DAC_T::CTL + * Offset: 0x00 DAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DACEN |DAC Enable Bit + * | | |0 = DAC is Disabled. + * | | |1 = DAC is Enabled. + * |[1] |DACIEN |DAC Interrupt Enable Bit + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[2] |DMAEN |DMA Mode Enable Bit + * | | |0 = DMA mode Disabled. + * | | |1 = DMA mode Enabled. + * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit + * | | |0 = DMA under-run interrupt Disabled. + * | | |1 = DMA under-run interrupt Enabled. + * |[4] |TRGEN |Trigger Mode Enable Bit + * | | |0 = DAC event trigger mode Disabled. + * | | |1 = DAC event trigger mode Enabled. + * |[7:5] |TRGSEL |Trigger Source Selection + * | | |000 = Software trigger. + * | | |001 = External pin DAC0_ST trigger. + * | | |010 = Timer 0 trigger. + * | | |011 = Timer 1 trigger. + * | | |100 = Timer 2 trigger. + * | | |101 = Timer 3 trigger. + * | | |110 = EPWM0 trigger. + * | | |111 = EPWM1 trigger. + * |[8] |BYPASS |Bypass Buffer Mode + * | | |0 = Output voltage buffer Enabled. + * | | |1 = Output voltage buffer Disabled. + * |[10] |LALIGN |DAC Data Left-aligned Enabled Control + * | | |0 = Right alignment. + * | | |1 = Left alignment. + * |[13:12] |ETRGSEL |External Pin Trigger Selection + * | | |00 = Low level trigger. + * | | |01 = High level trigger. + * | | |10 = Falling edge trigger. + * | | |11 = Rising edge trigger. + * |[15:14] |BWSEL |DAC Data Bit-width Selection + * | | |00 = data is 12 bits. + * | | |01 = data is 8 bits. + * | | |Others = reserved. + * |[16] |GRPEN |DAC Group Mode Enable Bit + * | | |0 = DAC0 and DAC1 are not grouped. + * | | |1 = DAC0 and DAC1 are grouped. + * @var DAC_T::SWTRG + * Offset: 0x04 DAC Software Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWTRG |Software Trigger + * | | |0 = Software trigger Disabled. + * | | |1 = Software trigger Enabled. + * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0. + * @var DAC_T::DAT + * Offset: 0x08 DAC Data Holding Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DACDAT |DAC 12-bit Holding Data + * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output + * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. + * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + * @var DAC_T::DATOUT + * Offset: 0x0C DAC Data Output Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DATOUT |DAC 12-bit Output Data + * | | |These bits are current digital data for DAC output conversion. + * | | |It is loaded from DAC_DAT register and user cannot write it directly. + * @var DAC_T::STATUS + * Offset: 0x10 DAC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FINISH |DAC Conversion Complete Finish Flag + * | | |0 = DAC is in conversion state. + * | | |1 = DAC conversion finish. + * | | |This bit set to 1 when conversion time counter counts to SETTLET + * | | |It is cleared to 0 when DAC starts a new conversion + * | | |User writes 1 to clear this bit to 0. + * |[1] |DMAUDR |DMA Under-run Interrupt Flag + * | | |0 = No DMA under-run error condition occurred. + * | | |1 = DMA under-run error condition occurred. + * | | |User writes 1 to clear this bit. + * |[8] |BUSY |DAC Busy Flag (Read Only) + * | | |0 = DAC is ready for next conversion. + * | | |1 = DAC is busy in conversion. + * | | |This is read only bit. + * @var DAC_T::TCTL + * Offset: 0x14 DAC Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |SETTLET |DAC Output Settling Time + * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. + * | | |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50. + * | | |SELTTLET = DAC controller clock speed x settling time. + */ + __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */ + __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */ + __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */ + __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */ + __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */ + __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */ + +} DAC_T; + +/** + @addtogroup DAC_CONST DAC Bit Field Definition + Constant Definitions for DAC Controller +@{ */ + +#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */ +#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */ + +#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */ +#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */ + +#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */ +#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */ + +#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */ +#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */ + +#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */ +#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */ + +#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */ +#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */ + +#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */ +#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */ + +#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */ +#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */ + +#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */ +#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */ + +#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */ +#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */ + +#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */ +#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */ + +#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */ +#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */ + +#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */ +#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */ + +#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */ +#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */ + +#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */ +#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */ + +#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */ +#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */ + +#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */ +#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */ + +#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */ +#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */ + +/**@}*/ /* DAC_CONST */ +/**@}*/ /* end of DAC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __DAC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/eadc_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/eadc_reg.h new file mode 100644 index 00000000000..7cabdad9b20 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/eadc_reg.h @@ -0,0 +1,1710 @@ +/**************************************************************************//** + * @file eadc_reg.h + * @version V1.00 + * @brief EADC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EADC_REG_H__ +#define __EADC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EADC Enhanced Analog to Digital Converter(EADC) + Memory Mapped Structure for EADC Controller +@{ */ + +typedef struct +{ + + + /** + * @var EADC_T::DAT[19] + * Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::CURDAT + * Offset: 0x4C ADC PDMA Current Transfer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register + * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. + * | | |This is a read only register. + * @var EADC_T::CTL + * Offset: 0x50 ADC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCEN |ADC Converter Enable Bit + * | | |0 = Disabled EADC. + * | | |1 = Enabled EADC. + * | | |Note: Before starting ADC conversion function, this bit should be set to 1 + * | | |Clear it to 0 to disable ADC converter analog circuit power consumption. + * |[1] |ADCRST |ADC Converter Control Circuits Reset + * | | |0 = No effect. + * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. + * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. + * |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. + * | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled. + * |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. + * | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled. + * |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. + * | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled. + * |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. + * | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled. + * |[7:6] |RESSEL |Resolution Selection + * | | |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]). + * | | |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]). + * | | |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]). + * | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]). + * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit + * | | |0 = Single-end analog input mode. + * | | |1 = Differential analog input mode. + * |[9] |DMOF |ADC Differential Input Mode Output Format + * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format. + * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format. + * |[11] |PDMAEN |PDMA Transfer Enable Bit + * | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. + * | | |0 = PDMA data transfer Disabled. + * | | |1 = PDMA data transfer Enabled. + * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * @var EADC_T::SWTRG + * Offset: 0x54 ADC Sample Module Software Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SWTRG |ADC Sample Module 0~18 Software Force to Start ADC Conversion + * | | |0 = No effect. + * | | |1 = Cause an ADC conversion when the priority is given to sample module. + * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion + * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * @var EADC_T::PENDSTS + * Offset: 0x58 ADC Start of Conversion Pending Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |STPF |ADC Sample Module 0~18 Start of Conversion Pending Flag + * | | |Read: + * | | |0 = There is no pending conversion for sample module. + * | | |1 = Sample module ADC start of conversion is pending. + * | | |Write: + * | | |1 = clear pending flag & cancel the conversion for sample module. + * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0 + * @var EADC_T::OVSTS + * Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SPOVF |ADC SAMPLE0~18 Overrun Flag + * | | |0 = No sample module event overrun. + * | | |1 = Indicates a new sample module event is generated while an old one event is pending. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EADC_T::SCTL[19] + * Offset: 0x80 ADC Sample Module 0~18 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0 (slow channel). + * | | |01H = EADC_CH1 (slow channel). + * | | |02H = EADC_CH2 (slow channel). + * | | |03H = EADC_CH3 (slow channel). + * | | |04H = EADC_CH4 (slow channel). + * | | |05H = EADC_CH5 (slow channel). + * | | |06H = EADC_CH6 (slow channel). + * | | |07H = EADC_CH7 (slow channel). + * | | |08H = EADC_CH8 (slow channel). + * | | |09H = EADC_CH9 (slow channel). + * | | |0AH = EADC_CH10 (fast channel). + * | | |0BH = EADC_CH11 (fast channel). + * | | |0CH = EADC_CH12 (fast channel). + * | | |0DH = EADC_CH13 (fast channel). + * | | |0EH = EADC_CH14 (fast channel). + * | | |0FH = EADC_CH15 (fast channel). + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting). + * |[20:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = EPWM0TG0. + * | | |9H = EPWM0TG1. + * | | |AH = EPWM0TG2. + * | | |BH = EPWM0TG3. + * | | |CH = EPWM0TG4. + * | | |DH = EPWM0TG5. + * | | |EH = EPWM1TG0. + * | | |FH = EPWM1TG1. + * | | |10H = EPWM1TG2. + * | | |11H = EPWM1TG3. + * | | |12H = EPWM1TG4. + * | | |13H = EPWM1TG5. + * | | |14H = BPWM0TG. + * | | |15H = BPWM1TG. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * |[23] |DBMEN |Double Buffer Mode Enable Bit + * | | |0 = Sample has one sample result register. (default). + * | | |1 = Sample has two sample result registers. + * |[31:24] |EXTSMPT |ADC Sampling Time Extend + * | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time. + * | | |The range of start delay time is from 0~255 ADC clock. + * @var EADC_T::INTSRC[4] + * Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit + * | | |0 = Sample Module 9 interrupt Disabled. + * | | |1 = Sample Module 9 interrupt Enabled. + * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit + * | | |0 = Sample Module 10 interrupt Disabled. + * | | |1 = Sample Module 10 interrupt Enabled. + * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit + * | | |0 = Sample Module 11 interrupt Disabled. + * | | |1 = Sample Module 11 interrupt Enabled. + * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit + * | | |0 = Sample Module 12 interrupt Disabled. + * | | |1 = Sample Module 12 interrupt Enabled. + * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit + * | | |0 = Sample Module 13 interrupt Disabled. + * | | |1 = Sample Module 13 interrupt Enabled. + * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit + * | | |0 = Sample Module 14 interrupt Disabled. + * | | |1 = Sample Module 14 interrupt Enabled. + * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit + * | | |0 = Sample Module 15 interrupt Disabled. + * | | |1 = Sample Module 15 interrupt Enabled. + * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit + * | | |0 = Sample Module 16 interrupt Disabled. + * | | |1 = Sample Module 16 interrupt Enabled. + * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit + * | | |0 = Sample Module 17 interrupt Disabled. + * | | |1 = Sample Module 17 interrupt Enabled. + * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit + * | | |0 = Sample Module 18 interrupt Disabled. + * | | |1 = Sample Module 18 interrupt Enabled. + * @var EADC_T::CMP[4] + * Offset: 0xE0 ADC Result Compare Register 0~3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |ADC Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. + * |[7:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. + * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. + * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. + * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. + * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. + * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. + * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. + * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. + * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. + * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::STATUS0 + * Offset: 0xF0 ADC Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). + * |[31:16] |OV |EADC_DAT0~15 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). + * @var EADC_T::STATUS1 + * Offset: 0xF4 ADC Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). + * |[18:16] |OV |EADC_DAT16~18 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). + * @var EADC_T::STATUS2 + * Offset: 0xF8 ADC Status Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADIF0 |ADC ADINT0 Interrupt Flag + * | | |0 = No ADINT0 interrupt pulse received. + * | | |1 = ADINT0 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[1] |ADIF1 |ADC ADINT1 Interrupt Flag + * | | |0 = No ADINT1 interrupt pulse received. + * | | |1 = ADINT1 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[2] |ADIF2 |ADC ADINT2 Interrupt Flag + * | | |0 = No ADINT2 interrupt pulse received. + * | | |1 = ADINT2 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[3] |ADIF3 |ADC ADINT3 Interrupt Flag + * | | |0 = No ADINT3 interrupt pulse received. + * | | |1 = ADINT3 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[4] |ADCMPF0 |ADC Compare 0 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |ADCMPF1 |ADC Compare 1 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |ADCMPF2 |ADC Compare 2 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[7] |ADCMPF3 |ADC Compare 3 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun + * | | |0 = ADINT0 interrupt flag is not overwritten to 1. + * | | |1 = ADINT0 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun + * | | |0 = ADINT1 interrupt flag is not overwritten to 1. + * | | |1 = ADINT1 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun + * | | |0 = ADINT2 interrupt flag is not overwritten to 1. + * | | |1 = ADINT2 interrupt flag is s overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun + * | | |0 = ADINT3 interrupt flag is not overwritten to 1. + * | | |1 = ADINT3 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only) + * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. + * |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only) + * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting. + * |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only) + * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting. + * |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only) + * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting. + * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) + * | | |This filed reflects ADC current conversion channel when BUSY=1. + * | | |It is read only. + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = EADC_CH8. + * | | |09H = EADC_CH9. + * | | |0AH = EADC_CH10. + * | | |0BH = EADC_CH11. + * | | |0CH = EADC_CH12. + * | | |0DH = EADC_CH13. + * | | |0EH = EADC_CH14. + * | | |0FH = EADC_CH15. + * | | |10H = VBG. + * | | |11H = VTEMP. + * | | |12H = VBAT/4. + * |[23] |BUSY |Busy/Idle (Read Only) + * | | |0 = EADC is in idle state. + * | | |1 = EADC is busy at conversion. + * |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only) + * | | |n=0~3. + * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. + * |[25] |STOVF |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. + * |[26] |AVALID |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. + * |[27] |AOV |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. + * @var EADC_T::STATUS3 + * Offset: 0xFC ADC Status Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CURSPL |ADC Current Sample Module + * | | |This register show the current ADC is controlled by which sample module control logic modules. + * | | |If the ADC is Idle, this bit filed will set to 0x1F. + * | | |This is a read only register. + * @var EADC_T::DDAT[4] + * Offset: 0x100 ADC Double Data Register 0 for Sample Module 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Results + * | | |This field contains 12 bits conversion results. + * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. + * |[16] |OV |Overrun Flag + * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. + * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. + * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 + * | | |It is cleared by hardware after EADC_DDAT register is read. + * |[17] |VALID |Valid Flag + * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. + * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read + * | | |(n=0~3). + * @var EADC_T::PWRM + * Offset: 0x110 ADC Power Management Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only) + * | | |0 = ADC is not ready for conversion may be in power down state or in the progress of start up. + * | | |1 = ADC is ready for conversion. + * |[1] |PWUCALEN |Power Up Calibration Function Enable Control + * | | |0 = Disable the function of calibration at power up. + * | | |1 = Enable the function of calibration at power up. + * | | |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following + * | | |{PWUCALEN, CALSEL } Description: + * | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate. + * | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate. + * | | |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up. + * | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up. + * |[3:2] |PWDMOD |ADC Power-down Mode + * | | |Set this bit fields to select ADC power down mode when system power-down. + * | | |00 = ADC Deep power down mode. + * | | |01 = ADC Power down. + * | | |10 = ADC Standby mode. + * | | |11 = ADC Deep power down mode. + * | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up + * |[19:8] |LDOSUT |ADC Internal LDO Start-up Time + * | | |Set this bit fields to control LDO start-up time + * | | |The minimum required LDO start-up time is 20us + * | | |LDO start-up time = (1/ADC_CLK) x LDOSUT. + * @var EADC_T::CALCTL + * Offset: 0x114 ADC Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |CALSTART |Calibration Functional Block Start + * | | |0 = Stops calibration functional block. + * | | |1 = Starts calibration functional block. + * | | |Note: This bit is set by SW and clear by HW after re-calibration finish + * |[2] |CALDONE |Calibration Functional Block Complete (Read Only) + * | | |0 = During a calibration. + * | | |1 = Calibration is completed. + * |[3] |CALSEL |Select Calibration Functional Block + * | | |0 = Load calibration word when calibration functional block is active. + * | | |1 = Execute calibration when calibration functional block is active. + * @var EADC_T::CALDWRD + * Offset: 0x118 ADC Calibration Load Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CALWORD |Calibration Word Bits + * | | |Write to this register with the previous calibration word before load calibration action. + * | | |Read this register after calibration done. + * | | |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. + */ + __I uint32_t DAT[19]; /*!< [0x0000] ADC Data Register 0~18 for Sample Module 0~18 */ + __I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */ + __IO uint32_t CTL; /*!< [0x0050] ADC Control Register */ + __O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */ + __IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */ + __IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SCTL[19]; /*!< [0x0080] ADC Sample Module 0~18 Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTSRC[4]; /*!< [0x00d0] ADC interrupt 0~3 Source Enable Control Register. */ + __IO uint32_t CMP[4]; /*!< [0x00e0] ADC Result Compare Register 0~3 */ + __I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */ + __I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */ + __IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */ + __I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */ + __I uint32_t DDAT[4]; /*!< [0x0100] ADC Double Data Register 0~3 for Sample Module 0~3 */ + __IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */ + __IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */ + __IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */ + +} EADC_T; + +/** + @addtogroup EADC_CONST EADC Bit Field Definition + Constant Definitions for EADC Controller +@{ */ + +#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ +#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ + +#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ +#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ + +#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ +#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ + +#define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ +#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ + +#define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ +#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ + +#define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ +#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ + +#define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ +#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ + +#define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ +#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ + +#define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ +#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ + +#define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ +#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ + +#define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ +#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ + +#define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ +#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ + +#define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ +#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ + +#define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ +#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ + +#define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ +#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ + +#define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ +#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ + +#define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ +#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ + +#define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ +#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ + +#define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ +#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ + +#define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ +#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ + +#define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ +#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ + +#define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ +#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ + +#define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ +#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ + +#define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ +#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ + +#define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ +#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ + +#define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ +#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ + +#define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ +#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ + +#define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ +#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ + +#define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ +#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ + +#define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ +#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ + +#define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */ +#define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */ + +#define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */ +#define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */ + +#define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */ +#define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */ + +#define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */ +#define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */ + +#define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */ +#define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */ + +#define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */ +#define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */ + +#define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */ +#define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */ + +#define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */ +#define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */ + +#define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */ +#define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */ + +#define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */ +#define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */ + +#define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */ +#define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */ + +#define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */ +#define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */ + +#define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */ +#define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */ + +#define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */ +#define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */ + +#define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */ +#define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */ + +#define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */ +#define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */ + +#define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */ +#define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */ + +#define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */ +#define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */ + +#define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */ +#define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */ + +#define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */ +#define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */ + +#define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */ +#define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */ + +#define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */ +#define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */ + +#define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */ +#define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */ + +#define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */ +#define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */ + +#define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */ +#define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */ + +#define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */ +#define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */ + +#define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */ +#define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */ + +#define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */ +#define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */ + +#define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */ +#define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */ + +#define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */ +#define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */ + +#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ +#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ + +#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ +#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ + +#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ +#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ + +#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ +#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ + +#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ +#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ + +#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ +#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ + +#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ +#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ + +#define EADC_CTL_RESSEL_Pos (6) /*!< EADC_T::CTL: RESSEL Position */ +#define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /*!< EADC_T::CTL: RESSEL Mask */ + +#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ +#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ + +#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ +#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ + +#define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */ +#define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */ + +#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ +#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ + +#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ +#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ + +#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ +#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ + +#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ +#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ + +#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */ +#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ + +#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */ +#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ + +#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ +#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ + +#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ +#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ + +#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ +#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ + +#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */ +#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ + +#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */ +#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */ + +#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ +#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ + +#define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ +#define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ + +#define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */ +#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ + +#define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */ +#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ + +#define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ +#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ + +#define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ +#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ + +#define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ +#define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ + +#define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */ +#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ + +#define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */ +#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */ + +#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */ +#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */ + +#define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ +#define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ + +#define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */ +#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ + +#define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */ +#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ + +#define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ +#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ + +#define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ +#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ + +#define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ +#define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ + +#define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */ +#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ + +#define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */ +#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */ + +#define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */ +#define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */ + +#define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ +#define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ + +#define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */ +#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ + +#define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */ +#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ + +#define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ +#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ + +#define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ +#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ + +#define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ +#define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ + +#define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */ +#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ + +#define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */ +#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */ + +#define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */ +#define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */ + +#define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ +#define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ + +#define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */ +#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ + +#define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */ +#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ + +#define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ +#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ + +#define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ +#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ + +#define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ +#define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ + +#define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */ +#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ + +#define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */ +#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */ + +#define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */ +#define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */ + +#define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ +#define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ + +#define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */ +#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ + +#define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */ +#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ + +#define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ +#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ + +#define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ +#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ + +#define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ +#define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ + +#define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */ +#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ + +#define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */ +#define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */ + +#define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ +#define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ + +#define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */ +#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ + +#define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */ +#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ + +#define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ +#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ + +#define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ +#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ + +#define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ +#define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ + +#define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */ +#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ + +#define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */ +#define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */ + +#define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ +#define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ + +#define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */ +#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ + +#define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */ +#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ + +#define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ +#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ + +#define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ +#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ + +#define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ +#define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ + +#define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */ +#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ + +#define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */ +#define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */ + +#define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ +#define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ + +#define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */ +#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ + +#define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */ +#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ + +#define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ +#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ + +#define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ +#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ + +#define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ +#define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ + +#define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */ +#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ + +#define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */ +#define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */ + +#define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */ +#define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */ + +#define EADC_SCTL8_EXTREN_Pos (4) /*!< EADC_T::SCTL8: EXTREN Position */ +#define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */ + +#define EADC_SCTL8_EXTFEN_Pos (5) /*!< EADC_T::SCTL8: EXTFEN Position */ +#define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */ + +#define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */ +#define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */ + +#define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */ +#define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */ + +#define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */ +#define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */ + +#define EADC_SCTL8_INTPOS_Pos (22) /*!< EADC_T::SCTL8: INTPOS Position */ +#define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */ + +#define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */ +#define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */ + +#define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */ +#define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */ + +#define EADC_SCTL9_EXTREN_Pos (4) /*!< EADC_T::SCTL9: EXTREN Position */ +#define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */ + +#define EADC_SCTL9_EXTFEN_Pos (5) /*!< EADC_T::SCTL9: EXTFEN Position */ +#define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */ + +#define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */ +#define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */ + +#define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */ +#define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */ + +#define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */ +#define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */ + +#define EADC_SCTL9_INTPOS_Pos (22) /*!< EADC_T::SCTL9: INTPOS Position */ +#define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */ + +#define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */ +#define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */ + +#define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */ +#define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */ + +#define EADC_SCTL10_EXTREN_Pos (4) /*!< EADC_T::SCTL10: EXTREN Position */ +#define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */ + +#define EADC_SCTL10_EXTFEN_Pos (5) /*!< EADC_T::SCTL10: EXTFEN Position */ +#define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */ + +#define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */ +#define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */ + +#define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */ +#define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */ + +#define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */ +#define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */ + +#define EADC_SCTL10_INTPOS_Pos (22) /*!< EADC_T::SCTL10: INTPOS Position */ +#define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */ + +#define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */ +#define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */ + +#define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */ +#define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */ + +#define EADC_SCTL11_EXTREN_Pos (4) /*!< EADC_T::SCTL11: EXTREN Position */ +#define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */ + +#define EADC_SCTL11_EXTFEN_Pos (5) /*!< EADC_T::SCTL11: EXTFEN Position */ +#define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */ + +#define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */ +#define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */ + +#define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */ +#define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */ + +#define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */ +#define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */ + +#define EADC_SCTL11_INTPOS_Pos (22) /*!< EADC_T::SCTL11: INTPOS Position */ +#define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */ + +#define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */ +#define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */ + +#define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */ +#define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */ + +#define EADC_SCTL12_EXTREN_Pos (4) /*!< EADC_T::SCTL12: EXTREN Position */ +#define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */ + +#define EADC_SCTL12_EXTFEN_Pos (5) /*!< EADC_T::SCTL12: EXTFEN Position */ +#define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */ + +#define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */ +#define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */ + +#define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */ +#define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */ + +#define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */ +#define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */ + +#define EADC_SCTL12_INTPOS_Pos (22) /*!< EADC_T::SCTL12: INTPOS Position */ +#define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */ + +#define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */ +#define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */ + +#define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */ +#define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */ + +#define EADC_SCTL13_EXTREN_Pos (4) /*!< EADC_T::SCTL13: EXTREN Position */ +#define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */ + +#define EADC_SCTL13_EXTFEN_Pos (5) /*!< EADC_T::SCTL13: EXTFEN Position */ +#define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */ + +#define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */ +#define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */ + +#define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */ +#define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */ + +#define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */ +#define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */ + +#define EADC_SCTL13_INTPOS_Pos (22) /*!< EADC_T::SCTL13: INTPOS Position */ +#define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */ + +#define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */ +#define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */ + +#define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */ +#define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */ + +#define EADC_SCTL14_EXTREN_Pos (4) /*!< EADC_T::SCTL14: EXTREN Position */ +#define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */ + +#define EADC_SCTL14_EXTFEN_Pos (5) /*!< EADC_T::SCTL14: EXTFEN Position */ +#define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */ + +#define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */ +#define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */ + +#define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */ +#define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */ + +#define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */ +#define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */ + +#define EADC_SCTL14_INTPOS_Pos (22) /*!< EADC_T::SCTL14: INTPOS Position */ +#define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */ + +#define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */ +#define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */ + +#define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */ +#define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */ + +#define EADC_SCTL15_EXTREN_Pos (4) /*!< EADC_T::SCTL15: EXTREN Position */ +#define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */ + +#define EADC_SCTL15_EXTFEN_Pos (5) /*!< EADC_T::SCTL15: EXTFEN Position */ +#define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */ + +#define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */ +#define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */ + +#define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */ +#define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */ + +#define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */ +#define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */ + +#define EADC_SCTL15_INTPOS_Pos (22) /*!< EADC_T::SCTL15: INTPOS Position */ +#define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */ + +#define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */ +#define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */ + +#define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */ +#define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */ + +#define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */ +#define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */ + +#define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */ +#define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */ + +#define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ +#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ + +#define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ +#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ + +#define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ +#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ + +#define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ +#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ + +#define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ +#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ + +#define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ +#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ + +#define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ +#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ + +#define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ +#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ + +#define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ +#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ + +#define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */ +#define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */ + +#define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */ +#define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */ + +#define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */ +#define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */ + +#define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */ +#define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */ + +#define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */ +#define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */ + +#define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */ +#define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */ + +#define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */ +#define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */ + +#define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */ +#define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */ + +#define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */ +#define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */ + +#define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */ +#define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */ + +#define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ +#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ + +#define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ +#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ + +#define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ +#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ + +#define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ +#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ + +#define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ +#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ + +#define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ +#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ + +#define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ +#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ + +#define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ +#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ + +#define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ +#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ + +#define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */ +#define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */ + +#define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */ +#define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */ + +#define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */ +#define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */ + +#define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */ +#define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */ + +#define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */ +#define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */ + +#define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */ +#define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */ + +#define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */ +#define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */ + +#define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */ +#define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */ + +#define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */ +#define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */ + +#define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */ +#define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */ + +#define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ +#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ + +#define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ +#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ + +#define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ +#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ + +#define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ +#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ + +#define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ +#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ + +#define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ +#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ + +#define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ +#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ + +#define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ +#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ + +#define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ +#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ + +#define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */ +#define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */ + +#define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */ +#define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */ + +#define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */ +#define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */ + +#define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */ +#define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */ + +#define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */ +#define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */ + +#define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */ +#define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */ + +#define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */ +#define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */ + +#define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */ +#define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */ + +#define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */ +#define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */ + +#define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */ +#define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */ + +#define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ +#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ + +#define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ +#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ + +#define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ +#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ + +#define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ +#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ + +#define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ +#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ + +#define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ +#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ + +#define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ +#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ + +#define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ +#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ + +#define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ +#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ + +#define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */ +#define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */ + +#define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */ +#define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */ + +#define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */ +#define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */ + +#define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */ +#define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */ + +#define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */ +#define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */ + +#define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */ +#define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */ + +#define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */ +#define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */ + +#define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */ +#define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */ + +#define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */ +#define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */ + +#define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */ +#define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */ + +#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */ +#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */ + +#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */ +#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */ + +#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */ +#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */ + +#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */ +#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */ + +#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */ +#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */ + +#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */ +#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */ + +#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */ +#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */ + +#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ +#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ + +#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ +#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ + +#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ +#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ + +#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ +#define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ + +#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ +#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ + +#define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ +#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ + +#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ +#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ + +#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ +#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ + +#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ +#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ + +#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ +#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ + +#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ +#define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ + +#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ +#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ + +#define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ +#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ + +#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ +#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ + +#define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ +#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ + +#define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ +#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ + +#define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ +#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ + +#define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ +#define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ + +#define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ +#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ + +#define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ +#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ + +#define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ +#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ + +#define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ +#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ + +#define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ +#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ + +#define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ +#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ + +#define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ +#define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ + +#define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ +#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ + +#define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ +#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ + +#define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ +#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ + +#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ +#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ + +#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ +#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ + +#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ +#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ + +#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ +#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ + +#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ +#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ + +#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ +#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ + +#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ +#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ + +#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ +#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ + +#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ +#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ + +#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ +#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ + +#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ +#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ + +#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ +#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ + +#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ +#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ + +#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ +#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ + +#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ +#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ + +#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ +#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ + +#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ +#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ + +#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ +#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ + +#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ +#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ + +#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ +#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ + +#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ +#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ + +#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ +#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ + +#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ +#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ + +#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ +#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ + +#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ +#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ + +#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ +#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ + +#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ +#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ + +#define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ +#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ + +#define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ +#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ + +#define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ +#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ + +#define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ +#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ + +#define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ +#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ + +#define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ +#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ + +#define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ +#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ + +#define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ +#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ + +#define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ +#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ + +#define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ +#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ + +#define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ +#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ + +#define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ +#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ + +#define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */ +#define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */ + +#define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */ +#define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */ + +#define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */ +#define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */ + +#define EADC_PWRM_LDOSUT_Pos (8) /*!< EADC_T::PWRM: LDOSUT Position */ +#define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /*!< EADC_T::PWRM: LDOSUT Mask */ + +#define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */ +#define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */ + +#define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */ +#define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */ + +#define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */ +#define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */ + +#define EADC_CALDWRD_CALWORD_Pos (0) /*!< EADC_T::CALDWRD: CALWORD Position */ +#define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /*!< EADC_T::CALDWRD: CALWORD Mask */ + +/**@}*/ /* EADC_CONST */ +/**@}*/ /* end of EADC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EADC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ebi_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ebi_reg.h new file mode 100644 index 00000000000..f0a51018a86 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ebi_reg.h @@ -0,0 +1,428 @@ +/**************************************************************************//** + * @file ebi_reg.h + * @version V1.00 + * @brief EBI register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_REG_H__ +#define __EBI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EBI External Bus Interface Controller(EBI) + Memory Mapped Structure for EBI Controller +@{ */ + +typedef struct +{ + + + /** + * @var EBI_T::CTL0 + * Offset: 0x00 External Bus Interface Bank0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL0 + * Offset: 0x04 External Bus Interface Bank0 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + * @var EBI_T::CTL1 + * Offset: 0x10 External Bus Interface Bank1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL1 + * Offset: 0x14 External Bus Interface Bank1 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + * @var EBI_T::CTL2 + * Offset: 0x20 External Bus Interface Bank2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL2 + * Offset: 0x24 External Bus Interface Bank2 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + */ + __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ + __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ + __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ + __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ + +} EBI_T; + +/** + @addtogroup EBI_CONST EBI Bit Field Definition + Constant Definitions for EBI Controller +@{ */ + +#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */ +#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */ + +#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */ +#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */ + +#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */ +#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */ + +#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */ +#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */ + +#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */ +#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */ + +#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */ +#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */ + +#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */ +#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */ + +#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */ +#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */ + +#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */ +#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */ + +#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */ +#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */ + +#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */ +#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */ + +#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */ +#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */ + +#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */ +#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */ + +#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */ +#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */ + +#define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */ +#define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */ + +#define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */ +#define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */ + +#define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */ +#define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */ + +#define EBI_CTL0_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */ +#define EBI_CTL0_ADSEPEN_Msk (0x1ul << EBI_CTL0_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */ + +#define EBI_CTL0_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */ +#define EBI_CTL0_CACCESS_Msk (0x1ul << EBI_CTL0_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */ + +#define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */ +#define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */ + +#define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */ +#define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */ + +#define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */ +#define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */ + +#define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */ +#define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */ + +#define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */ +#define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */ + +#define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */ +#define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */ + +#define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */ +#define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */ + +#define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */ +#define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */ + +#define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */ +#define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */ + +#define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */ +#define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */ + +#define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */ +#define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */ + +#define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */ +#define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */ + +#define EBI_CTL1_ADSEPEN_Pos (3) /*!< EBI_T::CTL1: ADSEPEN Position */ +#define EBI_CTL1_ADSEPEN_Msk (0x1ul << EBI_CTL1_ADSEPEN_Pos) /*!< EBI_T::CTL1: ADSEPEN Mask */ + +#define EBI_CTL1_CACCESS_Pos (4) /*!< EBI_T::CTL1: CACCESS Position */ +#define EBI_CTL1_CACCESS_Msk (0x1ul << EBI_CTL1_CACCESS_Pos) /*!< EBI_T::CTL1: CACCESS Mask */ + +#define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */ +#define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */ + +#define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */ +#define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */ + +#define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */ +#define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */ + +#define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */ +#define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */ + +#define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */ +#define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */ + +#define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */ +#define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */ + +#define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */ +#define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */ + +#define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */ +#define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */ + +#define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */ +#define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */ + +#define EBI_CTL2_EN_Pos (0) /*!< EBI_T::CTL2: EN Position */ +#define EBI_CTL2_EN_Msk (0x1ul << EBI_CTL2_EN_Pos) /*!< EBI_T::CTL2: EN Mask */ + +#define EBI_CTL2_DW16_Pos (1) /*!< EBI_T::CTL2: DW16 Position */ +#define EBI_CTL2_DW16_Msk (0x1ul << EBI_CTL2_DW16_Pos) /*!< EBI_T::CTL2: DW16 Mask */ + +#define EBI_CTL2_CSPOLINV_Pos (2) /*!< EBI_T::CTL2: CSPOLINV Position */ +#define EBI_CTL2_CSPOLINV_Msk (0x1ul << EBI_CTL2_CSPOLINV_Pos) /*!< EBI_T::CTL2: CSPOLINV Mask */ + +#define EBI_CTL2_ADSEPEN_Pos (3) /*!< EBI_T::CTL2: ADSEPEN Position */ +#define EBI_CTL2_ADSEPEN_Msk (0x1ul << EBI_CTL2_ADSEPEN_Pos) /*!< EBI_T::CTL2: ADSEPEN Mask */ + +#define EBI_CTL2_CACCESS_Pos (4) /*!< EBI_T::CTL2: CACCESS Position */ +#define EBI_CTL2_CACCESS_Msk (0x1ul << EBI_CTL2_CACCESS_Pos) /*!< EBI_T::CTL2: CACCESS Mask */ + +#define EBI_CTL2_MCLKDIV_Pos (8) /*!< EBI_T::CTL2: MCLKDIV Position */ +#define EBI_CTL2_MCLKDIV_Msk (0x7ul << EBI_CTL2_MCLKDIV_Pos) /*!< EBI_T::CTL2: MCLKDIV Mask */ + +#define EBI_CTL2_TALE_Pos (16) /*!< EBI_T::CTL2: TALE Position */ +#define EBI_CTL2_TALE_Msk (0x7ul << EBI_CTL2_TALE_Pos) /*!< EBI_T::CTL2: TALE Mask */ + +#define EBI_CTL2_WBUFEN_Pos (24) /*!< EBI_T::CTL2: WBUFEN Position */ +#define EBI_CTL2_WBUFEN_Msk (0x1ul << EBI_CTL2_WBUFEN_Pos) /*!< EBI_T::CTL2: WBUFEN Mask */ + +#define EBI_TCTL2_TACC_Pos (3) /*!< EBI_T::TCTL2: TACC Position */ +#define EBI_TCTL2_TACC_Msk (0x1ful << EBI_TCTL2_TACC_Pos) /*!< EBI_T::TCTL2: TACC Mask */ + +#define EBI_TCTL2_TAHD_Pos (8) /*!< EBI_T::TCTL2: TAHD Position */ +#define EBI_TCTL2_TAHD_Msk (0x7ul << EBI_TCTL2_TAHD_Pos) /*!< EBI_T::TCTL2: TAHD Mask */ + +#define EBI_TCTL2_W2X_Pos (12) /*!< EBI_T::TCTL2: W2X Position */ +#define EBI_TCTL2_W2X_Msk (0xful << EBI_TCTL2_W2X_Pos) /*!< EBI_T::TCTL2: W2X Mask */ + +#define EBI_TCTL2_RAHDOFF_Pos (22) /*!< EBI_T::TCTL2: RAHDOFF Position */ +#define EBI_TCTL2_RAHDOFF_Msk (0x1ul << EBI_TCTL2_RAHDOFF_Pos) /*!< EBI_T::TCTL2: RAHDOFF Mask */ + +#define EBI_TCTL2_WAHDOFF_Pos (23) /*!< EBI_T::TCTL2: WAHDOFF Position */ +#define EBI_TCTL2_WAHDOFF_Msk (0x1ul << EBI_TCTL2_WAHDOFF_Pos) /*!< EBI_T::TCTL2: WAHDOFF Mask */ + +#define EBI_TCTL2_R2R_Pos (24) /*!< EBI_T::TCTL2: R2R Position */ +#define EBI_TCTL2_R2R_Msk (0xful << EBI_TCTL2_R2R_Pos) /*!< EBI_T::TCTL2: R2R Mask */ + +/**@}*/ /* EBI_CONST */ +/**@}*/ /* end of EBI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EBI_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ecap_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ecap_reg.h new file mode 100644 index 00000000000..b09379fb629 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ecap_reg.h @@ -0,0 +1,389 @@ +/**************************************************************************//** + * @file ecap_reg.h + * @version V1.00 + * @brief ECAP register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ECAP_REG_H__ +#define __ECAP_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup ECAP Enhanced Input Capture Timer(ECAP) + Memory Mapped Structure for ECAP Controller +@{ */ + +typedef struct +{ + + /** + * @var ECAP_T::CNT + * Offset: 0x00 Input Capture Counter (24-bit up counter) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Input Capture Timer/Counter + * | | |The input Capture Timer/Counter is a 24-bit up-counting counter + * | | |The clock source for the counter is from the clock divider + * @var ECAP_T::HLD0 + * Offset: 0x04 Input Capture Hold Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD1 + * Offset: 0x08 Input Capture Hold Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD2 + * Offset: 0x0C Input Capture Hold Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::CNTCMP + * Offset: 0x10 Input Capture Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNTCMP |Input Capture Counter Compare Register + * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT). + * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT. + * @var ECAP_T::CTL0 + * Offset: 0x14 Input Capture Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock + * | | |000 = CAP_CLK. + * | | |001 = CAP_CLK/2. + * | | |010 = CAP_CLK/4. + * | | |011 = CAP_CLK/16. + * | | |100 = CAP_CLK/32. + * | | |101 = CAP_CLK/64. + * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control + * | | |0 = Noise filter of Input Capture Enabled. + * | | |1 = Noise filter of Input Capture Disabled (Bypass). + * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control + * | | |0 = IC0 input to Input Capture Unit Disabled. + * | | |1 = IC0 input to Input Capture Unit Enabled. + * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control + * | | |0 = IC1 input to Input Capture Unit Disabled. + * | | |1 = IC1 input to Input Capture Unit Enabled. + * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control + * | | |0 = IC2 input to Input Capture Unit Disabled. + * | | |1 = IC2 input to Input Capture Unit Enabled. + * |[9:8] |CAPSEL0 |CAP0 Input Source Selection + * | | |00 = CAP0 input is from port pin ICAP0. + * | | |01 = Reserved. + * | | |10 = CAP0 input is from signal CHA of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[11:10] |CAPSEL1 |CAP1 Input Source Selection + * | | |00 = CAP1 input is from port pin ICAP1. + * | | |01 = Reserved. + * | | |10 = CAP1 input is from signal CHB of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[13:12] |CAPSEL2 |CAP2 Input Source Selection + * | | |00 = CAP2 input is from port pin ICAP2. + * | | |01 = Reserved. + * | | |10 = CAP2 input is from signal CHX of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control + * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled. + * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control + * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled. + * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control + * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled. + * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled. + * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled. + * |[24] |CNTEN |Input Capture Counter Start Counting Control + * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . + * | | |0 = ECAP_CNT stop counting. + * | | |1 = ECAP_CNT starts up-counting. + * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control + * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. + * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled. + * |[28] |CMPEN |Compare Function Enable Control + * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. + * | | |0 = The compare function Disabled. + * | | |1 = The compare function Enabled. + * |[29] |CAPEN |Input Capture Timer/Counter Enable Control + * | | |0 = Input Capture function Disabled. + * | | |1 = Input Capture function Enabled. + * @var ECAP_T::CTL1 + * Offset: 0x18 Input Capture Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection + * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection + * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection + * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit + * | | |0 = The reload triggered by Event CAPTE0 Disabled. + * | | |1 = The reload triggered by Event CAPTE0 Enabled. + * |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit + * | | |0 = The reload triggered by Event CAPTE1 Disabled. + * | | |1 = The reload triggered by Event CAPTE1 Enabled. + * |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit + * | | |0 = The reload triggered by Event CAPTE2 Disabled. + * | | |1 = The reload triggered by Event CAPTE2 Enabled. + * |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit + * | | |0 = The reload triggered by CAPOV Disabled. + * | | |1 = The reload triggered by CAPOV Enabled. + * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection + * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. + * | | |000 = CAP_CLK/1. + * | | |001 = CAP_CLK/4. + * | | |010 = CAP_CLK/16. + * | | |011 = CAP_CLK/32. + * | | |100 = CAP_CLK/64. + * | | |101 = CAP_CLK/96. + * | | |110 = CAP_CLK/112. + * | | |111 = CAP_CLK/128. + * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection + * | | |Select the capture timer/counter clock source. + * | | |00 = CAP_CLK (default). + * | | |01 = CAP0. + * | | |10 = CAP1. + * | | |11 = CAP2. + * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control + * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled. + * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control + * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled. + * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control + * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled. + * @var ECAP_T::STATUS + * Offset: 0x1C Input Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag + * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. + * | | |0 = No valid edge change has been detected at CAP0 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag + * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. + * | | |0 = No valid edge change has been detected at CAP1 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag + * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. + * | | |0 = No valid edge change has been detected at CAP2 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[4] |CAPCMPF |Input Capture Compare-match Flag + * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. + * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear. + * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[5] |CAPOVF |Input Capture Counter Overflow Flag + * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. + * | | |0 = No overflow event has occurred since last clear. + * | | |1 = Overflow event(s) has/have occurred since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only) + * | | |Reflecting the value of input channel 0, CAP0 + * | | |(The bit is read only and write is ignored) + * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only) + * | | |Reflecting the value of input channel 1, CAP1 + * | | |(The bit is read only and write is ignored) + * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only) + * | | |Reflecting the value of input channel 2, CAP2. + * | | |(The bit is read only and write is ignored) + */ + __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */ + __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */ + __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */ + __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */ + __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */ + __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */ + __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */ + +} ECAP_T; + +/** + @addtogroup ECAP_CONST ECAP Bit Field Definition + Constant Definitions for ECAP Controller +@{ */ + +#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */ +#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */ + +#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */ +#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */ + +#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */ +#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */ + +#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */ +#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */ + +#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */ +#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */ + +#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */ +#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */ + +#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */ +#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */ + +#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */ +#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */ + +#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */ +#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */ + +#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */ +#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */ + +#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */ +#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */ + +#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */ +#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */ + +#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */ +#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */ + +#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */ +#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */ + +#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */ +#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */ + +#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */ +#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */ + +#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */ +#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */ + +#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */ +#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */ + +#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */ +#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */ + +#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */ +#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */ + +#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */ +#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */ + +#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */ +#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */ + +#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */ +#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */ + +#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */ +#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */ + +#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */ +#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */ + +#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */ +#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */ + +#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */ +#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */ + +#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */ +#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */ + +#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */ +#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */ + +#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */ +#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */ + +#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */ +#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */ + +#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */ +#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */ + +#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */ +#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */ + +#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */ +#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */ + +#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */ +#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */ + +#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */ +#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */ + +#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */ +#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */ + +#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */ +#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */ + +#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */ +#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */ + +#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */ +#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */ + +#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */ +#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */ + +#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */ +#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */ + +/**@}*/ /* ECAP_CONST */ +/**@}*/ /* end of ECAP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __ECAP_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/emac_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/emac_reg.h new file mode 100644 index 00000000000..b75fed4d1f3 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/emac_reg.h @@ -0,0 +1,2062 @@ +/**************************************************************************//** + * @file emac_reg.h + * @version V1.00 + * @brief EMAC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EMAC_REG_H__ +#define __EMAC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EMAC Ethernet MAC Controller(EMAC) + Memory Mapped Structure for EMAC Controller +@{ */ + +typedef struct +{ + + /** + * @var EMAC_T::CAMCTL + * Offset: 0x00 CAM Comparison Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AUP |Accept Unicast Packet + * | | |The AUP controls the unicast packet reception + * | | |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all unicast packets. + * |[1] |AMP |Accept Multicast Packet + * | | |The AMP controls the multicast packet reception + * | | |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all multicast packets. + * |[2] |ABP |Accept Broadcast Packet + * | | |The ABP controls the broadcast packet reception + * | | |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all broadcast packets. + * |[3] |COMPEN |Complement CAM Comparison Enable Bit + * | | |The COMPEN controls the complement of the CAM comparison result + * | | |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address + * | | |configured in CAM entry will be dropped + * | | |And the incoming packet with destination MAC address does not configured in any CAM entry will be received. + * | | |0 = Complement CAM comparison result Disabled. + * | | |1 = Complement CAM comparison result Enabled. + * |[4] |CMPEN |CAM Compare Enable Bit + * | | |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition + * | | |If software wants to receive a packet with specific destination MAC address, configures the MAC address + * | | |into CAM 12~0, then enables that CAM entry and set CMPEN to 1. + * | | |0 = CAM comparison function for destination MAC address recognition Disabled. + * | | |1 = CAM comparison function for destination MAC address recognition Enabled. + * @var EMAC_T::CAMEN + * Offset: 0x04 CAM Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAMxEN |CAM Entry X Enable Bit + * | | |The CAMxEN controls the validation of CAM entry x. + * | | |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission + * | | |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM + * | | |entries all must be enabled first. + * | | |0 = CAM entry x Disabled. + * | | |1 = CAM entry x Enabled. + * @var EMAC_T::CAM0M + * Offset: 0x08 CAM0 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM0L + * Offset: 0x0C CAM0 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM1M + * Offset: 0x10 CAM1 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM1L + * Offset: 0x14 CAM1 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM2M + * Offset: 0x18 CAM2 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM2L + * Offset: 0x1C CAM2 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM3M + * Offset: 0x20 CAM3 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM3L + * Offset: 0x24 CAM3 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM4M + * Offset: 0x28 CAM4 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM4L + * Offset: 0x2C CAM4 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM5M + * Offset: 0x30 CAM5 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM5L + * Offset: 0x34 CAM5 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM6M + * Offset: 0x38 CAM6 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM6L + * Offset: 0x3C CAM6 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM7M + * Offset: 0x40 CAM7 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM7L + * Offset: 0x44 CAM7 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM8M + * Offset: 0x48 CAM8 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM8L + * Offset: 0x4C CAM8 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM9M + * Offset: 0x50 CAM9 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM9L + * Offset: 0x54 CAM9 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM10M + * Offset: 0x58 CAM10 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM10L + * Offset: 0x5C CAM10 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM11M + * Offset: 0x60 CAM11 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM11L + * Offset: 0x64 CAM11 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM12M + * Offset: 0x68 CAM12 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM12L + * Offset: 0x6C CAM12 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM13M + * Offset: 0x70 CAM13 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM13L + * Offset: 0x74 CAM13 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM14M + * Offset: 0x78 CAM14 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM14L + * Offset: 0x7C CAM14 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM15MSB + * Offset: 0x80 CAM15 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |OPCODE |OP Code Field of PAUSE Control Frame + * | | |In the PAUSE control frame, an op code field defined and is 0x0001. + * |[31:16] |LENGTH |LENGTH Field of PAUSE Control Frame + * | | |In the PAUSE control frame, a LENGTH field defined and is 0x8808. + * @var EMAC_T::CAM15LSB + * Offset: 0x84 CAM15 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:24] |OPERAND |Pause Parameter + * | | |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination + * | | |Ethernet MAC Controller paused + * | | |The unit of the OPERAND is a slot time, the 512-bit time. + * @var EMAC_T::TXDSA + * Offset: 0x88 Transmit Descriptor Link List Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXDSA |Transmit Descriptor Link-list Start Address + * | | |The TXDSA keeps the start address of transmit descriptor link-list + * | | |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the + * | | |current transmit descriptor start address register (EMAC_CTXDSA) + * | | |The TXDSA does not be updated by EMAC + * | | |During the operation, EMAC will ignore the bits [1:0] of TXDSA + * | | |This means that TX descriptors must locate at word boundary memory address. + * @var EMAC_T::RXDSA + * Offset: 0x8C Receive Descriptor Link List Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXDSA |Receive Descriptor Link-list Start Address + * | | |The RXDSA keeps the start address of receive descriptor link-list + * | | |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current + * | | |receive descriptor start address register (EMAC_CRXDSA) + * | | |The RXDSA does not be updated by EMAC + * | | |During the operation, EMAC will ignore the bits [1:0] of RXDSA + * | | |This means that RX descriptors must locate at word boundary memory address. + * @var EMAC_T::CTL + * Offset: 0x90 MAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXON |Frame Reception ON + * | | |The RXON controls the normal packet reception of EMAC + * | | |If the RXON is set to high, the EMAC starts the packet reception process, including the RX + * | | |descriptor fetching, packet reception and RX descriptor modification. + * | | |It is necessary to finish EMAC initial sequence before enable RXON + * | | |Otherwise, the EMAC operation is undefined. + * | | |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet + * | | |reception process after the current packet reception finished. + * | | |0 = Packet reception process stopped. + * | | |1 = Packet reception process started. + * |[1] |ALP |Accept Long Packet + * | | |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception + * | | |If the ALP is set to high, the EMAC will accept the long packet. + * | | |Otherwise, the long packet will be dropped. + * | | |0 = Ethernet MAC controller dropped the long packet. + * | | |1 = Ethernet MAC controller received the long packet. + * |[2] |ARP |Accept Runt Packet + * | | |The ARP controls the runt packet, which length is less than 64 bytes, reception + * | | |If the ARP is set to high, the EMAC will accept the runt packet. + * | | |Otherwise, the runt packet will be dropped. + * | | |0 = Ethernet MAC controller dropped the runt packet. + * | | |1 = Ethernet MAC controller received the runt packet. + * |[3] |ACP |Accept Control Packet + * | | |The ACP controls the control frame reception + * | | |If the ACP is set to high, the EMAC will accept the control frame + * | | |Otherwise, the control frame will be dropped + * | | |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode. + * | | |0 = Ethernet MAC controller dropped the control frame. + * | | |1 = Ethernet MAC controller received the control frame. + * |[4] |AEP |Accept CRC Error Packet + * | | |The AEP controls the EMAC accepts or drops the CRC error packet + * | | |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet. + * | | |0 = Ethernet MAC controller dropped the CRC error packet. + * | | |1 = Ethernet MAC controller received the CRC error packet. + * |[5] |STRIPCRC |Strip CRC Checksum + * | | |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum + * | | |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet. + * | | |0 = The 4 bytes CRC checksum is included in packet length calculation. + * | | |1 = The 4 bytes CRC checksum is excluded in packet length calculation. + * |[6] |WOLEN |Wake on LAN Enable Bit + * | | |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet + * | | |is Magic Packet and wakeup system from Power-down mode. + * | | |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller + * | | |would generate a wakeup event to wake system up from Power-down mode. + * | | |0 = Wake-up by Magic Packet function Disabled. + * | | |1 = Wake-up by Magic Packet function Enabled. + * |[8] |TXON |Frame Transmission ON + * | | |The TXON controls the normal packet transmission of EMAC + * | | |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX + * | | |descriptor fetching, packet transmission and TX descriptor modification. + * | | |It is must to finish EMAC initial sequence before enable TXON + * | | |Otherwise, the EMAC operation is undefined. + * | | |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet + * | | |transmission process after the current packet transmission finished. + * | | |0 = Packet transmission process stopped. + * | | |1 = Packet transmission process started. + * |[9] |NODEF |No Deferral + * | | |The NODEF controls the enable of deferral exceed counter + * | | |If NODEF is set to high, the deferral exceed counter is disabled + * | | |The NODEF is only useful while EMAC is operating on half duplex mode. + * | | |0 = The deferral exceed counter Enabled. + * | | |1 = The deferral exceed counter Disabled. + * |[16] |SDPZ |Send PAUSE Frame + * | | |The SDPZ controls the PAUSE control frame transmission. + * | | |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured + * | | |first and the corresponding CAM enable bit of CAMEN register also must be set. + * | | |Then, set SDPZ to 1 enables the PAUSE control frame transmission. + * | | |The SDPZ is a self-clear bit + * | | |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically. + * | | |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode. + * | | |0 = PAUSE control frame transmission completed. + * | | |1 = PAUSE control frame transmission Enabled. + * |[17] |SQECHKEN |SQE Checking Enable Bit + * | | |The SQECHKEN controls the enable of SQE checking + * | | |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode + * | | |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps + * | | |or full duplex mode. + * | | |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode. + * | | |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode. + * |[18] |FUDUP |Full Duplex Mode Selection + * | | |The FUDUP controls that if EMAC is operating on full or half duplex mode. + * | | |0 = EMAC operates in half duplex mode. + * | | |1 = EMAC operates in full duplex mode. + * |[19] |RMIIRXCTL |RMII RX Control + * | | |The RMIIRXCTL control the receive data sample in RMII mode + * | | |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high. + * | | |0 = RMII RX control disabled. + * | | |1 = RMII RX control enabled. + * |[20] |OPMODE |Operation Mode Selection + * | | |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode + * | | |The RST (EMAC_CTL[24]) would not affect OPMODE value. + * | | |0 = EMAC operates in 10Mbps mode. + * | | |1 = EMAC operates in 100Mbps mode. + * |[22] |RMIIEN |RMII Mode Enable Bit + * | | |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII + * | | |interface or RMII interface + * | | |The RST (EMAC_CTL[24]) would not affect RMIIEN value. + * | | |0 = Ethernet MAC controller RMII mode Disabled. + * | | |1 = Ethernet MAC controller RMII mode Enabled. + * | | |NOTE: This field must keep 1. + * |[24] |RST |Software Reset + * | | |The RST implements a reset function to make the EMAC return default state + * | | |The RST is a self-clear bit + * | | |This means after the software reset finished, the RST will be cleared automatically + * | | |Enable RST can also reset all control and status registers, exclusive of the control bits + * | | |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]). + * | | |The EMAC re-initial is necessary after the software reset completed. + * | | |0 = Software reset completed. + * | | |1 = Software reset Enabled. + * @var EMAC_T::MIIMDAT + * Offset: 0x94 MII Management Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATA |MII Management Data + * | | |The DATA is the 16 bits data that will be written into the registers of external PHY for MII + * | | |Management write command or the data from the registers of external PHY for MII Management read command. + * @var EMAC_T::MIIMCTL + * Offset: 0x98 MII Management Control and Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PHYREG |PHY Register Address + * | | |The PHYREG keeps the address to indicate which register of external PHY is the target of the + * | | |MII management command. + * |[12:8] |PHYADDR |PHY Address + * | | |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command. + * |[16] |WRITE |Write Command + * | | |The Write defines the MII management command is a read or write. + * | | |0 = MII management command is a read command. + * | | |1 = MII management command is a write command. + * |[17] |BUSY |Busy Bit + * | | |The BUSY controls the enable of the MII management frame generation + * | | |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates + * | | |the MII management frame to external PHY through MII Management I/F + * | | |The BUSY is a self-clear bit + * | | |This means the BUSY will be cleared automatically after the MII management command finished. + * | | |0 = MII management command generation finished. + * | | |1 = MII management command generation Enabled. + * |[18] |PREAMSP |Preamble Suppress + * | | |The PREAMSP controls the preamble field generation of MII management frame + * | | |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped. + * | | |0 = Preamble field generation of MII management frame not skipped. + * | | |1 = Preamble field generation of MII management frame skipped. + * |[19] |MDCON |MDC Clock ON + * | | |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on. + * | | |0 = MDC clock off. + * | | |1 = MDC clock on. + * @var EMAC_T::FIFOCTL + * Offset: 0x9C FIFO Threshold Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RXFIFOTH |RXFIFO Low Threshold + * | | |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO + * | | |and system memory + * | | |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold + * | | |The low threshold is the half of high threshold always + * | | |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to + * | | |transfer frame data from RXFIFO to system memory + * | | |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame + * | | |data to system memory. + * | | |00 = Depend on the burst length setting + * | | |If the burst length is 8 words, high threshold is 8 words, too. + * | | |01 = RXFIFO high threshold is 64B and low threshold is 32B. + * | | |10 = RXFIFO high threshold is 128B and low threshold is 64B. + * | | |11 = RXFIFO high threshold is 192B and low threshold is 96B. + * |[9:8] |TXFIFOTH |TXFIFO Low Threshold + * | | |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system + * | | |memory and TXFIFO + * | | |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold + * | | |The high threshold is the twice of low threshold always + * | | |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops + * | | |generate request to transfer frame data from system memory to TXFIFO + * | | |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data + * | | |from system memory to TXFIFO. + * | | |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network + * | | |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold + * | | |during the transmission of the frame + * | | |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame + * | | |out after the frame data are all inside the TXFIFO. + * | | |00 = Undefined. + * | | |01 = TXFIFO low threshold is 64B and high threshold is 128B. + * | | |10 = TXFIFO low threshold is 80B and high threshold is 160B. + * | | |11 = TXFIFO low threshold is 96B and high threshold is 192B. + * |[21:20] |BURSTLEN |DMA Burst Length + * | | |This defines the burst length of AHB bus cycle while EMAC accesses system memory. + * | | |00 = 4 words. + * | | |01 = 8 words. + * | | |10 = 16 words. + * | | |11 = 16 words. + * @var EMAC_T::TXST + * Offset: 0xA0 Transmit Start Demand Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXST |Transmit Start Demand + * | | |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, + * | | |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted + * | | |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write + * | | |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission. + * | | |The EMAC_TXST is a write only register and read from this register is undefined. + * | | |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state. + * @var EMAC_T::RXST + * Offset: 0xA4 Receive Start Demand Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXST |Receive Start Demand + * | | |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, + * | | |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted + * | | |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write + * | | |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception. + * | | |The EMAC_RXST is a write only register and read from this register is undefined. + * | | |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state. + * @var EMAC_T::MRFL + * Offset: 0xA8 Maximum Receive Frame Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MRFL |Maximum Receive Frame Length + * | | |The MRFL defines the maximum frame length for received frame + * | | |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) + * | | |is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered. + * | | |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to + * | | |receive a frame which length is greater than 1518 bytes. + * @var EMAC_T::INTEN + * Offset: 0xAC MAC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXIEN |Receive Interrupt Enable Bit + * | | |The RXIEN controls the RX interrupt generation. + * | | |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU + * | | |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] + * | | |is set and the corresponding bit of EMAC_INTEN is enabled + * | | |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled + * | | |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit. + * | | |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled. + * | | |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled. + * |[1] |CRCEIEN |CRC Error Interrupt Enable Bit + * | | |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation + * | | |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |CRCEIF (EMAC_INTSTS[1]) is set. + * | | |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled. + * | | |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled. + * |[2] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Bit + * | | |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation + * | | |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXOVIF (EMAC_INTSTS[2]) is set. + * | | |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled. + * | | |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled. + * |[3] |LPIEN |Long Packet Interrupt Enable Bit + * | | |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation + * | | |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC + * | | |generates the RX interrupt to CPU + * | | |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF + * | | |(EMAC_INTSTS[3]) is set. + * | | |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled. + * | | |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled. + * |[4] |RXGDIEN |Receive Good Interrupt Enable Bit + * | | |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation + * | | |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXGDIF (EMAC_INTSTS[4]) is set. + * | | |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled. + * | | |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled. + * |[5] |ALIEIEN |Alignment Error Interrupt Enable Bit + * | | |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation + * | | |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |ALIEIF (EMAC_INTSTS[5]) is set. + * | | |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled. + * | | |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled. + * |[6] |RPIEN |Runt Packet Interrupt Enable Bit + * | | |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation + * | | |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC + * | | |generates the RX interrupt to CPU + * | | |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RPIF (EMAC_INTSTS[6]) is set. + * | | |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled. + * | | |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled. + * |[7] |MPCOVIEN |Miss Packet Counter Overrun Interrupt Enable Bit + * | | |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation + * | | |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, + * | | |the EMAC generates the RX interrupt to CPU + * | | |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |MPCOVIF (EMAC_INTSTS[7]) is set. + * | | |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled. + * | | |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled. + * |[8] |MFLEIEN |Maximum Frame Length Exceed Interrupt Enable Bit + * | | |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation + * | | |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |MFLEIF (EMAC_INTSTS[8]) is set. + * | | |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled. + * | | |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled. + * |[9] |DENIEN |DMA Early Notification Interrupt Enable Bit + * | | |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation + * | | |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |DENIF (EMAC_INTSTS[9]) is set. + * | | |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled. + * | | |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled. + * |[10] |RDUIEN |Receive Descriptor Unavailable Interrupt Enable Bit + * | | |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation + * | | |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RDUIF (EMAC_MIOSTA[10]) register is set. + * | | |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled. + * | | |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled. + * |[11] |RXBEIEN |Receive Bus Error Interrupt Enable Bit + * | | |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation + * | | |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXBEIF (EMAC_INTSTS[11]) is set. + * | | |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled. + * | | |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled. + * |[14] |CFRIEN |Control Frame Receive Interrupt Enable Bit + * | | |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation + * | | |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |CFRIF (EMAC_INTSTS[14]) register is set. + * | | |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled. + * | | |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled. + * |[15] |WOLIEN |Wake on LAN Interrupt Enable Bit + * | | |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation + * | | |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, + * | | |the EMAC generates the RX interrupt to CPU + * | | |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |WOLIF (EMAC_INTSTS[15]) is set. + * | | |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled. + * | | |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled. + * |[16] |TXIEN |Transmit Interrupt Enable Bit + * | | |The TXIEN controls the TX interrupt generation. + * | | |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU + * | | |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of + * | | |EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled + * | | |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled + * | | |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit. + * | | |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled. + * | | |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled. + * |[17] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Bit + * | | |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation + * | | |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even + * | | |the TXUDIF (EMAC_INTSTS[17]) is set. + * | | |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled. + * | | |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled. + * |[18] |TXCPIEN |Transmit Completion Interrupt Enable Bit + * | | |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation + * | | |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXCPIF (EMAC_INTSTS[18]) is set. + * | | |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled. + * | | |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled. + * |[19] |EXDEFIEN |Defer Exceed Interrupt Enable Bit + * | | |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation + * | | |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |EXDEFIF (EMAC_INTSTS[19]) is set. + * | | |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled. + * | | |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled. + * |[20] |NCSIEN |No Carrier Sense Interrupt Enable Bit + * | | |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation + * | | |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |NCSIF (EMAC_INTSTS[20]) is set. + * | | |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled. + * | | |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled. + * |[21] |TXABTIEN |Transmit Abort Interrupt Enable Bit + * | | |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation + * | | |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXABTIF (EMAC_INTSTS[21]) is set. + * | | |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled. + * | | |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled. + * |[22] |LCIEN |Late Collision Interrupt Enable Bit + * | | |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation + * | | |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |LCIF (EMAC_INTSTS[22]) is set. + * | | |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled. + * | | |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled. + * |[23] |TDUIEN |Transmit Descriptor Unavailable Interrupt Enable Bit + * | | |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation + * | | |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TDUIF (EMAC_INTSTS[23]) is set. + * | | |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled. + * | | |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled. + * |[24] |TXBEIEN |Transmit Bus Error Interrupt Enable Bit + * | | |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation + * | | |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXBEIF (EMAC_INTSTS[24]) is set. + * | | |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled. + * | | |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled. + * |[28] |TSALMIEN |Time Stamp Alarm Interrupt Enable Bit + * | | |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation + * | | |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the + * | | |TXTSALMIF (EMAC_INTEN[28]) is set. + * | | |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled. + * | | |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled. + * @var EMAC_T::INTSTS + * Offset: 0xB0 MAC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXIF |Receive Interrupt + * | | |The RXIF indicates the RX interrupt status. + * | | |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates + * | | |the EMAC generates RX interrupt to CPU + * | | |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated. + * | | |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1] + * | | |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in + * | | |EMAC_INTEN[15:1] is also enabled, the RXIF will be high. + * | | |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too. + * | | |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled. + * | | |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in + * | | |EMAC_INTEN[15:1] is enabled, too. + * |[1] |CRCEIF |CRC Error Interrupt + * | | |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped + * | | |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and + * | | |CRCEIF will not be set. + * | | |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the CRCEIF status. + * | | |0 = The frame does not incur CRC error. + * | | |1 = The frame incurred CRC error. + * |[2] |RXOVIF |Receive FIFO Overflow Interrupt + * | | |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception + * | | |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer + * | | |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control, + * | | |the RXFIFOTH of FFTCR register, to higher level. + * | | |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXOVIF status. + * | | |0 = No RXFIFO overflow occurred during packet reception. + * | | |1 = RXFIFO overflow occurred during packet reception. + * |[3] |LPIF |Long Packet Interrupt Flag + * | | |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the + * | | |incoming packet is dropped + * | | |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set. + * | | |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the LPIF status. + * | | |0 = The incoming frame is not a long frame or S/W wants to receive a long frame. + * | | |1 = The incoming frame is a long frame and dropped. + * |[4] |RXGDIF |Receive Good Interrupt + * | | |The RXGDIF high indicates the frame reception has completed. + * | | |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXGDIF status. + * | | |0 = The frame reception has not complete yet. + * | | |1 = The frame reception has completed. + * |[5] |ALIEIF |Alignment Error Interrupt + * | | |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte + * | | |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the ALIEIF status. + * | | |0 = The frame length is a multiple of byte. + * | | |1 = The frame length is not a multiple of byte. + * |[6] |RPIF |Runt Packet Interrupt + * | | |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped + * | | |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set. + * | | |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RPIF status. + * | | |0 = The incoming frame is not a short frame or S/W wants to receive a short frame. + * | | |1 = The incoming frame is a short frame and dropped. + * |[7] |MPCOVIF |Missed Packet Counter Overrun Interrupt Flag + * | | |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow + * | | |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the MPCOVIF status. + * | | |0 = The MPCNT has not rolled over yet. + * | | |1 = The MPCNT has rolled over yet. + * |[8] |MFLEIF |Maximum Frame Length Exceed Interrupt Flag + * | | |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation + * | | |configured in DMARFC register and the incoming packet is dropped + * | | |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the MFLEIF status. + * | | |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC. + * | | |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC. + * |[9] |DENIF |DMA Early Notification Interrupt + * | | |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet. + * | | |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the DENIF status. + * | | |0 = The LENGTH field of incoming packet has not received yet. + * | | |1 = The LENGTH field of incoming packet has received. + * |[10] |RDUIF |Receive Descriptor Unavailable Interrupt + * | | |The RDUIF high indicates that there is no available RX descriptor for packet reception and + * | | |RXDMA will stay at Halt state + * | | |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to + * | | |make RXDMA leave Halt state while new RX descriptor is available. + * | | |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RDUIF status. + * | | |0 = RX descriptor is available. + * | | |1 = RX descriptor is unavailable. + * |[11] |RXBEIF |Receive Bus Error Interrupt + * | | |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access + * | | |system memory through RXDMA during packet reception process + * | | |Reset EMAC is recommended while RXBEIF status is high. + * | | |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXBEIF status. + * | | |0 = No ERROR response is received. + * | | |1 = ERROR response is received. + * |[14] |CFRIF |Control Frame Receive Interrupt + * | | |The CFRIF high indicates EMAC receives a flow control frame + * | | |The CFRIF only available while EMAC is operating on full duplex mode. + * | | |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the CFRIF status. + * | | |0 = The EMAC does not receive the flow control frame. + * | | |1 = The EMAC receives a flow control frame. + * |[15] |WOLIF |Wake on LAN Interrupt Flag + * | | |The WOLIF high indicates EMAC receives a Magic Packet + * | | |The CFRIF only available while system is in power down mode and WOLEN is set high. + * | | |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the WOLIF status. + * | | |0 = The EMAC does not receive the Magic Packet. + * | | |1 = The EMAC receives a Magic Packet. + * |[16] |TXIF |Transmit Interrupt + * | | |The TXIF indicates the TX interrupt status. + * | | |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates + * | | |the EMAC generates TX interrupt to CPU + * | | |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated. + * | | |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17] + * | | |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit + * | | |in EMAC_INTEN[28:17] is also enabled, the TXIF will be high + * | | |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too. + * | | |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled. + * | | |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit + * | | |in EMAC_INTEN[28:17] is enabled, too. + * |[17] |TXUDIF |Transmit FIFO Underflow Interrupt + * | | |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission + * | | |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically + * | | |without S/W intervention + * | | |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, + * | | |the TXFIFOTH of FFTCR register, to higher level. + * | | |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXUDIF status. + * | | |0 = No TXFIFO underflow occurred during packet transmission. + * | | |1 = TXFIFO underflow occurred during packet transmission. + * |[18] |TXCPIF |Transmit Completion Interrupt + * | | |The TXCPIF indicates the packet transmission has completed correctly. + * | | |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXCPIF status. + * | | |0 = The packet transmission not completed. + * | | |1 = The packet transmission has completed. + * |[19] |EXDEFIF |Defer Exceed Interrupt + * | | |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms + * | | |on 100Mbps mode, or 3.2768ms on 10Mbps mode. + * | | |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC + * | | |is operating on half-duplex mode. + * | | |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the EXDEFIF status. + * | | |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). + * | | |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). + * |[20] |NCSIF |No Carrier Sense Interrupt + * | | |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during + * | | |the packet transmission + * | | |The NCSIF is only available while EMAC is operating on half-duplex mode + * | | |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the NCSIF status. + * | | |0 = CRS signal actives correctly. + * | | |1 = CRS signal does not active at the start of or during the packet transmission. + * |[21] |TXABTIF |Transmit Abort Interrupt + * | | |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission, + * | | |and then the transmission process for this packet is aborted + * | | |The transmission abort is only available while EMAC is operating on half-duplex mode. + * | | |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXABTIF status. + * | | |0 = Packet does not incur 16 consecutive collisions during transmission. + * | | |1 = Packet incurred 16 consecutive collisions during transmission. + * |[22] |LCIF |Late Collision Interrupt + * | | |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window + * | | |This means after the 64 bytes of a frame has been transmitted out to the network, the collision + * | | |still occurred. + * | | |The late collision check will only be done while EMAC is operating on half-duplex mode + * | | |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the LCIF status. + * | | |0 = No collision occurred in the outside of 64 bytes collision window. + * | | |1 = Collision occurred in the outside of 64 bytes collision window. + * |[23] |TDUIF |Transmit Descriptor Unavailable Interrupt + * | | |The TDUIF high indicates that there is no available TX descriptor for packet transmission and + * | | |TXDMA will stay at Halt state. + * | | |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make + * | | |TXDMA leave Halt state while new TX descriptor is available. + * | | |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TDUIF status. + * | | |0 = TX descriptor is available. + * | | |1 = TX descriptor is unavailable. + * |[24] |TXBEIF |Transmit Bus Error Interrupt + * | | |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system + * | | |memory through TXDMA during packet transmission process + * | | |Reset EMAC is recommended while TXBEIF status is high. + * | | |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TXBEIF status. + * | | |0 = No ERROR response is received. + * | | |1 = ERROR response is received. + * |[28] |TSALMIF |Time Stamp Alarm Interrupt + * | | |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and + * | | |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR. + * | | |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TSALMIF status. + * | | |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC. + * | | |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC. + * @var EMAC_T::GENSTS + * Offset: 0xB4 MAC General Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CFR |Control Frame Received + * | | |The CFRIF high indicates EMAC receives a flow control frame + * | | |The CFRIF only available while EMAC is operating on full duplex mode. + * | | |0 = The EMAC does not receive the flow control frame. + * | | |1 = The EMAC receives a flow control frame. + * |[1] |RXHALT |Receive Halted + * | | |The RXHALT high indicates the next normal packet reception process will be halted because + * | | |the bit RXON of MCMDR is disabled be S/W. + * | | |0 = Next normal packet reception process will go on. + * | | |1 = Next normal packet reception process will be halted. + * |[2] |RXFFULL |RXFIFO Full + * | | |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO + * | | |and the following incoming packet will be dropped. + * | | |0 = The RXFIFO is not full. + * | | |1 = The RXFIFO is full and the following incoming packet will be dropped. + * |[7:4] |COLCNT |Collision Count + * | | |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission + * | | |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be + * | | |0 and bit TXABTIF will be set to 1. + * |[8] |DEF |Deferred Transmission + * | | |The DEF high indicates the packet transmission has deferred once + * | | |The DEF is only available while EMAC is operating on half-duplex mode. + * | | |0 = Packet transmission does not defer. + * | | |1 = Packet transmission has deferred once. + * |[9] |TXPAUSED |Transmission Paused + * | | |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally + * | | |because EMAC received a PAUSE control frame. + * | | |0 = Next normal packet transmission process will go on. + * | | |1 = Next normal packet transmission process will be paused. + * |[10] |SQE |Signal Quality Error + * | | |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode + * | | |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC + * | | |is operating on 10Mbps half-duplex mode. + * | | |0 = No SQE error found at end of packet transmission. + * | | |1 = SQE error found at end of packet transmission. + * |[11] |TXHALT |Transmission Halted + * | | |The TXHALT high indicates the next normal packet transmission process will be halted because + * | | |the bit TXON (EMAC_CTL[8]) is disabled be S/W. + * | | |0 = Next normal packet transmission process will go on. + * | | |1 = Next normal packet transmission process will be halted. + * |[12] |RPSTS |Remote Pause Status + * | | |The RPSTS indicates that remote pause counter down counting actives. + * | | |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause + * | | |counter down counting + * | | |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet + * | | |transmission until the down counting done. + * | | |0 = Remote pause counter down counting done. + * | | |1 = Remote pause counter down counting actives. + * @var EMAC_T::MPCNT + * Offset: 0xB8 Missed Packet Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MPCNT |Miss Packet Count + * | | |The MPCNT indicates the number of packets that were dropped due to various types of receive errors + * | | |The following type of receiving error makes missed packet counter increase: + * | | |1. Incoming packet is incurred RXFIFO overflow. + * | | |2. Incoming packet is dropped due to RXON is disabled. + * | | |3. Incoming packet is incurred CRC error. + * @var EMAC_T::RPCNT + * Offset: 0xBC MAC Receive Pause Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RPCNT |MAC Receive Pause Count + * | | |The RPCNT keeps the OPERAND field of the PAUSE control frame + * | | |It indicates how many slot time (512 bit time) the TX of EMAC will be paused. + * @var EMAC_T::FRSTS + * Offset: 0xC8 DMA Receive Frame Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXFLT |Receive Frame LENGTH + * | | |The RXFLT keeps the LENGTH field of each incoming Ethernet packet + * | | |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has + * | | |received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt. + * | | |And, the content of LENGTH field will be stored in RXFLT. + * @var EMAC_T::CTXDSA + * Offset: 0xCC Current Transmit Descriptor Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CTXDSA |Current Transmit Descriptor Start Address + * | | |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently + * | | |The CTXDSA is read only and write to this register has no effect. + * @var EMAC_T::CTXBSA + * Offset: 0xD0 Current Transmit Buffer Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CTXBSA |Current Transmit Buffer Start Address + * | | |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently + * | | |The CTXBSA is read only and write to this register has no effect. + * @var EMAC_T::CRXDSA + * Offset: 0xD4 Current Receive Descriptor Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRXDSA |Current Receive Descriptor Start Address + * | | |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently + * | | |The CRXDSA is read only and write to this register has no effect. + * @var EMAC_T::CRXBSA + * Offset: 0xD8 Current Receive Buffer Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRXBSA |Current Receive Buffer Start Address + * | | |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently + * | | |The CRXBSA is read only and write to this register has no effect. + * @var EMAC_T::TSCTL + * Offset: 0x100 Time Stamp Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TSEN |Time Stamp Function Enable Bit + * | | |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not. + * | | |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low + * | | |to disable IEEE 1588 PTP time stamp function. + * | | |0 = I EEE 1588 PTP time stamp function Disabled. + * | | |1 = IEEE 1588 PTP time stamp function Enabled. + * |[1] |TSIEN |Time Stamp Counter Initialization Enable Bit + * | | |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC + * | | |and EMAC_UPDSUBSEC to PTP time stamp counter. + * | | |After the load operation finished, Ethernet MAC controller clear this bit to low automatically. + * | | |0 = Time stamp counter initialization done. + * | | |1 = Time stamp counter initialization Enabled. + * |[2] |TSMODE |Time Stamp Fine Update Enable Bit + * | | |This bit chooses the time stamp counter update mode. + * | | |0 = Time stamp counter is in coarse update mode. + * | | |1 = Time stamp counter is in fine update mode. + * |[3] |TSUPDATE |Time Stamp Counter Time Update Enable Bit + * | | |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and + * | | |EMAC_UPDSUBSEC to PTP time stamp counter. + * | | |After the add operation finished, Ethernet MAC controller clear this bit to low automatically. + * | | |0 = No action. + * | | |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC. + * |[5] |TSALMEN |Time Stamp Alarm Enable Bit + * | | |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when + * | | |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * | | |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * | | |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * @var EMAC_T::TSSEC + * Offset: 0x110 Time Stamp Counter Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second + * | | |This register reflects the bit [63:32] value of 64-bit reference timing counter + * | | |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. + * @var EMAC_T::TSSUBSEC + * Offset: 0x114 Time Stamp Counter Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second + * | | |This register reflects the bit [31:0] value of 64-bit reference timing counter + * | | |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. + * @var EMAC_T::TSINC + * Offset: 0x118 Time Stamp Increment Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNTINC |Time Stamp Counter Increment + * | | |Time stamp counter increment value. + * | | |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every + * | | |time when it wants to increase the EMAC_TSSUBSEC value. + * @var EMAC_T::TSADDEND + * Offset: 0x11C Time Stamp Addend Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDEND |Time Stamp Counter Addend + * | | |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC. + * | | |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator + * | | |with this 32-bit value in each HCLK + * | | |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit + * | | |value kept in register EMAC_TSINC. + * @var EMAC_T::UPDSEC + * Offset: 0x120 Time Stamp Update Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second Update + * | | |When TSIEN (EMAC_TSCTL[1]) is high + * | | |EMAC loads this 32-bit value to EMAC_TSSEC directly + * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value. + * @var EMAC_T::UPDSUBSEC + * Offset: 0x124 Time Stamp Update Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Update + * | | |When TSIEN (EMAC_TSCTL[1]) is high + * | | |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly + * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value. + * @var EMAC_T::ALMSEC + * Offset: 0x128 Time Stamp Alarm Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second Alarm + * | | |Time stamp counter second part alarm value. + * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high + * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to + * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. + * @var EMAC_T::ALMSUBSEC + * Offset: 0x12C Time Stamp Alarm Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Alarm + * | | |Time stamp counter sub-second part alarm value. + * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high + * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to + * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. + */ + __IO uint32_t CAMCTL; /*!< [0x0000] CAM Comparison Control Register */ + __IO uint32_t CAMEN; /*!< [0x0004] CAM Enable Register */ + __IO uint32_t CAM0M; /*!< [0x0008] CAM0 Most Significant Word Register */ + __IO uint32_t CAM0L; /*!< [0x000c] CAM0 Least Significant Word Register */ + __IO uint32_t CAM1M; /*!< [0x0010] CAM1 Most Significant Word Register */ + __IO uint32_t CAM1L; /*!< [0x0014] CAM1 Least Significant Word Register */ + __IO uint32_t CAM2M; /*!< [0x0018] CAM2 Most Significant Word Register */ + __IO uint32_t CAM2L; /*!< [0x001c] CAM2 Least Significant Word Register */ + __IO uint32_t CAM3M; /*!< [0x0020] CAM3 Most Significant Word Register */ + __IO uint32_t CAM3L; /*!< [0x0024] CAM3 Least Significant Word Register */ + __IO uint32_t CAM4M; /*!< [0x0028] CAM4 Most Significant Word Register */ + __IO uint32_t CAM4L; /*!< [0x002c] CAM4 Least Significant Word Register */ + __IO uint32_t CAM5M; /*!< [0x0030] CAM5 Most Significant Word Register */ + __IO uint32_t CAM5L; /*!< [0x0034] CAM5 Least Significant Word Register */ + __IO uint32_t CAM6M; /*!< [0x0038] CAM6 Most Significant Word Register */ + __IO uint32_t CAM6L; /*!< [0x003c] CAM6 Least Significant Word Register */ + __IO uint32_t CAM7M; /*!< [0x0040] CAM7 Most Significant Word Register */ + __IO uint32_t CAM7L; /*!< [0x0044] CAM7 Least Significant Word Register */ + __IO uint32_t CAM8M; /*!< [0x0048] CAM8 Most Significant Word Register */ + __IO uint32_t CAM8L; /*!< [0x004c] CAM8 Least Significant Word Register */ + __IO uint32_t CAM9M; /*!< [0x0050] CAM9 Most Significant Word Register */ + __IO uint32_t CAM9L; /*!< [0x0054] CAM9 Least Significant Word Register */ + __IO uint32_t CAM10M; /*!< [0x0058] CAM10 Most Significant Word Register */ + __IO uint32_t CAM10L; /*!< [0x005c] CAM10 Least Significant Word Register */ + __IO uint32_t CAM11M; /*!< [0x0060] CAM11 Most Significant Word Register */ + __IO uint32_t CAM11L; /*!< [0x0064] CAM11 Least Significant Word Register */ + __IO uint32_t CAM12M; /*!< [0x0068] CAM12 Most Significant Word Register */ + __IO uint32_t CAM12L; /*!< [0x006c] CAM12 Least Significant Word Register */ + __IO uint32_t CAM13M; /*!< [0x0070] CAM13 Most Significant Word Register */ + __IO uint32_t CAM13L; /*!< [0x0074] CAM13 Least Significant Word Register */ + __IO uint32_t CAM14M; /*!< [0x0078] CAM14 Most Significant Word Register */ + __IO uint32_t CAM14L; /*!< [0x007c] CAM14 Least Significant Word Register */ + __IO uint32_t CAM15MSB; /*!< [0x0080] CAM15 Most Significant Word Register */ + __IO uint32_t CAM15LSB; /*!< [0x0084] CAM15 Least Significant Word Register */ + __IO uint32_t TXDSA; /*!< [0x0088] Transmit Descriptor Link List Start Address Register */ + __IO uint32_t RXDSA; /*!< [0x008c] Receive Descriptor Link List Start Address Register */ + __IO uint32_t CTL; /*!< [0x0090] MAC Control Register */ + __IO uint32_t MIIMDAT; /*!< [0x0094] MII Management Data Register */ + __IO uint32_t MIIMCTL; /*!< [0x0098] MII Management Control and Address Register */ + __IO uint32_t FIFOCTL; /*!< [0x009c] FIFO Threshold Control Register */ + __O uint32_t TXST; /*!< [0x00a0] Transmit Start Demand Register */ + __O uint32_t RXST; /*!< [0x00a4] Receive Start Demand Register */ + __IO uint32_t MRFL; /*!< [0x00a8] Maximum Receive Frame Control Register */ + __IO uint32_t INTEN; /*!< [0x00ac] MAC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x00b0] MAC Interrupt Status Register */ + __IO uint32_t GENSTS; /*!< [0x00b4] MAC General Status Register */ + __IO uint32_t MPCNT; /*!< [0x00b8] Missed Packet Count Register */ + __I uint32_t RPCNT; /*!< [0x00bc] MAC Receive Pause Count Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[2]; + /** @endcond */ + __IO uint32_t FRSTS; /*!< [0x00c8] DMA Receive Frame Status Register */ + __I uint32_t CTXDSA; /*!< [0x00cc] Current Transmit Descriptor Start Address Register */ + __I uint32_t CTXBSA; /*!< [0x00d0] Current Transmit Buffer Start Address Register */ + __I uint32_t CRXDSA; /*!< [0x00d4] Current Receive Descriptor Start Address Register */ + __I uint32_t CRXBSA; /*!< [0x00d8] Current Receive Buffer Start Address Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[9]; + /** @endcond */ + __IO uint32_t TSCTL; /*!< [0x0100] Time Stamp Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[3]; + /** @endcond */ + __I uint32_t TSSEC; /*!< [0x0110] Time Stamp Counter Second Register */ + __I uint32_t TSSUBSEC; /*!< [0x0114] Time Stamp Counter Sub Second Register */ + __IO uint32_t TSINC; /*!< [0x0118] Time Stamp Increment Register */ + __IO uint32_t TSADDEND; /*!< [0x011c] Time Stamp Addend Register */ + __IO uint32_t UPDSEC; /*!< [0x0120] Time Stamp Update Second Register */ + __IO uint32_t UPDSUBSEC; /*!< [0x0124] Time Stamp Update Sub Second Register */ + __IO uint32_t ALMSEC; /*!< [0x0128] Time Stamp Alarm Second Register */ + __IO uint32_t ALMSUBSEC; /*!< [0x012c] Time Stamp Alarm Sub Second Register */ + +} EMAC_T; + +/** + @addtogroup EMAC_CONST EMAC Bit Field Definition + Constant Definitions for EMAC Controller +@{ */ + +#define EMAC_CAMCTL_AUP_Pos (0) /*!< EMAC_T::CAMCTL: AUP Position */ +#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /*!< EMAC_T::CAMCTL: AUP Mask */ + +#define EMAC_CAMCTL_AMP_Pos (1) /*!< EMAC_T::CAMCTL: AMP Position */ +#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /*!< EMAC_T::CAMCTL: AMP Mask */ + +#define EMAC_CAMCTL_ABP_Pos (2) /*!< EMAC_T::CAMCTL: ABP Position */ +#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /*!< EMAC_T::CAMCTL: ABP Mask */ + +#define EMAC_CAMCTL_COMPEN_Pos (3) /*!< EMAC_T::CAMCTL: COMPEN Position */ +#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /*!< EMAC_T::CAMCTL: COMPEN Mask */ + +#define EMAC_CAMCTL_CMPEN_Pos (4) /*!< EMAC_T::CAMCTL: CMPEN Position */ +#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /*!< EMAC_T::CAMCTL: CMPEN Mask */ + +#define EMAC_CAMEN_CAMxEN_Pos (0) /*!< EMAC_T::CAMEN: CAMxEN Position */ +#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /*!< EMAC_T::CAMEN: CAMxEN Mask */ + +#define EMAC_CAM0M_MACADDR2_Pos (0) /*!< EMAC_T::CAM0M: MACADDR2 Position */ +#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /*!< EMAC_T::CAM0M: MACADDR2 Mask */ + +#define EMAC_CAM0M_MACADDR3_Pos (8) /*!< EMAC_T::CAM0M: MACADDR3 Position */ +#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /*!< EMAC_T::CAM0M: MACADDR3 Mask */ + +#define EMAC_CAM0M_MACADDR4_Pos (16) /*!< EMAC_T::CAM0M: MACADDR4 Position */ +#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /*!< EMAC_T::CAM0M: MACADDR4 Mask */ + +#define EMAC_CAM0M_MACADDR5_Pos (24) /*!< EMAC_T::CAM0M: MACADDR5 Position */ +#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /*!< EMAC_T::CAM0M: MACADDR5 Mask */ + +#define EMAC_CAM0L_MACADDR0_Pos (16) /*!< EMAC_T::CAM0L: MACADDR0 Position */ +#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /*!< EMAC_T::CAM0L: MACADDR0 Mask */ + +#define EMAC_CAM0L_MACADDR1_Pos (24) /*!< EMAC_T::CAM0L: MACADDR1 Position */ +#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /*!< EMAC_T::CAM0L: MACADDR1 Mask */ + +#define EMAC_CAM1M_MACADDR2_Pos (0) /*!< EMAC_T::CAM1M: MACADDR2 Position */ +#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /*!< EMAC_T::CAM1M: MACADDR2 Mask */ + +#define EMAC_CAM1M_MACADDR3_Pos (8) /*!< EMAC_T::CAM1M: MACADDR3 Position */ +#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /*!< EMAC_T::CAM1M: MACADDR3 Mask */ + +#define EMAC_CAM1M_MACADDR4_Pos (16) /*!< EMAC_T::CAM1M: MACADDR4 Position */ +#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /*!< EMAC_T::CAM1M: MACADDR4 Mask */ + +#define EMAC_CAM1M_MACADDR5_Pos (24) /*!< EMAC_T::CAM1M: MACADDR5 Position */ +#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /*!< EMAC_T::CAM1M: MACADDR5 Mask */ + +#define EMAC_CAM1L_MACADDR0_Pos (16) /*!< EMAC_T::CAM1L: MACADDR0 Position */ +#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /*!< EMAC_T::CAM1L: MACADDR0 Mask */ + +#define EMAC_CAM1L_MACADDR1_Pos (24) /*!< EMAC_T::CAM1L: MACADDR1 Position */ +#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /*!< EMAC_T::CAM1L: MACADDR1 Mask */ + +#define EMAC_CAM2M_MACADDR2_Pos (0) /*!< EMAC_T::CAM2M: MACADDR2 Position */ +#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /*!< EMAC_T::CAM2M: MACADDR2 Mask */ + +#define EMAC_CAM2M_MACADDR3_Pos (8) /*!< EMAC_T::CAM2M: MACADDR3 Position */ +#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /*!< EMAC_T::CAM2M: MACADDR3 Mask */ + +#define EMAC_CAM2M_MACADDR4_Pos (16) /*!< EMAC_T::CAM2M: MACADDR4 Position */ +#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /*!< EMAC_T::CAM2M: MACADDR4 Mask */ + +#define EMAC_CAM2M_MACADDR5_Pos (24) /*!< EMAC_T::CAM2M: MACADDR5 Position */ +#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /*!< EMAC_T::CAM2M: MACADDR5 Mask */ + +#define EMAC_CAM2L_MACADDR0_Pos (16) /*!< EMAC_T::CAM2L: MACADDR0 Position */ +#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /*!< EMAC_T::CAM2L: MACADDR0 Mask */ + +#define EMAC_CAM2L_MACADDR1_Pos (24) /*!< EMAC_T::CAM2L: MACADDR1 Position */ +#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /*!< EMAC_T::CAM2L: MACADDR1 Mask */ + +#define EMAC_CAM3M_MACADDR2_Pos (0) /*!< EMAC_T::CAM3M: MACADDR2 Position */ +#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /*!< EMAC_T::CAM3M: MACADDR2 Mask */ + +#define EMAC_CAM3M_MACADDR3_Pos (8) /*!< EMAC_T::CAM3M: MACADDR3 Position */ +#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /*!< EMAC_T::CAM3M: MACADDR3 Mask */ + +#define EMAC_CAM3M_MACADDR4_Pos (16) /*!< EMAC_T::CAM3M: MACADDR4 Position */ +#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /*!< EMAC_T::CAM3M: MACADDR4 Mask */ + +#define EMAC_CAM3M_MACADDR5_Pos (24) /*!< EMAC_T::CAM3M: MACADDR5 Position */ +#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /*!< EMAC_T::CAM3M: MACADDR5 Mask */ + +#define EMAC_CAM3L_MACADDR0_Pos (16) /*!< EMAC_T::CAM3L: MACADDR0 Position */ +#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /*!< EMAC_T::CAM3L: MACADDR0 Mask */ + +#define EMAC_CAM3L_MACADDR1_Pos (24) /*!< EMAC_T::CAM3L: MACADDR1 Position */ +#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /*!< EMAC_T::CAM3L: MACADDR1 Mask */ + +#define EMAC_CAM4M_MACADDR2_Pos (0) /*!< EMAC_T::CAM4M: MACADDR2 Position */ +#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /*!< EMAC_T::CAM4M: MACADDR2 Mask */ + +#define EMAC_CAM4M_MACADDR3_Pos (8) /*!< EMAC_T::CAM4M: MACADDR3 Position */ +#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /*!< EMAC_T::CAM4M: MACADDR3 Mask */ + +#define EMAC_CAM4M_MACADDR4_Pos (16) /*!< EMAC_T::CAM4M: MACADDR4 Position */ +#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /*!< EMAC_T::CAM4M: MACADDR4 Mask */ + +#define EMAC_CAM4M_MACADDR5_Pos (24) /*!< EMAC_T::CAM4M: MACADDR5 Position */ +#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /*!< EMAC_T::CAM4M: MACADDR5 Mask */ + +#define EMAC_CAM4L_MACADDR0_Pos (16) /*!< EMAC_T::CAM4L: MACADDR0 Position */ +#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /*!< EMAC_T::CAM4L: MACADDR0 Mask */ + +#define EMAC_CAM4L_MACADDR1_Pos (24) /*!< EMAC_T::CAM4L: MACADDR1 Position */ +#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /*!< EMAC_T::CAM4L: MACADDR1 Mask */ + +#define EMAC_CAM5M_MACADDR2_Pos (0) /*!< EMAC_T::CAM5M: MACADDR2 Position */ +#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /*!< EMAC_T::CAM5M: MACADDR2 Mask */ + +#define EMAC_CAM5M_MACADDR3_Pos (8) /*!< EMAC_T::CAM5M: MACADDR3 Position */ +#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /*!< EMAC_T::CAM5M: MACADDR3 Mask */ + +#define EMAC_CAM5M_MACADDR4_Pos (16) /*!< EMAC_T::CAM5M: MACADDR4 Position */ +#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /*!< EMAC_T::CAM5M: MACADDR4 Mask */ + +#define EMAC_CAM5M_MACADDR5_Pos (24) /*!< EMAC_T::CAM5M: MACADDR5 Position */ +#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /*!< EMAC_T::CAM5M: MACADDR5 Mask */ + +#define EMAC_CAM5L_MACADDR0_Pos (16) /*!< EMAC_T::CAM5L: MACADDR0 Position */ +#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /*!< EMAC_T::CAM5L: MACADDR0 Mask */ + +#define EMAC_CAM5L_MACADDR1_Pos (24) /*!< EMAC_T::CAM5L: MACADDR1 Position */ +#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /*!< EMAC_T::CAM5L: MACADDR1 Mask */ + +#define EMAC_CAM6M_MACADDR2_Pos (0) /*!< EMAC_T::CAM6M: MACADDR2 Position */ +#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /*!< EMAC_T::CAM6M: MACADDR2 Mask */ + +#define EMAC_CAM6M_MACADDR3_Pos (8) /*!< EMAC_T::CAM6M: MACADDR3 Position */ +#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /*!< EMAC_T::CAM6M: MACADDR3 Mask */ + +#define EMAC_CAM6M_MACADDR4_Pos (16) /*!< EMAC_T::CAM6M: MACADDR4 Position */ +#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /*!< EMAC_T::CAM6M: MACADDR4 Mask */ + +#define EMAC_CAM6M_MACADDR5_Pos (24) /*!< EMAC_T::CAM6M: MACADDR5 Position */ +#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /*!< EMAC_T::CAM6M: MACADDR5 Mask */ + +#define EMAC_CAM6L_MACADDR0_Pos (16) /*!< EMAC_T::CAM6L: MACADDR0 Position */ +#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /*!< EMAC_T::CAM6L: MACADDR0 Mask */ + +#define EMAC_CAM6L_MACADDR1_Pos (24) /*!< EMAC_T::CAM6L: MACADDR1 Position */ +#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /*!< EMAC_T::CAM6L: MACADDR1 Mask */ + +#define EMAC_CAM7M_MACADDR2_Pos (0) /*!< EMAC_T::CAM7M: MACADDR2 Position */ +#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /*!< EMAC_T::CAM7M: MACADDR2 Mask */ + +#define EMAC_CAM7M_MACADDR3_Pos (8) /*!< EMAC_T::CAM7M: MACADDR3 Position */ +#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /*!< EMAC_T::CAM7M: MACADDR3 Mask */ + +#define EMAC_CAM7M_MACADDR4_Pos (16) /*!< EMAC_T::CAM7M: MACADDR4 Position */ +#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /*!< EMAC_T::CAM7M: MACADDR4 Mask */ + +#define EMAC_CAM7M_MACADDR5_Pos (24) /*!< EMAC_T::CAM7M: MACADDR5 Position */ +#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /*!< EMAC_T::CAM7M: MACADDR5 Mask */ + +#define EMAC_CAM7L_MACADDR0_Pos (16) /*!< EMAC_T::CAM7L: MACADDR0 Position */ +#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /*!< EMAC_T::CAM7L: MACADDR0 Mask */ + +#define EMAC_CAM7L_MACADDR1_Pos (24) /*!< EMAC_T::CAM7L: MACADDR1 Position */ +#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /*!< EMAC_T::CAM7L: MACADDR1 Mask */ + +#define EMAC_CAM8M_MACADDR2_Pos (0) /*!< EMAC_T::CAM8M: MACADDR2 Position */ +#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /*!< EMAC_T::CAM8M: MACADDR2 Mask */ + +#define EMAC_CAM8M_MACADDR3_Pos (8) /*!< EMAC_T::CAM8M: MACADDR3 Position */ +#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /*!< EMAC_T::CAM8M: MACADDR3 Mask */ + +#define EMAC_CAM8M_MACADDR4_Pos (16) /*!< EMAC_T::CAM8M: MACADDR4 Position */ +#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /*!< EMAC_T::CAM8M: MACADDR4 Mask */ + +#define EMAC_CAM8M_MACADDR5_Pos (24) /*!< EMAC_T::CAM8M: MACADDR5 Position */ +#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /*!< EMAC_T::CAM8M: MACADDR5 Mask */ + +#define EMAC_CAM8L_MACADDR0_Pos (16) /*!< EMAC_T::CAM8L: MACADDR0 Position */ +#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /*!< EMAC_T::CAM8L: MACADDR0 Mask */ + +#define EMAC_CAM8L_MACADDR1_Pos (24) /*!< EMAC_T::CAM8L: MACADDR1 Position */ +#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /*!< EMAC_T::CAM8L: MACADDR1 Mask */ + +#define EMAC_CAM9M_MACADDR2_Pos (0) /*!< EMAC_T::CAM9M: MACADDR2 Position */ +#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /*!< EMAC_T::CAM9M: MACADDR2 Mask */ + +#define EMAC_CAM9M_MACADDR3_Pos (8) /*!< EMAC_T::CAM9M: MACADDR3 Position */ +#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /*!< EMAC_T::CAM9M: MACADDR3 Mask */ + +#define EMAC_CAM9M_MACADDR4_Pos (16) /*!< EMAC_T::CAM9M: MACADDR4 Position */ +#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /*!< EMAC_T::CAM9M: MACADDR4 Mask */ + +#define EMAC_CAM9M_MACADDR5_Pos (24) /*!< EMAC_T::CAM9M: MACADDR5 Position */ +#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /*!< EMAC_T::CAM9M: MACADDR5 Mask */ + +#define EMAC_CAM9L_MACADDR0_Pos (16) /*!< EMAC_T::CAM9L: MACADDR0 Position */ +#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /*!< EMAC_T::CAM9L: MACADDR0 Mask */ + +#define EMAC_CAM9L_MACADDR1_Pos (24) /*!< EMAC_T::CAM9L: MACADDR1 Position */ +#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /*!< EMAC_T::CAM9L: MACADDR1 Mask */ + +#define EMAC_CAM10M_MACADDR2_Pos (0) /*!< EMAC_T::CAM10M: MACADDR2 Position */ +#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /*!< EMAC_T::CAM10M: MACADDR2 Mask */ + +#define EMAC_CAM10M_MACADDR3_Pos (8) /*!< EMAC_T::CAM10M: MACADDR3 Position */ +#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /*!< EMAC_T::CAM10M: MACADDR3 Mask */ + +#define EMAC_CAM10M_MACADDR4_Pos (16) /*!< EMAC_T::CAM10M: MACADDR4 Position */ +#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /*!< EMAC_T::CAM10M: MACADDR4 Mask */ + +#define EMAC_CAM10M_MACADDR5_Pos (24) /*!< EMAC_T::CAM10M: MACADDR5 Position */ +#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /*!< EMAC_T::CAM10M: MACADDR5 Mask */ + +#define EMAC_CAM10L_MACADDR0_Pos (16) /*!< EMAC_T::CAM10L: MACADDR0 Position */ +#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /*!< EMAC_T::CAM10L: MACADDR0 Mask */ + +#define EMAC_CAM10L_MACADDR1_Pos (24) /*!< EMAC_T::CAM10L: MACADDR1 Position */ +#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /*!< EMAC_T::CAM10L: MACADDR1 Mask */ + +#define EMAC_CAM11M_MACADDR2_Pos (0) /*!< EMAC_T::CAM11M: MACADDR2 Position */ +#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /*!< EMAC_T::CAM11M: MACADDR2 Mask */ + +#define EMAC_CAM11M_MACADDR3_Pos (8) /*!< EMAC_T::CAM11M: MACADDR3 Position */ +#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /*!< EMAC_T::CAM11M: MACADDR3 Mask */ + +#define EMAC_CAM11M_MACADDR4_Pos (16) /*!< EMAC_T::CAM11M: MACADDR4 Position */ +#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /*!< EMAC_T::CAM11M: MACADDR4 Mask */ + +#define EMAC_CAM11M_MACADDR5_Pos (24) /*!< EMAC_T::CAM11M: MACADDR5 Position */ +#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /*!< EMAC_T::CAM11M: MACADDR5 Mask */ + +#define EMAC_CAM11L_MACADDR0_Pos (16) /*!< EMAC_T::CAM11L: MACADDR0 Position */ +#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /*!< EMAC_T::CAM11L: MACADDR0 Mask */ + +#define EMAC_CAM11L_MACADDR1_Pos (24) /*!< EMAC_T::CAM11L: MACADDR1 Position */ +#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /*!< EMAC_T::CAM11L: MACADDR1 Mask */ + +#define EMAC_CAM12M_MACADDR2_Pos (0) /*!< EMAC_T::CAM12M: MACADDR2 Position */ +#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /*!< EMAC_T::CAM12M: MACADDR2 Mask */ + +#define EMAC_CAM12M_MACADDR3_Pos (8) /*!< EMAC_T::CAM12M: MACADDR3 Position */ +#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /*!< EMAC_T::CAM12M: MACADDR3 Mask */ + +#define EMAC_CAM12M_MACADDR4_Pos (16) /*!< EMAC_T::CAM12M: MACADDR4 Position */ +#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /*!< EMAC_T::CAM12M: MACADDR4 Mask */ + +#define EMAC_CAM12M_MACADDR5_Pos (24) /*!< EMAC_T::CAM12M: MACADDR5 Position */ +#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /*!< EMAC_T::CAM12M: MACADDR5 Mask */ + +#define EMAC_CAM12L_MACADDR0_Pos (16) /*!< EMAC_T::CAM12L: MACADDR0 Position */ +#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /*!< EMAC_T::CAM12L: MACADDR0 Mask */ + +#define EMAC_CAM12L_MACADDR1_Pos (24) /*!< EMAC_T::CAM12L: MACADDR1 Position */ +#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /*!< EMAC_T::CAM12L: MACADDR1 Mask */ + +#define EMAC_CAM13M_MACADDR2_Pos (0) /*!< EMAC_T::CAM13M: MACADDR2 Position */ +#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /*!< EMAC_T::CAM13M: MACADDR2 Mask */ + +#define EMAC_CAM13M_MACADDR3_Pos (8) /*!< EMAC_T::CAM13M: MACADDR3 Position */ +#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /*!< EMAC_T::CAM13M: MACADDR3 Mask */ + +#define EMAC_CAM13M_MACADDR4_Pos (16) /*!< EMAC_T::CAM13M: MACADDR4 Position */ +#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /*!< EMAC_T::CAM13M: MACADDR4 Mask */ + +#define EMAC_CAM13M_MACADDR5_Pos (24) /*!< EMAC_T::CAM13M: MACADDR5 Position */ +#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /*!< EMAC_T::CAM13M: MACADDR5 Mask */ + +#define EMAC_CAM13L_MACADDR0_Pos (16) /*!< EMAC_T::CAM13L: MACADDR0 Position */ +#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /*!< EMAC_T::CAM13L: MACADDR0 Mask */ + +#define EMAC_CAM13L_MACADDR1_Pos (24) /*!< EMAC_T::CAM13L: MACADDR1 Position */ +#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /*!< EMAC_T::CAM13L: MACADDR1 Mask */ + +#define EMAC_CAM14M_MACADDR2_Pos (0) /*!< EMAC_T::CAM14M: MACADDR2 Position */ +#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /*!< EMAC_T::CAM14M: MACADDR2 Mask */ + +#define EMAC_CAM14M_MACADDR3_Pos (8) /*!< EMAC_T::CAM14M: MACADDR3 Position */ +#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /*!< EMAC_T::CAM14M: MACADDR3 Mask */ + +#define EMAC_CAM14M_MACADDR4_Pos (16) /*!< EMAC_T::CAM14M: MACADDR4 Position */ +#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /*!< EMAC_T::CAM14M: MACADDR4 Mask */ + +#define EMAC_CAM14M_MACADDR5_Pos (24) /*!< EMAC_T::CAM14M: MACADDR5 Position */ +#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /*!< EMAC_T::CAM14M: MACADDR5 Mask */ + +#define EMAC_CAM14L_MACADDR0_Pos (16) /*!< EMAC_T::CAM14L: MACADDR0 Position */ +#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /*!< EMAC_T::CAM14L: MACADDR0 Mask */ + +#define EMAC_CAM14L_MACADDR1_Pos (24) /*!< EMAC_T::CAM14L: MACADDR1 Position */ +#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /*!< EMAC_T::CAM14L: MACADDR1 Mask */ + +#define EMAC_CAM15MSB_OPCODE_Pos (0) /*!< EMAC_T::CAM15MSB: OPCODE Position */ +#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /*!< EMAC_T::CAM15MSB: OPCODE Mask */ + +#define EMAC_CAM15MSB_LENGTH_Pos (16) /*!< EMAC_T::CAM15MSB: LENGTH Position */ +#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /*!< EMAC_T::CAM15MSB: LENGTH Mask */ + +#define EMAC_CAM15LSB_OPERAND_Pos (24) /*!< EMAC_T::CAM15LSB: OPERAND Position */ +#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /*!< EMAC_T::CAM15LSB: OPERAND Mask */ + +#define EMAC_TXDSA_TXDSA_Pos (0) /*!< EMAC_T::TXDSA: TXDSA Position */ +#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /*!< EMAC_T::TXDSA: TXDSA Mask */ + +#define EMAC_RXDSA_RXDSA_Pos (0) /*!< EMAC_T::RXDSA: RXDSA Position */ +#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /*!< EMAC_T::RXDSA: RXDSA Mask */ + +#define EMAC_CTL_RXON_Pos (0) /*!< EMAC_T::CTL: RXON Position */ +#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /*!< EMAC_T::CTL: RXON Mask */ + +#define EMAC_CTL_ALP_Pos (1) /*!< EMAC_T::CTL: ALP Position */ +#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /*!< EMAC_T::CTL: ALP Mask */ + +#define EMAC_CTL_ARP_Pos (2) /*!< EMAC_T::CTL: ARP Position */ +#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /*!< EMAC_T::CTL: ARP Mask */ + +#define EMAC_CTL_ACP_Pos (3) /*!< EMAC_T::CTL: ACP Position */ +#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /*!< EMAC_T::CTL: ACP Mask */ + +#define EMAC_CTL_AEP_Pos (4) /*!< EMAC_T::CTL: AEP Position */ +#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /*!< EMAC_T::CTL: AEP Mask */ + +#define EMAC_CTL_STRIPCRC_Pos (5) /*!< EMAC_T::CTL: STRIPCRC Position */ +#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /*!< EMAC_T::CTL: STRIPCRC Mask */ + +#define EMAC_CTL_WOLEN_Pos (6) /*!< EMAC_T::CTL: WOLEN Position */ +#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /*!< EMAC_T::CTL: WOLEN Mask */ + +#define EMAC_CTL_TXON_Pos (8) /*!< EMAC_T::CTL: TXON Position */ +#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /*!< EMAC_T::CTL: TXON Mask */ + +#define EMAC_CTL_NODEF_Pos (9) /*!< EMAC_T::CTL: NODEF Position */ +#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /*!< EMAC_T::CTL: NODEF Mask */ + +#define EMAC_CTL_SDPZ_Pos (16) /*!< EMAC_T::CTL: SDPZ Position */ +#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /*!< EMAC_T::CTL: SDPZ Mask */ + +#define EMAC_CTL_SQECHKEN_Pos (17) /*!< EMAC_T::CTL: SQECHKEN Position */ +#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /*!< EMAC_T::CTL: SQECHKEN Mask */ + +#define EMAC_CTL_FUDUP_Pos (18) /*!< EMAC_T::CTL: FUDUP Position */ +#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /*!< EMAC_T::CTL: FUDUP Mask */ + +#define EMAC_CTL_RMIIRXCTL_Pos (19) /*!< EMAC_T::CTL: RMIIRXCTL Position */ +#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /*!< EMAC_T::CTL: RMIIRXCTL Mask */ + +#define EMAC_CTL_OPMODE_Pos (20) /*!< EMAC_T::CTL: OPMODE Position */ +#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /*!< EMAC_T::CTL: OPMODE Mask */ + +#define EMAC_CTL_RMIIEN_Pos (22) /*!< EMAC_T::CTL: RMIIEN Position */ +#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /*!< EMAC_T::CTL: RMIIEN Mask */ + +#define EMAC_CTL_RST_Pos (24) /*!< EMAC_T::CTL: RST Position */ +#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /*!< EMAC_T::CTL: RST Mask */ + +#define EMAC_MIIMDAT_DATA_Pos (0) /*!< EMAC_T::MIIMDAT: DATA Position */ +#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /*!< EMAC_T::MIIMDAT: DATA Mask */ + +#define EMAC_MIIMCTL_PHYREG_Pos (0) /*!< EMAC_T::MIIMCTL: PHYREG Position */ +#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /*!< EMAC_T::MIIMCTL: PHYREG Mask */ + +#define EMAC_MIIMCTL_PHYADDR_Pos (8) /*!< EMAC_T::MIIMCTL: PHYADDR Position */ +#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /*!< EMAC_T::MIIMCTL: PHYADDR Mask */ + +#define EMAC_MIIMCTL_WRITE_Pos (16) /*!< EMAC_T::MIIMCTL: WRITE Position */ +#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /*!< EMAC_T::MIIMCTL: WRITE Mask */ + +#define EMAC_MIIMCTL_BUSY_Pos (17) /*!< EMAC_T::MIIMCTL: BUSY Position */ +#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /*!< EMAC_T::MIIMCTL: BUSY Mask */ + +#define EMAC_MIIMCTL_PREAMSP_Pos (18) /*!< EMAC_T::MIIMCTL: PREAMSP Position */ +#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /*!< EMAC_T::MIIMCTL: PREAMSP Mask */ + +#define EMAC_MIIMCTL_MDCON_Pos (19) /*!< EMAC_T::MIIMCTL: MDCON Position */ +#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /*!< EMAC_T::MIIMCTL: MDCON Mask */ + +#define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /*!< EMAC_T::FIFOCTL: RXFIFOTH Position */ +#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: RXFIFOTH Mask */ + +#define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /*!< EMAC_T::FIFOCTL: TXFIFOTH Position */ +#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: TXFIFOTH Mask */ + +#define EMAC_FIFOCTL_BURSTLEN_Pos (20) /*!< EMAC_T::FIFOCTL: BURSTLEN Position */ +#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /*!< EMAC_T::FIFOCTL: BURSTLEN Mask */ + +#define EMAC_TXST_TXST_Pos (0) /*!< EMAC_T::TXST: TXST Position */ +#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /*!< EMAC_T::TXST: TXST Mask */ + +#define EMAC_RXST_RXST_Pos (0) /*!< EMAC_T::RXST: RXST Position */ +#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /*!< EMAC_T::RXST: RXST Mask */ + +#define EMAC_MRFL_MRFL_Pos (0) /*!< EMAC_T::MRFL: MRFL Position */ +#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /*!< EMAC_T::MRFL: MRFL Mask */ + +#define EMAC_INTEN_RXIEN_Pos (0) /*!< EMAC_T::INTEN: RXIEN Position */ +#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /*!< EMAC_T::INTEN: RXIEN Mask */ + +#define EMAC_INTEN_CRCEIEN_Pos (1) /*!< EMAC_T::INTEN: CRCEIEN Position */ +#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /*!< EMAC_T::INTEN: CRCEIEN Mask */ + +#define EMAC_INTEN_RXOVIEN_Pos (2) /*!< EMAC_T::INTEN: RXOVIEN Position */ +#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /*!< EMAC_T::INTEN: RXOVIEN Mask */ + +#define EMAC_INTEN_LPIEN_Pos (3) /*!< EMAC_T::INTEN: LPIEN Position */ +#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /*!< EMAC_T::INTEN: LPIEN Mask */ + +#define EMAC_INTEN_RXGDIEN_Pos (4) /*!< EMAC_T::INTEN: RXGDIEN Position */ +#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /*!< EMAC_T::INTEN: RXGDIEN Mask */ + +#define EMAC_INTEN_ALIEIEN_Pos (5) /*!< EMAC_T::INTEN: ALIEIEN Position */ +#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /*!< EMAC_T::INTEN: ALIEIEN Mask */ + +#define EMAC_INTEN_RPIEN_Pos (6) /*!< EMAC_T::INTEN: RPIEN Position */ +#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /*!< EMAC_T::INTEN: RPIEN Mask */ + +#define EMAC_INTEN_MPCOVIEN_Pos (7) /*!< EMAC_T::INTEN: MPCOVIEN Position */ +#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /*!< EMAC_T::INTEN: MPCOVIEN Mask */ + +#define EMAC_INTEN_MFLEIEN_Pos (8) /*!< EMAC_T::INTEN: MFLEIEN Position */ +#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /*!< EMAC_T::INTEN: MFLEIEN Mask */ + +#define EMAC_INTEN_DENIEN_Pos (9) /*!< EMAC_T::INTEN: DENIEN Position */ +#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /*!< EMAC_T::INTEN: DENIEN Mask */ + +#define EMAC_INTEN_RDUIEN_Pos (10) /*!< EMAC_T::INTEN: RDUIEN Position */ +#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /*!< EMAC_T::INTEN: RDUIEN Mask */ + +#define EMAC_INTEN_RXBEIEN_Pos (11) /*!< EMAC_T::INTEN: RXBEIEN Position */ +#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /*!< EMAC_T::INTEN: RXBEIEN Mask */ + +#define EMAC_INTEN_CFRIEN_Pos (14) /*!< EMAC_T::INTEN: CFRIEN Position */ +#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /*!< EMAC_T::INTEN: CFRIEN Mask */ + +#define EMAC_INTEN_WOLIEN_Pos (15) /*!< EMAC_T::INTEN: WOLIEN Position */ +#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /*!< EMAC_T::INTEN: WOLIEN Mask */ + +#define EMAC_INTEN_TXIEN_Pos (16) /*!< EMAC_T::INTEN: TXIEN Position */ +#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /*!< EMAC_T::INTEN: TXIEN Mask */ + +#define EMAC_INTEN_TXUDIEN_Pos (17) /*!< EMAC_T::INTEN: TXUDIEN Position */ +#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /*!< EMAC_T::INTEN: TXUDIEN Mask */ + +#define EMAC_INTEN_TXCPIEN_Pos (18) /*!< EMAC_T::INTEN: TXCPIEN Position */ +#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /*!< EMAC_T::INTEN: TXCPIEN Mask */ + +#define EMAC_INTEN_EXDEFIEN_Pos (19) /*!< EMAC_T::INTEN: EXDEFIEN Position */ +#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /*!< EMAC_T::INTEN: EXDEFIEN Mask */ + +#define EMAC_INTEN_NCSIEN_Pos (20) /*!< EMAC_T::INTEN: NCSIEN Position */ +#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /*!< EMAC_T::INTEN: NCSIEN Mask */ + +#define EMAC_INTEN_TXABTIEN_Pos (21) /*!< EMAC_T::INTEN: TXABTIEN Position */ +#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /*!< EMAC_T::INTEN: TXABTIEN Mask */ + +#define EMAC_INTEN_LCIEN_Pos (22) /*!< EMAC_T::INTEN: LCIEN Position */ +#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /*!< EMAC_T::INTEN: LCIEN Mask */ + +#define EMAC_INTEN_TDUIEN_Pos (23) /*!< EMAC_T::INTEN: TDUIEN Position */ +#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /*!< EMAC_T::INTEN: TDUIEN Mask */ + +#define EMAC_INTEN_TXBEIEN_Pos (24) /*!< EMAC_T::INTEN: TXBEIEN Position */ +#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /*!< EMAC_T::INTEN: TXBEIEN Mask */ + +#define EMAC_INTEN_TSALMIEN_Pos (28) /*!< EMAC_T::INTEN: TSALMIEN Position */ +#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /*!< EMAC_T::INTEN: TSALMIEN Mask */ + +#define EMAC_INTSTS_RXIF_Pos (0) /*!< EMAC_T::INTSTS: RXIF Position */ +#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /*!< EMAC_T::INTSTS: RXIF Mask */ + +#define EMAC_INTSTS_CRCEIF_Pos (1) /*!< EMAC_T::INTSTS: CRCEIF Position */ +#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /*!< EMAC_T::INTSTS: CRCEIF Mask */ + +#define EMAC_INTSTS_RXOVIF_Pos (2) /*!< EMAC_T::INTSTS: RXOVIF Position */ +#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /*!< EMAC_T::INTSTS: RXOVIF Mask */ + +#define EMAC_INTSTS_LPIF_Pos (3) /*!< EMAC_T::INTSTS: LPIF Position */ +#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /*!< EMAC_T::INTSTS: LPIF Mask */ + +#define EMAC_INTSTS_RXGDIF_Pos (4) /*!< EMAC_T::INTSTS: RXGDIF Position */ +#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /*!< EMAC_T::INTSTS: RXGDIF Mask */ + +#define EMAC_INTSTS_ALIEIF_Pos (5) /*!< EMAC_T::INTSTS: ALIEIF Position */ +#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /*!< EMAC_T::INTSTS: ALIEIF Mask */ + +#define EMAC_INTSTS_RPIF_Pos (6) /*!< EMAC_T::INTSTS: RPIF Position */ +#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /*!< EMAC_T::INTSTS: RPIF Mask */ + +#define EMAC_INTSTS_MPCOVIF_Pos (7) /*!< EMAC_T::INTSTS: MPCOVIF Position */ +#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /*!< EMAC_T::INTSTS: MPCOVIF Mask */ + +#define EMAC_INTSTS_MFLEIF_Pos (8) /*!< EMAC_T::INTSTS: MFLEIF Position */ +#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /*!< EMAC_T::INTSTS: MFLEIF Mask */ + +#define EMAC_INTSTS_DENIF_Pos (9) /*!< EMAC_T::INTSTS: DENIF Position */ +#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /*!< EMAC_T::INTSTS: DENIF Mask */ + +#define EMAC_INTSTS_RDUIF_Pos (10) /*!< EMAC_T::INTSTS: RDUIF Position */ +#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /*!< EMAC_T::INTSTS: RDUIF Mask */ + +#define EMAC_INTSTS_RXBEIF_Pos (11) /*!< EMAC_T::INTSTS: RXBEIF Position */ +#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /*!< EMAC_T::INTSTS: RXBEIF Mask */ + +#define EMAC_INTSTS_CFRIF_Pos (14) /*!< EMAC_T::INTSTS: CFRIF Position */ +#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /*!< EMAC_T::INTSTS: CFRIF Mask */ + +#define EMAC_INTSTS_WOLIF_Pos (15) /*!< EMAC_T::INTSTS: WOLIF Position */ +#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /*!< EMAC_T::INTSTS: WOLIF Mask */ + +#define EMAC_INTSTS_TXIF_Pos (16) /*!< EMAC_T::INTSTS: TXIF Position */ +#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /*!< EMAC_T::INTSTS: TXIF Mask */ + +#define EMAC_INTSTS_TXUDIF_Pos (17) /*!< EMAC_T::INTSTS: TXUDIF Position */ +#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /*!< EMAC_T::INTSTS: TXUDIF Mask */ + +#define EMAC_INTSTS_TXCPIF_Pos (18) /*!< EMAC_T::INTSTS: TXCPIF Position */ +#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /*!< EMAC_T::INTSTS: TXCPIF Mask */ + +#define EMAC_INTSTS_EXDEFIF_Pos (19) /*!< EMAC_T::INTSTS: EXDEFIF Position */ +#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /*!< EMAC_T::INTSTS: EXDEFIF Mask */ + +#define EMAC_INTSTS_NCSIF_Pos (20) /*!< EMAC_T::INTSTS: NCSIF Position */ +#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /*!< EMAC_T::INTSTS: NCSIF Mask */ + +#define EMAC_INTSTS_TXABTIF_Pos (21) /*!< EMAC_T::INTSTS: TXABTIF Position */ +#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /*!< EMAC_T::INTSTS: TXABTIF Mask */ + +#define EMAC_INTSTS_LCIF_Pos (22) /*!< EMAC_T::INTSTS: LCIF Position */ +#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /*!< EMAC_T::INTSTS: LCIF Mask */ + +#define EMAC_INTSTS_TDUIF_Pos (23) /*!< EMAC_T::INTSTS: TDUIF Position */ +#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /*!< EMAC_T::INTSTS: TDUIF Mask */ + +#define EMAC_INTSTS_TXBEIF_Pos (24) /*!< EMAC_T::INTSTS: TXBEIF Position */ +#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /*!< EMAC_T::INTSTS: TXBEIF Mask */ + +#define EMAC_INTSTS_TSALMIF_Pos (28) /*!< EMAC_T::INTSTS: TSALMIF Position */ +#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /*!< EMAC_T::INTSTS: TSALMIF Mask */ + +#define EMAC_GENSTS_CFR_Pos (0) /*!< EMAC_T::GENSTS: CFR Position */ +#define EMAC_GENSTS_CFR_Msk (0x1ul << EMAC_GENSTS_CFR_Pos) /*!< EMAC_T::GENSTS: CFR Mask */ + +#define EMAC_GENSTS_RXHALT_Pos (1) /*!< EMAC_T::GENSTS: RXHALT Position */ +#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /*!< EMAC_T::GENSTS: RXHALT Mask */ + +#define EMAC_GENSTS_RXFFULL_Pos (2) /*!< EMAC_T::GENSTS: RXFFULL Position */ +#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /*!< EMAC_T::GENSTS: RXFFULL Mask */ + +#define EMAC_GENSTS_COLCNT_Pos (4) /*!< EMAC_T::GENSTS: COLCNT Position */ +#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /*!< EMAC_T::GENSTS: COLCNT Mask */ + +#define EMAC_GENSTS_DEF_Pos (8) /*!< EMAC_T::GENSTS: DEF Position */ +#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /*!< EMAC_T::GENSTS: DEF Mask */ + +#define EMAC_GENSTS_TXPAUSED_Pos (9) /*!< EMAC_T::GENSTS: TXPAUSED Position */ +#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /*!< EMAC_T::GENSTS: TXPAUSED Mask */ + +#define EMAC_GENSTS_SQE_Pos (10) /*!< EMAC_T::GENSTS: SQE Position */ +#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /*!< EMAC_T::GENSTS: SQE Mask */ + +#define EMAC_GENSTS_TXHALT_Pos (11) /*!< EMAC_T::GENSTS: TXHALT Position */ +#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /*!< EMAC_T::GENSTS: TXHALT Mask */ + +#define EMAC_GENSTS_RPSTS_Pos (12) /*!< EMAC_T::GENSTS: RPSTS Position */ +#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /*!< EMAC_T::GENSTS: RPSTS Mask */ + +#define EMAC_MPCNT_MPCNT_Pos (0) /*!< EMAC_T::MPCNT: MPCNT Position */ +#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /*!< EMAC_T::MPCNT: MPCNT Mask */ + +#define EMAC_RPCNT_RPCNT_Pos (0) /*!< EMAC_T::RPCNT: RPCNT Position */ +#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /*!< EMAC_T::RPCNT: RPCNT Mask */ + +#define EMAC_FRSTS_RXFLT_Pos (0) /*!< EMAC_T::FRSTS: RXFLT Position */ +#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /*!< EMAC_T::FRSTS: RXFLT Mask */ + +#define EMAC_CTXDSA_CTXDSA_Pos (0) /*!< EMAC_T::CTXDSA: CTXDSA Position */ +#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /*!< EMAC_T::CTXDSA: CTXDSA Mask */ + +#define EMAC_CTXBSA_CTXBSA_Pos (0) /*!< EMAC_T::CTXBSA: CTXBSA Position */ +#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /*!< EMAC_T::CTXBSA: CTXBSA Mask */ + +#define EMAC_CRXDSA_CRXDSA_Pos (0) /*!< EMAC_T::CRXDSA: CRXDSA Position */ +#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /*!< EMAC_T::CRXDSA: CRXDSA Mask */ + +#define EMAC_CRXBSA_CRXBSA_Pos (0) /*!< EMAC_T::CRXBSA: CRXBSA Position */ +#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /*!< EMAC_T::CRXBSA: CRXBSA Mask */ + +#define EMAC_TSCTL_TSEN_Pos (0) /*!< EMAC_T::TSCTL: TSEN Position */ +#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /*!< EMAC_T::TSCTL: TSEN Mask */ + +#define EMAC_TSCTL_TSIEN_Pos (1) /*!< EMAC_T::TSCTL: TSIEN Position */ +#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /*!< EMAC_T::TSCTL: TSIEN Mask */ + +#define EMAC_TSCTL_TSMODE_Pos (2) /*!< EMAC_T::TSCTL: TSMODE Position */ +#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /*!< EMAC_T::TSCTL: TSMODE Mask */ + +#define EMAC_TSCTL_TSUPDATE_Pos (3) /*!< EMAC_T::TSCTL: TSUPDATE Position */ +#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /*!< EMAC_T::TSCTL: TSUPDATE Mask */ + +#define EMAC_TSCTL_TSALMEN_Pos (5) /*!< EMAC_T::TSCTL: TSALMEN Position */ +#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /*!< EMAC_T::TSCTL: TSALMEN Mask */ + +#define EMAC_TSSEC_SEC_Pos (0) /*!< EMAC_T::TSSEC: SEC Position */ +#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /*!< EMAC_T::TSSEC: SEC Mask */ + +#define EMAC_TSSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::TSSUBSEC: SUBSEC Position */ +#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /*!< EMAC_T::TSSUBSEC: SUBSEC Mask */ + +#define EMAC_TSINC_CNTINC_Pos (0) /*!< EMAC_T::TSINC: CNTINC Position */ +#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /*!< EMAC_T::TSINC: CNTINC Mask */ + +#define EMAC_TSADDEND_ADDEND_Pos (0) /*!< EMAC_T::TSADDEND: ADDEND Position */ +#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /*!< EMAC_T::TSADDEND: ADDEND Mask */ + +#define EMAC_UPDSEC_SEC_Pos (0) /*!< EMAC_T::UPDSEC: SEC Position */ +#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /*!< EMAC_T::UPDSEC: SEC Mask */ + +#define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::UPDSUBSEC: SUBSEC Position */ +#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /*!< EMAC_T::UPDSUBSEC: SUBSEC Mask */ + +#define EMAC_ALMSEC_SEC_Pos (0) /*!< EMAC_T::ALMSEC: SEC Position */ +#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /*!< EMAC_T::ALMSEC: SEC Mask */ + +#define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::ALMSUBSEC: SUBSEC Position */ +#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /*!< EMAC_T::ALMSUBSEC: SUBSEC Mask */ + +/**@}*/ /* EMAC_CONST */ +/**@}*/ /* end of EMAC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EMAC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/epwm_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/epwm_reg.h new file mode 100644 index 00000000000..ffd4735cac4 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/epwm_reg.h @@ -0,0 +1,3755 @@ +/**************************************************************************//** + * @file epwm_reg.h + * @version V1.00 + * @brief EPWM register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_REG_H__ +#define __EPWM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EPWM Pulse Width Modulation Controller(EPWM) + Memory Mapped Structure for EPWM Controller +@{ */ + +typedef struct +{ + /** + * @var ECAPDAT_T::RCAPDAT + * Offset: 0x20C EPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var ECAPDAT_T::FCAPDAT + * Offset: 0x210 EPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ +} ECAPDAT_T; + +typedef struct +{ + + + /** + * @var EPWM_T::CTL0 + * Offset: 0x00 EPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[8] |WINLDEN0 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[9] |WINLDEN1 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[10] |WINLDEN2 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[11] |WINLDEN3 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[12] |WINLDEN4 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[13] |WINLDEN5 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[16] |IMMLDEN0 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[24] |GROUPEN |Group Function Enable Bit(S) + * | | |0 = The output waveform of each EPWM channel are independent. + * | | |1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects EPWM output. + * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::CTL1 + * Offset: 0x04 EPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[16] |CNTMODE0 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[17] |CNTMODE1 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[18] |CNTMODE2 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[19] |CNTMODE3 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[20] |CNTMODE4 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[21] |CNTMODE5 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[24] |OUTMODE0 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[25] |OUTMODE2 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[26] |OUTMODE4 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * @var EPWM_T::SYNC + * Offset: 0x08 EPWM Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PHSEN0 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[1] |PHSEN2 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[2] |PHSEN4 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits + * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled. + * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled. + * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count + * | | |The register bits control the counter number of edge detector. + * |[23] |SINPINV |SYNC Input Pin Inverse + * | | |0 = The state of pin SYNC is passed to the negative edge detector. + * | | |1 = The inversed state of pin SYNC is passed to the negative edge detector. + * |[24] |PHSDIR0 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[25] |PHSDIR2 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[26] |PHSDIR4 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * @var EPWM_T::SWSYNC + * Offset: 0x0C EPWM Software Control Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWSYNC0 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * |[1] |SWSYNC2 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * |[2] |SWSYNC4 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * @var EPWM_T::CLKSRC + * Offset: 0x10 EPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var EPWM_T::CLKPSC[3] + * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair share one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CNTEN + * Offset: 0x20 EPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[1] |CNTEN1 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[2] |CNTEN2 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[3] |CNTEN3 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[4] |CNTEN4 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[5] |CNTEN5 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * @var EPWM_T::CNTCLR + * Offset: 0x24 EPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * @var EPWM_T::LOAD + * Offset: 0x28 EPWM Load Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * @var EPWM_T::PERIOD[6] + * Offset: 0x30 EPWM Period Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period. + * @var EPWM_T::CMPDAT[6] + * Offset: 0x50 EPWM Comparator Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::DTCTL[3] + * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect) + * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from EPWM_CLK. + * | | |1 = Dead-time clock source from prescaler output. + * | | |Note: This register is write protected. Refer toREGWRPROT register. + * @var EPWM_T::PHS[3] + * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PHS |EPWM Synchronous Start Phase Bits + * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. + * @var EPWM_T::CNT[6] + * Offset: 0x90 EPWM Counter Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var EPWM_T::WGCTL0 + * Offset: 0xB0 EPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[3:2] |ZPCTL1 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[5:4] |ZPCTL2 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[7:6] |ZPCTL3 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[9:8] |ZPCTL4 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[11:10] |ZPCTL5 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIODn+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * @var EPWM_T::WGCTL1 + * Offset: 0xB4 EPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * @var EPWM_T::MSKEN + * Offset: 0xB8 EPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * @var EPWM_T::MSK + * Offset: 0xBC EPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[1] |MSKDAT1 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[2] |MSKDAT2 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[3] |MSKDAT3 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[4] |MSKDAT4 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[5] |MSKDAT5 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * @var EPWM_T::BNF + * Offset: 0xC0 EPWM Brake Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 0 Disabled. + * | | |1 = Noise filter of EPWM Brake 0 Enabled. + * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count + * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. + * |[7] |BRK0PINV |Brake 0 Pin Inverse + * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector. + * | | |1 = The inversed state of pin EPWMx_BRAKE10 is passed to the negative edge detector. + * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 1 Disabled. + * | | |1 = Noise filter of EPWM Brake 1 Enabled. + * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count + * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. + * |[15] |BRK1PINV |Brake 1 Pin Inverse + * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector. + * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector. + * |[16] |BK0SRC |Brake 0 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |For EPWM1 setting: + * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. + * |[24] |BK1SRC |Brake 1 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |For EPWM1 setting: + * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. + * @var EPWM_T::FAILBRK + * Offset: 0xC4 EPWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by CSS detection Disabled. + * | | |1 = Brake Function triggered by CSS detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by BOD Disabled. + * | | |1 = Brake Function triggered by BOD Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by Core lockup detection Disabled. + * | | |1 = Brake Function triggered by Core lockup detection Enabled. + * @var EPWM_T::BRKCTL[3] + * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as edge-detect brake source Disabled. + * | | |1 = ACMP0_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as edge-detect brake source Disabled. + * | | |1 = ACMP1_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as edge-detect brake source Disabled. + * | | |1 = System Fail condition as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as level-detect brake source Disabled. + * | | |1 = ACMP0_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as level-detect brake source Disabled. + * | | |1 = ACMP1_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as level-detect brake source Disabled. + * | | |1 = System Fail condition as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect even channels output. + * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM even channel output low level when EPWMx brake event happened. + * | | |11 = EPWM even channel output high level when EPWMx brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect odd channels output. + * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. + * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect) + * | | |0 = EADCRM as edge-detect brake source Disabled. + * | | |1 = EADCRM as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect) + * | | |0 = EADCRM as level-detect brake source Disabled. + * | | |1 = EADCRM as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::POLCTL + * Offset: 0xD4 EPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[1] |PINV1 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[2] |PINV2 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[3] |PINV3 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[4] |PINV4 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * |[5] |PINV5 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM output. + * | | |0 = EPWM output polar inverse Disabled. + * | | |1 = EPWM output polar inverse Enabled. + * @var EPWM_T::POEN + * Offset: 0xD8 EPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[1] |POEN1 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[2] |POEN2 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[3] |POEN3 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[4] |POEN4 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * |[5] |POEN5 |EPWM Pin Output Enable Bits + * | | |0 = EPWM pin at tri-state. + * | | |1 = EPWM pin in output mode. + * @var EPWM_T::SWBRK + * Offset: 0xDC EPWM Software Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::INTEN0 + * Offset: 0xE0 EPWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * @var EPWM_T::INTEN1 + * Offset: 0xE4 EPWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::INTSTS0 + * Offset: 0xE8 EPWM Interrupt Flag Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[9] |PIF1 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[10] |PIF2 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[11] |PIF3 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[12] |PIF4 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[13] |PIF5 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * @var EPWM_T::INTSTS1 + * Offset: 0xEC EPWM Interrupt Flag Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 edge-detect brake event do not happened. + * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 edge-detect brake event do not happened. + * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 edge-detect brake event do not happened. + * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 edge-detect brake event do not happened. + * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 edge-detect brake event do not happened. + * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 edge-detect brake event do not happened. + * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 level-detect brake event do not happened. + * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 level-detect brake event do not happened. + * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 level-detect brake event do not happened. + * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 level-detect brake event do not happened. + * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 level-detect brake event do not happened. + * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 level-detect brake event do not happened. + * | | |1 = When EEPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 edge-detect brake state is released. + * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear. + * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 edge-detect brake state is released. + * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear. + * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 edge-detect brake state is released. + * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear. + * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 edge-detect brake state is released. + * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear. + * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 edge-detect brake state is released. + * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear. + * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 edge-detect brake state is released. + * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear. + * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 level-detect brake state is released. + * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 level-detect brake state is released. + * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 level-detect brake state is released. + * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 level-detect brake state is released. + * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 level-detect brake state is released. + * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 level-detect brake state is released. + * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * @var EPWM_T::DACTRGEN + * Offset: 0xF4 EPWM Trigger DAC Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * @var EPWM_T::EADCTS0 + * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count CMPDAT point. + * | | |0100 = EPWM_CH0 down-count CMPDAT point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count CMPDAT point. + * | | |1001 = EPWM_CH1 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit + * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count CMPDAT point. + * | | |0100 = EPWM_CH0 down-count CMPDAT point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count CMPDAT point. + * | | |1001 = EPWM_CH1 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit + * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count CMPDAT point. + * | | |0100 = EPWM_CH2 down-count CMPDAT point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count CMPDAT point. + * | | |1001 = EPWM_CH3 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit + * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count CMPDAT point. + * | | |0100 = EPWM_CH2 down-count CMPDAT point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count CMPDAT point. + * | | |1001 = EPWM_CH3 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit + * @var EPWM_T::EADCTS1 + * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count CMPDAT point. + * | | |0100 = EPWM_CH4 down-count CMPDAT point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count CMPDAT point. + * | | |1001 = EPWM_CH5 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit + * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count CMPDAT point. + * | | |0100 = EPWM_CH4 down-count CMPDAT point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count CMPDAT point. + * | | |1001 = EPWM_CH5 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit + * @var EPWM_T::FTCMPDAT[3] + * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMP |EPWM Free Trigger Compare Register + * | | |FTCMP use to compare with even CNTR to trigger EADC + * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::SSCTL + * Offset: 0x110 EPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits + * | | |00 = Synchronous start source come from EPWM0. + * | | |01 = Synchronous start source come from EPWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var EPWM_T::SSTRG + * Offset: 0x114 EPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) + * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. + * @var EPWM_T::LEBCTL + * Offset: 0x118 EPWM Leading Edge Blanking Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit + * | | |0 = EPWM Leading Edge Blanking Disabled. + * | | |1 = EPWM Leading Edge Blanking Enabled. + * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. + * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. + * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. + * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type + * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. + * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. + * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. + * | | |3 = Reserved. + * @var EPWM_T::LEBCNT + * Offset: 0x11C EPWM Leading Edge Blanking Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter + * | | |This counter value decides leading edge blanking window size + * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. + * @var EPWM_T::STATUS + * Offset: 0x120 EPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[8] |SYNCINF0 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[9] |SYNCINF2 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[10] |SYNCINF4 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[16] |EADCTRGF0 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRGF1 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRGF2 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRGF3 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRGF4 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRGF5 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[24] |DACTRGF |DAC Start of Conversion Flag + * | | |0 = Indicates no DAC start of conversion trigger event has occurred. + * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit + * @var EPWM_T::IFA[6] + * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = CNT equal to Zero in channel n. + * | | |01 = CNT equal to PERIOD in channel n. + * | | |10 = CNT equal to CMPU in channel n. + * | | |11 = CNT equal to CMPD in channel n. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator disable. + * | | |1 = EPWM_CHn interrupt flag accumulator enable. + * @var EPWM_T::AINTSTS + * Offset: 0x150 EPWM Accumulator Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * @var EPWM_T::AINTEN + * Offset: 0x154 EPWM Accumulator Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * @var EPWM_T::APDMACTL + * Offset: 0x158 EPWM Accumulator PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * @var EPWM_T::CAPINEN + * Offset: 0x200 EPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * @var EPWM_T::CAPCTL + * Offset: 0x204 EPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var EPWM_T::CAPSTS + * Offset: 0x208 EPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * @var EPWM_T::PDMACTL + * Offset: 0x23C EPWM PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable + * | | |0 = Channel 0/1 PDMA function Disabled. + * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. + * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT0/1. + * | | |10 = EPWM_FCAPDAT0/1. + * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1. + * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11. + * | | |0 = EPWM_FCAPDAT0/1 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT0/1 is the first captured data to memory. + * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer + * | | |0 = Channel0. + * | | |1 = Channel1. + * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable + * | | |0 = Channel 2/3 PDMA function Disabled. + * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. + * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT2/3. + * | | |10 = EPWM_FCAPDAT2/3. + * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3. + * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11. + * | | |0 = EPWM_FCAPDAT2/3 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT2/3 is the first captured data to memory. + * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer + * | | |0 = Channel2. + * | | |1 = Channel3. + * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable + * | | |0 = Channel 4/5 PDMA function Disabled. + * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. + * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT4/5. + * | | |10 = EPWM_FCAPDAT4/5. + * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5. + * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11. + * | | |0 = EPWM_FCAPDAT4/5 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT4/5 is the first captured data to memory. + * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer + * | | |0 = Channel4. + * | | |1 = Channel5. + * @var EPWM_T::PDMACAP[3] + * Offset: 0x240 EPWM Capture Channel 01 PDMA Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) + * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. + * @var EPWM_T::CAPIEN + * Offset: 0x250 EPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var EPWM_T::CAPIF + * Offset: 0x254 EPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will cleared by hardware after PDMA transfer data. + * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * @var EPWM_T::PBUF[6] + * Offset: 0x304 EPWM PERIOD0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::CMPBUF[6] + * Offset: 0x31C EPWM CMPDAT0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CPSCBUF[3] + * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Use as EPWM counter clock prescale active register. + * @var EPWM_T::FTCBUF[3] + * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) + * | | |Used as FTCMPDAT active register. + * @var EPWM_T::FTCI + * Offset: 0x34C EPWM FTCMPDAT Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + */ + __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ + __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ + __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ + __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ + __IO uint32_t CLKPSC[3]; /*!< [0x0014] EPWM Clock Prescale Register 0/1,2/3,4/5 */ + __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ + __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PERIOD[6]; /*!< [0x0030] EPWM Period Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CMPDAT[6]; /*!< [0x0050] EPWM Comparator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DTCTL[3]; /*!< [0x0070] EPWM Dead-Time Control Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PHS[3]; /*!< [0x0080] EPWM Counter Phase Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CNT[6]; /*!< [0x0090] EPWM Counter Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ + __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ + __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ + __IO uint32_t BRKCTL[3]; /*!< [0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 */ + __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ + __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ + __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ + __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ + __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ + __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ + __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ + __IO uint32_t FTCMPDAT[3]; /*!< [0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE7[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ + __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ + __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ + __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE8[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t IFA[6]; /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE9[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ + __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ + __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE10[41]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ + ECAPDAT_T CAPDAT[6]; /*!< [0x020C] EPWM Rising and Falling Capture Data Register 0~5 */ + __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ + __I uint32_t PDMACAP[3]; /*!< [0x0240] EPWM Capture Channel 01,23,45 PDMA Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE11[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE12[43]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t PBUF[6]; /*!< [0x0304] EPWM PERIOD0~5 Buffer */ + __I uint32_t CMPBUF[6]; /*!< [0x031c] EPWM CMPDAT0~5 Buffer */ + __I uint32_t CPSCBUF[3]; /*!< [0x0334] EPWM CLKPSC0_1/2_3/4_5 Buffer */ + __I uint32_t FTCBUF[3]; /*!< [0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer */ + __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ + +} EPWM_T; + +/** + @addtogroup EPWM_CONST EPWM Bit Field Definition + Constant Definitions for EPWM Controller +@{ */ + +#define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ +#define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ + +#define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ +#define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ + +#define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ +#define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ + +#define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ +#define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ + +#define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ +#define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ + +#define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ +#define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ + +#define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ +#define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ + +#define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ +#define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ + +#define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ +#define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ + +#define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ +#define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ + +#define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ +#define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ + +#define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ +#define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ + +#define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ +#define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ + +#define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ +#define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ + +#define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ +#define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ + +#define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ +#define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ + +#define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ +#define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ + +#define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ +#define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ + +#define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ +#define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ + +#define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ +#define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ + +#define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ +#define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ + +#define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ +#define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ + +#define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ +#define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ + +#define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ +#define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ + +#define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ +#define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ + +#define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ +#define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ + +#define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ +#define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ + +#define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ +#define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ + +#define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ +#define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ + +#define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ +#define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ + +#define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ +#define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ + +#define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ +#define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ + +#define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ +#define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ + +#define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ +#define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ + +#define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ +#define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ + +#define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ +#define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ + +#define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ +#define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ + +#define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ +#define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ + +#define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ +#define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ + +#define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ +#define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ + +#define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ +#define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ + +#define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ +#define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ + +#define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ +#define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ + +#define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ +#define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ + +#define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ +#define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ + +#define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ +#define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ + +#define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ +#define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ + +#define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ +#define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ + +#define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ +#define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ + +#define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ +#define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ + +#define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ +#define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ + +#define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ +#define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ + +#define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ +#define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ +#define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ + +#define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ +#define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ + +#define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */ +#define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */ + +#define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */ +#define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */ + +#define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */ +#define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */ + +#define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ +#define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ + +#define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ +#define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ + +#define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ +#define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ + +#define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ +#define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ + +#define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ +#define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ + +#define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ +#define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ + +#define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ +#define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ +#define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ + +#define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ +#define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ + +#define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ +#define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ + +#define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ +#define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ + +#define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ +#define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ + +#define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ +#define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ + +#define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ +#define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ + +#define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ +#define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ + +#define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ +#define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ + +#define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ +#define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ + +#define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ +#define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ + +#define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ +#define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ + +#define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ +#define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ + +#define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ +#define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ + +#define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ +#define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ + +#define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ +#define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ + +#define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ +#define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ + +#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ +#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ + +#define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ +#define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ + +#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ +#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ + +#define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ +#define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ + +#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ +#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ + +#define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ +#define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ + +#define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */ +#define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */ + +#define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */ +#define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */ + +#define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */ +#define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */ + +#define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */ +#define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */ + +#define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */ +#define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */ + +#define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */ +#define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */ + +#define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */ +#define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */ + +#define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */ +#define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */ + +#define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */ +#define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */ + +#define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ +#define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ + +#define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ +#define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ + +#define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ +#define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ + +#define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ +#define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ + +#define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ +#define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ + +#define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ +#define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ + +#define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ +#define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ + +#define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ +#define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ + +#define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ +#define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ + +#define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ +#define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ + +#define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ +#define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ + +#define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ +#define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ + +#define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ +#define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ + +#define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ +#define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ + +#define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ +#define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ + +#define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ +#define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ +#define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ +#define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ +#define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ +#define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ +#define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ +#define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ +#define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ +#define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ +#define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ +#define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ +#define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ +#define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ +#define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ +#define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ +#define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ +#define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ +#define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ +#define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ +#define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ +#define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ +#define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ +#define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ +#define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ +#define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ + +#define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ +#define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ + +#define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ +#define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ + +#define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ +#define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ + +#define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ +#define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ + +#define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ +#define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ + +#define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ +#define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ + +#define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ +#define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ + +#define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ +#define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ + +#define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ +#define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ + +#define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ +#define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ + +#define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ +#define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ + +#define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ +#define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ + +#define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ +#define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ + +#define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ +#define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ + +#define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ +#define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ + +#define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ +#define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ + +#define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ +#define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ + +#define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ +#define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ + +#define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ +#define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ + +#define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ +#define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ + +#define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ +#define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ + +#define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ +#define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ + +#define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ +#define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ + +#define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ +#define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ + +#define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ +#define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */ +#define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */ +#define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ +#define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ +#define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ + +#define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ +#define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */ +#define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */ +#define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ +#define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ +#define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ + +#define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ +#define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ +#define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ +#define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ + +#define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */ +#define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */ + +#define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */ +#define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */ +#define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */ +#define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ +#define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ +#define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ + +#define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ +#define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */ +#define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */ +#define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ +#define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ +#define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ + +#define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ +#define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ +#define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ +#define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ + +#define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */ +#define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */ + +#define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */ +#define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */ +#define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */ +#define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ +#define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ +#define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ + +#define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ +#define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */ +#define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */ +#define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ +#define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ +#define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ + +#define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ +#define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ +#define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ +#define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ + +#define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */ +#define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */ + +#define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */ +#define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */ + +#define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ +#define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ + +#define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ +#define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ + +#define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ +#define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ + +#define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ +#define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ + +#define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ +#define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ + +#define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ +#define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ + +#define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ +#define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ + +#define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ +#define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ + +#define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ +#define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ + +#define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ +#define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ + +#define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ +#define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ + +#define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ +#define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ + +#define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ +#define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ + +#define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ +#define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ + +#define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ +#define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ + +#define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ +#define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ + +#define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ +#define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ + +#define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ +#define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ + +#define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ +#define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ + +#define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ +#define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ + +#define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ +#define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ + +#define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ +#define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ + +#define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ +#define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ + +#define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ +#define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ + +#define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ +#define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ + +#define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ +#define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ + +#define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ +#define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ + +#define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ +#define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ + +#define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ +#define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ + +#define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ +#define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ + +#define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ +#define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ + +#define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ +#define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ + +#define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ +#define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ + +#define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ +#define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ + +#define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ +#define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ + +#define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ +#define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ + +#define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ +#define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ + +#define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ +#define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ + +#define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ +#define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ + +#define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ +#define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ + +#define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ +#define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ + +#define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ +#define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ + +#define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ +#define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ +#define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ +#define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ + +#define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ +#define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ +#define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ +#define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ + +#define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ +#define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ + +#define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ +#define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ + +#define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ +#define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ + +#define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ +#define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ + +#define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ +#define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ + +#define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ +#define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ + +#define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ +#define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ + +#define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ +#define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ + +#define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ +#define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ + +#define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ +#define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ + +#define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ +#define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ + +#define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ +#define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ + +#define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ +#define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ + +#define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ +#define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ + +#define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ +#define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ + +#define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ +#define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ + +#define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ +#define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ + +#define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ +#define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ + +#define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ +#define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ + +#define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ +#define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ + +#define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ +#define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ + +#define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ +#define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ + +#define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ +#define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ + +#define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ +#define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ + +#define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ +#define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ + +#define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ +#define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ + +#define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ +#define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ + +#define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ +#define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ + +#define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ +#define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ + +#define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ +#define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ + +#define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ +#define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ + +#define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ +#define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ + +#define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ +#define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ + +#define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ +#define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ + +#define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ +#define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ + +#define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ +#define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ + +#define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ +#define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ + +#define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ +#define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ + +#define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ +#define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ + +#define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ +#define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ + +#define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ +#define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ + +#define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ +#define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ + +#define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ +#define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ + +#define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ +#define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ + +#define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ +#define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ + +#define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ +#define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ + +#define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ +#define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ + +#define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ +#define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ + +#define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */ +#define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */ + +#define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */ +#define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */ + +#define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */ +#define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */ + +#define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */ +#define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */ + +#define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */ +#define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */ + +#define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */ +#define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */ + +#define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */ +#define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */ + +#define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */ +#define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */ + +#define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */ +#define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */ + +#define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */ +#define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */ + +#define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */ +#define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */ + +#define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */ +#define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */ + +#define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */ +#define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */ + +#define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */ +#define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */ + +#define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */ +#define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */ + +#define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */ +#define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */ + +#define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */ +#define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */ + +#define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */ +#define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */ + +#define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */ +#define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */ + +#define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */ +#define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */ + +#define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */ +#define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */ + +#define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */ +#define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */ + +#define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */ +#define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */ + +#define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */ +#define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */ + +#define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ +#define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ +#define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ + +#define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ +#define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ +#define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ + +#define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ +#define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ +#define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ + +#define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ +#define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ +#define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ + +#define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ +#define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ +#define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ + +#define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ +#define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ +#define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ + +#define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ +#define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ + +#define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ +#define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ + +#define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ +#define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ + +#define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ +#define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ + +#define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ +#define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ + +#define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ +#define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ + +#define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ +#define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ + +#define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ +#define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ + +#define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ +#define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ + +#define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ +#define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ + +#define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ +#define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ + +#define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ +#define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ + +#define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ +#define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ + +#define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ +#define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ + +#define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ +#define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ + +#define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ +#define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ + +#define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ +#define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ + +#define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ +#define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ + +#define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ +#define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ + +#define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ +#define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ + +#define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ +#define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ + +#define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ +#define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ + +#define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ +#define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ + +#define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ +#define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ + +#define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ +#define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ + +#define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ +#define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ + +#define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ +#define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ + +#define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ +#define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ + +#define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ +#define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ + +#define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ +#define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ + +#define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ +#define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ + +#define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ +#define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ + +#define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */ +#define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */ + +#define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ +#define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ + +#define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ +#define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ + +#define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ +#define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ + +#define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ +#define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ + +#define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ +#define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ + +#define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ +#define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ + +#define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ +#define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ + +#define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ +#define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ + +#define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ +#define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ + +#define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ +#define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ + +#define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ +#define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ + +#define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ +#define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ + +#define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ +#define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ + +#define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ +#define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ + +#define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ +#define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ + +#define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ +#define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ + +#define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ +#define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ + +#define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ +#define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ + +#define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ +#define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ + +#define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ +#define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ + +#define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ +#define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ + +#define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ +#define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ + +#define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ +#define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ + +#define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ +#define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ + +#define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ +#define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ + +#define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ +#define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ + +#define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ +#define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ + +#define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ +#define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ + +#define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ +#define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ + +#define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ +#define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ + +#define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ +#define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ + +#define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ +#define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ + +#define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ +#define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ + +#define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ +#define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ + +#define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ +#define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ + +#define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ +#define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ + +#define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ +#define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ +#define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ +#define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ +#define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ +#define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ +#define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ +#define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ + +#define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ +#define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ + +#define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ +#define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ + +#define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ +#define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ + +#define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ +#define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ + +#define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ +#define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ + +#define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ +#define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ + +#define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ +#define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ + +#define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ +#define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ + +#define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ +#define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ + +#define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ +#define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ + +#define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ +#define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ + +#define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ +#define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ +#define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ +#define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ +#define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ +#define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ +#define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ +#define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ +#define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ +#define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ +#define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ +#define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ +#define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ +#define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ + +#define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ +#define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ + +#define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ +#define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ + +#define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ +#define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ + +#define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ +#define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ + +#define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ +#define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ + +#define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ +#define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ + +#define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ +#define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ + +#define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ +#define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ + +#define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ +#define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ + +#define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ +#define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ + +#define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ +#define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ + +#define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ +#define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ +#define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ +#define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ +#define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ +#define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ +#define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ +#define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ +#define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ +#define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ +#define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ +#define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ +#define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ +#define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ + +#define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ +#define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ + +#define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ +#define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ + +#define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ +#define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ + +#define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ +#define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ + +#define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ +#define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ + +#define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ +#define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ + +#define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ +#define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ + +#define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ +#define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ + +#define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ +#define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ + +#define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ +#define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ + +#define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ +#define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ + +#define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ +#define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ + +#define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ +#define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ + +#define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ +#define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ + +#define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ +#define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ + +#define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ +#define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ + +#define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ +#define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ + +#define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ +#define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ + +#define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ +#define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ + +#define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ +#define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ + +#define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ +#define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ + +#define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ +#define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ + +#define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ +#define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ + +#define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ +#define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ + +#define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ +#define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ + +#define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ +#define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ + +#define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ +#define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ + +#define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ +#define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ + +#define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ +#define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ + +#define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ +#define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ + +#define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ +#define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ + +#define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ +#define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ + +#define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ +#define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ + +#define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ +#define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ + +#define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ +#define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ + +#define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ +#define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ + +#define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ +#define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ + +#define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ +#define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ + +#define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ +#define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ + +#define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ +#define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ + +#define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ +#define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ + +#define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ +#define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ + +#define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ +#define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ + +#define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ +#define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ + +#define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ +#define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ + +#define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ +#define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ + +#define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ +#define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ + +#define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ +#define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ + +#define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ +#define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ + +#define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ +#define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ + +#define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */ +#define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */ + +#define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */ +#define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */ + +#define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */ +#define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */ + +#define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ +#define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ + +#define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ +#define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ + +#define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ +#define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ + +#define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ +#define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ + +#define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ +#define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ + +#define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ +#define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ + +#define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ +#define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ + +#define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ +#define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ + +#define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ +#define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ + +/**@}*/ /* EPWM_CONST */ +/**@}*/ /* end of EPWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EPWM_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/fmc_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/fmc_reg.h new file mode 100644 index 00000000000..46ab4332e27 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/fmc_reg.h @@ -0,0 +1,640 @@ +/**************************************************************************//** + * @file fmc_reg.h + * @version V1.00 + * @brief FMC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __FMC_REG_H__ +#define __FMC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup FMC Flash Memory Controller(FMC) + Memory Mapped Structure for FMC Controller +@{ */ + +typedef struct +{ + /** + * @var FMC_T::ISPCTL + * Offset: 0x00 ISP Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPEN |ISP Enable Bit (Write Protect) + * | | |ISP function enable bit. Set this bit to enable ISP function. + * | | |0 = ISP function Disabled. + * | | |1 = ISP function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |BS |Boot Select (Write Protect) + * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively + * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from + * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. + * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |SPUEN |SPROM Update Enable Bit (Write Protect) + * | | |0 = SPROM cannot be updated. + * | | |1 = SPROM can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |APUEN |APROM Update Enable Bit (Write Protect) + * | | |0 = APROM cannot be updated when the chip runs in APROM. + * | | |1 = APROM can be updated when the chip runs in APROM. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) + * | | |0 = CONFIG cannot be updated. + * | | |1 = CONFIG can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) + * | | |LDROM update enable bit. + * | | |0 = LDROM cannot be updated. + * | | |1 = LDROM can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |This bit needs to be cleared by writing 1 to it. + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region + * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 + * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1 + * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A + * | | |(17) Read any content of boot loader with ICE connection + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |BL |Boot Loader Booting (Write Protect) + * | | |This bit is initiated with the inversed value of MBS (CONFIG0[5]) + * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded + * | | |This bit is used to check chip boot from Boot Loader or not + * | | |User should keep original value of this bit when updating FMC_ISPCTL register. + * | | |0 = Booting from APROM or LDROM. + * | | |1 = Booting from Boot Loader. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::ISPADDR + * Offset: 0x04 ISP Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPADDR |ISP Address + * | | |The NuMicro M480 series is equipped with embedded flash + * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation + * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. + * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation. + * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) + * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). + * @var FMC_T::ISPDAT + * Offset: 0x08 ISP Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT |ISP Data + * | | |Write data to this register before ISP program operation. + * | | |Read data from this register after ISP read operation. + * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff + * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment + * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result + * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect + * @var FMC_T::ISPCMD + * Offset: 0x0C ISP Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CMD |ISP Command + * | | |ISP command table is shown below: + * | | |0x00= FLASH Read. + * | | |0x04= Read Unique ID. + * | | |0x08= Read Flash All-One Result. + * | | |0x0B= Read Company ID. + * | | |0x0C= Read Device ID. + * | | |0x0D= Read Checksum. + * | | |0x21= FLASH 32-bit Program. + * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. + * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. + * | | |0x25= FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1.. + * | | |0x27= FLASH Multi-Word Program. + * | | |0x28= Run Flash All-One Verification. + * | | |0x2D= Run Checksum Calculation. + * | | |0x2E= Vector Remap. + * | | |0x40= FLASH 64-bit Read. + * | | |0x61= FLASH 64-bit Program. + * | | |The other commands are invalid. + * @var FMC_T::ISPTRG + * Offset: 0x10 ISP Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPGO |ISP Start Trigger (Write Protect) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::DFBA + * Offset: 0x14 Data Flash Base Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DFBA |Data Flash Base Address + * | | |This register indicates Data Flash start address. It is a read only register. + * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 + * | | |This register is valid when DFEN (CONFIG0[0]) =0 . + * @var FMC_T::ISPSTS + * Offset: 0x40 ISP Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPBUSY |ISP Busy Flag (Read Only) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * |[2:1] |CBS |Boot Selection of CONFIG (Read Only) + * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. + * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. + * | | |00 = LDROM with IAP mode. + * | | |01 = LDROM without IAP mode. + * | | |10 = APROM with IAP mode. + * | | |11 = APROM without IAP mode. + * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) + * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from Boot Loader. + * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) + * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only) + * | | |This bit is set if flash access cycle auto-tuning function is disabled + * | | |The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. + * | | |0 = Flash access cycle auto-tuning is enabled. + * | | |1 = Flash access cycle auto-tuning is disabled. + * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) + * | | |This bit is set if data is mismatched at ISP programming verification + * | | |This bit is clear by performing ISP flash erase or ISP read CID operation + * | | |0 = Flash Program is success. + * | | |1 = Flash Program is fail. Program data is different with data in the flash memory + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region. + * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 + * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A + * | | |(17) Read any content of boot loader with ICE connection + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |ALLONE |Flash All-one Verification Flag + * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1 + * | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. + * | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete. + * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) + * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF} + * |[31] |SCODE |Security Code Active Flag + * | | |This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation. + * | | |0 = Secured code is inactive. + * | | |1 = Secured code is active. + * @var FMC_T::CYCCTL + * Offset: 0x4C Flash Access Cycle Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) + * | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;. + * | | |The HCLK working frequency range range is<27MHz + * | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;. + * | | | The optimized HCLK working frequency range is 27~54 MHz + * | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;. + * | | |The optimized HCLK working frequency range is 54~81MHz + * | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;. + * | | | The optimized HCLK working frequency range is81~108MHz + * | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;. + * | | |The optimized HCLK working frequency range is 108~135MHz + * | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;. + * | | | The optimized HCLK working frequency range is 135~162MHz + * | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;. + * | | | The optimized HCLK working frequency range is 162~192MHz + * | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;. + * | | |The optimized HCLK working frequency range is >192MHz + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::KPKEY0 + * Offset: 0x50 KPROM KEY0 Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only) + * | | |Write KPKEY0 data to this register before KEY Comparison operation. + * @var FMC_T::KPKEY1 + * Offset: 0x54 KPROM KEY1 Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only) + * | | |Write KPKEY1 data to this register before KEY Comparison operation. + * @var FMC_T::KPKEY2 + * Offset: 0x58 KPROM KEY2 Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only) + * | | |Write KPKEY2 data to this register before KEY Comparison operation. + * @var FMC_T::KPKEYTRG + * Offset: 0x5C KPROM KEY Comparison Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection) + * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished + * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0. + * | | |0 = KEY comparison operation is finished. + * | | |1 = KEY comparison is progressed. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * |[1] |TCEN |Timeout Counting Enable (Write Protection) + * | | |0 = Timeout counting is disabled. + * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish. + * | | |10 minutes is at least for timeout, and average is about 20 minutes. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::KPKEYSTS + * Offset: 0x60 KPROM KEY Comparison Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KEYBUSY |KEY Comparison Busy (Read Only) + * | | |0 = KEY comparison is finished. + * | | |1 = KEY comparison is busy. + * |[1] |KEYLOCK |KEY LOCK Flag + * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection + * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0 + * | | |This bit also can be set to 1 while + * | | | - CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or + * | | | - KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or + * | | | - KEYENROM is programmed a non-0xFF value or + * | | | - Timeout event or + * | | | - FORBID(FMC_KPKEYSTS[3]) is 1 + * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection. + * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection. + * | | |SPROM write protect is depended on SPFLAG. + * | | |CONFIG write protect is depended on CFGFLAG + * |[2] |KEYMATCH |KEY Match Flag (Read Only) + * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched + * | | |This bit is also cleared to 0 while + * | | | - CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or + * | | | - Timeout event or + * | | | - KPROM is erased or + * | | | - KEYENROM is programmed to a non-0xFF value. + * | | | - Chip is in power down mode. + * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. + * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting. + * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only) + * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]). + * | | |0 = KEY comparison is not forbidden. + * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger. + * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only) + * | | |This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset + * | | |This bit is cleared to 0 by hardware while KPROM is erased + * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. + * | | |0 = Security Key protection is disabled. + * | | |1 = Security Key protection is enabled. + * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only) + * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset + * | | |This bit is cleared to 0 by hardware while KPROM is erased + * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. + * | | |0 = CONFIG write-protection is disabled. + * | | |1 = CONFIG write-protection is enabled. + * |[6] |SPFLAG |SPROM Write-protection Enabled Flag (Read Only) + * | | |This bit is set while the KEYENROM [1] is 0 at power-on or reset + * | | |This bit is cleared to 0 by hardware while KPROM is erased + * | | |This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0. + * | | |0 = SPROM write-protection is disabled. + * | | |1 = SPROM write-protection is enabled. + * @var FMC_T::KPKEYCNT + * Offset: 0x64 KPROM KEY-Unmatched Counting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only) + * | | |KPKECNT is increased when entry keys is wrong in Security Key protection + * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on. + * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only) + * | | |KPKEMAX is the maximum error key entry number at each power-on + * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated + * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting + * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX. + * @var FMC_T::KPCNT + * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only) + * | | |KPCNT is the power-on counting for error key entry in Security Key protection + * | | |KPCNT is cleared to 0 if key comparison is matched. + * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only) + * | | |KPMAX is the power-on maximum number for error key entry + * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated + * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting + * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX + * @var FMC_T::MPDAT0 + * Offset: 0x80 ISP Data0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT0 |ISP Data 0 + * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data + * @var FMC_T::MPDAT1 + * Offset: 0x84 ISP Data1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT1 |ISP Data 1 + * | | |This register is the second 32-bit data for 64-bit/multi-word programming. + * @var FMC_T::MPDAT2 + * Offset: 0x88 ISP Data2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT2 |ISP Data 2 + * | | |This register is the third 32-bit data for multi-word programming. + * @var FMC_T::MPDAT3 + * Offset: 0x8C ISP Data3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT3 |ISP Data 3 + * | | |This register is the fourth 32-bit data for multi-word programming. + * @var FMC_T::MPSTS + * Offset: 0xC0 ISP Multi-Program Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) + * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP Multi-Word program operation is finished. + * | | |1 = ISP Multi-Word program operation is progressed. + * |[1] |PPGO |ISP Multi-program Status (Read Only) + * | | |0 = ISP multi-word program operation is not active. + * | | |1 = ISP multi-word program operation is in progress. + * |[2] |ISPFF |ISP Fail Flag (Read Only) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region. + * |[4] |D0 |ISP DATA 0 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. + * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. + * |[5] |D1 |ISP DATA 1 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. + * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. + * |[6] |D2 |ISP DATA 2 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. + * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. + * |[7] |D3 |ISP DATA 3 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. + * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. + * @var FMC_T::MPADDR + * Offset: 0xC4 ISP Multi-Program Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MPADDR |ISP Multi-word Program Address + * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. + * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. + */ + __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ + __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ + __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ + __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ + __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ + __I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[10]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ + __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */ + __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */ + __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */ + __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */ + __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */ + __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */ + __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ + __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ + __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ + __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[12]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ + __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ + +} FMC_T; + +/** + @addtogroup FMC_CONST FMC Bit Field Definition + Constant Definitions for FMC Controller +@{ */ + +#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ +#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ + +#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ +#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ + +#define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */ +#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */ + +#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ +#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ + +#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ +#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ + +#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ +#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ + +#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ +#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ + +#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */ +#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */ + +#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ +#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ + +#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ +#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ + +#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ +#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ + +#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ +#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ + +#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */ +#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */ + +#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ +#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ + +#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */ +#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ + +#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ +#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ + +#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */ +#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */ + +#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ +#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ + +#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ +#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ + +#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ +#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ + +#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ +#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ + +#define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */ +#define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */ + +#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ +#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ + +#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */ +#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */ + +#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */ +#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */ + +#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */ +#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */ + +#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */ +#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */ + +#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */ +#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */ + +#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */ +#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */ + +#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */ +#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */ + +#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */ +#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */ + +#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */ +#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */ + +#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */ +#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */ + +#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */ +#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */ + +#define FMC_KPKEYSTS_SPFLAG_Pos (6) /*!< FMC_T::KPKEYSTS: SPFLAG Position */ +#define FMC_KPKEYSTS_SPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SPFLAG Mask */ + +#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */ +#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */ + +#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */ +#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */ + +#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */ +#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */ + +#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */ +#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */ + +#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ +#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ + +#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ +#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ + +#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ +#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ + +#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ +#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ + +#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ +#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ + +#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ +#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ + +#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ +#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ + +#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ +#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ + +#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ +#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ + +#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ +#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ + +#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ +#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ + +#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ +#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ + +/**@}*/ /* FMC_CONST */ +/**@}*/ /* end of FMC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __FMC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/gpio_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/gpio_reg.h new file mode 100644 index 00000000000..e5114d58926 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/gpio_reg.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file gpio_reg.h + * @version V1.00 + * @brief GPIO register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GPIO_REG_H__ +#define __GPIO_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup GPIO General Purpose Input/Output Controller(GPIO) + Memory Mapped Structure for GPIO Controller +@{ */ + + +typedef struct +{ + + /** + * @var GPIO_T::MODE + * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control + * | | |Determine each I/O mode of Px.n pins. + * | | |00 = Px.n is in Input mode. + * | | |01 = Px.n is in Push-pull Output mode. + * | | |10 = Px.n is in Open-drain Output mode. + * | | |11 = Px.n is in Quasi-bidirectional mode. + * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]). + * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on. + * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. + * | | |Note2: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DINOFF + * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control + * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. + * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. + * | | |0 = Px.n digital input path Enabled. + * | | |1 = Px.n digital input path Disabled (digital input tied to low). + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DOUT + * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DOUTn |Port A-H Pin[n] Output Value + * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DATMSK + * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask + * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. + * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. + * | | |If the write signal is masked, writing data to the protect bit is ignored. + * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. + * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected. + * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[n]) bit. + * | | |Note2: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::PIN + * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |PINn |Port A-H Pin[n] Pin Value + * | | |Each bit of the register reflects the actual status of the respective Px.n pin. + * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::DBEN + * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DBENn |Port A-H Pin[n] Input Signal De-Bounce Enable Bit + * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. + * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). + * | | |0 = Px.n de-bounce function Disabled. + * | | |1 = Px.n de-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::INTTYPE + * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control + * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. + * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. + * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. + * | | |0 = Edge trigger interrupt. + * | | |1 = Level trigger interrupt. + * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). + * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::INTEN + * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit + * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. + * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. + * | | |0 = Px.n level low or high to low interrupt Disabled. + * | | |1 = Px.n level low or high to low interrupt Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit + * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. + * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. + * | | |0 = Px.n level high or low to high interrupt Disabled. + * | | |1 = Px.n level high or low to high interrupt Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::INTSRC + * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag + * | | |Write Operation : + * | | |0 = No action. + * | | |1 = Clear the corresponding pending interrupt. + * | | |Read Operation : + * | | |0 = No interrupt at Px.n. + * | | |1 = Px.n generates an interrupt. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::SMTEN + * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit + * | | |0 = Px.n input Schmitt trigger function Disabled. + * | | |1 = Px.n input Schmitt trigger function Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::SLEWCTL + * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control + * | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V). + * | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V). + * | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V. + * | | |11 = Reserved. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var GPIO_T::PUSEL + * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register + * | | |Determine each I/O Pull-up/pull-down of Px.n pins. + * | | |00 = Px.n pull-up and pull-up disable. + * | | |01 = Px.n pull-up enable. + * | | |10 = Px.n pull-down enable. + * | | |11 = Reserved. + * | | |Note1: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation + * | | |The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode + * | | |The independent pull-down control register only valid when MODEn set as tri-state mode + * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode + * | | |Note2: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + */ + + __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 Port A-H I/O Mode Control */ + __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 Port A-H Digital Input Path Disable Control */ + __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 Port A-H Data Output Value */ + __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC Port A-H Data Output Write Mask */ + __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 Port A-H Pin Value */ + __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 Port A-H De-Bounce Enable Control Register */ + __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 Port A-H Interrupt Trigger Type Control */ + __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC Port A-H Interrupt Enable Control Register */ + __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 Port A-H Interrupt Source Flag */ + __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 Port A-H Input Schmitt Trigger Enable Register */ + __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 Port A-H High Slew Rate Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PUSEL; /* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 Port A-H Pull-up and Pull-down Enable Register */ + +} GPIO_T; + +typedef struct +{ + + /** + * @var GPIO_DBCTL_T::DBCTL + * Offset: 0x440 Interrupt De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection + * | | |0000 = Sample interrupt input once per 1 clocks. + * | | |0001 = Sample interrupt input once per 2 clocks. + * | | |0010 = Sample interrupt input once per 4 clocks. + * | | |0011 = Sample interrupt input once per 8 clocks. + * | | |0100 = Sample interrupt input once per 16 clocks. + * | | |0101 = Sample interrupt input once per 32 clocks. + * | | |0110 = Sample interrupt input once per 64 clocks. + * | | |0111 = Sample interrupt input once per 128 clocks. + * | | |1000 = Sample interrupt input once per 256 clocks. + * | | |1001 = Sample interrupt input once per 2*256 clocks. + * | | |1010 = Sample interrupt input once per 4*256 clocks. + * | | |1011 = Sample interrupt input once per 8*256 clocks. + * | | |1100 = Sample interrupt input once per 16*256 clocks. + * | | |1101 = Sample interrupt input once per 32*256 clocks. + * | | |1110 = Sample interrupt input once per 64*256 clocks. + * | | |1111 = Sample interrupt input once per 128*256 clocks. + * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection + * | | |0 = De-bounce counter clock source is the HCLK. + * | | |1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * |[5] |ICLKON |Interrupt Clock On Mode + * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. + * | | |1 = All I/O pins edge detection circuit is always active after reset. + * | | |Note: It is recommended to disable this bit to save system power if no special application concern. + */ + + __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */ + +} GPIO_DBCTL_T; + +/** + @addtogroup GPIO_CONST GPIO Bit Field Definition + Constant Definitions for GPIO Controller +@{ */ + +#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */ +#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */ + +#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */ +#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */ + +#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */ +#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */ + +#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */ +#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */ + +#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */ +#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */ + +#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */ +#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */ + +#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */ +#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */ + +#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */ +#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */ + +#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */ +#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */ + +#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */ +#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */ + +#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */ +#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */ + +#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */ +#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */ + +#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */ +#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */ + +#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */ +#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */ + +#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */ +#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */ + +#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */ +#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */ + +#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */ +#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */ + +#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */ +#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */ + +#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */ +#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */ + +#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */ +#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */ + +#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */ +#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */ + +#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */ +#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */ + +#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */ +#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */ + +#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */ +#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */ + +#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */ +#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */ + +#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */ +#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */ + +#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */ +#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */ + +#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */ +#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */ + +#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */ +#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */ + +#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */ +#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */ + +#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */ +#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */ + +#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */ +#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */ + +#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */ +#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */ + +#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */ +#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */ + +#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */ +#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */ + +#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */ +#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */ + +#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */ +#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */ + +#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */ +#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */ + +#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */ +#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */ + +#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */ +#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */ + +#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */ +#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */ + +#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */ +#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */ + +#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */ +#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */ + +#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */ +#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */ + +#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */ +#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */ + +#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */ +#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */ + +#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */ +#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */ + +#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */ +#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */ + +#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */ +#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */ + +#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */ +#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */ + +#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */ +#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */ + +#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */ +#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */ + +#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */ +#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */ + +#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */ +#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */ + +#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */ +#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */ + +#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */ +#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */ + +#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */ +#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */ + +#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */ +#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */ + +#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */ +#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */ + +#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */ +#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */ + +#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */ +#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */ + +#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */ +#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */ + +#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */ +#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */ + +#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */ +#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */ + +#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */ +#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */ + +#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */ +#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */ + +#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */ +#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */ + +#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */ +#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */ + +#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */ +#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */ + +#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */ +#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */ + +#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */ +#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */ + +#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */ +#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */ + +#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */ +#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */ + +#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */ +#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */ + +#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */ +#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */ + +#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */ +#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */ + +#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */ +#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */ + +#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */ +#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */ + +#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */ +#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */ + +#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */ +#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */ + +#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */ +#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */ + +#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */ +#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */ + +#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */ +#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */ + +#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */ +#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */ + +#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */ +#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */ + +#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */ +#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */ + +#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */ +#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */ + +#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */ +#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */ + +#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */ +#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */ + +#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */ +#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */ + +#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */ +#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */ + +#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */ +#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */ + +#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */ +#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */ + +#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */ +#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */ + +#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */ +#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */ + +#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */ +#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */ + +#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */ +#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */ + +#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */ +#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */ + +#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */ +#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */ + +#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */ +#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */ + +#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */ +#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */ + +#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */ +#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */ + +#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */ +#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */ + +#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */ +#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */ + +#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */ +#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */ + +#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */ +#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */ + +#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */ +#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */ + +#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */ +#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */ + +#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */ +#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */ + +#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */ +#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */ + +#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */ +#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */ + +#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */ +#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */ + +#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */ +#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */ + +#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */ +#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */ + +#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */ +#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */ + +#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */ +#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */ + +#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */ +#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */ + +#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */ +#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */ + +#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */ +#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */ + +#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */ +#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */ + +#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */ +#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */ + +#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */ +#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */ + +#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */ +#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */ + +#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */ +#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */ + +#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */ +#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */ + +#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */ +#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */ + +#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */ +#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */ + +#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */ +#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */ + +#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */ +#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */ + +#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */ +#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */ + +#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */ +#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */ + +#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */ +#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */ + +#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */ +#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */ + +#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */ +#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */ + +#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */ +#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */ + +#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */ +#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */ + +#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */ +#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */ + +#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */ +#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */ + +#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */ +#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */ + +#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */ +#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */ + +#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */ +#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */ + +#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */ +#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */ + +#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */ +#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */ + +#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */ +#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */ + +#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */ +#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */ + +#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */ +#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */ + +#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */ +#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */ + +#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */ +#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */ + +#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */ +#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */ + +#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */ +#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */ + +#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */ +#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */ + +#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */ +#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */ + +#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */ +#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */ + +#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */ +#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */ + +#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */ +#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */ + +#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */ +#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */ + +#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */ +#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */ + +#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */ +#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */ + +#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */ +#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */ + +#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */ +#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */ + +#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */ +#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */ + +#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */ +#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */ + +#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */ +#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */ + +#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */ +#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */ + +#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */ +#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */ + +#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */ +#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */ + +#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */ +#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */ + +#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */ +#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */ + +#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */ +#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */ + +#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */ +#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */ + +#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */ +#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */ + +#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */ +#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */ + +#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */ +#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */ + +#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */ +#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */ + +#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */ +#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */ + +#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */ +#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */ + +#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */ +#define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */ + +#define GPIO_SLEWCTL_HSREN1_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN1 Position */ +#define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */ + +#define GPIO_SLEWCTL_HSREN2_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN2 Position */ +#define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */ + +#define GPIO_SLEWCTL_HSREN3_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN3 Position */ +#define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */ + +#define GPIO_SLEWCTL_HSREN4_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN4 Position */ +#define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */ + +#define GPIO_SLEWCTL_HSREN5_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN5 Position */ +#define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */ + +#define GPIO_SLEWCTL_HSREN6_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN6 Position */ +#define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */ + +#define GPIO_SLEWCTL_HSREN7_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN7 Position */ +#define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */ + +#define GPIO_SLEWCTL_HSREN8_Pos (16) /*!< GPIO_T::SLEWCTL: HSREN8 Position */ +#define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */ + +#define GPIO_SLEWCTL_HSREN9_Pos (18) /*!< GPIO_T::SLEWCTL: HSREN9 Position */ +#define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */ + +#define GPIO_SLEWCTL_HSREN10_Pos (20) /*!< GPIO_T::SLEWCTL: HSREN10 Position */ +#define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */ + +#define GPIO_SLEWCTL_HSREN11_Pos (22) /*!< GPIO_T::SLEWCTL: HSREN11 Position */ +#define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */ + +#define GPIO_SLEWCTL_HSREN12_Pos (24) /*!< GPIO_T::SLEWCTL: HSREN12 Position */ +#define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */ + +#define GPIO_SLEWCTL_HSREN13_Pos (26) /*!< GPIO_T::SLEWCTL: HSREN13 Position */ +#define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */ + +#define GPIO_SLEWCTL_HSREN14_Pos (28) /*!< GPIO_T::SLEWCTL: HSREN14 Position */ +#define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */ + +#define GPIO_SLEWCTL_HSREN15_Pos (30) /*!< GPIO_T::SLEWCTL: HSREN15 Position */ +#define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */ + +#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */ +#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */ + +#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */ +#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */ + +#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */ +#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */ + +#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */ +#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */ + +#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */ +#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */ + +#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */ +#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */ + +#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */ +#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */ + +#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */ +#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */ + +#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */ +#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */ + +#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */ +#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */ + +#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */ +#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */ + +#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */ +#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */ + +#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */ +#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */ + +#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */ +#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */ + +#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */ +#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */ + +#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */ +#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */ + +#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */ +#define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */ + +#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */ +#define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */ + +#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */ +#define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */ + +/**@}*/ /* GPIO_CONST */ +/**@}*/ /* end of GPIO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __GPIO_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsotg_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsotg_reg.h new file mode 100644 index 00000000000..01aab99e311 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsotg_reg.h @@ -0,0 +1,397 @@ +/**************************************************************************//** + * @file hsotg_reg.h + * @version V1.00 + * @brief HSOTG register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSOTG_REG_H__ +#define __HSOTG_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSOTG High Speed USB On-The-Go Controller(HSOTG) + Memory Mapped Structure for HSOTG Controller +@{ */ + +typedef struct +{ + + + /** + * @var HSOTG_T::CTL + * Offset: 0x00 HSOTG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDROP |Drop VBUS Control + * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS + * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. + * | | |0 = Not drop the VBUS. + * | | |1 = Drop the VBUS. + * |[1] |BUSREQ |OTG Bus Request + * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection + * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power + * | | |This bit will be cleared when A-device goes to A_wait_vfall state + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol + * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification) + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed. + * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. + * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. + * |[2] |HNPREQEN |OTG HNP Request Enable Bit + * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral + * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state + * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host + * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. + * | | |0 = HNP request Disabled. + * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). + * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. + * |[4] |OTGEN |OTG Function Enable Bit + * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device + * | | |When USB frame not configured as OTG device, this bit is must be low. + * | | |0= OTG function Disabled. + * | | |1 = OTG function Enabled. + * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit + * | | |0 = OTG ID pin status change wake-up function Disabled. + * | | |1 = OTG ID pin status change wake-up function Enabled. + * @var HSOTG_T::PHYCTL + * Offset: 0x04 HSOTG PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OTGPHYEN |OTG PHY Enable + * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function + * | | |If device is not configured as OTG-device nor ID-dependent, this bit is "don't care". + * | | |0 = OTG PHY Disabled. + * | | |1 = OTG PHY Enabled. + * |[1] |IDDETEN |ID Detection Enable Bit + * | | |0 = Detect ID pin status Disabled. + * | | |1 = Detect ID pin status Enabled. + * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity + * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need + * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. + * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The off-chip USB VBUS power switch enable is active high. + * | | |1 = The off-chip USB VBUS power switch enable is active low. + * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity + * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component + * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. + * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. + * @var HSOTG_T::INTEN + * Offset: 0x08 HSOTG Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec. + * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Going to idle state means going to a_idle or b_idle state + * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. + * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted. + * | | |0 = This device as a peripheral interrupt Disabled. + * | | |1 = This device as a peripheral interrupt Enabled. + * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted. + * | | |0 = This device as a host interrupt Disabled. + * | | |1 = This device as a host interrupt Enabled. + * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var HSOTG_T::INTSTS + * Offset: 0x0C HSOTG Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIF |OTG Role Change Interrupt Status + * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. + * | | |0 = OTG device role not changed. + * | | |1 = OTG device role changed. + * | | |Note: Write 1 to clear this flag. + * |[1] |VBEIF |VBUS Error Interrupt Status + * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. + * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. + * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. + * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. + * |[2] |SRPFIF |SRP Fail Interrupt Status + * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification + * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. + * | | |0 = OTG B-device gets VBUS high before this interval. + * | | |1 = OTG B-device does not get VBUS high before this interval. + * | | |Note: Write 1 to clear this flag. + * |[3] |HNPFIF |HNP Fail Interrupt Status + * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. + * | | |0 = A-device connects to B-device before specified interval expires. + * | | |1 = A-device does not connect to B-device before specified interval expires. + * | | |Note: Write 1 to clear this flag. + * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status + * | | |Flag is set if the OTG device transfers from non-idle state to idle state + * | | |The OTG device will be neither a host nor a peripheral. + * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). + * | | |1 = OTG device goes back to idle state(a_idle or b_idle). + * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. + * | | |Note 2: Write 1 to clear this flag. + * |[5] |IDCHGIF |ID State Change Interrupt Status + * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. + * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[6] |PDEVIF |Act As Peripheral Interrupt Status + * | | |0= This device does not act as a peripheral. + * | | |1 = This device acts as a peripheral. + * | | |Note: Write 1 to clear this flag. + * |[7] |HOSTIF |Act As Host Interrupt Status + * | | |0= This device does not act as a host. + * | | |1 = This device acts as a host. + * | | |Note: Write 1 to clear this flag. + * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status + * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. + * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status + * | | |0 = AVLD (OTG_STATUS[4]) not toggled. + * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status + * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. + * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. + * | | |Note: Write 1 to clear this status. + * |[11] |SECHGIF |SESSEND State Change Interrupt Status + * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. + * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[13] |SRPDETIF |SRP Detected Interrupt Status + * | | |0 = SRP not detected. + * | | |1 = SRP detected. + * | | |Note: Write 1 to clear this status. + * @var HSOTG_T::STATUS + * Offset: 0x10 HSOTG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OVERCUR |over Current Condition + * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. + * | | |0 = OTG A-device drives VBUS successfully. + * | | |1 = OTG A-device cannot drives VBUS high in this interval. + * |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug + * | | |0 = Mini-A/Micro-A plug is attached. + * | | |1 = Mini-B/Micro-B plug is attached. + * |[2] |SESSEND |Session End Status + * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 + * | | |Session end means no meaningful power on VBUS. + * | | |0 = Session is not end. + * | | |1 = Session is end. + * |[3] |BVLD |B-device Session Valid Status + * | | |0 = B-device session is not valid. + * | | |1 = B-device session is valid. + * |[4] |AVLD |A-device Session Valid Status + * | | |0 = A-device session is not valid. + * | | |1 = A-device session is valid. + * |[5] |VBUSVLD |VBUS Valid Status + * | | |When VBUS is larger than 4.7V and A-device drives VBUS , this bit will be set to 1. + * | | |0 = VBUS is not valid. + * | | |1 = VBUS is valid. + * |[6] |ASPERI |As Peripheral Status + * | | |When OTG as peripheral, this bit is set. + * | | |0: OTG not as peripheral + * | | |1: OTG as peripheral + * |[7] |ASHOST |As Host Status + * | | |When OTG as Host, this bit is set. + * | | |0: OTG not as Host + * | | |1: OTG as Host + */ + __IO uint32_t CTL; /*!< [0x0000] HSOTG Control Register */ + __IO uint32_t PHYCTL; /*!< [0x0004] HSOTG PHY Control Register */ + __IO uint32_t INTEN; /*!< [0x0008] HSOTG Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x000c] HSOTG Interrupt Status Register */ + __I uint32_t STATUS; /*!< [0x0010] HSOTG Status Register */ + +} HSOTG_T; + +/** + @addtogroup HSOTG_CONST HSOTG Bit Field Definition + Constant Definitions for HSOTG Controller +@{ */ + +#define HSOTG_CTL_VBUSDROP_Pos (0) /*!< HSOTG_T::CTL: VBUSDROP Position */ +#define HSOTG_CTL_VBUSDROP_Msk (0x1ul << HSOTG_CTL_VBUSDROP_Pos) /*!< HSOTG_T::CTL: VBUSDROP Mask */ + +#define HSOTG_CTL_BUSREQ_Pos (1) /*!< HSOTG_T::CTL: BUSREQ Position */ +#define HSOTG_CTL_BUSREQ_Msk (0x1ul << HSOTG_CTL_BUSREQ_Pos) /*!< HSOTG_T::CTL: BUSREQ Mask */ + +#define HSOTG_CTL_HNPREQEN_Pos (2) /*!< HSOTG_T::CTL: HNPREQEN Position */ +#define HSOTG_CTL_HNPREQEN_Msk (0x1ul << HSOTG_CTL_HNPREQEN_Pos) /*!< HSOTG_T::CTL: HNPREQEN Mask */ + +#define HSOTG_CTL_OTGEN_Pos (4) /*!< HSOTG_T::CTL: OTGEN Position */ +#define HSOTG_CTL_OTGEN_Msk (0x1ul << HSOTG_CTL_OTGEN_Pos) /*!< HSOTG_T::CTL: OTGEN Mask */ + +#define HSOTG_CTL_WKEN_Pos (5) /*!< HSOTG_T::CTL: WKEN Position */ +#define HSOTG_CTL_WKEN_Msk (0x1ul << HSOTG_CTL_WKEN_Pos) /*!< HSOTG_T::CTL: WKEN Mask */ + +#define HSOTG_PHYCTL_OTGPHYEN_Pos (0) /*!< HSOTG_T::PHYCTL: OTGPHYEN Position */ +#define HSOTG_PHYCTL_OTGPHYEN_Msk (0x1ul << HSOTG_PHYCTL_OTGPHYEN_Pos) /*!< HSOTG_T::PHYCTL: OTGPHYEN Mask */ + +#define HSOTG_PHYCTL_IDDETEN_Pos (1) /*!< HSOTG_T::PHYCTL: IDDETEN Position */ +#define HSOTG_PHYCTL_IDDETEN_Msk (0x1ul << HSOTG_PHYCTL_IDDETEN_Pos) /*!< HSOTG_T::PHYCTL: IDDETEN Mask */ + +#define HSOTG_PHYCTL_VBENPOL_Pos (4) /*!< HSOTG_T::PHYCTL: VBENPOL Position */ +#define HSOTG_PHYCTL_VBENPOL_Msk (0x1ul << HSOTG_PHYCTL_VBENPOL_Pos) /*!< HSOTG_T::PHYCTL: VBENPOL Mask */ + +#define HSOTG_PHYCTL_VBSTSPOL_Pos (5) /*!< HSOTG_T::PHYCTL: VBSTSPOL Position */ +#define HSOTG_PHYCTL_VBSTSPOL_Msk (0x1ul << HSOTG_PHYCTL_VBSTSPOL_Pos) /*!< HSOTG_T::PHYCTL: VBSTSPOL Mask */ + +#define HSOTG_INTEN_ROLECHGIEN_Pos (0) /*!< HSOTG_T::INTEN: ROLECHGIEN Position */ +#define HSOTG_INTEN_ROLECHGIEN_Msk (0x1ul << HSOTG_INTEN_ROLECHGIEN_Pos) /*!< HSOTG_T::INTEN: ROLECHGIEN Mask */ + +#define HSOTG_INTEN_VBEIEN_Pos (1) /*!< HSOTG_T::INTEN: VBEIEN Position */ +#define HSOTG_INTEN_VBEIEN_Msk (0x1ul << HSOTG_INTEN_VBEIEN_Pos) /*!< HSOTG_T::INTEN: VBEIEN Mask */ + +#define HSOTG_INTEN_SRPFIEN_Pos (2) /*!< HSOTG_T::INTEN: SRPFIEN Position */ +#define HSOTG_INTEN_SRPFIEN_Msk (0x1ul << HSOTG_INTEN_SRPFIEN_Pos) /*!< HSOTG_T::INTEN: SRPFIEN Mask */ + +#define HSOTG_INTEN_HNPFIEN_Pos (3) /*!< HSOTG_T::INTEN: HNPFIEN Position */ +#define HSOTG_INTEN_HNPFIEN_Msk (0x1ul << HSOTG_INTEN_HNPFIEN_Pos) /*!< HSOTG_T::INTEN: HNPFIEN Mask */ + +#define HSOTG_INTEN_GOIDLEIEN_Pos (4) /*!< HSOTG_T::INTEN: GOIDLEIEN Position */ +#define HSOTG_INTEN_GOIDLEIEN_Msk (0x1ul << HSOTG_INTEN_GOIDLEIEN_Pos) /*!< HSOTG_T::INTEN: GOIDLEIEN Mask */ + +#define HSOTG_INTEN_IDCHGIEN_Pos (5) /*!< HSOTG_T::INTEN: IDCHGIEN Position */ +#define HSOTG_INTEN_IDCHGIEN_Msk (0x1ul << HSOTG_INTEN_IDCHGIEN_Pos) /*!< HSOTG_T::INTEN: IDCHGIEN Mask */ + +#define HSOTG_INTEN_PDEVIEN_Pos (6) /*!< HSOTG_T::INTEN: PDEVIEN Position */ +#define HSOTG_INTEN_PDEVIEN_Msk (0x1ul << HSOTG_INTEN_PDEVIEN_Pos) /*!< HSOTG_T::INTEN: PDEVIEN Mask */ + +#define HSOTG_INTEN_HOSTIEN_Pos (7) /*!< HSOTG_T::INTEN: HOSTIEN Position */ +#define HSOTG_INTEN_HOSTIEN_Msk (0x1ul << HSOTG_INTEN_HOSTIEN_Pos) /*!< HSOTG_T::INTEN: HOSTIEN Mask */ + +#define HSOTG_INTEN_BVLDCHGIEN_Pos (8) /*!< HSOTG_T::INTEN: BVLDCHGIEN Position */ +#define HSOTG_INTEN_BVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_BVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: BVLDCHGIEN Mask */ + +#define HSOTG_INTEN_AVLDCHGIEN_Pos (9) /*!< HSOTG_T::INTEN: AVLDCHGIEN Position */ +#define HSOTG_INTEN_AVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_AVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: AVLDCHGIEN Mask */ + +#define HSOTG_INTEN_VBCHGIEN_Pos (10) /*!< HSOTG_T::INTEN: VBCHGIEN Position */ +#define HSOTG_INTEN_VBCHGIEN_Msk (0x1ul << HSOTG_INTEN_VBCHGIEN_Pos) /*!< HSOTG_T::INTEN: VBCHGIEN Mask */ + +#define HSOTG_INTEN_SECHGIEN_Pos (11) /*!< HSOTG_T::INTEN: SECHGIEN Position */ +#define HSOTG_INTEN_SECHGIEN_Msk (0x1ul << HSOTG_INTEN_SECHGIEN_Pos) /*!< HSOTG_T::INTEN: SECHGIEN Mask */ + +#define HSOTG_INTEN_SRPDETIEN_Pos (13) /*!< HSOTG_T::INTEN: SRPDETIEN Position */ +#define HSOTG_INTEN_SRPDETIEN_Msk (0x1ul << HSOTG_INTEN_SRPDETIEN_Pos) /*!< HSOTG_T::INTEN: SRPDETIEN Mask */ + +#define HSOTG_INTSTS_ROLECHGIF_Pos (0) /*!< HSOTG_T::INTSTS: ROLECHGIF Position */ +#define HSOTG_INTSTS_ROLECHGIF_Msk (0x1ul << HSOTG_INTSTS_ROLECHGIF_Pos) /*!< HSOTG_T::INTSTS: ROLECHGIF Mask */ + +#define HSOTG_INTSTS_VBEIF_Pos (1) /*!< HSOTG_T::INTSTS: VBEIF Position */ +#define HSOTG_INTSTS_VBEIF_Msk (0x1ul << HSOTG_INTSTS_VBEIF_Pos) /*!< HSOTG_T::INTSTS: VBEIF Mask */ + +#define HSOTG_INTSTS_SRPFIF_Pos (2) /*!< HSOTG_T::INTSTS: SRPFIF Position */ +#define HSOTG_INTSTS_SRPFIF_Msk (0x1ul << HSOTG_INTSTS_SRPFIF_Pos) /*!< HSOTG_T::INTSTS: SRPFIF Mask */ + +#define HSOTG_INTSTS_HNPFIF_Pos (3) /*!< HSOTG_T::INTSTS: HNPFIF Position */ +#define HSOTG_INTSTS_HNPFIF_Msk (0x1ul << HSOTG_INTSTS_HNPFIF_Pos) /*!< HSOTG_T::INTSTS: HNPFIF Mask */ + +#define HSOTG_INTSTS_GOIDLEIF_Pos (4) /*!< HSOTG_T::INTSTS: GOIDLEIF Position */ +#define HSOTG_INTSTS_GOIDLEIF_Msk (0x1ul << HSOTG_INTSTS_GOIDLEIF_Pos) /*!< HSOTG_T::INTSTS: GOIDLEIF Mask */ + +#define HSOTG_INTSTS_IDCHGIF_Pos (5) /*!< HSOTG_T::INTSTS: IDCHGIF Position */ +#define HSOTG_INTSTS_IDCHGIF_Msk (0x1ul << HSOTG_INTSTS_IDCHGIF_Pos) /*!< HSOTG_T::INTSTS: IDCHGIF Mask */ + +#define HSOTG_INTSTS_PDEVIF_Pos (6) /*!< HSOTG_T::INTSTS: PDEVIF Position */ +#define HSOTG_INTSTS_PDEVIF_Msk (0x1ul << HSOTG_INTSTS_PDEVIF_Pos) /*!< HSOTG_T::INTSTS: PDEVIF Mask */ + +#define HSOTG_INTSTS_HOSTIF_Pos (7) /*!< HSOTG_T::INTSTS: HOSTIF Position */ +#define HSOTG_INTSTS_HOSTIF_Msk (0x1ul << HSOTG_INTSTS_HOSTIF_Pos) /*!< HSOTG_T::INTSTS: HOSTIF Mask */ + +#define HSOTG_INTSTS_BVLDCHGIF_Pos (8) /*!< HSOTG_T::INTSTS: BVLDCHGIF Position */ +#define HSOTG_INTSTS_BVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_BVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: BVLDCHGIF Mask */ + +#define HSOTG_INTSTS_AVLDCHGIF_Pos (9) /*!< HSOTG_T::INTSTS: AVLDCHGIF Position */ +#define HSOTG_INTSTS_AVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_AVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: AVLDCHGIF Mask */ + +#define HSOTG_INTSTS_VBCHGIF_Pos (10) /*!< HSOTG_T::INTSTS: VBCHGIF Position */ +#define HSOTG_INTSTS_VBCHGIF_Msk (0x1ul << HSOTG_INTSTS_VBCHGIF_Pos) /*!< HSOTG_T::INTSTS: VBCHGIF Mask */ + +#define HSOTG_INTSTS_SECHGIF_Pos (11) /*!< HSOTG_T::INTSTS: SECHGIF Position */ +#define HSOTG_INTSTS_SECHGIF_Msk (0x1ul << HSOTG_INTSTS_SECHGIF_Pos) /*!< HSOTG_T::INTSTS: SECHGIF Mask */ + +#define HSOTG_INTSTS_SRPDETIF_Pos (13) /*!< HSOTG_T::INTSTS: SRPDETIF Position */ +#define HSOTG_INTSTS_SRPDETIF_Msk (0x1ul << HSOTG_INTSTS_SRPDETIF_Pos) /*!< HSOTG_T::INTSTS: SRPDETIF Mask */ + +#define HSOTG_STATUS_OVERCUR_Pos (0) /*!< HSOTG_T::STATUS: OVERCUR Position */ +#define HSOTG_STATUS_OVERCUR_Msk (0x1ul << HSOTG_STATUS_OVERCUR_Pos) /*!< HSOTG_T::STATUS: OVERCUR Mask */ + +#define HSOTG_STATUS_IDSTS_Pos (1) /*!< HSOTG_T::STATUS: IDSTS Position */ +#define HSOTG_STATUS_IDSTS_Msk (0x1ul << HSOTG_STATUS_IDSTS_Pos) /*!< HSOTG_T::STATUS: IDSTS Mask */ + +#define HSOTG_STATUS_SESSEND_Pos (2) /*!< HSOTG_T::STATUS: SESSEND Position */ +#define HSOTG_STATUS_SESSEND_Msk (0x1ul << HSOTG_STATUS_SESSEND_Pos) /*!< HSOTG_T::STATUS: SESSEND Mask */ + +#define HSOTG_STATUS_BVLD_Pos (3) /*!< HSOTG_T::STATUS: BVLD Position */ +#define HSOTG_STATUS_BVLD_Msk (0x1ul << HSOTG_STATUS_BVLD_Pos) /*!< HSOTG_T::STATUS: BVLD Mask */ + +#define HSOTG_STATUS_AVLD_Pos (4) /*!< HSOTG_T::STATUS: AVLD Position */ +#define HSOTG_STATUS_AVLD_Msk (0x1ul << HSOTG_STATUS_AVLD_Pos) /*!< HSOTG_T::STATUS: AVLD Mask */ + +#define HSOTG_STATUS_VBUSVLD_Pos (5) /*!< HSOTG_T::STATUS: VBUSVLD Position */ +#define HSOTG_STATUS_VBUSVLD_Msk (0x1ul << HSOTG_STATUS_VBUSVLD_Pos) /*!< HSOTG_T::STATUS: VBUSVLD Mask */ + +#define HSOTG_STATUS_ASPERI_Pos (6) /*!< HSOTG_T::STATUS: ASPERI Position */ +#define HSOTG_STATUS_ASPERI_Msk (0x1ul << HSOTG_STATUS_ASPERI_Pos) /*!< HSOTG_T::STATUS: ASPERI Mask */ + +#define HSOTG_STATUS_ASHOST_Pos (7) /*!< HSOTG_T::STATUS: ASHOST Position */ +#define HSOTG_STATUS_ASHOST_Msk (0x1ul << HSOTG_STATUS_ASHOST_Pos) /*!< HSOTG_T::STATUS: ASHOST Mask */ + +/**@}*/ /* HSOTG_CONST */ +/**@}*/ /* end of HSOTG register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSOTG_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbd_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbd_reg.h new file mode 100644 index 00000000000..052f9876602 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbd_reg.h @@ -0,0 +1,1380 @@ +/**************************************************************************//** + * @file hsusbd_reg.h + * @version V1.00 + * @brief HSUSBD register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBD_REG_H__ +#define __HSUSBD_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSUSBD USB 2.0 Device Controller(HSUSBD) + Memory Mapped Structure for HSUSBD Controller +@{ */ + +typedef struct +{ + + /** + * @var HSUSBD_EP_T::EPDAT + * Offset: 0x00 Endpoint n Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |EPDAT |Endpoint A~L Data Register + * | | |Endpoint A~L data buffer for the buffer transaction (read or write). + * | | |Note: Only word access is supported. + * @var HSUSBD_EP_T::EPDAT_BYTE + * Offset: 0x00 Endpoint n Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EPDAT |Endpoint A~L Data Register + * | | |Endpoint A~L data buffer for the buffer transaction (read or write). + * | | |Note: Only byte access is supported. + * @var HSUSBD_EP_T::EPINTSTS + * Offset: 0x04 Endpoint n Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUFFULLIF |Buffer Full + * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write) + * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading). + * | | |0 = The endpoint packet buffer is not full. + * | | |1 = The endpoint packet buffer is full. + * | | |Note: This bit is read-only. + * |[1] |BUFEMPTYIF|Buffer Empty + * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. + * | | |0 = The endpoint buffer is not empty. + * | | |1 = The endpoint buffer is empty. + * | | |For an OUT endpoint: + * | | |0 = The currently selected buffer has not a count of 0. + * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read). + * | | |Note: This bit is read-only. + * |[2] |SHORTTXIF |Short Packet Transferred Interrupt + * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS). + * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS). + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |TXPKIF |Data Packet Transmitted Interrupt + * | | |0 = Not a data packet is transmitted from the endpoint to the host. + * | | |1 = A data packet is transmitted from the endpoint to the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |RXPKIF |Data Packet Received Interrupt + * | | |0 = No data packet is received from the host by the endpoint. + * | | |1 = A data packet is received from the host by the endpoint. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |OUTTKIF |Data OUT Token Interrupt + * | | |0 = A Data OUT token has not been received from the host. + * | | |1 = A Data OUT token has been received from the host + * | | |This bit also set by PING token (in high-speed only). + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |INTKIF |Data IN Token Interrupt + * | | |0 = Not Data IN token has been received from the host. + * | | |1 = A Data IN token has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |PINGIF |PING Token Interrupt + * | | |0 = A Data PING token has not been received from the host. + * | | |1 = A Data PING token has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |NAKIF |USB NAK Sent + * | | |0 = The last USB IN packet could be provided, and was acknowledged with an ACK. + * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |STALLIF |USB STALL Sent + * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. + * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |NYETIF |NYET Sent + * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet. + * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet. + * | | |Note: Write 1 to clear this bit to 0. + * |[11] |ERRIF |ERR Sent + * | | |0 = No any error in the transaction. + * | | |1 = There occurs any error in the transaction. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |SHORTRXIF |Bulk Out Short Packet Received + * | | |0 = No bulk out short packet is received. + * | | |1 = Received bulk out short packet (including zero length packet). + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_EP_T::EPINTEN + * Offset: 0x08 Endpoint n Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUFFULLIEN|Buffer Full Interrupt + * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus. + * | | |0 = Buffer full interrupt Disabled. + * | | |1 = Buffer full interrupt Enabled. + * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt + * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus. + * | | |0 = Buffer empty interrupt Disabled. + * | | |1 = Buffer empty interrupt Enabled. + * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host. + * | | |0 = Short data packet interrupt Disabled. + * | | |1 = Short data packet interrupt Enabled. + * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host. + * | | |0 = Data packet has been received from the host interrupt Disabled. + * | | |1 = Data packet has been received from the host interrupt Enabled. + * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host. + * | | |0 = Data packet has been transmitted to the host interrupt Disabled. + * | | |1 = Data packet has been transmitted to the host interrupt Enabled. + * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host. + * | | |0 = Data OUT token interrupt Disabled. + * | | |1 = Data OUT token interrupt Enabled. + * |[6] |INTKIEN |Data IN Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host. + * | | |0 = Data IN token interrupt Disabled. + * | | |1 = Data IN token interrupt Enabled. + * |[7] |PINGIEN |PING Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host. + * | | |0 = PING token interrupt Disabled. + * | | |1 = PING token interrupt Enabled. + * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host. + * | | |0 = NAK token interrupt Disabled. + * | | |1 = NAK token interrupt Enabled. + * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host. + * | | |0 = STALL token interrupt Disabled. + * | | |1 = STALL token interrupt Enabled. + * |[10] |NYETIEN |NYET Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint. + * | | |0 = NYET condition interrupt Disabled. + * | | |1 = NYET condition interrupt Enabled. + * |[11] |ERRIEN |ERR Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint. + * | | |0 = Error event interrupt Disabled. + * | | |1 = Error event interrupt Enabled. + * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint. + * | | |0 = Bulk out interrupt Disabled. + * | | |1 = Bulk out interrupt Enabled. + * @var HSUSBD_EP_T::EPDATCNT + * Offset: 0x0C Endpoint n Data Available Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATCNT |Data Count + * | | |For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer. + * | | |For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer. + * |[30:16] |DMALOOP |DMA Loop + * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer. + * @var HSUSBD_EP_T::EPRSPCTL + * Offset: 0x10 Endpoint n Response Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FLUSH |Buffer Flush + * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared + * | | |This bit is self-clearing + * | | |This bit should always be written after an configuration event. + * | | |0 = The packet buffer is not flushed. + * | | |1 = The packet buffer is flushed by user. + * |[2:1] |MODE |Mode Control + * | | |The two bits decide the operation mode of the in-endpoint. + * | | |00: Auto-Validate Mode + * | | |01: Manual-Validate Mode + * | | |10: Fly Mode + * | | |11: Reserved + * | | |These bits are not valid for an out-endpoint + * | | |The auto validate mode will be activated when the reserved mode is selected + * |[3] |TOGGLE |Endpoint Toggle + * | | |This bit is used to clear the endpoint data toggle bit + * | | |Reading this bit returns the current state of the endpoint data toggle bit. + * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host + * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3]. + * | | |0 = Not clear the endpoint data toggle bit. + * | | |1 = Clear the endpoint data toggle bit. + * |[4] |HALT |Endpoint Halt + * | | |This bit is used to send a STALL handshake as response to the token from the host + * | | |When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit. + * | | |0 = Not send a STALL handshake as response to the token from the host. + * | | |1 = Send a STALL handshake as response to the token from the host. + * |[5] |ZEROLEN |Zero Length + * | | |This bit is used to send a zero-length packet response to an IN-token + * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token + * | | |This bit gets cleared once the zero length data packet is sent. + * | | |0 = A zero packet is not sent to the host on reception of an IN-token. + * | | |1 = A zero packet is sent to the host on reception of an IN-token. + * |[6] |SHORTTXEN |Short Packet Transfer Enable + * | | |This bit is applicable only in case of Auto-Validate Method + * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer + * | | |This bit gets cleared once the data packet is sent. + * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint. + * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint. + * |[7] |DISBUF |Buffer Disable Bit + * | | |This bit is used to receive unknown size OUT short packet + * | | |The received packet size is reference USBD_EPxDATCNT register. + * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received. + * | | |1 = Buffer Disabled when Bulk-OUT short packet is received. + * @var HSUSBD_EP_T::EPMPS + * Offset: 0x14 Endpoint n Maximum Packet Size Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |EPMPS |Endpoint Maximum Packet Size + * | | |This field determines the Maximum Packet Size of the Endpoint. + * @var HSUSBD_EP_T::EPTXCNT + * Offset: 0x18 Endpoint n Transfer Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |TXCNT |Endpoint Transfer Count + * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method. + * | | |For OUT endpoints, this field has no effect. + * @var HSUSBD_EP_T::EPCFG + * Offset: 0x1C Endpoint n Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EPEN |Endpoint Valid + * | | |When set, this bit enables this endpoint + * | | |This bit has no effect on Endpoint 0, which is always enabled. + * | | |0 = The endpoint Disabled. + * | | |1 = The endpoint Enabled. + * |[2:1] |EPTYPE |Endpoint Type + * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type. + * | | |00 = Reserved. + * | | |01 = Bulk. + * | | |10 = Interrupt. + * | | |11 = Isochronous. + * |[3] |EPDIR |Endpoint Direction + * | | |0 = out-endpoint (Host OUT to Device). + * | | |1 = in-endpoint (Host IN to Device). + * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number. + * |[7:4] |EPNUM |Endpoint Number + * | | |This field selects the number of the endpoint. Valid numbers 1 to 15. + * | | |Note: Do not support two endpoints have same endpoint number. + * @var HSUSBD_EP_T::EPBUFST + * Offset: 0x20 Endpoint n RAM Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |SADDR |Endpoint Start Address + * | | |This is the start-address of the RAM space allocated for the endpoint A~L. + * @var HSUSBD_EP_T::EPBUFEND + * Offset: 0x24 Endpoint n RAM End Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |EADDR |Endpoint End Address + * | | |This is the end-address of the RAM space allocated for the endpoint A~L. + */ + + union + { + __IO uint32_t EPDAT; + __IO uint8_t EPDAT_BYTE; + + }; /*!< [0x0000] Endpoint n Data Register */ + + __IO uint32_t EPINTSTS; /*!< [0x0004] Endpoint n Interrupt Status Register */ + __IO uint32_t EPINTEN; /*!< [0x0008] Endpoint n Interrupt Enable Register */ + __I uint32_t EPDATCNT; /*!< [0x000c] Endpoint n Data Available Count Register */ + __IO uint32_t EPRSPCTL; /*!< [0x0010] Endpoint n Response Control Register */ + __IO uint32_t EPMPS; /*!< [0x0014] Endpoint n Maximum Packet Size Register */ + __IO uint32_t EPTXCNT; /*!< [0x0018] Endpoint n Transfer Count Register */ + __IO uint32_t EPCFG; /*!< [0x001c] Endpoint n Configuration Register */ + __IO uint32_t EPBUFST; /*!< [0x0020] Endpoint n RAM Start Address Register */ + __IO uint32_t EPBUFEND; /*!< [0x0024] Endpoint n RAM End Address Register */ + +} HSUSBD_EP_T; + +typedef struct +{ + + /** + * @var HSUSBD_T::GINTSTS + * Offset: 0x00 Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIF |USB Interrupt + * | | |This bit conveys the interrupt status for USB specific events endpoint + * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[1] |CEPIF |Control Endpoint Interrupt + * | | |This bit conveys the interrupt status for control endpoint + * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[2] |EPAIF |Endpoint a Interrupt + * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[3] |EPBIF |Endpoint B Interrupt + * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[4] |EPCIF |Endpoint C Interrupt + * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[5] |EPDIF |Endpoint D Interrupt + * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[6] |EPEIF |Endpoint E Interrupt + * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[7] |EPFIF |Endpoint F Interrupt + * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[8] |EPGIF |Endpoint G Interrupt + * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[9] |EPHIF |Endpoint H Interrupt + * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[10] |EPIIF |Endpoint I Interrupt + * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[11] |EPJIF |Endpoint J Interrupt + * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[12] |EPKIF |Endpoint K Interrupt + * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[13] |EPLIF |Endpoint L Interrupt + * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * @var HSUSBD_T::GINTEN + * Offset: 0x08 Global Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIEN |USB Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[1] |CEPIEN |Control Endpoint Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[2] |EPAIEN |Interrupt Enable Control for Endpoint a + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[3] |EPBIEN |Interrupt Enable Control for Endpoint B + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[4] |EPCIEN |Interrupt Enable Control for Endpoint C + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[5] |EPDIEN |Interrupt Enable Control for Endpoint D + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[6] |EPEIEN |Interrupt Enable Control for Endpoint E + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[7] |EPFIEN |Interrupt Enable Control for Endpoint F + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[8] |EPGIEN |Interrupt Enable Control for Endpoint G + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[9] |EPHIEN |Interrupt Enable Control for Endpoint H + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[10] |EPIIEN |Interrupt Enable Control for Endpoint I + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[11] |EPJIEN |Interrupt Enable Control for Endpoint J + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[12] |EPKIEN |Interrupt Enable Control for Endpoint K + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[13] |EPLIEN |Interrupt Enable Control for Endpoint L + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * @var HSUSBD_T::BUSINTSTS + * Offset: 0x10 USB Bus Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SOFIF |SOF Receive Control + * | | |This bit indicates when a start-of-frame packet has been received. + * | | |0 = No start-of-frame packet has been received. + * | | |1 = Start-of-frame packet has been received. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |RSTIF |Reset Status + * | | |When set, this bit indicates that either the USB root port reset is end. + * | | |0 = No USB root port reset is end. + * | | |1 = USB root port reset is end. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |RESUMEIF |Resume + * | | |When set, this bit indicates that a device resume has occurred. + * | | |0 = No device resume has occurred. + * | | |1 = Device resume has occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |SUSPENDIF |Suspend Request + * | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset + * | | |This bit is also set when a USB Suspend request is detected from the host. + * | | |0 = No USB Suspend request is detected from the host. + * | | |1= USB Suspend request is detected from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |HISPDIF |High-speed Settle + * | | |0 = No valid high-speed reset protocol is detected. + * | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |DMADONEIF |DMA Completion Interrupt + * | | |0 = No DMA transfer over. + * | | |1 = DMA transfer is over. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |PHYCLKVLDIF|Usable Clock Interrupt + * | | |0 = Usable clock is not available. + * | | |1 = Usable clock is available from the transceiver. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |VBUSDETIF |VBUS Detection Interrupt Status + * | | |0 = No VBUS is plug-in. + * | | |1 = VBUS is plug-in. + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_T::BUSINTEN + * Offset: 0x14 USB Bus Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SOFIEN |SOF Interrupt + * | | |This bit enables the SOF interrupt. + * | | |0 = SOF interrupt Disabled. + * | | |1 = SOF interrupt Enabled. + * |[1] |RSTIEN |Reset Status + * | | |This bit enables the USB-Reset interrupt. + * | | |0 = USB-Reset interrupt Disabled. + * | | |1 = USB-Reset interrupt Enabled. + * |[2] |RESUMEIEN |Resume + * | | |This bit enables the Resume interrupt. + * | | |0 = Resume interrupt Disabled. + * | | |1 = Resume interrupt Enabled. + * |[3] |SUSPENDIEN|Suspend Request + * | | |This bit enables the Suspend interrupt. + * | | |0 = Suspend interrupt Disabled. + * | | |1 = Suspend interrupt Enabled. + * |[4] |HISPDIEN |High-speed Settle + * | | |This bit enables the high-speed settle interrupt. + * | | |0 = High-speed settle interrupt Disabled. + * | | |1 = High-speed settle interrupt Enabled. + * |[5] |DMADONEIEN|DMA Completion Interrupt + * | | |This bit enables the DMA completion interrupt + * | | |0 = DMA completion interrupt Disabled. + * | | |1 = DMA completion interrupt Enabled. + * |[6] |PHYCLKVLDIEN|Usable Clock Interrupt + * | | |This bit enables the usable clock interrupt. + * | | |0 = Usable clock interrupt Disabled. + * | | |1 = Usable clock interrupt Enabled. + * |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Bit + * | | |This bit enables the VBUS floating detection interrupt. + * | | |0 = VBUS floating detection interrupt Disabled. + * | | |1 = VBUS floating detection interrupt Enabled. + * @var HSUSBD_T::OPER + * Offset: 0x18 USB Operational Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RESUMEEN |Generate Resume + * | | |0 = No Resume sequence to be initiated to the host. + * | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled + * | | |This bit is self-clearing. + * |[1] |HISPDEN |USB High-speed + * | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host. + * | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol. + * |[2] |CURSPD |USB Current Speed + * | | |0 = The device has settled in Full Speed. + * | | |1 = The USB device controller has settled in High-speed. + * @var HSUSBD_T::FRAMECNT + * Offset: 0x1C USB Frame Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |MFRAMECNT |Micro-frame Counter + * | | |This field contains the micro-frame number for the frame number in the frame counter field. + * |[13:3] |FRAMECNT |Frame Counter + * | | |This field contains the frame count from the most recent start-of-frame packet. + * @var HSUSBD_T::FADDR + * Offset: 0x20 USB Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Function Address + * | | |This field contains the current USB address of the device + * | | |This field is cleared when a root port reset is detected + * @var HSUSBD_T::TEST + * Offset: 0x24 USB Test Mode Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TESTMODE |Test Mode Selection + * | | |000 = Normal Operation. + * | | |001 = Test_J. + * | | |010 = Test_K. + * | | |011 = Test_SE0_NAK. + * | | |100 = Test_Packet. + * | | |101 = Test_Force_Enable. + * | | |110 = Reserved. + * | | |111 = Reserved. + * | | |Note: This field is cleared when root port reset is detected. + * @var HSUSBD_T::CEPDAT + * Offset: 0x28 Control-Endpoint Data Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DAT |Control-endpoint Data Buffer + * | | |Control endpoint data buffer for the buffer transaction (read or write). + * | | |Note: Only word access is supported. + * @var HSUSBD_T::CEPDAT_BYTE + * Offset: 0x28 Control-Endpoint Data Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Control-endpoint Data Buffer + * | | |Control endpoint data buffer for the buffer transaction (read or write). + * | | |Note: Only byte access is supported. + * @var HSUSBD_T::CEPCTL + * Offset: 0x2C Control-Endpoint Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |NAKCLR |No Acknowledge Control + * | | |This bit plays a crucial role in any control transfer. + * | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase + * | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request. + * | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received + * | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit. + * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. + * |[1] |STALLEN |Stall Enable Bit + * | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter + * | | |This is typically used for response to invalid/unsupported requests + * | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL + * | | |It is automatically cleared on receipt of a next setup-token + * | | |So, the local CPU need not write again to clear this bit. + * | | |0 = No sends a stall handshake in response to any in or out token thereafter. + * | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter. + * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. + * |[2] |ZEROLEN |Zero Packet Length + * | | |This bit is valid for Auto Validation mode only. + * | | |0 = No zero length packet to the host during Data stage to an IN token. + * | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token + * | | |This bit gets cleared once the zero length data packet is sent + * | | |So, the local CPU need not write again to clear this bit. + * |[3] |FLUSH |CEP-flush Bit + * | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. + * | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared + * | | |This bit is self-cleaning. + * @var HSUSBD_T::CEPINTEN + * Offset: 0x30 Control-Endpoint Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SETUPTKIEN|Setup Token Interrupt Enable Bit + * | | |0 = The SETUP token interrupt in Control Endpoint Disabled. + * | | |1 = The SETUP token interrupt in Control Endpoint Enabled. + * |[1] |SETUPPKIEN|Setup Packet Interrupt + * | | |0 = The SETUP packet interrupt in Control Endpoint Disabled. + * | | |1 = The SETUP packet interrupt in Control Endpoint Enabled. + * |[2] |OUTTKIEN |Out Token Interrupt + * | | |0 = The OUT token interrupt in Control Endpoint Disabled. + * | | |1 = The OUT token interrupt in Control Endpoint Enabled. + * |[3] |INTKIEN |In Token Interrupt + * | | |0 = The IN token interrupt in Control Endpoint Disabled. + * | | |1 = The IN token interrupt in Control Endpoint Enabled. + * |[4] |PINGIEN |Ping Token Interrupt + * | | |0 = The ping token interrupt in Control Endpoint Disabled. + * | | |1 = The ping token interrupt Control Endpoint Enabled. + * |[5] |TXPKIEN |Data Packet Transmitted Interrupt + * | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled. + * | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled. + * |[6] |RXPKIEN |Data Packet Received Interrupt + * | | |0 = The data received interrupt in Control Endpoint Disabled. + * | | |1 = The data received interrupt in Control Endpoint Enabled. + * |[7] |NAKIEN |NAK Sent Interrupt + * | | |0 = The NAK sent interrupt in Control Endpoint Disabled. + * | | |1 = The NAK sent interrupt in Control Endpoint Enabled. + * |[8] |STALLIEN |STALL Sent Interrupt + * | | |0 = The STALL sent interrupt in Control Endpoint Disabled. + * | | |1 = The STALL sent interrupt in Control Endpoint Enabled. + * |[9] |ERRIEN |USB Error Interrupt + * | | |0 = The USB Error interrupt in Control Endpoint Disabled. + * | | |1 = The USB Error interrupt in Control Endpoint Enabled. + * |[10] |STSDONEIEN|Status Completion Interrupt + * | | |0 = The Status Completion interrupt in Control Endpoint Disabled. + * | | |1 = The Status Completion interrupt in Control Endpoint Enabled. + * |[11] |BUFFULLIEN|Buffer Full Interrupt + * | | |0 = The buffer full interrupt in Control Endpoint Disabled. + * | | |1 = The buffer full interrupt in Control Endpoint Enabled. + * |[12] |BUFEMPTYIEN|Buffer Empty Interrupt + * | | |0 = The buffer empty interrupt in Control Endpoint Disabled. + * | | |1= The buffer empty interrupt in Control Endpoint Enabled. + * @var HSUSBD_T::CEPINTSTS + * Offset: 0x34 Control-Endpoint Interrupt Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SETUPTKIF |Setup Token Interrupt + * | | |0 = Not a Setup token is received. + * | | |1 = A Setup token is received. Writing 1 clears this status bit + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |SETUPPKIF |Setup Packet Interrupt + * | | |This bit must be cleared (by writing 1) before the next setup packet can be received + * | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer. + * | | |0 = Not a Setup packet has been received from the host. + * | | |1 = A Setup packet has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |OUTTKIF |Out Token Interrupt + * | | |0 = The control-endpoint does not received an OUT token from the host. + * | | |1 = The control-endpoint receives an OUT token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |INTKIF |in Token Interrupt + * | | |0 = The control-endpoint does not received an IN token from the host. + * | | |1 = The control-endpoint receives an IN token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |PINGIF |Ping Token Interrupt + * | | |0 = The control-endpoint does not received a ping token from the host. + * | | |1 = The control-endpoint receives a ping token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |TXPKIF |Data Packet Transmitted Interrupt + * | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. + * | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |RXPKIF |Data Packet Received Interrupt + * | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. + * | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |NAKIF |NAK Sent Interrupt + * | | |0 = Not a NAK-token is sent in response to an IN/OUT token. + * | | |1 = A NAK-token is sent in response to an IN/OUT token. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |STALLIF |STALL Sent Interrupt + * | | |0 = Not a stall-token is sent in response to an IN/OUT token. + * | | |1 = A stall-token is sent in response to an IN/OUT token. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |ERRIF |USB Error Interrupt + * | | |0 = No error had occurred during the transaction. + * | | |1 = An error had occurred during the transaction. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |STSDONEIF |Status Completion Interrupt + * | | |0 = Not a USB transaction has completed successfully. + * | | |1 = The status stage of a USB transaction has completed successfully. + * | | |Note: Write 1 to clear this bit to 0. + * |[11] |BUFFULLIF |Buffer Full Interrupt + * | | |0 = The control-endpoint buffer is not full. + * | | |1 = The control-endpoint buffer is full. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |BUFEMPTYIF|Buffer Empty Interrupt + * | | |0 = The control-endpoint buffer is not empty. + * | | |1 = The control-endpoint buffer is empty. + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_T::CEPTXCNT + * Offset: 0x38 Control-Endpoint In-transfer Data Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TXCNT |In-transfer Data Count + * | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register + * | | |When zero is written into this field, a zero length packet is sent to the host + * | | |When the count written in the register is more than the MPS, the data sent will be of only MPS. + * @var HSUSBD_T::CEPRXCNT + * Offset: 0x3C Control-Endpoint Out-transfer Data Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RXCNT |Out-transfer Data Count + * | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer. + * @var HSUSBD_T::CEPDATCNT + * Offset: 0x40 Control-Endpoint data count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATCNT |Control-endpoint Data Count + * | | |The USB device controller maintains the count of the data of control-endpoint. + * @var HSUSBD_T::SETUP1_0 + * Offset: 0x44 Setup1 & Setup0 bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP0 |Setup Byte 0[7:0] + * | | |This register provides byte 0 of the last setup packet received + * | | |For a Standard Device Request, the following bmRequestType information is returned. + * | | |Bit 7(Direction): + * | | | 0: Host to device + * | | | 1: Device to host + * | | |Bit 6-5 (Type): + * | | | 00: Standard + * | | | 01: Class + * | | | 10: Vendor + * | | | 11: Reserved + * | | |Bit 4-0 (Recipient) + * | | | 00000: Device + * | | | 00001: Interface + * | | | 00010: Endpoint + * | | | 00011: Other + * | | | Others: Reserved + * |[15:8] |SETUP1 |Setup Byte 1[15:8] + * | | |This register provides byte 1 of the last setup packet received + * | | |For a Standard Device Request, the following bRequest Code information is returned. + * | | |00000000 = Get Status. + * | | |00000001 = Clear Feature. + * | | |00000010 = Reserved. + * | | |00000011 = Set Feature. + * | | |00000100 = Reserved. + * | | |00000101 = Set Address. + * | | |00000110 = Get Descriptor. + * | | |00000111 = Set Descriptor. + * | | |00001000 = Get Configuration. + * | | |00001001 = Set Configuration. + * | | |00001010 = Get Interface. + * | | |00001011 = Set Interface. + * | | |00001100 = Sync Frame. + * @var HSUSBD_T::SETUP3_2 + * Offset: 0x48 Setup3 & Setup2 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP2 |Setup Byte 2 [7:0] + * | | |This register provides byte 2 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wValue field is returned + * |[15:8] |SETUP3 |Setup Byte 3 [15:8] + * | | |This register provides byte 3 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wValue field is returned. + * @var HSUSBD_T::SETUP5_4 + * Offset: 0x4C Setup5 & Setup4 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP4 |Setup Byte 4[7:0] + * | | |This register provides byte 4 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wIndex is returned. + * |[15:8] |SETUP5 |Setup Byte 5[15:8] + * | | |This register provides byte 5 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wIndex field is returned. + * @var HSUSBD_T::SETUP7_6 + * Offset: 0x50 Setup7 & Setup6 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP6 |Setup Byte 6[7:0] + * | | |This register provides byte 6 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wLength field is returned. + * |[15:8] |SETUP7 |Setup Byte 7[15:8] + * | | |This register provides byte 7 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wLength field is returned. + * @var HSUSBD_T::CEPBUFST + * Offset: 0x54 Control Endpoint RAM Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |SADDR |Control-endpoint Start Address + * | | |This is the start-address of the RAM space allocated for the control-endpoint. + * @var HSUSBD_T::CEPBUFEND + * Offset: 0x58 Control Endpoint RAM End Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |EADDR |Control-endpoint End Address + * | | |This is the end-address of the RAM space allocated for the control-endpoint. + * @var HSUSBD_T::DMACTL + * Offset: 0x5C DMA Control Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |DMA Endpoint Address Bits + * | | |Used to define the Endpoint Address + * |[4] |DMARD |DMA Operation + * | | |0 : The operation is a DMA write (read from USB buffer) + * | | |DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation. + * | | |1 : The operation is a DMA read (write to USB buffer). + * |[5] |DMAEN |DMA Enable Bit + * | | |0 : DMA function Disabled. + * | | |1 : DMA function Enabled. + * |[6] |SGEN |Scatter Gather Function Enable Bit + * | | |0 : Scatter gather function Disabled. + * | | |1 : Scatter gather function Enabled. + * |[7] |DMARST |Reset DMA State Machine + * | | |0 : No reset the DMA state machine. + * | | |1 : Reset the DMA state machine. + * |[8] |SVINEP |Serve IN Endpoint + * | | |This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint. + * | | |0: DMA serves OUT endpoint + * | | |1: DMA serves IN endpoint + * @var HSUSBD_T::DMACNT + * Offset: 0x60 DMA Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[19:0] |DMACNT |DMA Transfer Count + * | | |The transfer count of the DMA operation to be performed is written to this register. + * @var HSUSBD_T::DMAADDR + * Offset: 0x700 AHB DMA Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMAADDR |DMAADDR + * | | |The register specifies the address from which the DMA has to read / write + * | | |The address must WORD (32-bit) aligned. + * @var HSUSBD_T::PHYCTL + * Offset: 0x704 USB PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |DPPUEN |DP Pull-up + * | | |0 = Pull-up resistor on D+ Disabled. + * | | |1 = Pull-up resistor on D+ Enabled. + * |[9] |PHYEN |PHY Suspend Enable Bit + * | | |0 = The USB PHY is suspend. + * | | |1 = The USB PHY is not suspend. + * |[24] |WKEN |Wake-up Enable Bit + * | | |0 = The wake-up function Disabled. + * | | |1 = The wake-up function Enabled. + * |[31] |VBUSDET |VBUS Status + * | | |0 = The VBUS is not detected yet. + * | | |1 = The VBUS is detected. + */ + + __I uint32_t GINTSTS; /*!< [0x0000] Global Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t GINTEN; /*!< [0x0008] Global Interrupt Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t BUSINTSTS; /*!< [0x0010] USB Bus Interrupt Status Register */ + __IO uint32_t BUSINTEN; /*!< [0x0014] USB Bus Interrupt Enable Register */ + __IO uint32_t OPER; /*!< [0x0018] USB Operational Register */ + __I uint32_t FRAMECNT; /*!< [0x001c] USB Frame Count Register */ + __IO uint32_t FADDR; /*!< [0x0020] USB Function Address Register */ + __IO uint32_t TEST; /*!< [0x0024] USB Test Mode Register */ + + union + { + __IO uint32_t CEPDAT; + __IO uint8_t CEPDAT_BYTE; + + }; /*!< [0x0028] Control-Endpoint Data Buffer */ + + __IO uint32_t CEPCTL; /*!< [0x002c] Control-Endpoint Control Register */ + __IO uint32_t CEPINTEN; /*!< [0x0030] Control-Endpoint Interrupt Enable */ + __IO uint32_t CEPINTSTS; /*!< [0x0034] Control-Endpoint Interrupt Status */ + __IO uint32_t CEPTXCNT; /*!< [0x0038] Control-Endpoint In-transfer Data Count */ + __I uint32_t CEPRXCNT; /*!< [0x003c] Control-Endpoint Out-transfer Data Count */ + __I uint32_t CEPDATCNT; /*!< [0x0040] Control-Endpoint data count */ + __I uint32_t SETUP1_0; /*!< [0x0044] Setup1 & Setup0 bytes */ + __I uint32_t SETUP3_2; /*!< [0x0048] Setup3 & Setup2 Bytes */ + __I uint32_t SETUP5_4; /*!< [0x004c] Setup5 & Setup4 Bytes */ + __I uint32_t SETUP7_6; /*!< [0x0050] Setup7 & Setup6 Bytes */ + __IO uint32_t CEPBUFST; /*!< [0x0054] Control Endpoint RAM Start Address Register */ + __IO uint32_t CEPBUFEND; /*!< [0x0058] Control Endpoint RAM End Address Register */ + __IO uint32_t DMACTL; /*!< [0x005c] DMA Control Status Register */ + __IO uint32_t DMACNT; /*!< [0x0060] DMA Count Register */ + + HSUSBD_EP_T EP[12]; + + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[303]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMAADDR; /*!< [0x0700] AHB DMA Address Register */ + __IO uint32_t PHYCTL; /*!< [0x0704] USB PHY Control Register */ + +} HSUSBD_T; + +/** + @addtogroup HSUSBD_CONST HSUSBD Bit Field Definition + Constant Definitions for HSUSBD Controller +@{ */ + +#define HSUSBD_GINTSTS_USBIF_Pos (0) /*!< HSUSBD_T::GINTSTS: USBIF Position */ +#define HSUSBD_GINTSTS_USBIF_Msk (0x1ul << HSUSBD_GINTSTS_USBIF_Pos) /*!< HSUSBD_T::GINTSTS: USBIF Mask */ + +#define HSUSBD_GINTSTS_CEPIF_Pos (1) /*!< HSUSBD_T::GINTSTS: CEPIF Position */ +#define HSUSBD_GINTSTS_CEPIF_Msk (0x1ul << HSUSBD_GINTSTS_CEPIF_Pos) /*!< HSUSBD_T::GINTSTS: CEPIF Mask */ + +#define HSUSBD_GINTSTS_EPAIF_Pos (2) /*!< HSUSBD_T::GINTSTS: EPAIF Position */ +#define HSUSBD_GINTSTS_EPAIF_Msk (0x1ul << HSUSBD_GINTSTS_EPAIF_Pos) /*!< HSUSBD_T::GINTSTS: EPAIF Mask */ + +#define HSUSBD_GINTSTS_EPBIF_Pos (3) /*!< HSUSBD_T::GINTSTS: EPBIF Position */ +#define HSUSBD_GINTSTS_EPBIF_Msk (0x1ul << HSUSBD_GINTSTS_EPBIF_Pos) /*!< HSUSBD_T::GINTSTS: EPBIF Mask */ + +#define HSUSBD_GINTSTS_EPCIF_Pos (4) /*!< HSUSBD_T::GINTSTS: EPCIF Position */ +#define HSUSBD_GINTSTS_EPCIF_Msk (0x1ul << HSUSBD_GINTSTS_EPCIF_Pos) /*!< HSUSBD_T::GINTSTS: EPCIF Mask */ + +#define HSUSBD_GINTSTS_EPDIF_Pos (5) /*!< HSUSBD_T::GINTSTS: EPDIF Position */ +#define HSUSBD_GINTSTS_EPDIF_Msk (0x1ul << HSUSBD_GINTSTS_EPDIF_Pos) /*!< HSUSBD_T::GINTSTS: EPDIF Mask */ + +#define HSUSBD_GINTSTS_EPEIF_Pos (6) /*!< HSUSBD_T::GINTSTS: EPEIF Position */ +#define HSUSBD_GINTSTS_EPEIF_Msk (0x1ul << HSUSBD_GINTSTS_EPEIF_Pos) /*!< HSUSBD_T::GINTSTS: EPEIF Mask */ + +#define HSUSBD_GINTSTS_EPFIF_Pos (7) /*!< HSUSBD_T::GINTSTS: EPFIF Position */ +#define HSUSBD_GINTSTS_EPFIF_Msk (0x1ul << HSUSBD_GINTSTS_EPFIF_Pos) /*!< HSUSBD_T::GINTSTS: EPFIF Mask */ + +#define HSUSBD_GINTSTS_EPGIF_Pos (8) /*!< HSUSBD_T::GINTSTS: EPGIF Position */ +#define HSUSBD_GINTSTS_EPGIF_Msk (0x1ul << HSUSBD_GINTSTS_EPGIF_Pos) /*!< HSUSBD_T::GINTSTS: EPGIF Mask */ + +#define HSUSBD_GINTSTS_EPHIF_Pos (9) /*!< HSUSBD_T::GINTSTS: EPHIF Position */ +#define HSUSBD_GINTSTS_EPHIF_Msk (0x1ul << HSUSBD_GINTSTS_EPHIF_Pos) /*!< HSUSBD_T::GINTSTS: EPHIF Mask */ + +#define HSUSBD_GINTSTS_EPIIF_Pos (10) /*!< HSUSBD_T::GINTSTS: EPIIF Position */ +#define HSUSBD_GINTSTS_EPIIF_Msk (0x1ul << HSUSBD_GINTSTS_EPIIF_Pos) /*!< HSUSBD_T::GINTSTS: EPIIF Mask */ + +#define HSUSBD_GINTSTS_EPJIF_Pos (11) /*!< HSUSBD_T::GINTSTS: EPJIF Position */ +#define HSUSBD_GINTSTS_EPJIF_Msk (0x1ul << HSUSBD_GINTSTS_EPJIF_Pos) /*!< HSUSBD_T::GINTSTS: EPJIF Mask */ + +#define HSUSBD_GINTSTS_EPKIF_Pos (12) /*!< HSUSBD_T::GINTSTS: EPKIF Position */ +#define HSUSBD_GINTSTS_EPKIF_Msk (0x1ul << HSUSBD_GINTSTS_EPKIF_Pos) /*!< HSUSBD_T::GINTSTS: EPKIF Mask */ + +#define HSUSBD_GINTSTS_EPLIF_Pos (13) /*!< HSUSBD_T::GINTSTS: EPLIF Position */ +#define HSUSBD_GINTSTS_EPLIF_Msk (0x1ul << HSUSBD_GINTSTS_EPLIF_Pos) /*!< HSUSBD_T::GINTSTS: EPLIF Mask */ + +#define HSUSBD_GINTEN_USBIEN_Pos (0) /*!< HSUSBD_T::GINTEN: USBIEN Position */ +#define HSUSBD_GINTEN_USBIEN_Msk (0x1ul << HSUSBD_GINTEN_USBIEN_Pos) /*!< HSUSBD_T::GINTEN: USBIEN Mask */ + +#define HSUSBD_GINTEN_CEPIEN_Pos (1) /*!< HSUSBD_T::GINTEN: CEPIEN Position */ +#define HSUSBD_GINTEN_CEPIEN_Msk (0x1ul << HSUSBD_GINTEN_CEPIEN_Pos) /*!< HSUSBD_T::GINTEN: CEPIEN Mask */ + +#define HSUSBD_GINTEN_EPAIEN_Pos (2) /*!< HSUSBD_T::GINTEN: EPAIEN Position */ +#define HSUSBD_GINTEN_EPAIEN_Msk (0x1ul << HSUSBD_GINTEN_EPAIEN_Pos) /*!< HSUSBD_T::GINTEN: EPAIEN Mask */ + +#define HSUSBD_GINTEN_EPBIEN_Pos (3) /*!< HSUSBD_T::GINTEN: EPBIEN Position */ +#define HSUSBD_GINTEN_EPBIEN_Msk (0x1ul << HSUSBD_GINTEN_EPBIEN_Pos) /*!< HSUSBD_T::GINTEN: EPBIEN Mask */ + +#define HSUSBD_GINTEN_EPCIEN_Pos (4) /*!< HSUSBD_T::GINTEN: EPCIEN Position */ +#define HSUSBD_GINTEN_EPCIEN_Msk (0x1ul << HSUSBD_GINTEN_EPCIEN_Pos) /*!< HSUSBD_T::GINTEN: EPCIEN Mask */ + +#define HSUSBD_GINTEN_EPDIEN_Pos (5) /*!< HSUSBD_T::GINTEN: EPDIEN Position */ +#define HSUSBD_GINTEN_EPDIEN_Msk (0x1ul << HSUSBD_GINTEN_EPDIEN_Pos) /*!< HSUSBD_T::GINTEN: EPDIEN Mask */ + +#define HSUSBD_GINTEN_EPEIEN_Pos (6) /*!< HSUSBD_T::GINTEN: EPEIEN Position */ +#define HSUSBD_GINTEN_EPEIEN_Msk (0x1ul << HSUSBD_GINTEN_EPEIEN_Pos) /*!< HSUSBD_T::GINTEN: EPEIEN Mask */ + +#define HSUSBD_GINTEN_EPFIEN_Pos (7) /*!< HSUSBD_T::GINTEN: EPFIEN Position */ +#define HSUSBD_GINTEN_EPFIEN_Msk (0x1ul << HSUSBD_GINTEN_EPFIEN_Pos) /*!< HSUSBD_T::GINTEN: EPFIEN Mask */ + +#define HSUSBD_GINTEN_EPGIEN_Pos (8) /*!< HSUSBD_T::GINTEN: EPGIEN Position */ +#define HSUSBD_GINTEN_EPGIEN_Msk (0x1ul << HSUSBD_GINTEN_EPGIEN_Pos) /*!< HSUSBD_T::GINTEN: EPGIEN Mask */ + +#define HSUSBD_GINTEN_EPHIEN_Pos (9) /*!< HSUSBD_T::GINTEN: EPHIEN Position */ +#define HSUSBD_GINTEN_EPHIEN_Msk (0x1ul << HSUSBD_GINTEN_EPHIEN_Pos) /*!< HSUSBD_T::GINTEN: EPHIEN Mask */ + +#define HSUSBD_GINTEN_EPIIEN_Pos (10) /*!< HSUSBD_T::GINTEN: EPIIEN Position */ +#define HSUSBD_GINTEN_EPIIEN_Msk (0x1ul << HSUSBD_GINTEN_EPIIEN_Pos) /*!< HSUSBD_T::GINTEN: EPIIEN Mask */ + +#define HSUSBD_GINTEN_EPJIEN_Pos (11) /*!< HSUSBD_T::GINTEN: EPJIEN Position */ +#define HSUSBD_GINTEN_EPJIEN_Msk (0x1ul << HSUSBD_GINTEN_EPJIEN_Pos) /*!< HSUSBD_T::GINTEN: EPJIEN Mask */ + +#define HSUSBD_GINTEN_EPKIEN_Pos (12) /*!< HSUSBD_T::GINTEN: EPKIEN Position */ +#define HSUSBD_GINTEN_EPKIEN_Msk (0x1ul << HSUSBD_GINTEN_EPKIEN_Pos) /*!< HSUSBD_T::GINTEN: EPKIEN Mask */ + +#define HSUSBD_GINTEN_EPLIEN_Pos (13) /*!< HSUSBD_T::GINTEN: EPLIEN Position */ +#define HSUSBD_GINTEN_EPLIEN_Msk (0x1ul << HSUSBD_GINTEN_EPLIEN_Pos) /*!< HSUSBD_T::GINTEN: EPLIEN Mask */ + +#define HSUSBD_BUSINTSTS_SOFIF_Pos (0) /*!< HSUSBD_T::BUSINTSTS: SOFIF Position */ +#define HSUSBD_BUSINTSTS_SOFIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SOFIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SOFIF Mask */ + +#define HSUSBD_BUSINTSTS_RSTIF_Pos (1) /*!< HSUSBD_T::BUSINTSTS: RSTIF Position */ +#define HSUSBD_BUSINTSTS_RSTIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RSTIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RSTIF Mask */ + +#define HSUSBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Position */ +#define HSUSBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RESUMEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Mask */ + +#define HSUSBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Position*/ +#define HSUSBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SUSPENDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Mask */ + +#define HSUSBD_BUSINTSTS_HISPDIF_Pos (4) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Position */ +#define HSUSBD_BUSINTSTS_HISPDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_HISPDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Mask */ + +#define HSUSBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Position*/ +#define HSUSBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_DMADONEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Mask */ + +#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Position*/ +#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Mask */ + +#define HSUSBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Position*/ +#define HSUSBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << HSUSBD_BUSINTSTS_VBUSDETIF_Pos) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Mask */ + +#define HSUSBD_BUSINTEN_SOFIEN_Pos (0) /*!< HSUSBD_T::BUSINTEN: SOFIEN Position */ +#define HSUSBD_BUSINTEN_SOFIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SOFIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SOFIEN Mask */ + +#define HSUSBD_BUSINTEN_RSTIEN_Pos (1) /*!< HSUSBD_T::BUSINTEN: RSTIEN Position */ +#define HSUSBD_BUSINTEN_RSTIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RSTIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RSTIEN Mask */ + +#define HSUSBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Position */ +#define HSUSBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RESUMEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Mask */ + +#define HSUSBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Position*/ +#define HSUSBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SUSPENDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Mask */ + +#define HSUSBD_BUSINTEN_HISPDIEN_Pos (4) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Position */ +#define HSUSBD_BUSINTEN_HISPDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_HISPDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Mask */ + +#define HSUSBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Position*/ +#define HSUSBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_DMADONEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Mask */ + +#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Position*/ +#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Mask */ + +#define HSUSBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Position*/ +#define HSUSBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << HSUSBD_BUSINTEN_VBUSDETIEN_Pos) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Mask */ + +#define HSUSBD_OPER_RESUMEEN_Pos (0) /*!< HSUSBD_T::OPER: RESUMEEN Position */ +#define HSUSBD_OPER_RESUMEEN_Msk (0x1ul << HSUSBD_OPER_RESUMEEN_Pos) /*!< HSUSBD_T::OPER: RESUMEEN Mask */ + +#define HSUSBD_OPER_HISPDEN_Pos (1) /*!< HSUSBD_T::OPER: HISPDEN Position */ +#define HSUSBD_OPER_HISPDEN_Msk (0x1ul << HSUSBD_OPER_HISPDEN_Pos) /*!< HSUSBD_T::OPER: HISPDEN Mask */ + +#define HSUSBD_OPER_CURSPD_Pos (2) /*!< HSUSBD_T::OPER: CURSPD Position */ +#define HSUSBD_OPER_CURSPD_Msk (0x1ul << HSUSBD_OPER_CURSPD_Pos) /*!< HSUSBD_T::OPER: CURSPD Mask */ + +#define HSUSBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Position */ +#define HSUSBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << HSUSBD_FRAMECNT_MFRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Mask */ + +#define HSUSBD_FRAMECNT_FRAMECNT_Pos (3) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Position */ +#define HSUSBD_FRAMECNT_FRAMECNT_Msk (0x7fful << HSUSBD_FRAMECNT_FRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Mask */ + +#define HSUSBD_FADDR_FADDR_Pos (0) /*!< HSUSBD_T::FADDR: FADDR Position */ +#define HSUSBD_FADDR_FADDR_Msk (0x7ful << HSUSBD_FADDR_FADDR_Pos) /*!< HSUSBD_T::FADDR: FADDR Mask */ + +#define HSUSBD_TEST_TESTMODE_Pos (0) /*!< HSUSBD_T::TEST: TESTMODE Position */ +#define HSUSBD_TEST_TESTMODE_Msk (0x7ul << HSUSBD_TEST_TESTMODE_Pos) /*!< HSUSBD_T::TEST: TESTMODE Mask */ + +#define HSUSBD_CEPDAT_DAT_Pos (0) /*!< HSUSBD_T::CEPDAT: DAT Position */ +#define HSUSBD_CEPDAT_DAT_Msk (0xfffffffful << HSUSBD_CEPDAT_DAT_Pos) /*!< HSUSBD_T::CEPDAT: DAT Mask */ + +#define HSUSBD_CEPCTL_NAKCLR_Pos (0) /*!< HSUSBD_T::CEPCTL: NAKCLR Position */ +#define HSUSBD_CEPCTL_NAKCLR_Msk (0x1ul << HSUSBD_CEPCTL_NAKCLR_Pos) /*!< HSUSBD_T::CEPCTL: NAKCLR Mask */ + +#define HSUSBD_CEPCTL_STALLEN_Pos (1) /*!< HSUSBD_T::CEPCTL: STALLEN Position */ +#define HSUSBD_CEPCTL_STALLEN_Msk (0x1ul << HSUSBD_CEPCTL_STALLEN_Pos) /*!< HSUSBD_T::CEPCTL: STALLEN Mask */ + +#define HSUSBD_CEPCTL_ZEROLEN_Pos (2) /*!< HSUSBD_T::CEPCTL: ZEROLEN Position */ +#define HSUSBD_CEPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_CEPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::CEPCTL: ZEROLEN Mask */ + +#define HSUSBD_CEPCTL_FLUSH_Pos (3) /*!< HSUSBD_T::CEPCTL: FLUSH Position */ +#define HSUSBD_CEPCTL_FLUSH_Msk (0x1ul << HSUSBD_CEPCTL_FLUSH_Pos) /*!< HSUSBD_T::CEPCTL: FLUSH Mask */ + +#define HSUSBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Position*/ +#define HSUSBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Mask */ + +#define HSUSBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Position*/ +#define HSUSBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Mask */ + +#define HSUSBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Position */ +#define HSUSBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Mask */ + +#define HSUSBD_CEPINTEN_INTKIEN_Pos (3) /*!< HSUSBD_T::CEPINTEN: INTKIEN Position */ +#define HSUSBD_CEPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: INTKIEN Mask */ + +#define HSUSBD_CEPINTEN_PINGIEN_Pos (4) /*!< HSUSBD_T::CEPINTEN: PINGIEN Position */ +#define HSUSBD_CEPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_CEPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::CEPINTEN: PINGIEN Mask */ + +#define HSUSBD_CEPINTEN_TXPKIEN_Pos (5) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Position */ +#define HSUSBD_CEPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Mask */ + +#define HSUSBD_CEPINTEN_RXPKIEN_Pos (6) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Position */ +#define HSUSBD_CEPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Mask */ + +#define HSUSBD_CEPINTEN_NAKIEN_Pos (7) /*!< HSUSBD_T::CEPINTEN: NAKIEN Position */ +#define HSUSBD_CEPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: NAKIEN Mask */ + +#define HSUSBD_CEPINTEN_STALLIEN_Pos (8) /*!< HSUSBD_T::CEPINTEN: STALLIEN Position */ +#define HSUSBD_CEPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STALLIEN Mask */ + +#define HSUSBD_CEPINTEN_ERRIEN_Pos (9) /*!< HSUSBD_T::CEPINTEN: ERRIEN Position */ +#define HSUSBD_CEPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_CEPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::CEPINTEN: ERRIEN Mask */ + +#define HSUSBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Position*/ +#define HSUSBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STSDONEIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Mask */ + +#define HSUSBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Position*/ +#define HSUSBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Mask */ + +#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Position*/ +#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Mask */ + +#define HSUSBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Position*/ +#define HSUSBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Mask */ + +#define HSUSBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Position*/ +#define HSUSBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Mask */ + +#define HSUSBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Position */ +#define HSUSBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Mask */ + +#define HSUSBD_CEPINTSTS_INTKIF_Pos (3) /*!< HSUSBD_T::CEPINTSTS: INTKIF Position */ +#define HSUSBD_CEPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: INTKIF Mask */ + +#define HSUSBD_CEPINTSTS_PINGIF_Pos (4) /*!< HSUSBD_T::CEPINTSTS: PINGIF Position */ +#define HSUSBD_CEPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_CEPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::CEPINTSTS: PINGIF Mask */ + +#define HSUSBD_CEPINTSTS_TXPKIF_Pos (5) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Position */ +#define HSUSBD_CEPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Mask */ + +#define HSUSBD_CEPINTSTS_RXPKIF_Pos (6) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Position */ +#define HSUSBD_CEPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Mask */ + +#define HSUSBD_CEPINTSTS_NAKIF_Pos (7) /*!< HSUSBD_T::CEPINTSTS: NAKIF Position */ +#define HSUSBD_CEPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: NAKIF Mask */ + +#define HSUSBD_CEPINTSTS_STALLIF_Pos (8) /*!< HSUSBD_T::CEPINTSTS: STALLIF Position */ +#define HSUSBD_CEPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STALLIF Mask */ + +#define HSUSBD_CEPINTSTS_ERRIF_Pos (9) /*!< HSUSBD_T::CEPINTSTS: ERRIF Position */ +#define HSUSBD_CEPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_CEPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::CEPINTSTS: ERRIF Mask */ + +#define HSUSBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Position*/ +#define HSUSBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STSDONEIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Mask */ + +#define HSUSBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Position*/ +#define HSUSBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Mask */ + +#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Position*/ +#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Mask */ + +#define HSUSBD_CEPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::CEPTXCNT: TXCNT Position */ +#define HSUSBD_CEPTXCNT_TXCNT_Msk (0xfful << HSUSBD_CEPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::CEPTXCNT: TXCNT Mask */ + +#define HSUSBD_CEPRXCNT_RXCNT_Pos (0) /*!< HSUSBD_T::CEPRXCNT: RXCNT Position */ +#define HSUSBD_CEPRXCNT_RXCNT_Msk (0xfful << HSUSBD_CEPRXCNT_RXCNT_Pos) /*!< HSUSBD_T::CEPRXCNT: RXCNT Mask */ + +#define HSUSBD_CEPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::CEPDATCNT: DATCNT Position */ +#define HSUSBD_CEPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_CEPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::CEPDATCNT: DATCNT Mask */ + +#define HSUSBD_SETUP1_0_SETUP0_Pos (0) /*!< HSUSBD_T::SETUP1_0: SETUP0 Position */ +#define HSUSBD_SETUP1_0_SETUP0_Msk (0xfful << HSUSBD_SETUP1_0_SETUP0_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP0 Mask */ + +#define HSUSBD_SETUP1_0_SETUP1_Pos (8) /*!< HSUSBD_T::SETUP1_0: SETUP1 Position */ +#define HSUSBD_SETUP1_0_SETUP1_Msk (0xfful << HSUSBD_SETUP1_0_SETUP1_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP1 Mask */ + +#define HSUSBD_SETUP3_2_SETUP2_Pos (0) /*!< HSUSBD_T::SETUP3_2: SETUP2 Position */ +#define HSUSBD_SETUP3_2_SETUP2_Msk (0xfful << HSUSBD_SETUP3_2_SETUP2_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP2 Mask */ + +#define HSUSBD_SETUP3_2_SETUP3_Pos (8) /*!< HSUSBD_T::SETUP3_2: SETUP3 Position */ +#define HSUSBD_SETUP3_2_SETUP3_Msk (0xfful << HSUSBD_SETUP3_2_SETUP3_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP3 Mask */ + +#define HSUSBD_SETUP5_4_SETUP4_Pos (0) /*!< HSUSBD_T::SETUP5_4: SETUP4 Position */ +#define HSUSBD_SETUP5_4_SETUP4_Msk (0xfful << HSUSBD_SETUP5_4_SETUP4_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP4 Mask */ + +#define HSUSBD_SETUP5_4_SETUP5_Pos (8) /*!< HSUSBD_T::SETUP5_4: SETUP5 Position */ +#define HSUSBD_SETUP5_4_SETUP5_Msk (0xfful << HSUSBD_SETUP5_4_SETUP5_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP5 Mask */ + +#define HSUSBD_SETUP7_6_SETUP6_Pos (0) /*!< HSUSBD_T::SETUP7_6: SETUP6 Position */ +#define HSUSBD_SETUP7_6_SETUP6_Msk (0xfful << HSUSBD_SETUP7_6_SETUP6_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP6 Mask */ + +#define HSUSBD_SETUP7_6_SETUP7_Pos (8) /*!< HSUSBD_T::SETUP7_6: SETUP7 Position */ +#define HSUSBD_SETUP7_6_SETUP7_Msk (0xfful << HSUSBD_SETUP7_6_SETUP7_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP7 Mask */ + +#define HSUSBD_CEPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::CEPBUFST: SADDR Position */ +#define HSUSBD_CEPBUFST_SADDR_Msk (0xffful << HSUSBD_CEPBUFST_SADDR_Pos) /*!< HSUSBD_T::CEPBUFST: SADDR Mask */ + +#define HSUSBD_CEPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::CEPBUFEND: EADDR Position */ +#define HSUSBD_CEPBUFEND_EADDR_Msk (0xffful << HSUSBD_CEPBUFEND_EADDR_Pos) /*!< HSUSBD_T::CEPBUFEND: EADDR Mask */ + +#define HSUSBD_DMACTL_EPNUM_Pos (0) /*!< HSUSBD_T::DMACTL: EPNUM Position */ +#define HSUSBD_DMACTL_EPNUM_Msk (0xful << HSUSBD_DMACTL_EPNUM_Pos) /*!< HSUSBD_T::DMACTL: EPNUM Mask */ + +#define HSUSBD_DMACTL_DMARD_Pos (4) /*!< HSUSBD_T::DMACTL: DMARD Position */ +#define HSUSBD_DMACTL_DMARD_Msk (0x1ul << HSUSBD_DMACTL_DMARD_Pos) /*!< HSUSBD_T::DMACTL: DMARD Mask */ + +#define HSUSBD_DMACTL_DMAEN_Pos (5) /*!< HSUSBD_T::DMACTL: DMAEN Position */ +#define HSUSBD_DMACTL_DMAEN_Msk (0x1ul << HSUSBD_DMACTL_DMAEN_Pos) /*!< HSUSBD_T::DMACTL: DMAEN Mask */ + +#define HSUSBD_DMACTL_SGEN_Pos (6) /*!< HSUSBD_T::DMACTL: SGEN Position */ +#define HSUSBD_DMACTL_SGEN_Msk (0x1ul << HSUSBD_DMACTL_SGEN_Pos) /*!< HSUSBD_T::DMACTL: SGEN Mask */ + +#define HSUSBD_DMACTL_DMARST_Pos (7) /*!< HSUSBD_T::DMACTL: DMARST Position */ +#define HSUSBD_DMACTL_DMARST_Msk (0x1ul << HSUSBD_DMACTL_DMARST_Pos) /*!< HSUSBD_T::DMACTL: DMARST Mask */ + +#define HSUSBD_DMACTL_SVINEP_Pos (8) /*!< HSUSBD_T::DMACTL: SVINEP Position */ +#define HSUSBD_DMACTL_SVINEP_Msk (0x1ul << HSUSBD_DMACTL_SVINEP_Pos) /*!< HSUSBD_T::DMACTL: SVINEP Mask */ + +#define HSUSBD_DMACNT_DMACNT_Pos (0) /*!< HSUSBD_T::DMACNT: DMACNT Position */ +#define HSUSBD_DMACNT_DMACNT_Msk (0xffffful << HSUSBD_DMACNT_DMACNT_Pos) /*!< HSUSBD_T::DMACNT: DMACNT Mask */ + +#define HSUSBD_EPDAT_EPDAT_Pos (0) /*!< HSUSBD_T::EPDAT: EPDAT Position */ +#define HSUSBD_EPDAT_EPDAT_Msk (0xfffffffful << HSUSBD_EPDAT_EPDAT_Pos) /*!< HSUSBD_T::EPDAT: EPDAT Mask */ + +#define HSUSBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Position */ +#define HSUSBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Mask */ + +#define HSUSBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Position*/ +#define HSUSBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Mask */ + +#define HSUSBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Position */ +#define HSUSBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTTXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Mask */ + +#define HSUSBD_EPINTSTS_TXPKIF_Pos (3) /*!< HSUSBD_T::EPINTSTS: TXPKIF Position */ +#define HSUSBD_EPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: TXPKIF Mask */ + +#define HSUSBD_EPINTSTS_RXPKIF_Pos (4) /*!< HSUSBD_T::EPINTSTS: RXPKIF Position */ +#define HSUSBD_EPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: RXPKIF Mask */ + +#define HSUSBD_EPINTSTS_OUTTKIF_Pos (5) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Position */ +#define HSUSBD_EPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Mask */ + +#define HSUSBD_EPINTSTS_INTKIF_Pos (6) /*!< HSUSBD_T::EPINTSTS: INTKIF Position */ +#define HSUSBD_EPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: INTKIF Mask */ + +#define HSUSBD_EPINTSTS_PINGIF_Pos (7) /*!< HSUSBD_T::EPINTSTS: PINGIF Position */ +#define HSUSBD_EPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_EPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::EPINTSTS: PINGIF Mask */ + +#define HSUSBD_EPINTSTS_NAKIF_Pos (8) /*!< HSUSBD_T::EPINTSTS: NAKIF Position */ +#define HSUSBD_EPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_EPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::EPINTSTS: NAKIF Mask */ + +#define HSUSBD_EPINTSTS_STALLIF_Pos (9) /*!< HSUSBD_T::EPINTSTS: STALLIF Position */ +#define HSUSBD_EPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_EPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::EPINTSTS: STALLIF Mask */ + +#define HSUSBD_EPINTSTS_NYETIF_Pos (10) /*!< HSUSBD_T::EPINTSTS: NYETIF Position */ +#define HSUSBD_EPINTSTS_NYETIF_Msk (0x1ul << HSUSBD_EPINTSTS_NYETIF_Pos) /*!< HSUSBD_T::EPINTSTS: NYETIF Mask */ + +#define HSUSBD_EPINTSTS_ERRIF_Pos (11) /*!< HSUSBD_T::EPINTSTS: ERRIF Position */ +#define HSUSBD_EPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_EPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::EPINTSTS: ERRIF Mask */ + +#define HSUSBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Position */ +#define HSUSBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTRXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Mask */ + +#define HSUSBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Position */ +#define HSUSBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Mask */ + +#define HSUSBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Position*/ +#define HSUSBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Mask */ + +#define HSUSBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Position */ +#define HSUSBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTTXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Mask */ + +#define HSUSBD_EPINTEN_TXPKIEN_Pos (3) /*!< HSUSBD_T::EPINTEN: TXPKIEN Position */ +#define HSUSBD_EPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: TXPKIEN Mask */ + +#define HSUSBD_EPINTEN_RXPKIEN_Pos (4) /*!< HSUSBD_T::EPINTEN: RXPKIEN Position */ +#define HSUSBD_EPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: RXPKIEN Mask */ + +#define HSUSBD_EPINTEN_OUTTKIEN_Pos (5) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Position */ +#define HSUSBD_EPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Mask */ + +#define HSUSBD_EPINTEN_INTKIEN_Pos (6) /*!< HSUSBD_T::EPINTEN: INTKIEN Position */ +#define HSUSBD_EPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: INTKIEN Mask */ + +#define HSUSBD_EPINTEN_PINGIEN_Pos (7) /*!< HSUSBD_T::EPINTEN: PINGIEN Position */ +#define HSUSBD_EPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_EPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::EPINTEN: PINGIEN Mask */ + +#define HSUSBD_EPINTEN_NAKIEN_Pos (8) /*!< HSUSBD_T::EPINTEN: NAKIEN Position */ +#define HSUSBD_EPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_EPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::EPINTEN: NAKIEN Mask */ + +#define HSUSBD_EPINTEN_STALLIEN_Pos (9) /*!< HSUSBD_T::EPINTEN: STALLIEN Position */ +#define HSUSBD_EPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_EPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::EPINTEN: STALLIEN Mask */ + +#define HSUSBD_EPINTEN_NYETIEN_Pos (10) /*!< HSUSBD_T::EPINTEN: NYETIEN Position */ +#define HSUSBD_EPINTEN_NYETIEN_Msk (0x1ul << HSUSBD_EPINTEN_NYETIEN_Pos) /*!< HSUSBD_T::EPINTEN: NYETIEN Mask */ + +#define HSUSBD_EPINTEN_ERRIEN_Pos (11) /*!< HSUSBD_T::EPINTEN: ERRIEN Position */ +#define HSUSBD_EPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_EPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::EPINTEN: ERRIEN Mask */ + +#define HSUSBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Position */ +#define HSUSBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTRXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Mask */ + +#define HSUSBD_EPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::EPDATCNT: DATCNT Position */ +#define HSUSBD_EPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_EPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::EPDATCNT: DATCNT Mask */ + +#define HSUSBD_EPDATCNT_DMALOOP_Pos (16) /*!< HSUSBD_T::EPDATCNT: DMALOOP Position */ +#define HSUSBD_EPDATCNT_DMALOOP_Msk (0x7ffful << HSUSBD_EPDATCNT_DMALOOP_Pos) /*!< HSUSBD_T::EPDATCNT: DMALOOP Mask */ + +#define HSUSBD_EPRSPCTL_FLUSH_Pos (0) /*!< HSUSBD_T::EPRSPCTL: FLUSH Position */ +#define HSUSBD_EPRSPCTL_FLUSH_Msk (0x1ul << HSUSBD_EPRSPCTL_FLUSH_Pos) /*!< HSUSBD_T::EPRSPCTL: FLUSH Mask */ + +#define HSUSBD_EPRSPCTL_MODE_Pos (1) /*!< HSUSBD_T::EPRSPCTL: MODE Position */ +#define HSUSBD_EPRSPCTL_MODE_Msk (0x3ul << HSUSBD_EPRSPCTL_MODE_Pos) /*!< HSUSBD_T::EPRSPCTL: MODE Mask */ + +#define HSUSBD_EPRSPCTL_TOGGLE_Pos (3) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Position */ +#define HSUSBD_EPRSPCTL_TOGGLE_Msk (0x1ul << HSUSBD_EPRSPCTL_TOGGLE_Pos) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Mask */ + +#define HSUSBD_EPRSPCTL_HALT_Pos (4) /*!< HSUSBD_T::EPRSPCTL: HALT Position */ +#define HSUSBD_EPRSPCTL_HALT_Msk (0x1ul << HSUSBD_EPRSPCTL_HALT_Pos) /*!< HSUSBD_T::EPRSPCTL: HALT Mask */ + +#define HSUSBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Position */ +#define HSUSBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_EPRSPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Mask */ + +#define HSUSBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Position */ +#define HSUSBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << HSUSBD_EPRSPCTL_SHORTTXEN_Pos) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Mask */ + +#define HSUSBD_EPRSPCTL_DISBUF_Pos (7) /*!< HSUSBD_T::EPRSPCTL: DISBUF Position */ +#define HSUSBD_EPRSPCTL_DISBUF_Msk (0x1ul << HSUSBD_EPRSPCTL_DISBUF_Pos) /*!< HSUSBD_T::EPRSPCTL: DISBUF Mask */ + +#define HSUSBD_EPMPS_EPMPS_Pos (0) /*!< HSUSBD_T::EPMPS: EPMPS Position */ +#define HSUSBD_EPMPS_EPMPS_Msk (0x7fful << HSUSBD_EPMPS_EPMPS_Pos) /*!< HSUSBD_T::EPMPS: EPMPS Mask */ + +#define HSUSBD_EPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::EPTXCNT: TXCNT Position */ +#define HSUSBD_EPTXCNT_TXCNT_Msk (0x7fful << HSUSBD_EPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::EPTXCNT: TXCNT Mask */ + +#define HSUSBD_EPCFG_EPEN_Pos (0) /*!< HSUSBD_T::EPCFG: EPEN Position */ +#define HSUSBD_EPCFG_EPEN_Msk (0x1ul << HSUSBD_EPCFG_EPEN_Pos) /*!< HSUSBD_T::EPCFG: EPEN Mask */ + +#define HSUSBD_EPCFG_EPTYPE_Pos (1) /*!< HSUSBD_T::EPCFG: EPTYPE Position */ +#define HSUSBD_EPCFG_EPTYPE_Msk (0x3ul << HSUSBD_EPCFG_EPTYPE_Pos) /*!< HSUSBD_T::EPCFG: EPTYPE Mask */ + +#define HSUSBD_EPCFG_EPDIR_Pos (3) /*!< HSUSBD_T::EPCFG: EPDIR Position */ +#define HSUSBD_EPCFG_EPDIR_Msk (0x1ul << HSUSBD_EPCFG_EPDIR_Pos) /*!< HSUSBD_T::EPCFG: EPDIR Mask */ + +#define HSUSBD_EPCFG_EPNUM_Pos (4) /*!< HSUSBD_T::EPCFG: EPNUM Position */ +#define HSUSBD_EPCFG_EPNUM_Msk (0xful << HSUSBD_EPCFG_EPNUM_Pos) /*!< HSUSBD_T::EPCFG: EPNUM Mask */ + +#define HSUSBD_EPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::EPBUFST: SADDR Position */ +#define HSUSBD_EPBUFST_SADDR_Msk (0xffful << HSUSBD_EPBUFST_SADDR_Pos) /*!< HSUSBD_T::EPBUFST: SADDR Mask */ + +#define HSUSBD_EPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::EPBUFEND: EADDR Position */ +#define HSUSBD_EPBUFEND_EADDR_Msk (0xffful << HSUSBD_EPBUFEND_EADDR_Pos) /*!< HSUSBD_T::EPBUFEND: EADDR Mask */ + +#define HSUSBD_DMAADDR_DMAADDR_Pos (0) /*!< HSUSBD_T::DMAADDR: DMAADDR Position */ +#define HSUSBD_DMAADDR_DMAADDR_Msk (0xfffffffful << HSUSBD_DMAADDR_DMAADDR_Pos) /*!< HSUSBD_T::DMAADDR: DMAADDR Mask */ + +#define HSUSBD_PHYCTL_DPPUEN_Pos (8) /*!< HSUSBD_T::PHYCTL: DPPUEN Position */ +#define HSUSBD_PHYCTL_DPPUEN_Msk (0x1ul << HSUSBD_PHYCTL_DPPUEN_Pos) /*!< HSUSBD_T::PHYCTL: DPPUEN Mask */ + +#define HSUSBD_PHYCTL_PHYEN_Pos (9) /*!< HSUSBD_T::PHYCTL: PHYEN Position */ +#define HSUSBD_PHYCTL_PHYEN_Msk (0x1ul << HSUSBD_PHYCTL_PHYEN_Pos) /*!< HSUSBD_T::PHYCTL: PHYEN Mask */ + +#define HSUSBD_PHYCTL_WKEN_Pos (24) /*!< HSUSBD_T::PHYCTL: WKEN Position */ +#define HSUSBD_PHYCTL_WKEN_Msk (0x1ul << HSUSBD_PHYCTL_WKEN_Pos) /*!< HSUSBD_T::PHYCTL: WKEN Mask */ + +#define HSUSBD_PHYCTL_VBUSDET_Pos (31) /*!< HSUSBD_T::PHYCTL: VBUSDET Position */ +#define HSUSBD_PHYCTL_VBUSDET_Msk (0x1ul << HSUSBD_PHYCTL_VBUSDET_Pos) /*!< HSUSBD_T::PHYCTL: VBUSDET Mask */ + +/**@}*/ /* HSUSBD_CONST */ +/**@}*/ /* end of HSUSBD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSUSBD_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbh_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbh_reg.h new file mode 100644 index 00000000000..245c8a5c031 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/hsusbh_reg.h @@ -0,0 +1,652 @@ +/**************************************************************************//** + * @file hsusbh_reg.h + * @version V1.00 + * @brief HSUSBH register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBH_REG_H__ +#define __HSUSBH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSUSBH High Speed USB Host Controller (HSUSBH) + Memory Mapped Structure for HSUSBH Controller +@{ */ + +typedef struct +{ + + + /** + * @var HSUSBH_T::EHCVNR + * Offset: 0x00 EHCI Version Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CRLEN |Capability Registers Length + * | | |This register is used as an offset to add to register base to find the beginning of the Operational Register Space. + * |[31:16] |VERSION |Host Controller Interface Version Number + * | | |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller + * | | |The most significant byte of this register represents a major revision and the least significant byte is the minor revision. + * @var HSUSBH_T::EHCSPR + * Offset: 0x04 EHCI Structural Parameters Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |N_PORTS |Number of Physical Downstream Ports + * | | |This field specifies the number of physical downstream ports implemented on this host controller + * | | |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8) + * | | |Valid values are in the range of 1H to FH. + * | | |A zero in this field is undefined. + * |[4] |PPC |Port Power Control + * | | |This field indicates whether the host controller implementation includes port power control + * | | |A one in this bit indicates the ports have port power switches + * | | |A zero in this bit indicates the port do not have port power stitches + * | | |The value of this field affects the functionality of the Port Power field in each port status and control register. + * |[11:8] |N_PCC |Number of Ports Per Companion Controller + * | | |This field indicates the number of ports supported per companion host controller + * | | |It is used to indicate the port routing configuration to system software. + * | | |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3 + * | | |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc + * | | |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. + * | | |The number in this field must be consistent with N_PORTS and N_CC. + * |[15:12] |N_CC |Number of Companion Controller + * | | |This field indicates the number of companion controllers associated with this USB 2.0 host controller. + * | | |A zero in this field indicates there are no companion host controllers + * | | |Port-ownership hand-off is not supported + * | | |Only high-speed devices are supported on the host controller root ports. + * | | |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s) + * | | |Port-ownership hand-offs are supported + * | | |High, Full- and Low-speed devices are supported on the host controller root ports. + * @var HSUSBH_T::EHCCPR + * Offset: 0x08 EHCI Capability Parameters Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AC64 |64-bit Addressing Capability + * | | |0 = Data structure using 32-bit address memory pointers. + * |[1] |PFLF |Programmable Frame List Flag + * | | |0 = System software must use a frame list length of 1024 elements with this EHCI host controller. + * |[2] |ASPC |Asynchronous Schedule Park Capability + * | | |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule. + * |[7:4] |IST |Isochronous Scheduling Threshold + * | | |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. + * | | |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. + * |[15:8] |EECP |EHCI Extended Capabilities Pointer (EECP) + * | | |0 = No extended capabilities are implemented. + * @var HSUSBH_T::UCMDR + * Offset: 0x20 USB Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RUN |Run/Stop (R/W) + * | | |When set to a 1, the Host Controller proceeds with execution of the schedule + * | | |The Host Controller continues execution as long as this bit is set to a 1 + * | | |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts + * | | |The Host Controller must halt within 16 micro-frames after software clears the Run bit + * | | |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state + * | | |Software must not write a one to this field unless the host controller is in the Halted state (i.e. + * | | |HCHalted in the USBSTS register is a one) + * | | |Doing so will yield undefined results. + * | | |0 = Stop. + * | | |1 = Run. + * |[1] |HCRST |Host Controller Reset (HCRESET) (R/W) + * | | |This control bit is used by software to reset the host controller + * | | |The effects of this on Root Hub registers are similar to a Chip Hardware Reset. + * | | |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc + * | | |to their initial value + * | | |Any transaction currently in progress on USB is immediately terminated + * | | |A USB reset is not driven on downstream ports. + * | | |All operational registers, including port registers and port state machines are set to their initial values + * | | |Port ownership reverts to the companion host controller(s), with the side effects + * | | |Software must reinitialize the host controller in order to return the host controller to an operational state. + * | | |This bit is set to zero by the Host Controller when the reset process is complete + * | | |Software cannot terminate the reset process early by writing a zero to this register. + * | | |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero + * | | |Attempting to reset an actively running host controller will result in undefined behavior. + * |[3:2] |FLSZ |Frame List Size (R/W or RO) + * | | |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one + * | | |This field specifies the size of the frame list + * | | |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index + * | | |Values mean: + * | | |00 = 1024 elements (4096 bytes) Default value. + * | | |01 = 512 elements (2048 bytes). + * | | |10 = 256 elements (1024 bytes) u2013 for resource-constrained environment. + * | | |11 = Reserved. + * |[4] |PSEN |Periodic Schedule Enable (R/W) + * | | |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean: + * | | |0 = Do not process the Periodic Schedule. + * | | |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. + * |[5] |ASEN |Asynchronous Schedule Enable (R/W) + * | | |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean: + * | | |0 = Do not process the Asynchronous Schedule. + * | | |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + * |[6] |IAAD |Interrupt on Asynchronous Advance Doorbell (R/W) + * | | |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule + * | | |Software must write a 1 to this bit to ring the doorbell. + * | | |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register + * | | |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold. + * | | |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one. + * | | |Software should not write a one to this bit when the asynchronous schedule is disabled + * | | |Doing so will yield undefined results. + * |[23:16] |ITC |Interrupt Threshold Control (R/W) + * | | |This field is used by system software to select the maximum rate at which the host controller will issue interrupts + * | | |The only valid values are defined below + * | | |If software writes an invalid value to this register, the results are undefined + * | | |Value Maximum Interrupt Interval + * | | |0x00 = Reserved. + * | | |0x01 = 1 micro-frame. + * | | |0x02 = 2 micro-frames. + * | | |0x04 = 4 micro-frames. + * | | |0x08 = 8 micro-frames (default, equates to 1 ms). + * | | |0x10 = 16 micro-frames (2 ms). + * | | |0x20 = 32 micro-frames (4 ms). + * | | |0x40 = 64 micro-frames (8 ms). + * | | |Any other value in this register yields undefined results. + * | | |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior. + * @var HSUSBH_T::USTSR + * Offset: 0x24 USB Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBINT |USB Interrupt (USBINT) (R/WC) + * | | |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. + * | | |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). + * |[1] |UERRINT |USB Error Interrupt (USBERRINT) (R/WC) + * | | |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow) + * | | |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set. + * |[2] |PCD |Port Change Detect (R/WC) + * | | |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port + * | | |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit. + * | | |This bit is allowed to be maintained in the Auxiliary power well + * | | |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change). + * |[3] |FLR |Frame List Rollover (R/WC) + * | | |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero + * | | |The exact value at which the rollover occurs depends on the frame list size + * | | |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles + * | | |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles. + * |[4] |HSERR |Host System Error (R/WC) + * | | |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. + * |[5] |IAA |Interrupt on Asynchronous Advance (R/WC) + * | | |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register + * | | |This status bit indicates the assertion of that interrupt source. + * |[12] |HCHalted |HCHalted (RO) + * | | |This bit is a zero whenever the Run/Stop bit is a one + * | | |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. + * | | |internal error). + * |[13] |RECLA |Reclamation (RO) + * | | |This is a read-only status bit, which is used to detect an empty asynchronous schedule. + * |[14] |PSS |Periodic Schedule Status (RO) + * | | |The bit reports the current real status of the Periodic Schedule + * | | |If this bit is a zero then the status of the Periodic Schedule is disabled + * | | |If this bit is a one then the status of the Periodic Schedule is enabled + * | | |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register + * | | |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). + * |[15] |ASS |Asynchronous Schedule Status (RO) + * | | |The bit reports the current real status of the Asynchronous Schedule + * | | |If this bit is a zero then the status of them Asynchronous Schedule is disabled + * | | |If this bit is a one then the status of the Asynchronous Schedule is enabled + * | | |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register + * | | |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). + * @var HSUSBH_T::UIENR + * Offset: 0x28 USB Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIEN |USB Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the USBINT bit. + * | | |0 = USB interrupt Disabled. + * | | |1 = USB interrupt Enabled. + * |[1] |UERRIEN |USB Error Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the USBERRINT bit. + * | | |0 = USB Error interrupt Disabled. + * | | |1 = USB Error interrupt Enabled. + * |[2] |PCIEN |Port Change Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Port Change Detect bit. + * | | |0 = Port Change interrupt Disabled. + * | | |1 = Port Change interrupt Enabled. + * |[3] |FLREN |Frame List Rollover Enable or Disable Bit + * | | |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Frame List Rollover bit. + * | | |0 = Frame List Rollover interrupt Disabled. + * | | |1 = Frame List Rollover interrupt Enabled. + * |[4] |HSERREN |Host System Error Enable or Disable Bit + * | | |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Host System Error bit. + * | | |0 = Host System Error interrupt Disabled. + * | | |1 = Host System Error interrupt Enabled. + * |[5] |IAAEN |Interrupt on Asynchronous Advance Enable or Disable Bit + * | | |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit. + * | | |0 = Interrupt on Asynchronous Advance Disabled. + * | | |1 = Interrupt on Asynchronous Advance Enabled. + * @var HSUSBH_T::UFINDR + * Offset: 0x2C USB Frame Index Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Index + * | | |The value in this register increment at the end of each time frame (e.g. + * | | |micro-frame) + * | | |Bits [N:3] are used for the Frame List current index + * | | |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index + * | | |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register. + * | | |FLSZ (UCMDR[3:2] Number Elements N + * | | |0x0 1024 12 + * | | |0x1 512 11 + * | | |0x2 256 10 + * | | |0x3 Reserved + * @var HSUSBH_T::UPFLBAR + * Offset: 0x34 USB Periodic Frame List Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |BADDR |Base Address + * | | |These bits correspond to memory address signals [31:12], respectively. + * @var HSUSBH_T::UCALAR + * Offset: 0x38 USB Current Asynchronous List Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:5] |LPL |Link Pointer Low (LPL) + * | | |These bits correspond to memory address signals [31:5], respectively + * | | |This field may only reference a Queue Head (QH). + * @var HSUSBH_T::UASSTR + * Offset: 0x3C USB Asynchronous Schedule Sleep Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ASSTMR |Asynchronous Schedule Sleep Timer + * | | |This field defines the AsyncSchedSleepTime of EHCI spec. + * | | |The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty. + * | | |The default value of this timer is 12'hBD6 + * | | |Because this timer is implemented in UTMI clock (30MHz) domain, the default sleeping time will be about 100us. + * @var HSUSBH_T::UCFGR + * Offset: 0x60 USB Configure Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CF |Configure Flag (CF) + * | | |Host software sets this bit as the last action in its process of configuring the Host Controller + * | | |This bit controls the default port-routing control logic + * | | |Bit values and side-effects are listed below. + * | | |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller. + * | | |1 = Port routing control logic default-routes all ports to this host controller. + * @var HSUSBH_T::UPSCR[2] + * Offset: 0x64~0x68 USB Port 0~1 Status and Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |Current Connect Status (RO) + * | | |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. + * | | |This field is zero if Port Power is zero. + * | | |0 = No device is present. + * | | |1 = Device is present on port. + * |[1] |CSC |Connect Status Change (R/W) + * | | |Indicates a change has occurred in the port's Current Connect Status + * | | |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change + * | | |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it. + * | | |This field is zero if Port Power is zero. + * | | |0 = No change. + * | | |1 = Change in Current Connect Status. + * |[2] |PE |Port Enabled/Disabled (R/W) + * | | |Ports can only be enabled by the host controller as a part of the reset and enable + * | | |Software cannot enable a port by writing a one to this field + * | | |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. + * | | |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software + * | | |Note that the bit status does not change until the port state actually changes + * | | |There may be a delay in disabling or enabling a port due to other host controller and bus events. + * | | |When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[3] |PEC |Port Enable/Disable Change (R/WC) + * | | |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error) + * | | |Software clears this bit by writing a 1 to it. + * | | |This field is zero if Port Power is zero. + * | | |0 = No change. + * | | |1 = Port enabled/disabled status has changed. + * |[4] |OCA |Over-current Active (RO) + * | | |This bit will automatically transition from a one to a zero when the over current condition is removed. + * | | |0 = This port does not have an over-current condition. + * | | |1 = This port currently has an over-current condition. + * |[5] |OCC |Over-current Change (R/WC) + * | | |1 = This bit gets set to a one when there is a change to Over-current Active + * | | |Software clears this bit by writing a one to this bit position. + * |[6] |FPR |Force Port Resume (R/W) + * | | |This functionality defined for manipulating this bit depends on the value of the Suspend bit + * | | |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined. + * | | |Software sets this bit to a 1 to drive resume signaling + * | | |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state + * | | |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one + * | | |If software sets this bit to a one, the host controller must not set the Port Change Detect bit. + * | | |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0 + * | | |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one + * | | |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed + * | | |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle) + * | | |This bit will remain a one until the port has switched to the high-speed idle + * | | |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero. + * | | |This field is zero if Port Power is zero. + * | | |0 = No resume (K-state) detected/driven on port. + * | | |1 = Resume detected/driven on port. + * |[7] |SUSPEND |Suspend (R/W) + * | | |Port Enabled Bit and Suspend bit of this register define the port states as follows: + * | | |Port enable is 0 and suspend is 0 = Disable. + * | | |Port enable is 0 and suspend is 1 = Disable. + * | | |Port enable is 1 and suspend is 0 = Enable. + * | | |Port enable is 1 and suspend is 1 = Suspend. + * | | |When in suspend state, downstream propagation of data is blocked on this port, except for port reset + * | | |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1 + * | | |In the suspend state, the port is sensitive to resume detection + * | | |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. + * | | |A write of zero to this bit is ignored by the host controller + * | | |The host controller will unconditionally set this bit to a zero when: + * | | |Software sets the Force Port Resume bit to a zero (from a one). + * | | |Software sets the Port Reset bit to a one (from a zero). + * | | |If host software sets this bit to a one when the port is not enabled (i.e. + * | | |Port enabled bit is a zero) the results are undefined. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port not in suspend state. + * | | |1 = Port in suspend state. + * |[8] |PRST |Port Reset (R/W) + * | | |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started + * | | |Software writes a zero to this bit to terminate the bus reset sequence + * | | |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes + * | | |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit. + * | | |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero + * | | |The bit status will not read as a zero until after the reset has completed + * | | |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. + * | | |set the Port Enable bit to a one) + * | | |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero + * | | |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero. + * | | |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit + * | | |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port is not in Reset. + * | | |1 = Port is in Reset. + * |[11:10] |LSTS |Line Status (RO) + * | | |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines + * | | |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence + * | | |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one. + * | | |The encoding of the bits are: + * | | |Bits[11:10] USB State Interpretation + * | | |00 = SE0 Not Low-speed device, perform EHCI reset. + * | | |01 = K-state Low-speed device, release ownership of port. + * | | |10 = J-state Not Low-speed device, perform EHCI reset. + * | | |11 = Undefined Not Low-speed device, perform EHCI reset. + * | | |This value of this field is undefined if Port Power is zero. + * |[12] |PP |Port Power (PP) + * | | |Host controller has port power control switches + * | | |This bit represents the Current setting of the switch (0 = off, 1 = on) + * | | |When power is not available on a port (i.e. + * | | |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc. + * | | |When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port). + * |[13] |PO |Port Owner (R/W) + * | | |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition + * | | |This bit unconditionally goes to 1 whenever the Configured bit is zero. + * | | |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device) + * | | |Software writes a one to this bit when the attached device is not a high-speed device + * | | |A one in this bit means that a companion host controller owns and controls the port. + * |[19:16] |PTC |Port Test Control (R/W) + * | | |When this field is zero, the port is NOT operating in a test mode + * | | |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value + * | | |The encoding of the test mode bits are (0x6 ~ 0xF are reserved): + * | | |Bits Test Mode + * | | |0x0 = Test mode not enabled. + * | | |0x1 = Test J_STATE. + * | | |0x2 = Test K_STATE. + * | | |0x3 = Test SE0_NAK. + * | | |0x4 = Test Packet. + * | | |0x5 = Test FORCE_ENABLE. + * @var HSUSBH_T::USBPCR0 + * Offset: 0xC4 USB PHY 0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |SUSPEND |Suspend Assertion + * | | |This bit controls the suspend mode of USB PHY 0. + * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state. + * | | |This bit is 1'b0 in default + * | | |This means the USB PHY 0 is suspended in default + * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host. + * | | |0 = USB PHY 0 was suspended. + * | | |1 = USB PHY 0 was not suspended. + * |[11] |CLKVALID |UTMI Clock Valid + * | | |This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready + * | | |S/W program must prevent to write other control registers before this UTMI clock valid flag is active. + * | | |0 = UTMI clock is not valid. + * | | |1 = UTMI clock is valid. + * @var HSUSBH_T::USBPCR1 + * Offset: 0xC8 USB PHY 1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |SUSPEND |Suspend Assertion + * | | |This bit controls the suspend mode of USB PHY 1. + * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state. + * | | |This bit is 1'b0 in default + * | | |This means the USB PHY 0 is suspended in default + * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host. + * | | |0 = USB PHY 1 was suspended. + * | | |1 = USB PHY 1 was not suspended. + */ + __I uint32_t EHCVNR; /*!< [0x0000] EHCI Version Number Register */ + __I uint32_t EHCSPR; /*!< [0x0004] EHCI Structural Parameters Register */ + __I uint32_t EHCCPR; /*!< [0x0008] EHCI Capability Parameters Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UCMDR; /*!< [0x0020] USB Command Register */ + __IO uint32_t USTSR; /*!< [0x0024] USB Status Register */ + __IO uint32_t UIENR; /*!< [0x0028] USB Interrupt Enable Register */ + __IO uint32_t UFINDR; /*!< [0x002c] USB Frame Index Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UPFLBAR; /*!< [0x0034] USB Periodic Frame List Base Address Register */ + __IO uint32_t UCALAR; /*!< [0x0038] USB Current Asynchronous List Address Register */ + __IO uint32_t UASSTR; /*!< [0x003c] USB Asynchronous Schedule Sleep Timer Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UCFGR; /*!< [0x0060] USB Configure Flag Register */ + __IO uint32_t UPSCR[2]; /*!< [0x0064] ~ [0x0068] USB Port 0 & 1 Status and Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[22]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t USBPCR0; /*!< [0x00c4] USB PHY 0 Control Register */ + __IO uint32_t USBPCR1; /*!< [0x00c8] USB PHY 1 Control Register */ + +} HSUSBH_T; + +/** + @addtogroup HSUSBH_CONST HSUSBH Bit Field Definition + Constant Definitions for HSUSBH Controller +@{ */ + +#define HSUSBH_EHCVNR_CRLEN_Pos (0) /*!< HSUSBH_T::EHCVNR: CRLEN Position */ +#define HSUSBH_EHCVNR_CRLEN_Msk (0xfful << HSUSBH_EHCVNR_CRLEN_Pos) /*!< HSUSBH_T::EHCVNR: CRLEN Mask */ + +#define HSUSBH_EHCVNR_VERSION_Pos (16) /*!< HSUSBH_T::EHCVNR: VERSION Position */ +#define HSUSBH_EHCVNR_VERSION_Msk (0xfffful << HSUSBH_EHCVNR_VERSION_Pos) /*!< HSUSBH_T::EHCVNR: VERSION Mask */ + +#define HSUSBH_EHCSPR_N_PORTS_Pos (0) /*!< HSUSBH_T::EHCSPR: N_PORTS Position */ +#define HSUSBH_EHCSPR_N_PORTS_Msk (0xful << HSUSBH_EHCSPR_N_PORTS_Pos) /*!< HSUSBH_T::EHCSPR: N_PORTS Mask */ + +#define HSUSBH_EHCSPR_PPC_Pos (4) /*!< HSUSBH_T::EHCSPR: PPC Position */ +#define HSUSBH_EHCSPR_PPC_Msk (0x1ul << HSUSBH_EHCSPR_PPC_Pos) /*!< HSUSBH_T::EHCSPR: PPC Mask */ + +#define HSUSBH_EHCSPR_N_PCC_Pos (8) /*!< HSUSBH_T::EHCSPR: N_PCC Position */ +#define HSUSBH_EHCSPR_N_PCC_Msk (0xful << HSUSBH_EHCSPR_N_PCC_Pos) /*!< HSUSBH_T::EHCSPR: N_PCC Mask */ + +#define HSUSBH_EHCSPR_N_CC_Pos (12) /*!< HSUSBH_T::EHCSPR: N_CC Position */ +#define HSUSBH_EHCSPR_N_CC_Msk (0xful << HSUSBH_EHCSPR_N_CC_Pos) /*!< HSUSBH_T::EHCSPR: N_CC Mask */ + +#define HSUSBH_EHCCPR_AC64_Pos (0) /*!< HSUSBH_T::EHCCPR: AC64 Position */ +#define HSUSBH_EHCCPR_AC64_Msk (0x1ul << HSUSBH_EHCCPR_AC64_Pos) /*!< HSUSBH_T::EHCCPR: AC64 Mask */ + +#define HSUSBH_EHCCPR_PFLF_Pos (1) /*!< HSUSBH_T::EHCCPR: PFLF Position */ +#define HSUSBH_EHCCPR_PFLF_Msk (0x1ul << HSUSBH_EHCCPR_PFLF_Pos) /*!< HSUSBH_T::EHCCPR: PFLF Mask */ + +#define HSUSBH_EHCCPR_ASPC_Pos (2) /*!< HSUSBH_T::EHCCPR: ASPC Position */ +#define HSUSBH_EHCCPR_ASPC_Msk (0x1ul << HSUSBH_EHCCPR_ASPC_Pos) /*!< HSUSBH_T::EHCCPR: ASPC Mask */ + +#define HSUSBH_EHCCPR_IST_Pos (4) /*!< HSUSBH_T::EHCCPR: IST Position */ +#define HSUSBH_EHCCPR_IST_Msk (0xful << HSUSBH_EHCCPR_IST_Pos) /*!< HSUSBH_T::EHCCPR: IST Mask */ + +#define HSUSBH_EHCCPR_EECP_Pos (8) /*!< HSUSBH_T::EHCCPR: EECP Position */ +#define HSUSBH_EHCCPR_EECP_Msk (0xfful << HSUSBH_EHCCPR_EECP_Pos) /*!< HSUSBH_T::EHCCPR: EECP Mask */ + +#define HSUSBH_UCMDR_RUN_Pos (0) /*!< HSUSBH_T::UCMDR: RUN Position */ +#define HSUSBH_UCMDR_RUN_Msk (0x1ul << HSUSBH_UCMDR_RUN_Pos) /*!< HSUSBH_T::UCMDR: RUN Mask */ + +#define HSUSBH_UCMDR_HCRST_Pos (1) /*!< HSUSBH_T::UCMDR: HCRST Position */ +#define HSUSBH_UCMDR_HCRST_Msk (0x1ul << HSUSBH_UCMDR_HCRST_Pos) /*!< HSUSBH_T::UCMDR: HCRST Mask */ + +#define HSUSBH_UCMDR_FLSZ_Pos (2) /*!< HSUSBH_T::UCMDR: FLSZ Position */ +#define HSUSBH_UCMDR_FLSZ_Msk (0x3ul << HSUSBH_UCMDR_FLSZ_Pos) /*!< HSUSBH_T::UCMDR: FLSZ Mask */ + +#define HSUSBH_UCMDR_PSEN_Pos (4) /*!< HSUSBH_T::UCMDR: PSEN Position */ +#define HSUSBH_UCMDR_PSEN_Msk (0x1ul << HSUSBH_UCMDR_PSEN_Pos) /*!< HSUSBH_T::UCMDR: PSEN Mask */ + +#define HSUSBH_UCMDR_ASEN_Pos (5) /*!< HSUSBH_T::UCMDR: ASEN Position */ +#define HSUSBH_UCMDR_ASEN_Msk (0x1ul << HSUSBH_UCMDR_ASEN_Pos) /*!< HSUSBH_T::UCMDR: ASEN Mask */ + +#define HSUSBH_UCMDR_IAAD_Pos (6) /*!< HSUSBH_T::UCMDR: IAAD Position */ +#define HSUSBH_UCMDR_IAAD_Msk (0x1ul << HSUSBH_UCMDR_IAAD_Pos) /*!< HSUSBH_T::UCMDR: IAAD Mask */ + +#define HSUSBH_UCMDR_ITC_Pos (16) /*!< HSUSBH_T::UCMDR: ITC Position */ +#define HSUSBH_UCMDR_ITC_Msk (0xfful << HSUSBH_UCMDR_ITC_Pos) /*!< HSUSBH_T::UCMDR: ITC Mask */ + +#define HSUSBH_USTSR_USBINT_Pos (0) /*!< HSUSBH_T::USTSR: USBINT Position */ +#define HSUSBH_USTSR_USBINT_Msk (0x1ul << HSUSBH_USTSR_USBINT_Pos) /*!< HSUSBH_T::USTSR: USBINT Mask */ + +#define HSUSBH_USTSR_UERRINT_Pos (1) /*!< HSUSBH_T::USTSR: UERRINT Position */ +#define HSUSBH_USTSR_UERRINT_Msk (0x1ul << HSUSBH_USTSR_UERRINT_Pos) /*!< HSUSBH_T::USTSR: UERRINT Mask */ + +#define HSUSBH_USTSR_PCD_Pos (2) /*!< HSUSBH_T::USTSR: PCD Position */ +#define HSUSBH_USTSR_PCD_Msk (0x1ul << HSUSBH_USTSR_PCD_Pos) /*!< HSUSBH_T::USTSR: PCD Mask */ + +#define HSUSBH_USTSR_FLR_Pos (3) /*!< HSUSBH_T::USTSR: FLR Position */ +#define HSUSBH_USTSR_FLR_Msk (0x1ul << HSUSBH_USTSR_FLR_Pos) /*!< HSUSBH_T::USTSR: FLR Mask */ + +#define HSUSBH_USTSR_HSERR_Pos (4) /*!< HSUSBH_T::USTSR: HSERR Position */ +#define HSUSBH_USTSR_HSERR_Msk (0x1ul << HSUSBH_USTSR_HSERR_Pos) /*!< HSUSBH_T::USTSR: HSERR Mask */ + +#define HSUSBH_USTSR_IAA_Pos (5) /*!< HSUSBH_T::USTSR: IAA Position */ +#define HSUSBH_USTSR_IAA_Msk (0x1ul << HSUSBH_USTSR_IAA_Pos) /*!< HSUSBH_T::USTSR: IAA Mask */ + +#define HSUSBH_USTSR_HCHalted_Pos (12) /*!< HSUSBH_T::USTSR: HCHalted Position */ +#define HSUSBH_USTSR_HCHalted_Msk (0x1ul << HSUSBH_USTSR_HCHalted_Pos) /*!< HSUSBH_T::USTSR: HCHalted Mask */ + +#define HSUSBH_USTSR_RECLA_Pos (13) /*!< HSUSBH_T::USTSR: RECLA Position */ +#define HSUSBH_USTSR_RECLA_Msk (0x1ul << HSUSBH_USTSR_RECLA_Pos) /*!< HSUSBH_T::USTSR: RECLA Mask */ + +#define HSUSBH_USTSR_PSS_Pos (14) /*!< HSUSBH_T::USTSR: PSS Position */ +#define HSUSBH_USTSR_PSS_Msk (0x1ul << HSUSBH_USTSR_PSS_Pos) /*!< HSUSBH_T::USTSR: PSS Mask */ + +#define HSUSBH_USTSR_ASS_Pos (15) /*!< HSUSBH_T::USTSR: ASS Position */ +#define HSUSBH_USTSR_ASS_Msk (0x1ul << HSUSBH_USTSR_ASS_Pos) /*!< HSUSBH_T::USTSR: ASS Mask */ + +#define HSUSBH_UIENR_USBIEN_Pos (0) /*!< HSUSBH_T::UIENR: USBIEN Position */ +#define HSUSBH_UIENR_USBIEN_Msk (0x1ul << HSUSBH_UIENR_USBIEN_Pos) /*!< HSUSBH_T::UIENR: USBIEN Mask */ + +#define HSUSBH_UIENR_UERRIEN_Pos (1) /*!< HSUSBH_T::UIENR: UERRIEN Position */ +#define HSUSBH_UIENR_UERRIEN_Msk (0x1ul << HSUSBH_UIENR_UERRIEN_Pos) /*!< HSUSBH_T::UIENR: UERRIEN Mask */ + +#define HSUSBH_UIENR_PCIEN_Pos (2) /*!< HSUSBH_T::UIENR: PCIEN Position */ +#define HSUSBH_UIENR_PCIEN_Msk (0x1ul << HSUSBH_UIENR_PCIEN_Pos) /*!< HSUSBH_T::UIENR: PCIEN Mask */ + +#define HSUSBH_UIENR_FLREN_Pos (3) /*!< HSUSBH_T::UIENR: FLREN Position */ +#define HSUSBH_UIENR_FLREN_Msk (0x1ul << HSUSBH_UIENR_FLREN_Pos) /*!< HSUSBH_T::UIENR: FLREN Mask */ + +#define HSUSBH_UIENR_HSERREN_Pos (4) /*!< HSUSBH_T::UIENR: HSERREN Position */ +#define HSUSBH_UIENR_HSERREN_Msk (0x1ul << HSUSBH_UIENR_HSERREN_Pos) /*!< HSUSBH_T::UIENR: HSERREN Mask */ + +#define HSUSBH_UIENR_IAAEN_Pos (5) /*!< HSUSBH_T::UIENR: IAAEN Position */ +#define HSUSBH_UIENR_IAAEN_Msk (0x1ul << HSUSBH_UIENR_IAAEN_Pos) /*!< HSUSBH_T::UIENR: IAAEN Mask */ + +#define HSUSBH_UFINDR_FI_Pos (0) /*!< HSUSBH_T::UFINDR: FI Position */ +#define HSUSBH_UFINDR_FI_Msk (0x3ffful << HSUSBH_UFINDR_FI_Pos) /*!< HSUSBH_T::UFINDR: FI Mask */ + +#define HSUSBH_UPFLBAR_BADDR_Pos (12) /*!< HSUSBH_T::UPFLBAR: BADDR Position */ +#define HSUSBH_UPFLBAR_BADDR_Msk (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos) /*!< HSUSBH_T::UPFLBAR: BADDR Mask */ + +#define HSUSBH_UCALAR_LPL_Pos (5) /*!< HSUSBH_T::UCALAR: LPL Position */ +#define HSUSBH_UCALAR_LPL_Msk (0x7fffffful << HSUSBH_UCALAR_LPL_Pos) /*!< HSUSBH_T::UCALAR: LPL Mask */ + +#define HSUSBH_UASSTR_ASSTMR_Pos (0) /*!< HSUSBH_T::UASSTR: ASSTMR Position */ +#define HSUSBH_UASSTR_ASSTMR_Msk (0xffful << HSUSBH_UASSTR_ASSTMR_Pos) /*!< HSUSBH_T::UASSTR: ASSTMR Mask */ + +#define HSUSBH_UCFGR_CF_Pos (0) /*!< HSUSBH_T::UCFGR: CF Position */ +#define HSUSBH_UCFGR_CF_Msk (0x1ul << HSUSBH_UCFGR_CF_Pos) /*!< HSUSBH_T::UCFGR: CF Mask */ + +#define HSUSBH_UPSCR_CCS_Pos (0) /*!< HSUSBH_T::UPSCR[2]: CCS Position */ +#define HSUSBH_UPSCR_CCS_Msk (0x1ul << HSUSBH_UPSCR_CCS_Pos) /*!< HSUSBH_T::UPSCR[2]: CCS Mask */ + +#define HSUSBH_UPSCR_CSC_Pos (1) /*!< HSUSBH_T::UPSCR[2]: CSC Position */ +#define HSUSBH_UPSCR_CSC_Msk (0x1ul << HSUSBH_UPSCR_CSC_Pos) /*!< HSUSBH_T::UPSCR[2]: CSC Mask */ + +#define HSUSBH_UPSCR_PE_Pos (2) /*!< HSUSBH_T::UPSCR[2]: PE Position */ +#define HSUSBH_UPSCR_PE_Msk (0x1ul << HSUSBH_UPSCR_PE_Pos) /*!< HSUSBH_T::UPSCR[2]: PE Mask */ + +#define HSUSBH_UPSCR_PEC_Pos (3) /*!< HSUSBH_T::UPSCR[2]: PEC Position */ +#define HSUSBH_UPSCR_PEC_Msk (0x1ul << HSUSBH_UPSCR_PEC_Pos) /*!< HSUSBH_T::UPSCR[2]: PEC Mask */ + +#define HSUSBH_UPSCR_OCA_Pos (4) /*!< HSUSBH_T::UPSCR[2]: OCA Position */ +#define HSUSBH_UPSCR_OCA_Msk (0x1ul << HSUSBH_UPSCR_OCA_Pos) /*!< HSUSBH_T::UPSCR[2]: OCA Mask */ + +#define HSUSBH_UPSCR_OCC_Pos (5) /*!< HSUSBH_T::UPSCR[2]: OCC Position */ +#define HSUSBH_UPSCR_OCC_Msk (0x1ul << HSUSBH_UPSCR_OCC_Pos) /*!< HSUSBH_T::UPSCR[2]: OCC Mask */ + +#define HSUSBH_UPSCR_FPR_Pos (6) /*!< HSUSBH_T::UPSCR[2]: FPR Position */ +#define HSUSBH_UPSCR_FPR_Msk (0x1ul << HSUSBH_UPSCR_FPR_Pos) /*!< HSUSBH_T::UPSCR[2]: FPR Mask */ + +#define HSUSBH_UPSCR_SUSPEND_Pos (7) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Position */ +#define HSUSBH_UPSCR_SUSPEND_Msk (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Mask */ + +#define HSUSBH_UPSCR_PRST_Pos (8) /*!< HSUSBH_T::UPSCR[2]: PRST Position */ +#define HSUSBH_UPSCR_PRST_Msk (0x1ul << HSUSBH_UPSCR_PRST_Pos) /*!< HSUSBH_T::UPSCR[2]: PRST Mask */ + +#define HSUSBH_UPSCR_LSTS_Pos (10) /*!< HSUSBH_T::UPSCR[2]: LSTS Position */ +#define HSUSBH_UPSCR_LSTS_Msk (0x3ul << HSUSBH_UPSCR_LSTS_Pos) /*!< HSUSBH_T::UPSCR[2]: LSTS Mask */ + +#define HSUSBH_UPSCR_PP_Pos (12) /*!< HSUSBH_T::UPSCR[2]: PP Position */ +#define HSUSBH_UPSCR_PP_Msk (0x1ul << HSUSBH_UPSCR_PP_Pos) /*!< HSUSBH_T::UPSCR[2]: PP Mask */ + +#define HSUSBH_UPSCR_PO_Pos (13) /*!< HSUSBH_T::UPSCR[2]: PO Position */ +#define HSUSBH_UPSCR_PO_Msk (0x1ul << HSUSBH_UPSCR_PO_Pos) /*!< HSUSBH_T::UPSCR[2]: PO Mask */ + +#define HSUSBH_UPSCR_PTC_Pos (16) /*!< HSUSBH_T::UPSCR[2]: PTC Position */ +#define HSUSBH_UPSCR_PTC_Msk (0xful << HSUSBH_UPSCR_PTC_Pos) /*!< HSUSBH_T::UPSCR[2]: PTC Mask */ + +#define HSUSBH_USBPCR0_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR0: SUSPEND Position */ +#define HSUSBH_USBPCR0_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR0: SUSPEND Mask */ + +#define HSUSBH_USBPCR0_CLKVALID_Pos (11) /*!< HSUSBH_T::USBPCR0: CLKVALID Position */ +#define HSUSBH_USBPCR0_CLKVALID_Msk (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos) /*!< HSUSBH_T::USBPCR0: CLKVALID Mask */ + +#define HSUSBH_USBPCR1_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR1: SUSPEND Position */ +#define HSUSBH_USBPCR1_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR1: SUSPEND Mask */ + +/**@}*/ /* HSUSBH_CONST */ +/**@}*/ /* end of HSUSBH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSUSBH_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2c_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2c_reg.h new file mode 100644 index 00000000000..e0500564740 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2c_reg.h @@ -0,0 +1,724 @@ +/**************************************************************************//** + * @file i2c_reg.h + * @version V1.00 + * @brief I2C register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2C_REG_H__ +#define __I2C_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup I2C Inter-IC Bus Controller(I2C) + Memory Mapped Structure for I2C Controller +@{ */ + +typedef struct +{ + + + /** + * @var I2C_T::CTL0 + * Offset: 0x00 I2C Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line + * |[3] |SI |I2C Interrupt Flag + * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware + * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested + * | | |SI must be cleared by software + * | | |Clear SI by writing 1 to this bit. + * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. + * |[4] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected + * | | |This bit will be cleared by hardware automatically. + * |[5] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[6] |I2CEN |I2C Controller Enable Bit + * | | |Set to enable I2C serial function controller + * | | |When I2CEN=1 the I2C serial function enable + * | | |The multi-function pin function must set to SDA, and SCL of I2C function first. + * | | |0 = I2C controller Disabled. + * | | |1 = I2C controller Enabled. + * |[7] |INTEN |Enable Interrupt + * | | |0 = I2C interrupt Disabled. + * | | |1 = I2C interrupt Enabled. + * @var I2C_T::ADDR0 + * Offset: 0x04 I2C Slave Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::DAT + * Offset: 0x08 I2C Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |I2C Data + * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. + * @var I2C_T::STATUS0 + * Offset: 0x0C I2C Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STATUS |I2C Status + * | | |The three least significant bits are always 0 + * | | |The five most significant bits contain the status code + * | | |There are 28 possible status codes + * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested + * | | |Others I2C_STATUS values correspond to defined I2C states + * | | |When each of these states is entered, a status interrupt is requested (SI = 1) + * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software + * | | |In addition, states 00H stands for a Bus Error + * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. + * @var I2C_T::CLKDIV + * Offset: 0x10 I2C Clock Divided Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DIVIDER |I2C Clock Divided + * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)). + * | | |Note: The minimum value of I2C_CLKDIV is 4. + * @var I2C_T::TOCTL + * Offset: 0x14 I2C Time-out Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIF |Time-out Flag + * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. + * | | |Note: Software can write 1 to clear this bit. + * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4 + * | | |When Enabled, The time-out period is extend 4 times. + * | | |0 = Time-out period is extend 4 times Disabled. + * | | |1 = Time-out period is extend 4 times Enabled. + * |[2] |TOCEN |Time-out Counter Enable Bit + * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear + * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. + * | | |0 = Time-out counter Disabled. + * | | |1 = Time-out counter Enabled. + * @var I2C_T::ADDR1 + * Offset: 0x18 I2C Slave Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDR2 + * Offset: 0x1C I2C Slave Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDR3 + * Offset: 0x20 I2C Slave Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDRMSK0 + * Offset: 0x24 I2C Slave Address Mask Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK1 + * Offset: 0x28 I2C Slave Address Mask Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK2 + * Offset: 0x2C I2C Slave Address Mask Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK3 + * Offset: 0x30 I2C Slave Address Mask Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::WKCTL + * Offset: 0x3C I2C Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |I2C Wake-up Enable Bit + * | | |0 = I2C wake-up function Disabled. + * | | |1 = I2C wake-up function Enabled. + * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit + * | | |0 = I2C hold bus after wake-up. + * | | |1 = I2C don't hold bus after wake-up. + * | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received + * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. + * @var I2C_T::WKSTS + * Offset: 0x40 I2C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKIF |I2C Wake-up Flag + * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit. + * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit. + * @var I2C_T::CTL1 + * Offset: 0x44 I2C Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function disable. + * | | |1 = Transmit PDMA function enable. + * |[1] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function disable. + * | | |1 = Receive PDMA function enable. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the I2C request to PDMA. + * |[8] |PDMASTR |PDMA Stretch Bit + * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX) + * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared + * | | |(only master TX) + * |[9] |ADDR10EN |Address 10-bit Function Enable + * | | |0 = Address match 10-bit function is disabled. + * | | |1 = Address match 10-bit function is enabled. + * @var I2C_T::STATUS1 + * Offset: 0x48 I2C Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |I2C Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |I2C Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[2] |ADMAT2 |I2C Address 2 Match Status Register + * | | |When address 2 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[3] |ADMAT3 |I2C Address 3 Match Status Register + * | | |When address 3 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[8] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected. + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * | | |Note:This bit is read only. + * @var I2C_T::TMCTL + * Offset: 0x4C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK. + * | | |Note: Setup time setting should not make SCL output less than three PCLKs. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK. + * @var I2C_T::BUSCTL + * Offset: 0x50 I2C Bus Management Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACKMEN |Acknowledge Control by Manual + * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. + * | | |0 = Slave byte control Disabled. + * | | |1 = Slave byte control Enabled + * | | |The 9th bit can response the ACK or NACK according the received data by user + * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse. + * | | |Note: If the BMDEN=1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition. + * |[1] |PECEN |Packet Error Checking Calculation Enable Bit + * | | |0 = Packet Error Checking Calculation Disabled. + * | | |1 = Packet Error Checking Calculation Enabled. + * | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation. + * |[2] |BMDEN |Bus Management Device Default Address Enable Bit + * | | |0 = Device default address Disable + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed + * | | |1 = Device default address Enabled + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed. + * |[3] |BMHEN |Bus Management Host Enable Bit + * | | |0 = Host function Disabled. + * | | |1 = Host function Enabled. + * |[4] |ALERTEN |Bus Management Alert Enable Bit + * | | |Device Mode (BMHEN=0). + * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. + * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. + * | | |Host Mode (BMHEN=1). + * | | |0 = BM_ALERT pin not supported. + * | | |1 = BM_ALERT pin supported. + * |[5] |SCTLOSTS |Suspend/Control Data Output Status + * | | |0 = The output of SUSCON pin is low. + * | | |1 = The output of SUSCON pin is high. + * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit + * | | |0 = The SUSCON pin in input. + * | | |1 = The output enable is active on the SUSCON pin. + * |[7] |BUSEN |BUS Enable Bit + * | | |0 = The system management function is Disabled. + * | | |1 = The system management function is Enable. + * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. + * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception + * | | |0 = No PEC transfer. + * | | |1 = PEC transmission is requested. + * | | |Note: This bit has no effect in slave mode when ACKMEN=0. + * |[9] |TIDLE |Timer Check in Idle State + * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle + * | | |This bit is used to define which condition is enabled. + * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active. + * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle. + * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. + * |[10] |PECCLR |PEC Clear at Repeat Start + * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected + * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. + * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled. + * | | |1 = The PEC calculation is cleared by "Repeat Start"" function is Enabled. + * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt + * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1. + * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1. + * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit + * | | |0 = Indicates the byte count done interrupt is Disabled. + * | | |1 = Indicates the byte count done interrupt is Enabled. + * | | |Note: This bit is used in PECEN=1. + * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit + * | | |0 = Indicates the PEC transfer done interrupt is Disabled. + * | | |1 = Indicates the PEC transfer done interrupt is Enabled. + * | | |Note: This bit is used in PECEN=1. + * @var I2C_T::BUSTCTL + * Offset: 0x54 I2C Bus Management Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSTOEN |Bus Time Out Enable Bit + * | | |0 = Indicates the bus clock low time-out detection is Disabled. + * | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) + * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit + * | | |0 = Indicates the cumulative clock low time-out detection is Disabled. + * | | |1 = Indicates the cumulative clock low time-out detection is Enabled. + * | | |For Master, it calculates the period from START to ACK + * | | |For Slave, it calculates the period from START to STOP + * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit + * | | |BUSY =1. + * | | |0 = Indicates the SCLK low time-out interrupt is Disabled. + * | | |1 = Indicates the SCLK low time-out interrupt is Enabled. + * | | |BUSY =0. + * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled. + * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled. + * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit + * | | |0 = Indicates the clock time out interrupt is Disabled. + * | | |1 = Indicates the clock time out interrupt is Enabled. + * |[4] |TORSTEN |Time Out Reset Enable Bit + * | | |0 = Indicates the I2C state machine reset is Disable. + * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high) + * @var I2C_T::BUSSTS + * Offset: 0x58 I2C Bus Management Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[1] |BCDONE |Byte Count Transmission/Receive Done + * | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * |[2] |PECERR |PEC Error in Reception + * | | |0 = Indicates the PEC value equal the received PEC data packet. + * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet. + * | | |Note: Software can write 1 to clear this bit. + * |[3] |ALERT |SMBus Alert Status + * | | |Device Mode (BMHEN =0). + * | | |0 = Indicates SMBALERT pin state is low. + * | | |1 = Indicates SMBALERT pin state is high. + * | | |Host Mode (BMHEN =1). + * | | |0 = No SMBALERT event. + * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1. + * | | |Note: + * | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system + * | | |2. Software can write 1 to clear this bit. + * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status + * | | |0 = The input status of SUSCON pin is 0. + * | | |1 = The input status of SUSCON pin is 1. + * |[5] |BUSTO |Bus Time-out Status + * | | |0 = Indicates that there is no any time-out or external clock time-out. + * | | |1 = Indicates that a time-out or external clock time-out occurred. + * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[6] |CLKTO |Clock Low Cumulate Time-out Status + * | | |0 = Indicates that the cumulative clock low is no any time-out. + * | | |1 = Indicates that the cumulative clock low time-out occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[7] |PECDONE |PEC Byte Transmission/Receive Done + * | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * @var I2C_T::PKTSIZE + * Offset: 0x5C I2C Packet Error Checking Byte Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |PLDSIZE |Transfer Byte Number + * | | |The transmission or receive byte number in one transaction when the PECEN is set + * | | |The maximum transaction or receive byte is 256 Bytes. + * | | |Notice: The byte number counting includes address, command code, and data frame. + * @var I2C_T::PKTCRC + * Offset: 0x60 I2C Packet Error Checking Byte Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PECCRC |Packet Error Checking Byte Value + * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1 + * | | |It is read only. + * @var I2C_T::BUSTOUT + * Offset: 0x64 I2C Bus Management Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BUSTO |Bus Management Time-out Value + * | | |Indicate the bus time-out value in bus is IDLE or SCLK low. + * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. + * @var I2C_T::CLKTOUT + * Offset: 0x68 I2C Bus Management Clock Low Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CLKTO |Bus Clock Low Timer + * | | |The field is used to configure the cumulative clock extension time-out. + * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */ + __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */ + __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */ + __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */ + __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */ + __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */ + __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */ + __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */ + __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */ + __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */ + __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */ + __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */ + __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */ + __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */ + __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */ + __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */ + __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */ + __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */ + __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */ + __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */ + +} I2C_T; + +/** + @addtogroup I2C_CONST I2C Bit Field Definition + Constant Definitions for I2C Controller +@{ */ + +#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL: AA Position */ +#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL: AA Mask */ + +#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL: SI Position */ +#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL: SI Mask */ + +#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL: STO Position */ +#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL: STO Mask */ + +#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL: STA Position */ +#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL: STA Mask */ + +#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */ +#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */ + +#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */ +#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */ + +#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */ +#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */ + +#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */ +#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */ + +#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */ +#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */ + +#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */ +#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos) /*!< I2C_T::STATUS: STATUS Mask */ + +#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */ +#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */ + +#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */ +#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */ + +#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */ +#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */ + +#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */ +#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */ + +#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */ +#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */ + +#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */ +#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */ + +#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */ +#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */ + +#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */ +#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */ + +#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */ +#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */ + +#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */ +#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */ + +#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */ +#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */ +#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */ +#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */ + +#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */ +#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */ + +#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */ +#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */ + +#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */ +#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */ + +#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */ +#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */ + +#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */ +#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */ + +#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */ +#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */ + +#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */ +#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */ + +#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */ +#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */ + +#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */ +#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */ + +#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */ +#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */ + +#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */ +#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */ + +#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */ +#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */ + +#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */ +#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */ + +#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */ +#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */ + +#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */ +#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */ + +#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */ +#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */ + +#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */ +#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */ + +#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */ +#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */ + +#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */ +#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */ + +#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */ +#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */ + +#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */ +#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */ + +#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */ +#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */ + +#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */ +#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */ + +#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */ +#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */ + +#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */ +#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */ + +#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */ +#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */ + +#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */ +#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */ + +#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */ +#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */ + +#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */ +#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */ + +#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */ +#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */ + +#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */ +#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */ + +#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */ +#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */ + +#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */ +#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */ + +#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */ +#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */ + +#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */ +#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */ + +#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */ +#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */ + +#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */ +#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */ + +#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */ +#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */ + +#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */ +#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */ + +#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */ +#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */ + +#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */ +#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */ + +#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */ +#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */ + +#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */ +#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */ + +#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */ +#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */ + +#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */ +#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */ + +#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */ +#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */ + +#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */ +#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */ + +#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */ +#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */ + +#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */ +#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */ + +/**@}*/ /* I2C_CONST */ +/**@}*/ /* end of I2C register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __I2C_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2s_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2s_reg.h new file mode 100644 index 00000000000..c0e57caf9b2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/i2s_reg.h @@ -0,0 +1,706 @@ +/**************************************************************************//** + * @file i2s_reg.h + * @version V1.00 + * @brief I2S register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2S_REG_H__ +#define __I2S_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup I2S I2S Interface Controller(I2S) + Memory Mapped Structure for I2S Controller +@{ */ + +typedef struct +{ + + + /** + * @var I2S_T::CTL0 + * Offset: 0x00 I2S Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Control + * | | |0 = I2S controller Disabled. + * | | |1 = I2S controller Enabled. + * |[1] |TXEN |Transmit Enable Control + * | | |0 = Data transmission Disabled. + * | | |1 = Data transmission Enabled. + * |[2] |RXEN |Receive Enable Control + * | | |0 = Data receiving Disabled. + * | | |1 = Data receiving Enabled. + * |[3] |MUTE |Transmit Mute Enable Control + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Send zero on transmit channel. + * |[5:4] |DATWIDTH |Data Width + * | | |This bit field is used to define the bit-width of data word in each audio channel + * | | |00 = The bit-width of data word is 8-bit. + * | | |01 = The bit-width of data word is 16-bit. + * | | |10 = The bit-width of data word is 24-bit. + * | | |11 = The bit-width of data word is 32-bit. + * |[6] |MONO |Monaural Data Control + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte + * | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries. + * | | |0 = Even channel data at high byte in 8-bit/16-bit data width. + * | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries. + * | | |1 = Even channel data at low byte. + * | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries. + * |[8] |SLAVE |Slave Mode Enable Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * | | |Note: I2S can operate as master or slave + * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip + * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. + * |[15] |MCLKEN |Master Clock Enable Control + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[18] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear TX FIFO. + * | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. + * | | |Note2: This bit is clear by hardware automatically, read it return zero. + * |[19] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear RX FIFO. + * | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty. + * | | |Note2: This bit is cleared by hardware automatically, read it return zero. + * |[20] |TXPDMAEN |Transmit PDMA Enable Control + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[21] |RXPDMAEN |Receive PDMA Enable Control + * | | |0 = Receiver PDMA function Disabled. + * | | |1 = Receiver PDMA function Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Control + * | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1. + * | | |0 = Receives channel1 data in MONO mode. + * | | |1 = Receives channel0 data in MONO mode. + * |[26:24] |FORMAT |Data Format Selection + * | | |000 = I2S standard data format. + * | | |001 = I2S with MSB justified. + * | | |010 = I2S with LSB justified. + * | | |011 = Reserved. + * | | |100 = PCM standard data format. + * | | |101 = PCM with MSB justified. + * | | |110 = PCM with LSB justified. + * | | |111 = Reserved. + * |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection + * | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol + * | | |0 = One BCLK period. + * | | |1 = One channel period. + * | | |Note: This bit is only available in master mode + * |[29:28] |CHWIDTH |Channel Width + * | | |This bit fields are used to define the length of audio channel + * | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH. + * | | |00 = The bit-width of each audio channel is 8-bit. + * | | |01 = The bit-width of each audio channel is 16-bit. + * | | |10 = The bit-width of each audio channel is 24-bit. + * | | |11 = The bit-width of each audio channel is 32-bit. + * |[31:30] |TDMCHNUM |TDM Channel Number + * | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1). + * | | |00 = 2 channels in audio frame. + * | | |01 = 4 channels in audio frame. + * | | |10 = 6 channels in audio frame. + * | | |11 = 8 channels in audio frame. + * @var I2S_T::CLKDIV + * Offset: 0x04 I2S Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MCLKDIV |Master Clock Divider + * | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip + * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input. + * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1. + * | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ). + * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ). + * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK + * |[16:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |Software can program these bit fields to generate sampling rate clock frequency. + * | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)). + * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK + * @var I2S_T::IEN + * Offset: 0x08 I2S Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. + * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1 + * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1 + * | | |If RXTHIEN bit is enabled, interrupt occur. + * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. + * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1 + * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]). + * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross + * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross + * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * @var I2S_T::STATUS0 + * Offset: 0x0C I2S Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SINT |I2S Interrupt Flag (Read Only) + * | | |0 = No I2S interrupt. + * | | |1 = I2S interrupt. + * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits. + * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only) + * | | |0 = No receive interrupt. + * | | |1 = Receive interrupt. + * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only) + * | | |0 = No transmit interrupt. + * | | |1 = Transmit interrupt. + * |[5:3] |DATACH |Transmission Data Channel (Read Only) + * | | |This bit fields are used to indicate which audio channel is current transmit data belong. + * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode). + * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode). + * | | |010 = channel2 (available while 4-channel TDM PCM mode). + * | | |011 = channel3 (available while 4-channel TDM PCM mode). + * | | |100 = channel4 (available while 6-channel TDM PCM mode). + * | | |101 = channel5 (available while 6-channel TDM PCM mode). + * | | |110 = channel6 (available while 8-channel TDM PCM mode). + * | | |111 = channel7 (available while 8-channel TDM PCM mode). + * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag + * | | |0 = No underflow occur. + * | | |1 = Underflow occur. + * | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again + * | | |This bit will be set to 1, and it indicates underflow situation occurs. + * | | |Note2: Write 1 to clear this bit to zero + * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag + * | | |0 = No overflow occur. + * | | |1 = Overflow occur. + * | | |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. + * | | |Note2: Write 1 to clear this bit to 0. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is not higher than threshold level. + * | | |1 = Data word(s) in FIFO is higher than threshold level. + * | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1 + * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. + * |[11] |RXFULL |Receive FIFO Full (Read Only) + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit reflects data words number in receive FIFO is 16. + * |[12] |RXEMPTY |Receive FIFO Empty (Read Only) + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit reflects data words number in receive FIFO is zero + * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag + * | | |0 = No underflow. + * | | |1 = Underflow. + * | | |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. + * | | |Note2: Write 1 to clear this bit to 0. + * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag + * | | |0 = No overflow. + * | | |1 = Overflow. + * | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1 + * | | |Note2: Write 1 to clear this bit to 0. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is higher than threshold level. + * | | |1 = Data word(s) in FIFO is equal or lower than threshold level. + * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1 + * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. + * |[19] |TXFULL |Transmit FIFO Full (Read Only) + * | | |This bit reflect data word number in transmit FIFO is 16 + * | | |0 = Not full. + * | | |1 = Full. + * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only) + * | | |This bit reflect data word number in transmit FIFO is zero + * | | |0 = Not empty. + * | | |1 = Empty. + * |[21] |TXBUSY |Transmit Busy (Read Only) + * | | |0 = Transmit shift buffer is empty. + * | | |1 = Transmit shift buffer is busy. + * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out + * | | |And set to 1 when 1st data is load to shift buffer + * @var I2S_T::TXFIFO + * Offset: 0x10 I2S Transmit FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXFIFO |Transmit FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data transmit + * | | |Write data to this register to prepare data for transmit + * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). + * @var I2S_T::RXFIFO + * Offset: 0x14 I2S Receive FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXFIFO |Receive FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data receive + * | | |Read this register to get data in FIFO + * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). + * @var I2S_T::CTL1 + * Offset: 0x20 I2S Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control + * | | |0 = channel0 zero-cross detect Disabled. + * | | |1 = channel0 zero-cross detect Enabled. + * | | |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. + * | | |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute. + * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control + * | | |0 = channel1 zero-cross detect Disabled. + * | | |1 = channel1 zero-cross detect Enabled. + * | | |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. + * | | |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute. + * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control + * | | |0 = channel2 zero-cross detect Disabled. + * | | |1 = channel2 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1. + * | | |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute. + * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control + * | | |0 = channel3 zero-cross detect Disabled. + * | | |1 = channel3 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1. + * | | |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute. + * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control + * | | |0 = channel4 zero-cross detect Disabled. + * | | |1 = channel4 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1. + * | | |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute. + * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control + * | | |0 = channel5 zero-cross detect Disabled. + * | | |1 = channel5 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1. + * | | |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute. + * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control + * | | |0 = channel6 zero-cross detect Disabled. + * | | |1 = channel6 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1. + * | | |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute. + * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control + * | | |0 = channel7 zero-cross detect Disabled. + * | | |1 = channel7 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1. + * | | |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute. + * |[11:8] |TXTH |Transmit FIFO Threshold Level + * | | |0000 = 0 data word in transmit FIFO. + * | | |0001 = 1 data word in transmit FIFO. + * | | |0010 = 2 data words in transmit FIFO. + * | | |... + * | | |1110 = 14 data words in transmit FIFO. + * | | |1111 = 15 data words in transmit FIFO. + * | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. + * |[19:16] |RXTH |Receive FIFO Threshold Level + * | | |0000 = 1 data word in receive FIFO. + * | | |0001 = 2 data words in receive FIFO. + * | | |0010 = 3 data words in receive FIFO. + * | | |... + * | | |1110 = 15 data words in receive FIFO. + * | | |1111 = 16 data words in receive FIFO. + * | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. + * |[24] |PBWIDTH |Peripheral Bus Data Width Selection + * | | |This bit is used to choice the available data width of APB bus + * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode + * | | |0 = 32 bits data width. + * | | |1 = 16 bits data width. + * | | |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available. + * | | |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations. + * | | |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations. + * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus + * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access + * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries. + * | | |0 = Low 16-bit read/write access first. + * | | |1 = High 16-bit read/write access first. + * | | |Note: This bit is available while PBWIDTH = 1. + * @var I2S_T::STATUS1 + * Offset: 0x24 I2S Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag + * | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel0. + * | | |1 = Channel0 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag + * | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel1. + * | | |1 = Channel1 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag + * | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel2. + * | | |1 = Channel2 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag + * | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel3. + * | | |1 = Channel3 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag + * | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel4. + * | | |1 = Channel4 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag + * | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel5. + * | | |1 = Channel5 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag + * | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel6. + * | | |1 = Channel6 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag + * | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel7. + * | | |1 = Channel7 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[12:8] |TXCNT |Transmit FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in transmit FIFO + * | | |00000 = No data. + * | | |00001 = 1 word in transmit FIFO. + * | | |00010 = 2 words in transmit FIFO. + * | | |... + * | | |01110 = 14 words in transmit FIFO. + * | | |01111 = 15 words in transmit FIFO. + * | | |10000 = 16 words in transmit FIFO. + * | | |Others are reserved. + * |[20:16] |RXCNT |Receive FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in receive FIFO + * | | |00000 = No data. + * | | |00001 = 1 word in receive FIFO. + * | | |00010 = 2 words in receive FIFO. + * | | |... + * | | |01110 = 14 words in receive FIFO. + * | | |01111 = 15 words in receive FIFO. + * | | |10000 = 16 words in receive FIFO. + * | | |Others are reserved. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */ + __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */ + __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */ + __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */ + __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */ + +} I2S_T; + +/** + @addtogroup I2S_CONST I2S Bit Field Definition + Constant Definitions for I2S Controller +@{ */ + +#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */ +#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */ + +#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */ +#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */ + +#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */ +#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */ + +#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */ +#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */ + +#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */ +#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */ + +#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */ +#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */ + +#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */ +#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */ + +#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */ +#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */ + +#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */ +#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */ + +#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */ +#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */ + +#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */ +#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */ + +#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */ +#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */ + +#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */ +#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */ + +#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */ +#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */ + +#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */ +#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */ + +#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */ +#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */ + +#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */ +#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */ + +#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */ +#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */ + +#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */ +#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */ + +#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */ +#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */ + +#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */ +#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */ + +#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */ +#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */ + +#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */ +#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */ + +#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */ +#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */ + +#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */ +#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */ + +#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */ +#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */ + +#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */ +#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */ + +#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */ +#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */ + +#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */ +#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */ + +#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */ +#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */ + +#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */ +#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */ + +#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */ +#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */ + +#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */ +#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */ + +#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */ +#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */ + +#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */ +#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */ + +#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */ +#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */ + +#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */ +#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */ + +#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */ +#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */ + +#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */ +#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */ + +#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */ +#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */ + +#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */ +#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */ + +#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */ +#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */ + +#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */ +#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */ + +#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */ +#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */ + +#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */ +#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */ + +#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */ +#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */ + +#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */ +#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */ + +#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */ +#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */ + +#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */ +#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */ + +#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */ +#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */ + +#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */ +#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */ + +#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */ +#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */ + +#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */ +#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */ + +#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */ +#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */ + +#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */ +#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */ + +#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */ +#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */ + +#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */ +#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */ + +#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */ +#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */ + +#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */ +#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */ + +#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */ +#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */ + +#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */ +#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */ + +#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */ +#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */ + +#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */ +#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */ + +#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */ +#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */ + +#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */ +#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */ + +#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */ +#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */ + +#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */ +#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */ + +#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */ +#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */ + +#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */ +#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */ + +#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */ +#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */ + +#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */ +#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */ + +#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */ +#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */ + +#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */ +#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */ + +/**@}*/ /* I2S_CONST */ +/**@}*/ /* end of I2S register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __I2S_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/opa_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/opa_reg.h new file mode 100644 index 00000000000..3f36202d37a --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/opa_reg.h @@ -0,0 +1,267 @@ +/**************************************************************************//** + * @file opa_reg.h + * @version V1.00 + * @brief OPA register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OPA_REG_H__ +#define __OPA_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup OPA OP Amplifier(OPA) + Memory Mapped Structure for OPA Controller +@{ */ + +typedef struct +{ + + + /** + * @var OPA_T::CTL + * Offset: 0x00 OP Amplifier Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPEN0 |OP Amplifier 0 Enable Bit + * | | |0 = OP amplifier0 Disabled. + * | | |1 = OP amplifier0 Enabled. + * | | |Note: OP Amplifier 0 output needs wait stable 20u03BCs after OPEN0 is set. + * |[1] |OPEN1 |OP Amplifier 1 Enable Bit + * | | |0 = OP amplifier1 Disabled. + * | | |1 = OP amplifier1 Enabled. + * | | |Note: OP Amplifier 1 output needs wait stable 20u03BCs after OPEN1 is set. + * |[2] |OPEN2 |OP Amplifier 2 Enable Bit + * | | |0 = OP amplifier2 Disabled. + * | | |1 = OP amplifier2 Enabled. + * | | |Note: OP Amplifier 2 output needs wait stable 20u03BCs after OPEN2 is set. + * |[4] |OPDOEN0 |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit + * | | |0 = OP amplifier0 Schmitt Trigger non-invert buffer Disabled. + * | | |1 = OP amplifier0 Schmitt Trigger non-invert buffer Enabled. + * |[5] |OPDOEN1 |OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit + * | | |0 = OP amplifier1 Schmitt Trigger non-invert buffer Disabled. + * | | |1 = OP amplifier1 Schmitt Trigger non-invert buffer Enabled. + * |[6] |OPDOEN2 |OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit + * | | |0 = OP amplifier2 Schmitt Trigger non-invert buffer Disabled. + * | | |1 = OP amplifier2 Schmitt Trigger non-invert buffer Enabled. + * |[8] |OPDOIEN0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit + * | | |0 = OP Amplifier 0 digital output interrupt function Disabled. + * | | |1 = OP Amplifier 0 digital output interrupt function Enabled. + * | | |The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated. + * |[9] |OPDOIEN1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit + * | | |0 = OP Amplifier 1 digital output interrupt function Disabled. + * | | |1 = OP Amplifier 1 digital output interrupt function Enabled. + * | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN1 is set to 1, a comparator interrupt request is generated. + * |[10] |OPDOIEN2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit + * | | |0 = OP Amplifier 2 digital output interrupt function Disabled. + * | | |1 = OP Amplifier 2 digital output interrupt function Enabled. + * | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN2 is set to 1, a comparator interrupt request is generated. + * @var OPA_T::STATUS + * Offset: 0x04 OP Amplifier Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPDO0 |OP Amplifier 0 Digital Output + * | | |Synchronized to the APB clock to allow reading by software + * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN0 = 0) + * |[1] |OPDO1 |OP Amplifier 1 Digital Output + * | | |Synchronized to the APB clock to allow reading by software + * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN1 = 0) + * |[2] |OPDO2 |OP Amplifier 2 Digital Output + * | | |Synchronized to the APB clock to allow reading by software + * | | |Cleared when the Schmitt Trigger buffer is disabled (OPDOEN2 = 0) + * |[4] |OPDOIF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag + * | | |OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt Trigger non-inverting buffer digital output changes state + * | | |This bit is cleared by writing 1 to it. + * |[5] |OPDOIF1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag + * | | |OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt Trigger non-inverting buffer digital output changes state + * | | |This bit is cleared by writing 1 to it. + * |[6] |OPDOIF2 |OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag + * | | |OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt Trigger non-inverting buffer digital output changes state + * | | |This bit is cleared by writing 1 to it. + * @var OPA_T::CALCTL + * Offset: 0x08 OP Amplifier Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CALTRG0 |OP Amplifier 0 Calibration Trigger Bit + * | | |0 = Stop, hardware auto clear. + * | | |1 = Start. Note: Before enable this bit, it should set OPEN0 in advance. + * |[1] |CALTRG1 |OP Amplifier 1 Calibration Trigger Bit + * | | |0 = Stop, hardware auto clear. + * | | |1 = Start. Note: Before enable this bit, it should set OPEN1 in advance. + * |[2] |CALTRG2 |OP Amplifier 2 Calibration Trigger Bit + * | | |0 = Stop, hardware auto clear. + * | | |1 = Start. Note: Before enable this bit, it should set OPEN2 in advance. + * |[16] |CALRVS0 |OPA0 Calibration Reference Voltage Selection + * | | |0 = VREF is AVDD. + * | | |1 = VREF from high vcm to low vcm. + * |[17] |CALRVS1 |OPA1 Calibration Reference Voltage Selection + * | | |0 = VREF is AVDD. + * | | |1 = VREF from high vcm to low vcm. + * |[18] |CALRVS2 |OPA2 Calibration Reference Voltage Selection + * | | |0 = VREF is AVDD. + * | | |1 = VREF from high vcm to low vcm. + * @var OPA_T::CALST + * Offset: 0x0C OP Amplifier Calibration Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DONE0 |OP Amplifier 0 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Done. + * |[1] |CALNS0 |OP Amplifier 0 Calibration Result Status for NMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[2] |CALPS0 |OP Amplifier 0 Calibration Result Status for PMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[4] |DONE1 |OP Amplifier 1 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Done. + * |[5] |CALNS1 |OP Amplifier 1 Calibration Result Status for NMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[6] |CALPS1 |OP Amplifier 1 Calibration Result Status for PMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[8] |DONE2 |OP Amplifier 2 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Done. + * |[9] |CALNS2 |OP Amplifier 2 Calibration Result Status for NMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[10] |CALPS2 |OP Amplifier 2 Calibration Result Status for PMOS + * | | |0 = Pass. + * | | |1 = Fail. + */ + __IO uint32_t CTL; /*!< [0x0000] OP Amplifier Control Register */ + __IO uint32_t STATUS; /*!< [0x0004] OP Amplifier Status Register */ + __IO uint32_t CALCTL; /*!< [0x0008] OP Amplifier Calibration Control Register */ + __I uint32_t CALST; /*!< [0x000c] OP Amplifier Calibration Status Register */ + +} OPA_T; + +/** + @addtogroup OPA_CONST OPA Bit Field Definition + Constant Definitions for OPA Controller +@{ */ + +#define OPA_CTL_OPEN0_Pos (0) /*!< OPA_T::CTL: OPEN0 Position */ +#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA_T::CTL: OPEN0 Mask */ + +#define OPA_CTL_OPEN1_Pos (1) /*!< OPA_T::CTL: OPEN1 Position */ +#define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /*!< OPA_T::CTL: OPEN1 Mask */ + +#define OPA_CTL_OPEN2_Pos (2) /*!< OPA_T::CTL: OPEN2 Position */ +#define OPA_CTL_OPEN2_Msk (0x1ul << OPA_CTL_OPEN2_Pos) /*!< OPA_T::CTL: OPEN2 Mask */ + +#define OPA_CTL_OPDOEN0_Pos (4) /*!< OPA_T::CTL: OPDOEN0 Position */ +#define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) /*!< OPA_T::CTL: OPDOEN0 Mask */ + +#define OPA_CTL_OPDOEN1_Pos (5) /*!< OPA_T::CTL: OPDOEN1 Position */ +#define OPA_CTL_OPDOEN1_Msk (0x1ul << OPA_CTL_OPDOEN1_Pos) /*!< OPA_T::CTL: OPDOEN1 Mask */ + +#define OPA_CTL_OPDOEN2_Pos (6) /*!< OPA_T::CTL: OPDOEN2 Position */ +#define OPA_CTL_OPDOEN2_Msk (0x1ul << OPA_CTL_OPDOEN2_Pos) /*!< OPA_T::CTL: OPDOEN2 Mask */ + +#define OPA_CTL_OPDOIEN0_Pos (8) /*!< OPA_T::CTL: OPDOIEN0 Position */ +#define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) /*!< OPA_T::CTL: OPDOIEN0 Mask */ + +#define OPA_CTL_OPDOIEN1_Pos (9) /*!< OPA_T::CTL: OPDOIEN1 Position */ +#define OPA_CTL_OPDOIEN1_Msk (0x1ul << OPA_CTL_OPDOIEN1_Pos) /*!< OPA_T::CTL: OPDOIEN1 Mask */ + +#define OPA_CTL_OPDOIEN2_Pos (10) /*!< OPA_T::CTL: OPDOIEN2 Position */ +#define OPA_CTL_OPDOIEN2_Msk (0x1ul << OPA_CTL_OPDOIEN2_Pos) /*!< OPA_T::CTL: OPDOIEN2 Mask */ + +#define OPA_STATUS_OPDO0_Pos (0) /*!< OPA_T::STATUS: OPDO0 Position */ +#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA_T::STATUS: OPDO0 Mask */ + +#define OPA_STATUS_OPDO1_Pos (1) /*!< OPA_T::STATUS: OPDO1 Position */ +#define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /*!< OPA_T::STATUS: OPDO1 Mask */ + +#define OPA_STATUS_OPDO2_Pos (2) /*!< OPA_T::STATUS: OPDO2 Position */ +#define OPA_STATUS_OPDO2_Msk (0x1ul << OPA_STATUS_OPDO2_Pos) /*!< OPA_T::STATUS: OPDO2 Mask */ + +#define OPA_STATUS_OPDOIF0_Pos (4) /*!< OPA_T::STATUS: OPDOIF0 Position */ +#define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) /*!< OPA_T::STATUS: OPDOIF0 Mask */ + +#define OPA_STATUS_OPDOIF1_Pos (5) /*!< OPA_T::STATUS: OPDOIF1 Position */ +#define OPA_STATUS_OPDOIF1_Msk (0x1ul << OPA_STATUS_OPDOIF1_Pos) /*!< OPA_T::STATUS: OPDOIF1 Mask */ + +#define OPA_STATUS_OPDOIF2_Pos (6) /*!< OPA_T::STATUS: OPDOIF2 Position */ +#define OPA_STATUS_OPDOIF2_Msk (0x1ul << OPA_STATUS_OPDOIF2_Pos) /*!< OPA_T::STATUS: OPDOIF2 Mask */ + +#define OPA_CALCTL_CALTRG0_Pos (0) /*!< OPA_T::CALCTL: CALTRG0 Position */ +#define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) /*!< OPA_T::CALCTL: CALTRG0 Mask */ + +#define OPA_CALCTL_CALTRG1_Pos (1) /*!< OPA_T::CALCTL: CALTRG1 Position */ +#define OPA_CALCTL_CALTRG1_Msk (0x1ul << OPA_CALCTL_CALTRG1_Pos) /*!< OPA_T::CALCTL: CALTRG1 Mask */ + +#define OPA_CALCTL_CALTRG2_Pos (2) /*!< OPA_T::CALCTL: CALTRG2 Position */ +#define OPA_CALCTL_CALTRG2_Msk (0x1ul << OPA_CALCTL_CALTRG2_Pos) /*!< OPA_T::CALCTL: CALTRG2 Mask */ + +#define OPA_CALCTL_CALCLK0_Pos (4) /*!< OPA_T::CALCTL: CALCLK0 Position */ +#define OPA_CALCTL_CALCLK0_Msk (0x3ul << OPA_CALCTL_CALCLK0_Pos) /*!< OPA_T::CALCTL: CALCLK0 Mask */ + +#define OPA_CALCTL_CALCLK1_Pos (6) /*!< OPA_T::CALCTL: CALCLK1 Position */ +#define OPA_CALCTL_CALCLK1_Msk (0x3ul << OPA_CALCTL_CALCLK1_Pos) /*!< OPA_T::CALCTL: CALCLK1 Mask */ + +#define OPA_CALCTL_CALCLK2_Pos (8) /*!< OPA_T::CALCTL: CALCLK2 Position */ +#define OPA_CALCTL_CALCLK2_Msk (0x3ul << OPA_CALCTL_CALCLK2_Pos) /*!< OPA_T::CALCTL: CALCLK2 Mask */ + +#define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */ +#define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */ + +#define OPA_CALCTL_CALRVS1_Pos (17) /*!< OPA_T::CALCTL: CALRVS1 Position */ +#define OPA_CALCTL_CALRVS1_Msk (0x1ul << OPA_CALCTL_CALRVS1_Pos) /*!< OPA_T::CALCTL: CALRVS1 Mask */ + +#define OPA_CALCTL_CALRVS2_Pos (18) /*!< OPA_T::CALCTL: CALRVS2 Position */ +#define OPA_CALCTL_CALRVS2_Msk (0x1ul << OPA_CALCTL_CALRVS2_Pos) /*!< OPA_T::CALCTL: CALRVS2 Mask */ + +#define OPA_CALST_DONE0_Pos (0) /*!< OPA_T::CALST: DONE0 Position */ +#define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) /*!< OPA_T::CALST: DONE0 Mask */ + +#define OPA_CALST_CALNS0_Pos (1) /*!< OPA_T::CALST: CALNS0 Position */ +#define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) /*!< OPA_T::CALST: CALNS0 Mask */ + +#define OPA_CALST_CALPS0_Pos (2) /*!< OPA_T::CALST: CALPS0 Position */ +#define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) /*!< OPA_T::CALST: CALPS0 Mask */ + +#define OPA_CALST_DONE1_Pos (4) /*!< OPA_T::CALST: DONE1 Position */ +#define OPA_CALST_DONE1_Msk (0x1ul << OPA_CALST_DONE1_Pos) /*!< OPA_T::CALST: DONE1 Mask */ + +#define OPA_CALST_CALNS1_Pos (5) /*!< OPA_T::CALST: CALNS1 Position */ +#define OPA_CALST_CALNS1_Msk (0x1ul << OPA_CALST_CALNS1_Pos) /*!< OPA_T::CALST: CALNS1 Mask */ + +#define OPA_CALST_CALPS1_Pos (6) /*!< OPA_T::CALST: CALPS1 Position */ +#define OPA_CALST_CALPS1_Msk (0x1ul << OPA_CALST_CALPS1_Pos) /*!< OPA_T::CALST: CALPS1 Mask */ + +#define OPA_CALST_DONE2_Pos (8) /*!< OPA_T::CALST: DONE2 Position */ +#define OPA_CALST_DONE2_Msk (0x1ul << OPA_CALST_DONE2_Pos) /*!< OPA_T::CALST: DONE2 Mask */ + +#define OPA_CALST_CALNS2_Pos (9) /*!< OPA_T::CALST: CALNS2 Position */ +#define OPA_CALST_CALNS2_Msk (0x1ul << OPA_CALST_CALNS2_Pos) /*!< OPA_T::CALST: CALNS2 Mask */ + +#define OPA_CALST_CALPS2_Pos (10) /*!< OPA_T::CALST: CALPS2 Position */ +#define OPA_CALST_CALPS2_Msk (0x1ul << OPA_CALST_CALPS2_Pos) /*!< OPA_T::CALST: CALPS2 Mask */ + +/**@}*/ /* OPA_CONST */ +/**@}*/ /* end of OPA register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __OPA_REG_H__ */ + diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/otg_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/otg_reg.h new file mode 100644 index 00000000000..f88158805fa --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/otg_reg.h @@ -0,0 +1,398 @@ +/**************************************************************************//** + * @file otg_reg.h + * @version V1.00 + * @brief OTG register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OTG_REG_H__ +#define __OTG_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup OTG USB On-The-Go Controller(OTG) + Memory Mapped Structure for OTG Controller +@{ */ + +typedef struct +{ + + + /** + * @var OTG_T::CTL + * Offset: 0x00 OTG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDROP |Drop VBUS Control + * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS + * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. + * | | |0 = Not drop the VBUS. + * | | |1 = Drop the VBUS. + * |[1] |BUSREQ |OTG Bus Request + * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection + * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power + * | | |This bit will be cleared when A-device goes to A_wait_vfall state + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol + * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification) + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed. + * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. + * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. + * |[2] |HNPREQEN |OTG HNP Request Enable Bit + * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral + * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state + * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host + * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. + * | | |0 = HNP request Disabled. + * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). + * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. + * |[4] |OTGEN |OTG Function Enable Bit + * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device + * | | |When USB frame not configured as OTG device, this bit is must be low. + * | | |0= OTG function Disabled. + * | | |1 = OTG function Enabled. + * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit + * | | |0 = OTG ID pin status change wake-up function Disabled. + * | | |1 = OTG ID pin status change wake-up function Enabled. + * @var OTG_T::PHYCTL + * Offset: 0x04 OTG PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OTGPHYEN |OTG PHY Enable + * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function + * | | |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care". + * | | |0 = OTG PHY Disabled. + * | | |1 = OTG PHY Enabled. + * |[1] |IDDETEN |ID Detection Enable Bit + * | | |0 = Detect ID pin status Disabled. + * | | |1 = Detect ID pin status Enabled. + * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity + * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need + * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. + * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The off-chip USB VBUS power switch enable is active high. + * | | |1 = The off-chip USB VBUS power switch enable is active low. + * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity + * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component + * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. + * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. + * @var OTG_T::INTEN + * Offset: 0x08 OTG Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec. + * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Going to idle state means going to a_idle or b_idle state + * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. + * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted. + * | | |0 = This device as a peripheral interrupt Disabled. + * | | |1 = This device as a peripheral interrupt Enabled. + * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted. + * | | |0 = This device as a host interrupt Disabled. + * | | |1 = This device as a host interrupt Enabled. + * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var OTG_T::INTSTS + * Offset: 0x0C OTG Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIF |OTG Role Change Interrupt Status + * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. + * | | |0 = OTG device role not changed. + * | | |1 = OTG device role changed. + * | | |Note: Write 1 to clear this flag. + * |[1] |VBEIF |VBUS Error Interrupt Status + * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. + * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. + * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. + * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. + * |[2] |SRPFIF |SRP Fail Interrupt Status + * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification + * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. + * | | |0 = OTG B-device gets VBUS high before this interval. + * | | |1 = OTG B-device does not get VBUS high before this interval. + * | | |Note: Write 1 to clear this flag. + * |[3] |HNPFIF |HNP Fail Interrupt Status + * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. + * | | |0 = A-device connects to B-device before specified interval expires. + * | | |1 = A-device does not connect to B-device before specified interval expires. + * | | |Note: Write 1 to clear this flag. + * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status + * | | |Flag is set if the OTG device transfers from non-idle state to idle state + * | | |The OTG device will be neither a host nor a peripheral. + * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). + * | | |1 = OTG device goes back to idle state(a_idle or b_idle). + * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. + * | | |Note 2: Write 1 to clear this flag. + * |[5] |IDCHGIF |ID State Change Interrupt Status + * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. + * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[6] |PDEVIF |Act As Peripheral Interrupt Status + * | | |0= This device does not act as a peripheral. + * | | |1 = This device acts as a peripheral. + * | | |Note: Write 1 to clear this flag. + * |[7] |HOSTIF |Act As Host Interrupt Status + * | | |0= This device does not act as a host. + * | | |1 = This device acts as a host. + * | | |Note: Write 1 to clear this flag. + * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status + * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. + * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status + * | | |0 = AVLD (OTG_STATUS[4]) not toggled. + * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status + * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. + * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. + * | | |Note: Write 1 to clear this status. + * |[11] |SECHGIF |SESSEND State Change Interrupt Status + * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. + * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[13] |SRPDETIF |SRP Detected Interrupt Status + * | | |0 = SRP not detected. + * | | |1 = SRP detected. + * | | |Note: Write 1 to clear this status. + * @var OTG_T::STATUS + * Offset: 0x10 OTG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OVERCUR |over Current Condition + * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. + * | | |0 = OTG A-device drives VBUS successfully. + * | | |1 = OTG A-device cannot drives VBUS high in this interval. + * |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug + * | | |0 = Mini-A/Micro-A plug is attached. + * | | |1 = Mini-B/Micro-B plug is attached. + * |[2] |SESSEND |Session End Status + * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 + * | | |Session end means no meaningful power on VBUS. + * | | |0 = Session is not end. + * | | |1 = Session is end. + * |[3] |BVLD |B-device Session Valid Status + * | | |0 = B-device session is not valid. + * | | |1 = B-device session is valid. + * |[4] |AVLD |A-device Session Valid Status + * | | |0 = A-device session is not valid. + * | | |1 = A-device session is valid. + * |[5] |VBUSVLD |VBUS Valid Status + * | | |When VBUS is larger than 4.7V, this bit will be set to 1. + * | | |0 = VBUS is not valid. + * | | |1 = VBUS is valid. + * |[6] |ASPERI |As Peripheral Status + * | | |When OTG as peripheral, this bit is set. + * | | |0: OTG not as peripheral + * | | |1: OTG as peripheral + * |[7] |ASHOST |As Host Status + * | | |When OTG as Host, this bit is set. + * | | |0: OTG not as Host + * | | |1: OTG as Host + */ + __IO uint32_t CTL; /*!< [0x0000] OTG Control Register */ + __IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */ + __IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */ + __I uint32_t STATUS; /*!< [0x0010] OTG Status Register */ + +} OTG_T; + + +/** + @addtogroup OTG_CONST OTG Bit Field Definition + Constant Definitions for OTG Controller +@{ */ + +#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */ +#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */ + +#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */ +#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */ + +#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */ +#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */ + +#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */ +#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */ + +#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */ +#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */ + +#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */ +#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */ + +#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */ +#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */ + +#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */ +#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */ + +#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */ +#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */ + +#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */ +#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */ + +#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */ +#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */ + +#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */ +#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */ + +#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */ +#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */ + +#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */ +#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */ + +#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */ +#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */ + +#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */ +#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */ + +#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */ +#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */ + +#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */ +#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */ + +#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */ +#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */ + +#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */ +#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */ + +#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */ +#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */ + +#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */ +#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */ + +#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */ +#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */ + +#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */ +#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */ + +#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */ +#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */ + +#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */ +#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */ + +#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */ +#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */ + +#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */ +#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */ + +#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */ +#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */ + +#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */ +#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */ + +#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */ +#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */ + +#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */ +#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */ + +#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */ +#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */ + +#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */ +#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */ + +#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */ +#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */ + +#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */ +#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */ + +#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */ +#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */ + +#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */ +#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */ + +#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */ +#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */ + +#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */ +#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */ + +#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */ +#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */ + +#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */ +#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */ + +#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */ +#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */ + +/**@}*/ /* OTG_CONST */ +/**@}*/ /* end of OTG register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __OTG_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/pdma_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/pdma_reg.h new file mode 100644 index 00000000000..0cc32c212ed --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/pdma_reg.h @@ -0,0 +1,848 @@ +/**************************************************************************//** + * @file pdma_reg.h + * @version V1.00 + * @brief PDMA register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_REG_H__ +#define __PDMA_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA) + Memory Mapped Structure for PDMA Controller +@{ */ + + +typedef struct +{ + + /** + * @var DSCT_T::CTL + * Offset: 0x00 Descriptor Table Control Register of PDMA Channel n. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE |PDMA Operation Mode Selection + * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. + * | | |01 = Basic mode: The descriptor table only has one task + * | | |When this task is finished, the PDMA_INTSTS[n] will be asserted. + * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute. + * | | |11 = Reserved. + * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. + * |[2] |TXTYPE |Transfer Type + * | | |0 = Burst transfer type. + * | | |1 = Single transfer type. + * |[6:4] |BURSIZE |Burst Size + * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. + * | | |000 = 128 Transfers. + * | | |001 = 64 Transfers. + * | | |010 = 32 Transfers. + * | | |011 = 16 Transfers. + * | | |100 = 8 Transfers. + * | | |101 = 4 Transfers. + * | | |110 = 2 Transfers. + * | | |111 = 1 Transfers. + * | | |Note: This field is only useful in burst transfer type. + * |[7] |TBINTDIS |Table Interrupt Disable Bit + * | | |This field can be used to decide whether to enable table interrupt or not + * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. + * | | |0 = Table interrupt Enabled. + * | | |1 = Table interrupt Disabled. + * |[9:8] |SAINC |Source Address Increment + * | | |This field is used to set the source address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[11:10] |DAINC |Destination Address Increment + * | | |This field is used to set the destination address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[13:12] |TXWIDTH |Transfer Width Selection + * | | |This field is used for transfer width. + * | | |00 = One byte (8 bit) is transferred for every operation. + * | | |01= One half-word (16 bit) is transferred for every operation. + * | | |10 = One word (32-bit) is transferred for every operation. + * | | |11 = Reserved. + * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection + * |[14] |TXACK |Transfer Acknowledge Selection + * | | |0 = transfer ack when transfer done. + * | | |1 = transfer ack when PDMA get transfer data. + * |[15] |STRIDEEN |Stride Mode Enable Bit + * | | |0 = Stride transfer mode Disabled. + * | | |1 = Stride transfer mode Enabled. + * |[31:16] |TXCNT |Transfer Count + * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. + * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately. + * @var DSCT_T::SA + * Offset: 0x04 Source Address Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SA |PDMA Transfer Source Address Register + * | | |This field indicates a 32-bit source address of PDMA controller. + * @var DSCT_T::DA + * Offset: 0x08 Destination Address Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DA |PDMA Transfer Destination Address Register + * | | |This field indicates a 32-bit destination address of PDMA controller. + * @var DSCT_T::NEXT + * Offset: 0x0C Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |EXENEXT |PDMA Execution Next Descriptor Table Offset + * | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. + * | | |Note: write operation is useless in this field. + * |[31:16] |NEXT |PDMA Next Descriptor Table Offset. + * | | |This field indicates the offset of the next descriptor table address in system memory. + * | | |Write Operation: + * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. + * | | |Read Operation: + * | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. + * | | |Note1: The descriptor table address must be word boundary. + * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. + */ + __IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */ + __IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */ + __IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */ + __IO uint32_t NEXT; /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */ +} DSCT_T; + + +typedef struct +{ + /** + * @var STRIDE_T::STCR + * Offset: 0x500 Stride Transfer Count Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STC |PDMA Stride Transfer Count + * | | |The 16-bit register defines the stride transfer count of each row. + * @var STRIDE_T::ASOCR + * Offset: 0x504 Address Stride Offset Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SASOL |VDMA Source Address Stride Offset Length + * | | |The 16-bit register defines the source address stride transfer offset count of each row. + * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length + * | | |The 16-bit register defines the destination address stride transfer offset count of each row. + */ + __IO uint32_t STCR; /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0 */ + __IO uint32_t ASOCR; /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0 */ +} STRIDE_T; + +typedef struct +{ + + + /** + * @var PDMA_T::CURSCAT + * Offset: 0x100 Current Scatter-Gather Descriptor Table Address of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only) + * | | |This field indicates a 32-bit current external description address of PDMA controller. + * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. + * @var PDMA_T::CHCTL + * Offset: 0x400 PDMA Channel Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHENn |PDMA Channel Enable Bit + * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. + * | | |0 = PDMA channel [n] Disabled. + * | | |1 = PDMA channel [n] Enabled. + * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. + * @var PDMA_T::PAUSE + * Offset: 0x404 PDMA Transfer Stop Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only) + * | | |User can set PAUSEn bit field to pause the PDMA transfer + * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag + * | | |If re-enable the paused channel again, the remaining transfers will be processed. + * | | |0 = No effect. + * | | |1 = Pause PDMA channel n transfer. + * @var PDMA_T::SWREQ + * Offset: 0x408 PDMA Software Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SWREQn |PDMA Software Request Register (Write Only) + * | | |Set this bit to 1 to generate a software request to PDMA [n]. + * | | |0 = No effect. + * | | |1 = Generate a software request. + * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active + * | | |Active flag may be triggered by software request or peripheral request. + * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored. + * @var PDMA_T::TRGSTS + * Offset: 0x40C PDMA Channel Request Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only) + * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral + * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. + * | | |0 = PDMA Channel n has no request. + * | | |1 = PDMA Channel n has a request. + * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer. + * @var PDMA_T::PRISET + * Offset: 0x410 PDMA Fixed Priority Setting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register + * | | |Set this bit to 1 to enable fixed priority level. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set PDMA channel [n] to fixed priority channel. + * | | |Read Operation: + * | | |0 = Corresponding PDMA channel is round-robin priority. + * | | |1 = Corresponding PDMA channel is fixed priority. + * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. + * @var PDMA_T::PRICLR + * Offset: 0x414 PDMA Fixed Priority Clear Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only) + * | | |Set this bit to 1 to clear fixed priority level. + * | | |0 = No effect. + * | | |1 = Clear PDMA channel [n] fixed priority setting. + * | | |Note: User can read PDMA_PRISET register to know the channel priority. + * @var PDMA_T::INTEN + * Offset: 0x418 PDMA Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |INTENn |PDMA Interrupt Enable Register + * | | |This field is used for enabling PDMA channel[n] interrupt. + * | | |0 = PDMA channel n interrupt Disabled. + * | | |1 = PDMA channel n interrupt Enabled. + * @var PDMA_T::INTSTS + * Offset: 0x41C PDMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-only) + * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. + * | | |0 = No AHB bus ERROR response received. + * | | |1 = AHB bus ERROR response received. + * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. + * | | |0 = Not finished yet. + * | | |1 = PDMA channel has finished transmission. + * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * @var PDMA_T::ABTSTS + * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag + * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. + * | | |0 = No AHB bus ERROR response received when channel n transfer. + * | | |1 = AHB bus ERROR response received when channel n transfer. + * @var PDMA_T::TDSTS + * Offset: 0x424 PDMA Channel Transfer Done Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TDIFn |Transfer Done Flag Register + * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. + * | | |0 = PDMA channel transfer has not finished. + * | | |1 = PDMA channel has finished transmission. + * @var PDMA_T::ALIGN + * Offset: 0x428 PDMA Transfer Alignment Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ALIGNn |Transfer Alignment Flag Register + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * @var PDMA_T::TACTSTS + * Offset: 0x42C PDMA Transfer Active Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only) + * | | |This bit indicates which PDMA channel is in active. + * | | |0 = PDMA channel is not finished. + * | | |1 = PDMA channel is active. + * @var PDMA_T::TOUTPSC + * Offset: 0x430 PDMA Time-out Prescaler Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 0 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 0 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 0 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 0 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 0 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 0 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 0 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 0 time-out clock source is HCLK/215. + * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 1 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 1 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 1 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 1 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 1 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 1 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 1 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 1 time-out clock source is HCLK/215. + * @var PDMA_T::TOUTEN + * Offset: 0x434 PDMA Time-out Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TOUTENn |PDMA Time-out Enable Bits + * | | |0 = PDMA Channel n time-out function Disable. + * | | |1 = PDMA Channel n time-out function Enable. + * @var PDMA_T::TOUTIEN + * Offset: 0x438 PDMA Time-out Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits + * | | |0 = PDMA Channel n time-out interrupt Disable. + * | | |1 = PDMA Channel n time-out interrupt Enable. + * @var PDMA_T::SCATBA + * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register + * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address + * | | |The next link address equation is + * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. + * | | |Note: Only useful in Scatter-Gather mode. + * @var PDMA_T::TOC0_1 + * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC0 |Time-out Counter for Channel 0 + * | | |This controls the period of time-out function for channel 0 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC1 |Time-out Counter for Channel 1 + * | | |This controls the period of time-out function for channel 1 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::CHRST + * Offset: 0x460 PDMA Channel Reset Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHnRST |Channel N Reset + * | | |0 = corresponding channel n not reset. + * | | |1 = corresponding channel n is reset. + * @var PDMA_T::REQSEL0_3 + * Offset: 0x480 PDMA Request Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC0 |Channel 0 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 0 + * | | |User can configure the peripheral by setting REQSRC0. + * | | |0 = Disable PDMA peripheral request. + * | | |1 = Reserved. + * | | |2 = Channel connects to USB_TX. + * | | |3 = Channel connects to USB_RX. + * | | |4 = Channel connects to UART0_TX. + * | | |5 = Channel connects to UART0_RX. + * | | |6 = Channel connects to UART1_TX. + * | | |7 = Channel connects to UART1_RX. + * | | |8 = Channel connects to UART2_TX. + * | | |9 = Channel connects to UART2_RX. + * | | |10=Channel connects to UART3_TX. + * | | |11 = Channel connects to UART3_RX. + * | | |12 = Channel connects to UART4_TX. + * | | |13 = Channel connects to UART4_RX. + * | | |14 = Channel connects to UART5_TX. + * | | |15 = Channel connects to UART5_RX. + * | | |16 = Channel connects to USCI0_TX. + * | | |17 = Channel connects to USCI0_RX. + * | | |18 = Channel connects to USCI1_TX. + * | | |19 = Channel connects to USCI1_RX. + * | | |20 = Channel connects to QSPI0_TX. + * | | |21 = Channel connects to QSPI0_RX. + * | | |22 = Channel connects to SPI0_TX. + * | | |23 = Channel connects to SPI0_RX. + * | | |24 = Channel connects to SPI1_TX. + * | | |25 = Channel connects to SPI1_RX. + * | | |26 = Channel connects to SPI2_TX. + * | | |27 = Channel connects to SPI2_RX. + * | | |28 = Channel connects to SPI3_TX. + * | | |29 = Channel connects to SPI3_RX. + * | | |30 = Reserved. + * | | |31 = Reserved. + * | | |32 = Channel connects to EPWM0_P1_RX. + * | | |33 = Channel connects to EPWM0_P2_RX. + * | | |34 = Channel connects to EPWM0_P3_RX. + * | | |35 = Channel connects to EPWM1_P1_RX. + * | | |36 = Channel connects to EPWM1_P2_RX. + * | | |37 = Channel connects to EPWM1_P3_RX. + * | | |38 = Channel connects to I2C0_TX. + * | | |39 = Channel connects to I2C0_RX. + * | | |40 = Channel connects to I2C1_TX. + * | | |41 = Channel connects to I2C1_RX. + * | | |42 = Channel connects to I2C2_TX. + * | | |43 = Channel connects to I2C2_RX. + * | | |44 = Channel connects to I2S0_TX. + * | | |45 = Channel connects to I2S0_RX. + * | | |46 = Channel connects to TMR0. + * | | |47 = Channel connects to TMR1. + * | | |48 = Channel connects to TMR2. + * | | |49 = Channel connects to TMR3. + * | | |50 = Channel connects to ADC_RX. + * | | |51 = Channel connects to DAC0_TX. + * | | |52 = Channel connects to DAC1_TX. + * | | |53 = Channel connects to EPWM0_CH0_TX. + * | | |54 = Channel connects to EPWM0_CH1_TX. + * | | |55 = Channel connects to EPWM0_CH2_TX. + * | | |56 = Channel connects to EPWM0_CH3_TX. + * | | |57 = Channel connects to EPWM0_CH4_TX. + * | | |58 = Channel connects to EPWM0_CH5_TX. + * | | |59 = Channel connects to EPWM1_CH0_TX. + * | | |60 = Channel connects to EPWM1_CH1_TX. + * | | |61 = Channel connects to EPWM1_CH2_TX. + * | | |62 = Channel connects to EPWM1_CH3_TX. + * | | |63 = Channel connects to EPWM1_CH4_TX. + * | | |64 = Channel connects to EPWM1_CH5_TX. + * | | |65 = Channel connects to ETMC_RX. + * | | |Others = Reserved. + * | | |Note 1: A peripheral can't assign to two channels at the same time. + * | | |Note 2: This field is useless when transfer between memory and memory. + * |[14:8] |REQSRC1 |Channel 1 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 1 + * | | |User can configure the peripheral setting by REQSRC1. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC2 |Channel 2 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 2 + * | | |User can configure the peripheral setting by REQSRC2. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC3 |Channel 3 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 3 + * | | |User can configure the peripheral setting by REQSRC3. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL4_7 + * Offset: 0x484 PDMA Request Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC4 |Channel 4 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 4 + * | | |User can configure the peripheral setting by REQSRC4. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC5 |Channel 5 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 5 + * | | |User can configure the peripheral setting by REQSRC5. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC6 |Channel 6 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 6 + * | | |User can configure the peripheral setting by REQSRC6. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC7 |Channel 7 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 7 + * | | |User can configure the peripheral setting by REQSRC7. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL8_11 + * Offset: 0x488 PDMA Request Source Select Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC8 |Channel 8 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 8 + * | | |User can configure the peripheral setting by REQSRC8. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC9 |Channel 9 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 9 + * | | |User can configure the peripheral setting by REQSRC9. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC10 |Channel 10 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 10 + * | | |User can configure the peripheral setting by REQSRC10. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC11 |Channel 11 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 11 + * | | |User can configure the peripheral setting by REQSRC11. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL12_15 + * Offset: 0x48C PDMA Request Source Select Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC12 |Channel 12 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 12 + * | | |User can configure the peripheral setting by REQSRC12. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC13 |Channel 13 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 13 + * | | |User can configure the peripheral setting by REQSRC13. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC14 |Channel 14 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 14 + * | | |User can configure the peripheral setting by REQSRC14. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC15 |Channel 15 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 15 + * | | |User can configure the peripheral setting by REQSRC15. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + */ + DSCT_T DSCT[16]; + __I uint32_t CURSCAT[16]; /*!< [0x0100] Current Scatter-Gather Descriptor Table Address of PDMA Channel n */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[176]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ + __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ + __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ + __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ + __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ + __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ + __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ + __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ + __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ + __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ + __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ + __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */ + __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ + __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ + __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */ + __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch1 and Ch0 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */ + __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */ + __IO uint32_t REQSEL8_11; /*!< [0x0488] PDMA Request Source Select Register 2 */ + __IO uint32_t REQSEL12_15; /*!< [0x048c] PDMA Request Source Select Register 3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[28]; + /// @endcond //HIDDEN_SYMBOLS + STRIDE_T STRIDE[6]; +} PDMA_T; + +/** + @addtogroup PDMA_CONST PDMA Bit Field Definition + Constant Definitions for PDMA Controller +@{ */ + +#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */ +#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */ + +#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */ +#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */ + +#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */ +#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */ + +#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */ +#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */ + +#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */ +#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */ + +#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */ +#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */ + +#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */ +#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */ + +#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */ +#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */ + +#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */ +#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */ + +#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */ +#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */ + +#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */ +#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */ + +#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */ +#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */ + +#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */ +#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */ + +#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */ +#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */ + +#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ +#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ + +#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ +#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ + +#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ +#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ + +#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ +#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ + +#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ +#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ + +#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ +#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ + +#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ +#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ + +#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ +#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ + +#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ +#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ + +#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ +#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ + +#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ +#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ + +#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ +#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ + +#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ +#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ + +#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ +#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ + +#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ +#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ + +#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ +#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ + +#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ +#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ + +#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ +#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ + +#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ +#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ + +#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ +#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ + +#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ +#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ + +#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */ +#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */ + +#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */ +#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */ + +#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */ +#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */ + +#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */ +#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */ + +#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */ +#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */ + +#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */ +#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */ + +#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */ +#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */ + +#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */ +#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */ + +#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ +#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ + +#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ +#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ + +#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ +#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ + +#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ +#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ + +#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ +#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ + +#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ +#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ + +#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ +#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ + +#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ +#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ + +#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */ +#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */ + +#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */ +#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */ + +#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */ +#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */ + +#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */ +#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */ + +#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */ +#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */ + +#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */ +#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */ + +#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */ +#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */ + +#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */ +#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */ + +#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ +#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ + +#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ +#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ + +#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */ +#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */ + +#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */ +#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */ + +#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ +#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ + +#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ +#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ + +#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ +#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ + +#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */ +#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */ + +#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */ +#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */ + +#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ +#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ + +#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ +#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ + +#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ +#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ + +#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ +#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ + +#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ +#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ + +#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ +#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ + +#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ +#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ + +#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ +#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ + +#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ +#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ + +#define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */ +#define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */ + +#define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */ +#define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */ + +#define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */ +#define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */ + +#define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */ +#define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */ + +#define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA_T::REQSEL12_15: REQSRC12 Position */ +#define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC12 Mask */ + +#define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA_T::REQSEL12_15: REQSRC13 Position */ +#define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC13 Mask */ + +#define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA_T::REQSEL12_15: REQSRC14 Position */ +#define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC14 Mask */ + +#define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA_T::REQSEL12_15: REQSRC15 Position */ +#define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC15 Mask */ + +#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */ +#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */ + +#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */ +#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */ + +#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */ +#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */ + +/**@}*/ /* PDMA_CONST */ +/**@}*/ /* end of PDMA register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __PDMA_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qei_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qei_reg.h new file mode 100644 index 00000000000..94848093920 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qei_reg.h @@ -0,0 +1,314 @@ +/**************************************************************************//** + * @file qei_reg.h + * @version V1.00 + * @brief QEI register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QEI_REG_H__ +#define __QEI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup QEI Quadrature Encoder Interface(QEI) + Memory Mapped Structure for QEI Controller +@{ */ + +typedef struct +{ + + + /** + * @var QEI_T::CNT + * Offset: 0x00 QEI Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |Quadrature Encoder Interface Counter + * | | |A 32-bit up/down counter + * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF(QEI_STATUS[8]) is zero + * | | |This register performs an integrator which count value is proportional to the encoder position + * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs: + * | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0. + * | | |2. Compare-match event if QEIEN(QEI_CTL[29])=1 and QEI is in compare-counting mode. + * | | |3. Index signal change if QEIEN(QEI_CTL[29])=1 and IDXRLDEN (QEI_CTL[27])=1. + * @var QEI_T::CNTHOLD + * Offset: 0x04 QEI Counter Hold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold + * | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register. + * @var QEI_T::CNTLATCH + * Offset: 0x08 QEI Counter Index Latch Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch + * | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register. + * @var QEI_T::CNTCMP + * Offset: 0x0C QEI Counter Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare + * | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set + * | | |This register is software writable. + * @var QEI_T::CNTMAX + * Offset: 0x14 QEI Pre-set Maximum Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count + * | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode + * @var QEI_T::CTL + * Offset: 0x18 QEI Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock . + * | | |000 = QEI_CLK. + * | | |001 = QEI_CLK/2. + * | | |010 = QEI_CLK/4. + * | | |011 = QEI_CLK/16. + * | | |100 = QEI_CLK/32. + * | | |101 = QEI_CLK/64. + * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit + * | | |0 = The noise filter of QEI controller Enabled. + * | | |1 = The noise filter of QEI controller Disabled. + * |[4] |CHAEN |QEA Input to QEI Controller Enable Bit + * | | |0 = QEA input to QEI Controller Disabled. + * | | |1 = QEA input to QEI Controller Enabled. + * |[5] |CHBEN |QEB Input to QEI Controller Enable Bit + * | | |0 = QEB input to QEI Controller Disabled. + * | | |1 = QEB input to QEI Controller Enabled. + * |[6] |IDXEN |IDX Input to QEI Controller Enable Bit + * | | |0 = IDX input to QEI Controller Disabled. + * | | |1 = IDX input to QEI Controller Enabled. + * |[9:8] |MODE |QEI Counting Mode Selection + * | | |There are four quadrature encoder pulse counter operation modes. + * | | |00 = X4 Free-counting Mode. + * | | |01 = X2 Free-counting Mode. + * | | |10 = X4 Compare-counting Mode. + * | | |11 = X2 Compare-counting Mode. + * |[12] |CHAINV |Inverse QEA Input Polarity + * | | |0 = Not inverse QEA input polarity. + * | | |1 = QEA input polarity is inversed to QEI controller. + * |[13] |CHBINV |Inverse QEB Input Polarity + * | | |0 = Not inverse QEB input polarity. + * | | |1 = QEB input polarity is inversed to QEI controller. + * |[14] |IDXINV |Inverse IDX Input Polarity + * | | |0 = Not inverse IDX input polarity. + * | | |1 = IDX input polarity is inversed to QEI controller. + * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit + * | | |0 = OVUNF can trigger QEI controller interrupt Disabled. + * | | |1 = OVUNF can trigger QEI controller interrupt Enabled. + * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit + * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled. + * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled. + * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit + * | | |0 = CMPF can trigger QEI controller interrupt Disabled. + * | | |1 = CMPF can trigger QEI controller interrupt Enabled. + * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit + * | | |0 = The IDXF can trigger QEI interrupt Disabled. + * | | |1 = The IDXF can trigger QEI interrupt Enabled. + * |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0 + * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1. + * |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1 + * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1. + * |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2 + * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1. + * |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3 + * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1. + * |[24] |HOLDCNT |Hold QEI_CNT Control + * | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0]) + * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). + * | | |0 = No operation. + * | | |1 = QEI_CNT content is captured and stored in CNTHOLD(QEI_CNTHOLD[31:0]). + * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value. + * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit + * | | |If this bit is set to high, the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX. + * | | |0 = The index signal latch QEI counter function Disabled. + * | | |1 = The index signal latch QEI counter function Enabled. + * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit + * | | |When this bit is high and a rising edge comes on signal CHX, the CNT(QEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(QEI_STATUS[8]) = 1); while the CNT(QEI_CNT[31:0]) will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(QEI_STATUS[8]) = 0). + * | | |0 = Reload function Disabled. + * | | |1 = QEI_CNT re-initialized by Index signal Enabled. + * |[28] |CMPEN |The Compare Function Enable Bit + * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set. + * | | |0 = Compare function Disabled. + * | | |1 = Compare function Enabled. + * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit + * | | |0 = QEI controller function Disabled. + * | | |1 = QEI controller function Enabled. + * @var QEI_T::STATUS + * Offset: 0x2C QEI Controller Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IDXF |IDX Detected Flag + * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high. + * | | |0 = No rising edge detected on signal CHX. + * | | |1 = A rising edge occurs on signal CHX. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CMPF |Compare-match Flag + * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]). + * | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]). + * | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]). + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag + * | | |Flag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode + * | | |Similarly, the flag is set while QEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]). + * | | |0 = No overflow or underflow occurs in QEI counter. + * | | |1 = QEI counter occurs counting overflow or underflow. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[3] |DIRCHGF |Direction Change Flag + * | | |Flag is set by hardware while QEI counter counting direction is changed. + * | | |Software can clear this bit by writing 1 to it. + * | | |0 = No change in QEI counter counting direction. + * | | |1 = QEI counter counting direction is changed. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[8] |DIRF |QEI Counter Counting Direction Indication + * | | |0 = QEI Counter is in down-counting. + * | | |1 = QEI Counter is in up-counting. + * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB. + */ + __IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */ + __IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */ + __IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */ + __IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */ + __IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */ + +} QEI_T; + +/** + @addtogroup QEI_CONST QEI Bit Field Definition + Constant Definitions for QEI Controller +@{ */ + +#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */ +#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */ + +#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */ +#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */ + +#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */ +#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */ + +#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */ +#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */ + +#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */ +#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */ + +#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */ +#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */ + +#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */ +#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */ + +#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */ +#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */ + +#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */ +#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */ + +#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */ +#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */ + +#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */ +#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */ + +#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */ +#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */ + +#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */ +#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */ + +#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */ +#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */ + +#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */ +#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */ + +#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */ +#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */ + +#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */ +#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */ + +#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */ +#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */ + +#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */ +#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */ + +#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */ +#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */ + +#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */ +#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */ + +#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */ +#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */ + +#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */ +#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */ + +#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */ +#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */ + +#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */ +#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */ + +#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */ +#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */ + +#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */ +#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */ + +#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */ +#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */ + +#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */ +#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */ + +#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */ +#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */ + +#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */ +#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */ + +#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */ +#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */ + +/**@}*/ /* QEI_CONST */ +/**@}*/ /* end of QEI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __QEI_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qspi_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qspi_reg.h new file mode 100644 index 00000000000..1f78d51ddae --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/qspi_reg.h @@ -0,0 +1,591 @@ +/**************************************************************************//** + * @file qspi_reg.h + * @version V1.00 + * @brief QSPI register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QSPI_REG_H__ +#define __QSPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup QSPI Serial Peripheral Interface Controller(QSPI) + Memory Mapped Structure for QSPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var QSPI_T::CTL + * Offset: 0x00 QSPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |QSPIEN |QSPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the QSPIEN (QSPIx_CTL[0]) and confirm the QSPIENSTS (QSPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = QSPI bus clock is idle low. + * | | |1 = QSPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX). + * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer + * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = QSPI operates in full-duplex transfer. + * | | |1 = QSPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = 2-Bit Transfer mode Disabled. + * | | |1 = 2-Bit Transfer mode Enabled. + * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data + * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = QSPI unit transfer interrupt Disabled. + * | | |1 = QSPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = QSPI data is input direction. + * | | |1 = QSPI data is output direction. + * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = Dual I/O mode Disabled. + * | | |1 = Dual I/O mode Enabled. + * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = Quad I/O mode Disabled. + * | | |1 = Quad I/O mode Enabled. + * @var QSPI_T::CLKDIV + * Offset: 0x04 QSPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * @var QSPI_T::SSCTL + * Offset: 0x08 QSPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control (Master Only) + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the QSPIx_SS line to inactive state. + * | | |1 = set the QSPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the QSPIx_SS line at inactive state. + * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]). + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS). + * | | |0 = The slave selection signal QSPIx_SS is active low. + * | | |1 = The slave selection signal QSPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in QSPI0) + * | | |Slave 3-wire mode is only available in QSPI0 + * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in QSPI0) + * | | |0 = Slave mode time-out interrupt Disabled. + * | | |1 = Slave mode time-out interrupt Enabled. + * |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in QSPI0) + * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. + * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in QSPI0) + * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active + * | | |The clock source of the time-out counter is Slave peripheral clock + * | | |If the value is 0, it indicates the slave mode time-out function is disabled. + * @var QSPI_T::PDMACTL + * Offset: 0x0C QSPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0. + * @var QSPI_T::FIFOCTL + * Offset: 0x10 QSPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * @var QSPI_T::STATUS + * Offset: 0x14 QSPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = QSPI controller is in idle state. + * | | |1 = QSPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active. + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = QSPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status. + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in QSPI0) + * | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started + * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. + * | | |0 = Slave time-out is not active. + * | | |1 = Slave time-out is active. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |QSPIENSTS |QSPI Enable Status (Read Only) + * | | |0 = The QSPI controller is disabled. + * | | |1 = The QSPI controller is enabled. + * | | |Note: The QSPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var QSPI_T::TX + * Offset: 0x20 QSPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in SPI mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer. + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid + * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var QSPI_T::RX + * Offset: 0x30 QSPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |There are 4-level FIFO buffers in this controller + * | | |The data receive register holds the data received from QSPI data input pin + * | | |This is a read only register. + */ + __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */ + +} QSPI_T; + +/** + @addtogroup QSPI_CONST QSPI Bit Field Definition + Constant Definitions for QSPI Controller +@{ */ + +#define QSPI_CTL_QSPIEN_Pos (0) /*!< QSPI_T::CTL: QSPIEN Position */ +#define QSPI_CTL_QSPIEN_Msk (0x1ul << QSPI_CTL_QSPIEN_Pos) /*!< QSPI_T::CTL: QSPIEN Mask */ + +#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */ +#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */ + +#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */ +#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */ + +#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */ +#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */ + +#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */ +#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */ + +#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */ +#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */ + +#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */ +#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */ + +#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */ +#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */ + +#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */ +#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */ + +#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */ +#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */ + +#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */ +#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */ + +#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */ +#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */ + +#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */ +#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */ + +#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */ +#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */ + +#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */ +#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */ + +#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */ +#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */ + +#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */ +#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */ + +#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */ +#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */ + +#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */ +#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */ + +#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */ +#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */ + +#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */ +#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */ + +#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */ +#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */ + +#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */ +#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */ + +#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */ +#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */ + +#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */ +#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */ + +#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */ +#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */ + +#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */ +#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */ + +#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */ +#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */ + +#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */ +#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */ + +#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */ +#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */ + +#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */ +#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */ + +#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */ +#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */ + +#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */ +#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */ + +#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */ +#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */ + +#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */ +#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */ + +#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */ +#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */ + +#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */ +#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */ + +#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */ +#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */ + +#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */ +#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */ + +#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */ +#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */ + +#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */ +#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */ + +#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */ +#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */ + +#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */ +#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */ + +#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */ +#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */ + +#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */ +#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */ + +#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */ +#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */ + +#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */ +#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */ + +#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */ +#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */ + +#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */ +#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */ + +#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */ +#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */ + +#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */ +#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */ + +#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */ +#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */ + +#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */ +#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */ + +#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */ +#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */ + +#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */ +#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */ + +#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */ +#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */ + +#define QSPI_STATUS_QSPIENSTS_Pos (15) /*!< QSPI_T::STATUS: QSPIENSTS Position */ +#define QSPI_STATUS_QSPIENSTS_Msk (0x1ul << QSPI_STATUS_QSPIENSTS_Pos) /*!< QSPI_T::STATUS: QSPIENSTS Mask */ + +#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */ +#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */ + +#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */ +#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */ + +#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */ +#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */ + +#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */ +#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */ + +#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */ +#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */ + +#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */ +#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */ + +#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */ +#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */ + +#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */ +#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */ + +#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */ +#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */ + + +/**@}*/ /* QSPI_CONST */ +/**@}*/ /* end of QSPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __QSPI_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/rtc_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/rtc_reg.h new file mode 100644 index 00000000000..03f384dc6c2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/rtc_reg.h @@ -0,0 +1,1224 @@ +/**************************************************************************//** + * @file rtc_reg.h + * @version V1.00 + * @brief RTC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_REG_H__ +#define __RTC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup RTC Real Time Clock Controller(RTC) + Memory Mapped Structure for RTC Controller +@{ */ + +typedef struct +{ + + + /** + * @var RTC_T::INIT + * Offset: 0x00 RTC Initiation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) + * | | |0 = RTC is at reset state. + * | | |1 = RTC is at normal active state. + * |[31:1] |INIT |RTC Initiation (Write Only) + * | | |When RTC block is powered on, RTC is at reset state + * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leaving reset state + * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. + * | | |The INIT is a write-only field and read value will be always 0. + * @var RTC_T::RWEN + * Offset: 0x04 RTC Access Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16] |RWENF |RTC Register Access Enable Flag (Read Only) + * | | |0 = RTC register read/write Disabled. + * | | |1 = RTC register read/write Enabled. + * | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also. + * |[24] |RTCBUSY |RTC Write Busy Flag + * | | |This bit indicates RTC registers are writable or not. + * | | |0: RTC registers are writable. + * | | |1: RTC registers can't write, RTC under Busy Status. + * | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles. + * @var RTC_T::FREQADJ + * Offset: 0x08 RTC Frequency Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[21:0] |FREQADJ |Frequency Compensation Register + * | | |User must to get actual LXT frequency for RTC application. + * | | |FCR = 0x200000 * (32768 / LXT frequency). + * | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0. + * @var RTC_T::TIME + * Offset: 0x0C RTC Time Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit (0~5) + * |[11:8] |MIN |1-Min Time Digit (0~9) + * |[14:12] |TENMIN |10-Min Time Digit (0~5) + * |[19:16] |HR |1-Hour Time Digit (0~9) + * |[21:20] |TENHR |10-Hour Time Digit (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication + * | | |(If RTC_TIME[21] is 1, it indicates PM time message). + * @var RTC_T::CAL + * Offset: 0x10 RTC Calendar Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) + * |[11:8] |MON |1-Month Calendar Digit (0~9) + * |[12] |TENMON |10-Month Calendar Digit (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) + * @var RTC_T::CLKFMT + * Offset: 0x14 RTC Time Scale Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |24HEN |24-hour / 12-hour Time Scale Selection + * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale + * | | |0 = 12-hour time scale with AM and PM indication selected. + * | | |1 = 24-hour time scale selected. + * @var RTC_T::WEEKDAY + * Offset: 0x18 RTC Day of the Week Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |WEEKDAY |Day of the Week Register + * | | |000 = Sunday. + * | | |001 = Monday. + * | | |010 = Tuesday. + * | | |011 = Wednesday. + * | | |100 = Thursday. + * | | |101 = Friday. + * | | |110 = Saturday. + * | | |111 = Reserved. + * @var RTC_T::TALM + * Offset: 0x1C RTC Time Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) + * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) + * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication + * | | |(If RTC_TIME[21] is 1, it indicates PM time message). + * @var RTC_T::CALM + * Offset: 0x20 RTC Calendar Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) + * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) + * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::LEAPYEAR + * Offset: 0x24 RTC Leap Year Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only) + * | | |0 = This year is not a leap year. + * | | |1 = This year is leap year. + * @var RTC_T::INTEN + * Offset: 0x28 RTC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIEN |Alarm Interrupt Enable Bit + * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. + * | | |0 = RTC Alarm interrupt Disabled. + * | | |1 = RTC Alarm interrupt Enabled. + * |[1] |TICKIEN |Time Tick Interrupt Enable Bit + * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. + * | | |0 = RTC Time Tick interrupt Disabled. + * | | |1 = RTC Time Tick interrupt Enabled. + * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit + * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. + * | | |0 = Tamper 0 interrupt Disabled. + * | | |1 = Tamper 0 interrupt Enabled. + * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit + * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. + * | | |0 = Tamper 1 or Pair 0 interrupt Disabled. + * | | |1 = Tamper 1 or Pair 0 interrupt Enabled. + * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit + * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. + * | | |0 = Tamper 2 interrupt Disabled. + * | | |1 = Tamper 2 interrupt Enabled. + * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit + * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. + * | | |0 = Tamper 3 or Pair 1 interrupt Disabled. + * | | |1 = Tamper 3 or Pair 1 interrupt Enabled. + * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit + * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. + * | | |0 = Tamper 4 interrupt Disabled. + * | | |1 = Tamper 4 interrupt Enabled. + * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit + * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. + * | | |0 = Tamper 5 or Pair 2 interrupt Disabled. + * | | |1 = Tamper 5 or Pair 2 interrupt Enabled. + * @var RTC_T::INTSTS + * Offset: 0x2C RTC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIF |RTC Alarm Interrupt Flag + * | | |0 = Alarm condition is not matched. + * | | |1 = Alarm condition is matched. + * | | |Note: Write 1 to clear this bit. + * |[1] |TICKIF |RTC Time Tick Interrupt Flag + * | | |0 = Tick condition does not occur. + * | | |1 = Tick condition occur. + * | | |Note: Write 1 to clear this bit. + * |[8] |TAMP0IF |Tamper 0 Interrupt Flag + * | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). + * | | |0 = No Tamper 0 interrupt flag is generated. + * | | |1 = Tamper 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag + * | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) + * | | |or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated. + * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated. + * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[10] |TAMP2IF |Tamper 2 Interrupt Flag + * | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). + * | | |0 = No Tamper 2 interrupt flag is generated. + * | | |1 = Tamper 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag + * | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) + * | | |or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated + * | | |or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated. + * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated. + * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[12] |TAMP4IF |Tamper 4 Interrupt Flag + * | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]). + * | | |0 = No Tamper 4 interrupt flag is generated. + * | | |1 = Tamper 4 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag + * | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) + * | | |or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated + * | | |or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated. + * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated. + * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. + * @var RTC_T::TICK + * Offset: 0x30 RTC Time Tick Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TICK |Time Tick Register + * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. + * | | |000 = Time tick is 1 second. + * | | |001 = Time tick is 1/2 second. + * | | |010 = Time tick is 1/4 second. + * | | |011 = Time tick is 1/8 second. + * | | |100 = Time tick is 1/16 second. + * | | |101 = Time tick is 1/32 second. + * | | |110 = Time tick is 1/64 second. + * | | |111 = Time tick is 1/128 second. + * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. + * @var RTC_T::TAMSK + * Offset: 0x34 RTC Time Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) + * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) + * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) + * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) + * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) + * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) + * @var RTC_T::CAMSK + * Offset: 0x38 RTC Calendar Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) + * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) + * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) + * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) + * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) + * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::SPRCTL + * Offset: 0x3C RTC Spare Functional Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |SPRRWEN |Spare Register Enable Bit + * | | |0 = Spare register is Disabled. + * | | |1 = Spare register is Enabled. + * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. + * |[5] |SPRCSTS |SPR Clear Flag + * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected. + * | | |0 = Spare register content is not cleared. + * | | |1 = Spare register content is cleared. + * | | |Writes 1 to clear this bit. + * | | |Note: This bit keep 1 when RTC_INTSTS[13:8] not equal zero. + * @var RTC_T::SPR[20] + * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SPARE |Spare Register + * | | |This field is used to store back-up information defined by user. + * | | |This field will be cleared by hardware automatically once a tamper pin event is detected. + * | | |Before storing back-up information in to RTC_SPRx register, + * | | |user should check REWNF (RTC_RWEN[16]) is enabled. + * @var RTC_T::LXTCTL + * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:1] |GAIN |Oscillator Gain Option + * | | |User can select oscillator gain according to crystal external loading and operating temperature range + * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. + * | | |00 = L0 mode. + * | | |01 = L1 mode. + * | | |10 = L2 mode. + * | | |11 = L3 mode. + * @var RTC_T::GPIOCTL0 + * Offset: 0x104 RTC GPIO Control 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE0 |IO Operation Mode + * | | |00 = PF.4 is input only mode, without pull-up resistor. + * | | |01 = PF.4 is output push pull mode. + * | | |10 = PF.4 is open drain mode. + * | | |11 = PF.4 is quasi-bidirectional mode with internal pull up. + * |[2] |DOUT0 |IO Output Data + * | | |0 = PF.4 output low. + * | | |1 = PF.4 output high. + * |[3] |CTLSEL0 |IO Pin State Backup Selection + * | | |When low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function + * | | |User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.4 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off. + * | | |1 = PF.4 pin I/O function is controlled by VBAT power domain. + * | | |PF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1. + * | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable + * | | |Determine PF.4 I/O pull-up or pull-down. + * | | |00 = PF.4 pull-up and pull-up disable. + * | | |01 = PF.4 pull-down enable. + * | | |10 = PF.4 pull-up enable. + * | | |11 = PF.4 pull-up and pull-up disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode. + * |[9:8] |OPMODE1 |IO Operation Mode + * | | |00 = PF.5 is input only mode, without pull-up resistor. + * | | |01 = PF.5 is output push pull mode. + * | | |10 = PF.5 is open drain mode. + * | | |11 = PF.5 is quasi-bidirectional mode with internal pull up. + * |[10] |DOUT1 |IO Output Data + * | | |0 = PF.5 output low. + * | | |1 = PF.5 output high. + * |[11] |CTLSEL1 |IO Pin State Backup Selection + * | | |When low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function + * | | |User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.5 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off. + * | | |1 = PF.5 pin I/O function is controlled by VBAT power domain. + * | | |PF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1. + * | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable + * | | |Determine PF.5 I/O pull-up or pull-down. + * | | |00 = PF.5 pull-up and pull-up disable. + * | | |01 = PF.5 pull-down enable. + * | | |10 = PF.5 pull-up enable. + * | | |11 = PF.5 pull-up and pull-up disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode. + * |[17:16] |OPMODE2 |IO Operation Mode + * | | |00 = PF.6 is input only mode, without pull-up resistor. + * | | |01 = PF.6 is output push pull mode. + * | | |10 = PF.6 is open drain mode. + * | | |11 = PF.6 is quasi-bidirectional mode with internal pull up. + * |[18] |DOUT2 |IO Output Data + * | | |0 = PF.6 output low. + * | | |1 = PF.6 output high. + * |[19] |CTLSEL2 |IO Pin State Backup Selection + * | | |When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function + * | | |User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.6 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off. + * | | |1 = PF.6 pin I/O function is controlled by VBAT power domain. + * | | |PF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1. + * | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable + * | | |Determine PF.6 I/O pull-up or pull-down. + * | | |00 = PF.6 pull-up and pull-up disable. + * | | |01 = PF.6 pull-down enable. + * | | |10 = PF.6 pull-up enable. + * | | |11 = PF.6 pull-up and pull-up disable. + * | | |Note1: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode. + * |[25:24] |OPMODE3 |IO Operation Mode + * | | |00 = PF.7 is input only mode, without pull-up resistor. + * | | |01 = PF.7 is output push pull mode. + * | | |10 = PF.7 is open drain mode. + * | | |11 = PF.7 is quasi-bidirectional mode. + * |[26] |DOUT3 |IO Output Data + * | | |0 = PF.7 output low. + * | | |1 = PF.7 output high. + * |[27] |CTLSEL3 |IO Pin State Backup Selection + * | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function + * | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.7 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off. + * | | |1 = PF.7 pin I/O function is controlled by VBAT power domain. + * | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1. + * | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. + * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable + * | | |Determine PF.7 I/O pull-up or pull-down. + * | | |00 = PF.7 pull-up and pull-down disable. + * | | |01 = PF.7 pull-down enable. + * | | |10 = PF.7 pull-up enable. + * | | |11 = PF.7 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode. + * @var RTC_T::GPIOCTL1 + * Offset: 0x108 RTC GPIO Control 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE4 |IO Operation Mode + * | | |00 = PF.8 is input only mode, without pull-up resistor. + * | | |01 = PF.8 is output push pull mode. + * | | |10 = PF.8 is open drain mode. + * | | |11 = PF.8 is quasi-bidirectional mode. + * |[2] |DOUT4 |IO Output Data + * | | |0 = PF.8 output low. + * | | |1 = PF.8 output high. + * |[3] |CTLSEL4 |IO Pin State Backup Selection + * | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function + * | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.8 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off. + * | | |1 = PF.8 pin I/O function is controlled by VBAT power domain. + * | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1. + * | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. + * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable + * | | |Determine PF.8 I/O pull-up or pull-down. + * | | |00 = PF.8 pull-up and pull-down disable. + * | | |01 = PF.8 pull-down enable. + * | | |10 = PF.8 pull-up enable. + * | | |11 = PF.8 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode. + * |[9:8] |OPMODE5 |IO Operation Mode + * | | |00 = PF.9 is input only mode, without pull-up resistor. + * | | |01 = PF.9 is output push pull mode. + * | | |10 = PF.9 is open drain mode. + * | | |11 = PF.9 is quasi-bidirectional mode. + * |[10] |DOUT5 |IO Output Data + * | | |0 = PF.9 output low. + * | | |1 = PF.9 output high. + * |[11] |CTLSEL5 |IO Pin State Backup Selection + * | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function + * | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.9 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off. + * | | |1 = PF.9 pin I/O function is controlled by VBAT power domain. + * | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1. + * | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable + * | | |Determine PF.9 I/O pull-up or pull-down. + * | | |00 = PF.9 pull-up and pull-down disable. + * | | |01 = PF.9 pull-down enable. + * | | |10 = PF.9 pull-up enable. + * | | |11 = PF.9 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode. + * |[17:16] |OPMODE6 |IO Operation Mode + * | | |00 = PF.10 is input only mode, without pull-up resistor. + * | | |01 = PF.10 is output push pull mode. + * | | |10 = PF.10 is open drain mode. + * | | |11 = PF.10 is quasi-bidirectional mode. + * |[18] |DOUT6 |IO Output Data + * | | |0 = PF.10 output low. + * | | |1 = PF.10 output high. + * |[19] |CTLSEL6 |IO Pin State Backup Selection + * | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function + * | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.10 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off. + * | | |1 = PF.10 pin I/O function is controlled by VBAT power domain. + * | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1. + * | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable + * | | |Determine PF.10 I/O pull-up or pull-down. + * | | |00 = PF.10 pull-up and pull-down disable. + * | | |01 = PF.10 pull-down enable. + * | | |10 = PF.10 pull-up enable. + * | | |11 = PF.10 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode. + * |[25:24] |OPMODE7 |IO Operation Mode + * | | |00 = PF.11 is input only mode, without pull-up resistor. + * | | |01 = PF.11 is output push pull mode. + * | | |10 = PF.11 is open drain mode. + * | | |11 = PF.11 is quasi-bidirectional mode. + * |[26] |DOUT7 |IO Output Data + * | | |0 = PF.11 output low. + * | | |1 = PF.11 output high. + * |[27] |CTLSEL7 |IO Pin State Backup Selection + * | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function + * | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or + * | | |VBAT power domain RTC_GPIOCTL1 control register. + * | | |0 = PF.11 pin I/O function is controlled by GPIO module. + * | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off. + * | | |1 = PF.11 pin I/O function is controlled by VBAT power domain. + * | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1. + * | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. + * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable + * | | |Determine PF.11 I/O pull-up or pull-down. + * | | |00 = PF.11 pull-up and pull-down disable. + * | | |01 = PF.11 pull-down enable. + * | | |10 = PF.11 pull-up enable. + * | | |11 = PF.11 pull-up and pull-down disable. + * | | |Note: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode. + * @var RTC_T::DSTCTL + * Offset: 0x110 RTC Daylight Saving Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADDHR |Add 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. + * |[1] |SUBHR |Subtract 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. + * |[2] |DSBAK |Daylight Saving Back + * | | |0= Normal mode. + * | | |1= Daylight saving mode. + * @var RTC_T::TAMPCTL + * Offset: 0x120 RTC Tamper Pin Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select + * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set + * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select + * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 4. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set + * |[3:2] |DYNSRC |Dynamic Reference Pattern + * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode. + * | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out. + * | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. + * | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set. + * |[4] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |Setting this bit, the tamper configuration will be reload. + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * | | |Note: Before set this bit, the tamper configuration should be set to complete. + * |[7:5] |DYNRATE |Dynamic Change Rate + * | | |This item is choice the dynamic tamper output change rate. + * | | |000 = 210 * RTC_CLK. + * | | |001 = 211 * RTC_CLK. + * | | |010 = 212 * RTC_CLK. + * | | |011 = 213 * RTC_CLK. + * | | |100 = 214 * RTC_CLK. + * | | |101 = 215 * RTC_CLK. + * | | |110 = 216 * RTC_CLK. + * | | |111 = 217 * RTC_CLK. + * | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately. + * |[8] |TAMP0EN |Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[9] |TAMP0LV |Tamper 0 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit + * | | |0 = Tamper 0 de-bounce Disabled. + * | | |1 = Tamper 0 de-bounce Enabled. + * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[13] |TAMP1LV |Tamper 1 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit + * | | |0 = Tamper 1 de-bounce Disabled. + * | | |1 = Tamper 1 de-bounce Enabled. + * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[17] |TAMP2LV |Tamper 2 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit + * | | |0 = Tamper 2 de-bounce Disabled. + * | | |1 = Tamper 2 de-bounce Enabled. + * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[21] |TAMP3LV |Tamper 3 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit + * | | |0 = Tamper 3 de-bounce Disabled. + * | | |1 = Tamper 3 de-bounce Enabled. + * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[24] |TAMP4EN |Tamper4 Detect Enable Bit + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[25] |TAMP4LV |Tamper 4 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit + * | | |0 = Tamper 4 de-bounce Disabled. + * | | |1 = Tamper 4 de-bounce Enabled. + * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. + * |[29] |TAMP5LV |Tamper 5 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit + * | | |0 = Tamper 5 de-bounce Disabled. + * | | |1 = Tamper 5 de-bounce Enabled. + * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * @var RTC_T::TAMPSEED + * Offset: 0x128 RTC Tamper Dynamic Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed Value + * @var RTC_T::TAMPTIME + * Offset: 0x130 RTC Tamper Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) + * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) + * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) + * | | |Note: 24-hour time scale only. + * @var RTC_T::TAMPCAL + * Offset: 0x134 RTC Tamper Calendar Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) + * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) + * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) + */ + __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ + __IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */ + __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ + __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ + __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ + __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ + __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ + __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ + __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ + __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ + __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ + __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ + __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ + __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ + __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ + __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008c] RTC Spare Register 0 ~ 19 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[28]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ + __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ + __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ + __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ + +} RTC_T; + +/** + @addtogroup RTC_CONST RTC Bit Field Definition + Constant Definitions for RTC Controller +@{ */ + +#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: INIT_ACTIVE Position */ +#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: INIT_ACTIVE Mask */ + +#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ +#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ + +#define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */ +#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */ + +#define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */ +#define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */ + +#define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */ +#define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */ + +#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ +#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ + +#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ +#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ + +#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ +#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ + +#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ +#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ + +#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ +#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ + +#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ +#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ + +#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ +#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ + +#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ +#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ + +#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ +#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ + +#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ +#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ + +#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ +#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ + +#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ +#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ + +#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ +#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ + +#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ +#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ + +#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ +#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ + +#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ +#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ + +#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ +#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ + +#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ +#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ + +#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ +#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ + +#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ +#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ + +#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ +#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ + +#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ +#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ + +#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ +#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ + +#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ +#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ + +#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ +#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ + +#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ +#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ + +#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ +#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ + +#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ +#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ + +#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ +#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ + +#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ +#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ + +#define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ +#define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ + +#define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ +#define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ + +#define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */ +#define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */ + +#define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */ +#define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */ + +#define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */ +#define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */ + +#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ +#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ + +#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ +#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ + +#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ +#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ + +#define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ +#define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ + +#define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ +#define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ + +#define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */ +#define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */ + +#define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */ +#define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */ + +#define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */ +#define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */ + +#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ +#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ + +#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ +#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ + +#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ +#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ + +#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ +#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ + +#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ +#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ + +#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ +#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ + +#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ +#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ + +#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ +#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ + +#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ +#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ + +#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ +#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ + +#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ +#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ + +#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ +#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ + +#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ +#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ + +#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ +#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ + +#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ +#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ + +#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ +#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ + +#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ +#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ + +#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ +#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ + +#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ +#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ + +#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ +#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ + +#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */ +#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */ + +#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */ +#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */ + +#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */ +#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */ + +#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */ +#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */ + +#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */ +#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */ + +#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */ +#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */ + +#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */ +#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */ + +#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */ +#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */ + +#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */ +#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */ + +#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */ +#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */ + +#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */ +#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */ + +#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */ +#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */ + +#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */ +#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */ + +#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */ +#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */ + +#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */ +#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */ + +#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ +#define RTC_LXTCTL_GAIN_Msk (0x3ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ + +#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ +#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ + +#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ +#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ + +#define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */ +#define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */ + +#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ +#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ + +#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ +#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ + +#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ +#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ + +#define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */ +#define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */ + +#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ +#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ + +#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ +#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ + +#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ +#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ + +#define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */ +#define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */ + +#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ +#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ + +#define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ +#define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ + +#define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ +#define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ + +#define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */ +#define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */ + +#define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ +#define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ + +#define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ +#define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ + +#define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ +#define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ + +#define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */ +#define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */ + +#define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ +#define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ + +#define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ +#define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ + +#define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ +#define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ + +#define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */ +#define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */ + +#define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ +#define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ + +#define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ +#define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ + +#define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ +#define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ + +#define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */ +#define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */ + +#define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ +#define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ + +#define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ +#define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ + +#define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ +#define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ + +#define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */ +#define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */ + +#define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ +#define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ + +#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ +#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ + +#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ +#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ + +#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ +#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ + +#define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */ +#define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */ + +#define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */ +#define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */ + +#define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */ +#define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */ + +#define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */ +#define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */ + +#define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */ +#define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */ + +#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ +#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ + +#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ +#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ + +#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ +#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ + +#define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ +#define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ + +#define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ +#define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ + +#define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ +#define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */ +#define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */ + +#define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ +#define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ + +#define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ +#define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ + +#define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ +#define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ + +#define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */ +#define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */ + +#define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */ +#define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */ + +#define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */ +#define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */ +#define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */ + +#define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */ +#define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */ + +#define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */ +#define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */ + +#define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */ +#define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */ + +#define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */ +#define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */ + +#define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */ +#define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */ + +#define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */ +#define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */ +#define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */ + +#define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */ +#define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */ + +#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ +#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ + +#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ +#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ + +#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ +#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ + +#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ +#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ + +#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ +#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ + +#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ +#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ + +#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ +#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ + +#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ +#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ + +#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ +#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ + +#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ +#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ + +#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ +#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ + +#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ +#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ + + +/**@}*/ /* RTC_CONST */ +/**@}*/ /* end of RTC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __RTC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sc_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sc_reg.h new file mode 100644 index 00000000000..1d1f0eb5223 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sc_reg.h @@ -0,0 +1,1018 @@ +/**************************************************************************//** + * @file sc_reg.h + * @version V1.00 + * @brief SC register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_REG_H__ +#define __SC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SC Smart Card Host Interface Controller(SC) + Memory Mapped Structure for SC Controller +@{ */ + +typedef struct +{ + + + /** + * @var SC_T::DAT + * Offset: 0x00 SC Receive/Transmit Holding Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Receive/Transmit Holding Buffer + * | | |Write Operation: + * | | |By writing data to DAT, the SC will send out an 8-bit data. + * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. + * | | |Read Operation: + * | | |By reading DAT, the SC will return an 8-bit received data. + * @var SC_T::CTL + * Offset: 0x04 SC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SCEN |SC Controller Enable Bit + * | | |Set this bit to 1 to enable SC operation. If this bit is cleared, + * | | |0 = SC will force all transition to IDLE state. + * | | |1 = SC controller is enabled and all function can work correctly. + * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. + * |[1] |RXOFF |RX Transition Disable Control Bit + * | | |This bit is used for disable Rx transition function. + * | | |0 = The receiver Enabled. + * | | |1 = The receiver Disabled. + * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[2] |TXOFF |TX Transition Disable Control Bit + * | | |This bit is used for disable Tx transition function. + * | | |0 = The transceiver Enabled. + * | | |1 = The transceiver Disabled. + * |[3] |AUTOCEN |Auto Convention Enable Bit + * | | |This bit is used for enable auto convention function. + * | | |0 = Auto-convention Disabled. + * | | |1 = Auto-convention Enabled. + * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) + * | | |state and the first data must be 0x3B or 0x3F. + * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and + * | | |change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. + * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 + * | | |automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. + * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an + * | | |interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. + * |[5:4] |CONSEL |Convention Selection + * | | |00 = Direct convention. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Inverse convention. + * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[7:6] |RXTRGLV |Rx Buffer Trigger Level + * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set + * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. + * | | |00 = Rx Buffer Trigger Level with 01 bytes. + * | | |01 = Rx Buffer Trigger Level with 02 bytes. + * | | |10 = Rx Buffer Trigger Level with 03 bytes. + * | | |11 = Reserved. + * |[12:8] |BGT |Block Guard Time (BGT) + * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters + * | | |between different transfer directions + * | | |This field indicates the counter for the bit length of block guard time + * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this + * | | |field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. + * | | |Note: The real block guard time is BGT + 1. + * |[14:13] |TMRSEL |Timer Channel Selection + * | | |00 = All internal timer function Disabled. + * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled + * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. + * | | |Other configurations are reserved + * |[15] |NSB |Stop Bit Length + * | | |This field indicates the length of stop bit. + * | | |0 = The stop bit length is 2 ETU. + * | | |1= The stop bit length is 1 ETU. + * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. + * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. + * |[18:16] |RXRTY |RX Error Retry Count Number + * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred. + * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when RXRTYEN enabled + * | | |The change flow is to disable RXRTYEN first and then fill in new retry value. + * |[19] |RXRTYEN |RX Error Retry Enable Bit + * | | |This bit enables receiver retry function when parity error has occurred. + * | | |0 = RX error retry function Disabled. + * | | |1 = RX error retry function Enabled. + * | | |Note: User must fill in the RXRTY value before enabling this bit. + * |[22:20] |TXRTY |TX Error Retry Count Number + * | | |This field indicates the maximum number of transmitter retries that are allowed when parity + * | | |error has occurred. + * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when TXRTYEN enabled + * | | |The change flow is to disable TXRTYEN first and then fill in new retry value. + * |[23] |TXRTYEN |TX Error Retry Enable Bit + * | | |This bit enables transmitter retry function when parity error has occurred. + * | | |0 = TX error retry function Disabled. + * | | |1 = TX error retry function Enabled. + * |[25:24] |CDDBSEL |Card Detect De-bounce Selection + * | | |This field indicates the card detect de-bounce selection. + * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce + * | | |sample card removal once per 128 SC module clocks. + * | | |Other configurations are reserved. + * |[26] |CDLV |Card Detect Level Selection + * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. + * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. + * | | |Note: User must select card detect level before Smart Card controller enabled. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. + * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. + * | | |1 = Last value is synchronizing. + * @var SC_T::ALTCTL + * Offset: 0x08 SC Alternate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXRST |TX Software Reset + * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[1] |RXRST |Rx Software Reset + * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the Rx internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by deactivation sequence. + * | | |0 = No effect. + * | | |1 = Deactivation sequence generator Enabled. + * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and + * | | |the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[3] |ACTEN |Activation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by activation sequence. + * | | |0 = No effect. + * | | |1 = Activation sequence generator Enabled. + * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the + * | | |INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data + * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. + * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by warm reset sequence. + * | | |0 = No effect. + * | | |1 = Warm reset sequence generator Enabled. + * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the + * | | |INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data + * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform + * | | |warm reset sequence. + * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit + * | | |This bit enables Timer 0 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit + * | | |This bit enables Timer 1 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only + * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit + * | | |This bit enables Timer 2 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only + * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[9:8] |INITSEL |Initial Timing Selection + * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation. + * | | |The unit of initial timing is SC module clock. + * | | |Activation: refer to SC Activation Sequence in Figure 7.17-54. + * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 7.17-5. + * | | |Deactivation: refer to Deactivation Sequence in Figure 7.17-56. + * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation + * | | |at most 128 SC module clock cycles. + * |[11] |ADACEN |Auto Deactivation When Card Removal + * | | |This bit is used for enable hardware auto deactivation when smart card is removed. + * | | |0 = Auto deactivation Disabled. + * | | |1 = Auto deactivation Enabled. + * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence + * | | |if this bit is set + * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. + * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit + * | | |This bit enables the receiver block guard time function. + * | | |0 = Receiver block guard time function Disabled. + * | | |1 = Receiver block guard time function Enabled. + * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer0. + * | | |0 = Timer0 is not active. + * | | |1 = Timer0 is active. + * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). + * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer1. + * | | |0 = Timer1 is not active. + * | | |1 = Timer1 is active. + * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). + * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer2. + * | | |0 = Timer2 is not active. + * | | |1 = Timer2 is active. + * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::EGT + * Offset: 0x0C SC Extra Guard Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EGT |Extra Guard Time + * | | |This field indicates the extra guard time value. + * | | |Note: The extra guard time unit is ETU base. + * @var SC_T::RXTOUT + * Offset: 0x10 SC Receive Buffer Time-out Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter + * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data + * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by + * | | |reading SCn_DAT, a receiver time-out flag RBTOIF (SCn_INTSTS[9]) will be set, and hardware will + * | | |generate an interrupt to CPU when RBTOIEN (SCn_INTEN[9]) is enabled. + * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. + * | | |Note2: Filling in all 0 to this field indicates to disable this function. + * @var SC_T::ETUCTL + * Offset: 0x14 SC Element Time Unit Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ETURDIV |ETU Rate Divider + * | | |The field is used for ETU clock rate divider. + * | | |The real ETU is ETURDIV + 1. + * | | |Note: User can configure this field, but this field must be greater than 0x04. + * @var SC_T::INTEN + * Offset: 0x18 SC Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit + * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. + * | | |0 = Receive data reach trigger level interrupt Disabled. + * | | |1 = Receive data reach trigger level interrupt Enabled. + * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit + * | | |This field is used to enable transmit buffer empty interrupt. + * | | |0 = Transmit buffer empty interrupt Disabled. + * | | |1 = Transmit buffer empty interrupt Enabled. + * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit + * | | |This field is used to enable transfer error interrupt + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error + * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive + * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), + * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error + * | | |TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt Disabled. + * | | |1 = Transfer error interrupt Enabled. + * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit + * | | |This field is used to enable Timer0 interrupt function. + * | | |0 = Timer0 interrupt Disabled. + * | | |1 = Timer0 interrupt Enabled. + * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit + * | | |This field is used to enable the Timer1 interrupt function. + * | | |0 = Timer1 interrupt Disabled. + * | | |1 = Timer1 interrupt Enabled. + * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit + * | | |This field is used to enable Timer2 interrupt function. + * | | |0 = Timer2 interrupt Disabled. + * | | |1 = Timer2 interrupt Enabled. + * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit + * | | |This field is used to enable block guard time interrupt in receive direction. + * | | |0 = Block guard time interrupt Disabled. + * | | |1 = Block guard time interrupt Enabled. + * | | |Note: This bit is valid only for receive direction block guard time. + * |[7] |CDIEN |Card Detect Interrupt Enable Bit + * | | |This field is used to enable card detect interrupt + * | | |The card detect status is CDPINSTS (SCn_STATUS[13]). + * | | |0 = Card detect interrupt Disabled. + * | | |1 = Card detect interrupt Enabled. + * |[8] |INITIEN |Initial End Interrupt Enable Bit + * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation + * | | |(DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. + * | | |0 = Initial end interrupt Disabled. + * | | |1 = Initial end interrupt Enabled. + * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit + * | | |This field is used to enable receiver buffer time-out interrupt. + * | | |0 = Receiver buffer time-out interrupt Disabled. + * | | |1 = Receiver buffer time-out interrupt Enabled. + * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit + * | | |This field is used to enable auto-convention error interrupt. + * | | |0 = Auto-convention error interrupt Disabled. + * | | |1 = Auto-convention error interrupt Enabled. + * @var SC_T::INTSTS + * Offset: 0x1C SC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only) + * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. + * | | |0 = Number of receive buffer is less than RXTRGLV setting. + * | | |1 = Number of receive buffer data equals the RXTRGLV setting. + * | | |Note: This bit is read only + * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, + * | | |this bit will be cleared automatically. + * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only) + * | | |This field is used for transmit buffer empty interrupt status flag. + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * | | |Note: This bit is read only + * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit + * | | |will be cleared automatically. + * |[2] |TERRIF |Transfer Error Interrupt Status Flag + * | | |This field is used for transfer error interrupt status flag + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error + * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive + * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), + * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error + * | | |TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt did not occur. + * | | |1 = Transfer error interrupt occurred. + * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[3] |TMR0IF |Timer0 Interrupt Status Flag + * | | |This field is used for Timer0 interrupt status flag. + * | | |0 = Timer0 interrupt did not occur. + * | | |1 = Timer0 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[4] |TMR1IF |Timer1 Interrupt Status Flag + * | | |This field is used for Timer1 interrupt status flag. + * | | |0 = Timer1 interrupt did not occur. + * | | |1 = Timer1 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[5] |TMR2IF |Timer2 Interrupt Status Flag + * | | |This field is used for Timer2 interrupt status flag. + * | | |0 = Timer2 interrupt did not occur. + * | | |1 = Timer2 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[6] |BGTIF |Block Guard Time Interrupt Status Flag + * | | |This field is used for indicate block guard time interrupt status flag in receive direction. + * | | |0 = Block guard time interrupt did not occur. + * | | |1 = Block guard time interrupt occurred. + * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only) + * | | |This field is used for card detect interrupt status flag + * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). + * | | |0 = Card detect event did not occur. + * | | |1 = Card detect event occurred. + * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. + * |[8] |INITIF |Initial End Interrupt Status Flag + * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) + * | | |and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. + * | | |0 = Initial sequence is not complete. + * | | |1 = Initial sequence is completed. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only) + * | | |This field is used for indicate receive buffer time-out interrupt status flag. + * | | |0 = Receive buffer time-out interrupt did not occur. + * | | |1 = Receive buffer time-out interrupt occurred. + * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT + * | | |register to clear it. + * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag + * | | |This field indicates auto convention sequence error. + * | | |0 = Received TS at ATR state is 0x3B or 0x3F. + * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F. + * | | |Note: This bit can be cleared by writing 1 to it. + * @var SC_T::STATUS + * Offset: 0x20 SC Transfer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOV |Receive Overflow Error Status Flag + * | | |This bit is set when Rx buffer overflow. + * | | |0 = Rx buffer is not overflow. + * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only) + * | | |This bit indicates Rx buffer empty or not. + * | | |0 = Rx buffer is not empty. + * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. + * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only) + * | | |This bit indicates Rx buffer full or not. + * | | |0 = Rx buffer count is less than 4. + * | | |1 = Rx buffer count equals to 4. + * |[4] |PEF |Receiver Parity Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. + * | | |0 = Receiver parity error flag did not occur. + * | | |1 = Receiver parity error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not + * | | |set this flag. + * |[5] |FEF |Receiver Frame Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, + * | | |the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = Receiver frame error flag did not occur. + * | | |1 = Receiver frame error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not + * | | |set this flag. + * |[6] |BEF |Receiver Break Error Status Flag + * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state + * | | |(logic 0) is longer than a full word transmission time (that is, the total time of start bit + + * | | |data bits + parity bit + stop bit). + * | | |0 = Receiver break error flag did not occur. + * | | |1 = Receiver break error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set + * | | |this flag. + * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag + * | | |This bit is set when Tx buffer overflow. + * | | |0 = Tx buffer is not overflow. + * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only) + * | | |This bit indicates TX buffer empty or not. + * | | |0 = Tx buffer is not empty. + * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter + * | | |Shift Register. + * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). + * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only) + * | | |This bit indicates Tx buffer full or not. + * | | |0 = Tx buffer count is less than 4. + * | | |1 = Tx buffer count equals to 4. + * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin + * | | |This bit is set whenever card has been removal. + * | | |0 = No effect. + * | | |1 = Card removed. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. + * |[12] |CINSERT |Card Insert Status of SCn_CD Pin + * | | |This bit is set whenever card has been inserted. + * | | |0 = No effect. + * | | |1 = Card insert. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. + * |[13] |CDPINSTS |Card Detect Pin Status (Read Only) + * | | |This bit is the pin status of SCn_CD. + * | | |0 = The SCn_CD pin state at low. + * | | |1 = The SCn_CD pin state at high. + * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only) + * | | |This field indicates the Rx buffer pointer status + * | | |When SC controller receives one byte from external device, RXPOINT increases one + * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one. + * |[21] |RXRERR |Receiver Retry Error + * | | |This bit is used for receiver error retry and set by hardware. + * | | |0 = No Rx retry transfer. + * | | |1 = Rx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. + * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), + * | | |hardware will not set this flag. + * |[22] |RXOVERR |Receiver over Retry Error + * | | |This bit is used for receiver retry counts over than retry number limitation. + * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware + * | | |will not set this flag. + * |[23] |RXACT |Receiver in Active Status Flag (Read Only) + * | | |This bit indicates Rx transfer status. + * | | |0 = This bit is cleared automatically when Rx transfer is finished. + * | | |1 = This bit is set by hardware when Rx transfer is in active. + * | | |Note: This bit is read only. + * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only) + * | | |This field indicates the Tx buffer pointer status + * | | |When CPU writes data into SCn_DAT, TXPOINT increases one + * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. + * |[29] |TXRERR |Transmitter Retry Error + * | | |This bit is used for indicate transmitter error retry and set by hardware. + * | | |0 = No Tx retry transfer. + * | | |1 = Tx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU. + * |[30] |TXOVERR |Transmitter over Retry Error + * | | |This bit is used for transmitter retry counts over than retry number limitation. + * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[31] |TXACT |Transmit in Active Status Flag (Read Only) + * | | |This bit indicates Tx transmit status. + * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission + * | | |has completed. + * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP + * | | |bit of the last byte has not been transmitted. + * | | |Note: This bit is read only. + * @var SC_T::PINCTL + * Offset: 0x24 SC Pin Control State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWREN |SCn_PWR Pin Signal + * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. + * | | |Write this field to drive SCn_PWR pin + * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. + * | | |Read this field to get SCn_PWR signal status. + * | | |0 = SCn_PWR signal status is low. + * | | |1 = SCn_PWR signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[1] |RSTEN |SCn_RST Pin Signal + * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. + * | | |Write this field to drive SCn_RST pin. + * | | |0 = Drive SCn_RST pin to low. + * | | |1 = Drive SCn_RST pin to high. + * | | |Read this field to get SCn_RST signal status. + * | | |0 = SCn_RST signal status is low. + * | | |1 = SCn_RST signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[6] |CLKKEEP |SC Clock Enable Bit + * | | |0 = SC clock generation Disabled. + * | | |1 = SC clock always keeps free running. + * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[9] |SCDATA |SCn_DATA Pin Signal + * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. + * | | |0 = Drive SCn_DATA pin to low. + * | | |1 = Drive SCn_DATA pin to high. + * | | |Read this field to get SCn_DATA signal status. + * | | |0 = SCn_DATA signal status is low. + * | | |1 = SCn_DATA signal status is high. + * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when SC is in these modes. + * |[11] |PWRINV |SCn_PWR Pin Inverse + * | | |This bit is used for inverse the SCn_PWR pin. + * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). + * | | |PWRINV is 0 and PWREN is 0, SCn_PWR pin is 0. + * | | |PWRINV is 0 and PWREN is 1, SCn_PWR pin is 1. + * | | |PWRINV is 1 and PWREN is 0, SCn_PWR pin is 1. + * | | |PWRINV is 1 and PWREN is 1, SCn_PWR pin is 0. + * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). + * |[16] |DATASTS |SCn_DATA Pin Status (Read Only) + * | | |This bit is the pin status of SCn_DATA. + * | | |0 = The SCn_DATA pin status is low. + * | | |1 = The SCn_DATA pin status is high. + * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only) + * | | |This bit is the pin status of SCn_PWR. + * | | |0 = SCn_PWR pin to low. + * | | |1 = SCn_PWR pin to high. + * |[18] |RSTSTS |SCn_RST Pin Status (Read Only) + * | | |This bit is the pin status of SCn_RST. + * | | |0 = SCn_RST pin is low. + * | | |1 = SCn_RST pin is high. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL0 + * Offset: 0x28 SC Internal Timer0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer0 Counter Value + * | | |This field indicates the internal Timer0 counter values. + * | | |Note: Unit of Timer0 counter is ETU base. + * |[27:24] |OPMODE |Timer0 Operation Mode Selection + * | | |This field indicates the internal 24-bit Timer0 operation selection. + * | | |Refer to Table 7.17-3 for programming Timer0. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL1 + * Offset: 0x2C SC Internal Timer1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 1 Counter Value + * | | |This field indicates the internal Timer1 counter values. + * | | |Note: Unit of Timer1 counter is ETU base. + * |[27:24] |OPMODE |Timer 1 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer1 operation selection. + * | | |Refer to Table 7.17-3 for programming Timer1. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL2 + * Offset: 0x30 SC Internal Timer2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 2 Counter Value + * | | |This field indicates the internal Timer2 counter values. + * | | |Note: Unit of Timer2 counter is ETU base. + * |[27:24] |OPMODE |Timer 2 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer2 operation selection + * | | |Refer to Table 7.17-3 for programming Timer2. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::UARTCTL + * Offset: 0x34 SC UART Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |UARTEN |UART Mode Enable Bit + * | | |Sets this bit to enable UART mode function. + * | | |0 = Smart Card mode. + * | | |1 = UART mode. + * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. + * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. + * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. + * |[5:4] |WLS |Word Length Selection + * | | |This field is used for select UART data length. + * | | |00 = Word length is 8 bits. + * | | |01 = Word length is 7 bits. + * | | |10 = Word length is 6 bits. + * | | |11 = Word length is 5 bits. + * | | |Note: In smart card mode, this WLS must be '00'. + * |[6] |PBOFF |Parity Bit Disable Control + * | | |Sets this bit is used for disable parity check function. + * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. + * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. + * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit). + * |[7] |OPE |Odd Parity Enable Bit + * | | |This is used for odd/even parity selection. + * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |Note: This bit has effect only when PBOFF bit is '0'. + * @var SC_T::ACTCTL + * Offset: 0x4C SC Activation Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation + * | | |This field provide the configurable cycles to extend the activation time T1 period. + * | | |The cycle scaling factor is 2048. + * | | |Extend cycles = (filled value * 2048) cycles. + * | | |Refer to SC activation sequence in Figure 7.17-4. + * | | |For example, + * | | |SCLK = 4MHz, each cycle = 0.25us,. + * | | |Filled 20 to this field + * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms. + * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 + */ + __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */ + __IO uint32_t CTL; /*!< [0x0004] SC Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */ + __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */ + __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */ + __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */ + __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */ + __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */ + __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */ + __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */ + __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */ + __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */ + __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[5]; + /** @endcond */ + __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */ + +} SC_T; + +/** + @addtogroup SC_CONST SC Bit Field Definition + Constant Definitions for SC Controller +@{ */ + +#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */ +#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */ + +#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */ +#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */ + +#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */ +#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */ + +#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */ +#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */ + +#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */ +#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */ + +#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */ +#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */ + +#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */ +#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */ + +#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */ +#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ + +#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */ +#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */ + +#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */ +#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */ + +#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */ +#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */ + +#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */ +#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */ + +#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */ +#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */ + +#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */ +#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */ + +#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */ +#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */ + +#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */ +#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */ + +#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */ +#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ + +#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */ +#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */ + +#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */ +#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */ + +#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */ +#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */ + +#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */ +#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */ + +#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */ +#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */ + +#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */ +#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */ + +#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */ +#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */ + +#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */ +#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */ + +#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */ +#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */ + +#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */ +#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */ + +#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */ +#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */ + +#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */ +#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */ + +#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */ +#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */ + +#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */ +#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */ + +#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */ +#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */ + +#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */ +#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */ + +#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */ +#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */ + +#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */ +#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */ + +#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */ +#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */ + +#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */ +#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */ + +#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */ +#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */ + +#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */ +#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */ + +#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */ +#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */ + +#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */ +#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */ + +#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */ +#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */ + +#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */ +#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */ + +#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */ +#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */ + +#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */ +#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */ + +#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */ +#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */ + +#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */ +#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */ + +#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */ +#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */ + +#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */ +#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */ + +#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */ +#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */ + +#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */ +#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */ + +#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */ +#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */ + +#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */ +#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */ + +#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */ +#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */ + +#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */ +#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */ + +#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */ +#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */ + +#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */ +#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */ + +#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */ +#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */ + +#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */ +#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */ + +#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */ +#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */ + +#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */ +#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */ + +#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */ +#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */ + +#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */ +#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */ + +#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */ +#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */ + +#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */ +#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */ + +#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */ +#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */ + +#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */ +#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */ + +#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */ +#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */ + +#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */ +#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */ + +#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */ +#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */ + +#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */ +#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */ + +#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */ +#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */ + +#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */ +#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */ + +#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */ +#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */ + +#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */ +#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */ + +#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */ +#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */ + +#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */ +#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */ + +#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */ +#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */ + +#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */ +#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */ + +#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */ +#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */ + +#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */ +#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */ + +#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */ +#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */ + +#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */ +#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */ + +#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */ +#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */ + +#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */ +#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */ + +#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */ +#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */ + +#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */ +#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */ + +#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */ +#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */ + +#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */ +#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */ + +#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */ +#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */ + +#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */ +#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */ + +#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */ +#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */ + +#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */ +#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */ + +#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */ +#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */ + +#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */ +#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */ + +#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */ +#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */ + +#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */ +#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */ + +#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */ +#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */ + +#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */ +#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */ + +#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */ +#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */ + +/**@}*/ /* SC_CONST */ +/**@}*/ /* end of SC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SC_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sdh_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sdh_reg.h new file mode 100644 index 00000000000..ed227220c49 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sdh_reg.h @@ -0,0 +1,540 @@ +/**************************************************************************//** + * @file sdh_reg.h + * @version V1.00 + * @brief SDH register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SDH_REG_H__ +#define __SDH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SDH SD Card Host Interface(SDH) + Memory Mapped Structure for SDH Controller +@{ */ + +typedef struct +{ + + /** + * @var SDH_T::FB + * Offset: 0x00~0x7C Shared Buffer (FIFO) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |BUFFER |Shared Buffer + * | | |Buffer for DMA transfer + * @var SDH_T::DMACTL + * Offset: 0x400 DMA Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DMAEN |DMA Engine Enable Bit + * | | |0 = DMA Disabled. + * | | |1 = DMA Enabled. + * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. + * | | |Note: If target abort is occurred, DMAEN will be cleared. + * |[1] |DMARST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset internal state machine and pointers + * | | |The contents of control register will not be cleared + * | | |This bit will auto be cleared after few clock cycles. + * | | |Note: The software reset DMA related registers. + * |[3] |SGEN |Scatter-gather Function Enable Bit + * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory). + * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table + * | | |The format of these Pads' will be described later). + * |[9] |DMABUSY |DMA Transfer Is in Progress + * | | |This bit indicates if SD Host is granted and doing DMA transfer or not. + * | | |0 = DMA transfer is not in progress. + * | | |1 = DMA transfer is in progress. + * @var SDH_T::DMASA + * Offset: 0x408 DMA Transfer Starting Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order + * | | |0 = PAD table is fetched in order. + * | | |1 = PAD table is fetched out of order. + * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1. + * |[31:1] |DMASA |DMA Transfer Starting Address + * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. + * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. + * | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004. + * @var SDH_T::DMABCNT + * Offset: 0x40C DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[25:0] |BCNT |DMA Transfer Byte Count (Read Only) + * | | |This field indicates the remained byte count of DMA transfer + * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0. + * @var SDH_T::DMAINTEN + * Offset: 0x410 DMA Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit + * | | |0 = Target abort interrupt generation Disabled during DMA transfer. + * | | |1 = Target abort interrupt generation Enabled during DMA transfer. + * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit + * | | |0 = Interrupt generation Disabled when wrong EOT is encountered. + * | | |1 = Interrupt generation Enabled when wrong EOT is encountered. + * @var SDH_T::DMAINTSTS + * Offset: 0x414 DMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note1: This bit is read only, but can be cleared by writing '1' to it. + * | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened + * | | |DMA will stop transfer and respond this event and then go to IDLE state + * | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again. + * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag + * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set. + * | | |0 = No EOT encountered before DMA transfer finished. + * | | |1 = EOT encountered before DMA transfer finished. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::GCTL + * Offset: 0x800 Global Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset SD host + * | | |The contents of control register will not be cleared + * | | |This bit will auto cleared after reset complete. + * |[1] |SDEN |Secure Digital Functionality Enable Bit + * | | |0 = SD functionality disabled. + * | | |1 = SD functionality enabled. + * @var SDH_T::GINTEN + * Offset: 0x804 Global Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit + * | | |0 = DMA READ/WRITE target abort interrupt generation disabled. + * | | |1 = DMA READ/WRITE target abort interrupt generation enabled. + * @var SDH_T::GINTSTS + * Offset: 0x808 Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) + * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation + * | | |When Target Abort is occurred, please reset all engine. + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::CTL + * Offset: 0x820 SD Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |COEN |Command Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output a command to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[1] |RIEN |Response Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[2] |DIEN |Data Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[3] |DOEN |Data Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[4] |R2EN |Response R2 Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7). + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 74 clock cycles to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 8 clock cycles. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[7] |CLKKEEP |SD Clock Enable Control + * | | |0 = SD host decided when to output clock and when to disable clock output automatically. + * | | |1 = SD clock always keeps free running. + * |[13:8] |CMDCODE |SD Command Code + * | | |This register contains the SD command code (0x00 - 0x3F). + * |[14] |CTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset the internal state machine and counters + * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared) + * | | |This bit will be auto cleared after few clock cycles. + * |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection) + * | | |0 = Data bus width is 1-bit. + * | | |1 = Data bus width is 4-bit. + * |[23:16] |BLKCNT |Block Counts to Be Transferred or Received + * | | |This field contains the block counts for data-in and data-out transfer + * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance + * | | |Don't fill 0x0 to this field. + * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1). + * |[27:24] |SDNWR |NWR Parameter for Block Write Operation + * | | |This value indicates the NWR parameter for data block write operation in SD clock counts + * | | |The actual clock cycle will be SDNWR+1. + * @var SDH_T::CMDARG + * Offset: 0x824 SD Command Argument Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ARGUMENT |SD Command Argument + * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card + * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field. + * @var SDH_T::INTEN + * Offset: 0x828 SD Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit + * | | |0 = BLKDIF (SDH_INTEN[0]) trigger interrupt Disable. + * | | |1 = BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled. + * |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit + * | | |0 = CRCIF (SDH_INTEN[1]) trigger interrupt Disable. + * | | |1 = CRCIF (SDH_INTEN[1]) trigger interrupt Enabled. + * |[8] |CDIEN |SD Card Detection Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when card is inserted or removed. + * | | |0 = CDIF (SDH_INTEN[8]) trigger interrupt Disable. + * | | |1 = CDIF (SDH_INTEN[8]) trigger interrupt Enabled. + * |[12] |RTOIEN |Response Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = RTOIF (SDH_INTEN[12]) trigger interrupt Disabled. + * | | |1 = RTOIF (SDH_INTEN[12]) trigger interrupt Enabled. + * |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when data input time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = DITOIF (SDH_INTEN[13]) trigger interrupt Disabled. + * | | |1 = DITOIF (SDH_INTEN[13]) trigger interrupt Enabled. + * |[14] |WKIEN |Wake-up Signal Generating Enable Bit + * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host. + * | | |0 = SD Card interrupt to wake-up chip Disabled. + * | | |1 = SD Card interrupt to wake-up chip Enabled. + * |[30] |CDSRC |SD Card Detect Source Selection + * | | |0 = From SD card's DAT3 pin. + * | | |Host need clock to got data on pin DAT3 + * | | |Please make sure CLKKEEP (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin. + * | | |1 = From GPIO pin. + * @var SDH_T::INTSTS + * Offset: 0x82C SD Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has finished all data-in or data-out block transfer + * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set. + * | | |0 = Not finished yet. + * | | |1 = Done. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer + * | | |When CRC error is occurred, software should reset SD engine + * | | |Some response (ex + * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag + * | | |In this condition, software should ignore CRC error and clears this bit manually. + * | | |0 = No CRC error is occurred. + * | | |1 = CRC error is occurred. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[2] |CRC7 |CRC7 Check Status (Read Only) + * | | |SD host will check CRC7 correctness during each response in + * | | |If that response does not contain CRC7 information (ex + * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit. + * | | |0 = Fault. + * | | |1 = OK. + * |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only) + * | | |SD host will check CRC16 correctness after data-in transfer. + * | | |0 = Fault. + * | | |1 = OK. + * |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only) + * | | |SD host will record CRC status of data-out transfer + * | | |Software could use this value to identify what type of error is during data-out transfer. + * | | |010 = Positive CRC status. + * | | |101 = Negative CRC status. + * | | |111 = SD card programming error occurs. + * |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only) + * | | |This bit is the DAT0 pin status of current selected SD port. + * |[8] |CDIF |SD Card Detection Interrupt Flag (Read Only) + * | | |This bit indicates that SD card is inserted or removed + * | | |Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active. + * | | |0 = No card is inserted or removed. + * | | |1 = There is a card inserted in or removed from SD. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Response time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Data input time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[16] |CDSTS |Card Detect Status of SD (Read Only) + * | | |This bit indicates the card detect pin status of SD, and is used for card detection + * | | |When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal. + * | | |If CDSRC (SDH_INTEN[30]) = 0, to select DAT3 for card detection:. + * | | |0 = Card removed. + * | | |1 = Card inserted. + * | | |If CDSRC (SDH_INTEN[30]) = 1, to select GPIO for card detection:. + * | | |0 = Card inserted. + * | | |1 = Card removed. + * |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only) + * | | |This bit indicates the DAT1 pin status of SD port. + * @var SDH_T::RESP0 + * Offset: 0x830 SD Receiving Response Token Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RESPTK0 |SD Receiving Response Token 0 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This field contains response bit 47-16 of the response token. + * @var SDH_T::RESP1 + * Offset: 0x834 SD Receiving Response Token Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RESPTK1 |SD Receiving Response Token 1 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This register contains the bit 15-8 of the response token. + * @var SDH_T::BLEN + * Offset: 0x838 SD Block Length Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit + * | | |An 11-bit value specifies the SD transfer byte count of a block + * | | |The actual byte count is equal to BLKLEN+1. + * | | |Note: The default SD block length is 512 bytes + * @var SDH_T::TOUT + * Offset: 0x83C SD Response/Data-in Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |TOUT |SD Response/Data-in Time-out Value + * | | |A 24-bit value specifies the time-out counts of response and data input + * | | |SD host controller will wait start bit of response or data-in until this value reached + * | | |The time period depends on SD engine clock frequency + * | | |Do not write a small number into this field, or you may never get response or data due to time-out. + * | | |Note: Filling 0x0 into this field will disable hardware time-out function. + */ + + __IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[224]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */ + __I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */ + __IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */ + __IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[250]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */ + __IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */ + __I uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */ + __IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */ + __IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */ + __IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */ + __I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */ + __I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */ + __IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */ + __IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */ + +} SDH_T; + + +/** + @addtogroup SDH_CONST SDH Bit Field Definition + Constant Definitions for SDH Controller +@{ */ + +#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */ +#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */ + +#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */ +#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */ + +#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */ +#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */ + +#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */ +#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */ + +#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */ +#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */ + +#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */ +#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */ + +#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */ +#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */ + +#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */ +#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */ + +#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */ +#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */ + +#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */ +#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */ + +#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */ +#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */ + +#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */ +#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */ + +#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */ +#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */ + +#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */ +#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */ + +#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */ +#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */ + +#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */ +#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */ + +#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */ +#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */ + +#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */ +#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */ + +#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */ +#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */ + +#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */ +#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */ + +#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */ +#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */ + +#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */ +#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */ + +#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */ +#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */ + +#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */ +#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */ + +#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */ +#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */ + +#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */ +#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */ + +#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */ +#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */ + +#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */ +#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */ + +#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */ +#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */ + +#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */ +#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */ + +#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */ +#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */ + +#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */ +#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */ + +#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */ +#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */ + +#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */ +#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */ + +#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */ +#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */ + +#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */ +#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */ + +#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */ +#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */ + +#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */ +#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */ + +#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */ +#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */ + +#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */ +#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */ + +#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */ +#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */ + +#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */ +#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */ + +#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */ +#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */ + +#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */ +#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */ + +#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */ +#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */ + +#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */ +#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */ + +#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */ +#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */ + +#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */ +#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */ + +#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */ +#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */ + +#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */ +#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */ + +#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */ +#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */ + +/**@}*/ /* SDH_CONST */ +/**@}*/ /* end of SDH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SDH_REG_H__ */ + diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spi_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spi_reg.h new file mode 100644 index 00000000000..c9421ce4115 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spi_reg.h @@ -0,0 +1,799 @@ +/**************************************************************************//** + * @file spi_reg.h + * @version V1.00 + * @brief SPI register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SPI Serial Peripheral Interface Controller(SPI) + Memory Mapped Structure for SPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var SPI_T::CTL + * Offset: 0x00 SPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIEN |SPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = SPI bus clock is idle low. + * | | |1 = SPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * | | |Note: For SPI1~SPI4, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode + * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI1~SPI4. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). + * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for SPI transfer + * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = SPI operates in full-duplex transfer. + * | | |1 = SPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = SPI unit transfer interrupt Disabled. + * | | |1 = SPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = SPI data is input direction. + * | | |1 = SPI data is output direction. + * @var SPI_T::CLKDIV + * Offset: 0x04 SPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * | | |Note: Not supported in I2S mode. + * @var SPI_T::SSCTL + * Offset: 0x08 SPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control (Master Only) + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the SPIx_SS line to inactive state. + * | | |1 = set the SPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the SPIx_SS line at inactive state. + * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]). + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (SPIx_SS). + * | | |0 = The slave selection signal SPIx_SS is active low. + * | | |1 = The slave selection signal SPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * @var SPI_T::PDMACTL + * Offset: 0x0C SPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. + * @var SPI_T::FIFOCTL + * Offset: 0x10 SPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. This bit should be set as 0 in I2S mode. + * | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length + * @var SPI_T::STATUS + * Offset: 0x14 SPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = SPI controller is in idle state. + * | | |1 = SPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = SPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |SPIENSTS |SPI Enable Status (Read Only) + * | | |0 = The SPI controller is disabled. + * | | |1 = The SPI controller is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var SPI_T::TX + * Offset: 0x20 SPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer. + * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0] + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section + * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var SPI_T::RX + * Offset: 0x30 SPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |There are 4-level FIFO buffers in this controller + * | | |The data receive register holds the data received from SPI data input pin + * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register + * | | |This is a read only register. + * @var SPI_T::I2SCTL + * Offset: 0x60 I2S Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Bit + * | | |0 = Disabled I2S mode. + * | | |1 = Enabled I2S mode. + * | | |Note: + * | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode. + * | | |2 + * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. + * |[1] |TXEN |Transmit Enable Bit + * | | |0 = Data transmit Disabled. + * | | |1 = Data transmit Enabled. + * |[2] |RXEN |Receive Enable Bit + * | | |0 = Data receive Disabled. + * | | |1 = Data receive Enabled. + * |[3] |MUTE |Transmit Mute Enable Bit + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Transmit channel zero. + * |[5:4] |WDWIDTH |Word Width + * | | |00 = data size is 8-bit. + * | | |01 = data size is 16-bit. + * | | |10 = data size is 24-bit. + * | | |11 = data size is 32-bit. + * |[6] |MONO |Monaural Data + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |0 = Left channel data at high byte. + * | | |1 = Left channel data at low byte. + * |[8] |SLAVE |Slave Mode + * | | |I2S can operate as master or slave + * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M480 series to audio CODEC chip + * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[15] |MCLKEN |Master Clock Enable Bit + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Right channel zero cross detection Disabled. + * | | |1 = Right channel zero cross detection Enabled. + * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Left channel zero cross detection Disabled. + * | | |1 = Left channel zero cross detection Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Bit + * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. + * | | |0 = Receive right channel data in Mono mode. + * | | |1 = Receive left channel data in Mono mode. + * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[29:28] |FORMAT |Data Format Selection + * | | |00 = I2S data format. + * | | |01 = MSB justified data format. + * | | |10 = PCM mode A. + * | | |11 = PCM mode B. + * @var SPI_T::I2SCLK + * Offset: 0x64 I2S Clock Divider Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |MCLKDIV |Master Clock Divider + * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices + * | | |The frequency of master clock, fMCLK, is determined by the following expressions: + * | | |If MCLKDIV >= 1,. + * | | |If MCLKDIV = 0,. + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2 + * | | |In general, the master clock rate is 256 times sampling clock rate. + * |[17:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |The clock frequency of bit clock , fBCLK, is determined by the following expression: + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. + * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . + * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. + * @var SPI_T::I2SSTS + * Offset: 0x68 I2S Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |RIGHT |Right Channel (Read Only) + * | | |This bit indicates the current transmit data is belong to which channel. + * | | |0 = Left channel. + * | | |1 = Right channel. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |I2SENSTS |I2S Enable Status (Read Only) + * | | |0 = The SPI/I2S control logic is disabled. + * | | |1 = The SPI/I2S control logic is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag + * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on right channel. + * | | |1 = Zero cross event occurred on right channel. + * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on left channel. + * | | |1 = Zero cross event occurred on left channel. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + */ + __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[11]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ + __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ + __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ + +} SPI_T; + +/** + @addtogroup SPI_CONST SPI Bit Field Definition + Constant Definitions for SPI Controller +@{ */ + +#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ +#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ + +#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ +#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ + +#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ +#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ + +#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ +#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ + +#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ +#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ + +#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ +#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ + +#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ +#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ + +#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ +#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ + +#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ +#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ + +#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ +#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ + +#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ +#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ + +#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ +#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ + +#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ +#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ + +#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ +#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ + +#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ +#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ + +#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ +#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ + +#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ +#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ + +#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ +#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ + +#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ +#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ + +#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ +#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ + +#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ +#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ + +#define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */ +#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */ + +#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ +#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ + +#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ +#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ + +#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ +#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ + +#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ +#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ + +#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ +#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ + +#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ +#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ + +#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ +#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ + +#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ +#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ + +#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ +#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ + +#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ +#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ + +#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ +#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ + +#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ +#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ + +#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ +#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ + +#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ +#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ + +#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ +#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ + +#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ +#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ + +#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ +#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ + +#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ +#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ + +#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ +#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ + +#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ +#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ + +#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ +#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ + +#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ +#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ + +#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ +#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ + +#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ +#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ + +#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ +#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ + +#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ +#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ + +#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ +#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ + +#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ +#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ + +#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ +#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ + +#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ +#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ + +#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ +#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ + +#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ +#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ + +#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ +#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ + +#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ +#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ + +#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ +#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ + +#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ +#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ + +#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ +#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ + +#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ +#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ + +#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ +#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ + +#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ +#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ + +#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ +#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ + +#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ +#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ + +#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ +#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ + +#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ +#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ + +#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ +#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ + +#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ +#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ + +#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ +#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ + +#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ +#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ + +#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ +#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ + +#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ +#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ + +#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ +#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ + +#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ +#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ + +#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ +#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ + +#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ +#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ + +#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ +#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ + +#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ +#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ + +#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ +#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ + +#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ +#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ + +#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ +#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ + +#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ +#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ + +#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ +#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ + +#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ +#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ + +#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ +#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ + +#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ +#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ + +#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ +#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ + +#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ +#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ + +#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ +#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ + +#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ +#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ + +#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ +#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ + +#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ +#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ + +/**@}*/ /* SPI_CONST */ +/**@}*/ /* end of SPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SPI_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spim_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spim_reg.h new file mode 100644 index 00000000000..262a3fbe491 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/spim_reg.h @@ -0,0 +1,556 @@ +/**************************************************************************//** + * @file spim_reg.h + * @version V1.00 + * @brief SPIM register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPIM_REG_H__ +#define __SPIM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SPIM Serial Peripheral Interface Controller Master Mode (SPIM) + Memory Mapped Structure for SPIM Controller +@{ */ + +typedef struct +{ + + + /** + * @var SPIM_T::CTL0 + * Offset: 0x00 Control and Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CIPHOFF |Cipher Disable Control + * | | |0 = Cipher function Enabled. + * | | |1 = Cipher function Disabled. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * | | |Note3 : When cipher encryption/decryption is enabled, please set DESELTIM (SPIM_DMMCTL[20:16]) >= 0x10. + * | | |When cipher encryption/decryption is disabled, please set DESELTIM(SPIM_DMMCTL[20:16]) >= 0x8. + * |[2] |BALEN |Balance the AHB Control Time Between Cipher Enable and Disable Control + * | | |When cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation + * | | |Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled. + * | | |Note: Only useful when cipher is disabled. + * |[5] |B4ADDREN |4-byte Address Mode Enable Control + * | | |0 = 4-byte address mode is disabled, and 3-byte address mode is enabled. + * | | |1 = 4-byte address mode is enabled. + * | | |Note: Used for DMA write mode, DMA read mode, and DMM mode. + * |[6] |IEN |Interrupt Enable Control + * | | |0 = SPIM Interrupt Disabled. + * | | |1 = SPIM Interrupt Enabled. + * |[7] |IF |Interrupt Flag + * | | |(1) Write Operation : + * | | |0 = No effect. + * | | |1 = Write 1 to clear. + * | | |(2) Read Operation : + * | | |0 = The transfer has not finished yet. + * | | |1 = The transfer has done. + * |[12:8] |DWIDTH |Transmit/Receive Bit Length + * | | |This specifies how many bits are transmitted/received in one transmit/receive transaction. + * | | |0x7 = 8 bits. + * | | |0xF = 16 bits. + * | | |0x17 = 24 bits. + * | | |0x1F = 32 bits. + * | | |Others = Incorrect transfer result. + * | | |Note1: Only used for normal I/O mode. + * | | |Note2: Only 8, 16, 24, and 32 bits are allowed. Other bit length will result in incorrect transfer. + * |[14:13] |BURSTNUM |Transmit/Receive Burst Number + * | | |This field specifies how many transmit/receive transactions should be executed continuously in one transfer. + * | | |0x0 = Only one transmit/receive transaction will be executed in one transfer. + * | | |0x1 = Two successive transmit/receive transactions will be executed in one transfer. + * | | |0x2 = Three successive transmit/receive transactions will be executed in one transfer. + * | | |0x3 = Four successive transmit/receive transactions will be executed in one transfer. + * | | |Note: Only used for normal I/O Mode. + * |[15] |QDIODIR |SPI Interface Direction Select for Quad/Dual Mode + * | | |0 = Interface signals are input. + * | | |1 = Interface signals are output. + * | | |Note: Only used for normal I/O mode. + * |[19:16] |SUSPITV |Suspend Interval + * | | |These four bits provide the configuration of suspend interval between two successive transmit/receive transactions in a transfer + * | | |The default value is 0x00 + * | | |When BURSTNUM = 00, setting this field has no effect on transfer + * | | |The desired interval is obtained according to the following equation (from the last falling edge of current SPI clock to the first rising edge of next SPI clock): + * | | | (SUSPITV+2)*period of AHB clock + * | | | 0x0 = 2 AHB clock cycles. + * | | | 0x1 = 3 AHB clock cycles. + * | | | ...... + * | | | 0xE = 16 AHB clock cycles. + * | | | 0xF = 17 AHB clock cycles. + * | | | Note: Only used for normal I/O mode. + * |[21:20] |BITMODE |SPI Interface Bit Mode + * | | |0x0 = Standard mode. + * | | |0x1 = Dual mode. + * | | |0x2 = Quad mode. + * | | |0x3 = Reserved. + * | | |Note: Only used for normal I/O mode. + * |[23:22] |OPMODE |SPI Function Operation Mode + * | | |0x0 = Normal I/O mode. (Note1) (Note3) + * | | |0x1 = DMA write mode. (Note2) (Note3) + * | | |0x2 = DMA read mode. (Note3) + * | | |0x3 = Direct Memory Mapping mode (DMM mode) (Default). (Note4) + * | | |Note1 : After user uses Normal I/O mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * | | |Note2 : In DMA write mode, hardware will send just one page program command per operation + * | | |Users must take care of cross-page cases + * | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * | | |Note3 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x00000000 to 0x01FFFFFF when user uses Normal I/O mode, DMA write mode, and DMA read mode to write/read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * | | |Note4 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x08000000 to 0x09FFFFFF when user uses Direct Memory mapping mode (DMM mode) to read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * |[31:24] |CMDCODE |Page Program Command Code (Note4) + * | | |(1) 0x02 = Page program (Used for DMA Write mode). + * | | |(2) 0x32 = Quad page program with TYPE_1 program flow (Used for DMA Write mode). (Note3) + * | | |(3) 0x38 = Quad page program with TYPE_2 program flow (Used for DMA Write mode). (Note3) + * | | |(4) 0x40 = Quad page program with TYPE_3 program flow (Used for DMA Write mode). (Note3) + * | | |The Others = Reserved. + * | | |Read Command Code : + * | | |(1) 0x03 = Standard Read (Used for DMA Read/DMM mode). + * | | |(2) 0x0B = Fast Read (Used for DMA Read/DMM mode). + * | | |The fast read command code "0x0B" is similar to command code of standard read "0x03" except it can operate at highest possible frequency + * | | |(Note2) + * | | |(3) 0x3B = Fast Read Dual Output (Used for DMA Read/DMM mode). + * | | |(4) 0xBB = Fast Read Dual I/O (Used for DMA Read/DMM mode). + * | | |The fast read dual I/O command code "0xBB" is similar to command code of fast read dual output "0x3B" but with capability to input the address bits two bits per clock + * | | |(Note2) + * | | |(5) 0xEB = Fast quad read (Used for DMA Read/DMM mode). + * | | |(6) 0xE7 = Word quad read (Used for DMA Read/DMM mode). + * | | |The command code of word quad read "0xE7" is similar to command code of fast quad read "0xEB" except that the lowest address bit must equal to 0 and the number of dummy cycles is less than fast quad read + * | | |(Note2) + * | | |(7) 0x0D = DTR/DDR Fast read (Used for DMA Read/DMM mode). + * | | |(8) 0xBD = DTR/DDR dual read (Used for DMA Read/DMM mode). + * | | |(9) 0xED = DTR/DDR quad read (Used for DMA Read/DMM mode). + * | | |The Others command codes are Reserved. + * | | |The DTR/DDR read commands "0x0D,0xBD,0xED" improves throughput by transferring address and data on both the falling and rising edge of SPI flash clock (SPIM_CLK) + * | | |It is similar to those commands "0x0B, 0xBB, 0xEB" but allows transfer of address and data on rising edge and falling edge of SPI flash output clock + * | | |(Note2) + * | | |Note1: Quad mode of SPI Flash must be enabled first by normal I/O mode before using quad page program/quad read commands. + * | | |Note2: See SPI flash specifications for support items. + * | | |Note3: For TYPE_1, TYPE_2, and TYPE_3 of page program command code, refer to Figure 7.19-3, Figure 7.19-4, and Figure 7.19-5. + * | | |Note4: Please disable "continuous read mode" and "burst wrap mode" before DMA write mode of SPI flash controller is used to program data of external SPI flash + * | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * @var SPIM_T::CTL1 + * Offset: 0x04 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIMEN |Go and Busy Status + * | | |(1) Write Operation : + * | | |0 = No effect. + * | | |1 = Start the transfer + * | | |This bit remains set during the transfer and is automatically cleared after transfer finished. + * | | |(2) Read Operation : + * | | |0 = The transfer has done. + * | | |1 = The transfer has not finished yet. + * | | |Note: All registers should be set before writing 1 to the SPIMEN bit + * | | |When a transfer is in progress, you should not write to any register of this peripheral. + * |[1] |CACHEOFF |Cache Memory Function Disable Control + * | | |0 = Cache memory function enable. (Default value) + * | | |1 = Cache memory function disable. + * | | |Note: When CCM mode is enabled, the cache function will be disable by hardware automatically + * | | |When CCM mode is disabled, the cache function can be enable or disable by user. + * |[2] |CCMEN |CCM (Core Coupled Memory) Mode Enable Control + * | | |0 = CCM mode disable. (Default value) + * | | |1 = CCM mode enable. + * | | |Note1: When CCM mode is enabled, the cache function will be disable by hardware automatically + * | | |When CCM mode is disabled, the cache function can be enabled or disabled by user. + * | | |Note2: When CCM mode is disabled, user accesses the core coupled memory by bus master + * | | |In this case, the SPI flash controller will send error response via HRESP bus signal to bus master. + * | | |Note3: When CCM mode needs to be enabled, user sets CCMEN to 1 and needs to read this register to show the current hardware status + * | | |When reading data of CCMEN is 1, MCU can start to read data from CCM memory space or write data to CCM memory space. + * |[3] |CDINVAL |Cache Data Invalid Enable Control + * | | |(1) Write Operation: + * | | |0 = No effect. + * | | |1 = Set all cache data to be invalid. This bit is cleared by hardware automatically. + * | | |(2) Read Operation : No effect + * | | |Note: When SPI flash memory is page erasing or whole flash erasing, please set CDINVAL to 0x1 + * | | |After user uses normal I/O mode or DMA write mode of SPI flash controller to program or erase the content of external SPI flash, please set CDINVAL to 0x1. + * |[4] |SS |Slave Select Active Enable Control + * | | |0 = SPIM_SS is in active level. + * | | |1 = SPIM_SS is in inactive level (Default). + * | | |Note: This interface can only drive one device/slave at a given time + * | | |Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer + * | | |Functional description of SSACTPOL(SPIM_CTL1[5]) and SS is shown in Table 2. + * |[5] |SSACTPOL |Slave Select Active Level + * | | |It defines the active level of device/slave select signal (SPIM_SS), and we show in Table 2. + * | | |0 = The SPIM_SS slave select signal is active low. + * | | |1 = The SPIM_SS slave select signal is active high. + * |[11:8] |IDLETIME |Idle Time Interval + * | | |In DMM mode, IDLETIME is set to control the minimum idle time between two SPI Flash accesses. + * | | |Minimum idle time = (IDLETIME + 1) * AHB clock cycle time. + * | | |Note1: Only used for DMM mode. + * | | |Note2 : AHB clock cycle time = 1/AHB clock frequency. + * |[31:16] |DIVIDER |Clock Divider Register + * | | |The value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock "SCLK" on the output SPIM_CLK pin + * | | |The desired frequency is obtained according to the following equation: + * | | |Note1: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of HCLK. + * | | |Note2: SCLK is serial SPI output clock. + * | | |Note3: Please check the specification of the used SPI flash component to decide the frequency of SPI flash clock. + * | | |Note4: For DTR/DDR read commands "0x0D, 0xBD, 0xED", the setting values of DIVIDER are only 1,2,4,8,16,32,..., where n = 0,1,2,3,4, ... + * @var SPIM_T::RXCLKDLY + * Offset: 0x0C RX Clock Delay Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DWDELSEL |SPI flash deselect time interval of DMA write mode + * | | |For DMA write mode only + * | | |This register sets the deselect time interval of SPI flash (i.e. + * | | |time interval of inactive level of SPIM_SS) when SPI flash controller operates on DMA write mode + * | | |(Note1) + * | | |Deselect time interval of DMA write mode = (DWDELSEL + 1) * AHB clock cycle time (Note2). + * | | |Note1: Please user check the used external SPI flash component to set this register value + * | | |In general case, the deselect time interval of SPI flash is greater than 50 ns when SPI flash performs the program operation. + * | | |Note2: AHB clock cycle time = 1/AHB clock frequency. + * |[18:16] |RDDLYSEL |Sampling Clock Delay Selection for Received Data + * | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode + * | | |Determine the number of inserted delay cycles + * | | |Used to adjust the sampling clock of received data to latch the correct data. + * | | |0x0 : No delay. (Default Value) + * | | |0x1 : Delay 1 SPI flash clock. + * | | |0x2 : Delay 2 SPI flash clocks. + * | | |0x3 : Delay 3 SPI flash clocks. + * | | |... + * | | |0x7 : Delay 7 SPI flash clocks + * | | |Note : We can use manufacturer id or device id of external SPI flash component to determine the correct setting value of RDDLYSEL, and we give example as follows. + * | | |For example, manufacturer id and device id of external SPI flash for some vendor are 0xEF and 0x1234 separately + * | | |Firstly, we set RDDLYSEL to 0x0, and use read manufacturer id/device id command to read the manufacturer id of external SPI flash by using normal I/O mode (the manufacturer id is 0xEF (1110_1111) in this example). + * | | |If manufacturer id which reads from external SPI flash is 0xF7 (1111_0111), it denotes that manufacturer id is shifted the right by 1 bit and most significant bit (MSB) of manufacturer id is assigned to 1 + * | | |According to manufacturer id reads from external SPI flash, we need to set RDDLYSEL to 0x1 to receive SPI flash data correctly. + * |[20] |RDEDGE |Sampling Clock Edge Selection for Received Data + * | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode + * | | |0 : Use SPI input clock rising edge to sample received data. (Default Value) + * | | |1 : Use SPI input clock falling edge to sample received data. + * @var SPIM_T::RX[4] + * Offset: 0x10 ~ 0x1C Data Receive Register 0 ~ 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXDAT |Data Receive Register + * | | |The Data Receive Registers hold the received data of the last executed transfer. + * | | |Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM] + * | | |If BURSTNUM > 0, received data are held in the most significant RXDAT register first. + * | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH] + * | | |If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RXDAT register first. + * | | |In a byte, received data are held in the most significant bit of RXDAT register first. + * | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, received data will be held in the order SPIM_RX3[23:0], SPIM_RX2[23:0], SPIM_RX1[23:0], SPIM_RX0[23:0]. + * | | |Example 2: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, received data will be held in the order SPIM_RX0[7:0], SPIM_RX0[15:8], SPIM_RX0[23:16]. + * | | |Example 3: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, received data will be held in the order SPIM_RX0[7], SPIM_RX0[6], ..., + * | | |SPIM_RX0[0]. + * @var SPIM_T::TX[4] + * Offset: 0x20 ~ 0x2C Data Transmit Register 0 ~ 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXDAT |Data Transmit Register + * | | |The Data Transmit Registers hold the data to be transmitted in next transfer. + * | | |Number of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM] + * | | |If BURSTNUM > 0, data are transmitted in the most significant TXDAT register first. + * | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH] + * | | |If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TXDAT register first. + * | | |In a byte, data are transmitted in the most significant bit of TXDAT register first. + * | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX3[23:0], SPIM_TX2[23:0], SPIM_TX1[23:0], SPIM_TX0[23:0] in next transfer. + * | | |Example 2: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX0[7:0], SPIM_TX0[15:8], SPIM_TX0[23:16] in next transfer. + * | | |Example 3: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, data will be transmitted in the order SPIM_TX0[7], SPIM_TX0[6], ..., + * | | |SPIM_TX0[0] in next transfer. + * @var SPIM_T::SRAMADDR + * Offset: 0x30 SRAM Memory Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDR |SRAM Memory Address + * | | |For DMA Read mode, this is the destination address for DMA transfer. + * | | |For DMA Write mode, this is the source address for DMA transfer. + * | | |Note: This address must be word-aligned. + * @var SPIM_T::DMACNT + * Offset: 0x34 DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |DMACNT |DMA Transfer Byte Count Register + * | | |It indicates the transfer length for DMA process. + * | | |Note1: The unit for counting is byte. + * | | |Note2: The number must be the multiple of 4. + * | | |Note3: Please check specification of used SPI flash to know maximum byte length of page program. + * @var SPIM_T::FADDR + * Offset: 0x38 SPI Flash Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDR |SPI Flash Address Register + * | | |For DMA Read mode, this is the source address for DMA transfer. + * | | |For DMA Write mode, this is the destination address for DMA transfer. + * | | |Note 1 : This address must be word-aligned. + * | | |Note 2 : For external SPI flash with 32 MB, the value of this SPI flash address register "ADDR" is from 0x00000000 to 0x01FFFFFF when user uses DMA write mode and DMA read mode to write/read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * @var SPIM_T::KEY1 + * Offset: 0x3C Cipher Key1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY1 |Cipher Key1 Register + * | | |This is the KEY1 data for cipher function. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * @var SPIM_T::KEY2 + * Offset: 0x40 Cipher Key2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY2 |Cipher Key2 Register + * | | |This is the KEY2 data for cipher function. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * @var SPIM_T::DMMCTL + * Offset: 0x44 Direct Memory Mapping Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:8] |CRMDAT |Mode bits data for Continuous Read Mode (or performance enhance mode) (Default value = 0) + * | | |Only for direct memory mapping mode + * | | |Set the mode bits data for continuous read mode (or performance enhance mode). + * | | |When we set this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25]), this reduces the command phase by eight clocks and allows the read address to be immediately entered after SPIM_SS asserted to active + * | | |(Note1) + * | | |Note1 : Please check the used SPI flash specification to know the setting value of this mode bits data, and different SPI flash vendor may use different setting values. + * | | |Note2 : CRMDAT needs to used with CREN(SPIM_DMMCTL[25]). + * |[20:16] |DESELTIM |SPI Flash Deselect Time + * | | |Only for direct memory mapping mode + * | | |Set the minimum time width of SPI flash deselect time (i.e. + * | | |Minimum SPIM_SS deselect time), and we show in Figure 7.19-8. + * | | |(1) Cache function disable : + * | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 1) * AHB clock cycle time. + * | | |(2) Cache function enable : + * | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 4) * AHB clock cycle time. + * | | |Note1 : AHB clock cycle time = 1/AHB clock frequency. + * | | |Note2 : When cipher encryption/decryption is enabled, please set this register value >= 0x10 + * | | |When cipher encryption/decryption is disabled, please set this register value >= 0x8. + * | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values. + * |[24] |BWEN |16 bytes Burst Wrap Mode Enable Control Register (Default value = 0) + * | | |Only for WINBOND SPI flash, direct memory mapping mode, Cache enable, and read command code "0xEB, and 0xE7" + * | | |0 = Burst Wrap Mode Disable. (Default) + * | | |1 = Burst Wrap Mode Enable. + * | | |In direct memory mapping mode, both of quad read commands "0xEB" and "0xE7" support burst wrap mode for cache application and performance enhance + * | | |For cache application, the burst wrap mode can be used to fill the cache line quickly (In this SPI flash controller, we use cache data line with 16 bytes size) + * | | |For performance enhance with direct memory mapping mode and cache enable, when cache data is miss, the burst wrap mode can let MCU get the required SPI flash data quickly. + * |[25] |CREN |Continuous Read Mode Enable Control + * | | |Only for direct memory mapping mode, read command codes 0xBB, 0xEB, 0xE7, 0x0D, 0xBD, 0xED (Note2) + * | | |0 = Continuous Read Mode Disable. (Default) + * | | |1 = Continuous Read Mode Enable. + * | | |For read operations of SPI flash, commands of fast read quad I/O (0xEB), word read quad I/O (0xE7 in Winbond SPI flash), fast read dual I/O (0xBB), DTR/DDR fast read (0x0D), DTR/DDR fast read dual I/O (0xBD), and DTR/DDR fast read quad I/O (0xED) can further reduce command overhead through setting the "continuous read mode" bits (8 bits) after the input address data. + * | | |Note: When user uses function of continuous read mode and sets USETEN (SPIM_CTL2[16]) to 1, CRMDAT(SPIM_DMMCTL[15:8]) must be set by used SPI flash specifications + * | | |When user uses function of continuous read mode and sets USETEN(SPIM_CTL2[16]) to 0, CRMDAT(SPIM_DMMCTL[15:8]) is set by default value of WINBOND SPI flash. + * |[26] |UACTSCLK |User Sets SPI Flash Active SCLK Time + * | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode + * | | |0 = According to DIVIDER(SPIM_CTL1[31:16]), ACTSCLKT(SPIM_DMMCTL[31:28]) is set by hardware automatically + * | | |(Default value) + * | | |1 = Set ACTSCLKT(SPIM_DMMCTL[31:28]) by user manually. + * | | |When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually, please set UACTSCLK to 1. + * |[31:28] |ACTSCLKT |SPI Flash Active SCLK Time + * | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode + * | | |This register sets time interval between SPIM SS active edge and the position edge of the first serial SPI output clock, and we show in Figure 7.19-8. + * | | |(1) ACTSCLKT = 0 (function disable) :. + * | | |Time interval = 1 AHB clock cycle time. + * | | |(2) ACTSCLKT != 0 (function enable) : + * | | |Time interval = (ACTSCLKT + 3) * AHB clock cycle time. + * | | |Note1 : AHB clock cycle time = 1/AHB clock frequency. + * | | |Note2 : SCLK is SPI output clock + * | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values. + * @var SPIM_T::CTL2 + * Offset: 0x48 Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16] |USETEN |User Set Value Enable Control + * | | |Only for direct memory mapping mode and DMA read mode with read commands 0x03,0x0B,0x3B,0xBB,0xEB,0xE7 + * | | |0 = Hardware circuit of SPI flash controller will use the following default values of DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations automatically. + * | | |Dummy cycle number (DCNUM) : + * | | |Dummy cycle number for read command 0x03 : 0x0 + * | | |Dummy cycle number for read command 0x0B : 0x8 + * | | |Dummy cycle number for read command 0x3B : 0x8 + * | | |Dummy cycle number for read command 0xBB : 0x0 + * | | |Dummy cycle number for read command 0xEB : 0x4 + * | | |Dummy cycle number for read command 0xE7 : 0x2 + * | | |Mode bits data for continuous read mode (CRMDAT) : 0x20 + * | | |1 = If DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) are not set as above default values, user must set USETEN to 0x1, DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations manually. + * | | |For DTR/DDR command codes 0x0D, 0xBD, and 0xED, please set USETEN to 0x1. + * |[20] |DTRMPOFF |Mode Phase OFF for DTR/DDR Command Codes 0x0D, 0xBD, and 0xED + * | | |Only for direct memory mapping mode and DMA read mode (Note1) + * | | |0 = mode cycle number (or performance enhance cycle number) does not equal to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED. + * | | |1 = mode cycle number (or performance enhance cycle number) equals to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED. + * | | |Note1 : Please check the used SPI flash specification to know the mode cycle number (or performance enhance cycle number) for DTR/DDR command codes 0x0D, 0xBD, and 0xED. + * |[28:24] |DCNUM |Dummy Cycle Number + * | | |Only for direct memory mapping mode and DMA read mode (Note1) + * | | |Set number of dummy cycles + * | | |(1) For non-DTR/non-DDR command codes 0x03, 0x0B, 0x3B, 0xBB, 0xEB, and 0xE7 : + * | | |When read command code do not need any dummy cycles (i.e. + * | | |dummy cycle number = 0x0), user must set DCNUM to 0x0. + * | | |For command code 0xBB, if both mode cycle number (or performance enhance cycle number) and dummy cycle number do not equal to 0x0 simultaneously, user must set DCNUM to "mode cycle number + dummy cycle number" by used SPI flash specification. + * | | |For command code 0xBB, if there is only dummy cycle number (i.e. + * | | |dummy cycle number != 0x0 and mode cycle number = 0x0 (or performance enhance cycle number = 0x0)), user set DCNUM to dummy cycle number by used SPI flash specification. + * | | |For command codes 0x0B, 0x3B, 0xEB, and 0xE7, user only set DCNUM to dummy cycle number by used SPI flash specification. + * | | |(2) For DTR/DDR command codes 0x0D, 0xBD, and 0xED : + * | | |user sets DCNUM to dummy cycle number and DTRMPOFF(SPIM_CTL2[20]) by used SPI flash specification. + * | | |Note1 : Number of dummy cycles depends on the frequency of SPI output clock, SPI flash vendor, and read command types + * | | |Please check the used SPI flash specification to know the setting value of this number of dummy cycles. + */ + __IO uint32_t CTL0; /*!< [0x0000] Control and Status Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] Control Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t RXCLKDLY; /*!< [0x000c] RX Clock Delay Control Register */ + __I uint32_t RX[4]; /*!< [0x0010] ~ [0x001C] Data Receive Register 0~3 */ + __IO uint32_t TX[4]; /*!< [0x0020] ~ [0x002C] Data Transmit Register 0~3 */ + __IO uint32_t SRAMADDR; /*!< [0x0030] SRAM Memory Address Register */ + __IO uint32_t DMACNT; /*!< [0x0034] DMA Transfer Byte Count Register */ + __IO uint32_t FADDR; /*!< [0x0038] SPI Flash Address Register */ + __O uint32_t KEY1; /*!< [0x003c] Cipher Key1 Register */ + __O uint32_t KEY2; /*!< [0x0040] Cipher Key2 Register */ + __IO uint32_t DMMCTL; /*!< [0x0044] Direct Memory Mapping Mode Control Register */ + __IO uint32_t CTL2; /*!< [0x0048] Control Register 2 */ + +} SPIM_T; + +/** + @addtogroup SPIM_CONST SPIM Bit Field Definition + Constant Definitions for SPIM Controller +@{ */ + +#define SPIM_CTL0_CIPHOFF_Pos (0) /*!< SPIM_T::CTL0: CIPHOFF Position */ +#define SPIM_CTL0_CIPHOFF_Msk (0x1ul << SPIM_CTL0_CIPHOFF_Pos) /*!< SPIM_T::CTL0: CIPHOFF Mask */ + +#define SPIM_CTL0_BALEN_Pos (2) /*!< SPIM_T::CTL0: BALEN Position */ +#define SPIM_CTL0_BALEN_Msk (0x1ul << SPIM_CTL0_BALEN_Pos) /*!< SPIM_T::CTL0: BALEN Mask */ + +#define SPIM_CTL0_B4ADDREN_Pos (5) /*!< SPIM_T::CTL0: B4ADDREN Position */ +#define SPIM_CTL0_B4ADDREN_Msk (0x1ul << SPIM_CTL0_B4ADDREN_Pos) /*!< SPIM_T::CTL0: B4ADDREN Mask */ + +#define SPIM_CTL0_IEN_Pos (6) /*!< SPIM_T::CTL0: IEN Position */ +#define SPIM_CTL0_IEN_Msk (0x1ul << SPIM_CTL0_IEN_Pos) /*!< SPIM_T::CTL0: IEN Mask */ + +#define SPIM_CTL0_IF_Pos (7) /*!< SPIM_T::CTL0: IF Position */ +#define SPIM_CTL0_IF_Msk (0x1ul << SPIM_CTL0_IF_Pos) /*!< SPIM_T::CTL0: IF Mask */ + +#define SPIM_CTL0_DWIDTH_Pos (8) /*!< SPIM_T::CTL0: DWIDTH Position */ +#define SPIM_CTL0_DWIDTH_Msk (0x1ful << SPIM_CTL0_DWIDTH_Pos) /*!< SPIM_T::CTL0: DWIDTH Mask */ + +#define SPIM_CTL0_BURSTNUM_Pos (13) /*!< SPIM_T::CTL0: BURSTNUM Position */ +#define SPIM_CTL0_BURSTNUM_Msk (0x3ul << SPIM_CTL0_BURSTNUM_Pos) /*!< SPIM_T::CTL0: BURSTNUM Mask */ + +#define SPIM_CTL0_QDIODIR_Pos (15) /*!< SPIM_T::CTL0: QDIODIR Position */ +#define SPIM_CTL0_QDIODIR_Msk (0x1ul << SPIM_CTL0_QDIODIR_Pos) /*!< SPIM_T::CTL0: QDIODIR Mask */ + +#define SPIM_CTL0_SUSPITV_Pos (16) /*!< SPIM_T::CTL0: SUSPITV Position */ +#define SPIM_CTL0_SUSPITV_Msk (0xful << SPIM_CTL0_SUSPITV_Pos) /*!< SPIM_T::CTL0: SUSPITV Mask */ + +#define SPIM_CTL0_BITMODE_Pos (20) /*!< SPIM_T::CTL0: BITMODE Position */ +#define SPIM_CTL0_BITMODE_Msk (0x3ul << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_T::CTL0: BITMODE Mask */ + +#define SPIM_CTL0_OPMODE_Pos (22) /*!< SPIM_T::CTL0: OPMODE Position */ +#define SPIM_CTL0_OPMODE_Msk (0x3ul << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_T::CTL0: OPMODE Mask */ + +#define SPIM_CTL0_CMDCODE_Pos (24) /*!< SPIM_T::CTL0: CMDCODE Position */ +#define SPIM_CTL0_CMDCODE_Msk (0xfful << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_T::CTL0: CMDCODE Mask */ + +#define SPIM_CTL1_SPIMEN_Pos (0) /*!< SPIM_T::CTL1: SPIMEN Position */ +#define SPIM_CTL1_SPIMEN_Msk (0x1ul << SPIM_CTL1_SPIMEN_Pos) /*!< SPIM_T::CTL1: SPIMEN Mask */ + +#define SPIM_CTL1_CACHEOFF_Pos (1) /*!< SPIM_T::CTL1: CACHEOFF Position */ +#define SPIM_CTL1_CACHEOFF_Msk (0x1ul << SPIM_CTL1_CACHEOFF_Pos) /*!< SPIM_T::CTL1: CACHEOFF Mask */ + +#define SPIM_CTL1_CCMEN_Pos (2) /*!< SPIM_T::CTL1: CCMEN Position */ +#define SPIM_CTL1_CCMEN_Msk (0x1ul << SPIM_CTL1_CCMEN_Pos) /*!< SPIM_T::CTL1: CCMEN Mask */ + +#define SPIM_CTL1_CDINVAL_Pos (3) /*!< SPIM_T::CTL1: CDINVAL Position */ +#define SPIM_CTL1_CDINVAL_Msk (0x1ul << SPIM_CTL1_CDINVAL_Pos) /*!< SPIM_T::CTL1: CDINVAL Mask */ + +#define SPIM_CTL1_SS_Pos (4) /*!< SPIM_T::CTL1: SS Position */ +#define SPIM_CTL1_SS_Msk (0x1ul << SPIM_CTL1_SS_Pos) /*!< SPIM_T::CTL1: SS Mask */ + +#define SPIM_CTL1_SSACTPOL_Pos (5) /*!< SPIM_T::CTL1: SSACTPOL Position */ +#define SPIM_CTL1_SSACTPOL_Msk (0x1ul << SPIM_CTL1_SSACTPOL_Pos) /*!< SPIM_T::CTL1: SSACTPOL Mask */ + +#define SPIM_CTL1_IDLETIME_Pos (8) /*!< SPIM_T::CTL1: IDLETIME Position */ +#define SPIM_CTL1_IDLETIME_Msk (0xful << SPIM_CTL1_IDLETIME_Pos) /*!< SPIM_T::CTL1: IDLETIME Mask */ + +#define SPIM_CTL1_DIVIDER_Pos (16) /*!< SPIM_T::CTL1: DIVIDER Position */ +#define SPIM_CTL1_DIVIDER_Msk (0xfffful << SPIM_CTL1_DIVIDER_Pos) /*!< SPIM_T::CTL1: DIVIDER Mask */ + +#define SPIM_RXCLKDLY_DWDELSEL_Pos (0) /*!< SPIM_T::RXCLKDLY: DWDELSEL Position */ +#define SPIM_RXCLKDLY_DWDELSEL_Msk (0xfful << SPIM_RXCLKDLY_DWDELSEL_Pos) /*!< SPIM_T::RXCLKDLY: DWDELSEL Mask */ + +#define SPIM_RXCLKDLY_RDDLYSEL_Pos (16) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Position */ +#define SPIM_RXCLKDLY_RDDLYSEL_Msk (0x7ul << SPIM_RXCLKDLY_RDDLYSEL_Pos) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Mask */ + +#define SPIM_RXCLKDLY_RDEDGE_Pos (20) /*!< SPIM_T::RXCLKDLY: RDEDGE Position */ +#define SPIM_RXCLKDLY_RDEDGE_Msk (0x1ul << SPIM_RXCLKDLY_RDEDGE_Pos) /*!< SPIM_T::RXCLKDLY: RDEDGE Mask */ + +#define SPIM_RX_RXDAT_Pos (0) /*!< SPIM_T::RX[4]: RXDAT Position */ +#define SPIM_RX_RXDAT_Msk (0xfffffffful << SPIM_RX_RXDAT_Pos) /*!< SPIM_T::RX[4]: RXDAT Mask */ + +#define SPIM_TX_TXDAT_Pos (0) /*!< SPIM_T::TX[4]: TXDAT Position */ +#define SPIM_TX_TXDAT_Msk (0xfffffffful << SPIM_TX_TXDAT_Pos) /*!< SPIM_T::TX[4]: TXDAT Mask */ + +#define SPIM_SRAMADDR_ADDR_Pos (0) /*!< SPIM_T::SRAMADDR: ADDR Position */ +#define SPIM_SRAMADDR_ADDR_Msk (0xfffffffful << SPIM_SRAMADDR_ADDR_Pos) /*!< SPIM_T::SRAMADDR: ADDR Mask */ + +#define SPIM_DMACNT_DMACNT_Pos (0) /*!< SPIM_T::DMACNT: DMACNT Position */ +#define SPIM_DMACNT_DMACNT_Msk (0xfffffful << SPIM_DMACNT_DMACNT_Pos) /*!< SPIM_T::DMACNT: DMACNT Mask */ + +#define SPIM_FADDR_ADDR_Pos (0) /*!< SPIM_T::FADDR: ADDR Position */ +#define SPIM_FADDR_ADDR_Msk (0xfffffffful << SPIM_FADDR_ADDR_Pos) /*!< SPIM_T::FADDR: ADDR Mask */ + +#define SPIM_KEY1_KEY1_Pos (0) /*!< SPIM_T::KEY1: KEY1 Position */ +#define SPIM_KEY1_KEY1_Msk (0xfffffffful << SPIM_KEY1_KEY1_Pos) /*!< SPIM_T::KEY1: KEY1 Mask */ + +#define SPIM_KEY2_KEY2_Pos (0) /*!< SPIM_T::KEY2: KEY2 Position */ +#define SPIM_KEY2_KEY2_Msk (0xfffffffful << SPIM_KEY2_KEY2_Pos) /*!< SPIM_T::KEY2: KEY2 Mask */ + +#define SPIM_DMMCTL_CRMDAT_Pos (8) /*!< SPIM_T::DMMCTL: CRMDAT Position */ +#define SPIM_DMMCTL_CRMDAT_Msk (0xfful << SPIM_DMMCTL_CRMDAT_Pos) /*!< SPIM_T::DMMCTL: CRMDAT Mask */ + +#define SPIM_DMMCTL_DESELTIM_Pos (16) /*!< SPIM_T::DMMCTL: DESELTIM Position */ +#define SPIM_DMMCTL_DESELTIM_Msk (0x1ful << SPIM_DMMCTL_DESELTIM_Pos) /*!< SPIM_T::DMMCTL: DESELTIM Mask */ + +#define SPIM_DMMCTL_BWEN_Pos (24) /*!< SPIM_T::DMMCTL: BWEN Position */ +#define SPIM_DMMCTL_BWEN_Msk (0x1ul << SPIM_DMMCTL_BWEN_Pos) /*!< SPIM_T::DMMCTL: BWEN Mask */ + +#define SPIM_DMMCTL_CREN_Pos (25) /*!< SPIM_T::DMMCTL: CREN Position */ +#define SPIM_DMMCTL_CREN_Msk (0x1ul << SPIM_DMMCTL_CREN_Pos) /*!< SPIM_T::DMMCTL: CREN Mask */ + +#define SPIM_DMMCTL_UACTSCLK_Pos (26) /*!< SPIM_T::DMMCTL: UACTSCLK Position */ +#define SPIM_DMMCTL_UACTSCLK_Msk (0x1ul << SPIM_DMMCTL_UACTSCLK_Pos) /*!< SPIM_T::DMMCTL: UACTSCLK Mask */ + +#define SPIM_DMMCTL_ACTSCLKT_Pos (28) /*!< SPIM_T::DMMCTL: ACTSCLKT Position */ +#define SPIM_DMMCTL_ACTSCLKT_Msk (0xful << SPIM_DMMCTL_ACTSCLKT_Pos) /*!< SPIM_T::DMMCTL: ACTSCLKT Mask */ + +#define SPIM_CTL2_USETEN_Pos (16) /*!< SPIM_T::CTL2: USETEN Position */ +#define SPIM_CTL2_USETEN_Msk (0x1ul << SPIM_CTL2_USETEN_Pos) /*!< SPIM_T::CTL2: USETEN Mask */ + +#define SPIM_CTL2_DTRMPOFF_Pos (20) /*!< SPIM_T::CTL2: DTRMPOFF Position */ +#define SPIM_CTL2_DTRMPOFF_Msk (0x1ul << SPIM_CTL2_DTRMPOFF_Pos) /*!< SPIM_T::CTL2: DTRMPOFF Mask */ + +#define SPIM_CTL2_DCNUM_Pos (24) /*!< SPIM_T::CTL2: DCNUM Position */ +#define SPIM_CTL2_DCNUM_Msk (0x1ful << SPIM_CTL2_DCNUM_Pos) /*!< SPIM_T::CTL2: DCNUM Mask */ + +/**@}*/ /* SPIM_CONST */ +/**@}*/ /* end of SPIM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SPIM_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sys_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sys_reg.h new file mode 100644 index 00000000000..57c2bc985c3 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/sys_reg.h @@ -0,0 +1,3475 @@ +/**************************************************************************//** + * @file sys_reg.h + * @version V1.00 + * @brief SYS register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SYS_REG_H__ +#define __SYS_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SYS System Manger Controller(SYS) + Memory Mapped Structure for SYS Controller +@{ */ + +typedef struct +{ + + + /** + * @var SYS_T::PDID + * Offset: 0x00 Part Device Identification Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDID |Part Device Identification Number (Read Only) + * | | |This register reflects device part number code + * | | |Software can read this register to identify which device is used. + * @var SYS_T::RSTSTS + * Offset: 0x04 System Reset Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PORF |POR Reset Flag + * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. + * | | |0 = No reset from POR or CHIPRST. + * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |PINRF |NRESET Pin Reset Flag + * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. + * | | |0 = No reset from nRESET pin. + * | | |1 = Pin nRESET had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |WDTRF |WDT Reset Flag + * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. + * | | |0 = No reset from watchdog timer or window watchdog timer. + * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset + * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. + * |[3] |LVRF |LVR Reset Flag + * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. + * | | |0 = No reset from LVR. + * | | |1 = LVR controller had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |BODRF |BOD Reset Flag + * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. + * | | |0 = No reset from BOD. + * | | |1 = The BOD had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |SYSRF |System Reset Flag + * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source. + * | | |0 = No reset from Cortex-M4. + * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |CPURF |CPU Reset Flag + * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). + * | | |0 = No reset from CPU. + * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1. + * | | |Note: Write to clear this bit to 0. + * |[8] |CPULKRF |CPU Lock-up Reset Flag + * | | |0 = No reset from CPU lock-up happened. + * | | |1 = The Cortex-M4 lock-up happened and chip is reset. + * | | |Note: Write 1 to clear this bit to 0. + * | | |Note2: When CPU lock-up happened under ICE is connected, This flag will set to 1 but chip will not reset. + * @var SYS_T::IPRST0 + * Offset: 0x08 Peripheral Reset Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) + * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. + * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. + * | | |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 + * | | |0 = Chip normal operation. + * | | |1 = Chip one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) + * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. + * | | |0 = Processor core normal operation. + * | | |1 = Processor core one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PDMARST |PDMA Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = PDMA controller normal operation. + * | | |1 = PDMA controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |EBIRST |EBI Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the EBI + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EBI controller normal operation. + * | | |1 = EBI controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |EMACRST |EMAC Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the EMAC controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EMAC controller normal operation. + * | | |1 = EMAC controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SDHOST0 controller normal operation. + * | | |1 = SDHOST0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRC calculation controller normal operation. + * | | |1 = CRC calculation controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |HSUSBDRST |HSUSBD Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the HSUSBD controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = HSUSBD controller normal operation. + * | | |1 = HSUSBD controller reset. + * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRYPTO controller normal operation. + * | | |1 = CRYPTO controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[14] |SPIMRST |SPIM Controller Reset + * | | |Setting this bit to 1 will generate a reset signal to the SPIM controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SPIM controller normal operation. + * | | |1 = SPIM controller reset. + * |[16] |USBHRST |USBH Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the USBH controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = USBH controller normal operation. + * | | |1 = USBH controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |SDH1RST |SDHOST1 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SDHOST1 controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SDHOST1 controller normal operation. + * | | |1 = SDHOST1 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IPRST1 + * Offset: 0x0C Peripheral Reset Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |GPIORST |GPIO Controller Reset + * | | |0 = GPIO controller normal operation. + * | | |1 = GPIO controller reset. + * |[2] |TMR0RST |Timer0 Controller Reset + * | | |0 = Timer0 controller normal operation. + * | | |1 = Timer0 controller reset. + * |[3] |TMR1RST |Timer1 Controller Reset + * | | |0 = Timer1 controller normal operation. + * | | |1 = Timer1 controller reset. + * |[4] |TMR2RST |Timer2 Controller Reset + * | | |0 = Timer2 controller normal operation. + * | | |1 = Timer2 controller reset. + * |[5] |TMR3RST |Timer3 Controller Reset + * | | |0 = Timer3 controller normal operation. + * | | |1 = Timer3 controller reset. + * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset + * | | |0 = Analog Comparator 0/1 controller normal operation. + * | | |1 = Analog Comparator 0/1 controller reset. + * |[8] |I2C0RST |I2C0 Controller Reset + * | | |0 = I2C0 controller normal operation. + * | | |1 = I2C0 controller reset. + * |[9] |I2C1RST |I2C1 Controller Reset + * | | |0 = I2C1 controller normal operation. + * | | |1 = I2C1 controller reset. + * |[10] |I2C2RST |I2C2 Controller Reset + * | | |0 = I2C2 controller normal operation. + * | | |1 = I2C2 controller reset. + * |[12] |QSPI0RST |QSPI0 Controller Reset + * | | |0 = QSPI0 controller normal operation. + * | | |1 = QSPI0 controller reset. + * |[13] |SPI0RST |SPI0 Controller Reset + * | | |0 = SPI0 controller normal operation. + * | | |1 = SPI0 controller reset. + * |[14] |SPI1RST |SPI1 Controller Reset + * | | |0 = SPI1 controller normal operation. + * | | |1 = SPI1 controller reset. + * |[15] |SPI2RST |SPI2 Controller Reset + * | | |0 = SPI2 controller normal operation. + * | | |1 = SPI2 controller reset. + * |[16] |UART0RST |UART0 Controller Reset + * | | |0 = UART0 controller normal operation. + * | | |1 = UART0 controller reset. + * |[17] |UART1RST |UART1 Controller Reset + * | | |0 = UART1 controller normal operation. + * | | |1 = UART1 controller reset. + * |[18] |UART2RST |UART2 Controller Reset + * | | |0 = UART2 controller normal operation. + * | | |1 = UART2 controller reset. + * |[19] |UART3RST |UART3 Controller Reset + * | | |0 = UART3 controller normal operation. + * | | |1 = UART3 controller reset. + * |[20] |UART4RST |UART4 Controller Reset + * | | |0 = UART4 controller normal operation. + * | | |1 = UART4 controller reset. + * |[21] |UART5RST |UART5 Controller Reset + * | | |0 = UART5 controller normal operation. + * | | |1 = UART5 controller reset. + * |[24] |CAN0RST |CAN0 Controller Reset + * | | |0 = CAN0 controller normal operation. + * | | |1 = CAN0 controller reset. + * |[25] |CAN1RST |CAN1 Controller Reset + * | | |0 = CAN1 controller normal operation. + * | | |1 = CAN1 controller reset. + * |[27] |USBDRST |USBD Controller Reset + * | | |0 = USBD controller normal operation. + * | | |1 = USBD controller reset. + * |[28] |EADCRST |EADC Controller Reset + * | | |0 = EADC controller normal operation. + * | | |1 = EADC controller reset. + * |[29] |I2S0RST |I2S0 Controller Reset + * | | |0 = I2S0 controller normal operation. + * | | |1 = I2S0 controller reset. + * @var SYS_T::IPRST2 + * Offset: 0x10 Peripheral Reset Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0RST |SC0 Controller Reset + * | | |0 = SC0 controller normal operation. + * | | |1 = SC0 controller reset. + * |[1] |SC1RST |SC1 Controller Reset + * | | |0 = SC1 controller normal operation. + * | | |1 = SC1 controller reset. + * |[2] |SC2RST |SC2 Controller Reset + * | | |0 = SC2 controller normal operation. + * | | |1 = SC2 controller reset. + * |[6] |SPI3RST |SPI3 Controller Reset + * | | |0 = SPI3 controller normal operation. + * | | |1 = SPI3 controller reset. + * |[8] |USCI0RST |USCI0 Controller Reset + * | | |0 = USCI0 controller normal operation. + * | | |1 = USCI0 controller reset. + * |[9] |USCI1RST |USCI1 Controller Reset + * | | |0 = USCI1 controller normal operation. + * | | |1 = USCI1 controller reset. + * |[12] |DACRST |DAC Controller Reset + * | | |0 = DAC controller normal operation. + * | | |1 = DAC controller reset. + * |[16] |EPWM0RST |EPWM0 Controller Reset + * | | |0 = EPWM0 controller normal operation. + * | | |1 = EPWM0 controller reset. + * |[17] |EPWM1RST |EPWM1 Controller Reset + * | | |0 = EPWM1 controller normal operation. + * | | |1 = EPWM1 controller reset. + * |[18] |BPWM0RST |BPWM0 Controller Reset + * | | |0 = BPWM0 controller normal operation. + * | | |1 = BPWM0 controller reset. + * |[19] |BPWM1RST |BPWM1 Controller Reset + * | | |0 = BPWM1 controller normal operation. + * | | |1 = BPWM1 controller reset. + * |[22] |QEI0RST |QEI0 Controller Reset + * | | |0 = QEI0 controller normal operation. + * | | |1 = QEI0 controller reset. + * |[23] |QEI1RST |QEI1 Controller Reset + * | | |0 = QEI1 controller normal operation. + * | | |1 = QEI1 controller reset. + * |[26] |ECAP0RST |ECAP0 Controller Reset + * | | |0 = ECAP0 controller normal operation. + * | | |1 = ECAP0 controller reset. + * |[27] |ECAP1RST |ECAP1 Controller Reset + * | | |0 = ECAP1 controller normal operation. + * | | |1 = ECAP1 controller reset. + * |[30] |OPARST |OP Amplifier (OPA) Controller Reset + * | | |0 = OPA controller normal operation. + * | | |1 = OPA controller reset. + * @var SYS_T::BODCTL + * Offset: 0x18 Brown-Out Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBODEN(CONFIG0 [19]). + * | | |0 = Brown-out Detector function Disabled. + * | | |1 = Brown-out Detector function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . + * | | |0 = Brown-out INTERRUPT function Enabled. + * | | |1 = Brown-out RESET function Enabled. + * | | |Note1: + * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). + * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high + * | | |BOD interrupt will keep till to the BODEN set to 0 + * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |BODIF |Brown-out Detector Interrupt Flag + * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. + * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect) + * | | |0 = BOD operate in normal mode (default). + * | | |1 = BOD Low Power mode Enabled. + * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |BODOUT |Brown-out Detector Output Status + * | | |0 = Brown-out Detector output status is 0. + * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. + * | | |1 = Brown-out Detector output status is 1. + * | | |It means the detected voltage is lower than BODVL setting + * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000. + * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) + * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting + * | | |LVR function is enabled by default. + * | | |0 = Low Voltage Reset function Disabled. + * | | |1 = Low Voltage Reset function Enabled. + * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) + * | | |000 = BOD output is sampled by RC10K clock. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) + * | | |000 = Without de-glitch function. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) + * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). + * | | |000 = Brown-Out Detector threshold voltage is 1.6V. + * | | |001 = Brown-Out Detector threshold voltage is 1.8V. + * | | |010 = Brown-Out Detector threshold voltage is 2.0V. + * | | |011 = Brown-Out Detector threshold voltage is 2.2V. + * | | |100 = Brown-Out Detector threshold voltage is 2.4V. + * | | |101 = Brown-Out Detector threshold voltage is 2.6V. + * | | |110 = Brown-Out Detector threshold voltage is 2.8V. + * | | |111 = Brown-Out Detector threshold voltage is 3.0V. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IVSCTL + * Offset: 0x1C Internal Voltage Source Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VTEMPEN |Temperature Sensor Enable Bit + * | | |This bit is used to enable/disable temperature sensor function. + * | | |0 = Temperature sensor function Disabled (default). + * | | |1 = Temperature sensor function Enabled. + * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9. + * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit + * | | |This bit is used to enable/disable VBAT unity gain buffer function. + * | | |0 = VBAT unity gain buffer function Disabled (default). + * | | |1 = VBAT unity gain buffer function Enabled. + * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result + * @var SYS_T::PORCTL + * Offset: 0x24 Power-On-Reset Controller Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) + * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again + * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. + * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::VREFCTL + * Offset: 0x28 VREF Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) + * | | |00000 = VREF is from external pin. + * | | |00011 = VREF is internal 1.6V. + * | | |00111 = VREF is internal 2.0V. + * | | |01011 = VREF is internal 2.5V. + * | | |01111 = VREF is internal 3.0V. + * | | |Others = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7:6] |PRELOAD_SEL|Pre-load Timing Selection. + * | | |00 = pre-load time is 60us for 0.1uF Capacitor. + * | | |01 = pre-load time is 310us for 1uF Capacitor. + * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. + * | | |11 = pre-load time is 2650us for 10uF Capacitor. + * @var SYS_T::USBPHY + * Offset: 0x2C USB PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |USBROLE |USB Role Option (Write Protect) + * | | |These two bits are used to select the role of USB. + * | | |00 = Standard USB Device mode. + * | | |01 = Standard USB Host mode. + * | | |10 = ID dependent mode. + * | | |11 = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable + * |[8] |USBEN |USB PHY Enable (Write Protect) + * | | |This bit is used to enable/disable USB PHY. + * | | |0 = USB PHY Disabled. + * | | |1 = USB PHY Enabled. + * |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect) + * | | |These two bits are used to select the role of HSUSB + * | | |00 = Standard HSUSB Device mode. + * | | |01 = Standard HSUSB Host mode. + * | | |10 = ID dependent mode. + * | | |11 = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[24] |HSUSBEN |HSUSB PHY Enable (Write Protect) + * | | |This bit is used to enable/disable HSUSB PHY. + * | | |0 = HSUSB PHY Disabled. + * | | |1 = HSUSB PHY Enabled. + * |[25] |HSUSBACT |HSUSB PHY Active Control + * | | |This bit is used to control HSUSB PHY at reset state or active state. + * | | |0 = HSUSB PHY at reset state. + * | | |1 = HSUSB PHY at active state. + * | | |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode. + * @var SYS_T::GPA_MFPL + * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection + * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection + * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection + * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection + * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection + * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection + * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection + * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection + * @var SYS_T::GPA_MFPH + * Offset: 0x34 GPIOA High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection + * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection + * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection + * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection + * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection + * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection + * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection + * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection + * @var SYS_T::GPB_MFPL + * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection + * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection + * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection + * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection + * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection + * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection + * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection + * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection + * @var SYS_T::GPB_MFPH + * Offset: 0x3C GPIOB High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection + * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection + * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection + * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection + * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection + * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection + * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection + * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection + * @var SYS_T::GPC_MFPL + * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection + * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection + * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection + * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection + * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection + * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection + * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection + * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection + * @var SYS_T::GPC_MFPH + * Offset: 0x44 GPIOC High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection + * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection + * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection + * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection + * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection + * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection + * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection + * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection + * @var SYS_T::GPD_MFPL + * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection + * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection + * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection + * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection + * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection + * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection + * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection + * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection + * @var SYS_T::GPD_MFPH + * Offset: 0x4C GPIOD High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection + * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection + * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection + * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection + * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection + * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection + * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection + * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection + * @var SYS_T::GPE_MFPL + * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection + * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection + * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection + * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection + * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection + * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection + * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection + * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection + * @var SYS_T::GPE_MFPH + * Offset: 0x54 GPIOE High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection + * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection + * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection + * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection + * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection + * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection + * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection + * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection + * @var SYS_T::GPF_MFPL + * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection + * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection + * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection + * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection + * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection + * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection + * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection + * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection + * @var SYS_T::GPF_MFPH + * Offset: 0x5C GPIOF High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection + * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection + * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection + * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection + * |[19:16] |PF12MFP |PF.12 Multi-function Pin Selection + * |[23:20] |PF13MFP |PF.13 Multi-function Pin Selection + * |[27:24] |PF14MFP |PF.14 Multi-function Pin Selection + * |[31:28] |PF15MFP |PF.15 Multi-function Pin Selection + * @var SYS_T::GPG_MFPL + * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PG0MFP |PG.0 Multi-function Pin Selection + * |[7:4] |PG1MFP |PG.1 Multi-function Pin Selection + * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection + * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection + * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection + * |[23:20] |PG5MFP |PG.5 Multi-function Pin Selection + * |[27:24] |PG6MFP |PG.6 Multi-function Pin Selection + * |[31:28] |PG7MFP |PG.7 Multi-function Pin Selection + * @var SYS_T::GPG_MFPH + * Offset: 0x64 GPIOG High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PG8MFP |PG.8 Multi-function Pin Selection + * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection + * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection + * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection + * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection + * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection + * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection + * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection + * @var SYS_T::GPH_MFPL + * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PH0MFP |PH.0 Multi-function Pin Selection + * |[7:4] |PH1MFP |PH.1 Multi-function Pin Selection + * |[11:8] |PH2MFP |PH.2 Multi-function Pin Selection + * |[15:12] |PH3MFP |PH.3 Multi-function Pin Selection + * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection + * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection + * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection + * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection + * @var SYS_T::GPH_MFPH + * Offset: 0x6C GPIOH High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection + * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection + * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection + * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection + * |[19:16] |PH12MFP |PH.12 Multi-function Pin Selection + * |[23:20] |PH13MFP |PH.13 Multi-function Pin Selection + * |[27:24] |PH14MFP |PH.14 Multi-function Pin Selection + * |[31:28] |PH15MFP |PH.15 Multi-function Pin Selection + * @var SYS_T::GPA_MFOS + * Offset: 0x80 GPIOA Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPB_MFOS + * Offset: 0x84 GPIOB Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPC_MFOS + * Offset: 0x88 GPIOC Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPD_MFOS + * Offset: 0x8C GPIOD Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPE_MFOS + * Offset: 0x90 GPIOE Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPF_MFOS + * Offset: 0x94 GPIOF Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPG_MFOS + * Offset: 0x98 GPIOG Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::GPH_MFOS + * Offset: 0x9C GPIOH Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F/H. + * @var SYS_T::SRAM_INTCTL + * Offset: 0xC0 System SRAM Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit + * | | |0 = SRAM parity check error interrupt Disabled. + * | | |1 = SRAM parity check error interrupt Enabled. + * @var SYS_T::SRAM_STATUS + * Offset: 0xC4 System SRAM Parity Error Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIF |SRAM Parity Check Error Flag + * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. + * | | |0 = No System SRAM parity error. + * | | |1 = System SRAM parity error occur. + * @var SYS_T::SRAM_ERRADDR + * Offset: 0xC8 System SRAM Parity Check Error Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ERRADDR |System SRAM Parity Error Address + * | | |This register shows system SRAM parity error byte address. + * @var SYS_T::SRAM_BISTCTL + * Offset: 0xD0 System SRAM BIST Test Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRBIST0 |SRAM Bank0 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SRAM bank0. + * | | |0 = system SRAM bank0 BIST Disabled. + * | | |1 = system SRAM bank0 BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |SRBIST1 |SRAM Bank1 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SRAM bank1. + * | | |0 = system SRAM bank1 BIST Disabled. + * | | |1 = system SRAM bank1 BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |CRBIST |CACHE BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for CACHE RAM + * | | |0 = system CACHE BIST Disabled. + * | | |1 = system CACHE BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |CANBIST |CAN BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for CAN RAM + * | | |0 = system CAN BIST Disabled. + * | | |1 = system CAN BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |USBBIST |USB BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for USB RAM + * | | |0 = system USB BIST Disabled. + * | | |1 = system USB BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |SPIMBIST |SPIM BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SPIM RAM + * | | |0 = system SPIM BIST Disabled. + * | | |1 = system SPIM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |EMCBIST |EMC BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for EMC RAM + * | | |0 = system EMC BIST Disabled. + * | | |1 = system EMC BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |PDMABIST |PDMA BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for PDMA RAM + * | | |0 = system PDMA BIST Disabled. + * | | |1 = system PDMA BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for HSUSBD RAM + * | | |0 = system HSUSBD BIST Disabled. + * | | |1 = system HSUSBD BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[9] |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for HSUSBH RAM + * | | |0 = system HSUSBH BIST Disabled. + * | | |1 = system HSUSBH BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |SRB0S0 |SRAM Bank0 Section 0 BIST Select (Write Protect) + * | | |This bit define if the first 16KB section of SRAM bank0 is selected or not when doing bist test. + * | | |0 = SRAM bank0 section 0 is deselected when doing bist test. + * | | |1 = SRAM bank0 section 0 is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test. + * |[17] |SRB0S1 |SRAM Bank0 Section 1 BIST Select (Write Protect) + * | | |This bit define if the second 16KB section of SRAM bank0 is selected or not when doing bist test. + * | | |0 = SRAM bank0 section 1 is deselected when doing bist test. + * | | |1 = SRAM bank0 section 1 is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test. + * |[18] |SRB1S0 |SRAM Bank1 Section 0 BIST Select (Write Protect) + * | | |This bit define if the first 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 first 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 first 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[19] |SRB1S1 |SRAM Bank1 Section 1 BIST Select (Write Protect) + * | | |This bit define if the second 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 second 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 second 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[20] |SRB1S2 |SRAM Bank1 Section 0 BIST Select (Write Protect) + * | | |This bit define if the third 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 third 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 third 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[21] |SRB1S3 |SRAM Bank1 Section 1 BIST Select (Write Protect) + * | | |This bit define if the fourth 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 fourth 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 fourth 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[22] |SRB1S4 |SRAM Bank1 Section 0 BIST Select (Write Protect) + * | | |This bit define if the fifth 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 fifth 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 fifth 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * |[23] |SRB1S5 |SRAM Bank1 Section 1 BIST Select (Write Protect) + * | | |This bit define if the sixth 16KB section of SRAM bank1 is selected or not when doing bist test. + * | | |0 = SRAM bank1 sixth 16KB section is deselected when doing bist test. + * | | |1 = SRAM bank1 sixth 16KB section is selected when doing bist test. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. + * @var SYS_T::SRAM_BISTSTS + * Offset: 0xD4 System SRAM BIST Test Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag + * | | |0 = 1st system SRAM BIST test pass. + * | | |1 = 1st system SRAM BIST test fail. + * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag + * | | |0 = 2nd system SRAM BIST test pass. + * | | |1 = 2nd system SRAM BIST test fail. + * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag + * | | |0 = System CACHE RAM BIST test pass. + * | | |1 = System CACHE RAM BIST test fail. + * |[3] |CANBEF |CAN SRAM BIST Fail Flag + * | | |0 = CAN SRAM BIST test pass. + * | | |1 = CAN SRAM BIST test fail. + * |[4] |USBBEF |USB SRAM BIST Fail Flag + * | | |0 = USB SRAM BIST test pass. + * | | |1 = USB SRAM BIST test fail. + * |[16] |SRBEND0 |1st SRAM BIST Test Finish + * | | |0 = 1st system SRAM BIST active. + * | | |1 =1st system SRAM BIST finish. + * |[17] |SRBEND1 |2nd SRAM BIST Test Finish + * | | |0 = 2nd system SRAM BIST is active. + * | | |1 = 2nd system SRAM BIST finish. + * |[18] |CRBEND |CACHE SRAM BIST Test Finish + * | | |0 = System CACHE RAM BIST is active. + * | | |1 = System CACHE RAM BIST test finish. + * |[19] |CANBEND |CAN SRAM BIST Test Finish + * | | |0 = CAN SRAM BIST is active. + * | | |1 = CAN SRAM BIST test finish. + * |[20] |USBBEND |USB SRAM BIST Test Finish + * | | |0 = USB SRAM BIST is active. + * | | |1 = USB SRAM BIST test finish. + * @var SYS_T::IRCTCTL + * Offset: 0xF0 HIRC Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. + * | | |10 = Reserved.. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator. + * | | |1 = HIRC trim reference from internal USB synchronous mode. + * | | |Note: HIRC trim reference clock is 20Khz in test mode. + * @var SYS_T::IRCTIEN + * Offset: 0xF4 HIRC Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). + * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. + * @var SYS_T::IRCTISTS + * Offset: 0xF8 HIRC Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt + * | | |Write 1 to clear this to 0 + * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERRIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accuracy. + * | | |1 = Clock frequency is inaccuracy. + * @var SYS_T::REGLCTL + * Offset: 0x100 Register Lock Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REGLCTL |Register Lock Control Code + * | | |Some registers have write-protection function + * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. + * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. + * | | |Register Lock Control Code + * | | |0 = Write-protection Enabled for writing protected registers + * | | |Any write to the protected register is ignored. + * | | |1 = Write-protection Disabled for writing protected registers. + * @var SYS_T::PLCTL + * Offset: 0x1F8 Power Level Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PLSEL |Power Level Select(Write Protect) + * | | |00 = Power level is PL0. + * | | |01 = Power level is PL1. + * | | |Others = Reserved. + * |[21:16] |LVSSTEP |LDO Voltage Scaling Step(Write Protect) + * | | |The LVSSTEP value is LDO voltage rising step. + * | | |Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV. + * |[31:24] |LVSPRD |LDO Voltage Scaling Period(Write Protect) + * | | |The LVSPRD value is the period of each LDO voltage rising step. + * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. + * @var SYS_T::PLSTS + * Offset: 0x1FC Power Level Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) + * | | |This bit is set by hardware when core voltage is changing + * | | |After core voltage change is completed, this bit will be cleared automatically by hardware. + * | | |0 = Core voltage change is completed. + * | | |1 = Core voltage change is ongoing. + * |[9:8] |PLSTATUS |Power Level Status (Read Only) + * | | |00 = Power level is PL0. + * | | |01 = Power level is PL1. + * | | |Others = Reserved. + * @var SYS_T::AHBMCTL + * Offset: 0x400 AHB Bus Matrix Priority Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect) + * | | |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix + * | | |0 = Run robin mode. + * | | |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + */ + __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ + __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ + __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ + __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ + __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[1]; + /** @endcond */ + __IO uint32_t BODCTL; /*!< [0x0018] Brown-Out Detector Control Register */ + __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[1]; + /** @endcond */ + __IO uint32_t PORCTL; /*!< [0x0024] Power-On-Reset Controller Register */ + __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ + __IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */ + __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */ + __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPH; /*!< [0x005c] GPIOF High Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPH; /*!< [0x006c] GPIOH High Byte Multiple Function Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[4]; + /** @endcond */ + __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ + __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ + __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ + __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ + __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ + __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ + __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ + __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE3[8]; + /** @endcond */ + __IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */ + __IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */ + __I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE4[1]; + /** @endcond */ + __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */ + __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE5[6]; + /** @endcond */ + __IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */ + __IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */ + __IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE6[1]; + /** @endcond */ + __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE7[61]; + /** @endcond */ + __IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */ + __I uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE8[128]; + /** @endcond */ + __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ + +} SYS_T; + +/** + @addtogroup SYS_CONST SYS Bit Field Definition + Constant Definitions for SYS Controller +@{ */ + +#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ +#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ + +#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ +#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ + +#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ +#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ + +#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ +#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ + +#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ +#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ + +#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ +#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ + +#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ +#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ + +#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ +#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ + +#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ +#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ + +#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ +#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ + +#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ +#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ + +#define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */ +#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */ + +#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ +#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ + +#define SYS_IPRST0_EMACRST_Pos (5) /*!< SYS_T::IPRST0: EMACRST Position */ +#define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) /*!< SYS_T::IPRST0: EMACRST Mask */ + +#define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ +#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ + +#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ +#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ + +#define SYS_IPRST0_HSUSBDRST_Pos (10) /*!< SYS_T::IPRST0: HSUSBDRST Position */ +#define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */ + +#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ +#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ + +#define SYS_IPRST0_SPIMRST_Pos (14) /*!< SYS_T::IPRST0: SPIMRST Position */ +#define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) /*!< SYS_T::IPRST0: SPIMRST Mask */ + +#define SYS_IPRST0_USBHRST_Pos (16) /*!< SYS_T::IPRST0: USBHRST Position */ +#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */ + +#define SYS_IPRST0_SDH1RST_Pos (17) /*!< SYS_T::IPRST0: SDH1RST Position */ +#define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */ + +#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ +#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ + +#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ +#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ + +#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ +#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ + +#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ +#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ + +#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ +#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ + +#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ +#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ + +#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ +#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ + +#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ +#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ + +#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ +#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ + +#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ +#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ + +#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ +#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ + +#define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ +#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ + +#define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ +#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ + +#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ +#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ + +#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ +#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ + +#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ +#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ + +#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ +#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ + +#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ +#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ + +#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ +#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ + +#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */ +#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */ + +#define SYS_IPRST1_CAN1RST_Pos (25) /*!< SYS_T::IPRST1: CAN1RST Position */ +#define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /*!< SYS_T::IPRST1: CAN1RST Mask */ + +#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ +#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ + +#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */ +#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */ + +#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ +#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ + +#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ +#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ + +#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ +#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ + +#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ +#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ + +#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ +#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ + +#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ +#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ + +#define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ +#define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ + +#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ +#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ + +#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ +#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ + +#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ +#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ + +#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ +#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ + +#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ +#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ + +#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */ +#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */ + +#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */ +#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */ + +#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ +#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ + +#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ +#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ + +#define SYS_IPRST2_OPARST_Pos (30) /*!< SYS_T::IPRST2: OPARST Position */ +#define SYS_IPRST2_OPARST_Msk (0x1ul << SYS_IPRST2_OPARST_Pos) /*!< SYS_T::IPRST2: OPARST Mask */ + +#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ +#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ + +#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ +#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ + +#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ +#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ + +#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */ +#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */ + +#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ +#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ + +#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ +#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ + +#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ +#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ + +#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ +#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ + +#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ +#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ + +#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ +#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ + +#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ +#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ + +#define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */ +#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */ + +#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ +#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ + +#define SYS_VREFCTL_PRELOAD_SEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOAD_SEL Position */ +#define SYS_VREFCTL_PRELOAD_SEL_Msk (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos) /*!< SYS_T::VREFCTL: PRELOAD_SEL Mask */ + +#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ +#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ + +#define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ +#define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ + +#define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */ +#define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */ + +#define SYS_USBPHY_HSUSBROLE_Pos (16) /*!< SYS_T::USBPHY: HSUSBROLE Position */ +#define SYS_USBPHY_HSUSBROLE_Msk (0x3ul << SYS_USBPHY_HSUSBROLE_Pos) /*!< SYS_T::USBPHY: HSUSBROLE Mask */ + +#define SYS_USBPHY_HSUSBEN_Pos (24) /*!< SYS_T::USBPHY: HSUSBEN Position */ +#define SYS_USBPHY_HSUSBEN_Msk (0x1ul << SYS_USBPHY_HSUSBEN_Pos) /*!< SYS_T::USBPHY: HSUSBEN Mask */ + +#define SYS_USBPHY_HSUSBACT_Pos (25) /*!< SYS_T::USBPHY: HSUSBACT Position */ +#define SYS_USBPHY_HSUSBACT_Msk (0x1ul << SYS_USBPHY_HSUSBACT_Pos) /*!< SYS_T::USBPHY: HSUSBACT Mask */ + +#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ +#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ + +#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ +#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ + +#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ +#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ + +#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ +#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ + +#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ +#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ + +#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ +#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ + +#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ +#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ + +#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ +#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ + +#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ +#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ + +#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ +#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ + +#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ +#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ + +#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ +#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ + +#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ +#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ + +#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ +#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ + +#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ +#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ + +#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ +#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ + +#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ +#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ + +#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ +#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ + +#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ +#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ + +#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ +#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ + +#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ +#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ + +#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ +#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ + +#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ +#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ + +#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ +#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ + +#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ +#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ + +#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ +#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ + +#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ +#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ + +#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ +#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ + +#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ +#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ + +#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ +#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ + +#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ +#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ + +#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ +#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ + +#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ +#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ + +#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ +#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ + +#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ +#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ + +#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ +#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ + +#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ +#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ + +#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ +#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ + +#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ +#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ + +#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ +#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ + +#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ +#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ + +#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ +#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ + +#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ +#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ + +#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ +#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ + +#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ +#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ + +#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ +#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ + +#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */ +#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */ + +#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */ +#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */ + +#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ +#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ + +#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ +#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ + +#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ +#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ + +#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ +#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ + +#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ +#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ + +#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ +#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ + +#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ +#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ + +#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ +#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ + +#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ +#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ + +#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ +#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ + +#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ +#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ + +#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ +#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ + +#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ +#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ + +#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */ +#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */ + +#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ +#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ + +#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */ +#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */ + +#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ +#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ + +#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ +#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ + +#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ +#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ + +#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ +#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ + +#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ +#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ + +#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ +#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ + +#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ +#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ + +#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ +#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ + +#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ +#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ + +#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ +#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ + +#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ +#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ + +#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ +#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ + +#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ +#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ + +#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ +#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ + +#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */ +#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */ + +#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */ +#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */ + +#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ +#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ + +#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ +#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ + +#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ +#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ + +#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ +#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ + +#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ +#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ + +#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ +#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ + +#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ +#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ + +#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ +#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ + +#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ +#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ + +#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ +#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ + +#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ +#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ + +#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ +#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ + +#define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS_T::GPF_MFPH: PF12MFP Position */ +#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS_T::GPF_MFPH: PF12MFP Mask */ + +#define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS_T::GPF_MFPH: PF13MFP Position */ +#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS_T::GPF_MFPH: PF13MFP Mask */ + +#define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS_T::GPF_MFPH: PF14MFP Position */ +#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS_T::GPF_MFPH: PF14MFP Mask */ + +#define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS_T::GPF_MFPH: PF15MFP Position */ +#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS_T::GPF_MFPH: PF15MFP Mask */ + +#define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFPL: PG0MFP Position */ +#define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS_T::GPG_MFPL: PG0MFP Mask */ + +#define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS_T::GPG_MFPL: PG1MFP Position */ +#define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS_T::GPG_MFPL: PG1MFP Mask */ + +#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */ +#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */ + +#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */ +#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */ + +#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */ +#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */ + +#define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS_T::GPG_MFPL: PG5MFP Position */ +#define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS_T::GPG_MFPL: PG5MFP Mask */ + +#define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS_T::GPG_MFPL: PG6MFP Position */ +#define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS_T::GPG_MFPL: PG6MFP Mask */ + +#define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS_T::GPG_MFPL: PG7MFP Position */ +#define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS_T::GPG_MFPL: PG7MFP Mask */ + +#define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFPH: PG8MFP Position */ +#define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS_T::GPG_MFPH: PG8MFP Mask */ + +#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */ +#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */ + +#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */ +#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */ + +#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */ +#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */ + +#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */ +#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */ + +#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */ +#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */ + +#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */ +#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */ + +#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */ +#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */ + +#define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFPL: PH0MFP Position */ +#define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS_T::GPH_MFPL: PH0MFP Mask */ + +#define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS_T::GPH_MFPL: PH1MFP Position */ +#define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS_T::GPH_MFPL: PH1MFP Mask */ + +#define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS_T::GPH_MFPL: PH2MFP Position */ +#define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS_T::GPH_MFPL: PH2MFP Mask */ + +#define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS_T::GPH_MFPL: PH3MFP Position */ +#define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS_T::GPH_MFPL: PH3MFP Mask */ + +#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */ +#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */ + +#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */ +#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */ + +#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */ +#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */ + +#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */ +#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */ + +#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */ +#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */ + +#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */ +#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */ + +#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */ +#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */ + +#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */ +#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */ + +#define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS_T::GPH_MFPH: PH12MFP Position */ +#define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS_T::GPH_MFPH: PH12MFP Mask */ + +#define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS_T::GPH_MFPH: PH13MFP Position */ +#define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS_T::GPH_MFPH: PH13MFP Mask */ + +#define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS_T::GPH_MFPH: PH14MFP Position */ +#define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS_T::GPH_MFPH: PH14MFP Mask */ + +#define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS_T::GPH_MFPH: PH15MFP Position */ +#define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS_T::GPH_MFPH: PH15MFP Mask */ + +#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ +#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ + +#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ +#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ + +#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ +#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ + +#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ +#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ + +#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ +#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ + +#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ +#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ + +#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ +#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ + +#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ +#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ + +#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ +#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ + +#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ +#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ + +#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ +#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ + +#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ +#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ + +#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ +#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ + +#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ +#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ + +#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ +#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ + +#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ +#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ + +#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ +#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ + +#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ +#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ + +#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ +#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ + +#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ +#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ + +#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ +#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ + +#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ +#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ + +#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ +#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ + +#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ +#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ + +#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ +#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ + +#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ +#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ + +#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ +#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ + +#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ +#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ + +#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ +#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ + +#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ +#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ + +#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ +#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ + +#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ +#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ + +#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ +#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ + +#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ +#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ + +#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ +#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ + +#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ +#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ + +#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ +#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ + +#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ +#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ + +#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ +#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ + +#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ +#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ + +#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ +#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ + +#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ +#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ + +#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ +#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ + +#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ +#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ + +#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ +#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ + +#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ +#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ + +#define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */ +#define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */ + +#define SYS_GPC_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPC_MFOS: MFOS15 Position */ +#define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) /*!< SYS_T::GPC_MFOS: MFOS15 Mask */ + +#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ +#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ + +#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ +#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ + +#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ +#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ + +#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ +#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ + +#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ +#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ + +#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ +#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ + +#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ +#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ + +#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ +#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ + +#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ +#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ + +#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ +#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ + +#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ +#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ + +#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ +#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ + +#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ +#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ + +#define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */ +#define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */ + +#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ +#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ + +#define SYS_GPD_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPD_MFOS: MFOS15 Position */ +#define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) /*!< SYS_T::GPD_MFOS: MFOS15 Mask */ + +#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ +#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ + +#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ +#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ + +#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ +#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ + +#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ +#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ + +#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ +#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ + +#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ +#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ + +#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ +#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ + +#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ +#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ + +#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ +#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ + +#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ +#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ + +#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ +#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ + +#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ +#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ + +#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ +#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ + +#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ +#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ + +#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ +#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ + +#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ +#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ + +#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ +#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ + +#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ +#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ + +#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ +#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ + +#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ +#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ + +#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ +#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ + +#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ +#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ + +#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ +#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ + +#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ +#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ + +#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ +#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ + +#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ +#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ + +#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ +#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ + +#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ +#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ + +#define SYS_GPF_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPF_MFOS: MFOS12 Position */ +#define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) /*!< SYS_T::GPF_MFOS: MFOS12 Mask */ + +#define SYS_GPF_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPF_MFOS: MFOS13 Position */ +#define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) /*!< SYS_T::GPF_MFOS: MFOS13 Mask */ + +#define SYS_GPF_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPF_MFOS: MFOS14 Position */ +#define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) /*!< SYS_T::GPF_MFOS: MFOS14 Mask */ + +#define SYS_GPF_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPF_MFOS: MFOS15 Position */ +#define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) /*!< SYS_T::GPF_MFOS: MFOS15 Mask */ + +#define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */ +#define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */ + +#define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */ +#define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */ + +#define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ +#define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ + +#define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ +#define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ + +#define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ +#define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ + +#define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */ +#define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */ + +#define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */ +#define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */ + +#define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */ +#define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */ + +#define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */ +#define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */ + +#define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ +#define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ + +#define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ +#define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ + +#define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ +#define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ + +#define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ +#define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ + +#define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ +#define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ + +#define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ +#define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ + +#define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ +#define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ + +#define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */ +#define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */ + +#define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */ +#define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */ + +#define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */ +#define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */ + +#define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */ +#define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */ + +#define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ +#define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ + +#define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ +#define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ + +#define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ +#define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ + +#define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ +#define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ + +#define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ +#define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ + +#define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ +#define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ + +#define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ +#define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ + +#define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ +#define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ + +#define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */ +#define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */ + +#define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */ +#define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */ + +#define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */ +#define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */ + +#define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */ +#define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */ + +#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */ +#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */ + +#define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */ +#define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */ + +#define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */ +#define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */ + +#define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */ +#define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */ + +#define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */ +#define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */ + +#define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */ +#define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */ + +#define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */ +#define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */ + +#define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */ +#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */ + +#define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */ +#define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask */ + +#define SYS_SRAM_BISTCTL_EMCBIST_Pos (6) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Position */ +#define SYS_SRAM_BISTCTL_EMCBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMCBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Mask */ + +#define SYS_SRAM_BISTCTL_PDMABIST_Pos (7) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Position */ +#define SYS_SRAM_BISTCTL_PDMABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Mask */ + +#define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos (8) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/ +#define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask */ + +#define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos (9) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/ +#define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask */ + +#define SYS_SRAM_BISTCTL_SRB0S0_Pos (16) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Position */ +#define SYS_SRAM_BISTCTL_SRB0S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Mask */ + +#define SYS_SRAM_BISTCTL_SRB0S1_Pos (17) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Position */ +#define SYS_SRAM_BISTCTL_SRB0S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S0_Pos (18) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Position */ +#define SYS_SRAM_BISTCTL_SRB1S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S1_Pos (19) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Position */ +#define SYS_SRAM_BISTCTL_SRB1S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S2_Pos (20) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Position */ +#define SYS_SRAM_BISTCTL_SRB1S2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S2_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S3_Pos (21) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Position */ +#define SYS_SRAM_BISTCTL_SRB1S3_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S3_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S4_Pos (22) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Position */ +#define SYS_SRAM_BISTCTL_SRB1S4_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S4_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Mask */ + +#define SYS_SRAM_BISTCTL_SRB1S5_Pos (23) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Position */ +#define SYS_SRAM_BISTCTL_SRB1S5_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S5_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Mask */ + +#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/ +#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */ + +#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/ +#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */ + +#define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */ +#define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */ + +#define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */ +#define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */ + +#define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */ +#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */ + +#define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */ +#define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */ + +#define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */ +#define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */ + +#define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */ +#define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */ + +#define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */ +#define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */ + +#define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */ +#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */ + +#define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */ +#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */ + +#define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */ +#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */ + +#define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */ +#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */ + +#define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */ +#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */ + +#define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */ +#define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */ + +#define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */ +#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */ + +#define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */ +#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */ + +#define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */ +#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */ + +#define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */ +#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */ + +#define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */ +#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */ + +#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ +#define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ + +#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ +#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ + +#define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */ +#define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */ + +#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ +#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ + +#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ +#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ + +#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ +#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ + +#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ +#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ + +/**@}*/ /* SYS_CONST */ +/**@}*/ /* end of SYS register group */ + +/** + @addtogroup NMI NMI Controller (NMI) + Memory Mapped Structure for NMI Controller +@{ */ + +typedef struct +{ + + + /** + * @var NMI_T::NMIEN + * Offset: 0x00 NMI Source Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) + * | | |0 = BOD NMI source Disabled. + * | | |1 = BOD NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect) + * | | |0 = IRC TRIM NMI source Disabled. + * | | |1 = IRC TRIM NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PWRWU_INT |Power-down Mode Wake-up NMI Source Enable (Write Protect) + * | | |0 = Power-down mode wake-up NMI source Disabled. + * | | |1 = Power-down mode wake-up NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |SRAM_PERR |SRAM Parity Check NMI Source Enable (Write Protect) + * | | |0 = SRAM parity check error NMI source Disabled. + * | | |1 = SRAM parity check error NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CLKFAIL |Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect) + * | | |0 = Clock fail detected and IRC Auto Trim interrupt NMI source Disabled. + * | | |1 = Clock fail detected and IRC Auto Trim interrupt NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect) + * | | |0 = RTC NMI source Disabled. + * | | |1 = RTC NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect) + * | | |0 = Backup register tamper detected NMI source Disabled. + * | | |1 = Backup register tamper detected NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.6 or PB.5 pin NMI source Disabled. + * | | |1 = External interrupt from PA.6 or PB.5 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled. + * | | |1 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled. + * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.2 or PC.7 pin NMI source Disabled. + * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled. + * | | |1 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.7 or PF.14 pin NMI source Disabled. + * | | |1 = External interrupt from PB.7 or PF.14 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect) + * | | |0 = UART0 NMI source Disabled. + * | | |1 = UART0 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect) + * | | |0 = UART1 NMI source Disabled. + * | | |1 = UART1 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var NMI_T::NMISTS + * Offset: 0x04 NMI Source Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD Interrupt Flag (Read Only) + * | | |0 = BOD interrupt is deasserted. + * | | |1 = BOD interrupt is asserted. + * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only) + * | | |0 = HIRC TRIM interrupt is deasserted. + * | | |1 = HIRC TRIM interrupt is asserted. + * |[2] |PWRWU_INT |Power-down Mode Wake-up Interrupt Flag (Read Only) + * | | |0 = Power-down mode wake-up interrupt is deasserted. + * | | |1 = Power-down mode wake-up interrupt is asserted. + * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only) + * | | |0 = SRAM parity check error interrupt is deasserted. + * | | |1 = SRAM parity check error interrupt is asserted. + * |[4] |CLKFAIL |Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only) + * | | |0 = Clock fail detected or IRC Auto Trim interrupt is deasserted. + * | | |1 = Clock fail detected or IRC Auto Trim interrupt is asserted. + * |[6] |RTC_INT |RTC Interrupt Flag (Read Only) + * | | |0 = RTC interrupt is deasserted. + * | | |1 = RTC interrupt is asserted. + * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only) + * | | |0 = Backup register tamper detected interrupt is deasserted. + * | | |1 = Backup register tamper detected interrupt is asserted. + * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.6 or PB.5 interrupt is deasserted. + * | | |1 = External Interrupt from PA.6 or PB.5 interrupt is asserted. + * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted. + * | | |1 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted. + * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted. + * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted. + * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted. + * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted. + * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted. + * | | |1 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted. + * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.7 or PF.14 interrupt is deasserted. + * | | |1 = External Interrupt from PB.7 or PF.14 interrupt is asserted. + * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is deasserted. + * | | |1 = UART1 interrupt is asserted. + * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is deasserted. + * | | |1 = UART1 interrupt is asserted. + */ + __IO uint32_t NMIEN; /*!< [0x0000] NMI Source Interrupt Enable Register */ + __I uint32_t NMISTS; /*!< [0x0004] NMI Source Interrupt Status Register */ + +} NMI_T; + +/** + @addtogroup NMI_CONST NMI Bit Field Definition + Constant Definitions for NMI Controller +@{ */ + +#define NMI_NMIEN_BODOUT_Pos (0) /*!< NMI_T::NMIEN: BODOUT Position */ +#define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) /*!< NMI_T::NMIEN: BODOUT Mask */ + +#define NMI_NMIEN_IRC_INT_Pos (1) /*!< NMI_T::NMIEN: IRC_INT Position */ +#define NMI_NMIEN_IRC_INT_Msk (0x1ul << NMI_NMIEN_IRC_INT_Pos) /*!< NMI_T::NMIEN: IRC_INT Mask */ + +#define NMI_NMIEN_PWRWU_INT_Pos (2) /*!< NMI_T::NMIEN: PWRWU_INT Position */ +#define NMI_NMIEN_PWRWU_INT_Msk (0x1ul << NMI_NMIEN_PWRWU_INT_Pos) /*!< NMI_T::NMIEN: PWRWU_INT Mask */ + +#define NMI_NMIEN_SRAM_PERR_Pos (3) /*!< NMI_T::NMIEN: SRAM_PERR Position */ +#define NMI_NMIEN_SRAM_PERR_Msk (0x1ul << NMI_NMIEN_SRAM_PERR_Pos) /*!< NMI_T::NMIEN: SRAM_PERR Mask */ + +#define NMI_NMIEN_CLKFAIL_Pos (4) /*!< NMI_T::NMIEN: CLKFAIL Position */ +#define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) /*!< NMI_T::NMIEN: CLKFAIL Mask */ + +#define NMI_NMIEN_RTC_INT_Pos (6) /*!< NMI_T::NMIEN: RTC_INT Position */ +#define NMI_NMIEN_RTC_INT_Msk (0x1ul << NMI_NMIEN_RTC_INT_Pos) /*!< NMI_T::NMIEN: RTC_INT Mask */ + +#define NMI_NMIEN_TAMPER_INT_Pos (7) /*!< NMI_T::NMIEN: TAMPER_INT Position */ +#define NMI_NMIEN_TAMPER_INT_Msk (0x1ul << NMI_NMIEN_TAMPER_INT_Pos) /*!< NMI_T::NMIEN: TAMPER_INT Mask */ + +#define NMI_NMIEN_EINT0_Pos (8) /*!< NMI_T::NMIEN: EINT0 Position */ +#define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) /*!< NMI_T::NMIEN: EINT0 Mask */ + +#define NMI_NMIEN_EINT1_Pos (9) /*!< NMI_T::NMIEN: EINT1 Position */ +#define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) /*!< NMI_T::NMIEN: EINT1 Mask */ + +#define NMI_NMIEN_EINT2_Pos (10) /*!< NMI_T::NMIEN: EINT2 Position */ +#define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) /*!< NMI_T::NMIEN: EINT2 Mask */ + +#define NMI_NMIEN_EINT3_Pos (11) /*!< NMI_T::NMIEN: EINT3 Position */ +#define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) /*!< NMI_T::NMIEN: EINT3 Mask */ + +#define NMI_NMIEN_EINT4_Pos (12) /*!< NMI_T::NMIEN: EINT4 Position */ +#define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) /*!< NMI_T::NMIEN: EINT4 Mask */ + +#define NMI_NMIEN_EINT5_Pos (13) /*!< NMI_T::NMIEN: EINT5 Position */ +#define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) /*!< NMI_T::NMIEN: EINT5 Mask */ + +#define NMI_NMIEN_UART0_INT_Pos (14) /*!< NMI_T::NMIEN: UART0_INT Position */ +#define NMI_NMIEN_UART0_INT_Msk (0x1ul << NMI_NMIEN_UART0_INT_Pos) /*!< NMI_T::NMIEN: UART0_INT Mask */ + +#define NMI_NMIEN_UART1_INT_Pos (15) /*!< NMI_T::NMIEN: UART1_INT Position */ +#define NMI_NMIEN_UART1_INT_Msk (0x1ul << NMI_NMIEN_UART1_INT_Pos) /*!< NMI_T::NMIEN: UART1_INT Mask */ + +#define NMI_NMISTS_BODOUT_Pos (0) /*!< NMI_T::NMISTS: BODOUT Position */ +#define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) /*!< NMI_T::NMISTS: BODOUT Mask */ + +#define NMI_NMISTS_IRC_INT_Pos (1) /*!< NMI_T::NMISTS: IRC_INT Position */ +#define NMI_NMISTS_IRC_INT_Msk (0x1ul << NMI_NMISTS_IRC_INT_Pos) /*!< NMI_T::NMISTS: IRC_INT Mask */ + +#define NMI_NMISTS_PWRWU_INT_Pos (2) /*!< NMI_T::NMISTS: PWRWU_INT Position */ +#define NMI_NMISTS_PWRWU_INT_Msk (0x1ul << NMI_NMISTS_PWRWU_INT_Pos) /*!< NMI_T::NMISTS: PWRWU_INT Mask */ + +#define NMI_NMISTS_SRAM_PERR_Pos (3) /*!< NMI_T::NMISTS: SRAM_PERR Position */ +#define NMI_NMISTS_SRAM_PERR_Msk (0x1ul << NMI_NMISTS_SRAM_PERR_Pos) /*!< NMI_T::NMISTS: SRAM_PERR Mask */ + +#define NMI_NMISTS_CLKFAIL_Pos (4) /*!< NMI_T::NMISTS: CLKFAIL Position */ +#define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) /*!< NMI_T::NMISTS: CLKFAIL Mask */ + +#define NMI_NMISTS_RTC_INT_Pos (6) /*!< NMI_T::NMISTS: RTC_INT Position */ +#define NMI_NMISTS_RTC_INT_Msk (0x1ul << NMI_NMISTS_RTC_INT_Pos) /*!< NMI_T::NMISTS: RTC_INT Mask */ + +#define NMI_NMISTS_TAMPER_INT_Pos (7) /*!< NMI_T::NMISTS: TAMPER_INT Position */ +#define NMI_NMISTS_TAMPER_INT_Msk (0x1ul << NMI_NMISTS_TAMPER_INT_Pos) /*!< NMI_T::NMISTS: TAMPER_INT Mask */ + +#define NMI_NMISTS_EINT0_Pos (8) /*!< NMI_T::NMISTS: EINT0 Position */ +#define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) /*!< NMI_T::NMISTS: EINT0 Mask */ + +#define NMI_NMISTS_EINT1_Pos (9) /*!< NMI_T::NMISTS: EINT1 Position */ +#define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) /*!< NMI_T::NMISTS: EINT1 Mask */ + +#define NMI_NMISTS_EINT2_Pos (10) /*!< NMI_T::NMISTS: EINT2 Position */ +#define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) /*!< NMI_T::NMISTS: EINT2 Mask */ + +#define NMI_NMISTS_EINT3_Pos (11) /*!< NMI_T::NMISTS: EINT3 Position */ +#define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) /*!< NMI_T::NMISTS: EINT3 Mask */ + +#define NMI_NMISTS_EINT4_Pos (12) /*!< NMI_T::NMISTS: EINT4 Position */ +#define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) /*!< NMI_T::NMISTS: EINT4 Mask */ + +#define NMI_NMISTS_EINT5_Pos (13) /*!< NMI_T::NMISTS: EINT5 Position */ +#define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) /*!< NMI_T::NMISTS: EINT5 Mask */ + +#define NMI_NMISTS_UART0_INT_Pos (14) /*!< NMI_T::NMISTS: UART0_INT Position */ +#define NMI_NMISTS_UART0_INT_Msk (0x1ul << NMI_NMISTS_UART0_INT_Pos) /*!< NMI_T::NMISTS: UART0_INT Mask */ + +#define NMI_NMISTS_UART1_INT_Pos (15) /*!< NMI_T::NMISTS: UART1_INT Position */ +#define NMI_NMISTS_UART1_INT_Msk (0x1ul << NMI_NMISTS_UART1_INT_Pos) /*!< NMI_T::NMISTS: UART1_INT Mask */ + +/**@}*/ /* NMI_CONST */ +/**@}*/ /* end of NMI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SYS_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/system_M480.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/system_M480.h new file mode 100644 index 00000000000..b161062afd7 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/system_M480.h @@ -0,0 +1,66 @@ +/**************************************************************************//** + * @file system_M480.h + * @version V1.00 + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M480 + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __SYSTEM_M480_H__ +#define __SYSTEM_M480_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +#define __HSI (12000000UL) /*!< PLL default output is 50MHz */ +#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */ +#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */ +#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */ +#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */ +#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */ + + +#define __SYSTEM_CLOCK (1UL*__HXT) + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ +extern uint32_t PllClock; /*!< PLL Output Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the micro controller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_M480_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/timer_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/timer_reg.h new file mode 100644 index 00000000000..109926d342f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/timer_reg.h @@ -0,0 +1,1072 @@ +/**************************************************************************//** + * @file timer_reg.h + * @version V1.00 + * @brief TIMER register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup TIMER Timer Controller(TIMER) + Memory Mapped Structure for TIMER Controller +@{ */ + +typedef struct +{ + + + /** + * @var TIMER_T::CTL + * Offset: 0x00 Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PSC |Prescale Counter + * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter + * | | |If this field is 0 (PSC = 0), then there is no scaling. + * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. + * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control + * | | |Setting this bit will enable the inter-timer trigger capture function. + * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event + * | | |Also, Timer1/3 will be in trigger-counting mode of capture function. + * | | |0 = Inter-Timer Trigger Capture mode Disabled. + * | | |1 = Inter-Timer Trigger Capture mode Enabled. + * | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0. + * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit + * | | |0 = The behavior selection in periodic mode is Disabled. + * | | |When user updates CMPDAT while timer is running in periodic mode, + * | | |CNT will be reset to default value. + * | | |1 = The behavior selection in periodic mode is Enabled. + * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, + * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. + * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. + * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. + * |[21] |TGLPINSEL |Toggle-output Pin Select + * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). + * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). + * |[22] |CAPSRC |Capture Pin Source Selection + * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin. + * | | |1 = Capture Function source is from internal ACMP output signal + * | | |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source. + * |[23] |WKEN |Wake-up Function Enable Bit + * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. + * | | |0 = Wake-up function Disabled if timer interrupt signal generated. + * | | |1 = Wake-up function Enabled if timer interrupt signal generated. + * |[24] |EXTCNTEN |Event Counter Mode Enable Bit + * | | |This bit is for external counting pin function enabled. + * | | |0 = Event counter mode Disabled. + * | | |1 = Event counter mode Enabled. + * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. + * |[25] |ACTSTS |Timer Active Status Bit (Read Only) + * | | |This bit indicates the 24-bit up counter status. + * | | |0 = 24-bit up counter is not active. + * | | |1 = 24-bit up counter is active. + * | | |Note: This bit may active when CNT 0 transition to CNT 1. + * |[28:27] |OPMODE |Timer Counting Mode Select + * | | |00 = The Timer controller is operated in One-shot mode. + * | | |01 = The Timer controller is operated in Periodic mode. + * | | |10 = The Timer controller is operated in Toggle-output mode. + * | | |11 = The Timer controller is operated in Continuous Counting mode. + * |[29] |INTEN |Timer Interrupt Enable Bit + * | | |0 = Timer time-out interrupt Disabled. + * | | |1 = Timer time-out interrupt Enabled. + * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. + * |[30] |CNTEN |Timer Counting Enable Bit + * | | |0 = Stops/Suspends counting. + * | | |1 = Starts counting. + * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. + * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. + * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects TIMER counting. + * | | |TIMER counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |TIMER counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var TIMER_T::CMP + * Offset: 0x04 Timer Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CMPDAT |Timer Comparator Value + * | | |CMPDAT is a 24-bit compared value register + * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. + * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). + * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. + * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field + * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. + * @var TIMER_T::INTSTS + * Offset: 0x08 Timer Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIF |Timer Interrupt Flag + * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. + * | | |0 = No effect. + * | | |1 = CNT value matches the CMPDAT value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |TWKF |Timer Wake-up Flag + * | | |This bit indicates the interrupt wake-up flag status of timer. + * | | |0 = Timer does not cause CPU wake-up. + * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::CNT + * Offset: 0x0C Timer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer Data Register + * | | |Read operation. + * | | |Read this register to get CNT value. For example: + * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value. + * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value. + * | | |Write operation. + * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. + * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) + * | | |This bit indicates if the counter reset operation active. + * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter + * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress + * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. + * | | |0 = Reset operation is done. + * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. + * | | |Note: This bit is read only. + * @var TIMER_T::CAP + * Offset: 0x10 Timer Capture Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CAPDAT |Timer Capture Data Register + * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. + * @var TIMER_T::EXTCTL + * Offset: 0x14 Timer External Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTPHASE |Timer External Count Phase + * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3). + * | | |0 = A falling edge of external counting pin will be counted. + * | | |1 = A rising edge of external counting pin will be counted. + * |[3] |CAPEN |Timer External Capture Pin Enable Bit + * | | |This bit enables the TMx_EXT capture pin input function. + * | | |0 =TMx_EXT (x= 0~3) pin Disabled. + * | | |1 =TMx_EXT (x= 0~3) pin Enabled. + * |[4] |CAPFUNCS |Capture Function Selection + * | | |0 = External Capture Mode Enabled. + * | | |1 = External Reset Mode Enabled. + * | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. + * | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. + * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit + * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled. + * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled. + * | | |Note: CAPIEN is used to enable timer external interrupt + * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. + * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. + * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit + * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled. + * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. + * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit + * | | |0 = TMx (x= 0~3) pin de-bounce Disabled. + * | | |1 = TMx (x= 0~3) pin de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. + * |[8] |ACMPSSEL |ACMP Source Selection to Trigger Capture Function + * | | |0 = Capture Function source is from internal ACMP0 output signal. + * | | |1 = Capture Function source is from internal ACMP1 output signal. + * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. + * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect + * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. + * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. + * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. + * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer. + * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer.. + * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. + * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. + * | | |100, 101 = Reserved. + * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function + * | | |0 = Event Counter input source is from TMx (x= 0~3) pin. + * | | |1 = Event Counter input source is from USB internal SOF output signal. + * @var TIMER_T::EINTSTS + * Offset: 0x18 Timer External Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPIF |Timer External Capture Interrupt Flag + * | | |This bit indicates the timer external capture interrupt flag status. + * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur. + * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. + * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status + * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. + * @var TIMER_T::TRGCTL + * Offset: 0x1C Timer Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRGSSEL |Trigger Source Select Bit + * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or + * | | |capture interrupt signal. + * | | |0 = Time-out interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC. + * | | |1 = Capture interrupt signal is used to internal trigger EPWM, PDMA, DAC, and EADC. + * |[1] |TRGEPWM |Trigger EPWM Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be as EPWM counter clock source. + * | | |0 = Timer interrupt trigger EPWM Disabled. + * | | |1 = Timer interrupt trigger EPWM Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM counter clock source. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM counter clock source. + * |[2] |TRGEADC |Trigger EADC Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. + * | | |0 = Timer interrupt trigger EADC Disabled. + * | | |1 = Timer interrupt trigger EADC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion. + * |[3] |TRGDAC |Trigger DAC Enable Bit + * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. + * | | |0 = Timer interrupt trigger DAC Disabled. + * | | |1 = Timer interrupt trigger DAC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. + * |[4] |TRGPDMA |Trigger PDMA Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. + * | | |0 = Timer interrupt trigger PDMA Disabled. + * | | |1 = Timer interrupt trigger PDMA Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. + * @var TIMER_T::ALTCTL + * Offset: 0x20 Timer Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FUNCSEL |Function Selection + * | | |0 = Timer controller is used as timer function. + * | | |1 = Timer controller is used as PWM function. + * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. + * @var TIMER_T::PWMCTL + * Offset: 0x40 Timer PWM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN |PWM Counter Enable Bit + * | | |0 = PWM counter and clock prescale Stop Running. + * | | |1 = PWM counter and clock prescale Start Running. + * |[2:1] |CNTTYPE |PWM Counter Behavior Type + * | | |00 = Up count type. + * | | |01 = Down count type. + * | | |10 = Up-down count type. + * | | |11 = Reserved. + * |[3] |CNTMODE |PWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[8] |CTRLD |Center Re-load + * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. + * |[9] |IMMLDEN |Immediately Load Enable Bit + * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled + * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. + * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP. + * | | |Note: If IMMLDEN is enabled, CTRLD will be invalid. + * |[16] |OUTMODE |PWM Output Mode + * | | |This bit controls the output mode of corresponding PWM channel. + * | | |0 = PWM independent mode. + * | | |1 = PWM complementary mode. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects PWM output. + * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMCLKSRC + * Offset: 0x44 Timer PWM Counter Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CLKSRC |PWM Counter Clock Source Select + * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event. + * | | |000 = TMRx_CLK. + * | | |001 = Internal TIMER0 time-out or capture event. + * | | |010 = Internal TIMER1 time-out or capture event. + * | | |011 = Internal TIMER2 time-out or capture event. + * | | |100 = Internal TIMER3 time-out or capture event. + * | | |Others = Reserved. + * | | |Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. + * @var TIMER_T::PWMCLKPSC + * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale + * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) + * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. + * @var TIMER_T::PWMCNTCLR + * Offset: 0x4C Timer PWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR |Clear PWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type. + * @var TIMER_T::PWMPERIOD + * Offset: 0x50 Timer PWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |PWM Period Register + * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |In up and down count type: + * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. + * | | |In up-down count type: + * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK. + * | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. + * @var TIMER_T::PWMCMPDAT + * Offset: 0x54 Timer PWM Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |PWM Comparator Register + * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. + * @var TIMER_T::PWMDTCTL + * Offset: 0x58 Timer PWM Dead-Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following two formulas: + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0. + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect) + * | | |Dead-time insertion function is only active when PWM complementary mode is enabled + * | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale. + * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMCNT + * Offset: 0x5C Timer PWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |PWM Counter Value Register (Read Only) + * | | |User can monitor CNT to know the current counter value in 16-bit period counter. + * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only) + * | | |0 = Counter is active in down count. + * | | |1 = Counter is active up count. + * @var TIMER_T::PWMMSKEN + * Offset: 0x60 Timer PWM Output Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit + * | | |The PWMx_CH0 output signal will be masked when this bit is enabled + * | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. + * | | |0 = PWMx_CH0 output signal is non-masked. + * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data. + * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit + * | | |The PWMx_CH1 output signal will be masked when this bit is enabled + * | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. + * | | |0 = PWMx_CH1 output signal is non-masked. + * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data. + * @var TIMER_T::PWMMSK + * Offset: 0x64 Timer PWM Output Mask Data Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1). + * | | |0 = Output logic Low to PWMx_CH0. + * | | |1 = Output logic High to PWMx_CH0. + * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1). + * | | |0 = Output logic Low to PWMx_CH1. + * | | |1 = Output logic High to PWMx_CH1. + * @var TIMER_T::PWMBNF + * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit + * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled. + * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled. + * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection + * | | |000 = Noise filter clock is PCLKx. + * | | |001 = Noise filter clock is PCLKx/2. + * | | |010 = Noise filter clock is PCLKx/4. + * | | |011 = Noise filter clock is PCLKx/8. + * | | |100 = Noise filter clock is PCLKx/16. + * | | |101 = Noise filter clock is PCLKx/32. + * | | |110 = Noise filter clock is PCLKx/64. + * | | |111 = Noise filter clock is PCLKx/128. + * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count + * | | |The fields is used to control the active noise filter sample time. + * | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT. + * |[7] |BRKPINV |Brake Pin Detection Control Bit + * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect . + * |[17:16] |BKPINSRC |Brake Pin Source Select + * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin. + * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin. + * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin. + * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin. + * @var TIMER_T::PWMFAILBRK + * Offset: 0x6C Timer PWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by clock fail detection Disabled. + * | | |1 = Brake Function triggered by clock fail detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by BOD event Disabled. + * | | |1 = Brake Function triggered by BOD event Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by core lockup event Disabled. + * | | |1 = Brake Function triggered by core lockup event Enabled. + * @var TIMER_T::PWMBRKCTL + * Offset: 0x70 Timer PWM Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System fail condition as edge-detect brake source Disabled. + * | | |1 = System fail condition as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System fail condition as level-detect brake source Disabled. + * | | |1 = System fail condition as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output. + * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output. + * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMPOLCTL + * Offset: 0x74 Timer PWM Pin Output Polar Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH0 output pin. + * | | |0 = PWMx_CH0 output pin polar inverse Disabled. + * | | |1 = PWMx_CH0 output pin polar inverse Enabled. + * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH1 output pin. + * | | |0 = PWMx_CH1 output pin polar inverse Disabled. + * | | |1 = PWMx_CH1 output pin polar inverse Enabled. + * @var TIMER_T::PWMPOEN + * Offset: 0x78 Timer PWM Pin Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit + * | | |0 = PWMx_CH0 pin at tri-state mode. + * | | |1 = PWMx_CH0 pin in output mode. + * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit + * | | |0 = PWMx_CH1 pin at tri-state mode. + * | | |1 = PWMx_CH1 pin in output mode. + * @var TIMER_T::PWMSWBRK + * Offset: 0x7C Timer PWM Software Trigger Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMINTEN0 + * Offset: 0x80 Timer PWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[1] |PIEN |PWM Period Point Interrupt Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When in up-down count type, period point means the center point of current PWM period. + * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var TIMER_T::PWMINTEN1 + * Offset: 0x84 Timer PWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM edge-detect brake interrupt Disabled. + * | | |1 = PWM edge-detect brake interrupt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM level-detect brake interrupt Disabled. + * | | |1 = PWM level-detect brake interrupt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMINTSTS0 + * Offset: 0x88 Timer PWM Interrupt Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF |PWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |PIF |PWM Period Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. + * | | |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. + * | | |Note2: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMINTSTS1 + * Offset: 0x8C Timer PWM Interrupt Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 edge-detect brake event do not happened. + * | | |1 = PWMx_CH0 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 edge-detect brake event do not happened. + * | | |1 = PWMx_CH1 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 level-detect brake event do not happened. + * | | |1 = PWMx_CH0 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 level-detect brake event do not happened. + * | | |1 = PWMx_CH1 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 edge-detect brake state is released. + * | | |1 = PWMx_CH0 at edge-detect brake state. + * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. + * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 edge-detect brake state is released. + * | | |1 = PWMx_CH1 at edge-detect brake state. + * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. + * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 level-detect brake state is released. + * | | |1 = PWMx_CH0 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 level-detect brake state is released. + * | | |1 = PWMx_CH1 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * @var TIMER_T::PWMEADCTS + * Offset: 0x90 Timer PWM ADC Trigger Source Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger EADC Conversion + * | | |000 = Trigger EADC conversion at zero point (ZIF). + * | | |001 = Trigger EADC conversion at period point (PIF). + * | | |010 = Trigger EADC conversion at zero or period point (ZIF or PIF). + * | | |011 = Trigger EADC conversion at compare up count point (CMPUIF). + * | | |100 = Trigger EADC conversion at compare down count point (CMPDIF). + * | | |Others = Reserved. + * |[7] |TRGEN |PWM Counter Event Trigger EADC Conversion Enable Bit + * | | |0 = PWM counter event trigger EADC conversion Disabled. + * | | |1 = PWM counter event trigger EADC conversion Enabled. + * @var TIMER_T::PWMSCTL + * Offset: 0x94 Timer PWM Synchronous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select + * | | |00 = PWM synchronous function Disabled. + * | | |01 = PWM synchronous counter start function Enabled. + * | | |10 = Reserved. + * | | |11 = PWM synchronous counter clear function Enabled. + * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select + * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN. + * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN. + * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. + * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. + * @var TIMER_T::PWMSTRG + * Offset: 0x98 Timer PWM Synchronous Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only) + * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting. + * | | |Note: This bit is only available in TIMER0 and TIMER2. + * @var TIMER_T::PWMSTATUS + * Offset: 0x9C Timer PWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag + * | | |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF. + * | | |1 = Indicates the PWM counter value has reached its maximum value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag + * | | |0 = PWM counter event trigger EADC start conversion is not occurred. + * | | |1 = PWM counter event trigger EADC start conversion has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMPBUF + * Offset: 0xA0 Timer PWM Period Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) + * | | |Used as PERIOD active register. + * @var TIMER_T::PWMCMPBUF + * Offset: 0xA4 Timer PWM Comparator Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ + __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ + __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ + __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ + __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ + __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ + __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ + __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[7]; + /** @endcond */ + __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ + __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */ + __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */ + __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */ + __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */ + __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */ + __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */ + __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */ + __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */ + __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */ + __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */ + __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */ + __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */ + __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */ + __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */ + __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */ + __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */ + __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */ + __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */ + __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */ + __IO uint32_t PWMEADCTS; /*!< [0x0090] Timer PWM EADC Trigger Source Select Register */ + __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */ + __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */ + __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */ + __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */ + __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */ + +} TIMER_T; + +/** + @addtogroup TIMER_CONST TIMER Bit Field Definition + Constant Definitions for TIMER Controller +@{ */ + +#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ +#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ + +#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ +#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ + +#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ +#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ + +#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ +#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ + +#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ +#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ + +#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ +#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ + +#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ +#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ + +#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ +#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ + +#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ +#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ + +#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ +#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ + +#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ +#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ + +#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ +#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ + +#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ +#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ + +#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ +#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ + +#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ +#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ + +#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ +#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ + +#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ +#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ + +#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ +#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ + +#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ +#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ + +#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ +#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ + +#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ +#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ + +#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ +#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ + +#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ +#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ + +#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ +#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ + +#define TIMER_EXTCTL_ACMPSSEL_Pos (8) /*!< TIMER_T::EXTCTL: ACMPSSEL Position */ +#define TIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos) /*!< TIMER_T::EXTCTL: ACMPSSEL Mask */ + +#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ +#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ + +#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ +#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ + +#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ +#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ + +#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ +#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ + +#define TIMER_TRGCTL_TRGEPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGEPWM Position */ +#define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) /*!< TIMER_T::TRGCTL: TRGEPWM Mask */ + +#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ +#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ + +#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */ +#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */ + +#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ +#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ + +#define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */ +#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */ + +#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ +#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ + +#define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */ +#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */ + +#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ +#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ + +#define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */ +#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */ + +#define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */ +#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */ + +#define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */ +#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */ + +#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ +#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ + +#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ +#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ + +#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */ +#define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */ + +#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ +#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ + +#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ +#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ + +#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ +#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ + +#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ +#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ + +#define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */ +#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */ + +#define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */ +#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */ + +#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */ +#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */ + +#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ +#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ + +#define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */ +#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */ + +#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */ +#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */ + +#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */ +#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */ + +#define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */ +#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */ + +#define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */ +#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */ + +#define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */ +#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */ + +#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */ +#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */ + +#define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */ +#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */ + +#define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */ +#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */ + +#define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */ +#define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */ + +#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */ +#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */ + +#define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */ +#define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */ + +#define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */ +#define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */ + +#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */ +#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */ +#define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */ +#define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */ +#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */ + +#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */ +#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */ +#define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */ +#define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */ +#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */ + +#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */ +#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */ +#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */ +#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */ + +#define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */ +#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */ + +#define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */ +#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */ + +#define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */ +#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */ + +#define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */ +#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */ + +#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */ +#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */ + +#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */ +#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */ + +#define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */ +#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */ + +#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ +#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ + +#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ +#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ + +#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */ +#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */ + +#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */ +#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */ + +#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */ +#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */ + +#define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */ +#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */ + +#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ +#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ + +#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ +#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ + +#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */ +#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */ +#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */ +#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */ +#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */ +#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */ +#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */ +#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */ + +#define TIMER_PWMEADCTS_TRGSEL_Pos (0) /*!< TIMER_T::PWMEADCTS: TRGSEL Position */ +#define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< TIMER_T::PWMEADCTS: TRGSEL Mask */ + +#define TIMER_PWMEADCTS_TRGEN_Pos (7) /*!< TIMER_T::PWMEADCTS: TRGEN Position */ +#define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /*!< TIMER_T::PWMEADCTS: TRGEN Mask */ + +#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */ +#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */ + +#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */ +#define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */ + +#define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */ +#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */ + +#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ +#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ + +#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ +#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ + +#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ +#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ + +#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ +#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ + +/**@}*/ /* TIMER_CONST */ +/**@}*/ /* end of TIMER register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __TIMER_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uart_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uart_reg.h new file mode 100644 index 00000000000..eb09b653177 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uart_reg.h @@ -0,0 +1,1272 @@ +/**************************************************************************//** + * @file uart_reg.h + * @version V1.00 + * @brief UART register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART) + Memory Mapped Structure for UART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UART_T::DAT + * Offset: 0x00 UART Receive/Transmit Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Data Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO + * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. + * | | |Read Operation: + * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. + * |[8] |PARITY |Parity Bit Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, + * | | |the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. + * | | |Read Operation: + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. + * @var UART_T::INTEN + * Offset: 0x04 UART Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit + * | | |0 = Receive data available interrupt Disabled. + * | | |1 = Receive data available interrupt Enabled. + * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit + * | | |0 = Transmit holding register empty interrupt Disabled. + * | | |1 = Transmit holding register empty interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive Line Status interrupt Disabled. + * | | |1 = Receive Line Status interrupt Enabled. + * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit + * | | |0 = Modem status interrupt Disabled. + * | | |1 = Modem status interrupt Enabled. + * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit + * | | |0 = RX time-out interrupt Disabled. + * | | |1 = RX time-out interrupt Enabled. + * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit + * | | |0 = Buffer error interrupt Disabled. + * | | |1 = Buffer error interrupt Enabled. + * |[6] |WKIEN |Wake-up Interrupt Enable Bit + * | | |0 = Wake-up Interrupt Disabled. + * | | |1 = Wake-up Interrupt Enabled. + * |[8] |LINIEN |LIN Bus Interrupt Enable Bit + * | | |0 = LIN bus interrupt Disabled. + * | | |1 = LIN bus interrupt Enabled. + * | | |Note: This bit is used for LIN function mode. + * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit + * | | |0 = Receive Buffer Time-out counter Disabled. + * | | |1 = Receive Buffer Time-out counter Enabled. + * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. + * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). + * |[14] |TXPDMAEN |TX PDMA Enable Bit + * | | |This bit can enable or disable TX PDMA service. + * | | |0 = TX PDMA Disabled. + * | | |1 = TX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA transmit request operation is stop + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. + * |[15] |RXPDMAEN |RX PDMA Enable Bit + * | | |This bit can enable or disable RX PDMA service. + * | | |0 = RX PDMA Disabled. + * | | |1 = RX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. + * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). + * | | |0 = Transmitter empty interrupt Disabled. + * | | |1 = Transmitter empty interrupt Enabled. + * @var UART_T::FIFO + * Offset: 0x08 UART FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RXRST |RX Field Software Reset + * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the RX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. + * |[2] |TXRST |TX Field Software Reset + * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. + * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level + * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). + * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. + * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. + * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. + * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. + * | | |Others = Reserved. + * |[8] |RXOFF |Receiver Disable Bit + * | | |The receiver is disabled or not (set 1 to disable receiver). + * | | |0 = Receiver Enabled. + * | | |1 = Receiver Disabled. + * | | |Note: This bit is used for RS-485 Normal Multi-drop mode + * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. + * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control Use + * | | |0000 = nRTS Trigger Level is 1 byte. + * | | |0001 = nRTS Trigger Level is 4 bytes. + * | | |0010 = nRTS Trigger Level is 8 bytes. + * | | |0011 = nRTS Trigger Level is 14 bytes. + * | | |Others = Reserved. + * | | |Note: This field is used for auto nRTS flow control. + * @var UART_T::LINE + * Offset: 0x0C UART Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WLS |Word Length Selection + * | | |This field sets UART word length. + * | | |00 = 5 bits. + * | | |01 = 6 bits. + * | | |10 = 7 bits. + * | | |11 = 8 bits. + * |[2] |NSB |Number of 'STOP Bit' + * | | |0 = One 'STOP bit' is generated in the transmitted data. + * | | |1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data + * | | |When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data. + * |[3] |PBE |Parity Bit Enable Bit + * | | |0 = Parity bit generated Disabled. + * | | |1 = Parity bit generated Enabled. + * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data. + * |[4] |EPE |Even Parity Enable Bit + * | | |0 = Odd number of logic '1's is transmitted and checked in each word. + * | | |1 = Even number of logic '1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set. + * |[5] |SPE |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0 + * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. + * |[6] |BCB |Break Control Bit + * | | |0 = Break Control Disabled. + * | | |1 = Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[7] |PSS |Parity Bit Source Selection + * | | |The parity bit can be selected to be generated and checked automatically or by software. + * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically. + * | | |1 = Parity bit generated and checked by software. + * | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set. + * | | |Note2: If PSS is 0, the parity bit is transmitted and checked automatically + * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). + * |[8] |TXDINV |TX Data Inverted + * | | |0 = Transmitted data signal inverted Disabled. + * | | |1 = Transmitted data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * |[9] |RXDINV |RX Data Inverted + * | | |0 = Received data signal inverted Disabled. + * | | |1 = Received data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * @var UART_T::MODEM + * Offset: 0x10 UART Modem Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RTS |nRTS (Request-to-send) Signal Control + * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. + * | | |0 = nRTS signal is active. + * | | |1 = nRTS signal is inactive. + * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. + * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. + * |[9] |RTSACTLV |nRTS Pin Active Level + * | | |This bit defines the active level state of nRTS pin output. + * | | |0 = nRTS pin output is high level active. + * | | |1 = nRTS pin output is low level active. (Default) + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * |[13] |RTSSTS |nRTS Pin Status (Read Only) + * | | |This bit mirror from nRTS pin output of voltage logic status. + * | | |0 = nRTS pin output is low level voltage logic state. + * | | |1 = nRTS pin output is high level voltage logic state. + * @var UART_T::MODEMSTS + * Offset: 0x14 UART Modem Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSDETF |Detect nCTS State Change Flag + * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. + * | | |0 = nCTS input has not change state. + * | | |1 = nCTS input has change state. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[4] |CTSSTS |nCTS Pin Status (Read Only) + * | | |This bit mirror from nCTS pin input of voltage logic status. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. + * |[8] |CTSACTLV |nCTS Pin Active Level + * | | |This bit defines the active level state of nCTS pin input. + * | | |0 = nCTS pin input is high level active. + * | | |1 = nCTS pin input is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * @var UART_T::FIFOSTS + * Offset: 0x18 UART FIFO Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOVIF |RX Overflow Error Interrupt Flag + * | | |This bit is set when RX FIFO overflow. + * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. + * | | |0 = RX FIFO is not overflow. + * | | |1 = RX FIFO is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag + * | | |This bit is set to logic '1' when auto-baud rate detect function is finished. + * | | |0 = Auto-baud rate detect function is not finished. + * | | |1 = Auto-baud rate detect function is finished. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag + * | | |This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. + * | | |0 = Auto-baud rate counter is underflow. + * | | |1 = Auto-baud rate counter is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag + * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0'). + * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1'). + * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[4] |PEF |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[5] |FEF |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' + * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[6] |BIF |Break Interrupt Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) + * | | |for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break interrupt is generated. + * | | |1 = Break interrupt is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[13:8] |RXPTR |RX FIFO Pointer (Read Only) + * | | |This field indicates the RX FIFO Buffer Pointer + * | | |When UART receives one byte from external device, RXPTR increases one + * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one. + * | | |The Maximum value shown in RXPTR is 15 + * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0 + * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15 + * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only) + * | | |This bit initiate RX FIFO empty or not. + * | | |0 = RX FIFO is not empty. + * | | |1 = RX FIFO is empty. + * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high + * | | |It will be cleared when UART receives any new data. + * |[15] |RXFULL |Receiver FIFO Full (Read Only) + * | | |This bit initiates RX FIFO full or not. + * | | |0 = RX FIFO is not full. + * | | |1 = RX FIFO is full. + * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[21:16] |TXPTR |TX FIFO Pointer (Read Only) + * | | |This field indicates the TX FIFO Buffer Pointer + * | | |When CPU writes one byte into UART_DAT, TXPTR increases one + * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. + * | | |The Maximum value shown in TXPTR is 15 + * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0 + * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15 + * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only) + * | | |This bit indicates TX FIFO empty or not. + * | | |0 = TX FIFO is not empty. + * | | |1 = TX FIFO is empty. + * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high + * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[23] |TXFULL |Transmitter FIFO Full (Read Only) + * | | |This bit indicates TX FIFO full or not. + * | | |0 = TX FIFO is not full. + * | | |1 = TX FIFO is full. + * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[24] |TXOVIF |TX Overflow Error Interrupt Flag + * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. + * | | |0 = TX FIFO is not overflow. + * | | |1 = TX FIFO is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only) + * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. + * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. + * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[29] |RXIDLE |RX Idle Status (Read Only) + * | | |This bit is set by hardware when RX is idle. + * | | |0 = RX is busy. + * | | |1 = RX is idle. (Default) + * |[31] |TXRXACT |TX and RX Active Status (Read Only) + * | | |This bit indicates TX and RX are active or inactive. + * | | |0 = TX and RX are inactive. + * | | |1 = TX and RX are active. (Default) + * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared + * | | |The UART controller can not transmit or receive data at this moment + * | | |Otherwise this bit is set. + * @var UART_T::INTSTS + * Offset: 0x1C UART Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Available Interrupt Flag + * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set + * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. + * | | |0 = No RDA interrupt flag is generated. + * | | |1 = RDA interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). + * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag + * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register + * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. + * | | |0 = No THRE interrupt flag is generated. + * | | |1 = THRE interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set) + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated. + * | | |1 = RLS interrupt flag is generated. + * | | |Note1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = '1') bit" + * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. + * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1) + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated. + * | | |1 = Modem interrupt flag is generated. + * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). + * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]) + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated. + * | | |1 = RX time-out interrupt flag is generated. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set) + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated. + * | | |1 = Buffer error interrupt flag is generated. + * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). + * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only) + * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1. + * | | |0 = No UART wake-up interrupt flag is generated. + * | | |1 = UART wake-up interrupt flag is generated. + * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. + * |[7] |LINIF |LIN Bus Interrupt Flag + * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] = 1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])) + * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. + * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). + * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) + * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. + * | | |0 = No RDA interrupt is generated. + * | | |1 = RDA interrupt is generated. + * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only) + * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. + * | | |0 = No THRE interrupt is generated. + * | | |1 = THRE interrupt is generated. + * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. + * | | |0 = No RLS interrupt is generated. + * | | |1 = RLS interrupt is generated. + * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 + * | | |0 = No Modem interrupt is generated. + * | | |1 = Modem interrupt is generated. + * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated. + * | | |1 = RX time-out interrupt is generated. + * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. + * | | |0 = No buffer error interrupt is generated. + * | | |1 = Buffer error interrupt is generated. + * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only) + * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. + * | | |0 = No UART wake-up interrupt is generated. + * | | |1 = UART wake-up interrupt is generated. + * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only) + * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. + * | | |0 = No LIN Bus interrupt is generated. + * | | |1 = The LIN Bus interrupt is generated. + * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set) + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated in PDMA mode. + * | | |1 = RLS interrupt flag is generated in PDMA mode. + * | | |Note1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = '1') bit". + * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared + * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1)) + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated in PDMA mode. + * | | |1 = Modem interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). + * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]) + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . + * | | |0 = No RX time-out interrupt flag is generated in PDMA mode. + * | | |1 = RX time-out interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set) + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated in PDMA mode. + * | | |1 = Buffer error interrupt flag is generated in PDMA mode. + * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. + * |[22] |TXENDIF |Transmitter Empty Interrupt Flag + * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set) + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. + * | | |0 = No transmitter empty interrupt flag is generated. + * | | |1 = Transmitter empty interrupt flag is generated. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. + * | | |0 = No RLS interrupt is generated in PDMA mode. + * | | |1 = RLS interrupt is generated in PDMA mode. + * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. + * | | |0 = No Modem interrupt is generated in PDMA mode. + * | | |1 = Modem interrupt is generated in PDMA mode. + * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated in PDMA mode. + * | | |1 = RX time-out interrupt is generated in PDMA mode. + * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. + * | | |0 = No buffer error interrupt is generated in PDMA mode. + * | | |1 = Buffer error interrupt is generated in PDMA mode. + * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only) + * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. + * | | |0 = No Transmitter Empty interrupt is generated. + * | | |1 = Transmitter Empty interrupt is generated. + * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only) + * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. + * | | |0 = No Auto-baud Rate interrupt is generated. + * | | |1 = The Auto-baud Rate interrupt is generated. + * @var UART_T::TOUT + * Offset: 0x20 UART Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TOIC |Time-out Interrupt Comparator + * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]) + * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled + * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]) + * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255 + * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. + * |[15:8] |DLY |TX Delay Time Value + * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit + * | | |The unit is bit time. + * @var UART_T::BAUD + * Offset: 0x24 UART Baud Rate Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BRD |Baud Rate Divider + * | | |The field indicates the baud rate divider + * | | |This filed is used in baud rate calculation + * | | |The detail description is shown in Table 7.15-4. + * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1 + * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2 + * | | |The detail description is shown in Table 7.15-4 + * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0 + * | | |This bit is baud rate mode selection bit 0 + * | | |UART provides three baud rate calculation modes + * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode + * | | |The detail description is shown in Table 7.15-4. + * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1 + * | | |This bit is baud rate mode selection bit 1 + * | | |UART provides three baud rate calculation modes + * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode + * | | |The detail description is shown in Table 7.15-4. + * | | |Note: In IrDA mode must be operated in mode 0. + * @var UART_T::IRDA + * Offset: 0x28 UART IrDA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit + * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) + * | | |1 = IrDA Transmitter Enabled and Receiver Disabled. + * |[5] |TXINV |IrDA Inverse Transmitting Output Signal + * | | |0 = None inverse transmitting signal. (Default). + * | | |1 = Inverse transmitting output signal. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * |[6] |RXINV |IrDA Inverse Receive Input Signal + * | | |0 = None inverse receiving input signal. + * | | |1 = Inverse receiving input signal. (Default) + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * @var UART_T::ALTCTL + * Offset: 0x2C UART Alternate Control/Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRKFL |UART LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: This break field length is BRKFL + 1. + * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13). + * |[6] |LINRXEN |LIN RX Enable Bit + * | | |0 = LIN RX mode Disabled. + * | | |1 = LIN RX mode Enabled. + * |[7] |LINTXEN |LIN TX Break Mode Enable Bit + * | | |0 = LIN TX Break mode Disabled. + * | | |1 = LIN TX Break mode Enabled. + * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically. + * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM) + * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. + * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. + * | | |Note: It cannot be active with RS-485_AAD operation mode. + * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD) + * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. + * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. + * | | |Note: It cannot be active with RS-485_NMM operation mode. + * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD) + * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled. + * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled. + * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. + * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit + * | | |This bit is used to enable RS-485 Address Detection mode. + * | | |0 = Address detection mode Disabled. + * | | |1 = Address detection mode Enabled. + * | | |Note: This bit is used for RS-485 any operation mode. + * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only) + * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. + * | | |0 = No auto-baud rate interrupt flag is generated. + * | | |1 = Auto-baud rate interrupt flag is generated. + * | | |Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]) + * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note : This bit is cleared automatically after auto-baud detection is finished. + * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length + * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. + * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. + * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. + * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. + * | | |Note : The calculation of bit number includes the START bit. + * |[31:24] |ADDRMV |Address Match Value + * | | |This field contains the RS-485 address match values. + * | | |Note: This field is used for RS-485 auto address detection mode. + * @var UART_T::FUNCSEL + * Offset: 0x30 UART Function Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FUNCSEL |Function Select + * | | |00 = UART function. + * | | |01 = LIN function. + * | | |10 = IrDA function. + * | | |11 = RS-485 function. + * |[3] |TXRXDIS |TX and RX Disable Bit + * | | |Setting this bit can disable TX and RX. + * | | |0 = TX and RX Enabled. + * | | |1 = TX and RX Disabled. + * | | |Note: The TX and RX will not disable immediately when this bit is set + * | | |The TX and RX complete current task before disable TX and RX + * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. + * @var UART_T::LINCTL + * Offset: 0x34 UART LIN Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVEN |LIN Slave Mode Enable Bit + * | | |0 = LIN slave mode Disabled. + * | | |1 = LIN slave mode Enabled. + * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit + * | | |0 = LIN slave header detection Disabled. + * | | |1 = LIN slave header detection Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit + * | | |0 = LIN automatic resynchronization Disabled. + * | | |1 = LIN automatic resynchronization Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1). + * | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization). + * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit + * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time). + * | | |1 = UART_BAUD is updated at the next received character + * | | |User must set the bit before checksum reception. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode + * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared) + * | | |Note3: The control and interactions of this field are explained in 7.15.5.9 (Slave mode with automatic resynchronization). + * |[4] |MUTE |LIN Mute Mode Enable Bit + * | | |0 = LIN mute mode Disabled. + * | | |1 = LIN mute mode Enabled. + * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 7.15.5.9 (LIN slave mode). + * |[8] |SENDH |LIN TX Send Header Enable Bit + * | | |The LIN TX header can be break field or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). + * | | |0 = Send LIN TX header Disabled. + * | | |1 = Send LIN TX header Enabled. + * | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). + * | | |Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. + * |[9] |IDPEN |LIN ID Parity Enable Bit + * | | |0 = LIN frame ID parity Disabled. + * | | |1 = LIN frame ID parity Enabled. + * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked. + * | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10 + * |[10] |BRKDETEN |LIN Break Detection Enable Bit + * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field + * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated. + * | | |0 = LIN break detection Disabled . + * | | |1 = LIN break detection Enabled. + * |[11] |LINRXOFF |LIN Receiver Disable Bit + * | | |If the receiver is enabled (LINRXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore. + * | | |0 = LIN receiver Enabled. + * | | |1 = LIN receiver Disabled. + * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01). + * |[12] |BITERREN |Bit Error Detect Enable Bit + * | | |0 = Bit error detection function Disabled. + * | | |1 = Bit error detection function Enabled. + * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[19:16] |BRKFL |LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). + * | | |Note2: This break field length is BRKFL + 1. + * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13). + * |[21:20] |BSL |LIN Break/Sync Delimiter Length + * | | |00 = The LIN break/sync delimiter length is 1-bit time. + * | | |01 = The LIN break/sync delimiter length is 2-bit time. + * | | |10 = The LIN break/sync delimiter length is 3-bit time. + * | | |11 = The LIN break/sync delimiter length is 4-bit time. + * | | |Note: This bit used for LIN master to sending header field. + * |[23:22] |HSEL |LIN Header Select + * | | |00 = The LIN header includes 'break field'. + * | | |01 = The LIN header includes 'break field' and 'sync field'. + * | | |10 = The LIN header includes 'break field', 'sync field' and 'frame ID field'. + * | | |11 = Reserved. + * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1). + * |[31:24] |PID |LIN PID Bits + * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1. + * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. + * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). + * | | |Note2: This field can be used for LIN master mode or slave mode. + * @var UART_T::LINSTS + * Offset: 0x38 UART LIN Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVHDETF |LIN Slave Header Detection Flag + * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |0 = LIN header not detected. + * | | |1 = LIN header detected (break + sync + frame ID). + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. + * |[1] |SLVHEF |LIN Slave Header Error Flag + * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it + * | | |The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', + * | | |'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', + * | | |'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. + * | | |0 = LIN header error not detected. + * | | |1 = LIN header error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and + * | | |enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag + * | | |This bit is set by hardware when receipted frame ID parity is not correct. + * | | |0 = No active. + * | | |1 = Receipted frame ID parity is not correct. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]). + * |[3] |SLVSYNCF |LIN Slave Sync Field + * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode + * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. + * | | |0 = The current character is not at LIN sync state. + * | | |1 = The current character is at LIN sync state. + * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1). + * | | |Note2: This bit can be cleared by writing 1 to it. + * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. + * |[8] |BRKDETF |LIN Break Detection Flag + * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. + * | | |0 = LIN break not detected. + * | | |1 = LIN break detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1). + * |[9] |BITEF |Bit Error Detect Status Flag + * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. + * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * | | |0 = Bit error not detected. + * | | |1 = Bit error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1). + * @var UART_T::BRCOMP + * Offset: 0x3C UART Baud Rate Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |BRCOMP |Baud Rate Compensation Patten + * | | |These 9-bits are used to define the relative bit is compensated or not. + * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. + * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease + * | | |0 = Positive (increase one module clock) compensation for each compensated bit. + * | | |1 = Negative (decrease one module clock) compensation for each compensated bit. + * @var UART_T::WKCTL + * Offset: 0x40 UART Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKCTSEN |nCTS Wake-up Enable Bit + * | | |0 = nCTS Wake-up system function Disabled. + * | | |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external. + * | | |nCTS change will wake-up system from Power-down mode. + * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit + * | | |0 = Incoming data wake-up system function Disabled. + * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,. + * | | |incoming data will wake-up system from Power-down mode. + * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is. + * | | |in Power-down mode, Received Data FIFO reached threshold will wake-up system from + * | | |Power-down mode. + * |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit + * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. + * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in. + * | | |Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. + * | | |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode + * | | |and ADDRDEN (UART_ALTCTL[15]) is set to 1. + * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the. + * | | |system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up + * | | |system from Power-down mode. + * | | |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. + * @var UART_T::WKSTS + * Offset: 0x44 UART Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSWKF |nCTS Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by nCTS wake-up. + * | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[1] |DATWKF |Incoming Data Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by data wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up. + * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold + * | | |wake-up . + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. + * | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. + * | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out + * | | |wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out. + * | | |wake-up. + * | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * @var UART_T::DWKCOMP + * Offset: 0x48 UART Incoming Data Wake-up Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STCOMP |Start Bit Compensation Value + * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode. + * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. + */ + __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */ + __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */ + __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */ + __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */ + __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */ + __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */ + __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */ + __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */ + __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */ + __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */ + __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */ + __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */ + __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */ + __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */ + __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */ + __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */ + __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */ + __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */ + +} UART_T; + +/** + @addtogroup UART_CONST UART Bit Field Definition + Constant Definitions for UART Controller +@{ */ + +#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */ +#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */ + +#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */ +#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */ + +#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */ +#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */ + +#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */ +#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */ + +#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */ +#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */ + +#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */ +#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */ + +#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */ +#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */ + +#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */ +#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */ + +#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */ +#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */ + +#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */ +#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */ + +#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */ +#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */ + +#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */ +#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */ + +#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */ +#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */ + +#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */ +#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */ + +#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */ +#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */ + +#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */ +#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */ + +#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */ +#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */ + +#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */ +#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */ + +#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */ +#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */ + +#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */ +#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */ + +#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */ +#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */ + +#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */ +#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */ + +#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */ +#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */ + +#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */ +#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */ + +#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */ +#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */ + +#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */ +#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */ + +#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */ +#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */ + +#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */ +#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */ + +#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */ +#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */ + +#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */ +#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */ + +#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */ +#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */ + +#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */ +#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */ + +#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */ +#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */ + +#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */ +#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */ + +#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */ +#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */ + +#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */ +#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */ + +#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */ +#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */ + +#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */ +#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */ + +#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */ +#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */ + +#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */ +#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */ + +#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */ +#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */ + +#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */ +#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */ + +#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */ +#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */ + +#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */ +#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */ + +#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */ +#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */ + +#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */ +#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */ + +#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */ +#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */ + +#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */ +#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */ + +#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */ +#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */ + +#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */ +#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */ + +#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */ +#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */ + +#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */ +#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */ + +#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */ +#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */ + +#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */ +#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */ + +#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */ +#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */ + +#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */ +#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */ + +#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */ +#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */ + +#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */ +#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */ + +#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */ +#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */ + +#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */ +#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */ + +#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */ +#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */ + +#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */ +#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */ + +#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */ +#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */ + +#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */ +#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */ + +#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */ +#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */ + +#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */ +#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */ + +#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */ +#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */ + +#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */ +#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */ + +#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */ +#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */ + +#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */ +#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */ + +#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */ +#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */ + +#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */ +#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */ + +#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */ +#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */ + +#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */ +#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */ + +#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */ +#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */ + +#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */ +#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */ + +#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */ +#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */ + +#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */ +#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */ + +#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */ +#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */ + +#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */ +#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */ + +#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */ +#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */ + +#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */ +#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */ + +#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */ +#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */ + +#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */ +#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */ + +#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */ +#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */ + +#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */ +#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */ + +#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */ +#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */ + +#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */ +#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */ + +#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */ +#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */ + +#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */ +#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */ + +#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */ +#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */ + +#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */ +#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */ + +#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */ +#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */ + +#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */ +#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */ + +#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */ +#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */ + +#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */ +#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */ + +#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */ +#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */ + +#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */ +#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */ + +#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */ +#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */ + +#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */ +#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */ + +#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */ +#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */ + +#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */ +#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */ + +#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */ +#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */ + +#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */ +#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */ + +#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */ +#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */ + +#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */ +#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */ + +#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */ +#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */ + +#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */ +#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */ + +#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */ +#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */ + +#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */ +#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */ + +#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */ +#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */ + +#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */ +#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */ + +#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */ +#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */ + +#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */ +#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */ + +#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */ +#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */ + +#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */ +#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */ + +#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */ +#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */ + +#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */ +#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */ + +#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */ +#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */ + +#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */ +#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */ + +#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */ +#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */ + +#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */ +#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */ + +#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */ +#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */ + +#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */ +#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */ + +#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */ +#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */ + +#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */ +#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */ + +#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */ +#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */ + +#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */ +#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */ + +#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */ +#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */ + +#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */ +#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */ + +#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */ +#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */ + +#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */ +#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */ + +#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */ +#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */ + +#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */ +#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */ + +#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */ +#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */ + +#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */ +#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */ + +/**@}*/ /* UART_CONST */ +/**@}*/ /* end of UART register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UART_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ui2c_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ui2c_reg.h new file mode 100644 index 00000000000..6fa86a0d301 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/ui2c_reg.h @@ -0,0 +1,582 @@ +/**************************************************************************//** + * @file ui2c_reg.h + * @version V1.00 + * @brief UI2C register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UI2C_REG_H__ +#define __UI2C_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UI2C I2C Mode of USCI Controller(UI2C) + Memory Mapped Structure for UI2C Controller +@{ */ + +typedef struct +{ + + + /** + * @var UI2C_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UI2C_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UI2C_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits + * | | |And in I2C protocol, the length fixed as 8 bits. + * @var UI2C_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UI2C_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. + * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]). + * @var UI2C_T::DEVADDR0 + * Offset: 0x44 USCI Device Address Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. + * | | |Note 2: When software set 10'h000, the address can not be used. + * @var UI2C_T::DEVADDR1 + * Offset: 0x48 USCI Device Address Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note 1: The DEVADDR [9:7] must be set 3'000 when I2C operating in 7-bit address mode. + * | | |Note 2: When software set 10'h000, the address can not be used. + * @var UI2C_T::ADDRMSK0 + * Offset: 0x4C USCI Device Address Mask Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var UI2C_T::ADDRMSK1 + * Offset: 0x50 USCI Device Address Mask Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var UI2C_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * @var UI2C_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UI2C_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCFUNC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[1] |AA |Assert Acknowledge Control + * | | |When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. + * |[2] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically + * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (USCI_PROTSTS.ERRIF = 1). + * |[3] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[4] |ADDR10EN |Address 10-bit Function Enable Bit + * | | |0 = Address match 10 bit function is disabled. + * | | |1 = Address match 10 bit function is enabled. + * |[5] |PTRG |I2C Protocol Trigger (Write Only) + * | | |When a new state is present in the USCI_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested + * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. + * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead. + * | | |1 = I2C's stretch active. + * |[8] |SCLOUTEN |SCL Output Enable Bit + * | | |This bit enables monitor pulling SCL to low + * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. + * | | |0 = SCL output will be forced high due to open drain mechanism. + * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt. + * |[9] |MONEN |Monitor Mode Enable Bit + * | | |This bit enables monitor mode + * | | |In monitor mode the SDA output will be put in high impedance mode + * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. + * | | |0 = The monitor mode is disabled. + * | | |1 = The monitor mode is enabled. + * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. + * |[25:16] |TOCNT |Time-out Clock Cycle + * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) when each interrupt flags are clear + * | | |The time-out is enable when TOCNT bigger than 0. + * | | |Note: The TMCNTSRC (USCI_BRGEN [5]) must be set zero on I2C mode. + * |[31] |PROTEN |I2C Protocol Enable Bit + * | | |0 = I2C Protocol disable. + * | | |1 = I2C Protocol enable. + * @var UI2C_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIEN |Time-out Interrupt Enable Control + * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event. + * | | |0 = The time-out interrupt is disabled. + * | | |1 = The time-out interrupt is enabled. + * |[1] |STARIEN |Start Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a start condition is detected. + * | | |0 = The start condition interrupt is disabled. + * | | |1 = The start condition interrupt is enabled. + * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected. + * | | |0 = The stop condition interrupt is disabled. + * | | |1 = The stop condition interrupt is enabled. + * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. + * | | |0 = The non - acknowledge interrupt is disabled. + * | | |1 = The non - acknowledge interrupt is enabled. + * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. + * | | |0 = The arbitration lost interrupt is disabled. + * | | |1 = The arbitration lost interrupt is enabled. + * |[5] |ERRIEN |Error Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (USCI_PROTSTS [16])). + * | | |0 = The error interrupt is disabled. + * | | |1 = The error interrupt is enabled. + * |[6] |ACKIEN |Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. + * | | |0 = The acknowledge interrupt is disabled. + * | | |1 = The acknowledge interrupt is enabled. + * @var UI2C_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5] |TOIF |Time-out Interrupt Flag + * | | |0 = A time-out interrupt status has not occurred. + * | | |1 = A time-out interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit + * |[6] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[8] |STARIF |Start Condition Received Interrupt Flag + * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode + * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode. + * | | |A protocol interrupt can be generated if USCI_PROTCTL.STARIEN = 1. + * | | |0 = A start condition has not yet been detected. + * | | |1 = A start condition has been detected. + * | | |It is cleared by software writing one into this bit + * |[9] |STORIF |Stop Condition Received Interrupt Flag + * | | |This bit indicates that a stop condition has been detected on the I2C bus lines + * | | |A protocol interrupt can be generated if USCI_PROTCTL.STORIEN = 1. + * | | |0 = A stop condition has not yet been detected. + * | | |1 = A stop condition has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave RX mode. + * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag + * | | |This bit indicates that a non - acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if USCI_PROTCTL.NACKIEN = 1. + * | | |0 = A non - acknowledge has not been received. + * | | |1 = A non - acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag + * | | |This bit indicates that an arbitration has been lost + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ARBLOIEN = 1. + * | | |0 = An arbitration has not been lost. + * | | |1 = An arbitration has been lost. + * | | |It is cleared by software writing one into this bit + * |[12] |ERRIF |Error Interrupt Flag + * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ERRIEN = 1. + * | | |0 = An I2C error has not been detected. + * | | |1 = An I2C error has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode. + * |[13] |ACKIF |Acknowledge Received Interrupt Flag + * | | |This bit indicates that an acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ACKIEN = 1. + * | | |0 = An acknowledge has not been received. + * | | |1 = An acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[14] |SLASEL |Slave Select Status + * | | |This bit indicates that this device has been selected as slave. + * | | |0 = The device is not selected as slave. + * | | |1 = The device is selected as slave. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[15] |SLAREAD |Slave Read Request Status + * | | |This bit indicates that a slave read request has been detected. + * | | |0 = A slave R/W bit is 1 has not been detected. + * | | |1 = A slave R/W bit is 1 has been detected. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release when WKUPIF is set. + * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * |[18] |BUSHANG |Bus Hang-up + * | | |This bit indicates bus hang-up status + * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK + * | | |The hang-up counter will count to overflow and set this bit when SDA is low + * | | |The counter will be reset by falling edge of SCL signal. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is hang-up status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * |[19] |ERRARBLO |Error Arbitration Lost + * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor + * | | |The I2C can send start condition when ERRARBLO is set + * | | |Thus this bit doesn't be cared on slave mode. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is error arbitration lost status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * @var UI2C_T::ADMAT + * Offset: 0x88 I2C Slave Match Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |USCI Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |USCI Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * @var UI2C_T::TMCTL + * Offset: 0x8C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in + * | | |transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */ + __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */ + __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */ + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */ + __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */ + +} UI2C_T; + +/** + @addtogroup UI2C_CONST UI2C Bit Field Definition + Constant Definitions for UI2C Controller +@{ */ + +#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */ +#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */ + +#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */ +#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */ + +#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */ +#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */ + +#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */ +#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */ + +#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */ +#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */ + +#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */ +#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */ + +#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */ +#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */ + +#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */ +#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */ + +#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */ +#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */ + +#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */ +#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */ + +#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */ +#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */ + +#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */ +#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */ + +#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */ +#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */ + +#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */ +#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */ + +#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */ +#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */ + +#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */ +#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */ +#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */ +#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */ + +#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */ +#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */ + +#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */ +#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */ + +#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */ +#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */ + +#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */ +#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */ + +#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */ +#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */ + +#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */ +#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */ + +#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */ +#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */ + +#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */ +#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */ + +#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */ +#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */ + +#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */ +#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */ + +#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */ +#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */ + +#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */ +#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */ + +#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */ +#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */ + +#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */ +#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */ + +#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */ +#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */ + +#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */ +#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */ + +#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */ +#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */ + +#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */ +#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */ + +#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */ +#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */ + +#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */ +#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */ + +#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */ +#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */ + +#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */ +#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */ + +#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */ +#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */ + +#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */ +#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */ + +#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */ +#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */ + +#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */ +#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */ + +#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */ +#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */ + +#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */ +#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */ + +#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */ +#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */ + +#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */ +#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */ + +#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */ +#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */ + +#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */ +#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */ + +#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */ +#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */ + +#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */ +#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */ + +#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */ +#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */ + +#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */ +#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */ + +#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */ +#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */ + +/**@}*/ /* UI2C_CONST */ +/**@}*/ /* end of UI2C register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UI2C_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbd_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbd_reg.h new file mode 100644 index 00000000000..6fb5bd1aa9f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbd_reg.h @@ -0,0 +1,633 @@ +/**************************************************************************//** + * @file usbd_reg.h + * @version V1.00 + * @brief USBD register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBD_REG_H__ +#define __USBD_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USBD USB Device Controller(USBD) + Memory Mapped Structure for USBD Controller +@{ */ + +typedef struct +{ + + /** + * @var USBD_EP_T::BUFSEG + * Offset: 0x000 Endpoint n Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |BUFSEG |Endpoint Buffer Segmentation + * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is + * | | |USBD_SRAM address + { BUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Refer to the section 7.29.5.7 for the endpoint SRAM structure and its description. + * @var USBD_EP_T::MXPLD + * Offset: 0x004 Endpoint n Maximal Payload Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |MXPLD |Maximal Payload + * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) + * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. + * | | |(1) When the register is written by CPU, + * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. + * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. + * | | |(2) When the register is read by CPU, + * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host + * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. + * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. + * @var USBD_EP_T::CFG + * Offset: 0x008 Endpoint n Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |Endpoint Number + * | | |These bits are used to define the endpoint number of the current endpoint + * |[4] |ISOCH |Isochronous Endpoint + * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. + * | | |0 = No Isochronous endpoint. + * | | |1 = Isochronous endpoint. + * |[6:5] |STATE |Endpoint STATE + * | | |00 = Endpoint is Disabled. + * | | |01 = Out endpoint. + * | | |10 = IN endpoint. + * | | |11 = Undefined. + * |[7] |DSQSYNC |Data Sequence Synchronization + * | | |0 = DATA0 PID. + * | | |1 = DATA1 PID. + * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction + * | | |hardware will toggle automatically in IN token base on the bit. + * |[9] |CSTALL |Clear STALL Response + * | | |0 = Disable the device to clear the STALL handshake in setup stage. + * | | |1 = Clear the device to response STALL handshake in setup stage. + * @var USBD_EP_T::CFGP + * Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CLRRDY |Clear Ready + * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data + * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0. + * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. + * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. + * | | |This bit is write 1 only and is always 0 when it is read back. + * |[1] |SSTALL |Set STALL + * | | |0 = Disable the device to response STALL. + * | | |1 = Set the device to respond STALL automatically. + */ + __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint n Buffer Segmentation Register */ + __IO uint32_t MXPLD; /*!< [0x0004] Endpoint n Maximal Payload Register */ + __IO uint32_t CFG; /*!< [0x0008] Endpoint n Configuration Register */ + __IO uint32_t CFGP; /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register */ + +} USBD_EP_T; + +typedef struct +{ + + + /** + * @var USBD_T::INTEN + * Offset: 0x00 USB Device Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIEN |Bus Event Interrupt Enable Bit + * | | |0 = BUS event interrupt Disabled. + * | | |1 = BUS event interrupt Enabled. + * |[1] |USBIEN |USB Event Interrupt Enable Bit + * | | |0 = USB event interrupt Disabled. + * | | |1 = USB event interrupt Enabled. + * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit + * | | |0 = VBUS detection Interrupt Disabled. + * | | |1 = VBUS detection Interrupt Enabled. + * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit + * | | |0 = No-event-wake-up Interrupt Disabled. + * | | |1 = No-event-wake-up Interrupt Enabled. + * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit + * | | |0 = SOF Interrupt Disabled. + * | | |1 = SOF Interrupt Enabled. + * |[8] |WKEN |Wake-up Function Enable Bit + * | | |0 = USB wake-up function Disabled. + * | | |1 = USB wake-up function Enabled. + * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token + * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted. + * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token. + * @var USBD_T::INTSTS + * Offset: 0x04 USB Device Interrupt Event Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIF |BUS Interrupt Status + * | | |The BUS event means that there is one of the suspense or the resume function in the bus. + * | | |0 = No BUS event occurred. + * | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0]. + * |[1] |USBIF |USB Event Interrupt Status + * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. + * | | |0 = No USB event occurred. + * | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]). + * |[2] |VBDETIF |VBUS Detection Interrupt Status + * | | |0 = There is not attached/detached event in the USB. + * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2]. + * |[3] |NEVWKIF |No-event-wake-up Interrupt Status + * | | |0 = NEVWK event does not occur. + * | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3]. + * |[4] |SOFIF |Start of Frame Interrupt Status + * | | |0 = SOF event does not occur. + * | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4]. + * |[16] |EPEVT0 |Endpoint 0's USB Event Status + * | | |0 = No event occurred in endpoint 0. + * | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1]. + * |[17] |EPEVT1 |Endpoint 1's USB Event Status + * | | |0 = No event occurred in endpoint 1. + * | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1]. + * |[18] |EPEVT2 |Endpoint 2's USB Event Status + * | | |0 = No event occurred in endpoint 2. + * | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1]. + * |[19] |EPEVT3 |Endpoint 3's USB Event Status + * | | |0 = No event occurred in endpoint 3. + * | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1]. + * |[20] |EPEVT4 |Endpoint 4's USB Event Status + * | | |0 = No event occurred in endpoint 4. + * | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1]. + * |[21] |EPEVT5 |Endpoint 5's USB Event Status + * | | |0 = No event occurred in endpoint 5. + * | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1]. + * |[22] |EPEVT6 |Endpoint 6's USB Event Status + * | | |0 = No event occurred in endpoint 6. + * | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1]. + * |[23] |EPEVT7 |Endpoint 7's USB Event Status + * | | |0 = No event occurred in endpoint 7. + * | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1]. + * |[24] |EPEVT8 |Endpoint 8's USB Event Status + * | | |0 = No event occurred in endpoint 8. + * | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1]. + * |[25] |EPEVT9 |Endpoint 9's USB Event Status + * | | |0 = No event occurred in endpoint 9. + * | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1]. + * |[26] |EPEVT10 |Endpoint 10's USB Event Status + * | | |0 = No event occurred in endpoint 10. + * | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1]. + * |[27] |EPEVT11 |Endpoint 11's USB Event Status + * | | |0 = No event occurred in endpoint 11. + * | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1]. + * |[31] |SETUP |Setup Event Status + * | | |0 = No Setup event. + * | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31]. + * @var USBD_T::FADDR + * Offset: 0x08 USB Device Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Device Function Address + * @var USBD_T::EPSTS + * Offset: 0x0C USB Device Endpoint Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |OV |Overrun + * | | |It indicates that the received data is over the maximum payload number or not. + * | | |0 = No overrun. + * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes. + * @var USBD_T::ATTR + * Offset: 0x10 USB Device Bus Status and Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBRST |USB Reset Status + * | | |0 = Bus no reset. + * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us. + * | | |Note: This bit is read only. + * |[1] |SUSPEND |Suspend Status + * | | |0 = Bus no suspend. + * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping. + * | | |Note: This bit is read only. + * |[2] |RESUME |Resume Status + * | | |0 = No bus resume. + * | | |1 = Resume from suspend. + * | | |Note: This bit is read only. + * |[3] |TOUT |Time-out Status + * | | |0 = No time-out. + * | | |1 = No Bus response more than 18 bits time. + * | | |Note: This bit is read only. + * |[4] |PHYEN |PHY Transceiver Function Enable Bit + * | | |0 = PHY transceiver function Disabled. + * | | |1 = PHY transceiver function Enabled. + * |[5] |RWAKEUP |Remote Wake-up + * | | |0 = Release the USB bus from K state. + * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up. + * |[7] |USBEN |USB Controller Enable Bit + * | | |0 = USB Controller Disabled. + * | | |1 = USB Controller Enabled. + * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit + * | | |0 = Pull-up resistor in USB_D+ bus Disabled. + * | | |1 = Pull-up resistor in USB_D+ bus Active. + * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection + * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. + * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. + * |[11] |LPMACK |LPM Token Acknowledge Enable Bit + * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively. + * | | |0= the valid LPM Token will be NYET. + * | | |1= the valid LPM Token will be ACK. + * |[12] |L1SUSPEND |LPM L1 Suspend + * | | |0 = Bus no L1 state suspend. + * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. + * | | |Note: This bit is read only. + * |[13] |L1RESUME |LPM L1 Resume + * | | |0 = Bus no LPM L1 state resume. + * | | |1 = LPM L1 state Resume from LPM L1 state suspend. + * | | |Note: This bit is read only. + * @var USBD_T::VBUSDET + * Offset: 0x14 USB Device VBUS Detection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDET |Device VBUS Detection + * | | |0 = Controller is not attached to the USB host. + * | | |1 = Controller is attached to the USB host. + * @var USBD_T::STBUFSEG + * Offset: 0x18 SETUP Token Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation + * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is + * | | |USBD_SRAM address + {STBUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Note: It is used for SETUP token only. + * @var USBD_T::EPSTS0 + * Offset: 0x20 USB Device Endpoint Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[03:00] |EPSTS0 |Endpoint 0 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[07:04] |EPSTS1 |Endpoint 1 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:08] |EPSTS2 |Endpoint 2 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS3 |Endpoint 3 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[19:16] |EPSTS4 |Endpoint 4 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[23:20] |EPSTS5 |Endpoint 5 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[27:24] |EPSTS6 |Endpoint 6 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[31:28] |EPSTS7 |Endpoint 7 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::EPSTS1 + * Offset: 0x24 USB Device Endpoint Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPSTS8 |Endpoint 8 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[7:4] |EPSTS9 |Endpoint 9 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:8] |EPSTS10 |Endpoint 10 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS11 |Endpoint 11 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::LPMATTR + * Offset: 0x88 USB LPM Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LPMLINKSTS|LPM Link State + * | | |These bits contain the bLinkState received with last ACK LPM Token + * |[7:4] |LPMBESL |LPM Best Effort Service Latency + * | | |These bits contain the BESL value received with last ACK LPM Token + * |[8] |LPMRWAKUP |LPM Remote Wakeup + * | | |This bit contains the bRemoteWake value received with last ACK LPM Token + * @var USBD_T::FN + * Offset: 0x8C USB Frame number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FN |Frame Number + * | | |These bits contain the 11-bits frame number in the last received SOF packet. + * @var USBD_T::SE0 + * Offset: 0x90 USB Device Drive SE0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SE0 |Drive Single Ended Zero in USB Bus + * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. + * | | |0 = Normal operation. + * | | |1 = Force USB PHY transceiver to drive SE0. + */ + + __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */ + __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */ + __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */ + __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */ + __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */ + __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */ + __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[24]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */ + __I uint32_t FN; /*!< [0x008c] USB Frame number Register */ + __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[283]; + /// @endcond //HIDDEN_SYMBOLS + USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */ + +} USBD_T; + + +/** + @addtogroup USBD_CONST USBD Bit Field Definition + Constant Definitions for USBD Controller +@{ */ + +#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */ +#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */ + +#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */ +#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */ + +#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */ +#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */ + +#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */ +#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */ + +#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */ +#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */ + +#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */ +#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */ + +#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */ +#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */ + +#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */ +#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */ + +#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */ +#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */ + +#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */ +#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */ + +#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */ +#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */ + +#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */ +#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */ + +#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */ +#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */ + +#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */ +#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */ + +#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */ +#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */ + +#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */ +#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */ + +#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */ +#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */ + +#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */ +#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */ + +#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */ +#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */ + +#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */ +#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */ + +#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */ +#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */ + +#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */ +#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */ + +#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */ +#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */ + +#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */ +#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */ + +#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */ +#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ + +#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */ +#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ + +#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */ +#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */ + +#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */ +#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ + +#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */ +#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ + +#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */ +#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ + +#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */ +#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */ + +#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */ +#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */ + +#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */ +#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ + +#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */ +#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */ + +#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */ +#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */ + +#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */ +#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ + +#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */ +#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */ + +#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */ +#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */ + +#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */ +#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */ + +#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */ +#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */ + +#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */ +#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ + +#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */ +#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */ + +#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */ +#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */ + +#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */ +#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */ + +#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */ +#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */ + +#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */ +#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */ + +#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */ +#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */ + +#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */ +#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */ + +#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */ +#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */ + +#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */ +#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */ + +#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */ +#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */ + +#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */ +#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */ + +#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */ +#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */ + +#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ +#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ + +#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */ +#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ + +#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */ +#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */ + +#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */ +#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ + +#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */ +#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ + +#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */ +#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */ + +#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */ +#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ + +#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */ +#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ + +#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */ +#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ + +/**@}*/ /* USBD_CONST */ +/**@}*/ /* end of USBD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USBD_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbh_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbh_reg.h new file mode 100644 index 00000000000..cc299084aaf --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/usbh_reg.h @@ -0,0 +1,796 @@ +/**************************************************************************//** + * @file usbh_reg.h + * @version V1.00 + * @brief USBH register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBH_REG_H__ +#define __USBH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USBH USB Host Controller(USBH) + Memory Mapped Structure for USBH Controller +@{ */ + +typedef struct +{ + + /** + * @var USBH_T::HcRevision + * Offset: 0x00 Host Controller Revision Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REV |Revision Number + * | | |Indicates the Open HCI Specification revision number implemented by the Hardware + * | | |Host Controller supports 1.1 specification. + * | | |(X.Y = XYh). + * @var USBH_T::HcControl + * Offset: 0x04 Host Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CBSR |Control Bulk Service Ratio + * | | |This specifies the service ratio between Control and Bulk EDs + * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs + * | | |The internal count will be retained when crossing the frame boundary + * | | |In case of reset, HCD is responsible for restoring this + * | | |Value. + * | | |00 = Number of Control EDs over Bulk EDs served is 1:1. + * | | |01 = Number of Control EDs over Bulk EDs served is 2:1. + * | | |10 = Number of Control EDs over Bulk EDs served is 3:1. + * | | |11 = Number of Control EDs over Bulk EDs served is 4:1. + * |[2] |PLE |Periodic List Enable Bit + * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list + * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame. + * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled. + * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. + * |[3] |IE |Isochronous List Enable Bit + * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list + * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. + * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too. + * |[4] |CLE |Control List Enable Bit + * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Control list in the next frame Enabled. + * |[5] |BLE |Bulk List Enable Bit + * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Bulk list in the next frame Enabled. + * |[7:6] |HCFS |Host Controller Functional State + * | | |This field sets the Host Controller state + * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port + * | | |States are: + * | | |00 = USBSUSPEND. + * | | |01 = USBOPERATIONAL. + * | | |10 = USBRESUME. + * | | |11 = USBRESET. + * @var USBH_T::HcCommandStatus + * Offset: 0x08 Host Controller Command Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HCR |Host Controller Reset + * | | |This bit is set to initiate the software reset of Host Controller + * | | |This bit is cleared by the Host Controller, upon completed of the reset operation. + * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. + * | | |0 = Host Controller is not in software reset state. + * | | |1 = Host Controller is in software reset state. + * |[1] |CLF |Control List Filled + * | | |Set high to indicate there is an active TD on the Control List + * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. + * | | |0 = No active TD found or Host Controller begins to process the head of the Control list. + * | | |1 = An active TD added or found on the Control list. + * |[2] |BLF |Bulk List Filled + * | | |Set high to indicate there is an active TD on the Bulk list + * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. + * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list. + * | | |1 = An active TD added or found on the Bulk list. + * |[17:16] |SOC |Schedule Overrun Count + * | | |These bits are incremented on each scheduling overrun error + * | | |It is initialized to 00b and wraps around at 11b + * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. + * @var USBH_T::HcInterruptStatus + * Offset: 0x0C Host Controller Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun + * | | |Set when the List Processor determines a Schedule Overrun has occurred. + * | | |0 = Schedule Overrun didn't occur. + * | | |1 = Schedule Overrun has occurred. + * |[1] |WDH |Write Back Done Head + * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead + * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared. + * | | |0 =.Host Controller didn't update HccaDoneHead. + * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead. + * |[2] |SF |Start of Frame + * | | |Set when the Frame Management functional block signals a 'Start of Frame' event + * | | |Host Control generates a SOF token at the same time. + * | | |0 =.Not the start of a frame. + * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token. + * |[3] |RD |Resume Detected + * | | |Set when Host Controller detects resume signaling on a downstream port. + * | | |0 = No resume signaling detected on a downstream port. + * | | |1 = Resume signaling detected on a downstream port. + * |[5] |FNO |Frame Number Overflow + * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * | | |0 = The bit 15 of Frame Number didn't change. + * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * |[6] |RHSC |Root Hub Status Change + * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed. + * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change. + * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed. + * @var USBH_T::HcInterruptEnable + * Offset: 0x10 Host Controller Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Enable Bit + * | | |This bit is a global interrupt enable + * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcInterruptDisable + * Offset: 0x14 Host Controller Interrupt Disable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Disable Bit + * | | |Global interrupt disable. Writing '1' to disable all interrupts. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcHCCA + * Offset: 0x18 Host Controller Communication Area Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:8] |HCCA |Host Controller Communication Area + * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA). + * @var USBH_T::HcPeriodCurrentED + * Offset: 0x1C Host Controller Period Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |PCED |Periodic Current ED + * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor. + * @var USBH_T::HcControlHeadED + * Offset: 0x20 Host Controller Control Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CHED |Control Head ED + * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list. + * @var USBH_T::HcControlCurrentED + * Offset: 0x24 Host Controller Control Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CCED |Control Current Head ED + * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list. + * @var USBH_T::HcBulkHeadED + * Offset: 0x28 Host Controller Bulk Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BHED |Bulk Head ED + * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. + * @var USBH_T::HcBulkCurrentED + * Offset: 0x2C Host Controller Bulk Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BCED |Bulk Current Head ED + * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list. + * @var USBH_T::HcDoneHead + * Offset: 0x30 Host Controller Done Head Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |DH |Done Head + * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. + * @var USBH_T::HcFmInterval + * Offset: 0x34 Host Controller Frame Interval Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Interval + * | | |This field specifies the length of a frame as (bit times - 1) + * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here. + * |[30:16] |FSMPS |FS Largest Data Packet + * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. + * |[31] |FIT |Frame Interval Toggle + * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). + * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]). + * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]). + * @var USBH_T::HcFmRemaining + * Offset: 0x38 Host Controller Frame Remaining Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FR |Frame Remaining + * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period + * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval + * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. + * |[31] |FRT |Frame Remaining Toggle + * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. + * @var USBH_T::HcFmNumber + * Offset: 0x3C Host Controller Frame Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FN |Frame Number + * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]) + * | | |The count rolls over from 'FFFFh' to '0h.' + * @var USBH_T::HcPeriodicStart + * Offset: 0x40 Host Controller Periodic Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |PS |Periodic Start + * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. + * @var USBH_T::HcLSThreshold + * Offset: 0x44 Host Controller Low-speed Threshold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |LST |Low-speed Threshold + * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction + * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field + * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead. + * @var USBH_T::HcRhDescriptorA + * Offset: 0x48 Host Controller Root Hub Descriptor A Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |NDP |Number Downstream Ports + * | | |USB host control supports two downstream ports and only one port is available in this series of chip. + * |[8] |PSM |Power Switching Mode + * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled. + * | | |0 = Global Switching. + * | | |1 = Individual Switching. + * |[11] |OCPM |over Current Protection Mode + * | | |This bit describes how the over current status for the Root Hub ports reported + * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. + * | | |0 = Global Over current. + * | | |1 = Individual Over current. + * |[12] |NOCP |No over Current Protection + * | | |This bit describes how the over current status for the Root Hub ports reported. + * | | |0 = Over current status is reported. + * | | |1 = Over current status is not reported. + * @var USBH_T::HcRhDescriptorB + * Offset: 0x4C Host Controller Root Hub Descriptor B Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |PPCM |Port Power Control Mask + * | | |Global power switching + * | | |This field is only valid if PowerSwitchingMode is set (individual port switching) + * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower) + * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower). + * | | |0 = Port power controlled by global power switching. + * | | |1 = Port power controlled by port power switching. + * | | |Note: PPCM[15:2] and PPCM[0] are reserved. + * @var USBH_T::HcRhStatus + * Offset: 0x50 Host Controller Root Hub Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LPS |Clear Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear global power. + * |[1] |OCI |over Current Indicator + * | | |This bit reflects the state of the over current status pin + * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared. + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[15] |DRWE |Device Remote Wakeup Enable Bit + * | | |This bit controls if port's Connect Status Change as a remote wake-up event. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * | | |Read Operation: + * | | |0 = Connect Status Change as a remote wake-up event Disabled. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * |[16] |LPSC |Set Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set global power. + * |[17] |OCIC |over Current Indicator Change + * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]). + * | | |Write 1 to clear this bit to zero. + * | | |0 = OCI (HcRhStatus[1]) didn't change. + * | | |1 = OCI (HcRhStatus[1]) change. + * |[31] |CRWE |Clear Remote Wake-up Enable Bit + * | | |This bit is use to clear DRWE (HcRhStatus[15]). + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear DRWE (HcRhStatus[15]). + * @var USBH_T::HcRhPortStatus[2] + * Offset: 0x54 Host Controller Root Hub Port Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write) + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port enable. + * | | |Read Operation: + * | | |0 = No device connected. + * | | |1 = Device connected. + * |[1] |PES |Port Enable Status + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port enable. + * | | |Read Operation: + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[2] |PSS |Port Suspend Status + * | | |This bit indicates the port is suspended + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port suspend. + * | | |Read Operation: + * | | |0 = Port is not suspended. + * | | |1 = Port is selectively suspended. + * |[3] |POCI |Port over Current Indicator (Read) or Clear Port Suspend (Write) + * | | |This bit reflects the state of the over current status pin dedicated to this port + * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set. + * | | |This bit is also used to initiate the selective result sequence for the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port suspend. + * | | |Read Operation: + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[4] |PRS |Port Reset Status + * | | |This bit reflects the reset state of the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port reset. + * | | |Read Operation + * | | |0 = Port reset signal is not active. + * | | |1 = Port reset signal is active. + * |[8] |PPS |Port Power Status + * | | |This bit reflects the power state of the port regardless of the power switching mode. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Port Power Enabled. + * | | |Read Operation: + * | | |0 = Port power is Disabled. + * | | |1 = Port power is Enabled. + * |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write) + * | | |This bit defines the speed (and bud idle) of the attached device + * | | |It is only valid when CCS (HcRhPortStatus1[0]) is set. + * | | |This bit is also used to clear port power. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear PPS (HcRhPortStatus1[8]). + * | | |Read Operation: + * | | |0 = Full Speed device. + * | | |1 = Low-speed device. + * |[16] |CSC |Connect Status Change + * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed). + * | | |Write 1 to clear this bit to zero. + * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change). + * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed). + * |[17] |PESC |Port Enable Status Change + * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event. + * | | |Write 1 to clear this bit to zero. + * | | |0 = PES (HcRhPortStatus1[1]) didn't change. + * | | |1 = PES (HcRhPortStatus1[1]) changed. + * |[18] |PSSC |Port Suspend Status Change + * | | |This bit indicates the completion of the selective resume sequence for the port. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port resume is not completed. + * | | |1 = Port resume completed. + * |[19] |OCIC |Port over Current Indicator Change + * | | |This bit is set when POCI (HcRhPortStatus1[3]) changes. + * | | |Write 1 to clear this bit to zero. + * | | |0 = POCI (HcRhPortStatus1[3]) didn't change. + * | | |1 = POCI (HcRhPortStatus1[3]) changes. + * |[20] |PRSC |Port Reset Status Change + * | | |This bit indicates that the port reset signal has completed. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port reset is not complete. + * | | |1 = Port reset is complete. + * @var USBH_T::HcPhyControl + * Offset: 0x200 Host Controller PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27] |STBYEN |USB Transceiver Standby Enable Bit + * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption. + * | | |0 = The USB transceiver would never enter the standby mode. + * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive). + * @var USBH_T::HcMiscControl + * Offset: 0x204 Host Controller Miscellaneous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABORT |AHB Bus ERROR Response + * | | |This bit indicates there is an ERROR response received in AHB bus. + * | | |0 = No ERROR response received. + * | | |1 = ERROR response received. + * |[3] |OCAL |over Current Active Low + * | | |This bit controls the polarity of over current flag from external power IC. + * | | |0 = Over current flag is high active. + * | | |1 = Over current flag is low active. + * |[16] |DPRT1 |Disable Port 1 + * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled + * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus. + * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. + * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled. + * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode. + */ + __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */ + __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */ + __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */ + __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */ + __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */ + __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */ + __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */ + __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */ + __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */ + __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */ + __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */ + __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */ + __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */ + __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */ + __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */ + __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */ + __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */ + __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */ + __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */ + __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */ + __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */ + __IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status [1] */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[105]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */ + __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */ + +} USBH_T; + +/** + @addtogroup USBH_CONST USBH Bit Field Definition + Constant Definitions for USBH Controller +@{ */ + +#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */ +#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */ + +#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */ +#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */ + +#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */ +#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */ + +#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */ +#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */ + +#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */ +#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */ + +#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */ +#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */ + +#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */ +#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */ + +#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */ +#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */ + +#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */ +#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */ + +#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */ +#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */ + +#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */ +#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */ + +#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */ +#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */ + +#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/ +#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */ + +#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */ +#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */ + +#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */ +#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */ + +#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/ +#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */ + +#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/ +#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */ + +#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */ +#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */ + +#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/ +#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */ + +#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */ +#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */ + +#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */ +#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */ + +#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/ +#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */ + +#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/ +#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */ + +#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/ +#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */ + +#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/ +#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */ + +#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/ +#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */ + +#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/ +#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */ + +#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/ +#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */ + +#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/ +#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */ + +#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/ +#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */ + +#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/ +#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */ + +#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */ +#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */ + +#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/ +#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */ + +#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */ +#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */ + +#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/ +#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */ + +#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */ +#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */ + +#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */ +#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */ + +#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */ +#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */ + +#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */ +#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */ + +#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */ +#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */ + +#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */ +#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */ + +#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */ +#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */ + +#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */ +#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */ + +#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */ +#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */ + +#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */ +#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */ + +#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */ +#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */ + +#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */ +#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */ + +#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */ +#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */ + +#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */ +#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */ + +#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */ +#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */ + +#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */ +#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */ + +#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */ +#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */ + +#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */ +#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */ + +#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */ +#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */ + +#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */ +#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */ + +#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */ +#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */ + +#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */ +#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */ + +#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus1: CCS Position */ +#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus1: CCS Mask */ + +#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus1: PES Position */ +#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus1: PES Mask */ + +#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus1: PSS Position */ +#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus1: PSS Mask */ + +#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus1: POCI Position */ +#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus1: POCI Mask */ + +#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus1: PRS Position */ +#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus1: PRS Mask */ + +#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus1: PPS Position */ +#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus1: PPS Mask */ + +#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus1: LSDA Position */ +#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus1: LSDA Mask */ + +#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus1: CSC Position */ +#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus1: CSC Mask */ + +#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus1: PESC Position */ +#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus1: PESC Mask */ + +#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus1: PSSC Position */ +#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus1: PSSC Mask */ + +#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus1: OCIC Position */ +#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus1: OCIC Mask */ + +#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus1: PRSC Position */ +#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus1: PRSC Mask */ + +#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */ +#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */ + +#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */ +#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */ + +#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */ +#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */ + +#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */ +#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */ + +/**@}*/ /* USBH_CONST */ +/**@}*/ /* end of USBH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USBH_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uspi_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uspi_reg.h new file mode 100644 index 00000000000..dd2c5bb874f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uspi_reg.h @@ -0,0 +1,676 @@ +/**************************************************************************//** + * @file uspi_reg.h + * @version V1.00 + * @brief USPI register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USPI_REG_H__ +#define __USPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USPI SPI Mode of USCI Controller(USPI) + Memory Mapped Structure for USPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var USPI_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var USPI_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var USPI_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fDIV_CLK. + * | | |01 = fPROT_CLK. + * | | |10 = fSCLK. + * | | |11 = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var USPI_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * @var USPI_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var USPI_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * @var USPI_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. + * | | |0 = Data output level is not inverted. + * | | |1 = Data output level is inverted. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: The control signal has different definitions in different protocol + * | | |In SPI protocol, the control signal means slave select signal + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * @var USPI_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission + * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. + * |[16] |PORTDIR |Port Direction Control + * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer + * | | |It is used to define the direction of the data port pin + * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously. + * | | |0 = The data pin is configured as output mode. + * | | |1 = The data pin is configured as input mode. + * @var USPI_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * @var USPI_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6] |TXUDRIEN |Slave Transmit Under Run Interrupt Enable Bit + * | | |0 = Transmit under-run interrupt Disabled. + * | | |1 = Transmit under-run interrupt Enabled. + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * @var USPI_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Interrupt Status + * | | |This bit indicates that a receive buffer overrun event has been detected + * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun event has not been detected. + * | | |1 = A receive buffer overrun event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty and available for the next transmission datum. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status + * | | |This bit indicates that a transmit buffer under-run event has been detected + * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit + * | | |0 = A transmit buffer under-run event has not been detected. + * | | |1 = A transmit buffer under-run event has been detected. + * @var USPI_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * | | |Notice: The I2C is not supporting PDMA function. + * @var USPI_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var USPI_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var USPI_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLAVE |Slave Mode Selection + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only) + * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[2] |SS |Slave Select Control (Master Only) + * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state. + * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal. + * | | |Note: In SPI protocol, the internal slave select signal is active high. + * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only) + * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit. + * | | |1 = Slave select signal will be generated automatically + * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished. + * |[7:6] |SCLKMODE |Serial Bus Clock Mode + * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge. + * | | |MODE0 = The idle state of SPI clock is low level + * | | |Data is transmitted with falling edge and received with rising edge. + * | | |MODE1 = The idle state of SPI clock is low level + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |MODE2 = The idle state of SPI clock is high level + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |MODE3 = The idle state of SPI clock is high level + * | | |Data is transmitted with falling edge and received with rising edge. + * |[11:8] |SUSPITV |Suspend Interval (Master Only) + * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle. + * |[14:12] |TSMSEL |Transmit Data Mode Selection + * | | |This bit field describes how receive and transmit data is shifted in and out. + * | | |TSMSEL = 000b: Full-duplex SPI. + * | | |TSMSEL = 100b: Half-duplex SPI. + * | | |Other values are reserved. + * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. + * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only) + * | | |In Slave mode, this bit field is used for Slave time-out period + * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event + * | | |Writing 0x0 into this bit field will disable the Slave time-out function. + * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. + * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave) + * | | |This bit defines the transmitting data level when no data is available for transferring. + * | | |0 = The output data level is 0 if TX under run event occurs. + * | | |1 = The output data level is 1 if TX under run event occurs. + * |[31] |PROTEN |SPI Protocol Enable Bit + * | | |0 = SPI Protocol Disabled. + * | | |1 = SPI Protocol Enabled. + * @var USPI_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. + * | | |0 = Slave select inactive interrupt generation Disabled. + * | | |1 = Slave select inactive interrupt generation Enabled. + * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. + * | | |0 = Slave select active interrupt generation Disabled. + * | | |1 = Slave select active interrupt generation Enabled. + * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control + * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. + * | | |0 = The Slave time-out interrupt Disabled. + * | | |1 = The Slave time-out interrupt Enabled. + * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control + * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]) + * | | |Bit count error event occurs. + * | | |0 = The Slave mode bit count error interrupt Disabled. + * | | |1 = The Slave mode bit count error interrupt Enabled. + * @var USPI_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = Transmit start event does not occur. + * | | |1 = Transmit start event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = Transmit end event does not occur. + * | | |1 = Transmit end event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = Receive start event does not occur. + * | | |1 = Receive start event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = Receive end event does not occur. + * | | |1 = Receive end event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only) + * | | |0 = Slave time-out event does not occur. + * | | |1 = Slave time-out event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only) + * | | |0 = Slave bit count error event does not occur. + * | | |1 = Slave bit count error event occurs. + * | | |Note: It is cleared by software writes 1 to this bit. + * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to inactive + * | | |It is cleared by software writes 1 to this bit + * | | |0 = The slave select signal has not changed to inactive. + * | | |1 = The slave select signal has changed to inactive. + * | | |Note: The internal slave select signal is active high. + * |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to active + * | | |It is cleared by software writes one to this bit + * | | |0 = The slave select signal has not changed to active. + * | | |1 = The slave select signal has changed to active. + * | | |Note: The internal slave select signal is active high. + * |[16] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |This bit is only available in Slave mode + * | | |It used to monitor the current status of the input slave select signal on the bus. + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * |[17] |BUSY |Busy Status (Read Only) + * | | |0 = SPI is in idle state. + * | | |1 = SPI is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0. + * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only) + * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1 + * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. + * | | |0 = Slave transmit under-run event does not occur. + * | | |1 = Slave transmit under-run event occurs. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} USPI_T; + +/** + @addtogroup USPI_CONST USPI Bit Field Definition + Constant Definitions for USPI Controller +@{ */ + +#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */ +#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */ + +#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */ +#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */ + +#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */ +#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */ + +#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */ +#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */ + +#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */ +#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */ + +#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */ +#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */ + +#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */ +#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */ + +#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */ +#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */ + +#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */ +#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */ + +#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */ +#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */ + +#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */ +#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */ + +#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */ +#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */ + +#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */ +#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */ + +#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */ +#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */ + +#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */ +#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */ + +#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */ +#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */ + +#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */ +#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */ + +#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */ +#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */ + +#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */ +#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */ + +#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */ +#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */ + +#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */ +#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */ + +#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */ +#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */ + +#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */ +#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */ + +#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */ +#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */ + +#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */ +#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */ + +#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */ +#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */ + +#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */ +#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */ + +#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */ +#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */ + +#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */ +#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */ + +#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */ +#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */ + +#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */ +#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */ + +#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */ +#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */ + +#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */ +#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */ + +#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */ +#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */ + +#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */ +#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */ + +#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */ +#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */ + +#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */ +#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */ + +#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */ +#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */ + +#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */ +#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */ + +#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */ +#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */ + +#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */ +#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */ + +#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */ +#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */ + +#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */ +#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */ + +#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */ +#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */ + +#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */ +#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */ + +#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */ +#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */ + +#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */ +#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */ + +#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */ +#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */ + +#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */ +#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */ + +#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */ +#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */ + +#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */ +#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */ + +#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */ +#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */ + +#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */ +#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */ + +#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */ +#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */ + +#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */ +#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */ + +#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */ +#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */ + +#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */ +#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */ + +#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */ +#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */ + +#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */ +#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */ + +#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */ +#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */ + +#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */ +#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */ + +#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */ +#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */ + +#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */ +#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */ + +#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */ +#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */ + +#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */ +#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */ + +#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */ +#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */ + +#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */ +#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */ + +#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */ +#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */ + +/**@}*/ /* USPI_CONST */ +/**@}*/ /* end of USPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USPI_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uuart_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uuart_reg.h new file mode 100644 index 00000000000..d0b68b4c2e0 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/uuart_reg.h @@ -0,0 +1,678 @@ +/**************************************************************************//** + * @file uuart_reg.h + * @version V1.00 + * @brief UUART register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UUART_REG_H__ +#define __UUART_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UUART UART Mode of USCI Controller(UUART) + Memory Mapped Structure for UUART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UUART_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UUART_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable BIt + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var UUART_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Timing measurement counter is Disabled. + * | | |1 = Timing measurement counter is Enabled. + * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection + * | | |0 = Timing measurement counter with fPROT_CLK. + * | | |1 = Timing measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and + * | | |the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 + * | | |when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UUART_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or + * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * |[4:3] |EDGEDET |Input Signal Edge Detection Mode + * | | |This bit field selects which edge actives the trigger event of input data signal. + * | | |00 = The trigger event activation is disabled. + * | | |01 = A rising edge activates the trigger event of input data signal. + * | | |10 = A falling edge activates the trigger event of input data signal. + * | | |11 = Both edges activate the trigger event of input data signal. + * | | |Note: In UART function mode, it is suggested to set this bit field as 10. + * @var UUART_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or + * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var UUART_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or + * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * @var UUART_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. + * | | |0 = The value of USCIx_DAT1 is equal to the data shift register. + * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: In UART protocol, the control signal means nRTS signal. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |.. + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits. + * @var UUART_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UUART_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]). + * @var UUART_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value) + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value) + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note 1: It is cleared automatically after one PCLK cycle. + * | | |Note 2: It is suggest to check the RXBUSY (USCI_PROTSTS[10]) before this bit will be set to 1. + * @var UUART_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status + * | | |This bit indicates that a receive buffer overrun error event has been detected + * | | |If RXOVIEN (USCI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun error event has not been detected. + * | | |1 = A receive buffer overrun error event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * @var UUART_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * @var UUART_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var UUART_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UUART_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STOPB |Stop Bits + * | | |This bit defines the number of stop bits in an UART frame. + * | | |0 = The number of stop bits is 1. + * | | |1 = The number of stop bits is 2. + * |[1] |PARITYEN |Parity Enable Bit + * | | |This bit defines the parity bit is enabled in an UART frame. + * | | |0 = The parity bit Disabled. + * | | |1 = The parity bit Enabled. + * |[2] |EVENPARITY|Even Parity Enable Bit + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PARITYEN is set. + * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit + * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (USCI_BUFSTS[1] = 1'b1)), the UART will de-assert nRTS signal. + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: This bit has effect only when the RTSAUDIREN is not set. + * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit + * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit + * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically. + * | | |0 = nRTS auto direction control Disabled. + * | | |1 = nRTS auto direction control Enabled. + * | | |Note 1: This bit is used for nRTS auto direction control for RS485. + * | | |Note 2: This bit has effect only when the RTSAUTOEN is not set. + * |[6] |ABREN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit + * | | |The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (USCI_PROTIEN [1]) is enabled). + * |[9] |DATWKEN |Data Wake-up Mode Enable Bit + * | | |0 = Data wake-up mode Disabled. + * | | |1 = Data wake-up mode Enabled. + * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit + * | | |0 = nCTS wake-up mode Disabled. + * | | |1 = nCTS wake-up mode Enabled. + * |[14:11] |WAKECNT |Wake-up Counter + * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. + * |[24:16] |BRDETITV |Baud Rate Detection Interval + * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) does the slave calculates the baud rate in one bits + * | | |The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55) + * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (USCI_PROTCTL[9]) is set. + * | | |Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV. + * |[26] |STICKEN |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: Refer to RS-485 Support section for detail information. + * |[29] |BCEN |Transmit Break Control Enable Bit + * | | |0 = Transmit Break Control Disabled. + * | | |1 = Transmit Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[31] |PROTEN |UART Protocol Enable Bit + * | | |0 = UART Protocol Disabled. + * | | |1 = UART Protocol Enabled. + * @var UUART_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive line status interrupt Disabled. + * | | |1 = Receive line status interrupt Enabled. + * | | |Note: USCI_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. + * @var UUART_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = A transmit start interrupt status has not occurred. + * | | |1 = A transmit start interrupt status has occurred. + * | | |Note 1: It is cleared by software writing one into this bit. + * | | |Note 2: Used for user to load next transmit data when there is no data in transmit buffer. + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = A transmit end interrupt status has not occurred. + * | | |1 = A transmit end interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = A receive start interrupt status has not occurred. + * | | |1 = A receive start interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = A receive finish interrupt status has not occurred. + * | | |1 = A receive finish interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[5] |PARITYERR |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[6] |FRMERR |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' + * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[7] |BREAK |Break Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' + * | | |(logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break is generated. + * | | |1 = Break is generated in the receiver bus. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag + * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data + * | | |If the ABRIEN (USCI_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated + * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. + * | | |0 = Auto-baud rate detect function is not done. + * | | |1 = One Bit auto-baud rate detect function is done. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[10] |RXBUSY |RX Bus Status Flag (Read Only) + * | | |This bit indicates the busy status of the receiver. + * | | |0 = The receiver is Idle. + * | | |1 = The receiver is BUSY. + * |[11] |ABERRSTS |Auto-baud Rate Error Status + * | | |This bit is set when auto-baud rate detection counter overrun + * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (USCI_BRGEN[25:16]) value and + * | | |enable ABREN (USCI_PROTCTL[6]) to detect the correct baud rate again. + * | | |0 = Auto-baud rate detect counter is not overrun. + * | | |1 = Auto-baud rate detect counter is overrun. + * | | |Note 1: This bit is set at the same time of ABRDETIF. + * | | |Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. + * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only) + * | | |This bit used to indicate the current status of the internal synchronized nCTS signal. + * | | |0 = The internal synchronized nCTS is low. + * | | |1 = The internal synchronized nCTS is high. + * |[17] |CTSLV |nCTS Pin Status (Read Only) + * | | |This bit used to monitor the current status of nCTS pin input. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __IO uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __IO uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} UUART_T; + +/** + @addtogroup UUART_CONST UUART Bit Field Definition + Constant Definitions for UUART Controller +@{ */ + +#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */ +#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */ + +#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */ +#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */ + +#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */ +#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */ + +#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */ +#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */ + +#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */ +#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */ + +#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */ +#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */ + +#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */ +#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */ + +#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */ +#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */ + +#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */ +#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */ + +#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */ +#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */ + +#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */ +#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */ + +#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */ +#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */ + +#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */ +#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */ + +#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */ +#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */ + +#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */ +#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */ + +#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */ +#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */ + +#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */ +#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */ + +#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */ +#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */ + +#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */ +#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */ + +#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */ +#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */ + +#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */ +#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */ + +#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */ +#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */ + +#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */ +#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */ + +#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */ +#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */ + +#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */ +#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */ + +#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */ +#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */ + +#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */ +#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */ + +#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */ +#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */ + +#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */ +#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */ + +#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */ +#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */ + +#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */ +#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */ + +#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */ +#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */ + +#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */ +#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */ + +#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */ +#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */ + +#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */ +#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */ + +#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */ +#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */ + +#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */ +#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */ + +#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */ +#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */ + +#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */ +#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */ + +#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */ +#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */ + +#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */ +#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */ + +#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */ +#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */ + +#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */ +#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */ + +#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */ +#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */ + +#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */ +#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */ + +#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */ +#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */ + +#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */ +#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */ + +#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */ +#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */ + +#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */ +#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */ + +#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */ +#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */ + +#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */ +#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */ + +#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */ +#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */ + +#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */ +#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */ + +#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */ +#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */ + +#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */ +#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */ + +#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */ +#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */ + +#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */ +#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */ + +#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */ +#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */ + +#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */ +#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */ + +#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */ +#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */ + +#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */ +#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */ + +#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */ +#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */ + +#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */ +#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */ + +#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */ +#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */ + +#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */ +#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */ + +#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */ +#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */ + +#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */ +#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */ + +#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */ +#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */ + +#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */ +#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */ + +#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */ +#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */ + +/**@}*/ /* UUART_CONST */ +/**@}*/ /* end of UUART register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UUART_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wdt_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wdt_reg.h new file mode 100644 index 00000000000..8d4ef0fea59 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wdt_reg.h @@ -0,0 +1,182 @@ +/**************************************************************************//** + * @file wdt_reg.h + * @version V1.00 + * @brief WDT register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_REG_H__ +#define __WDT_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup WDT Watch Dog Timer Controller(WDT) + Memory Mapped Structure for WDT Controller +@{ */ + +typedef struct +{ + + + /** + * @var WDT_T::CTL + * Offset: 0x00 WDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RSTCNT |Reset WDT Up Counter (Write Protect) + * | | |0 = No effect. + * | | |1 = Reset the internal 18-bit WDT up counter value. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit will be automatically cleared by hardware. + * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect) + * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. + * | | |0 = WDT time-out reset function Disabled. + * | | |1 = WDT time-out reset function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |RSTF |WDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by WDT time-out reset or not. + * | | |0 = WDT time-out reset did not occur. + * | | |1 = WDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |IF |WDT Time-out Interrupt Flag + * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval + * | | |0 = WDT time-out interrupt did not occur. + * | | |1 = WDT time-out interrupt occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) + * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. + * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT. + * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect) + * | | |This bit indicates the interrupt wake-up flag status of WDT + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) + * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WDTEN |WDT Enable Control (Write Protect) + * | | |0 = WDT Disabled (This action will reset the internal up counter value). + * | | |1 = WDT Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0. + * |[10:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) + * | | |These three bits select the time-out interval period for the WDT. + * | | |000 = 24 * WDT_CLK. + * | | |001 = 26 * WDT_CLK. + * | | |010 = 28 * WDT_CLK. + * | | |011 = 210 * WDT_CLK. + * | | |100 = 212 * WDT_CLK. + * | | |101 = 214 * WDT_CLK. + * | | |110 = 216 * WDT_CLK. + * | | |111 = 218 * WDT_CLK. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only) + * | | |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. + * | | |0 = Set WDTEN bit is completed. + * | | |1 = Set WDTEN bit is synchronizing and not become active yet.. + * | | |Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgement affects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var WDT_T::ALTCTL + * Offset: 0x04 WDT Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect) + * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened + * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. + * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. + * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. + * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This register will be reset to 0 if WDT time-out reset happened. + * @var WDT_T::RSTCNT + * Offset: 0x08 WDT Reset Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RSTCNT |WDT Reset Counter Register + * | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0. + * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. + * | | |Note: RSTCNT (WDT_CTL[0]) bit is a write protected bit + * | | |RSTCNT (WDT_RSTCNT[31:0]) bits are not write protected. + */ + __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ + __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ + +} WDT_T; + +/** + @addtogroup WDT_CONST WDT Bit Field Definition + Constant Definitions for WDT Controller +@{ */ + +#define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */ +#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */ + +#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ +#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ + +#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ +#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ + +#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ +#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ + +#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ +#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ + +#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ +#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ + +#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ +#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ + +#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ +#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ + +#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ +#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ + +#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ +#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ + +#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ +#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ + +#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ +#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ + +#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ +#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ + +/**@}*/ /* WDT_CONST */ +/**@}*/ /* end of WDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __WDT_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wwdt_reg.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wwdt_reg.h new file mode 100644 index 00000000000..963a4fbf7f1 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Include/wwdt_reg.h @@ -0,0 +1,148 @@ +/**************************************************************************//** + * @file wwdt_reg.h + * @version V1.00 + * @brief WWDT register definition header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_REG_H__ +#define __WWDT_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup WWDT Window Watchdog Timer(WWDT) + Memory Mapped Structure for WWDT Controller +@{ */ + +typedef struct +{ + + + /** + * @var WWDT_T::RLDCNT + * Offset: 0x00 WWDT Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RLDCNT |WWDT Reload Counter Register + * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]) + * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately. + * @var WWDT_T::CTL + * Offset: 0x04 WWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Control Bit + * | | |Set this bit to enable WWDT counter counting. + * | | |0 = WWDT counter is stopped. + * | | |1 = WWDT counter is starting counting. + * |[1] |INTEN |WWDT Interrupt Enable Control Bit + * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. + * |[21:16] |CMPDAT |WWDT Window Compare Register + * | | |Set this register to adjust the valid reload window. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT + * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control + * | | |0 = ICE debug mode acknowledgement effects WWDT counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |WWDT down counter will keep going no matter CPU is held by ICE or not. + * @var WWDT_T::STATUS + * Offset: 0x08 WWDT Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). + * | | |0 = No effect. + * | | |1 = WWDT counter value matches CMPDAT. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Timer-out Reset Flag + * | | |This bit indicates the system has been reset by WWDT time-out reset or not. + * | | |0 = WWDT time-out reset did not occur. + * | | |1 = WWDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var WWDT_T::CNT + * Offset: 0x0C WWDT Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CNTDAT |WWDT Counter Value + * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. + */ + __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */ + __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */ + __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */ + +} WWDT_T; + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller +@{ */ + +#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */ +#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */ + +#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */ +#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */ + +#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */ +#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */ + +#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */ +#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */ + +#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */ +#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */ + +#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */ +#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */ + +#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */ +#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */ + +#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */ +#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */ + +#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */ +#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */ + +/**@}*/ /* WWDT_CONST */ +/**@}*/ /* end of WWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __WWDT_REG_H__ */ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/ARM/startup_M480.s b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/ARM/startup_M480.s new file mode 100644 index 00000000000..9887fb11a24 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/ARM/startup_M480.s @@ -0,0 +1,479 @@ +;/****************************************************************************** +; * @file startup_M480.s +; * @version V1.00 +; * @brief CMSIS Cortex-M4 Core Device Startup File for M480 +; * +; * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +;*****************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + IF :LNOT: :DEF: Stack_Size +Stack_Size EQU 0x00000800 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + IF :LNOT: :DEF: Heap_Size +Heap_Size EQU 0x00000100 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD BOD_IRQHandler ; 0: Brown Out detection + DCD IRC_IRQHandler ; 1: Internal RC + DCD PWRWU_IRQHandler ; 2: Power down wake up + DCD RAMPE_IRQHandler ; 3: RAM parity error + DCD CKFAIL_IRQHandler ; 4: Clock detection fail + DCD Default_Handler ; 5: Reserved + DCD RTC_IRQHandler ; 6: Real Time Clock + DCD TAMPER_IRQHandler ; 7: Tamper detection + DCD WDT_IRQHandler ; 8: Watchdog timer + DCD WWDT_IRQHandler ; 9: Window watchdog timer + DCD EINT0_IRQHandler ; 10: External Input 0 + DCD EINT1_IRQHandler ; 11: External Input 1 + DCD EINT2_IRQHandler ; 12: External Input 2 + DCD EINT3_IRQHandler ; 13: External Input 3 + DCD EINT4_IRQHandler ; 14: External Input 4 + DCD EINT5_IRQHandler ; 15: External Input 5 + DCD GPA_IRQHandler ; 16: GPIO Port A + DCD GPB_IRQHandler ; 17: GPIO Port B + DCD GPC_IRQHandler ; 18: GPIO Port C + DCD GPD_IRQHandler ; 19: GPIO Port D + DCD GPE_IRQHandler ; 20: GPIO Port E + DCD GPF_IRQHandler ; 21: GPIO Port F + DCD QSPI0_IRQHandler ; 22: QSPI0 + DCD SPI0_IRQHandler ; 23: SPI0 + DCD BRAKE0_IRQHandler ; 24: + DCD EPWM0P0_IRQHandler ; 25: + DCD EPWM0P1_IRQHandler ; 26: + DCD EPWM0P2_IRQHandler ; 27: + DCD BRAKE1_IRQHandler ; 28: + DCD EPWM1P0_IRQHandler ; 29: + DCD EPWM1P1_IRQHandler ; 30: + DCD EPWM1P2_IRQHandler ; 31: + DCD TMR0_IRQHandler ; 32: Timer 0 + DCD TMR1_IRQHandler ; 33: Timer 1 + DCD TMR2_IRQHandler ; 34: Timer 2 + DCD TMR3_IRQHandler ; 35: Timer 3 + DCD UART0_IRQHandler ; 36: UART0 + DCD UART1_IRQHandler ; 37: UART1 + DCD I2C0_IRQHandler ; 38: I2C0 + DCD I2C1_IRQHandler ; 39: I2C1 + DCD PDMA_IRQHandler ; 40: Peripheral DMA + DCD DAC_IRQHandler ; 41: DAC + DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0 + DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1 + DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1 + DCD Default_Handler ; 45: Reserved + DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2 + DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3 + DCD UART2_IRQHandler ; 48: UART2 + DCD UART3_IRQHandler ; 49: UART3 + DCD Default_Handler ; 50: Reserved + DCD SPI1_IRQHandler ; 51: SPI1 + DCD SPI2_IRQHandler ; 52: SPI2 + DCD USBD_IRQHandler ; 53: USB device + DCD OHCI_IRQHandler ; 54: OHCI + DCD USBOTG_IRQHandler ; 55: USB OTG + DCD CAN0_IRQHandler ; 56: CAN0 + DCD CAN1_IRQHandler ; 57: CAN1 + DCD SC0_IRQHandler ; 58: + DCD SC1_IRQHandler ; 59: + DCD SC2_IRQHandler ; 60: + DCD Default_Handler ; 61: + DCD SPI3_IRQHandler ; 62: SPI3 + DCD Default_Handler ; 63: + DCD SDH0_IRQHandler ; 64: SDH0 + DCD USBD20_IRQHandler ; 65: USBD20 + DCD EMAC_TX_IRQHandler ; 66: EMAC_TX + DCD EMAC_RX_IRQHandler ; 67: EMAX_RX + DCD I2S0_IRQHandler ; 68: I2S0 + DCD Default_Handler ; 69: ToDo: Add description to this Interrupt + DCD OPA0_IRQHandler ; 70: OPA0 + DCD CRYPTO_IRQHandler ; 71: CRYPTO + DCD GPG_IRQHandler ; 72: + DCD EINT6_IRQHandler ; 73: + DCD UART4_IRQHandler ; 74: UART4 + DCD UART5_IRQHandler ; 75: UART5 + DCD USCI0_IRQHandler ; 76: USCI0 + DCD USCI1_IRQHandler ; 77: USCI1 + DCD BPWM0_IRQHandler ; 78: BPWM0 + DCD BPWM1_IRQHandler ; 79: BPWM1 + DCD SPIM_IRQHandler ; 80: SPIM + DCD Default_Handler ; 81: ToDo: Add description to this Interrupt + DCD I2C2_IRQHandler ; 82: I2C2 + DCD Default_Handler ; 83: + DCD QEI0_IRQHandler ; 84: QEI0 + DCD QEI1_IRQHandler ; 85: QEI1 + DCD ECAP0_IRQHandler ; 86: ECAP0 + DCD ECAP1_IRQHandler ; 87: ECAP1 + DCD GPH_IRQHandler ; 88: + DCD EINT7_IRQHandler ; 89: + DCD SDH1_IRQHandler ; 90: SDH1 + DCD Default_Handler ; 91: + DCD EHCI_IRQHandler ; 92: EHCI + DCD USBOTG20_IRQHandler ; 93: + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ; Unlock Register + LDR R0, =0x40000100 + LDR R1, =0x59 + STR R1, [R0] + LDR R1, =0x16 + STR R1, [R0] + LDR R1, =0x88 + STR R1, [R0] + + IF :LNOT: :DEF: ENABLE_SPIM_CACHE + LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address + LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK) + ORR R1, R1, #0x4000 + STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; + + LDR R0, =0x40007000 ; R0 = SPIM Register Base Address + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk + STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE() + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk + STR R1, [R0,#4] ; _SPIM_ENABLE_CCM() + ENDIF + + LDR R0, =SystemInit + BLX R0 + + ; Init POR + ; LDR R2, =0x40000024 + ; LDR R1, =0x00005AA5 + ; STR R1, [R2] + + ; Lock + LDR R0, =0x40000100 + LDR R1, =0 + STR R1, [R0] + + LDR R0, =__main + BX R0 + + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT BOD_IRQHandler [WEAK] + EXPORT IRC_IRQHandler [WEAK] + EXPORT PWRWU_IRQHandler [WEAK] + EXPORT RAMPE_IRQHandler [WEAK] + EXPORT CKFAIL_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT WWDT_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT EINT4_IRQHandler [WEAK] + EXPORT EINT5_IRQHandler [WEAK] + EXPORT GPA_IRQHandler [WEAK] + EXPORT GPB_IRQHandler [WEAK] + EXPORT GPC_IRQHandler [WEAK] + EXPORT GPD_IRQHandler [WEAK] + EXPORT GPE_IRQHandler [WEAK] + EXPORT GPF_IRQHandler [WEAK] + EXPORT QSPI0_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT BRAKE0_IRQHandler [WEAK] + EXPORT EPWM0P0_IRQHandler [WEAK] + EXPORT EPWM0P1_IRQHandler [WEAK] + EXPORT EPWM0P2_IRQHandler [WEAK] + EXPORT BRAKE1_IRQHandler [WEAK] + EXPORT EPWM1P0_IRQHandler [WEAK] + EXPORT EPWM1P1_IRQHandler [WEAK] + EXPORT EPWM1P2_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT PDMA_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT ADC00_IRQHandler [WEAK] + EXPORT ADC01_IRQHandler [WEAK] + EXPORT ACMP01_IRQHandler [WEAK] + EXPORT ADC02_IRQHandler [WEAK] + EXPORT ADC03_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USBD_IRQHandler [WEAK] + EXPORT OHCI_IRQHandler [WEAK] + EXPORT USBOTG_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT SC0_IRQHandler [WEAK] + EXPORT SC1_IRQHandler [WEAK] + EXPORT SC2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SDH0_IRQHandler [WEAK] + EXPORT USBD20_IRQHandler [WEAK] + EXPORT EMAC_TX_IRQHandler [WEAK] + EXPORT EMAC_RX_IRQHandler [WEAK] + EXPORT I2S0_IRQHandler [WEAK] + EXPORT OPA0_IRQHandler [WEAK] + EXPORT CRYPTO_IRQHandler [WEAK] + EXPORT GPG_IRQHandler [WEAK] + EXPORT EINT6_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT USCI0_IRQHandler [WEAK] + EXPORT USCI1_IRQHandler [WEAK] + EXPORT BPWM0_IRQHandler [WEAK] + EXPORT BPWM1_IRQHandler [WEAK] + EXPORT SPIM_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT QEI0_IRQHandler [WEAK] + EXPORT QEI1_IRQHandler [WEAK] + EXPORT ECAP0_IRQHandler [WEAK] + EXPORT ECAP1_IRQHandler [WEAK] + EXPORT GPH_IRQHandler [WEAK] + EXPORT EINT7_IRQHandler [WEAK] + EXPORT SDH1_IRQHandler [WEAK] + EXPORT EHCI_IRQHandler [WEAK] + EXPORT USBOTG20_IRQHandler [WEAK] + +Default__IRQHandler +BOD_IRQHandler +IRC_IRQHandler +PWRWU_IRQHandler +RAMPE_IRQHandler +CKFAIL_IRQHandler +RTC_IRQHandler +TAMPER_IRQHandler +WDT_IRQHandler +WWDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +EINT5_IRQHandler +GPA_IRQHandler +GPB_IRQHandler +GPC_IRQHandler +GPD_IRQHandler +GPE_IRQHandler +GPF_IRQHandler +QSPI0_IRQHandler +SPI0_IRQHandler +BRAKE0_IRQHandler +EPWM0P0_IRQHandler +EPWM0P1_IRQHandler +EPWM0P2_IRQHandler +BRAKE1_IRQHandler +EPWM1P0_IRQHandler +EPWM1P1_IRQHandler +EPWM1P2_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +PDMA_IRQHandler +DAC_IRQHandler +ADC00_IRQHandler +ADC01_IRQHandler +ACMP01_IRQHandler +ADC02_IRQHandler +ADC03_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USBD_IRQHandler +OHCI_IRQHandler +USBOTG_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +SC0_IRQHandler +SC1_IRQHandler +SC2_IRQHandler +SPI3_IRQHandler +SDH0_IRQHandler +USBD20_IRQHandler +EMAC_TX_IRQHandler +EMAC_RX_IRQHandler +I2S0_IRQHandler +OPA0_IRQHandler +CRYPTO_IRQHandler +GPG_IRQHandler +EINT6_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +USCI0_IRQHandler +USCI1_IRQHandler +BPWM0_IRQHandler +BPWM1_IRQHandler +SPIM_IRQHandler +I2C2_IRQHandler +QEI0_IRQHandler +QEI1_IRQHandler +ECAP0_IRQHandler +ECAP1_IRQHandler +GPH_IRQHandler +EINT7_IRQHandler +SDH1_IRQHandler +EHCI_IRQHandler +USBOTG20_IRQHandler + + + + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END +;/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/_syscalls.c b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/_syscalls.c new file mode 100644 index 00000000000..adedf280d80 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/_syscalls.c @@ -0,0 +1,1168 @@ +// +// This file is part of the uOS++ III distribution +// Parts of this file are from the newlib sources, issued under GPL. +// Copyright (c) 2014 Liviu Ionescu +// + +// ---------------------------------------------------------------------------- + +int errno; +void *__dso_handle __attribute__ ((weak)); + +// ---------------------------------------------------------------------------- + +#if !defined(OS_USE_SEMIHOSTING) + +#include <_ansi.h> +#include <_syslist.h> +#include +//#include +#include +#include +#include +#include +#include + +void +__initialize_args(int* p_argc, char*** p_argv); + +// This is the standard default implementation for the routine to +// process args. It returns a single empty arg. +// For semihosting applications, this is redefined to get the real +// args from the debugger. You can also use it if you decide to keep +// some args in a non-volatile memory. + +void __attribute__((weak)) +__initialize_args(int* p_argc, char*** p_argv) +{ + // By the time we reach this, the data and bss should have been initialised. + + // The strings pointed to by the argv array shall be modifiable by the + // program, and retain their last-stored values between program startup + // and program termination. (static, no const) + static char name[] = ""; + + // The string pointed to by argv[0] represents the program name; + // argv[0][0] shall be the null character if the program name is not + // available from the host environment. argv[argc] shall be a null pointer. + // (static, no const) + static char* argv[2] = + { name, NULL }; + + *p_argc = 1; + *p_argv = &argv[0]; + return; +} + +// These functions are defined here to avoid linker errors in freestanding +// applications. They might be called in some error cases from library +// code. +// +// If you detect other functions to be needed, just let us know +// and we'll add them. + +int +raise(int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int +kill(pid_t pid, int sig); + +int +kill(pid_t pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +#endif // !defined(OS_USE_SEMIHOSTING) + +// ---------------------------------------------------------------------------- + +// If you need the empty definitions, remove the -ffreestanding option. + +#if __STDC_HOSTED__ == 1 + +char* __env[1] = +{ 0 }; +char** environ = __env; + +#if !defined(OS_USE_SEMIHOSTING) + +// Forward declarations + +int +_chown(const char* path, uid_t owner, gid_t group); + +int +_close(int fildes); + +int +_execve(char* name, char** argv, char** env); + +int +_fork(void); + +int +_fstat(int fildes, struct stat* st); + +int +_getpid(void); + +int +_gettimeofday(struct timeval* ptimeval, void* ptimezone); + +int +_isatty(int file); + +int +_kill(int pid, int sig); + +int +_link(char* existing, char* _new); + +int +_lseek(int file, int ptr, int dir); + +int +_open(char* file, int flags, int mode); + +int +_read(int file, char* ptr, int len); + +int +_readlink(const char* path, char* buf, size_t bufsize); + +int +_stat(const char* file, struct stat* st); + +int +_symlink(const char* path1, const char* path2); + +clock_t +_times(struct tms* buf); + +int +_unlink(char* name); + +int +_wait(int* status); + +int +_write(int file, char* ptr, int len); + +// Definitions + +int __attribute__((weak)) +_chown(const char* path __attribute__((unused)), + uid_t owner __attribute__((unused)), gid_t group __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_close(int fildes __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_execve(char* name __attribute__((unused)), char** argv __attribute__((unused)), + char** env __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_fork(void) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_fstat(int fildes __attribute__((unused)), + struct stat* st __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_getpid(void) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_gettimeofday(struct timeval* ptimeval __attribute__((unused)), + void* ptimezone __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_isatty(int file __attribute__((unused))) +{ + errno = ENOSYS; + return 0; +} + +int __attribute__((weak)) +_kill(int pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_link(char* existing __attribute__((unused)), + char* _new __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_lseek(int file __attribute__((unused)), int ptr __attribute__((unused)), + int dir __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_open(char* file __attribute__((unused)), int flags __attribute__((unused)), + int mode __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_read(int file __attribute__((unused)), char* ptr __attribute__((unused)), + int len __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_readlink(const char* path __attribute__((unused)), + char* buf __attribute__((unused)), size_t bufsize __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_stat(const char* file __attribute__((unused)), + struct stat* st __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_symlink(const char* path1 __attribute__((unused)), + const char* path2 __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +clock_t __attribute__((weak)) +_times(struct tms* buf __attribute__((unused))) +{ + errno = ENOSYS; + return ((clock_t) -1); +} + +int __attribute__((weak)) +_unlink(char* name __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_wait(int* status __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +int __attribute__((weak)) +_write(int file __attribute__((unused)), char* ptr __attribute__((unused)), + int len __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +#else // defined(OS_USE_SEMIHOSTING) + +// ---------------------------------------------------------------------------- + +/* Support files for GNU libc. Files in the system namespace go here. + Files in the C namespace (ie those that do not start with an + underscore) go in .c. */ + +#include <_ansi.h> +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "semihosting.h" + +int _kill (int pid, int sig); + +void __attribute__((noreturn)) _exit (int status); + +// Forward declarations. +int _system (const char*); +int _rename (const char*, const char*); +int _isatty (int); +clock_t _times (struct tms*); +int _gettimeofday (struct timeval *, void*); +int _unlink (const char*); +int _link (void); + +int _stat (const char*, struct stat*); + +int _fstat (int, struct stat*); +int _swistat (int fd, struct stat* st); +int _getpid (int); +int _close (int); +clock_t _clock (void); +int _swiclose (int); +int _open (const char*, int, ...); +int _swiopen (const char*, int); +int _write (int, char*, int); +int _swiwrite (int, char*, int); +int _lseek (int, int, int); +int _swilseek (int, int, int); +int _read (int, char*, int); +int _swiread (int, char*, int); + +void initialise_monitor_handles (void); + +void __initialize_args (int* p_argc, char*** p_argv); + +static int +checkerror (int); +static int +error (int); +static int +get_errno (void); + +// ---------------------------------------------------------------------------- + +#define ARGS_BUF_ARRAY_SIZE 80 +#define ARGV_BUF_ARRAY_SIZE 10 + +typedef struct +{ + char* pCommandLine; + int size; +} CommandLineBlock; + +void __initialize_args (int* p_argc, char*** p_argv) +{ + // Array of chars to receive the command line from the host + static char args_buf[ARGS_BUF_ARRAY_SIZE]; + + // Array of pointers to store the final argv pointers (pointing + // in the above array). + static char* argv_buf[ARGV_BUF_ARRAY_SIZE]; + + int argc = 0; + int isInArgument = 0; + + CommandLineBlock cmdBlock; + cmdBlock.pCommandLine = args_buf; + cmdBlock.size = sizeof(args_buf) - 1; + + int ret = call_host (SEMIHOSTING_SYS_GET_CMDLINE, &cmdBlock); + if (ret == 0) + { + + // In case the host send more than we can chew, limit the + // string to our buffer. + args_buf[ARGS_BUF_ARRAY_SIZE - 1] = '\0'; + + // The command line is a null terminated string + char* p = cmdBlock.pCommandLine; + + int delim = '\0'; + int ch; + + while ((ch = *p) != '\0') + { + if (isInArgument == 0) + { + if (!isblank(ch)) + { + if (argc >= (int) ((sizeof(argv_buf) / sizeof(argv_buf[0])) - 1)) + break; + + if (ch == '"' || ch == '\'') + { + // Remember the delimiter to search for the + // corresponding terminator + delim = ch; + ++p; // skip the delimiter + ch = *p; + } + // Remember the arg beginning address + argv_buf[argc++] = p; + isInArgument = 1; + } + } + else if (delim != '\0') + { + if ((ch == delim)) + { + delim = '\0'; + *p = '\0'; + isInArgument = 0; + } + } + else if (isblank(ch)) + { + delim = '\0'; + *p = '\0'; + isInArgument = 0; + } + ++p; + } + } + + if (argc == 0) + { + // No args found in string, return a single empty name. + args_buf[0] = '\0'; + argv_buf[0] = &args_buf[0]; + ++argc; + } + + // Must end the array with a null pointer. + argv_buf[argc] = NULL; + + *p_argc = argc; + *p_argv = &argv_buf[0]; + + // temporary here + initialise_monitor_handles (); + + return; +} + +// ---------------------------------------------------------------------------- + +void _exit (int status) +{ + /* There is only one SWI for both _exit and _kill. For _exit, call + the SWI with the second argument set to -1, an invalid value for + signum, so that the SWI handler can distinguish the two calls. + Note: The RDI implementation of _kill throws away both its + arguments. */ + report_exception (status == 0 ? ADP_Stopped_ApplicationExit : ADP_Stopped_RunTimeError); +} + +// ---------------------------------------------------------------------------- + +int __attribute__((weak)) +_kill (int pid __attribute__((unused)), int sig __attribute__((unused))) +{ + errno = ENOSYS; + return -1; +} + +// ---------------------------------------------------------------------------- + +/* Struct used to keep track of the file position, just so we + can implement fseek(fh,x,SEEK_CUR). */ +struct fdent +{ + int handle; + int pos; +}; + +#define MAX_OPEN_FILES 20 + +/* User file descriptors (fd) are integer indexes into + the openfiles[] array. Error checking is done by using + findslot(). + + This openfiles array is manipulated directly by only + these 5 functions: + + findslot() - Translate entry. + newslot() - Find empty entry. + initilise_monitor_handles() - Initialize entries. + _swiopen() - Initialize entry. + _close() - Handle stdout == stderr case. + + Every other function must use findslot(). */ + +static struct fdent openfiles[MAX_OPEN_FILES]; + +static struct fdent* findslot (int); +static int newslot (void); + +/* Register name faking - works in collusion with the linker. */ +register char* stack_ptr asm ("sp"); + +/* following is copied from libc/stdio/local.h to check std streams */ +extern void _EXFUN(__sinit,(struct _reent*)); +#define CHECK_INIT(ptr) \ + do \ + { \ + if ((ptr) && !(ptr)->__sdidinit) \ + __sinit (ptr); \ + } \ + while (0) + +static int monitor_stdin; +static int monitor_stdout; +static int monitor_stderr; + +/* Return a pointer to the structure associated with + the user file descriptor fd. */ +static struct fdent* +findslot (int fd) +{ + CHECK_INIT(_REENT); + + /* User file descriptor is out of range. */ + if ((unsigned int) fd >= MAX_OPEN_FILES) + { + return NULL; + } + + /* User file descriptor is open? */ + if (openfiles[fd].handle == -1) + { + return NULL; + } + + /* Valid. */ + return &openfiles[fd]; +} + +/* Return the next lowest numbered free file + structure, or -1 if we can't find one. */ +static int +newslot (void) +{ + int i; + + for (i = 0; i < MAX_OPEN_FILES; i++) + { + if (openfiles[i].handle == -1) + { + break; + } + } + + if (i == MAX_OPEN_FILES) + { + return -1; + } + + return i; +} + +void +initialise_monitor_handles (void) +{ + int i; + + /* Open the standard file descriptors by opening the special + * teletype device, ":tt", read-only to obtain a descriptor for + * standard input and write-only to obtain a descriptor for standard + * output. Finally, open ":tt" in append mode to obtain a descriptor + * for standard error. Since this is a write mode, most kernels will + * probably return the same value as for standard output, but the + * kernel can differentiate the two using the mode flag and return a + * different descriptor for standard error. + */ + + int volatile block[3]; + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 0; /* mode "r" */ + monitor_stdin = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 4; /* mode "w" */ + monitor_stdout = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + block[0] = (int) ":tt"; + block[2] = 3; /* length of filename */ + block[1] = 8; /* mode "a" */ + monitor_stderr = call_host (SEMIHOSTING_SYS_OPEN, (void*) block); + + /* If we failed to open stderr, redirect to stdout. */ + if (monitor_stderr == -1) + { + monitor_stderr = monitor_stdout; + } + + for (i = 0; i < MAX_OPEN_FILES; i++) + { + openfiles[i].handle = -1; + } + + openfiles[0].handle = monitor_stdin; + openfiles[0].pos = 0; + openfiles[1].handle = monitor_stdout; + openfiles[1].pos = 0; + openfiles[2].handle = monitor_stderr; + openfiles[2].pos = 0; +} + +static int +get_errno (void) +{ + return call_host (SEMIHOSTING_SYS_ERRNO, NULL); +} + +/* Set errno and return result. */ +static int +error (int result) +{ + errno = get_errno (); + return result; +} + +/* Check the return and set errno appropriately. */ +static int +checkerror (int result) +{ + if (result == -1) + { + return error (-1); + } + + return result; +} + +/* fh, is a valid internal file handle. + ptr, is a null terminated string. + len, is the length in bytes to read. + Returns the number of bytes *not* written. */ +int +_swiread (int fh, char* ptr, int len) +{ + int block[3]; + + block[0] = fh; + block[1] = (int) ptr; + block[2] = len; + + return checkerror (call_host (SEMIHOSTING_SYS_READ, block)); +} + +/* fd, is a valid user file handle. + Translates the return of _swiread into + bytes read. */ +int +_read (int fd, char* ptr, int len) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + res = _swiread (pfd->handle, ptr, len); + + if (res == -1) + { + return res; + } + + pfd->pos += len - res; + + /* res == len is not an error, + at least if we want feof() to work. */ + return len - res; +} + +/* fd, is a user file descriptor. */ +int _swilseek (int fd, int ptr, int dir) +{ + int res; + struct fdent *pfd; + + /* Valid file descriptor? */ + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Valid whence? */ + if ((dir != SEEK_CUR) && (dir != SEEK_SET) && (dir != SEEK_END)) + { + errno = EINVAL; + return -1; + } + + /* Convert SEEK_CUR to SEEK_SET */ + if (dir == SEEK_CUR) + { + ptr = pfd->pos + ptr; + /* The resulting file offset would be negative. */ + if (ptr < 0) + { + errno = EINVAL; + if ((pfd->pos > 0) && (ptr > 0)) + { + errno = EOVERFLOW; + } + return -1; + } + dir = SEEK_SET; + } + + int block[2]; + if (dir == SEEK_END) + { + block[0] = pfd->handle; + res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, block)); + if (res == -1) + { + return -1; + } + ptr += res; + } + + /* This code only does absolute seeks. */ + block[0] = pfd->handle; + block[1] = ptr; + res = checkerror (call_host (SEMIHOSTING_SYS_SEEK, block)); + + /* At this point ptr is the current file position. */ + if (res >= 0) + { + pfd->pos = ptr; + return ptr; + } + else + { + return -1; + } +} + +int _lseek (int fd, int ptr, int dir) +{ + return _swilseek (fd, ptr, dir); +} + +/* fh, is a valid internal file handle. + Returns the number of bytes *not* written. */ +int _swiwrite (int fh, char* ptr, int len) +{ + int block[3]; + + block[0] = fh; + block[1] = (int) ptr; + block[2] = len; + + return checkerror (call_host (SEMIHOSTING_SYS_WRITE, block)); +} + +/* fd, is a user file descriptor. */ +int _write (int fd, char* ptr, int len) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + res = _swiwrite (pfd->handle, ptr, len); + + /* Clearly an error. */ + if (res < 0) + { + return -1; + } + + pfd->pos += len - res; + + /* We wrote 0 bytes? + Retrieve errno just in case. */ + if ((len - res) == 0) + { + return error (0); + } + + return (len - res); +} + +int _swiopen (const char* path, int flags) +{ + int aflags = 0, fh; + uint32_t block[3]; + + int fd = newslot (); + + if (fd == -1) + { + errno = EMFILE; + return -1; + } + + /* It is an error to open a file that already exists. */ + if ((flags & O_CREAT) && (flags & O_EXCL)) + { + struct stat st; + int res; + res = _stat (path, &st); + if (res != -1) + { + errno = EEXIST; + return -1; + } + } + + /* The flags are Unix-style, so we need to convert them. */ +#ifdef O_BINARY + if (flags & O_BINARY) + { + aflags |= 1; + } +#endif + + /* In O_RDONLY we expect aflags == 0. */ + + if (flags & O_RDWR) + { + aflags |= 2; + } + + if ((flags & O_CREAT) || (flags & O_TRUNC) || (flags & O_WRONLY)) + { + aflags |= 4; + } + + if (flags & O_APPEND) + { + /* Can't ask for w AND a; means just 'a'. */ + aflags &= ~4; + aflags |= 8; + } + + block[0] = (uint32_t) path; + block[2] = strlen (path); + block[1] = (uint32_t) aflags; + + fh = call_host (SEMIHOSTING_SYS_OPEN, block); + + /* Return a user file descriptor or an error. */ + if (fh >= 0) + { + openfiles[fd].handle = fh; + openfiles[fd].pos = 0; + return fd; + } + else + { + return error (fh); + } +} + +int _open (const char* path, int flags, ...) +{ + return _swiopen (path, flags); +} + +/* fh, is a valid internal file handle. */ +int _swiclose (int fh) +{ + return checkerror (call_host (SEMIHOSTING_SYS_CLOSE, &fh)); +} + +/* fd, is a user file descriptor. */ +int _close (int fd) +{ + int res; + struct fdent *pfd; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Handle stderr == stdout. */ + if ((fd == 1 || fd == 2) && (openfiles[1].handle == openfiles[2].handle)) + { + pfd->handle = -1; + return 0; + } + + /* Attempt to close the handle. */ + res = _swiclose (pfd->handle); + + /* Reclaim handle? */ + if (res == 0) + { + pfd->handle = -1; + } + + return res; +} + +int __attribute__((weak)) +_getpid (int n __attribute__ ((unused))) +{ + return 1; +} + +int +_swistat (int fd, struct stat* st) +{ + struct fdent *pfd; + int res; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return -1; + } + + /* Always assume a character device, + with 1024 byte blocks. */ + st->st_mode |= S_IFCHR; + st->st_blksize = 1024; + res = checkerror (call_host (SEMIHOSTING_SYS_FLEN, &pfd->handle)); + if (res == -1) + { + return -1; + } + + /* Return the file size. */ + st->st_size = res; + return 0; +} + +int __attribute__((weak)) +_fstat (int fd, struct stat* st) +{ + memset (st, 0, sizeof(*st)); + return _swistat (fd, st); +} + +int __attribute__((weak)) +_stat (const char*fname, struct stat *st) +{ + int fd, res; + memset (st, 0, sizeof(*st)); + /* The best we can do is try to open the file readonly. + If it exists, then we can guess a few things about it. */ + if ((fd = _open (fname, O_RDONLY)) == -1) + { + return -1; + } + st->st_mode |= S_IFREG | S_IREAD; + res = _swistat (fd, st); + /* Not interested in the error. */ + _close (fd); + return res; +} + +int __attribute__((weak)) +_link (void) +{ + errno = ENOSYS; + return -1; +} + +int _unlink (const char* path) +{ + int res; + uint32_t block[2]; + block[0] = (uint32_t) path; + block[1] = strlen (path); + res = call_host (SEMIHOSTING_SYS_REMOVE, block); + + if (res == -1) + { + return error (res); + } + return 0; +} + +int _gettimeofday (struct timeval* tp, void* tzvp) +{ + struct timezone* tzp = tzvp; + if (tp) + { + /* Ask the host for the seconds since the Unix epoch. */ + tp->tv_sec = call_host (SEMIHOSTING_SYS_TIME, NULL); + tp->tv_usec = 0; + } + + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} + +/* Return a clock that ticks at 100Hz. */ +clock_t _clock (void) +{ + clock_t timeval; + + timeval = (clock_t) call_host (SEMIHOSTING_SYS_CLOCK, NULL); + return timeval; +} + +/* Return a clock that ticks at 100Hz. */ +clock_t +_times (struct tms* tp) +{ + clock_t timeval = _clock (); + + if (tp) + { + tp->tms_utime = timeval; /* user time */ + tp->tms_stime = 0; /* system time */ + tp->tms_cutime = 0; /* user time, children */ + tp->tms_cstime = 0; /* system time, children */ + } + + return timeval; +} + +int _isatty (int fd) +{ + struct fdent *pfd; + int tty; + + pfd = findslot (fd); + if (pfd == NULL) + { + errno = EBADF; + return 0; + } + + tty = call_host (SEMIHOSTING_SYS_ISTTY, &pfd->handle); + + if (tty == 1) + { + return 1; + } + + errno = get_errno (); + return 0; +} + +int _system (const char* s) +{ + uint32_t block[2]; + int e; + + /* Hmmm. The ARM debug interface specification doesn't say whether + SYS_SYSTEM does the right thing with a null argument, or assign any + meaning to its return value. Try to do something reasonable.... */ + if (!s) + { + return 1; /* maybe there is a shell available? we can hope. :-P */ + } + block[0] = (uint32_t) s; + block[1] = strlen (s); + e = checkerror (call_host (SEMIHOSTING_SYS_SYSTEM, block)); + if ((e >= 0) && (e < 256)) + { + /* We have to convert e, an exit status to the encoded status of + the command. To avoid hard coding the exit status, we simply + loop until we find the right position. */ + int exit_code; + + for (exit_code = e; e && WEXITSTATUS (e) != exit_code; e <<= 1) + { + continue; + } + } + return e; +} + +int _rename (const char* oldpath, const char* newpath) +{ + uint32_t block[4]; + block[0] = (uint32_t) oldpath; + block[1] = strlen (oldpath); + block[2] = (uint32_t) newpath; + block[3] = strlen (newpath); + return checkerror (call_host (SEMIHOSTING_SYS_RENAME, block)) ? -1 : 0; +} + +// ---------------------------------------------------------------------------- +// Required by Google Tests + +int mkdir (const char *path __attribute__((unused)), mode_t mode __attribute__((unused))) +{ +#if 0 + // always return true + return 0; +#else + errno = ENOSYS; + return -1; +#endif +} + +char *getcwd (char *buf, size_t size) +{ + // no cwd available via semihosting, so we use the temporary folder + strncpy (buf, "/tmp", size); + return buf; +} + +#endif // defined OS_USE_SEMIHOSTING + +#endif // __STDC_HOSTED__ == 1 diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm.ld b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm.ld new file mode 100644 index 00000000000..43c1ee59942 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm.ld @@ -0,0 +1,195 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* 512k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x28000 /* 160k */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm_128k.ld b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm_128k.ld new file mode 100644 index 00000000000..e3d71e6f68c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/gcc_arm_128k.ld @@ -0,0 +1,195 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* 512k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000 /* 128k */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/semihosting.h b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/semihosting.h new file mode 100644 index 00000000000..337085416be --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/semihosting.h @@ -0,0 +1,116 @@ + +#ifndef ARM_SEMIHOSTING_H_ +#define ARM_SEMIHOSTING_H_ + +// ---------------------------------------------------------------------------- + +// Semihosting operations. +enum OperationNumber +{ + // Regular operations + SEMIHOSTING_EnterSVC = 0x17, + SEMIHOSTING_ReportException = 0x18, + SEMIHOSTING_SYS_CLOSE = 0x02, + SEMIHOSTING_SYS_CLOCK = 0x10, + SEMIHOSTING_SYS_ELAPSED = 0x30, + SEMIHOSTING_SYS_ERRNO = 0x13, + SEMIHOSTING_SYS_FLEN = 0x0C, + SEMIHOSTING_SYS_GET_CMDLINE = 0x15, + SEMIHOSTING_SYS_HEAPINFO = 0x16, + SEMIHOSTING_SYS_ISERROR = 0x08, + SEMIHOSTING_SYS_ISTTY = 0x09, + SEMIHOSTING_SYS_OPEN = 0x01, + SEMIHOSTING_SYS_READ = 0x06, + SEMIHOSTING_SYS_READC = 0x07, + SEMIHOSTING_SYS_REMOVE = 0x0E, + SEMIHOSTING_SYS_RENAME = 0x0F, + SEMIHOSTING_SYS_SEEK = 0x0A, + SEMIHOSTING_SYS_SYSTEM = 0x12, + SEMIHOSTING_SYS_TICKFREQ = 0x31, + SEMIHOSTING_SYS_TIME = 0x11, + SEMIHOSTING_SYS_TMPNAM = 0x0D, + SEMIHOSTING_SYS_WRITE = 0x05, + SEMIHOSTING_SYS_WRITEC = 0x03, + SEMIHOSTING_SYS_WRITE0 = 0x04, + + // Codes returned by SEMIHOSTING_ReportException + ADP_Stopped_ApplicationExit = ((2 << 16) + 38), + ADP_Stopped_RunTimeError = ((2 << 16) + 35), + +}; + +// ---------------------------------------------------------------------------- + +// SWI numbers and reason codes for RDI (Angel) monitors. +#define AngelSWI_ARM 0x123456 +#ifdef __thumb__ +#define AngelSWI 0xAB +#else +#define AngelSWI AngelSWI_ARM +#endif +// For thumb only architectures use the BKPT instruction instead of SWI. +#if defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_7EM__) \ + || defined(__ARM_ARCH_6M__) +#define AngelSWIInsn "bkpt" +#define AngelSWIAsm bkpt +#else +#define AngelSWIInsn "swi" +#define AngelSWIAsm swi +#endif + +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) +// Testing the local semihosting handler cannot use another BKPT, since this +// configuration cannot trigger HaedFault exceptions while the debugger is +// connected, so we use an illegal op code, that will trigger an +// UsageFault exception. +#define AngelSWITestFault "setend be" +#define AngelSWITestFaultOpCode (0xB658) +#endif + +static inline int +__attribute__ ((always_inline)) +call_host (int reason, void* arg) +{ + int value; + asm volatile ( + + " mov r0, %[rsn] \n" + " mov r1, %[arg] \n" +#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) + " " AngelSWITestFault " \n" +#else + " " AngelSWIInsn " %[swi] \n" +#endif + " mov %[val], r0" + + : [val] "=r" (value) /* Outputs */ + : [rsn] "r" (reason), [arg] "r" (arg), [swi] "i" (AngelSWI) /* Inputs */ + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" + // Clobbers r0 and r1, and lr if in supervisor mode + ); + + // Accordingly to page 13-77 of ARM DUI 0040D other registers + // can also be clobbered. Some memory positions may also be + // changed by a system call, so they should not be kept in + // registers. Note: we are assuming the manual is right and + // Angel is respecting the APCS. + return value; +} + +// ---------------------------------------------------------------------------- + +// Function used in _exit() to return the status code as Angel exception. +static inline void +__attribute__ ((always_inline,noreturn)) +report_exception (int reason) +{ + call_host (SEMIHOSTING_ReportException, (void*) reason); + + for (;;) + ; +} + +// ---------------------------------------------------------------------------- + +#endif // ARM_SEMIHOSTING_H_ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup.s b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup.s new file mode 100644 index 00000000000..00fdcf9cf37 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup.s @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + // Unlock Register + ldr r0, =0x40000100 + ldr r1, =0x59 + str r1, [r0] + ldr r1, =0x16 + str r1, [r0] + ldr r1, =0x88 + str r1, [r0] + + // ENABLE_SPIM_CACHE + ldr r0, =0x40000200 // R0 = Clock Controller Register Base Address + ldr r1, [r0,#0x4] // R1 = 0x40000204 (AHBCLK) + orr r1, r1, #0x4000 + str r1, [r0,#0x4] // CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk// + + ldr r0, =0x40007000 // R0 = SPIM Register Base Address + ldr r1, [r0,#4] // R1 = SPIM->CTL1 + orr r1, r1,#2 // R1 |= SPIM_CTL1_CACHEOFF_Msk + str r1, [r0,#4] // _SPIM_DISABLE_CACHE() + ldr r1, [r0,#4] // R1 = SPIM->CTL1 + orr r1, r1, #4 // R1 |= SPIM_CTL1_CCMEN_Msk + str r1, [r0,#4] // _SPIM_ENABLE_CCM() + + // Lock + ldr r0, =0x40000100 + ldr r1, =0 + str r1, [r0] + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the application's entry point.*/ + bl entry + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack // Top of Stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word MemManage_Handler // MPU Fault Handler + .word BusFault_Handler // Bus Fault Handler + .word UsageFault_Handler // Usage Fault Handler + .word 0 // Reserved + .word 0 // DCDReserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word DebugMon_Handler // Debug Monitor Handler + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + + // External Interrupts + .word BOD_IRQHandler // 0: Brown Out detection + .word IRC_IRQHandler // 1: Internal RC + .word PWRWU_IRQHandler // 2: Power down wake up + .word RAMPE_IRQHandler // 3: RAM parity error + .word CKFAIL_IRQHandler // 4: Clock detection fail + .word Default_Handler // 5: Reserved + .word RTC_IRQHandler // 6: Real Time Clock + .word TAMPER_IRQHandler // 7: Tamper detection + .word WDT_IRQHandler // 8: Watchdog timer + .word WWDT_IRQHandler // 9: Window watchdog timer + .word EINT0_IRQHandler // 10: External Input 0 + .word EINT1_IRQHandler // 11: External Input 1 + .word EINT2_IRQHandler // 12: External Input 2 + .word EINT3_IRQHandler // 13: External Input 3 + .word EINT4_IRQHandler // 14: External Input 4 + .word EINT5_IRQHandler // 15: External Input 5 + .word GPA_IRQHandler // 16: GPIO Port A + .word GPB_IRQHandler // 17: GPIO Port B + .word GPC_IRQHandler // 18: GPIO Port C + .word GPD_IRQHandler // 19: GPIO Port D + .word GPE_IRQHandler // 20: GPIO Port E + .word GPF_IRQHandler // 21: GPIO Port F + .word QSPI0_IRQHandler // 22: QSPI0 + .word SPI0_IRQHandler // 23: SPI0 + .word BRAKE0_IRQHandler // 24: + .word EPWM0P0_IRQHandler // 25: + .word EPWM0P1_IRQHandler // 26: + .word EPWM0P2_IRQHandler // 27: + .word BRAKE1_IRQHandler // 28: + .word EPWM1P0_IRQHandler // 29: + .word EPWM1P1_IRQHandler // 30: + .word EPWM1P2_IRQHandler // 31: + .word TMR0_IRQHandler // 32: Timer 0 + .word TMR1_IRQHandler // 33: Timer 1 + .word TMR2_IRQHandler // 34: Timer 2 + .word TMR3_IRQHandler // 35: Timer 3 + .word UART0_IRQHandler // 36: UART0 + .word UART1_IRQHandler // 37: UART1 + .word I2C0_IRQHandler // 38: I2C0 + .word I2C1_IRQHandler // 39: I2C1 + .word PDMA_IRQHandler // 40: Peripheral DMA + .word DAC_IRQHandler // 41: DAC + .word ADC00_IRQHandler // 42: ADC0 interrupt source 0 + .word ADC01_IRQHandler // 43: ADC0 interrupt source 1 + .word ACMP01_IRQHandler // 44: ACMP0 and ACMP1 + .word Default_Handler // 45: Reserved + .word ADC02_IRQHandler // 46: ADC0 interrupt source 2 + .word ADC03_IRQHandler // 47: ADC0 interrupt source 3 + .word UART2_IRQHandler // 48: UART2 + .word UART3_IRQHandler // 49: UART3 + .word Default_Handler // 50: Reserved + .word SPI1_IRQHandler // 51: SPI1 + .word SPI2_IRQHandler // 52: SPI2 + .word USBD_IRQHandler // 53: USB device + .word OHCI_IRQHandler // 54: OHCI + .word USBOTG_IRQHandler // 55: USB OTG + .word CAN0_IRQHandler // 56: CAN0 + .word CAN1_IRQHandler // 57: CAN1 + .word SC0_IRQHandler // 58: + .word SC1_IRQHandler // 59: + .word SC2_IRQHandler // 60: + .word Default_Handler // 61: + .word SPI3_IRQHandler // 62: SPI3 + .word Default_Handler // 63: + .word SDH0_IRQHandler // 64: SDH0 + .word USBD20_IRQHandler // 65: USBD20 + .word EMAC_TX_IRQHandler // 66: EMAC_TX + .word EMAC_RX_IRQHandler // 67: EMAX_RX + .word I2S0_IRQHandler // 68: I2S0 + .word Default_Handler // 69: ToDo: Add description to this Interrupt + .word OPA0_IRQHandler // 70: OPA0 + .word CRYPTO_IRQHandler // 71: CRYPTO + .word GPG_IRQHandler // 72: + .word EINT6_IRQHandler // 73: + .word UART4_IRQHandler // 74: UART4 + .word UART5_IRQHandler // 75: UART5 + .word USCI0_IRQHandler // 76: USCI0 + .word USCI1_IRQHandler // 77: USCI1 + .word BPWM0_IRQHandler // 78: BPWM0 + .word BPWM1_IRQHandler // 79: BPWM1 + .word SPIM_IRQHandler // 80: SPIM + .word Default_Handler // 81: ToDo: Add description to this Interrupt + .word I2C2_IRQHandler // 82: I2C2 + .word Default_Handler // 83: + .word QEI0_IRQHandler // 84: QEI0 + .word QEI1_IRQHandler // 85: QEI1 + .word ECAP0_IRQHandler // 86: ECAP0 + .word ECAP1_IRQHandler // 87: ECAP1 + .word GPH_IRQHandler // 88: + .word EINT7_IRQHandler // 89: + .word SDH1_IRQHandler // 90: SDH1 + .word Default_Handler // 91: + .word EHCI_IRQHandler // 92: EHCI + .word USBOTG20_IRQHandler // 93: + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler BOD_IRQHandler + def_irq_handler IRC_IRQHandler + def_irq_handler PWRWU_IRQHandler + def_irq_handler RAMPE_IRQHandler + def_irq_handler CKFAIL_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TAMPER_IRQHandler + def_irq_handler WDT_IRQHandler + def_irq_handler WWDT_IRQHandler + def_irq_handler EINT0_IRQHandler + def_irq_handler EINT1_IRQHandler + def_irq_handler EINT2_IRQHandler + def_irq_handler EINT3_IRQHandler + def_irq_handler EINT4_IRQHandler + def_irq_handler EINT5_IRQHandler + def_irq_handler GPA_IRQHandler + def_irq_handler GPB_IRQHandler + def_irq_handler GPC_IRQHandler + def_irq_handler GPD_IRQHandler + def_irq_handler GPE_IRQHandler + def_irq_handler GPF_IRQHandler + def_irq_handler QSPI0_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler BRAKE0_IRQHandler + def_irq_handler EPWM0P0_IRQHandler + def_irq_handler EPWM0P1_IRQHandler + def_irq_handler EPWM0P2_IRQHandler + def_irq_handler BRAKE1_IRQHandler + def_irq_handler EPWM1P0_IRQHandler + def_irq_handler EPWM1P1_IRQHandler + def_irq_handler EPWM1P2_IRQHandler + def_irq_handler TMR0_IRQHandler + def_irq_handler TMR1_IRQHandler + def_irq_handler TMR2_IRQHandler + def_irq_handler TMR3_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler PDMA_IRQHandler + def_irq_handler DAC_IRQHandler + def_irq_handler ADC00_IRQHandler + def_irq_handler ADC01_IRQHandler + def_irq_handler ACMP01_IRQHandler + def_irq_handler ADC02_IRQHandler + def_irq_handler ADC03_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler SPI2_IRQHandler + def_irq_handler USBD_IRQHandler + def_irq_handler OHCI_IRQHandler + def_irq_handler USBOTG_IRQHandler + def_irq_handler CAN0_IRQHandler + def_irq_handler CAN1_IRQHandler + def_irq_handler SC0_IRQHandler + def_irq_handler SC1_IRQHandler + def_irq_handler SC2_IRQHandler + def_irq_handler SPI3_IRQHandler + def_irq_handler SDH0_IRQHandler + def_irq_handler USBD20_IRQHandler + def_irq_handler EMAC_TX_IRQHandler + def_irq_handler EMAC_RX_IRQHandler + def_irq_handler I2S0_IRQHandler + def_irq_handler OPA0_IRQHandler + def_irq_handler CRYPTO_IRQHandler + def_irq_handler GPG_IRQHandler + def_irq_handler EINT6_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler UART5_IRQHandler + def_irq_handler USCI0_IRQHandler + def_irq_handler USCI1_IRQHandler + def_irq_handler BPWM0_IRQHandler + def_irq_handler BPWM1_IRQHandler + def_irq_handler SPIM_IRQHandler + def_irq_handler I2C2_IRQHandler + def_irq_handler QEI0_IRQHandler + def_irq_handler QEI1_IRQHandler + def_irq_handler ECAP0_IRQHandler + def_irq_handler ECAP1_IRQHandler + def_irq_handler GPH_IRQHandler + def_irq_handler EINT7_IRQHandler + def_irq_handler SDH1_IRQHandler + def_irq_handler EHCI_IRQHandler + def_irq_handler USBOTG20_IRQHandler diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup_M480.S b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup_M480.S new file mode 100644 index 00000000000..ee59ad37842 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/GCC/startup_M480.S @@ -0,0 +1,449 @@ +/****************************************************************************//** + * @file startup_M480.S + * @version V1.00 + * @brief CMSIS Cortex-M4 Core Device Startup File for M480 + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + + + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00000800 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000100 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long BOD_IRQHandler /* 0: BOD */ + .long IRC_IRQHandler /* 1: IRC */ + .long PWRWU_IRQHandler /* 2: PWRWU */ + .long RAMPE_IRQHandler /* 3: RAMPE */ + .long CKFAIL_IRQHandler /* 4: CKFAIL */ + .long 0 /* 5: Reserved */ + .long RTC_IRQHandler /* 6: RTC */ + .long TAMPER_IRQHandler /* 7: TAMPER */ + .long WDT_IRQHandler /* 8: WDT */ + .long WWDT_IRQHandler /* 9: WWDT */ + .long EINT0_IRQHandler /* 10: EINT0 */ + .long EINT1_IRQHandler /* 11: EINT1 */ + .long EINT2_IRQHandler /* 12: EINT2 */ + .long EINT3_IRQHandler /* 13: EINT3 */ + .long EINT4_IRQHandler /* 14: EINT4 */ + .long EINT5_IRQHandler /* 15: EINT5 */ + .long GPA_IRQHandler /* 16: GPA */ + .long GPB_IRQHandler /* 17: GPB */ + .long GPC_IRQHandler /* 18: GPC */ + .long GPD_IRQHandler /* 19: GPD */ + .long GPE_IRQHandler /* 20: GPE */ + .long GPF_IRQHandler /* 21: GPF */ + .long QSPI0_IRQHandler /* 22: QSPI0 */ + .long SPI0_IRQHandler /* 23: SPI0 */ + .long BRAKE0_IRQHandler /* 24: BRAKE0 */ + .long EPWM0P0_IRQHandler /* 25: EPWM0P0 */ + .long EPWM0P1_IRQHandler /* 26: EPWM0P1 */ + .long EPWM0P2_IRQHandler /* 27: EPWM0P2 */ + .long BRAKE1_IRQHandler /* 28: BRAKE1 */ + .long EPWM1P0_IRQHandler /* 29: EPWM1P0 */ + .long EPWM1P1_IRQHandler /* 30: EPWM1P1 */ + .long EPWM1P2_IRQHandler /* 31: EPWM1P2 */ + .long TMR0_IRQHandler /* 32: TIMER0 */ + .long TMR1_IRQHandler /* 33: TIMER1 */ + .long TMR2_IRQHandler /* 34: TIMER2 */ + .long TMR3_IRQHandler /* 35: TIMER3 */ + .long UART0_IRQHandler /* 36: UART0 */ + .long UART1_IRQHandler /* 37: UART1 */ + .long I2C0_IRQHandler /* 38: I2C0 */ + .long I2C1_IRQHandler /* 39: I2C1 */ + .long PDMA_IRQHandler /* 40: PDMA */ + .long DAC_IRQHandler /* 41: DAC */ + .long ADC00_IRQHandler /* 42: ADC00 */ + .long ADC01_IRQHandler /* 43: ADC01 */ + .long ACMP01_IRQHandler /* 44: ACMP */ + .long 0 /* 45: Reserved */ + .long ADC02_IRQHandler /* 46: ADC02 */ + .long ADC03_IRQHandler /* 47: ADC03 */ + .long UART2_IRQHandler /* 48: UART2 */ + .long UART3_IRQHandler /* 49: UART3 */ + .long 0 /* 50: Reserved */ + .long SPI1_IRQHandler /* 51: SPI1 */ + .long SPI2_IRQHandler /* 52: SPI2 */ + .long USBD_IRQHandler /* 53: USBD */ + .long OHCI_IRQHandler /* 54: OHCI */ + .long USBOTG_IRQHandler /* 55: OTG */ + .long CAN0_IRQHandler /* 56: CAN0 */ + .long CAN1_IRQHandler /* 57: CAN1 */ + .long SC0_IRQHandler /* 58: SC0 */ + .long SC1_IRQHandler /* 59: SC1 */ + .long SC2_IRQHandler /* 60: SC2 */ + .long 0 /* 61: Reserved */ + .long SPI3_IRQHandler /* 62: SPI3 */ + .long 0 /* 63: Reserved */ + .long SDH0_IRQHandler /* 64: SDH0 */ + .long USBD20_IRQHandler /* 65: HSUSBD */ + .long EMAC_TX_IRQHandler /* 66: EMAC_TX */ + .long EMAC_RX_IRQHandler /* 67: EMAC_RX */ + .long I2S0_IRQHandler /* 68: I2S */ + .long 0 /* 69: Reserved */ + .long OPA0_IRQHandler /* 70: OPA */ + .long CRYPTO_IRQHandler /* 71: CRYPTO */ + .long GPG_IRQHandler /* 72: GPG */ + .long EINT6_IRQHandler /* 73: EINT6 */ + .long UART4_IRQHandler /* 74: UART4 */ + .long UART5_IRQHandler /* 75: UART5 */ + .long USCI0_IRQHandler /* 76: USCI0 */ + .long USCI1_IRQHandler /* 77: USCI1 */ + .long BPWM0_IRQHandler /* 78: BPWM0 */ + .long BPWM1_IRQHandler /* 79: BPWM1 */ + .long SPIM_IRQHandler /* 80: SPIM */ + .long 0 /* 81: Reserved */ + .long I2C2_IRQHandler /* 82: I2C2 */ + .long 0 /* 83: Reserved */ + .long QEI0_IRQHandler /* 84: QEI0 */ + .long QEI1_IRQHandler /* 85: QEI1 */ + .long ECAP0_IRQHandler /* 86: ECAP0 */ + .long ECAP1_IRQHandler /* 87: ECAP1 */ + .long GPH_IRQHandler /* 88: GPH */ + .long EINT7_IRQHandler /* 89: EINT7 */ + .long SDH1_IRQHandler /* 90: SDH1 */ + .long 0 /* 91: Reserved */ + .long EHCI_IRQHandler /* 92: EHCI */ + .long USBOTG20_IRQHandler /* 93: HSOTG */ + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +/* Unlock Register */ + ldr r0, =0x40000100 + ldr r1, =0x59 + str r1, [r0] + ldr r1, =0x16 + str r1, [r0] + ldr r1, =0x88 + str r1, [r0] + +#ifndef ENABLE_SPIM_CACHE + ldr r0, =0x40000200 /* R0 = Clock Controller Register Base Address */ + ldr r1, [r0,#0x4] /* R1 = 0x40000204 (AHBCLK) */ + orr r1, r1, #0x4000 + str r1, [r0,#0x4] /* CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; */ + + ldr r0, =0x40007000 /* R0 = SPIM Register Base Address */ + ldr r1, [r0,#4] /* R1 = SPIM->CTL1 */ + orr r1, r1,#2 /* R1 |= SPIM_CTL1_CACHEOFF_Msk */ + str r1, [r0,#4] /* _SPIM_DISABLE_CACHE() */ + ldr r1, [r0,#4] /* R1 = SPIM->CTL1 */ + orr r1, r1, #4 /* R1 |= SPIM_CTL1_CCMEN_Msk */ + str r1, [r0,#4] /* _SPIM_ENABLE_CCM() */ +#endif + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +/* Init POR */ +#if 0 + ldr r0, =0x40000024 + ldr r1, =0x00005AA5 + str r1, [r0] +#endif + +/* Lock register */ + ldr r0, =0x40000100 + ldr r1, =0 + str r1, [r0] + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler BOD_IRQHandler + def_irq_handler IRC_IRQHandler + def_irq_handler PWRWU_IRQHandler + def_irq_handler RAMPE_IRQHandler + def_irq_handler CKFAIL_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TAMPER_IRQHandler + def_irq_handler WDT_IRQHandler + def_irq_handler WWDT_IRQHandler + def_irq_handler EINT0_IRQHandler + def_irq_handler EINT1_IRQHandler + def_irq_handler EINT2_IRQHandler + def_irq_handler EINT3_IRQHandler + def_irq_handler EINT4_IRQHandler + def_irq_handler EINT5_IRQHandler + def_irq_handler GPA_IRQHandler + def_irq_handler GPB_IRQHandler + def_irq_handler GPC_IRQHandler + def_irq_handler GPD_IRQHandler + def_irq_handler GPE_IRQHandler + def_irq_handler GPF_IRQHandler + def_irq_handler QSPI0_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler BRAKE0_IRQHandler + def_irq_handler EPWM0P0_IRQHandler + def_irq_handler EPWM0P1_IRQHandler + def_irq_handler EPWM0P2_IRQHandler + def_irq_handler BRAKE1_IRQHandler + def_irq_handler EPWM1P0_IRQHandler + def_irq_handler EPWM1P1_IRQHandler + def_irq_handler EPWM1P2_IRQHandler + def_irq_handler TMR0_IRQHandler + def_irq_handler TMR1_IRQHandler + def_irq_handler TMR2_IRQHandler + def_irq_handler TMR3_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler PDMA_IRQHandler + def_irq_handler DAC_IRQHandler + def_irq_handler ADC00_IRQHandler + def_irq_handler ADC01_IRQHandler + def_irq_handler ACMP01_IRQHandler + def_irq_handler ADC02_IRQHandler + def_irq_handler ADC03_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler SPI2_IRQHandler + def_irq_handler USBD_IRQHandler + def_irq_handler OHCI_IRQHandler + def_irq_handler USBOTG_IRQHandler + def_irq_handler CAN0_IRQHandler + def_irq_handler CAN1_IRQHandler + def_irq_handler SC0_IRQHandler + def_irq_handler SC1_IRQHandler + def_irq_handler SC2_IRQHandler + def_irq_handler SPI3_IRQHandler + def_irq_handler SDH0_IRQHandler + def_irq_handler USBD20_IRQHandler + def_irq_handler EMAC_TX_IRQHandler + def_irq_handler EMAC_RX_IRQHandler + def_irq_handler I2S0_IRQHandler + def_irq_handler OPA0_IRQHandler + def_irq_handler CRYPTO_IRQHandler + def_irq_handler GPG_IRQHandler + def_irq_handler EINT6_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler UART5_IRQHandler + def_irq_handler USCI0_IRQHandler + def_irq_handler USCI1_IRQHandler + def_irq_handler BPWM0_IRQHandler + def_irq_handler BPWM1_IRQHandler + def_irq_handler SPIM_IRQHandler + def_irq_handler I2C2_IRQHandler + def_irq_handler QEI0_IRQHandler + def_irq_handler QEI1_IRQHandler + def_irq_handler ECAP0_IRQHandler + def_irq_handler ECAP1_IRQHandler + def_irq_handler GPH_IRQHandler + def_irq_handler EINT7_IRQHandler + def_irq_handler SDH1_IRQHandler + def_irq_handler EHCI_IRQHandler + def_irq_handler USBOTG20_IRQHandler + + .end diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/IAR/startup_M480.s b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/IAR/startup_M480.s new file mode 100644 index 00000000000..42ae7c2214e --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/IAR/startup_M480.s @@ -0,0 +1,416 @@ +;/****************************************************************************** +; * @file startup_M480.s +; * @version V1.00 +; * @brief CMSIS Cortex-M4 Core Device Startup File for M480 +; * +; * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +;*****************************************************************************/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN HardFault_Handler + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD BOD_IRQHandler ; 0: Brown Out detection + DCD IRC_IRQHandler ; 1: Internal RC + DCD PWRWU_IRQHandler ; 2: Power down wake up + DCD RAMPE_IRQHandler ; 3: RAM parity error + DCD CKFAIL_IRQHandler ; 4: Clock detection fail + DCD Default_Handler ; 5: Reserved + DCD RTC_IRQHandler ; 6: Real Time Clock + DCD TAMPER_IRQHandler ; 7: Tamper detection + DCD WDT_IRQHandler ; 8: Watchdog timer + DCD WWDT_IRQHandler ; 9: Window watchdog timer + DCD EINT0_IRQHandler ; 10: External Input 0 + DCD EINT1_IRQHandler ; 11: External Input 1 + DCD EINT2_IRQHandler ; 12: External Input 2 + DCD EINT3_IRQHandler ; 13: External Input 3 + DCD EINT4_IRQHandler ; 14: External Input 4 + DCD EINT5_IRQHandler ; 15: External Input 5 + DCD GPA_IRQHandler ; 16: GPIO Port A + DCD GPB_IRQHandler ; 17: GPIO Port B + DCD GPC_IRQHandler ; 18: GPIO Port C + DCD GPD_IRQHandler ; 19: GPIO Port D + DCD GPE_IRQHandler ; 20: GPIO Port E + DCD GPF_IRQHandler ; 21: GPIO Port F + DCD QSPI0_IRQHandler ; 22: QSPI0 + DCD SPI0_IRQHandler ; 23: SPI0 + DCD BRAKE0_IRQHandler ; 24: + DCD PWM0P0_IRQHandler ; 25: + DCD PWM0P1_IRQHandler ; 26: + DCD PWM0P2_IRQHandler ; 27: + DCD BRAKE1_IRQHandler ; 28: + DCD PWM1P0_IRQHandler ; 29: + DCD PWM1P1_IRQHandler ; 30: + DCD PWM1P2_IRQHandler ; 31: + DCD TMR0_IRQHandler ; 32: Timer 0 + DCD TMR1_IRQHandler ; 33: Timer 1 + DCD TMR2_IRQHandler ; 34: Timer 2 + DCD TMR3_IRQHandler ; 35: Timer 3 + DCD UART0_IRQHandler ; 36: UART0 + DCD UART1_IRQHandler ; 37: UART1 + DCD I2C0_IRQHandler ; 38: I2C0 + DCD I2C1_IRQHandler ; 39: I2C1 + DCD PDMA_IRQHandler ; 40: Peripheral DMA + DCD DAC_IRQHandler ; 41: DAC + DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0 + DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1 + DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1 + DCD Default_Handler ; 45: Reserved + DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2 + DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3 + DCD UART2_IRQHandler ; 48: UART2 + DCD UART3_IRQHandler ; 49: UART3 + DCD Default_Handler ; 50: Reserved + DCD SPI1_IRQHandler ; 51: SPI1 + DCD SPI2_IRQHandler ; 52: SPI2 + DCD USBD_IRQHandler ; 53: USB device + DCD OHCI_IRQHandler ; 54: OHCI + DCD USBOTG_IRQHandler ; 55: USB OTG + DCD CAN0_IRQHandler ; 56: CAN0 + DCD CAN1_IRQHandler ; 57: CAN1 + DCD SC0_IRQHandler ; 58: + DCD SC1_IRQHandler ; 59: + DCD SC2_IRQHandler ; 60: + DCD Default_Handler ; 61: + DCD SPI3_IRQHandler ; 62: SPI3 + DCD Default_Handler ; 63: + DCD SDH0_IRQHandler ; 64: SDH0 + DCD USBD20_IRQHandler ; 65: USBD20 + DCD EMAC_TX_IRQHandler ; 66: EMAC_TX + DCD EMAC_RX_IRQHandler ; 67: EMAX_RX + DCD I2S0_IRQHandler ; 68: I2S0 + DCD Default_Handler ; 69: ToDo: Add description to this Interrupt + DCD OPA0_IRQHandler ; 70: OPA0 + DCD CRYPTO_IRQHandler ; 71: CRYPTO + DCD GPG_IRQHandler ; 72: + DCD EINT6_IRQHandler ; 73: + DCD UART4_IRQHandler ; 74: UART4 + DCD UART5_IRQHandler ; 75: UART5 + DCD USCI0_IRQHandler ; 76: USCI0 + DCD USCI1_IRQHandler ; 77: USCI1 + DCD BPWM0_IRQHandler ; 78: BPWM0 + DCD BPWM1_IRQHandler ; 79: BPWM1 + DCD SPIM_IRQHandler ; 80: SPIM + DCD Default_Handler ; 81: ToDo: Add description to this Interrupt + DCD I2C2_IRQHandler ; 82: I2C2 + DCD Default_Handler ; 83: + DCD QEI0_IRQHandler ; 84: QEI0 + DCD QEI1_IRQHandler ; 85: QEI1 + DCD ECAP0_IRQHandler ; 86: ECAP0 + DCD ECAP1_IRQHandler ; 87: ECAP1 + DCD GPH_IRQHandler ; 88: + DCD EINT7_IRQHandler ; 89: + DCD SDH1_IRQHandler ; 90: SDH1 + DCD Default_Handler ; 91: + DCD EHCI_IRQHandler ; 92: EHCI + DCD USBOTG20_IRQHandler ; 93: +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + ; Unlock Register + LDR R0, =0x40000100 + LDR R1, =0x59 + STR R1, [R0] + LDR R1, =0x16 + STR R1, [R0] + LDR R1, =0x88 + STR R1, [R0] + + #ifndef ENABLE_SPIM_CACHE + LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address + LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK) + ORR R1, R1, #0x4000 + STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; + + LDR R0, =0x40007000 ; R0 = SPIM Register Base Address + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk + STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE() + LDR R1, [R0,#4] ; R1 = SPIM->CTL1 + ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk + STR R1, [R0,#4] ; _SPIM_ENABLE_CCM() + #endif + + LDR R0, =SystemInit + BLX R0 + + ; Init POR + ; LDR R2, =0x40000024 + ; LDR R1, =0x00005AA5 + ; STR R1, [R2] + + ; Lock register + LDR R0, =0x40000100 + MOVS R1, #0 + STR R1, [R0] + + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK BOD_IRQHandler + PUBWEAK IRC_IRQHandler + PUBWEAK PWRWU_IRQHandler + PUBWEAK RAMPE_IRQHandler + PUBWEAK CKFAIL_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK TAMPER_IRQHandler + PUBWEAK WDT_IRQHandler + PUBWEAK WWDT_IRQHandler + PUBWEAK EINT0_IRQHandler + PUBWEAK EINT1_IRQHandler + PUBWEAK EINT2_IRQHandler + PUBWEAK EINT3_IRQHandler + PUBWEAK EINT4_IRQHandler + PUBWEAK EINT5_IRQHandler + PUBWEAK GPA_IRQHandler + PUBWEAK GPB_IRQHandler + PUBWEAK GPC_IRQHandler + PUBWEAK GPD_IRQHandler + PUBWEAK GPE_IRQHandler + PUBWEAK GPF_IRQHandler + PUBWEAK QSPI0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK BRAKE0_IRQHandler + PUBWEAK PWM0P0_IRQHandler + PUBWEAK PWM0P1_IRQHandler + PUBWEAK PWM0P2_IRQHandler + PUBWEAK BRAKE1_IRQHandler + PUBWEAK PWM1P0_IRQHandler + PUBWEAK PWM1P1_IRQHandler + PUBWEAK PWM1P2_IRQHandler + PUBWEAK TMR0_IRQHandler + PUBWEAK TMR1_IRQHandler + PUBWEAK TMR2_IRQHandler + PUBWEAK TMR3_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK PDMA_IRQHandler + PUBWEAK DAC_IRQHandler + PUBWEAK ADC00_IRQHandler + PUBWEAK ADC01_IRQHandler + PUBWEAK ACMP01_IRQHandler + PUBWEAK ADC02_IRQHandler + PUBWEAK ADC03_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK UART3_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI2_IRQHandler + PUBWEAK USBD_IRQHandler + PUBWEAK OHCI_IRQHandler + PUBWEAK USBOTG_IRQHandler + PUBWEAK CAN0_IRQHandler + PUBWEAK CAN1_IRQHandler + PUBWEAK SC0_IRQHandler + PUBWEAK SC1_IRQHandler + PUBWEAK SC2_IRQHandler + PUBWEAK SPI3_IRQHandler + PUBWEAK SDH0_IRQHandler + PUBWEAK USBD20_IRQHandler + PUBWEAK EMAC_TX_IRQHandler + PUBWEAK EMAC_RX_IRQHandler + PUBWEAK I2S0_IRQHandler + PUBWEAK OPA0_IRQHandler + PUBWEAK CRYPTO_IRQHandler + PUBWEAK GPG_IRQHandler + PUBWEAK EINT6_IRQHandler + PUBWEAK UART4_IRQHandler + PUBWEAK UART5_IRQHandler + PUBWEAK USCI0_IRQHandler + PUBWEAK USCI1_IRQHandler + PUBWEAK BPWM0_IRQHandler + PUBWEAK BPWM1_IRQHandler + PUBWEAK SPIM_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK QEI0_IRQHandler + PUBWEAK QEI1_IRQHandler + PUBWEAK ECAP0_IRQHandler + PUBWEAK ECAP1_IRQHandler + PUBWEAK GPH_IRQHandler + PUBWEAK EINT7_IRQHandler + PUBWEAK SDH1_IRQHandler + PUBWEAK EHCI_IRQHandler + PUBWEAK USBOTG20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) + +BOD_IRQHandler +IRC_IRQHandler +PWRWU_IRQHandler +RAMPE_IRQHandler +CKFAIL_IRQHandler +RTC_IRQHandler +TAMPER_IRQHandler +WDT_IRQHandler +WWDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +EINT4_IRQHandler +EINT5_IRQHandler +GPA_IRQHandler +GPB_IRQHandler +GPC_IRQHandler +GPD_IRQHandler +GPE_IRQHandler +GPF_IRQHandler +QSPI0_IRQHandler +SPI0_IRQHandler +BRAKE0_IRQHandler +PWM0P0_IRQHandler +PWM0P1_IRQHandler +PWM0P2_IRQHandler +BRAKE1_IRQHandler +PWM1P0_IRQHandler +PWM1P1_IRQHandler +PWM1P2_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +PDMA_IRQHandler +DAC_IRQHandler +ADC00_IRQHandler +ADC01_IRQHandler +ACMP01_IRQHandler +ADC02_IRQHandler +ADC03_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USBD_IRQHandler +OHCI_IRQHandler +USBOTG_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +SC0_IRQHandler +SC1_IRQHandler +SC2_IRQHandler +SPI3_IRQHandler +SDH0_IRQHandler +USBD20_IRQHandler +EMAC_TX_IRQHandler +EMAC_RX_IRQHandler +I2S0_IRQHandler +OPA0_IRQHandler +CRYPTO_IRQHandler +GPG_IRQHandler +EINT6_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +USCI0_IRQHandler +USCI1_IRQHandler +BPWM0_IRQHandler +BPWM1_IRQHandler +SPIM_IRQHandler +I2C2_IRQHandler +QEI0_IRQHandler +QEI1_IRQHandler +ECAP0_IRQHandler +ECAP1_IRQHandler +GPH_IRQHandler +EINT7_IRQHandler +SDH1_IRQHandler +EHCI_IRQHandler +USBOTG20_IRQHandler +Default_Handler + B Default_Handler + + + + + END +;/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/system_M480.c b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/system_M480.c new file mode 100644 index 00000000000..cad72aca2d3 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/Nuvoton/M480/Source/system_M480.c @@ -0,0 +1,109 @@ +/**************************************************************************//** + * @file system_M480.c + * @version V1.000 + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480 + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ +uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */ +uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */ +uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC}; + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t u32Freq, u32ClkSrc; + uint32_t u32HclkDiv; + + /* Update PLL Clock */ + PllClock = CLK_GetPLLClockFreq(); + + u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; + + if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL) + { + /* Use PLL clock */ + u32Freq = PllClock; + } + else + { + /* Use the clock sources directly */ + u32Freq = gau32ClkSrcTbl[u32ClkSrc]; + } + + u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL; + + /* Update System Core Clock */ + SystemCoreClock = u32Freq / u32HclkDiv; + + + //if(SystemCoreClock == 0) + // __BKPT(0); + + CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL; +} + +/** + * @brief Set PF.2 and PF.3 to input mode + * @param None + * @return None + * @details GPIO default state could be configured as input or quasi through user config. + * To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes + * PF.2 and PF.3 to input mode no matter which mode they are working at. + */ +static __INLINE void HXTInit(void) +{ + PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk); + +} + +/** + * @brief Initialize the System + * + * @param none + * @return none + */ +void SystemInit (void) +{ + /* Add your system initialize code here. + Do not use global variables because this function is called before + reaching pre-main. RW section maybe overwritten afterwards. */ + + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + + /* Set access cycle for CPU @ 192MHz */ + FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos); + /* Configure power down bias, must set 1 before entering power down mode. + So set it at the very beginning */ + CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk; + /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */ + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; + RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk | + RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk); + RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk | + RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk); + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; + HXTInit(); + +} +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/Device/SConscript b/bsp/nuvoton_m487/libraries/Device/SConscript new file mode 100644 index 00000000000..30f12589f7c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/Device/SConscript @@ -0,0 +1,25 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +Nuvoton/M480/Source/system_M480.c +""") + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['Nuvoton/M480/Source/GCC/startup.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['Nuvoton/M480/Source/ARM/startup_M480.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['Nuvoton/M480/Source/IAR/startup_M480.s'] + +path = [cwd + '/Nuvoton/M480/Include',] + +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nuvoton_m487/libraries/SConscript b/bsp/nuvoton_m487/libraries/SConscript new file mode 100644 index 00000000000..4c815c49b83 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton_m487/libraries/StdDriver/SConscript b/bsp/nuvoton_m487/libraries/StdDriver/SConscript new file mode 100644 index 00000000000..97f035b6a17 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*src/*.c') + Glob('src/*.cpp') +CPPPATH = [cwd + '/inc'] + +group = DefineGroup('M487_StdPeriph', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/acmp.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/acmp.h new file mode 100644 index 00000000000..1a1d577c22b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/acmp.h @@ -0,0 +1,414 @@ +/**************************************************************************//** + * @file ACMP.h + * @version V1.00 + * @brief M480 Series ACMP Driver Header File + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __ACMP_H__ +#define __ACMP_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_CTL_FILTSEL_OFF (0UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for filter function disabled. \hideinitializer */ +#define ACMP_CTL_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 1 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 2 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 4 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 8 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 16 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 32 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 64 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_INTPOL_RF (0UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_INTPOL_R (1UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_INTPOL_F (2UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_POSSEL_P0 (0UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P1 (1UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P2 (2UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P3 (3UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_NEGSEL_PIN (0UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_CRV (1UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_VBG (2UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_DAC (3UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_30MV (3UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_20MV (2UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_10MV (1UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for disabling the hysteresis function. \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_VREF constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_VREF_CRVSSEL_VDDA (0UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage \hideinitializer */ +#define ACMP_VREF_CRVSSEL_INTVREF (1UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage \hideinitializer */ + + +/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function. + * \hideinitializer + */ +#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to disable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function. + * \hideinitializer + */ +#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to select ACMP negative input source + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Src is comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @return None + * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input. + * \hideinitializer + */ +#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to enable hysteresis function and set hysteresis to 30mV + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * \hideinitializer + */ +#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV) + +/** + * @brief This macro is used to disable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear HYSEL bits of ACMP_CTL register to disable hysteresis function. + * \hideinitializer + */ +#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk) + +/** + * @brief This macro is used to select hysteresis level + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * \hideinitializer + * @return None + */ +#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel)) + +/** + * @brief This macro is used to enable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function. + * If wake-up function is enabled, the wake-up interrupt will be enabled as well. + * \hideinitializer + */ +#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to disable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function. + * \hideinitializer + */ +#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to enable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator. + * \hideinitializer + */ +#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to disable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + * \hideinitializer + */ +#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to get ACMP output value + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP output value + * @details This macro will return the ACMP output value. + * \hideinitializer + */ +#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to get ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP interrupt occurred (1) or not (0) + * @details This macro will return the ACMP interrupt flag. + * \hideinitializer + */ +#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to clear ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to clear ACMP wake-up interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to enable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function. + * \hideinitializer + */ +#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function. + * \hideinitializer + */ +#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to select ACMP positive input pin + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Pin Comparator positive pin selection. Including: + * - \ref ACMP_CTL_POSSEL_P0 + * - \ref ACMP_CTL_POSSEL_P1 + * - \ref ACMP_CTL_POSSEL_P2 + * - \ref ACMP_CTL_POSSEL_P3 + * @return None + * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin. + * \hideinitializer + */ +#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin)) + +/** + * @brief This macro is used to enable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function. + * \hideinitializer + */ +#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to disable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function. + * \hideinitializer + */ +#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to set ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cnt is comparator filter count setting. + * - \ref ACMP_CTL_FILTSEL_OFF + * - \ref ACMP_CTL_FILTSEL_1PCLK + * - \ref ACMP_CTL_FILTSEL_2PCLK + * - \ref ACMP_CTL_FILTSEL_4PCLK + * - \ref ACMP_CTL_FILTSEL_8PCLK + * - \ref ACMP_CTL_FILTSEL_16PCLK + * - \ref ACMP_CTL_FILTSEL_32PCLK + * - \ref ACMP_CTL_FILTSEL_64PCLK + * @return None + * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]). + * \hideinitializer + */ +#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt)) + +/** + * @brief This macro is used to select comparator reference voltage + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32Level The comparator reference voltage setting. + * The formula is: + * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24) + * The range of u32Level is 0 ~ 15. + * @return None + * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]). + * \hideinitializer + */ +#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to select ACMP interrupt condition + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cond Comparator interrupt condition selection. Including: + * - \ref ACMP_CTL_INTPOL_RF + * - \ref ACMP_CTL_INTPOL_R + * - \ref ACMP_CTL_INTPOL_F + * @return None + * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge. + * \hideinitializer + */ +#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond)) + +/** + * @brief This macro is used to enable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode. + * When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch + * block; when ACMP0/1_WLAT pin is at low level, the output of window latch block, + * WLATOUT, is frozen. + * \hideinitializer + */ +#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to disable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode. + * \hideinitializer + */ +#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to enable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode. + * When window compare mode is enabled, user can connect the specific analog voltage + * source to either the positive inputs of both comparators or the negative inputs of + * both comparators. The upper bound and lower bound of the designated range are + * determined by the voltages applied to the other inputs of both comparators. If the + * output of a comparator is low and the other comparator outputs high, which means two + * comparators implies the upper and lower bound. User can directly monitor a specific + * analog voltage source via ACMPWO (ACMP_STATUS[16]). + * \hideinitializer + */ +#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk) + +/** + * @brief This macro is used to disable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode. + * \hideinitializer + */ +#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk) + + + + +/* Function prototype declaration */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel); +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum); + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __ACMP_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/bpwm.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/bpwm.h new file mode 100644 index 00000000000..c5ba58ab417 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/bpwm.h @@ -0,0 +1,360 @@ +/**************************************************************************//** + * @file bpwm.h + * @version V1.00 + * @brief M480 series PWM driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_H__ +#define __BPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + +/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants + @{ +*/ +#define BPWM_CHANNEL_NUM (6) /*!< BPWM channel number \hideinitializer */ +#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */ +#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */ +#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */ +#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */ +#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */ +#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_UP_COUNTER (0UL) /*!< Up counter type \hideinitializer */ +#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type \hideinitializer */ +#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) \hideinitializer */ +#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing \hideinitializer */ +#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low \hideinitializer */ +#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high \hideinitializer */ +#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_SSCTL_SSRC_PWM0 (0UL<SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief This macro enable BPWM counter synchronous start counting function. + * @param[in] bpwm The pointer of the specified BPWM module + * @return None + * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * \hideinitializer + */ +#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \ + { \ + (bpwm)->MSKEN = (u32ChannelMask); \ + (bpwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF + * @return None + * \hideinitializer + */ +#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler)) + +/** + * @brief This macro set the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * \hideinitializer + */ +#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) + +/** + * @brief This macro get the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * @note BPWM counter will stop if period length set to 0 + * \hideinitializer + */ +#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR)) + +/** + * @brief This macro get the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * \hideinitializer + */ +#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD) + +/** + * @brief This macro set the BPWM aligned type + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @param[in] u32AlignedType BPWM aligned type, valid values are: + * - \ref BPWM_EDGE_ALIGNED + * - \ref BPWM_CENTER_ALIGNED + * @return None + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType)) + +/** + * @brief Clear counter of channel 0 + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to clear counter of channel 0 + * \hideinitializer + */ +#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * \hideinitializer + */ +#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) { \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \ + } \ + } \ + }while(0) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define BPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BPWM_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/can.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/can.h new file mode 100644 index 00000000000..3b898212586 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/can.h @@ -0,0 +1,191 @@ +/**************************************************************************//** + * @file can.h + * @version V2.00 + * @brief M480 Series CAN Driver Header File + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CAN_H__ +#define __CAN_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CAN Test Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_NORMAL_MODE 0ul /*!< CAN select normal mode \hideinitializer */ +#define CAN_BASIC_MODE 1ul /*!< CAN select basic mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message ID Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_STD_ID 0ul /*!< CAN select standard ID \hideinitializer */ +#define CAN_EXT_ID 1ul /*!< CAN select extended ID \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message Frame Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_REMOTE_FRAME 0ul /*!< CAN frame select remote frame \hideinitializer */ +#define CAN_DATA_FRAME 1ul /*!< CAN frame select data frame \hideinitializer */ + +/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */ + + +/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs + @{ +*/ +/** + * @details CAN message structure + */ +typedef struct +{ + uint32_t IdType; /*!< ID type */ + uint32_t FrameType; /*!< Frame type */ + uint32_t Id; /*!< Message ID */ + uint8_t DLC; /*!< Data length */ + uint8_t Data[8]; /*!< Data */ +} STR_CANMSG_T; + +/** + * @details CAN mask message structure + */ +typedef struct +{ + uint8_t u8Xtd; /*!< Extended ID */ + uint8_t u8Dir; /*!< Direction */ + uint32_t u32Id; /*!< Message ID */ + uint8_t u8IdType; /*!< ID type*/ +} STR_CANMASK_T; + +/*@}*/ /* end of group CAN_EXPORTED_STRUCTS */ + +/** @cond HIDDEN_SYMBOLS */ +#define MSG(id) (id) +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** + * @brief Get interrupt status. + * + * @param[in] can The base address of can module. + * + * @return CAN module status register value. + * + * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]), + * EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]). + * \hideinitializer + */ +#define CAN_GET_INT_STATUS(can) ((can)->STATUS) + +/** + * @brief Get specified interrupt pending status. + * + * @param[in] can The base address of can module. + * + * @return The source of the interrupt. + * + * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt + * with the highest priority, disregarding their chronological order. + * \hideinitializer + */ +#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR) + +/** + * @brief Disable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details The macro is used to disable wake-up function. + * \hideinitializer + */ +#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0ul) + +/** + * @brief Enable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details User can wake-up system when there is a falling edge in the CAN_Rx pin. + * \hideinitializer + */ +#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk) + +/** + * @brief Get specified Message Object new data into bit value. + * + * @param[in] can The base address of can module. + * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31. + * + * @return Specified Message Object new data into bit value. + * + * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers + * or by the Message Handler after reception of a Data Frame or after a successful transmission. + * \hideinitializer + */ +#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16))) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define CAN functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate); +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode); +void CAN_Close(CAN_T *tCAN); +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum); +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask); +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask); +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask); +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum); +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask); +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask); +void CAN_LeaveTestMode(CAN_T *tCAN); +uint32_t CAN_GetCANBitRate(CAN_T *tCAN); +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj); +void CAN_LeaveInitMode(CAN_T *tCAN); +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast); +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast); +void CAN_WaitMsg(CAN_T *tCAN); +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg); + +/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CAN_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__CAN_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/clk.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/clk.h new file mode 100644 index 00000000000..2f57f55f5d8 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/clk.h @@ -0,0 +1,614 @@ +/**************************************************************************//** + * @file CLK.h + * @version V1.0 + * @brief M480 Series CLK Driver Header File + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CLK_H__ +#define __CLK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + + +#define FREQ_25MHZ 25000000UL /*!< 25 MHz \hideinitializer */ +#define FREQ_50MHZ 50000000UL /*!< 50 MHz \hideinitializer */ +#define FREQ_72MHZ 72000000UL /*!< 72 MHz \hideinitializer */ +#define FREQ_80MHZ 80000000UL /*!< 80 MHz \hideinitializer */ +#define FREQ_100MHZ 100000000UL /*!< 100 MHz \hideinitializer */ +#define FREQ_125MHZ 125000000UL /*!< 125 MHz \hideinitializer */ +#define FREQ_160MHZ 160000000UL /*!< 160 MHz \hideinitializer */ +#define FREQ_192MHZ 192000000UL /*!< 192 MHz \hideinitializer */ +#define FREQ_200MHZ 200000000UL /*!< 200 MHz \hideinitializer */ +#define FREQ_250MHZ 250000000UL /*!< 250 MHz \hideinitializer */ +#define FREQ_500MHZ 500000000UL /*!< 500 MHz \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL0 constant definitions. (Write-protection) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HXT/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HCLK/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HIRC/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK \hideinitializer */ + +#if(0) +#define CLK_CLKSEL0_PCLK0DIV1 (0x0UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_PCLK0DIV2 (0x1UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from 1/2 HCLK \hideinitializer */ + +#define CLK_CLKSEL0_PCLK1DIV1 (0x0UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_PCLK1DIV2 (0x1UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from 1/2 HCLK \hideinitializer */ +#endif + +#define CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_PLL (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_PLL (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from HCLK \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL1 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from HCLK/2048 \hideinitializer */ + +#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger \hideinitializer */ + +#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_PLL (0x1UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_PLL (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL2 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_EPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_EPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_BPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_BPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI2SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK0 \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL3 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL3_RTCSEL_LXT (0x0UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_PLL (0x1UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_PLL (0x1UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_PLL (0x1UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_PLL (0x1UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from PLL \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed oscillator \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV0 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_USB(x) (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_SDH0(x) (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV0_UART0(x) (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_UART1(x) (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV0_EADC(x) (((x) - 1UL) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV1 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV1_SC0(x) (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV1_SC1(x) (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV1_SC2(x) (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV3 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV3_EMAC(x) (((x) - 1UL) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV3 Setting for EMAC clock divider. It could be 1~256 \hideinitializer */ +#define CLK_CLKDIV3_SDH1(x) (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLKDIV3 Setting for SDH1 clock divider. It could be 1~256 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKDIV4 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKDIV4_UART2(x) (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV4_UART3(x) (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV4_UART4(x) (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */ +#define CLK_CLKDIV4_UART5(x) (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PCLKDIV constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#if(1) +#define CLK_PCLKDIV_PCLK0DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK0DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */ +#define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */ +#endif +/*---------------------------------------------------------------------------------------------------------*/ +/* PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 4MHz < FIN/NR < 8MHz \hideinitializer */ +#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz \hideinitializer */ + +#define CLK_PLLCTL_NF(x) (((x)-2UL)) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */ +#define CLK_PLLCTL_NR(x) (((x)-1UL)<<9) /*!< x must be constant and 1 <= x <= 32. 4MHz < FIN/NR < 8MHz \hideinitializer */ + +#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 \hideinitializer */ +#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 \hideinitializer */ +#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 \hideinitializer */ + +#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_80MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_160MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ +#define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal) \hideinitializer */ + +#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_80MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_144MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_160MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ +#define CLK_PLLCTL_192MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* MODULE constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ + +/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */ + +#define MODULE_APBCLK(x) (((x) >>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */ +#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */ +#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */ +#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */ +#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */ +#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */ +#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */ + +#define PDMA_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA Module \hideinitializer */ +#define ISP_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< ISP Module \hideinitializer */ +#define EBI_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< EBI Module \hideinitializer */ +#define USBH_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< USBH Module \hideinitializer */ +#define EMAC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(16UL<<5) |(5UL<<0)) /*!< EMAC Module \hideinitializer */ +#define SDH0_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(20UL<<20) |(0UL<<18) |(0xFFUL<<10) |(24UL<<5) |(6UL<<0)) /*!< SDH0 Module \hideinitializer */ +#define CRC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< CRC Module \hideinitializer */ +#define HSUSBD_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< HSUSBD Module \hideinitializer */ +#define CRPT_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< CRPT Module \hideinitializer */ +#define SPIM_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPIM Module \hideinitializer */ +#define SDH1_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(22UL<<20) |(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(17UL<<0)) /*!< SDH1 Module \hideinitializer */ +#define WDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WDT Module \hideinitializer */ +#define RTC_MODULE ((1UL<<30)|(3UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< RTC Module \hideinitializer */ +#define TMR0_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TMR0 Module \hideinitializer */ +#define TMR1_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< TMR1 Module \hideinitializer */ +#define TMR2_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< TMR2 Module \hideinitializer */ +#define TMR3_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(20UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< TMR3 Module \hideinitializer */ +#define CLKO_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(28UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< CLKO Module \hideinitializer */ +#define WWDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(30UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WWDT Module \hideinitializer */ +#define ACMP01_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< ACMP01 Module \hideinitializer */ +#define I2C0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< I2C0 Module \hideinitializer */ +#define I2C1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< I2C1 Module \hideinitializer */ +#define I2C2_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< I2C2 Module \hideinitializer */ +#define QSPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(2UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< QSPI0 Module \hideinitializer */ +#define SPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(4UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< SPI0 Module \hideinitializer */ +#define SPI1_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(6UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPI1 Module \hideinitializer */ +#define SPI2_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(10UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< SPI2 Module \hideinitializer */ +#define UART0_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(24UL<<20) |(0UL<<18) |(0xFUL<<10) |(8UL<<5) |(16UL<<0)) /*!< UART0 Module \hideinitializer */ +#define UART1_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(26UL<<20) |(0UL<<18) |(0xFUL<<10) |(12UL<<5) |(17UL<<0)) /*!< UART1 Module \hideinitializer */ +#define UART2_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(24UL<<20) |(3UL<<18) |(0xFUL<<10) |(0UL<<5) |(18UL<<0)) /*!< UART2 Module \hideinitializer */ +#define UART3_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(26UL<<20) |(3UL<<18) |(0xFUL<<10) |(4UL<<5) |(19UL<<0)) /*!< UART3 Module \hideinitializer */ +#define UART4_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(28UL<<20) |(3UL<<18) |(0xFUL<<10) |(8UL<<5) |(20UL<<0)) /*!< UART4 Module \hideinitializer */ +#define UART5_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(30UL<<20) |(3UL<<18) |(0xFUL<<10) |(12UL<<5) |(21UL<<0)) /*!< UART5 Module \hideinitializer */ +#define CAN0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< CAN0 Module \hideinitializer */ +#define CAN1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< CAN1 Module \hideinitializer */ +#define OTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< OTG Module \hideinitializer */ +#define USBD_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< USBD Module \hideinitializer */ +#define EADC_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(0UL<<18) |(0xFFUL<<10) |(16UL<<5) |(28UL<<0)) /*!< EADC Module \hideinitializer */ +#define I2S0_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(29UL<<0)) /*!< I2S0 Module \hideinitializer */ +#define HSOTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< HSOTG Module \hideinitializer */ +#define SC0_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(0UL<<20) |(1UL<<18) |(0xFFUL<<10) |(0UL<<5) |(0UL<<0)) /*!< SC0 Module \hideinitializer */ +#define SC1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(2UL<<20) |(1UL<<18) |(0xFFUL<<10) |(8UL<<5) |(1UL<<0)) /*!< SC1 Module \hideinitializer */ +#define SC2_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(4UL<<20) |(1UL<<18) |(0xFFUL<<10) |(16UL<<5) |(2UL<<0)) /*!< SC2 Module \hideinitializer */ +#define SPI3_MODULE ((2UL<<30)|(2UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< SPI3 Module \hideinitializer */ +#define USCI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< USCI0 Module \hideinitializer */ +#define USCI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< USCI1 Module \hideinitializer */ +#define DAC_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< DAC Module \hideinitializer */ +#define EPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< EPWM0 Module \hideinitializer */ +#define EPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(1UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< EPWM1 Module \hideinitializer */ +#define BPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< BPWM0 Module \hideinitializer */ +#define BPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(9UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< BPWM1 Module \hideinitializer */ +#define QEI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< QEI0 Module \hideinitializer */ +#define QEI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< QEI1 Module \hideinitializer */ +#define ECAP0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< ECAP0 Module \hideinitializer */ +#define ECAP1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< ECAP1 Module \hideinitializer */ +#define OPA_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< OPA Module \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PDMSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Low leakage Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Fast wake-up Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_SPD0 (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 0 \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_SPD1 (0x5UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 1 \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Deep Power-down mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WKTMRIS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* SWKDBCLKSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin both edge at Deep Power-down mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */ +#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */ +#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */ +#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function \hideinitializer */ +#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function \hideinitializer */ + +#define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */ +#define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */ +#define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */ + +/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Set Wake-up Timer Time-out Interval + * + * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be + * - \ref CLK_PMUCTL_WKTMRIS_128 + * - \ref CLK_PMUCTL_WKTMRIS_256 + * - \ref CLK_PMUCTL_WKTMRIS_512 + * - \ref CLK_PMUCTL_WKTMRIS_1024 + * - \ref CLK_PMUCTL_WKTMRIS_4096 + * - \ref CLK_PMUCTL_WKTMRIS_8192 + * - \ref CLK_PMUCTL_WKTMRIS_16384 + * - \ref CLK_PMUCTL_WKTMRIS_65536 + * + * @return None + * + * @details This function set Wake-up Timer Time-out Interval. + * + * \hideinitializer + */ +#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256 + * + * @return None + * + * @details This function set Set De-bounce Sampling Cycle Time. + * + * \hideinitializer + */ +#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel)) + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us); +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us); + +/** + * @brief This function execute delay function. + * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: + * 72MHz => 233016us, 50MHz => 335544us, + * 48MHz => 349525us, 28MHz => 699050us ... + * @return None + * @details Use the SysTick to generate the delay time and the unit is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us) +{ + SysTick->LOAD = us * CyclesPerUs; + SysTick->VAL = 0x0UL; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) + { + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; +} + +/** + * @brief This function execute long delay function. + * @param[in] us Delay time. + * @return None + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us) +{ + uint32_t delay; + + /* It should <= 349525us for each delay loop */ + delay = 349525UL; + + do + { + if(us > delay) + { + us -= delay; + } + else + { + delay = us; + us = 0UL; + } + + SysTick->LOAD = delay * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL); + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; + + } + while(us > 0UL); + +} + + +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); +void CLK_PowerDown(void); +void CLK_Idle(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLK0Freq(void); +uint32_t CLK_GetPCLK1Freq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +void CLK_DisablePLL(void); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); +void CLK_SetPowerDownMode(uint32_t u32PDMode); +void CLK_EnableDPDWKPin(uint32_t u32TriggerType); +uint32_t CLK_GetPMUWKSrc(void); +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn); +uint32_t CLK_GetPLLClockFreq(void); +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx); +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx); + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CLK_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/crc.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/crc.h new file mode 100644 index 00000000000..c981f9108c2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/crc.h @@ -0,0 +1,112 @@ +/**************************************************************************//** + * @file crc.h + * @version V1.00 + * @brief M480 series CRC driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CRC Polynomial Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0) + +/** + * @brief Get CRC Seed Value + * + * @param None + * + * @return CRC seed value + * + * @details This macro gets the current CRC seed value. + * \hideinitializer + */ +#define CRC_GET_SEED() (CRC->SEED) + +/** + * @brief CRC Write Data + * + * @param[in] u32Data Write data + * + * @return None + * + * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation. + * \hideinitializer + */ +#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data)) + +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen); +uint32_t CRC_GetChecksum(void); + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/crypto.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/crypto.h new file mode 100644 index 00000000000..da8d9e8803e --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/crypto.h @@ -0,0 +1,377 @@ +/**************************************************************************//** + * @file crypto.h + * @version V1.10 + * @brief Cryptographic Accelerator driver header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CRYPTO_H__ +#define __CRYPTO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants + @{ +*/ + +#define PRNG_KEY_SIZE_64 0UL /*!< Select to generate 64-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_128 1UL /*!< Select to generate 128-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_192 2UL /*!< Select to generate 192-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_256 3UL /*!< Select to generate 256-bit random key \hideinitializer */ + +#define PRNG_SEED_CONT 0UL /*!< PRNG using current seed \hideinitializer */ +#define PRNG_SEED_RELOAD 1UL /*!< PRNG reload new seed \hideinitializer */ + +#define AES_KEY_SIZE_128 0UL /*!< AES select 128-bit key length \hideinitializer */ +#define AES_KEY_SIZE_192 1UL /*!< AES select 192-bit key length \hideinitializer */ +#define AES_KEY_SIZE_256 2UL /*!< AES select 256-bit key length \hideinitializer */ + +#define AES_MODE_ECB 0UL /*!< AES select ECB mode \hideinitializer */ +#define AES_MODE_CBC 1UL /*!< AES select CBC mode \hideinitializer */ +#define AES_MODE_CFB 2UL /*!< AES select CFB mode \hideinitializer */ +#define AES_MODE_OFB 3UL /*!< AES select OFB mode \hideinitializer */ +#define AES_MODE_CTR 4UL /*!< AES select CTR mode \hideinitializer */ +#define AES_MODE_CBC_CS1 0x10UL /*!< AES select CBC CS1 mode \hideinitializer */ +#define AES_MODE_CBC_CS2 0x11UL /*!< AES select CBC CS2 mode \hideinitializer */ +#define AES_MODE_CBC_CS3 0x12UL /*!< AES select CBC CS3 mode \hideinitializer */ + +#define AES_NO_SWAP 0UL /*!< AES do not swap input and output data \hideinitializer */ +#define AES_OUT_SWAP 1UL /*!< AES swap output data \hideinitializer */ +#define AES_IN_SWAP 2UL /*!< AES swap input data \hideinitializer */ +#define AES_IN_OUT_SWAP 3UL /*!< AES swap both input and output data \hideinitializer */ + +#define DES_MODE_ECB 0x000UL /*!< DES select ECB mode \hideinitializer */ +#define DES_MODE_CBC 0x100UL /*!< DES select CBC mode \hideinitializer */ +#define DES_MODE_CFB 0x200UL /*!< DES select CFB mode \hideinitializer */ +#define DES_MODE_OFB 0x300UL /*!< DES select OFB mode \hideinitializer */ +#define DES_MODE_CTR 0x400UL /*!< DES select CTR mode \hideinitializer */ +#define TDES_MODE_ECB 0x004UL /*!< TDES select ECB mode \hideinitializer */ +#define TDES_MODE_CBC 0x104UL /*!< TDES select CBC mode \hideinitializer */ +#define TDES_MODE_CFB 0x204UL /*!< TDES select CFB mode \hideinitializer */ +#define TDES_MODE_OFB 0x304UL /*!< TDES select OFB mode \hideinitializer */ +#define TDES_MODE_CTR 0x404UL /*!< TDES select CTR mode \hideinitializer */ + +#define TDES_NO_SWAP 0UL /*!< TDES do not swap data \hideinitializer */ +#define TDES_WHL_SWAP 1UL /*!< TDES swap high-low word \hideinitializer */ +#define TDES_OUT_SWAP 2UL /*!< TDES swap output data \hideinitializer */ +#define TDES_OUT_WHL_SWAP 3UL /*!< TDES swap output data and high-low word \hideinitializer */ +#define TDES_IN_SWAP 4UL /*!< TDES swap input data \hideinitializer */ +#define TDES_IN_WHL_SWAP 5UL /*!< TDES swap input data and high-low word \hideinitializer */ +#define TDES_IN_OUT_SWAP 6UL /*!< TDES swap both input and output data \hideinitializer */ +#define TDES_IN_OUT_WHL_SWAP 7UL /*!< TDES swap input, output and high-low word \hideinitializer */ + +#define SHA_MODE_SHA1 0UL /*!< SHA select SHA-1 160-bit \hideinitializer */ +#define SHA_MODE_SHA224 5UL /*!< SHA select SHA-224 224-bit \hideinitializer */ +#define SHA_MODE_SHA256 4UL /*!< SHA select SHA-256 256-bit \hideinitializer */ +#define SHA_MODE_SHA384 7UL /*!< SHA select SHA-384 384-bit \hideinitializer */ +#define SHA_MODE_SHA512 6UL /*!< SHA select SHA-512 512-bit \hideinitializer */ + +#define SHA_NO_SWAP 0UL /*!< SHA do not swap input and output data \hideinitializer */ +#define SHA_OUT_SWAP 1UL /*!< SHA swap output data \hideinitializer */ +#define SHA_IN_SWAP 2UL /*!< SHA swap input data \hideinitializer */ +#define SHA_IN_OUT_SWAP 3UL /*!< SHA swap both input and output data \hideinitializer */ + +#define CRYPTO_DMA_FIRST 0x4UL /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_ONE_SHOT 0x5UL /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */ +#define CRYPTO_DMA_CONTINUE 0x6UL /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_LAST 0x7UL /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */ + +typedef enum +{ + /*!< ECC curve \hideinitializer */ + CURVE_P_192, /*!< ECC curve P-192 \hideinitializer */ + CURVE_P_224, /*!< ECC curve P-224 \hideinitializer */ + CURVE_P_256, /*!< ECC curve P-256 \hideinitializer */ + CURVE_P_384, /*!< ECC curve P-384 \hideinitializer */ + CURVE_P_521, /*!< ECC curve P-521 \hideinitializer */ + CURVE_K_163, /*!< ECC curve K-163 \hideinitializer */ + CURVE_K_233, /*!< ECC curve K-233 \hideinitializer */ + CURVE_K_283, /*!< ECC curve K-283 \hideinitializer */ + CURVE_K_409, /*!< ECC curve K-409 \hideinitializer */ + CURVE_K_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_B_163, /*!< ECC curve B-163 \hideinitializer */ + CURVE_B_233, /*!< ECC curve B-233 \hideinitializer */ + CURVE_B_283, /*!< ECC curve B-283 \hideinitializer */ + CURVE_B_409, /*!< ECC curve B-409 \hideinitializer */ + CURVE_B_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_KO_192, /*!< ECC 192-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_224, /*!< ECC 224-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_256, /*!< ECC 256-bits "Koblitz" curve \hideinitializer */ + CURVE_BP_256, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_384, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_512, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_UNDEF, /*!< Invalid curve \hideinitializer */ +} +E_ECC_CURVE; /*!< ECC curve \hideinitializer */ + + +/*@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */ + + +/** @addtogroup M480_CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros + @{ +*/ + +/*----------------------------------------------------------------------------------------------*/ +/* Macros */ +/*----------------------------------------------------------------------------------------------*/ + +/** + * @brief This macro enables PRNG interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro disables PRNG interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro gets PRNG interrupt flag. + * @param crpt Specified cripto module + * @return PRNG interrupt flag. + * \hideinitializer + */ +#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro clears PRNG interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro enables AES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro disables AES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro gets AES interrupt flag. + * @param crpt Specified cripto module + * @return AES interrupt flag. + * \hideinitializer + */ +#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro clears AES interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro enables AES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables AES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables TDES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro disables TDES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro gets TDES interrupt flag. + * @param crpt Specified cripto module + * @return TDES interrupt flag. + * \hideinitializer + */ +#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro clears TDES interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro enables TDES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables TDES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables SHA interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro disables SHA interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro gets SHA interrupt flag. + * @param crpt Specified cripto module + * @return SHA interrupt flag. + * \hideinitializer + */ +#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro clears SHA interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro enables ECC interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro disables ECC interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro gets ECC interrupt flag. + * @param crpt Specified cripto module + * @return ECC interrupt flag. + * \hideinitializer + */ +#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + +/** + * @brief This macro clears ECC interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + + +/*@}*/ /* end of group M480_CRYPTO_EXPORTED_MACROS */ + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed); +void PRNG_Start(CRPT_T *crpt); +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]); +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType); +void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode); +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize); +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]); +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType); +void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode); +void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]); +void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL); +void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len); +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode); +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt); +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]); +void ECC_Complete(CRPT_T *crpt); +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]); +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]); +int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]); +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]); +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S); +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S); + + +/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRYPTO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRYPTO_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/dac.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/dac.h new file mode 100644 index 00000000000..e73cbd193fa --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/dac.h @@ -0,0 +1,268 @@ +/**************************************************************************//** + * @file dac.h + * @version V1.00 + * @brief M480 series DAC driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __DAC_H__ +#define __DAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + + +/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DAC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk) + +/** + * @brief Enable DAC data left-aligned. + * @param[in] dac Base address of DAC module. + * @return None + * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. + * \hideinitializer + */ +#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable DAC data right-aligned. + * @param[in] dac Base address of DAC module. + * @return None + * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. + * \hideinitializer + */ +#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable output voltage buffer. + * @param[in] dac Base address of DAC module. + * @return None + * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and + * drive external loads directly without having to add an external operational amplifier. + * \hideinitializer + */ +#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) + +/** + * @brief Disable output voltage buffer. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to disable output voltage buffer. + * \hideinitializer + */ +#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details This macro is used to enable DAC interrupt. + * \hideinitializer + */ +#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) + +/** + * @brief Disable the interrupt. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details This macro is used to disable DAC interrupt. + * \hideinitializer + */ +#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) + +/** + * @brief Enable DMA under-run interrupt. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to enable DMA under-run interrupt. + * \hideinitializer + */ +#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Disable DMA under-run interrupt. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to disable DMA under-run interrupt. + * \hideinitializer + */ +#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Enable PDMA mode. + * @param[in] dac Base address of DAC module. + * @return None + * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. + * \hideinitializer + */ +#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) + +/** + * @brief Disable PDMA mode. + * @param[in] dac Base address of DAC module. + * @return None + * @details This macro is used to disable DMA mode. + * \hideinitializer + */ +#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) + +/** + * @brief Write data for conversion. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. + * @return None + * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + * \hideinitializer + */ +#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) + +/** + * @brief Read DAC 12-bit holding data. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return Return DAC 12-bit holding data. + * @details This macro is used to read DAC_DAT register. + * \hideinitializer + */ +#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) + +/** + * @brief Get the busy state of DAC. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. + * \hideinitializer + */ +#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) + +/** + * @brief Get the interrupt flag. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @retval 0 DAC is in conversion state. + * @retval 1 DAC conversion finish. + * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. + * \hideinitializer + */ +#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) + +/** + * @brief Get the DMA under-run flag. + * @param[in] dac Base address of DAC module. + * @retval 0 No DMA under-run error condition occurred. + * @retval 1 DMA under-run error condition occurred. + * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. + * \hideinitializer + */ +#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) + +/** + * @brief This macro clear the interrupt status bit. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. + * \hideinitializer + */ +#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) + +/** + * @brief This macro clear the DMA under-run flag. + * @param[in] dac Base address of DAC module. + * @return None + * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. + * \hideinitializer + */ +#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) + + +/** + * @brief Enable DAC group mode + * @param[in] dac Base address of DAC module. + * @return None + * \hideinitializer + */ +#define DAC_ENABLE_GROUP_MODE(dac) (DAC0->CTL |= DAC_CTL_GRPEN_Msk) + +/** + * @brief Disable DAC group mode + * @param[in] dac Base address of DAC module. + * @return None + * \hideinitializer + */ +#define DAC_DISABLE_GROUP_MODE(dac) (DAC0->CTL &= ~DAC_CTL_GRPEN_Msk) + +void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); +void DAC_Close(DAC_T *dac, uint32_t u32Ch); +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/eadc.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/eadc.h new file mode 100644 index 00000000000..725e6c7bad6 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/eadc.h @@ -0,0 +1,590 @@ +/**************************************************************************//** + * @file eadc.h + * @version V0.10 + * @brief M480 series EADC driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __EADC_H__ +#define __EADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EADC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EADC_CTL_DIFFEN_SINGLE_END (0UL<CTL |= EADC_CTL_ADCRST_Msk) + +/** + * @brief Enable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, + * user can enable this bit to generate a PDMA data transfer request. + * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * \hideinitializer + */ +#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk) + +/** + * @brief Disable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable PDMA transfer. + * \hideinitializer + */ +#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk)) + +/** + * @brief Enable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details The ADC controller supports a double buffer mode in sample module 0~3. + * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. + * \hideinitializer + */ +#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) + +/** + * @brief Disable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details Sample has one sample result register. + * \hideinitializer + */ +#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) + +/** + * @brief Set ADIFn at A/D end of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. + * \hideinitializer + */ +#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) + +/** + * @brief Set ADIFn at A/D start of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. + * \hideinitializer + */ +#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. + * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). + * \hideinitializer + */ +#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Disable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details Specific sample module A/D ADINT0 interrupt function Disabled. + * \hideinitializer + */ +#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Enable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + * \hideinitializer + */ +#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) + +/** + * @brief Disable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + * \hideinitializer + */ +#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask)) + +/** + * @brief Set the input mode output format. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Format Decides the output format. Valid values are: + * - EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. + * - EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. + * @return None + * @details The macro is used to set A/D input mode output format. + * \hideinitializer + */ +#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) + +/** + * @brief Start the A/D conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. + * @return None + * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. + * \hideinitializer + */ +#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) + +/** + * @brief Cancel the conversion for sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. + * @return None + * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * \hideinitializer + */ +#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) + +/** + * @brief Get the conversion pending flag. + * @param[in] eadc The pointer of the specified EADC module. + * @return Return the conversion pending sample module. + * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, + * the STPFn (n=0~18) bit is automatically cleared to 0. + * \hideinitializer + */ +#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) + +/** + * @brief Get the conversion data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the conversion data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. + * \hideinitializer + */ +#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) + +/** + * @brief Get the data overrun flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. + * @return Return the data overrun flag of the user-specified sample module. + * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. + * \hideinitializer + */ +#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) + +/** + * @brief Get the data valid flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. + * @return Return the data valid flag of the user-specified sample module. + * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. + * \hideinitializer + */ +#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) + +/** + * @brief Get the double data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the double data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. + * \hideinitializer + */ +#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) + +/** + * @brief Get the user-specified interrupt flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return Return the user-specified interrupt flags. + * @details This macro is used to get the user-specified interrupt flags. + * \hideinitializer + */ +#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) + +/** + * @brief Get the user-specified sample module overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. + * @return Return the user-specified sample module overrun flags. + * @details This macro is used to get the user-specified sample module overrun flags. + * \hideinitializer + */ +#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) + +/** + * @brief Clear the selected interrupt status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return None + * @details This macro is used to clear clear the selected interrupt status bits. + * \hideinitializer + */ +#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) + +/** + * @brief Clear the selected sample module overrun status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. + * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. + * @return None + * @details This macro is used to clear the selected sample module overrun status bits. + * \hideinitializer + */ +#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) + +/** + * @brief Check all sample module A/D result data register overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register overrun flag is set to 1. + * @retval 1 Any one of sample module data register overrun flag is set to 1. + * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) + +/** + * @brief Check all sample module A/D result data register valid flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register valid flag is set to 1. + * @retval 1 Any one of sample module data register valid flag is set to 1. + * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) + +/** + * @brief Check all A/D sample module start of conversion overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module event overrun flag is set to 1. + * @retval 1 Any one of sample module event overrun flag is set to 1. + * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) + +/** + * @brief Check all A/D interrupt flag overrun bits. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of ADINT interrupt flag is overwritten to 1. + * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. + * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * \hideinitializer + */ +#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) + +/** + * @brief Get the busy state of EADC. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. + * \hideinitializer + */ +#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) + +/** + * @brief Configure the comparator 0 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP0(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 1 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP1(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 2 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP2(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 3 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP3(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Enable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) + +/** + * @brief Disable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) + +/** + * @brief Enable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) + * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, + * if ADCMPIE is set to 1, a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details This macro is used to disable the compare interrupt. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable comparator 0. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 0. + * \hideinitializer + */ +#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0) + +/** + * @brief Disable comparator 1. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 1. + * \hideinitializer + */ +#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0) + +/** + * @brief Disable comparator 2. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 2. + * \hideinitializer + */ +#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0) + +/** + * @brief Disable comparator 3. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 3. + * \hideinitializer + */ +#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EADC functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); +void EADC_Close(EADC_T *eadc); +void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); +void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EADC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/ebi.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/ebi.h new file mode 100644 index 00000000000..830a6888d68 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/ebi.h @@ -0,0 +1,351 @@ +/**************************************************************************//** + * @file ebi.h + * @version V3.00 + * @brief M480 series External Bus Interface(EBI) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_H__ +#define __EBI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */ +#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */ +#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */ +#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI bank number */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */ +#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */ +#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI data bus width */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */ +#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI CS Active Level */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */ +#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI MCLK divider and Timing */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */ +#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */ +#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */ +#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */ +#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */ +#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */ +#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */ +#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */ + +#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */ +#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */ +#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */ +#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */ +#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */ +#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */ +#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */ + +#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */ +#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */ +#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */ + +/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Read 8-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Enable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to improve EBI write operation for all EBI banks. + * \hideinitializer + */ +#define EBI_ENABLE_WRITE_BUFFER() (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk); + +/** + * @brief Disable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to disable EBI write buffer function. + * \hideinitializer + */ +#define EBI_DISABLE_WRITE_BUFFER() (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk); + +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +void EBI_Close(uint32_t u32Bank); +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv); + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/ecap.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/ecap.h new file mode 100644 index 00000000000..0c029abd555 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/ecap.h @@ -0,0 +1,457 @@ +/**************************************************************************//** + * @file ecap.h + * @version V3.00 + * @brief EnHanced Input Capture Timer(ECAP) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __ECAP_H__ +#define __ECAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants + @{ +*/ + +#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */ +#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */ +#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ECAP CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel)) + +/** + * @brief This macro is used to disable noise filter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the noise filter of input capture. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk) + +/** + * @brief This macro is used to enable noise filter + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSel Select noise filter clock divide number + * - \ref ECAP_NOISE_FILTER_CLKDIV_1 + * - \ref ECAP_NOISE_FILTER_CLKDIV_2 + * - \ref ECAP_NOISE_FILTER_CLKDIV_4 + * - \ref ECAP_NOISE_FILTER_CLKDIV_16 + * - \ref ECAP_NOISE_FILTER_CLKDIV_32 + * - \ref ECAP_NOISE_FILTER_CLKDIV_64 + * @return None + * @details This macro will enable the noise filter of input capture and set noise filter clock divide. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel)) + +/** + * @brief This macro is used to enable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will enable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will disable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to select input channel source + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Src The input source + * - \ref ECAP_CAP_INPUT_SRC_FROM_IC + * - \ref ECAP_CAP_INPUT_SRC_FROM_CH + * @return None + * @details This macro will select the input source from ICx, CHx. + * \hideinitializer + */ +#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return None + * @details This macro will disable the input channel_n interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to enable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to disable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to enable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to disable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to start capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will start capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to stop capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will stop capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to set event to clear capture counter + * @param[in] ecap Specify ECAP port + * @param[in] u32Event The input channel number + * - \ref ECAP_CTL0_CMPCLREN_Msk + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + + * @return None + * @details This macro will enable and select compare or capture event that can clear capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \ + if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \ + (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \ + else \ + (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \ + (ecap)->CTL1 = ((ecap)->CTL1 &~0xF00) | ((u32Event) & 0xF00); \ + }while(0); + +/** + * @brief This macro is used to enable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the compare function. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to disable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the compare function. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to enable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to disable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to select input channel edge detection + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Edge The input source + * - \ref ECAP_RISING_EDGE + * - \ref ECAP_FALLING_EDGE + * - \ref ECAP_RISING_FALLING_EDGE + * @return None + * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change. + * \hideinitializer + */ +#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1))) + +/** + * @brief This macro is used to select ECAP counter reload trigger source + * @param[in] ecap Specify ECAP port + * @param[in] u32TrigSrc The input source + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + * @return None + * @details This macro will select capture counter reload trigger source. + * \hideinitializer + */ +#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc)) + +/** + * @brief This macro is used to select capture timer clock divide. + * @param[in] ecap Specify ECAP port + * @param[in] u32Clkdiv The input source + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_1 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_4 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_16 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_32 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_64 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_96 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_112 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_128 + * @return None + * @details This macro will select capture timer clock has a pre-divider with eight divided option. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv)) + +/** + * @brief This macro is used to select capture timer/counter clock source + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSrc The input source + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 + * @return None + * @details This macro will select capture timer/clock clock source. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc)) + +/** + * @brief This macro is used to read input capture status + * @param[in] ecap Specify ECAP port + * @return Input capture status flags + * @details This macro will get the input capture interrupt status. + * \hideinitializer + */ +#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS) + +/** + * @brief This macro is used to get input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to get the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) + +/** + * @brief This macro is used to clear input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to clear the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) + +/** + * @brief This macro is used to set input capture counter value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Counter value + * @return None + * @details This macro will set a counter value of input capture. + * \hideinitializer + */ +#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val)) + +/** + * @brief This macro is used to get input capture counter value + * @param[in] ecap Specify ECAP port + * @return Capture counter value + * @details This macro will get a counter value of input capture. + * \hideinitializer + */ +#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT) + +/** + * @brief This macro is used to get input capture counter hold value + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return Capture counter hold value + * @details This macro will get a hold value of input capture channel_n. + * \hideinitializer + */ +#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index))) + +/** + * @brief This macro is used to set input capture counter compare value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Input capture compare value + * @return None + * @details This macro will set a compare value of input capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val)) + +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask); +void ECAP_Close(ECAP_T* ecap); +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask); +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask); +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ECAP_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/emac.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/emac.h new file mode 100644 index 00000000000..ca279a8d6b0 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/emac.h @@ -0,0 +1,184 @@ +/**************************************************************************//** + * @file emac.h + * @version V1.00 + * @brief M480 EMAC driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __EMAC_H__ +#define __EMAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EMAC_Driver EMAC Driver + @{ +*/ + +/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants + @{ +*/ + +#define EMAC_PHY_ADDR 1UL /*!< PHY address, this address is board dependent \hideinitializer */ +#define EMAC_RX_DESC_SIZE 4UL /*!< Number of Rx Descriptors, should be 2 at least \hideinitializer */ +#define EMAC_TX_DESC_SIZE 4UL /*!< Number of Tx Descriptors, should be 2 at least \hideinitializer */ + +#define EMAC_LINK_DOWN 0UL /*!< Ethernet link is down \hideinitializer */ +#define EMAC_LINK_100F 1UL /*!< Ethernet link is 100Mbps full duplex \hideinitializer */ +#define EMAC_LINK_100H 2UL /*!< Ethernet link is 100Mbps half duplex \hideinitializer */ +#define EMAC_LINK_10F 3UL /*!< Ethernet link is 10Mbps full duplex \hideinitializer */ +#define EMAC_LINK_10H 4UL /*!< Ethernet link is 10Mbps half duplex \hideinitializer */ + +/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */ + + +/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions + @{ +*/ + + +/** + * @brief Enable EMAC Tx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_TX() (EMAC->CTL |= EMAC_CTL_TXON_Msk) + + +/** + * @brief Enable EMAC Rx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0) + +/** + * @brief Disable EMAC Tx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_TX() (EMAC->CTL &= ~EMAC_CTL_TXON_Msk) + + +/** + * @brief Disable EMAC Rx function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_RX() (EMAC->CTL &= ~EMAC_CTL_RXON_Msk) + +/** + * @brief Enable EMAC Magic Packet Wakeup function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL |= EMAC_CTL_WOLEN_Msk) + +/** + * @brief Disable EMAC Magic Packet Wakeup function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk) + +/** + * @brief Enable EMAC to receive broadcast packets + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_RECV_BCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk) + +/** + * @brief Disable EMAC to receive broadcast packets + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_RECV_BCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk) + +/** + * @brief Enable EMAC to receive multicast packets + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_ENABLE_RECV_MCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk) + +/** + * @brief Disable EMAC Magic Packet Wakeup function + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_DISABLE_RECV_MCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk) + +/** + * @brief Check if EMAC time stamp alarm interrupt occurred or not + * @param None + * @return If time stamp alarm interrupt occurred or not + * @retval 0 Alarm interrupt does not occur + * @retval 1 Alarm interrupt occurred + * \hideinitializer + */ +#define EMAC_GET_ALARM_FLAG() (EMAC->INTSTS & EMAC_INTSTS_TSALMIF_Msk ? 1 : 0) + +/** + * @brief Clear EMAC time stamp alarm interrupt flag + * @param None + * @return None + * \hideinitializer + */ +#define EMAC_CLR_ALARM_FLAG() (EMAC->INTSTS = EMAC_INTSTS_TSALMIF_Msk) + + +void EMAC_Open(uint8_t *pu8MacAddr); +void EMAC_Close(void); +void EMAC_SetMacAddr(uint8_t *pu8MacAddr); +void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[]); +void EMAC_DisableCamEntry(uint32_t u32Entry); + +uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size); +uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec); +void EMAC_RecvPktDone(void); + +uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size); +uint32_t EMAC_SendPktDone(void); +uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec); + +void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_DisableTS(void); +void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec); +void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec); +void EMAC_DisableAlarm(void); + +uint32_t EMAC_CheckLinkStatus(void); + +/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EMAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EMAC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/epwm.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/epwm.h new file mode 100644 index 00000000000..1235f21e2dd --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/epwm.h @@ -0,0 +1,620 @@ +/**************************************************************************//** + * @file epwm.h + * @version V3.00 + * @brief M480 series EPWM driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_H__ +#define __EPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + +/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants + @{ +*/ +#define EPWM_CHANNEL_NUM (6U) /*!< EPWM channel number \hideinitializer */ +#define EPWM_CH_0_MASK (0x1U) /*!< EPWM channel 0 mask \hideinitializer */ +#define EPWM_CH_1_MASK (0x2U) /*!< EPWM channel 1 mask \hideinitializer */ +#define EPWM_CH_2_MASK (0x4U) /*!< EPWM channel 2 mask \hideinitializer */ +#define EPWM_CH_3_MASK (0x8U) /*!< EPWM channel 3 mask \hideinitializer */ +#define EPWM_CH_4_MASK (0x10U) /*!< EPWM channel 4 mask \hideinitializer */ +#define EPWM_CH_5_MASK (0x20U) /*!< EPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_UP_COUNTER (0U) /*!< Up counter type \hideinitializer */ +#define EPWM_DOWN_COUNTER (1U) /*!< Down counter type \hideinitializer */ +#define EPWM_UP_DOWN_COUNTER (2U) /*!< Up-Down counter type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_EDGE_ALIGNED (1U) /*!< EPWM working in edge aligned type(down count) \hideinitializer */ +#define EPWM_CENTER_ALIGNED (2U) /*!< EPWM working in center aligned type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_OUTPUT_NOTHING (0U) /*!< EPWM output nothing \hideinitializer */ +#define EPWM_OUTPUT_LOW (1U) /*!< EPWM output low \hideinitializer */ +#define EPWM_OUTPUT_HIGH (2U) /*!< EPWM output high \hideinitializer */ +#define EPWM_OUTPUT_TOGGLE (3U) /*!< EPWM output toggle \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_SSCTL_SSRC_EPWM0 (0U<CTL1 = (epwm)->CTL1 | (0x7ul<CTL1 = (epwm)->CTL1 & ~(0x7ul<CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief This macro disable group mode + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to disable group mode of EPWM module. + * \hideinitializer + */ +#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief Enable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32SyncSrc Synchronous start source selection, valid values are: + * - \ref EPWM_SSCTL_SSRC_EPWM0 + * - \ref EPWM_SSCTL_SSRC_EPWM1 + * - \ref EPWM_SSCTL_SSRC_BPWM0 + * - \ref EPWM_SSCTL_SSRC_BPWM1 + * @return None + * @details This macro is used to enable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ + do{ \ + int i;\ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (epwm)->SSCTL &= ~(1UL << i); \ + } \ + }while(0) + +/** + * @brief This macro enable EPWM counter synchronous start counting function. + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to enable output inverter of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured rising data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured falling data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ + { \ + (epwm)->MSKEN = (u32ChannelMask); \ + (epwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @return None + * @details This macro is used to set the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)) + +/** + * @brief This macro get the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @details This macro is used to get the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U]) + +/** + * @brief This macro set the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) + +/** + * @brief This macro get the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the free trigger comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the free trigger comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) + +/** + * @brief This macro set the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the period of specified channel. + * @note This new setting will take effect on next EPWM period. + * @note EPWM counter will stop if period length set to 0. + * \hideinitializer + */ +#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) + +/** + * @brief This macro get the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the period of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the period of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) + +/** + * @brief This macro set the EPWM aligned type + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32AlignedType EPWM aligned type, valid values are: + * - \ref EPWM_EDGE_ALIGNED + * - \ref EPWM_CENTER_ALIGNED + * @return None + * @details This macro is used to set the EPWM aligned type of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ + } \ + }while(0) + +/** + * @brief Set load window of window loading mode for specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to set load window of window loading mode for specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) + +/** + * @brief Trigger synchronous event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @return None + * @details This macro is used to trigger synchronous event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1))) + +/** + * @brief Clear counter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to clear counter of specified channel(s). + * \hideinitializer + */ +#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) { \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + +/** + * @brief Trigger brake event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @param[in] u32BrakeType Type of brake trigger. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This macro is used to trigger brake event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) + +/** + * @brief Set Dead zone clock source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @return None + * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. + * @note The write-protection function should be disabled before using this function. + * \hideinitializer + */ +#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ + ((epwm)->DTCTL[(u32ChannelNum) >> 1] = (((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \ + ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); +void EPWM_EnableSyncPinInverse(EPWM_T *epwm); +void EPWM_DisableSyncPinInverse(EPWM_T *epwm); +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EPWM_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/fmc.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/fmc.h new file mode 100644 index 00000000000..2b2a083281d --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/fmc.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file fmc.h + * @version V1.00 + * @brief M480 Series Flash Memory Controller Driver Header File + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __FMC_H__ +#define __FMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_APROM_BASE 0x00000000UL /*!< APROM base address \hideinitializer */ +#define FMC_APROM_END 0x00080000UL /*!< APROM end address \hideinitializer */ +#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address \hideinitializer */ +#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM base address \hideinitializer */ +#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address \hideinitializer */ +#define FMC_SPROM_BASE 0x00200000UL /*!< SPROM base address \hideinitializer */ +#define FMC_SPROM_END 0x00201000UL /*!< SPROM end address \hideinitializer */ +#define FMC_CONFIG_BASE 0x00300000UL /*!< User Configuration address \hideinitializer */ +#define FMC_USER_CONFIG_0 0x00300000UL /*!< User Config 0 address \hideinitializer */ +#define FMC_USER_CONFIG_1 0x00300004UL /*!< User Config 1 address \hideinitializer */ +#define FMC_USER_CONFIG_2 0x00300008UL /*!< User Config 2 address \hideinitializer */ +#define FMC_KPROM_BASE 0x00301000UL /*!< Security ROM base address \hideinitializer */ +#define FMC_OTP_BASE 0x00310000UL /*!< OTP flash base address \hideinitializer */ + +#define FMC_FLASH_PAGE_SIZE 0x1000UL /*!< Flash Page Size (4K bytes) \hideinitializer */ +#define FMC_PAGE_ADDR_MASK 0xFFFFF000UL /*!< Flash page address mask \hideinitializer */ +#define FMC_MULTI_WORD_PROG_LEN 512 /*!< The maximum length of a multi-word program. */ + +#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size \hideinitializer */ +#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size \hideinitializer */ +#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) \hideinitializer */ +#define FMC_SPROM_SIZE 0x1000UL /*!< SPROM Size (4 Kbytes) \hideinitializer */ +#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCMD constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read flash word \hideinitializer */ +#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID \hideinitializer */ +#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result \hideinitializer */ +#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID \hideinitializer */ +#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID \hideinitializer */ +#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read checksum \hideinitializer */ +#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: Write flash word \hideinitializer */ +#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash \hideinitializer */ +#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Erase Flash bank 0 or 1 \hideinitializer */ +#define FMC_ISPCMD_BLOCK_ERASE 0x25UL /*!< ISP Command: Erase 4 pages alignment of APROM in bank 0 or 1 \hideinitializer */ +#define FMC_ISPCMD_PROGRAM_MUL 0x27UL /*!< ISP Command: Multuple word program \hideinitializer */ +#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification \hideinitializer */ +#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run checksum calculation \hideinitializer */ +#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Vector Page Remap \hideinitializer */ +#define FMC_ISPCMD_READ_64 0x40UL /*!< ISP Command: Read double flash word \hideinitializer */ +#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: Write double flash word \hideinitializer */ + +#define IS_BOOT_FROM_APROM 0UL /*!< Is booting from APROM \hideinitializer */ +#define IS_BOOT_FROM_LDROM 1UL /*!< Is booting from LDROM \hideinitializer */ + +#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. \hideinitializer */ +#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. \hideinitializer */ +#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. \hideinitializer */ + + +/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */ + + +/** @addtogroup FMC_EXPORTED_MACROS FMC Exported Macros + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macros */ +/*---------------------------------------------------------------------------------------------------------*/ + +#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM \hideinitializer */ +#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM \hideinitializer */ +#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM update \hideinitializer */ +#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM update \hideinitializer */ +#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable User Config update \hideinitializer */ +#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable User Config update \hideinitializer */ +#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM update \hideinitializer */ +#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM update \hideinitializer */ +#define FMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk) /*!< Enable SPROM update \hideinitializer */ +#define FMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk) /*!< Disable SPROM update \hideinitializer */ +#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP function \hideinitializer */ +#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP function \hideinitializer */ +#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag \hideinitializer */ +#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag \hideinitializer */ + +/*@}*/ /* end of group FMC_EXPORTED_MACROS */ + + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +__STATIC_INLINE uint32_t FMC_ReadCID(void); +__STATIC_INLINE uint32_t FMC_ReadPID(void); +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index); +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index); +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr); +__STATIC_INLINE uint32_t FMC_GetVECMAP(void); + +/** + * @brief Get current vector mapping address. + * @param None + * @return The current vector mapping address. + * @details To get VECMAP value which is the page address for remapping to vector page (0x0). + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + */ +__STATIC_INLINE uint32_t FMC_GetVECMAP(void) +{ + return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk); +} + +/** + * @brief Read company ID + * @param None + * @return The company ID (32-bit) + * @details The company ID of Nuvoton is fixed to be 0xDA + */ +__STATIC_INLINE uint32_t FMC_ReadCID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Read product ID + * @param None + * @return The product ID (32-bit) + * @details This function is used to read product ID. + */ +__STATIC_INLINE uint32_t FMC_ReadPID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Read Unique ID + * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64] + * @return The 32-bit unique ID data of specified UID index. + * @details To read out 96-bit Unique ID. + */ +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; + FMC->ISPADDR = ((uint32_t)u8Index << 2u); + FMC->ISPDAT = 0u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + while(FMC->ISPTRG) {} + + return FMC->ISPDAT; +} + +/** + * @brief To read UCID + * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. + * @return The UCID of specified index + * @details This function is used to read unique chip ID (UCID). + */ +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Set vector mapping address + * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment. + * @return To set VECMAP to remap specified page address to 0x0. + * @details This function is used to set VECMAP to map specified page to vector page (0x0). + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + */ +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr) +{ + FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */ + FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */ + FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG) {} /* Waiting for ISP Done */ +} + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +extern void FMC_Close(void); +extern int32_t FMC_Erase(uint32_t u32PageAddr); +extern int32_t FMC_Erase_SPROM(void); +extern int32_t FMC_Erase_Block(uint32_t u32BlockAddr); +extern int32_t FMC_Erase_Bank(uint32_t u32BankAddr); +extern int32_t FMC_GetBootSource(void); +extern void FMC_Open(void); +extern uint32_t FMC_Read(uint32_t u32Addr); +extern int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1); +extern uint32_t FMC_ReadDataFlashBaseAddr(void); +extern void FMC_SetBootSource(int32_t i32BootSrc); +extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data); +extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1); +extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); +extern int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word); +extern int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word); +extern int32_t FMC_Lock_OTP(uint32_t otp_num); +extern int32_t FMC_Is_OTP_Locked(uint32_t otp_num); +extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count); +extern int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count); +extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count); +extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count); +extern int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM); +extern int32_t FMC_CompareSPKey(uint32_t key[3]); + + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FMC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/gpio.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/gpio.h new file mode 100644 index 00000000000..3caff2064ee --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/gpio.h @@ -0,0 +1,496 @@ +/**************************************************************************//** + * @file GPIO.h + * @version V3.00 + * @brief M480 series GPIO driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ + + +#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode \hideinitializer */ +#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode \hideinitializer */ +#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode \hideinitializer */ +#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge \hideinitializer */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge \hideinitializer */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge \hideinitializer */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High \hideinitializer */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_INTTYPE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode \hideinitializer */ +#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Slew Rate Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode \hideinitializer */ +#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode \hideinitializer */ +#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Pull-up And Pull-down Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode \hideinitializer */ +#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode \hideinitializer */ +#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_DBCTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset \hideinitializer */ +#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 \hideinitializer */ + +#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz \hideinitializer */ +#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK \hideinitializer */ + +#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks \hideinitializer */ + + +/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + Example 1: + + PA0 = 1; + + It is used to set GPIO PA.0 to high; + + Example 2: + + if (PA0) + PA0 = 0; + + If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low. + */ +#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) /*!< Pin Data Input/Output \hideinitializer */ +#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output \hideinitializer */ +#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output \hideinitializer */ +#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output \hideinitializer */ +#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output \hideinitializer */ +#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output \hideinitializer */ +#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output \hideinitializer */ +#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output \hideinitializer */ +#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output \hideinitializer */ +#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output \hideinitializer */ +#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output \hideinitializer */ +#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output \hideinitializer */ +#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output \hideinitializer */ +#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output \hideinitializer */ +#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output \hideinitializer */ +#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output \hideinitializer */ +#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output \hideinitializer */ +#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output \hideinitializer */ +#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output \hideinitializer */ +#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output \hideinitializer */ +#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output \hideinitializer */ +#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output \hideinitializer */ +#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output \hideinitializer */ +#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output \hideinitializer */ +#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output \hideinitializer */ +#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output \hideinitializer */ +#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output \hideinitializer */ +#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output \hideinitializer */ +#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output \hideinitializer */ +#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output \hideinitializer */ +#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output \hideinitializer */ +#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output \hideinitializer */ +#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output \hideinitializer */ +#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output \hideinitializer */ +#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output \hideinitializer */ +#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output \hideinitializer */ +#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output \hideinitializer */ +#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output \hideinitializer */ +#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output \hideinitializer */ +#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output \hideinitializer */ +#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output \hideinitializer */ +#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output \hideinitializer */ +#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output \hideinitializer */ +#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output \hideinitializer */ +#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output \hideinitializer */ +#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output \hideinitializer */ +#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output \hideinitializer */ +#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output \hideinitializer */ +#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output \hideinitializer */ +#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output \hideinitializer */ +#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output \hideinitializer */ +#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output \hideinitializer */ +#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output \hideinitializer */ +#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output \hideinitializer */ +#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output \hideinitializer */ +#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output \hideinitializer */ +#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output \hideinitializer */ +#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output \hideinitializer */ +#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output \hideinitializer */ +#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output \hideinitializer */ +#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output \hideinitializer */ +#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output \hideinitializer */ +#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output \hideinitializer */ +#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output \hideinitializer */ +#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output \hideinitializer */ +#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output \hideinitializer */ +#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output \hideinitializer */ +#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output \hideinitializer */ +#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output \hideinitializer */ +#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output \hideinitializer */ +#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output \hideinitializer */ +#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output \hideinitializer */ +#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output \hideinitializer */ +#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output \hideinitializer */ +#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output \hideinitializer */ +#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output \hideinitializer */ +#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output \hideinitializer */ +#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output \hideinitializer */ +#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output \hideinitializer */ +#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output \hideinitializer */ +#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output \hideinitializer */ +#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output \hideinitializer */ +#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output \hideinitializer */ +#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output \hideinitializer */ +#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output \hideinitializer */ +#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output \hideinitializer */ +#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output \hideinitializer */ +#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output \hideinitializer */ +#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output \hideinitializer */ +#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output \hideinitializer */ +#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output \hideinitializer */ +#define PG0 GPIO_PIN_DATA(6, 0 ) /*!< Specify PG.0 Pin Data Input/Output \hideinitializer */ +#define PG1 GPIO_PIN_DATA(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output \hideinitializer */ +#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output \hideinitializer */ +#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output \hideinitializer */ +#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output \hideinitializer */ +#define PG5 GPIO_PIN_DATA(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output \hideinitializer */ +#define PG6 GPIO_PIN_DATA(6, 6 ) /*!< Specify PG.6 Pin Data Input/Output \hideinitializer */ +#define PG7 GPIO_PIN_DATA(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output \hideinitializer */ +#define PG8 GPIO_PIN_DATA(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output \hideinitializer */ +#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output \hideinitializer */ +#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output \hideinitializer */ +#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output \hideinitializer */ +#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output \hideinitializer */ +#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output \hideinitializer */ +#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output \hideinitializer */ +#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output \hideinitializer */ +#define PH0 GPIO_PIN_DATA(7, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */ +#define PH1 GPIO_PIN_DATA(7, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */ +#define PH2 GPIO_PIN_DATA(7, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */ +#define PH3 GPIO_PIN_DATA(7, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */ +#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */ +#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */ +#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */ +#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */ +#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */ +#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */ +#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */ +#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */ + + +/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */ + + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask)) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask)) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask)) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask)) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask)) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC. + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be + * - \ref GPIO_DBCTL_DBCLKSEL_1 + * - \ref GPIO_DBCTL_DBCLKSEL_2 + * - \ref GPIO_DBCTL_DBCLKSEL_4 + * - \ref GPIO_DBCTL_DBCLKSEL_8 + * - \ref GPIO_DBCTL_DBCLKSEL_16 + * - \ref GPIO_DBCTL_DBCLKSEL_32 + * - \ref GPIO_DBCTL_DBCLKSEL_64 + * - \ref GPIO_DBCTL_DBCLKSEL_128 + * - \ref GPIO_DBCTL_DBCLKSEL_256 + * - \ref GPIO_DBCTL_DBCLKSEL_512 + * - \ref GPIO_DBCTL_DBCLKSEL_1024 + * - \ref GPIO_DBCTL_DBCLKSEL_2048 + * - \ref GPIO_DBCTL_DBCLKSEL_4096 + * - \ref GPIO_DBCTL_DBCLKSEL_8192 + * - \ref GPIO_DBCTL_DBCLKSEL_16384 + * - \ref GPIO_DBCTL_DBCLKSEL_32768 + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n + * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us, + * and system will sampling interrupt input once per 00 us. + * \hideinitializer + */ +#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel))) + +/** + * @brief Get GPIO Port IN Data + * +* @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * + * @return The specified port data + * + * @details Get the PIN register of specified GPIO port. + * \hideinitializer + */ +#define GPIO_GET_IN_DATA(port) ((port)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Data GPIO port data. + * + * @return None + * + * @details Set the Data into specified GPIO port. + * \hideinitializer + */ +#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data)) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @return None + * + * @details Toggle the specified GPIO pint. + * \hideinitializer + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + + +/** + * @brief Enable External GPIO interrupt + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + * \hideinitializer + */ +#define GPIO_EnableEINT GPIO_EnableInt + +/** + * @brief Disable External GPIO interrupt + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + * \hideinitializer + */ +#define GPIO_DisableEINT GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin); +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_H__ */ + +/*** (C) COPYRIGHT 2013~2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/hsotg.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/hsotg.h new file mode 100644 index 00000000000..b73ad24cfd5 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/hsotg.h @@ -0,0 +1,268 @@ +/**************************************************************************//** + * @file hsotg.h + * @version V0.10 + * @brief M480 Series HSOTG Driver Header File + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __HSOTG_H__ +#define __HSOTG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSOTG_Driver HSOTG Driver + @{ +*/ + + +/** @addtogroup HSOTG_EXPORTED_CONSTANTS HSOTG Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* HSOTG constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define HSOTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */ +#define HSOTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */ +#define HSOTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */ +#define HSOTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */ + + +/*@}*/ /* end of group HSOTG_EXPORTED_CONSTANTS */ + + +/** @addtogroup HSOTG_EXPORTED_FUNCTIONS HSOTG Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable HSOTG function + * @param None + * @return None + * @details This macro will set OTGEN bit of HSOTG_CTL register to enable HSOTG function. + * \hideinitializer + */ +#define HSOTG_ENABLE() (HSOTG->CTL |= HSOTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to disable HSOTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of HSOTG_CTL register to disable HSOTG function. + * \hideinitializer + */ +#define HSOTG_DISABLE() (HSOTG->CTL &= ~HSOTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as HSOTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of HSOTG_PHYCTL register to enable USB PHY. + * \hideinitializer + */ +#define HSOTG_ENABLE_PHY() (HSOTG->PHYCTL |= HSOTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of HSOTG_PHYCTL register to disable USB PHY. + * \hideinitializer + */ +#define HSOTG_DISABLE_PHY() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of HSOTG_PHYCTL register to enable ID detection function. + * \hideinitializer + */ +#define HSOTG_ENABLE_ID_DETECT() (HSOTG->PHYCTL |= HSOTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of HSOTG_PHYCTL register to disable ID detection function. + * \hideinitializer + */ +#define HSOTG_DISABLE_ID_DETECT() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to enable HSOTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of HSOTG_CTL register to enable HSOTG wake-up function. + * \hideinitializer + */ +#define HSOTG_ENABLE_WAKEUP() (HSOTG->CTL |= HSOTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable HSOTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of HSOTG_CTL register to disable HSOTG wake-up function. + * \hideinitializer + */ +#define HSOTG_DISABLE_WAKEUP() (HSOTG->CTL &= ~HSOTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref HSOTG_VBUS_EN_ACTIVE_HIGH + * - \ref HSOTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + * \hideinitializer + */ +#define HSOTG_SET_VBUS_EN_POL(u32Pol) (HSOTG->PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask)) + +/** + * @brief This macro is used to disable HSOTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTEN_ROLECHGIEN_Msk + * - \ref HSOTG_INTEN_VBEIEN_Msk + * - \ref HSOTG_INTEN_SRPFIEN_Msk + * - \ref HSOTG_INTEN_HNPFIEN_Msk + * - \ref HSOTG_INTEN_GOIDLEIEN_Msk + * - \ref HSOTG_INTEN_IDCHGIEN_Msk + * - \ref HSOTG_INTEN_PDEVIEN_Msk + * - \ref HSOTG_INTEN_HOSTIEN_Msk + * - \ref HSOTG_INTEN_BVLDCHGIEN_Msk + * - \ref HSOTG_INTEN_AVLDCHGIEN_Msk + * - \ref HSOTG_INTEN_VBCHGIEN_Msk + * - \ref HSOTG_INTEN_SECHGIEN_Msk + * - \ref HSOTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable HSOTG related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_DISABLE_INT(u32Mask) (HSOTG->INTEN &= ~(u32Mask)) + +/** + * @brief This macro is used to get HSOTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTSTS_ROLECHGIF_Msk + * - \ref HSOTG_INTSTS_VBEIF_Msk + * - \ref HSOTG_INTSTS_SRPFIF_Msk + * - \ref HSOTG_INTSTS_HNPFIF_Msk + * - \ref HSOTG_INTSTS_GOIDLEIF_Msk + * - \ref HSOTG_INTSTS_IDCHGIF_Msk + * - \ref HSOTG_INTSTS_PDEVIF_Msk + * - \ref HSOTG_INTSTS_HOSTIF_Msk + * - \ref HSOTG_INTSTS_BVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_AVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_VBCHGIF_Msk + * - \ref HSOTG_INTSTS_SECHGIF_Msk + * - \ref HSOTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return HSOTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_GET_INT_FLAG(u32Mask) (HSOTG->INTSTS & (u32Mask)) + +/** + * @brief This macro is used to clear HSOTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTSTS_ROLECHGIF_Msk + * - \ref HSOTG_INTSTS_VBEIF_Msk + * - \ref HSOTG_INTSTS_SRPFIF_Msk + * - \ref HSOTG_INTSTS_HNPFIF_Msk + * - \ref HSOTG_INTSTS_GOIDLEIF_Msk + * - \ref HSOTG_INTSTS_IDCHGIF_Msk + * - \ref HSOTG_INTSTS_PDEVIF_Msk + * - \ref HSOTG_INTSTS_HOSTIF_Msk + * - \ref HSOTG_INTSTS_BVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_AVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_VBCHGIF_Msk + * - \ref HSOTG_INTSTS_SECHGIF_Msk + * - \ref HSOTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear HSOTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_CLR_INT_FLAG(u32Mask) (HSOTG->INTSTS = (u32Mask)) + +/** + * @brief This macro is used to get HSOTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref HSOTG_STATUS_OVERCUR_Msk + * - \ref HSOTG_STATUS_IDSTS_Msk + * - \ref HSOTG_STATUS_SESSEND_Msk + * - \ref HSOTG_STATUS_BVLD_Msk + * - \ref HSOTG_STATUS_AVLD_Msk + * - \ref HSOTG_STATUS_VBUSVLD_Msk + * @return The user specified status. + * @details This macro will return HSOTG related status specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_GET_STATUS(u32Mask) (HSOTG->STATUS & (u32Mask)) + + + +/*@}*/ /* end of group HSOTG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HSOTG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* __HSOTG_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/hsusbd.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/hsusbd.h new file mode 100644 index 00000000000..f09cf9ad1b2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/hsusbd.h @@ -0,0 +1,382 @@ +/**************************************************************************//** + * @file hsusbd.h + * @version V1.00 + * @brief M480 HSUSBD driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBD_H__ +#define __HSUSBD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSUSBD_Driver HSUSBD Driver + @{ +*/ + +/** @addtogroup HSUSBD_EXPORTED_CONSTANTS HSUSBD Exported Constants + @{ +*/ +/** @cond HIDDEN_SYMBOLS */ +#define HSUSBD_MAX_EP 12ul + +#define Maximum(a,b) (a)>(b) ? (a) : (b) +#define Minimum(a,b) (((a)<(b)) ? (a) : (b)) + + +#define CEP 0xfful /*!< Control Endpoint \hideinitializer */ +#define EPA 0ul /*!< Endpoint A \hideinitializer */ +#define EPB 1ul /*!< Endpoint B \hideinitializer */ +#define EPC 2ul /*!< Endpoint C \hideinitializer */ +#define EPD 3ul /*!< Endpoint D \hideinitializer */ +#define EPE 4ul /*!< Endpoint E \hideinitializer */ +#define EPF 5ul /*!< Endpoint F \hideinitializer */ +#define EPG 6ul /*!< Endpoint G \hideinitializer */ +#define EPH 7ul /*!< Endpoint H \hideinitializer */ +#define EPI 8ul /*!< Endpoint I \hideinitializer */ +#define EPJ 9ul /*!< Endpoint J \hideinitializer */ +#define EPK 10ul /*!< Endpoint K \hideinitializer */ +#define EPL 11ul /*!< Endpoint L \hideinitializer */ + +/** @endcond HIDDEN_SYMBOLS */ +/********************* Bit definition of CEPCTL register **********************/ +#define HSUSBD_CEPCTL_NAKCLR ((uint32_t)0x00000000ul) /*!PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk|HSUSBD_PHYCTL_DPPUEN_Msk))) /*!PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!PHYCTL |= HSUSBD_PHYCTL_PHYEN_Msk)) /*!PHYCTL &= ~HSUSBD_PHYCTL_PHYEN_Msk)) /*!PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!PHYCTL |= HSUSBD_PHYCTL_DPPUEN_Msk)) /*!FADDR = (addr)) /*!FADDR)) /*!GINTEN = (intr)) /*!BUSINTEN = (intr)) /*!BUSINTSTS) /*!BUSINTSTS = (flag)) /*!CEPINTEN = (intr)) /*!CEPINTSTS = (flag)) /*!CEPCTL = (flag)) /*!CEPTXCNT = (size)) /*!EP[(ep)].EPMPS = (size)) /*!EP[(ep)].EPINTEN = (intr)) /*!EP[(ep)].EPINTSTS) /*!EP[(ep)].EPINTSTS = (flag)) /*!DMACNT = (len)) /*!DMAADDR = (addr)) /*!DMACTL = (HSUSBD->DMACTL & ~HSUSBD_DMACTL_EPNUM_Msk) | HSUSBD_DMACTL_DMARD_Msk | (epnum) | 0x100) /*!DMACTL = (HSUSBD->DMACTL & ~(HSUSBD_DMACTL_EPNUM_Msk | HSUSBD_DMACTL_DMARD_Msk | 0x100)) | (epnum)) /*!DMACTL |= HSUSBD_DMACTL_DMAEN_Msk) /*!PHYCTL & HSUSBD_PHYCTL_VBUSDET_Msk)) /*!DMACNT = 0ul; + HSUSBD->DMACTL = 0x80ul; + HSUSBD->DMACTL = 0x00ul; +} +/** + * @brief HSUSBD_SetEpBufAddr, Set Endpoint buffer address + * @param[in] u32Ep Endpoint Number + * @param[in] u32Base Buffer Start Address + * @param[in] u32Len Buffer length + * @retval None. + */ +__STATIC_INLINE void HSUSBD_SetEpBufAddr(uint32_t u32Ep, uint32_t u32Base, uint32_t u32Len) +{ + if (u32Ep == CEP) + { + HSUSBD->CEPBUFST = u32Base; + HSUSBD->CEPBUFEND = u32Base + u32Len - 1ul; + } + else + { + HSUSBD->EP[u32Ep].EPBUFST = u32Base; + HSUSBD->EP[u32Ep].EPBUFEND = u32Base + u32Len - 1ul; + } +} + +/** + * @brief HSUSBD_ConfigEp, Config Endpoint + * @param[in] u32Ep USB endpoint + * @param[in] u32EpNum Endpoint number + * @param[in] u32EpType Endpoint type + * @param[in] u32EpDir Endpoint direction + * @retval None. + */ +__STATIC_INLINE void HSUSBD_ConfigEp(uint32_t u32Ep, uint32_t u32EpNum, uint32_t u32EpType, uint32_t u32EpDir) +{ + if (u32EpType == HSUSBD_EP_CFG_TYPE_BULK) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_AUTO); + } + else if (u32EpType == HSUSBD_EP_CFG_TYPE_INT) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_MANUAL); + } + else if (u32EpType == HSUSBD_EP_CFG_TYPE_ISO) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_FLY); + } + + HSUSBD->EP[u32Ep].EPCFG = (u32EpType|u32EpDir|HSUSBD_EP_CFG_VALID|(u32EpNum << 4)); +} + +/** + * @brief Set USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @return None + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + */ +__STATIC_INLINE void HSUSBD_SetEpStall(uint32_t u32Ep) +{ + if (u32Ep == CEP) + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL); + } + else + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT; + } +} + +/** + * @brief Set USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @return None + * + * @details Set USB endpoint stall state, endpoint will return STALL token. + */ +__STATIC_INLINE void HSUSBD_SetStall(uint32_t u32EpNum) +{ + uint32_t i; + + if (u32EpNum == 0ul) + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL); + } + else + { + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT; + } + } + } +} + +/** + * @brief Clear USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @return None + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void HSUSBD_ClearEpStall(uint32_t u32Ep) +{ + HSUSBD->EP[u32Ep].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @return None + * + * @details Clear USB endpoint stall state, endpoint will return ACK/NAK token. + */ +__STATIC_INLINE void HSUSBD_ClearStall(uint32_t u32EpNum) +{ + uint32_t i; + + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; + } + } +} + +/** + * @brief Get USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * @details Get USB endpoint stall state of the specified endpoint ID. + */ +__STATIC_INLINE uint32_t HSUSBD_GetEpStall(uint32_t u32Ep) +{ + return (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT); +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @retval 0: USB endpoint is not stalled. + * @retval non-0: USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + */ +__STATIC_INLINE uint32_t HSUSBD_GetStall(uint32_t u32EpNum) +{ + uint32_t i; + uint32_t val = 0ul; + + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + val = (HSUSBD->EP[i].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT); + break; + } + } + return val; +} + + +/*-------------------------------------------------------------------------------------------*/ +typedef void (*HSUSBD_VENDOR_REQ)(void); /*!CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl)) + +/** + * @brief The macro is used to set START condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus START condition in I2C_CTL register. + * \hideinitializer + */ +#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk) + +/** + * @brief The macro is used to wait I2C bus status get ready + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register. + * \hideinitializer + */ +#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk)) + +/** + * @brief The macro is used to Read I2C Bus Data Register + * + * @param[in] i2c Specify I2C port + * + * @return A byte of I2C data register + * + * @details I2C controller read data from bus and save it in I2CDAT register. + * \hideinitializer + */ +#define I2C_GET_DATA(i2c) ((i2c)->DAT) + +/** + * @brief Write a Data to I2C Data Register + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data A byte that writes to data register + * + * @return None + * + * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus. + * \hideinitializer + */ +#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data)) + +/** + * @brief Get I2C Bus status code + * + * @param[in] i2c Specify I2C port + * + * @return I2C status code + * + * @details To get this status code to monitor I2C bus event. + * \hideinitializer + */ +#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0) + +/** + * @brief Get Time-out flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 I2C Bus time-out is not happened + * @retval 1 I2C Bus time-out is happened + * + * @details When I2C bus occurs time-out event, the time-out flag will be set. + * \hideinitializer + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 ) + +/** + * @brief To get wake-up flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details I2C bus occurs wake-up event, wake-up flag will be set. + * \hideinitializer + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 ) + +/** + * @brief To clear wake-up flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up flag is set, use this macro to clear it. + * \hideinitializer + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk) + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * \hideinitializer + * + */ +#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS) + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return Packet error check byte value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * \hideinitializer + */ +#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC) + +/** + * @brief Set SMBus Bytes number of Transmission or reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * \hideinitializer + */ +#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize)) + +/** + * @brief Enable SMBus Alert function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger) + * \hideinitializer + */ +#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Disable SMBus Alert pin function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger) + * \hideinitializer + */ +#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is output mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode. + * + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is input mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode. + * + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin output high state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state. + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk) + + +/** + * @brief Set SMBus SUSCON pin output low state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state. + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk) + +/** + * @brief Enable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse. + * \hideinitializer + */ +#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Disable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable acknowledge response control by user. + * \hideinitializer + */ +#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Enable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * \hideinitializer + */ +#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Disable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * \hideinitializer + */ +#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Enable SMBus PEC clear at REPEAT START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation. + * \hideinitializer + */ +#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Disable SMBus PEC clear at Repeat START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable the condition of Repeat START can clear the PEC calculation. + * \hideinitializer + */ +#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Enable RX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Enable TX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Enable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared. + * \hideinitializer + */ +#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Disable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C will send STOP after PDMA transfers done automatically. + * \hideinitializer + */ +#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Reset PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C PDMA engine will be reset after this function is called. + * \hideinitializer + */ +#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c); + +/** + * @brief The macro is used to set STOP condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus STOP condition in I2C_CTL register. + */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c) +{ + + (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk); + while(i2c->CTL0 & I2C_CTL0_STO_Msk) + { + } +} + +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Close(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +uint8_t I2C_GetData(I2C_T *i2c); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag); +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr); +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint32_t I2C_SMBusGetStatus(I2C_T *i2c); +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize); +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice); +void I2C_SMBusClose(I2C_T *i2c); +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn); +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c); +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk); +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/i2s.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/i2s.h new file mode 100644 index 00000000000..f6ae32b4ff9 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/i2s.h @@ -0,0 +1,352 @@ +/****************************************************************************//** + * @file i2s.h + * @version V0.10 + * @brief M480 I2S driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __I2S_H__ +#define __I2S_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants + @{ +*/ +#define I2S_DATABIT_8 (0U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define I2S_DATABIT_16 (1U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define I2S_DATABIT_24 (2U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define I2S_DATABIT_32 (3U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* Audio Format */ +#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */ +#define I2S_DISABLE_MONO (0U) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define I2S_FORMAT_I2S (0U << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */ +#define I2S_FORMAT_I2S_MSB (1U << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */ +#define I2S_FORMAT_I2S_LSB (2U << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */ +#define I2S_FORMAT_PCM (4U << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */ +#define I2S_FORMAT_PCM_MSB (5U << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */ +#define I2S_FORMAT_PCM_LSB (6U << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */ + +/* I2S Data Format */ +#define I2S_ORDER_AT_MSB (0U) /*!< Channel data is at MSB \hideinitializer */ +#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */ + +/* I2S TDM Channel Number */ +#define I2S_TDM_2CH 0U /*!< Use TDM 2 channel \hideinitializer */ +#define I2S_TDM_4CH 1U /*!< Use TDM 4 channel \hideinitializer */ +#define I2S_TDM_6CH 2U /*!< Use TDM 6 channel \hideinitializer */ +#define I2S_TDM_8CH 3U /*!< Use TDM 8 channel \hideinitializer */ + +/* I2S TDM Channel Width */ +#define I2S_TDM_WIDTH_8BIT 0U /*!< TDM channel witch is 8-bit \hideinitializer */ +#define I2S_TDM_WIDTH_16BIT 1U /*!< TDM channel witch is 16-bit \hideinitializer */ +#define I2S_TDM_WIDTH_24BIT 2U /*!< TDM channel witch is 24-bit \hideinitializer */ +#define I2S_TDM_WIDTH_32BIT 3U /*!< TDM channel witch is 32-bit \hideinitializer */ + +/* I2S TDM Sync Width */ +#define I2S_TDM_SYNC_ONE_BCLK 0U /*!< TDM sync widht is one BLCK period \hideinitializer */ +#define I2S_TDM_SYNC_ONE_CHANNEL 1U /*!< TDM sync widht is one channel period \hideinitializer */ + +/* I2S Operation mode */ +#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */ +#define I2S_MODE_MASTER (0u) /*!< As master mode \hideinitializer */ + +/* I2S FIFO Threshold */ +#define I2S_FIFO_TX_LEVEL_WORD_0 (0U) /*!< TX threshold is 0 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_1 (1U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_2 (2U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_3 (3U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_4 (4U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_5 (5U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_6 (6U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_7 (7U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_8 (8U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_9 (9U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_10 (10U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_11 (11U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_12 (12U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_13 (13U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_14 (14U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_15 (15U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */ + +#define I2S_FIFO_RX_LEVEL_WORD_1 (0U) /*!< RX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_2 (1U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_3 (2U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_4 (3U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_5 (4U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_6 (5U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_7 (6U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_8 (7U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_9 (8U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_10 (9U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_11 (10U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_12 (11U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_13 (12U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_14 (13U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_15 (14U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_16 (15U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */ + +/* I2S Record Channel */ +#define I2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */ +#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */ + +/* I2S Channel */ +#define I2S_RIGHT (0U) /*!< Select right channel \hideinitializer */ +#define I2S_LEFT (1U) /*!< Select left channel \hideinitializer */ + +/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Enable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0U) && (u32ChMask < 9U)) + { + i2s->CTL1 |= ((uint32_t)1U << (u32ChMask-1U)); + } +} + +/** + * @brief Disable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0U) && (u32ChMask < 9U)) + { + i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask-1U)); + } +} + +/** + * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk ) + +/** + * @brief Disable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk ) + +/** + * @brief Enable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk ) + +/** + * @brief Disable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk ) + +/** + * @brief Enable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk ) + +/** + * @brief Disable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk ) + +/** + * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk ) + +/** + * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref I2S_MONO_LEFT + * - \ref I2S_MONO_RIGHT + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch) +{ + u32Ch == I2S_MONO_LEFT ? + (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) : + (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk); +} + +/** + * @brief Write data to I2S Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Data: The data written to FIFO. + * @return none + * \hideinitializer + */ +#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) ) + +/** + * @brief Read Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return Data in Rx FIFO. + * \hideinitializer + */ +#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO ) + +/** + * @brief This function gets the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) ) + +/** + * @brief This function clears the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) ) + +/** + * @brief This function gets the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) ) + +/** + * @brief This function clears the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF ) + +void I2S_Close(I2S_T *i2s); +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); +void I2S_DisableMCLK(I2S_T *i2s); +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth); +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat); + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/opa.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/opa.h new file mode 100644 index 00000000000..3f2b5926588 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/opa.h @@ -0,0 +1,208 @@ +/**************************************************************************//** + * @file opa.h + * @version V3.00 + * @brief M480 series OPA driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OPA_H__ +#define __OPA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup OPA_Driver OPA Driver + @{ +*/ + +/** @addtogroup OPA_EXPORTED_CONSTANTS OPA Exported Constants + @{ +*/ +#define OPA_CALIBRATION_CLK_1K (0UL) /*!< OPA calibration clock select 1 KHz \hideinitializer */ +#define OPA_CALIBRATION_RV_1_2_AVDD (0UL) /*!< OPA calibration reference voltage select 1/2 AVDD \hideinitializer */ +#define OPA_CALIBRATION_RV_H_L_VCM (1UL) /*!< OPA calibration reference voltage select from high vcm to low vcm \hideinitializer */ + +/*@}*/ /* end of group OPA_EXPORTED_CONSTANTS */ + +/** @addtogroup OPA_EXPORTED_FUNCTIONS OPA Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define OPA functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, uint32_t u32OpaNum, uint32_t u32ClockSel, uint32_t u32LevelSel); + +/** + * @brief This macro is used to power on the OPA circuit + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will set OPx_EN (x=0, 1) bit of OPACR register to power on the OPA circuit. + * @note Remember to enable HIRC clock while power on the OPA circuit. + * \hideinitializer + */ +#define OPA_POWER_ON(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to power down the OPA circuit + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will clear OPx_EN (x=0, 1) bit of OPACR register to power down the OPA circuit. + * \hideinitializer + */ +#define OPA_POWER_DOWN(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to enable the OPA Schmitt trigger buffer + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will set OPSCHx_EN (x=0, 1) bit of OPACR register to enable the OPA Schmitt trigger buffer. + * \hideinitializer + */ +#define OPA_ENABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to disable the OPA Schmitt trigger buffer + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will clear OPSCHx_EN (x=0, 1) bit of OPACR register to disable the OPA Schmitt trigger buffer. + * \hideinitializer + */ +#define OPA_DISABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to enable OPA Schmitt trigger digital output interrupt + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will set OPDIEx (x=0, 1) bit of OPACR register to enable the OPA Schmitt trigger digital output interrupt. + * \hideinitializer + */ +#define OPA_ENABLE_INT(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to disable OPA Schmitt trigger digital output interrupt + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will clear OPDIEx (x=0, 1) bit of OPACR register to disable the OPA Schmitt trigger digital output interrupt. + * \hideinitializer + */ +#define OPA_DISABLE_INT(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to get OPA digital output state + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return OPA digital output state + * @details This macro will return the OPA digital output value. + * \hideinitializer + */ +#define OPA_GET_DIGITAL_OUTPUT(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDO0_Msk<<(u32OpaNum)))?1UL:0UL) + +/** + * @brief This macro is used to get OPA interrupt flag + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @retval 0 OPA interrupt does not occur. + * @retval 1 OPA interrupt occurs. + * @details This macro will return the ACMP interrupt flag. + * \hideinitializer + */ +#define OPA_GET_INT_FLAG(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum)))?1UL:0UL) + +/** + * @brief This macro is used to clear OPA interrupt flag + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @return None + * @details This macro will write 1 to OPDFx (x=0,1) bit of OPASR register to clear interrupt flag. + * \hideinitializer + */ +#define OPA_CLR_INT_FLAG(opa, u32OpaNum) ((opa)->STATUS = (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum))) + + +/** + * @brief This function is used to configure and start OPA calibration + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2. + * @param[in] u32ClockSel Select OPA calibration clock + * - \ref OPA_CALIBRATION_CLK_1K + * @param[in] u32RefVol Select OPA reference voltage + * - \ref OPA_CALIBRATION_RV_1_2_AVDD + * - \ref OPA_CALIBRATION_RV_H_L_VCM + * @retval 0 PMOS and NMOS calibration successfully. + * @retval -1 only PMOS calibration failed. + * @retval -2 only NMOS calibration failed. + * @retval -3 PMOS and NMOS calibration failed. + */ +__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, + uint32_t u32OpaNum, + uint32_t u32ClockSel, + uint32_t u32RefVol) +{ + uint32_t u32CALResult; + int32_t i32Ret = 0L; + + (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALCLK0_Msk << (u32OpaNum << 1))); + (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALRVS0_Msk << (u32OpaNum))) | (((u32RefVol) << OPA_CALCTL_CALRVS0_Pos) << (u32OpaNum)); + (opa)->CALCTL |= (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum)); + while((opa)->CALCTL & (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum))) {} + + u32CALResult = ((opa)->CALST >> ((u32OpaNum)*4U)) & (OPA_CALST_CALNS0_Msk|OPA_CALST_CALPS0_Msk); + if (u32CALResult == 0U) + { + i32Ret = 0L; + } + else if (u32CALResult == OPA_CALST_CALNS0_Msk) + { + i32Ret = -2L; + } + else if (u32CALResult == OPA_CALST_CALPS0_Msk) + { + i32Ret = -1L; + } + else if (u32CALResult == (OPA_CALST_CALNS0_Msk|OPA_CALST_CALPS0_Msk)) + { + i32Ret = -3L; + } + + return i32Ret; +} + +/** + * @brief This macro is used to generate asynchronous reset signals to OPA controller + * @param None + * @return None + * \hideinitializer + */ +#define OPA_Reset() \ +do { \ + SYS->IPRST2 |= SYS_IPRST2_OPARST_Msk; \ + SYS->IPRST2 &= ~SYS_IPRST2_OPARST_Msk; \ +} while(0) + +/*@}*/ /* end of group OPA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group OPA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __OPA_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/otg.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/otg.h new file mode 100644 index 00000000000..b0af0c421d2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/otg.h @@ -0,0 +1,268 @@ +/**************************************************************************//** + * @file otg.h + * @version V0.10 + * @brief M480 Series OTG Driver Header File + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __OTG_H__ +#define __OTG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup OTG_Driver OTG Driver + @{ +*/ + + +/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* OTG constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */ +#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */ +#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */ +#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */ + + +/*@}*/ /* end of group OTG_EXPORTED_CONSTANTS */ + + +/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable OTG function + * @param None + * @return None + * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function. + * \hideinitializer + */ +#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to disable OTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function. + * \hideinitializer + */ +#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as OTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY. + * \hideinitializer + */ +#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY. + * \hideinitializer + */ +#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function. + * \hideinitializer + */ +#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function. + * \hideinitializer + */ +#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to enable OTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function. + * \hideinitializer + */ +#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable OTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function. + * \hideinitializer + */ +#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref OTG_VBUS_EN_ACTIVE_HIGH + * - \ref OTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + * \hideinitializer + */ +#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask)) + +/** + * @brief This macro is used to disable OTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTEN_ROLECHGIEN_Msk + * - \ref OTG_INTEN_VBEIEN_Msk + * - \ref OTG_INTEN_SRPFIEN_Msk + * - \ref OTG_INTEN_HNPFIEN_Msk + * - \ref OTG_INTEN_GOIDLEIEN_Msk + * - \ref OTG_INTEN_IDCHGIEN_Msk + * - \ref OTG_INTEN_PDEVIEN_Msk + * - \ref OTG_INTEN_HOSTIEN_Msk + * - \ref OTG_INTEN_BVLDCHGIEN_Msk + * - \ref OTG_INTEN_AVLDCHGIEN_Msk + * - \ref OTG_INTEN_VBCHGIEN_Msk + * - \ref OTG_INTEN_SECHGIEN_Msk + * - \ref OTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable OTG related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask)) + +/** + * @brief This macro is used to get OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return OTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask)) + +/** + * @brief This macro is used to clear OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask)) + +/** + * @brief This macro is used to get OTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref OTG_STATUS_OVERCUR_Msk + * - \ref OTG_STATUS_IDSTS_Msk + * - \ref OTG_STATUS_SESSEND_Msk + * - \ref OTG_STATUS_BVLD_Msk + * - \ref OTG_STATUS_AVLD_Msk + * - \ref OTG_STATUS_VBUSVLD_Msk + * @return The user specified status. + * @details This macro will return OTG related status specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask)) + + + +/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group OTG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + + +#endif /*__OTG_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/pdma.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/pdma.h new file mode 100644 index 00000000000..fb713e39a3e --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/pdma.h @@ -0,0 +1,384 @@ +/**************************************************************************//** + * @file pdma.h + * @version V1.00 + * @brief M480 series PDMA driver header file + * + * @copyright (C) 2014~2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_H__ +#define __PDMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + +/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ +#define PDMA_CH_MAX 16UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_OP_STOP 0x00000000UL /*!INTSTS)) + +/** + * @brief Get Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_TD_STS(pdma) ((uint32_t)(pdma->TDSTS)) + +/** + * @brief Clear Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TD_FLAG(pdma,u32Mask) ((uint32_t)(pdma->TDSTS = (u32Mask))) + +/** + * @brief Get Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)(pdma->ABTSTS)) + +/** + * @brief Clear Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ABORT_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ABTSTS = (u32Mask))) + +/** + * @brief Get Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)(PDMA->ALIGN)) + +/** + * @brief Clear Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ALIGN = (u32Mask))) + +/** + * @brief Clear Timeout Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details Clear the selected channel timeout interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TMOUT_FLAG(pdma,u32Ch) ((uint32_t)(pdma->INTSTS = (1 << ((u32Ch) + 8)))) + +/** + * @brief Check Channel Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @retval 0 Idle state + * @retval 1 Busy state + * + * @details Check the selected channel is busy or not. + * \hideinitializer + */ +#define PDMA_IS_CH_BUSY(pdma,u32Ch) ((uint32_t)(pdma->TRGSTS & (1 << (u32Ch)))? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + * \hideinitializer + */ +#define PDMA_SET_SRC_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].SA = (u32Addr))) + +/** + * @brief Set Destination Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + * \hideinitializer + */ +#define PDMA_SET_DST_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].DA = (u32Addr))) + +/** + * @brief Set Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32TransCount Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + * \hideinitializer + */ +#define PDMA_SET_TRANS_CNT(pdma,u32Ch, u32TransCount) ((uint32_t)(pdma->DSCT[(u32Ch)].CTL=(pdma->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1) << PDMA_DSCT_CTL_TXCNT_Pos))) + +/** + * @brief Set Scatter-gather descriptor Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The descriptor address + * + * @return None + * + * @details This macro set the selected channel scatter-gather descriptor address. + * \hideinitializer + */ +#define PDMA_SET_SCATTER_DESC(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].NEXT = (u32Addr) - (pdma->SCATBA))) + +/** + * @brief Stop the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + * \hideinitializer + */ +#define PDMA_STOP(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch)))) + +/** + * @brief Pause the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro pause the selected channel. + * \hideinitializer + */ +#define PDMA_PAUSE(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch)))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define PDMA functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_Close(PDMA_T * pdma); +void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); +void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); +void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch); +void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); +void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); + + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PDMA_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/qei.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/qei.h new file mode 100644 index 00000000000..32dde229220 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/qei.h @@ -0,0 +1,389 @@ +/**************************************************************************//** + * @file qei.h + * @version V3.00 + * @brief Quadrature Encoder Interface (QEI) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* QEI counting mode selection constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<CTL &= (~QEI_CTL_CMPEN_Msk)) + +/** + * @brief Enable QEI compare function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI counter compare function. + * \hideinitializer + */ +#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk) + +/** + * @brief Disable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk)) + +/** + * @brief Enable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk) + +/** + * @brief Disable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk)) + +/** + * @brief Enable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk) + +/** + * @brief Disable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHAEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro disable specified QEI signal input. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHBEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro enable specified QEI signal input. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro disable specified QEI signal inverted input polarity. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro inverse specified QEI signal input polarity. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro disable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel)) + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro enable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel)) + +/** + * @brief Disable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI noise filter function. + * \hideinitializer + */ +#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk) + +/** + * @brief Enable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32ClkSel The sampling frequency of the noise filter clock. + * - \ref QEI_CTL_NFCLKSEL_DIV1 + * - \ref QEI_CTL_NFCLKSEL_DIV2 + * - \ref QEI_CTL_NFCLKSEL_DIV4 + * - \ref QEI_CTL_NFCLKSEL_DIV16 + * - \ref QEI_CTL_NFCLKSEL_DIV32 + * - \ref QEI_CTL_NFCLKSEL_DIV64 + * @return None + * @details This macro enable QEI noise filter function and select noise filter clock. + * \hideinitializer + */ +#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel)) + +/** + * @brief Get QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter register value. + * @details This macro get QEI pulse counter value. + * \hideinitializer + */ +#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT) + +/** + * @brief Get QEI counting direction + * @param[in] qei The pointer of the specified QEI module. + * @retval 0 QEI counter is in down-counting. + * @retval 1 QEI counter is in up-counting. + * @details This macro get QEI counting direction. + * \hideinitializer + */ +#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0) + +/** + * @brief Get QEI counter hold value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter hold register value. + * @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control. + * \hideinitializer + */ +#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD) + +/** + * @brief Get QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter index latch value + * @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH) + +/** + * @brief Set QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Val The latch value. + * @return QEI pulse counter index latch value + * @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH = (u32Val)) + +/** + * @brief Get QEI interrupt flag status + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. +* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @retval 0 QEI specified interrupt flag is not set. + * @retval 1 QEI specified interrupt flag is set. + * @details This macro get QEI specified interrupt flag status. + * \hideinitializer + */ +#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0) + + +/** + * @brief Clear QEI interrupt flag + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @return None + * @details This macro clear QEI specified interrupt flag. + * \hideinitializer + */ +#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel)) + +/** + * @brief Set QEI counter compare value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter compare value. + * \hideinitializer + */ +#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value)) + +/** + * @brief Set QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter value. + * \hideinitializer + */ +#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value)) + +/** + * @brief Enable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro enable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type)) + +/** + * @brief Disable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro disable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type)) + +/** + * @brief Set QEI maximum count value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter maximum value. + * @return QEI maximum count value + * @details This macro set QEI maximum count value. + * \hideinitializer + */ +#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value)) + +/** + * @brief Set QEI counting mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @return None + * @details This macro set QEI counting mode. + * \hideinitializer + */ +#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode)) + + +void QEI_Close(QEI_T* qei); +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value); +void QEI_Start(QEI_T* qei); +void QEI_Stop(QEI_T* qei); + + +/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __QEI_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/qspi.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/qspi.h new file mode 100644 index 00000000000..ec8a91789d5 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/qspi.h @@ -0,0 +1,356 @@ +/**************************************************************************//** + * @file qspi.h + * @version V3.00 + * @brief M480 series QSPI driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __QSPI_H__ +#define __QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants + @{ +*/ + +#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define QSPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ + +#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define QSPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ + +/* QSPI Interrupt Mask */ +#define QSPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ +#define QSPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define QSPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define QSPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ +#define QSPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define QSPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define QSPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* QSPI Status Mask */ +#define QSPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ +#define QSPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ +#define QSPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ +#define QSPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ +#define QSPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ +#define QSPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ +#define QSPI_QSPIEN_STS_MASK (0x40U) /*!< QSPIEN status mask \hideinitializer */ +#define QSPI_SSLINE_STS_MASK (0x80U) /*!< QSPIx_SS line status mask \hideinitializer */ + +/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. + * \hideinitializer + */ +#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk) + +/** + * @brief Trigger RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] qspi The pointer of the specified QSPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos) + +/** + * @brief Get the datum read from RX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Data in RX register. + * @details Read QSPI_RX register to get the received datum. + * \hideinitializer + */ +#define QSPI_READ_RX(qspi) ((qspi)->RX) + +/** + * @brief Write datum to TX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. + * @return None. + * @details Write u32TxData to QSPI_TX register. + * \hideinitializer + */ +#define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData)) + +/** + * @brief Set QSPIx_SS pin to high state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. + * \hideinitializer + */ +#define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk)) + +/** + * @brief Set QSPIx_SS pin to low state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. + * \hideinitializer + */ +#define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk) + +/** + * @brief Enable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). + * \hideinitializer + */ +#define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). + * \hideinitializer + */ +#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos)) + +/** + * @brief Set the QSPI transfer sequence with LSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. + * \hideinitializer + */ +#define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk) + +/** + * @brief Set the QSPI transfer sequence with MSB first. + * @param[in] qspi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. + * \hideinitializer + */ +#define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk) + +/** + * @brief Set the data width of a QSPI transaction. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos)) + +/** + * @brief Get the QSPI busy state. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 QSPI controller is not busy. + * @retval 1 QSPI controller is busy. + * @details This macro will return the busy state of QSPI controller. + * \hideinitializer + */ +#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set QSPIEN (QSPI_CTL[0]) to enable QSPI controller. + * \hideinitializer + */ +#define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk) + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear QSPIEN (QSPI_CTL[0]) to disable QSPI controller. + * \hideinitializer + */ +#define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk) + +/** + * @brief Disable QSPI Dual IO function. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual IO function and set QSPI Dual IO direction to input. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual IO function and set QSPI Dual IO direction to output. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Disable QSPI Dual IO function. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Quad IO direction to input. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Quad IO direction to output. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk ) + + + + +/* Function prototype declaration */ +uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void QSPI_Close(QSPI_T *qspi); +void QSPI_ClearRxFIFO(QSPI_T *qspi); +void QSPI_ClearTxFIFO(QSPI_T *qspi); +void QSPI_DisableAutoSS(QSPI_T *qspi); +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock); +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t QSPI_GetBusClock(QSPI_T *qspi); +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask); + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/rtc.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/rtc.h new file mode 100644 index 00000000000..c58255839a2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/rtc.h @@ -0,0 +1,336 @@ +/**************************************************************************//** + * @file rtc.h + * @version V3.00 + * @brief M480 series RTC driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Initial Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */ +#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Time Attribute Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */ +#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */ +#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */ +#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tick Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */ +#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */ +#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */ +#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */ +#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */ +#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */ +#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */ +#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Day of Week Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */ +#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */ +#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */ +#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */ +#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */ +#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */ +#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_WAIT_COUNT 0xFFFFFFFFUL /*!< Initial Time-out Value \hideinitializer */ +#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */ +#define RTC_FCR_REFERENCE 32761UL /*!< RTC Reference for frequency compensation \hideinitializer */ + + +#define RTC_TAMPER0_SELECT (0x1ul << 0) /*!< Select Tamper 0 \hideinitializer */ +#define RTC_TAMPER1_SELECT (0x1ul << 1) /*!< Select Tamper 1 \hideinitializer */ +#define RTC_TAMPER2_SELECT (0x1ul << 2) /*!< Select Tamper 2 \hideinitializer */ +#define RTC_TAMPER3_SELECT (0x1ul << 3) /*!< Select Tamper 3 \hideinitializer */ +#define RTC_TAMPER4_SELECT (0x1ul << 4) /*!< Select Tamper 4 \hideinitializer */ +#define RTC_TAMPER5_SELECT (0x1ul << 5) /*!< Select Tamper 5 \hideinitializer */ +#define MAX_TAMPER_PIN_NUM 6ul /*!< Tamper Pin number \hideinitializer */ + +#define RTC_TAMPER_HIGH_LEVEL_DETECT 1ul /*!< Tamper pin detect voltage level is high \hideinitializer */ +#define RTC_TAMPER_LOW_LEVEL_DETECT 0ul /*!< Tamper pin detect voltage level is low \hideinitializer */ + +#define RTC_TAMPER_DEBOUNCE_ENABLE 1ul /*!< Enable RTC tamper pin de-bounce function \hideinitializer */ +#define RTC_TAMPER_DEBOUNCE_DISABLE 0ul /*!< Disable RTC tamper pin de-bounce function \hideinitializer */ + +#define RTC_PAIR0_SELECT (0x1ul << 0) /*!< Select Pair 0 \hideinitializer */ +#define RTC_PAIR1_SELECT (0x1ul << 1) /*!< Select Pair 1 \hideinitializer */ +#define RTC_PAIR2_SELECT (0x1ul << 2) /*!< Select Pair 2 \hideinitializer */ +#define MAX_PAIR_NUM 3ul /*!< Pair number \hideinitializer */ + +#define RTC_2POW10_CLK (0x0 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */ +#define RTC_2POW11_CLK (0x1 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */ +#define RTC_2POW12_CLK (0x2 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */ +#define RTC_2POW13_CLK (0x3 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */ +#define RTC_2POW14_CLK (0x4 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */ +#define RTC_2POW15_CLK (0x5 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */ +#define RTC_2POW16_CLK (0x6 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */ +#define RTC_2POW17_CLK (0x7 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */ + +#define REF_RANDOM_PATTERN 0x0 /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */ +#define REF_PREVIOUS_PATTERN 0x1 /*!< The new reference pattern is repeated previous random value when the reference pattern run out \hideinitializer */ +#define REF_SEED 0x3 /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */ + +/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ +/** + * @details RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */ + + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Indicate is Leap Year or not + * + * @param None + * + * @retval 0 This year is not a leap year + * @retval 1 This year is a leap year + * + * @details According to current date, return this year is leap year or not. + * \hideinitializer + */ +#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0) + +/** + * @brief Clear RTC Alarm Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC alarm interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk) + +/** + * @brief Clear RTC Tick Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC tick interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk) + +/** + * @brief Clear RTC Tamper Interrupt Flag + * + * @param u32TamperFlag Tamper interrupt flag. It consists of: \n + * - \ref RTC_INTSTS_TAMP0IF_Msk \n + * - \ref RTC_INTSTS_TAMP1IF_Msk \n + * - \ref RTC_INTSTS_TAMP2IF_Msk \n + * - \ref RTC_INTSTS_TAMP3IF_Msk \n + * - \ref RTC_INTSTS_TAMP4IF_Msk \n + * - \ref RTC_INTSTS_TAMP5IF_Msk + * + * @return None + * + * @details This macro is used to clear RTC snooper pin interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TAMPER_INT_FLAG(u32TamperFlag) (RTC->INTSTS = (u32TamperFlag)) + +/** + * @brief Get RTC Alarm Interrupt Flag + * + * @param None + * + * @retval 0 RTC alarm interrupt did not occur + * @retval 1 RTC alarm interrupt occurred + * + * @details This macro indicates RTC alarm interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0) + +/** + * @brief Get RTC Time Tick Interrupt Flag + * + * @param None + * + * @retval 0 RTC time tick interrupt did not occur + * @retval 1 RTC time tick interrupt occurred + * + * @details This macro indicates RTC time tick interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Flag + * + * @param None + * + * @retval 0 RTC snooper pin interrupt did not occur + * @retval 1 RTC snooper pin interrupt occurred + * + * @details This macro indicates RTC snooper pin interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_FLAG() ((RTC->INTSTS & (0x3F00))? 1:0) + +/** + * @brief Get RTC TAMPER Interrupt Status + * + * @param None + * + * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated + * @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated + * @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated + * @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated + * @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated + * @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated + * + * @details This macro indicates RTC snooper pin interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_STATUS() ((RTC->INTSTS & (0x3F00))) + +/** + * @brief Read Spare Register + * + * @param[in] u32RegNum The spare register number, 0~19. + * + * @return Spare register content + * + * @details Read the specify spare register content. + * @note The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n + * And its controlled by RTC Access Enable Register. + * \hideinitializer + */ +#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)]) + +/** + * @brief Write Spare Register + * + * @param[in] u32RegNum The spare register number, 0~19. + * @param[in] u32RegValue The spare register value. + * + * @return None + * + * @details Write specify data to spare register. + * @note This macro is effect only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n + * And its controlled by RTC Access Enable Register(RTC_RWEN). + * \hideinitializer + */ +#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void RTC_WaitAccessEnable(void); + +/** + * @brief Wait RTC Access Enable + * + * @param None + * + * @return None + * + * @details This function is used to enable the maximum RTC read/write accessible time. + */ +__STATIC_INLINE void RTC_WaitAccessEnable(void) +{ + while((RTC->RWEN & RTC_RWEN_RTCBUSY_Msk) == RTC_RWEN_RTCBUSY_Msk) + { + } + + /* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */ + RTC->RWEN = RTC_WRITE_KEY; + + /* To wait RWENF bit is set and user can access the protected-register of RTC from now on */ + while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == (uint32_t)0x0) + { + } +} + +void RTC_Open(S_RTC_TIME_DATA_T *sPt); +void RTC_Close(void); +void RTC_32KCalibration(int32_t i32FrequencyX10000); +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +uint32_t RTC_GetDayOfWeek(void); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); +void RTC_EnableSpareAccess(void); +void RTC_DisableSpareRegister(void); +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn); +void RTC_StaticTamperDisable(uint32_t u32TamperSelect); +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source); +void RTC_DynamicTamperDisable(uint32_t u32PairSel); +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed); + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/sc.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/sc.h new file mode 100644 index 00000000000..18d6861947e --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/sc.h @@ -0,0 +1,267 @@ +/**************************************************************************//** + * @file sc.h + * @version V1.00 + * @brief M480 Smartcard (SC) driver header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_H__ +#define __SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM 3 /*!< Smartcard interface numbers \hideinitializer */ +#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high \hideinitializer */ +#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low \hideinitializer */ +#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status \hideinitializer */ +#define SC_CLK_ON 1 /*!< Smartcard clock on \hideinitializer */ +#define SC_CLK_OFF 0 /*!< Smartcard clock off \hideinitializer */ + +#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask)) + +/** + * @brief This macro disable smartcard interrupt + * @param[in] sc Base address of smartcard module + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTEN_ACERRIEN_Msk + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_INITIEN_Msk + * - \ref SC_INTEN_CDIEN_Msk + * - \ref SC_INTEN_BGTIEN_Msk + * - \ref SC_INTEN_TMR2IEN_Msk + * - \ref SC_INTEN_TMR1IEN_Msk + * - \ref SC_INTEN_TMR0IEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief This macro set VCC pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_VCC_PIN(sc, u32State) \ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\ + }while(0) + + +/** + * @brief This macro turns CLK output on or off + * @param[in] sc Base address of smartcard module + * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF + * @return None + * \hideinitializer + */ +#define SC_SET_CLK_PIN(sc, u32OnOff)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32OnOff)\ + (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\ + else\ + (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\ + }while(0) + +/** + * @brief This macro set I/O pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_IO_PIN(sc, u32State)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\ + }while(0) + +/** + * @brief This macro set RST pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_RST_PIN(sc, u32State)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\ + }while(0) + +/** + * @brief This macro read one byte from smartcard module receive FIFO + * @param[in] sc Base address of smartcard module + * @return One byte read from receive FIFO + * \hideinitializer + */ +#define SC_READ(sc) ((char)((sc)->DAT)) + +/** + * @brief This macro write one byte to smartcard module transmit FIFO + * @param[in] sc Base address of smartcard module + * @param[in] u8Data Data to write to transmit FIFO + * @return None + * \hideinitializer + */ +#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief This macro set smartcard stop bit length + * @param[in] sc Base address of smartcard module + * @param[in] u32Len Stop bit length, ether 1 or 2. + * @return None + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1 ? SC_CTL_NSB_Msk : 0)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count); +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count); + +/** + * @brief Enable/Disable Tx error retry, and set Tx error retry count + * @param[in] sc Base address of smartcard module + * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry + * @return None + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count) +{ + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk; + } +} + +/** + * @brief Enable/Disable Rx error retry, and set Rx error retry count + * @param[in] sc Base address of smartcard module + * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry + * @return None + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count) +{ + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk; + } + +} + + +uint32_t SC_IsCardInserted(SC_T *sc); +void SC_ClearFIFO(SC_T *sc); +void SC_Close(SC_T *sc); +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *sc); +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *sc); +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum); +uint32_t SC_GetInterfaceClock(SC_T *sc); + + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SC_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/scuart.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/scuart.h new file mode 100644 index 00000000000..40fe3330d04 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/scuart.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file scuart.h + * @version V1.00 + * @brief M480 Smartcard UART mode (SCUART) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCUART_H__ +#define __SCUART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants + @{ +*/ +#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */ +#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */ +#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */ +#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */ + +#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */ +#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */ +#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */ + +#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */ +#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */ + + +/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/* TX Macros */ +/** + * @brief Write Data to Tx data register + * @param[in] sc The base address of smartcard module. + * @param[in] u8Data Data byte to transmit + * @return None + * \hideinitializer + */ +#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief Get TX FIFO empty flag status from register + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk) + +/** + * @brief Get TX FIFO full flag status from register + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk) + +/** + * @brief Wait specified smartcard port transmission complete + * @param[in] sc The base address of smartcard module + * @return None + * @note This Macro blocks until transmit complete. + * \hideinitializer + */ +#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk) + +/** + * @brief Check specified smartcard port transmit FIFO is full or not + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval 1 Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port transmission is over + * @param[in] sc The base address of smartcard module + * @return Transmit complete status + * @retval 0 Transmit is not complete + * @retval 1 Transmit complete + * \hideinitializer + */ +#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1) + +/** + * @brief Check specified Smartcard port Transmission Status + * @param[in] sc The pointer of smartcard module. + * @retval 0 Transmit is completed + * @retval 1 Transmit is active + * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted. + * \hideinitializer + */ +#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0) + +/* RX Macros */ + +/** + * @brief Read Rx data register + * @param[in] sc The base address of smartcard module + * @return The oldest data byte in RX FIFO + * \hideinitializer + */ +#define SCUART_READ(sc) ((sc)->DAT) + +/** + * @brief Get RX FIFO empty flag status from register + * @param[in] sc The base address of smartcard module + * @return Receive FIFO empty status + * @retval 0 Receive FIFO is not empty + * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk) + + +/** + * @brief Get RX FIFO full flag status from register + * @param[in] sc The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full + * \hideinitializer + */ +#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk) + +/** + * @brief Check if receive data number in FIFO reach FIFO trigger level or not + * @param[in] sc The base address of smartcard module + * @return Receive FIFO data status + * @retval 0 The number of bytes in receive FIFO is less than trigger level + * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level + * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO + * \hideinitializer + */ +#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port receive FIFO is full or not + * @param[in] sc The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval 1 Receive FIFO is full + * \hideinitializer + */ +#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0) + +/* Interrupt Macros */ + +/** + * @brief Enable specified interrupts + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Interrupt masks to enable, a combination of following bits + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask)) + +/** + * @brief Disable specified interrupts + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Interrupt masks to disable, a combination of following bits + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief Get specified interrupt flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to check, could be one of following value + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * @return The status of specified interrupt + * @retval 0 Specified interrupt does not happened + * @retval 1 Specified interrupt happened + * \hideinitializer + */ +#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & (u32Type) ? 1 : 0) + +/** + * @brief Clear specified interrupt flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type)) + +/** + * @brief Get receive error flag/status + * @param[in] sc The base address of smartcard module + * @return Current receive error status, could one of following errors: + * @retval SC_STATUS_PEF_Msk Parity error + * @retval SC_STATUS_FEF_Msk Frame error + * @retval SC_STATUS_BEF_Msk Break error + * \hideinitializer + */ +#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)) + +/** + * @brief Clear specified receive error flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Receive error flag/status to clear, combination following values + * - \ref SC_STATUS_PEF_Msk + * - \ref SC_STATUS_FEF_Msk + * - \ref SC_STATUS_BEF_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask)) + +void SCUART_Close(SC_T* sc); +uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate); +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC); +void SCUART_Write(SC_T* sc,uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCUART_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/sdh.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/sdh.h new file mode 100644 index 00000000000..2b53fd369c5 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/sdh.h @@ -0,0 +1,200 @@ +/**************************************************************************//** + * @file sdh.h + * @version V1.00 + * @brief M480 SDH driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include + +#ifndef __SDH_H__ +#define __SDH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + + +/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants + @{ +*/ + +#define SDH_ERR_ID 0xFFFF0100ul /*!< SDH error ID \hideinitializer */ + +#define SDH_TIMEOUT (SDH_ERR_ID|0x01ul) /*!< Timeout \hideinitializer */ +#define SDH_NO_MEMORY (SDH_ERR_ID|0x02ul) /*!< OOM \hideinitializer */ + +/*-- function return value */ +#define Successful 0ul /*!< Success \hideinitializer */ +#define Fail 1ul /*!< Failed \hideinitializer */ + +/*--- define type of SD card or MMC */ +#define SDH_TYPE_UNKNOWN 0ul /*!< Unknown card type \hideinitializer */ +#define SDH_TYPE_SD_HIGH 1ul /*!< SDHC card \hideinitializer */ +#define SDH_TYPE_SD_LOW 2ul /*!< SD card \hideinitializer */ +#define SDH_TYPE_MMC 3ul /*!< MMC card \hideinitializer */ +#define SDH_TYPE_EMMC 4ul /*!< eMMC card \hideinitializer */ + +/* SD error */ +#define SDH_NO_SD_CARD (SDH_ERR_ID|0x10ul) /*!< Card removed \hideinitializer */ +#define SDH_ERR_DEVICE (SDH_ERR_ID|0x11ul) /*!< Device error \hideinitializer */ +#define SDH_INIT_TIMEOUT (SDH_ERR_ID|0x12ul) /*!< Card init timeout \hideinitializer */ +#define SDH_SELECT_ERROR (SDH_ERR_ID|0x13ul) /*!< Card select error \hideinitializer */ +#define SDH_WRITE_PROTECT (SDH_ERR_ID|0x14ul) /*!< Card write protect \hideinitializer */ +#define SDH_INIT_ERROR (SDH_ERR_ID|0x15ul) /*!< Card init error \hideinitializer */ +#define SDH_CRC7_ERROR (SDH_ERR_ID|0x16ul) /*!< CRC 7 error \hideinitializer */ +#define SDH_CRC16_ERROR (SDH_ERR_ID|0x17ul) /*!< CRC 16 error \hideinitializer */ +#define SDH_CRC_ERROR (SDH_ERR_ID|0x18ul) /*!< CRC error \hideinitializer */ +#define SDH_CMD8_ERROR (SDH_ERR_ID|0x19ul) /*!< Command 8 error \hideinitializer */ + +#define MMC_FREQ 20000ul /*!< output 20MHz to MMC \hideinitializer */ +#define SD_FREQ 25000ul /*!< output 25MHz to SD \hideinitializer */ +#define SDHC_FREQ 50000ul /*!< output 50MHz to SDH \hideinitializer */ + +#define SD_PORT0 (1 << 0) /*!< Card select SD0 \hideinitializer */ +#define SD_PORT1 (1 << 2) /*!< Card select SD1 \hideinitializer */ +#define CardDetect_From_GPIO (1ul << 8) /*!< Card detection pin is GPIO \hideinitializer */ +#define CardDetect_From_DAT3 (1ul << 9) /*!< Card detection pin is DAT3 \hideinitializer */ + +/*@}*/ /* end of group SDH_EXPORTED_CONSTANTS */ + +/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines + @{ +*/ +typedef struct SDH_info_t +{ + unsigned int CardType; /*!< SDHC, SD, or MMC */ + unsigned int RCA; /*!< Relative card address */ + unsigned char IsCardInsert; /*!< Card insert state */ + unsigned int totalSectorN; /*!< Total sector number */ + unsigned int diskSize; /*!< Disk size in K bytes */ + int sectorSize; /*!< Sector size in bytes */ +} SDH_INFO_T; /*!< Structure holds SD card info */ + +/*@}*/ /* end of group SDH_EXPORTED_TYPEDEF */ + +/** @cond HIDDEN_SYMBOLS */ +extern uint8_t g_u8R3Flag; +extern uint8_t volatile g_u8SDDataReadyFlag; +extern SDH_INFO_T SD0, SD1; +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ + +/** + * @brief Enable specified interrupt. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_CDSRC_Msk \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / + * \ref SDH_INTEN_WKIEN_Msk + * + * @return None. + * \hideinitializer + */ +#define SDH_ENABLE_INT(sdh, u32IntMask) ((sdh)->INTEN |= (u32IntMask)) + +/** + * @brief Disable specified interrupt. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk / + * + * @return None. + * \hideinitializer + */ +#define SDH_DISABLE_INT(sdh, u32IntMask) ((sdh)->INTEN &= ~(u32IntMask)) + +/** + * @brief Get specified interrupt flag/status. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk / + * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk / + * \ref SDH_INTSTS_CDIF_Msk \ref SDH_INTSTS_RTOIF_Msk / + * \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk / + * \ref SDH_INTSTS_DAT1STS_Msk + * + * + * @return 0 = The specified interrupt is not happened. + * 1 = The specified interrupt is happened. + * \hideinitializer + */ +#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0) + + +/** + * @brief Clear specified interrupt flag/status. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk / + * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk + * + * + * @return None. + * \hideinitializer + */ +#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask)) + + +/** + * @brief Check SD Card inserted or removed. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return 1: Card inserted. + * 0: Card removed. + * \hideinitializer + */ +#define SDH_IS_CARD_PRESENT(sdh) (((sdh) == SDH0)? SD0.IsCardInsert : SD1.IsCardInsert) + +/** + * @brief Get SD Card capacity. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return SD Card capacity. (unit: KByte) + * \hideinitializer + */ +#define SDH_GET_CARD_CAPACITY(sdh) (((sdh) == SDH0)? SD0.diskSize : SD1.diskSize) + + +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc); +uint32_t SDH_Probe(SDH_T *sdh); +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); + +uint32_t SDH_CardDetection(SDH_T *sdh); +void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc); +void SDH_Close_Disk(SDH_T *sdh); + + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SDH_H__ */ +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/spi.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/spi.h new file mode 100644 index 00000000000..57c23968f3b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/spi.h @@ -0,0 +1,594 @@ +/**************************************************************************//** + * @file spi.h + * @version V3.00 + * @brief M480 series SPI driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define SPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ + +#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define SPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ + +/* SPI Interrupt Mask */ +#define SPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ +#define SPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define SPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define SPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ +#define SPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define SPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define SPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* SPI Status Mask */ +#define SPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ +#define SPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ +#define SPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ +#define SPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ +#define SPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ +#define SPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ +#define SPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */ +#define SPI_SSLINE_STS_MASK (0x80U) /*!< SPIx_SS line status mask \hideinitializer */ + + +/* I2S Data Width */ +#define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* I2S Audio Format */ +#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */ +#define SPII2S_STEREO (0U) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define SPII2S_FORMAT_I2S (0U<STATUS = SPI_STATUS_UNITIF_Msk) + +/** + * @brief Trigger RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi The pointer of the specified SPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos) + +/** + * @brief Get the datum read from RX register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX register. + * @details Read SPI_RX register to get the received datum. + * \hideinitializer + */ +#define SPI_READ_RX(spi) ((spi)->RX) + +/** + * @brief Write datum to TX register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to SPI_TX register. + * \hideinitializer + */ +#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData)) + +/** + * @brief Set SPIx_SS pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to high state. + * \hideinitializer + */ +#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) + +/** + * @brief Set SPIx_SS pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to low state. + * \hideinitializer + */ +#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk) + +/** + * @brief Enable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]). + * \hideinitializer + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle). + * \hideinitializer + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos)) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first. + * \hideinitializer + */ +#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first. + * \hideinitializer + */ +#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos)) + +/** + * @brief Get the SPI busy state. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 SPI controller is not busy. + * @retval 1 SPI controller is busy. + * @details This macro will return the busy state of SPI controller. + * \hideinitializer + */ +#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller. + * \hideinitializer + */ +#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk) + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller. + * \hideinitializer + */ +#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch); + +/** + * @brief Enable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Disable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Enable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Disable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Enable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Disable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Enable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Disable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Clear TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk ) + +/** + * @brief Clear RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref SPII2S_MONO_LEFT + * - \ref SPII2S_MONO_RIGHT + * @return None + * @details This function selects the recording source channel of monaural mode. + * \hideinitializer + */ +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch) +{ + u32Ch == SPII2S_MONO_LEFT ? + (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) : + (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk); +} + +/** + * @brief Write data to I2S TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Data The value written to TX FIFO. + * @return None + * @details This macro will write a value to TX FIFO. + * \hideinitializer + */ +#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) ) + +/** + * @brief Read RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return The value read from RX FIFO. + * @details This function will return a value read from RX FIFO. + * \hideinitializer + */ +#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX ) + +/** + * @brief Get the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return The interrupt flags specified by the u32mask parameter. + * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter. + * \hideinitializer + */ +#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) ) + +/** + * @brief Clear the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return None + * @details This macro will clear the interrupt flags specified by the u32mask parameter. + * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself. + * \hideinitializer + */ +#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return TX FIFO level + * @details This macro will return the number of available words in TX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return RX FIFO level + * @details This macro will return the number of available words in RX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos ) + + + +/* Function prototype declaration */ +uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void SPI_Close(SPI_T *spi); +void SPI_ClearRxFIFO(SPI_T *spi); +void SPI_ClearTxFIFO(SPI_T *spi); +void SPI_DisableAutoSS(SPI_T *spi); +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock); +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t SPI_GetBusClock(SPI_T *spi); +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask); +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask); + +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat); +void SPII2S_Close(SPI_T *i2s); +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask); +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask); +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock); +void SPII2S_DisableMCLK(SPI_T *i2s); +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); + + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/spim.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/spim.h new file mode 100644 index 00000000000..62da94c0502 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/spim.h @@ -0,0 +1,631 @@ +/**************************************************************************//** + * @file spim.h + * @version V1.00 + * @brief M480 series SPIM driver header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SPIM_H__ +#define __SPIM_H__ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Include related headers */ +/*---------------------------------------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPIM_Driver SPIM Driver + @{ +*/ + + +/** @addtogroup SPIM_EXPORTED_CONSTANTS SPIM Exported Constants + @{ +*/ + +#define SPIM_DMM_MAP_ADDR 0x8000000UL /*!< DMM mode memory map base address \hideinitializer */ +#define SPIM_DMM_SIZE 0x2000000UL /*!< DMM mode memory mapping size \hideinitializer */ +#define SPIM_CCM_ADDR 0x20020000UL /*!< CCM mode memory map base address \hideinitializer */ +#define SPIM_CCM_SIZE 0x8000UL /*!< CCM mode memory size \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPIM_CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SPIM_CTL0_RW_IN(x) ((x) ? 0UL : (0x1UL << SPIM_CTL0_QDIODIR_Pos)) /*!< SPIM_CTL0: SPI Interface Direction Select \hideinitializer */ +#define SPIM_CTL0_BITMODE_SING (0UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: One bit mode (SPI Interface including DO, DI, HOLD, WP) \hideinitializer */ +#define SPIM_CTL0_BITMODE_DUAL (1UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Two bits mode (SPI Interface including D0, D1, HOLD, WP) \hideinitializer */ +#define SPIM_CTL0_BITMODE_QUAD (2UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Four bits mode (SPI Interface including D0, D1, D2, D3) \hideinitializer */ +#define SPIM_CTL0_OPMODE_IO (0UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: I/O Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_PAGEWRITE (1UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Write Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_PAGEREAD (2UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Read Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_DIRECTMAP (3UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Direct Map Mode \hideinitializer */ + +#define CMD_NORMAL_PAGE_PROGRAM (0x02UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ +#define CMD_NORMAL_PAGE_PROGRAM_4B (0x12UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_WINBOND (0x32UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for Winbond) (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_MXIC (0x38UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for MXIC) (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_EON (0x40UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page Program (for EON) (Page Write Mode Use) \hideinitializer */ + +#define CMD_DMA_NORMAL_READ (0x03UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Read Data (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ (0x0BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_NORMAL_DUAL_READ (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ_DUAL_OUTPUT (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ_QUAD_OUTPUT (0x6BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_DUAL_READ (0xBBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_NORMAL_QUAD_READ (0xE7UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_QUAD_READ (0xEBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ + +/** @cond HIDDEN_SYMBOLS */ + +typedef enum +{ + MFGID_UNKNOW = 0x00U, + MFGID_SPANSION = 0x01U, + MFGID_EON = 0x1CU, + MFGID_ISSI = 0x7FU, + MFGID_MXIC = 0xC2U, + MFGID_WINBOND = 0xEFU +} +E_MFGID; + +/* Flash opcodes. */ +#define OPCODE_WREN 0x06U /* Write enable */ +#define OPCODE_RDSR 0x05U /* Read status register #1*/ +#define OPCODE_WRSR 0x01U /* Write status register #1 */ +#define OPCODE_RDSR2 0x35U /* Read status register #2*/ +#define OPCODE_WRSR2 0x31U /* Write status register #2 */ +#define OPCODE_RDSR3 0x15U /* Read status register #3*/ +#define OPCODE_WRSR3 0x11U /* Write status register #3 */ +#define OPCODE_PP 0x02U /* Page program (up to 256 bytes) */ +#define OPCODE_SE_4K 0x20U /* Erase 4KB sector */ +#define OPCODE_BE_32K 0x52U /* Erase 32KB block */ +#define OPCODE_CHIP_ERASE 0xc7U /* Erase whole flash chip */ +#define OPCODE_BE_64K 0xd8U /* Erase 64KB block */ +#define OPCODE_READ_ID 0x90U /* Read ID */ +#define OPCODE_RDID 0x9fU /* Read JEDEC ID */ +#define OPCODE_BRRD 0x16U /* SPANSION flash - Bank Register Read command */ +#define OPCODE_BRWR 0x17U /* SPANSION flash - Bank Register write command */ +#define OPCODE_NORM_READ 0x03U /* Read data bytes */ +#define OPCODE_FAST_READ 0x0bU /* Read data bytes */ +#define OPCODE_FAST_DUAL_READ 0x3bU /* Read data bytes */ +#define OPCODE_FAST_QUAD_READ 0x6bU /* Read data bytes */ + +/* Used for SST flashes only. */ +#define OPCODE_BP 0x02U /* Byte program */ +#define OPCODE_WRDI 0x04U /* Write disable */ +#define OPCODE_AAI_WP 0xadU /* Auto u32Address increment word program */ + +/* Used for Macronix flashes only. */ +#define OPCODE_EN4B 0xb7U /* Enter 4-byte mode */ +#define OPCODE_EX4B 0xe9U /* Exit 4-byte mode */ + +#define OPCODE_RDSCUR 0x2bU +#define OPCODE_WRSCUR 0x2fU + +#define OPCODE_RSTEN 0x66U +#define OPCODE_RST 0x99U + +#define OPCODE_ENQPI 0x38U +#define OPCODE_EXQPI 0xFFU + +/* Status Register bits. */ +#define SR_WIP 0x1U /* Write in progress */ +#define SR_WEL 0x2U /* Write enable latch */ +#define SR_QE 0x40U /* Quad Enable for MXIC */ +/* Status Register #2 bits. */ +#define SR2_QE 0x2U /* Quad Enable for Winbond */ +/* meaning of other SR_* bits may differ between vendors */ +#define SR_BP0 0x4U /* Block protect 0 */ +#define SR_BP1 0x8U /* Block protect 1 */ +#define SR_BP2 0x10U /* Block protect 2 */ +#define SR_SRWD 0x80U /* SR write protect */ +#define SR3_ADR 0x01U /* 4-byte u32Address mode */ + +#define SCUR_4BYTE 0x04U /* 4-byte u32Address mode */ + +/** @endcond HIDDEN_SYMBOLS */ + +/*@}*/ /* end of group SPIM_EXPORTED_CONSTANTS */ + + +/** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/** + * @details Enable cipher. + * \hideinitializer + */ +#define SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk) + +/** + * @details Disable cipher. + * \hideinitializer + */ +#define SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk) + +/** + * @details Enable cipher balance + * \hideinitializer + */ +#define SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk) + +/** + * @details Disable cipher balance + * \hideinitializer + */ +#define SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk) + +/** + * @details Set 4-byte address to be enabled/disabled. + * \hideinitializer + */ +#define SPIM_SET_4BYTE_ADDR_EN(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \ + } while (0) + +/** + * @details Enable SPIM interrupt + * \hideinitializer + */ +#define SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk) + +/** + * @details Disable SPIM interrupt + * \hideinitializer + */ +#define SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk) + +/** + * @details Is interrupt flag on. + * \hideinitializer + */ +#define SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL) + +/** + * @details Clear interrupt flag. + * \hideinitializer + */ +#define SPIM_CLR_INT() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos); \ + } while (0) + +/** + * @details Set transmit/receive bit length + * \hideinitializer + */ +#define SPIM_SET_DATA_WIDTH(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos); \ + } while (0) + +/** + * @details Get data transmit/receive bit length setting + * \hideinitializer + */ +#define SPIM_GET_DATA_WIDTH() \ + (((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U) + +/** + * @details Set data transmit/receive burst number + * \hideinitializer + */ +#define SPIM_SET_DATA_NUM(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos); \ + } while (0) + +/** + * @details Get data transmit/receive burst number + * \hideinitializer + */ +#define SPIM_GET_DATA_NUM() \ + (((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U) + +/** + * @details Enable Single Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_SING_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1)); \ + } while (0) + +/** + * @details Enable Single Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_SING_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0)); \ + } while (0) + +/** + * @details Enable Dual Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_DUAL_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U)); \ + } while (0) + +/** + * @details Enable Dual Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_DUAL_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U)); \ + } while (0) + +/** + * @details Enable Quad Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_QUAD_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U)); \ + } while (0) + +/** + * @details Enable Quad Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_QUAD_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U)); \ + } while (0) + +/** + * @details Set suspend interval which ranges between 0 and 15. + * \hideinitializer + */ +#define SPIM_SET_SUSP_INTVL(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos); \ + } while (0) + +/** + * @details Get suspend interval setting + * \hideinitializer + */ +#define SPIM_GET_SUSP_INTVL() \ + ((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos) + +/** + * @details Set operation mode. + * \hideinitializer + */ +#define SPIM_SET_OPMODE(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \ + } while (0) + +/** + * @details Get operation mode. + * \hideinitializer + */ +#define SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk) + +/** + * @details Set SPIM mode. + * \hideinitializer + */ +#define SPIM_SET_SPIM_MODE(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x); \ + } while (0) + +/** + * @details Get SPIM mode. + * \hideinitializer + */ +#define SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk) + +/** + * @details Start operation. + * \hideinitializer + */ +#define SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk) + +/** + * @details Is engine busy. + * \hideinitializer + */ +#define SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) + +/** + * @details Wait for free. + * \hideinitializer + */ +#define SPIM_WAIT_FREE() \ + do { \ + while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) { } \ + } while (0) + +/** + * @details Enable cache. + * \hideinitializer + */ +#define SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk) + +/** + * @details Disable cache. + * \hideinitializer + */ +#define SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk) + +/** + * @details Is cache enabled. + * \hideinitializer + */ +#define SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1) + +/** + * @details Enable CCM + * \hideinitializer + */ +#define SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk) + +/** + * @details Disable CCM. + * \hideinitializer + */ +#define SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk) + +/** + * @details Is CCM enabled. + * \hideinitializer + */ +#define SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos) + +/** + * @details Invalidate cache. + * \hideinitializer + */ +#define SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk) + +/** + * @details Set SS(Select Active) to active level. + * \hideinitializer + */ +#define SPIM_SET_SS_EN(x) \ + do { \ + (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \ + } while (0) + +/** + * @details Is SS(Select Active) in active level. + * \hideinitializer + */ +#define SPIM_GET_SS_EN() \ + (!(SPIM->CTL1 & SPIM_CTL1_SS_Msk)) + +/** + * @details Set active level of slave select to be high/low. + * \hideinitializer + */ +#define SPIM_SET_SS_ACTLVL(x) \ + do { \ + (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos)); \ + } while (0) + +/** + * @details Set idle time interval + * \hideinitializer + */ +#define SPIM_SET_IDL_INTVL(x) \ + do { \ + SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos); \ + } while (0) + +/** + * @details Get idle time interval setting + * \hideinitializer + */ +#define SPIM_GET_IDL_INTVL() \ + ((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos) + +/** + * @details Set SPIM clock divider + * \hideinitializer + */ +#define SPIM_SET_CLOCK_DIVIDER(x) \ + do { \ + SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos); \ + } while (0) + +/** + * @details Get SPIM current clock divider setting + * \hideinitializer + */ +#define SPIM_GET_CLOCK_DIVIDER() \ + ((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos) + +/** + * @details Set SPI flash deselect time interval of DMA write mode + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_DWDELSEL(x) \ + do { \ + (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) | ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \ + } while (0) + +/** + * @details Get SPI flash deselect time interval of DMA write mode + * \hideinitializer + */ +#define SPIM_GET_RXCLKDLY_DWDELSEL() \ + ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos) + +/** + * @details Set sampling clock delay selection for received data + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \ + do { \ + (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) | ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \ + } while (0) + +/** + * @details Get sampling clock delay selection for received data + * \hideinitializer + */ +#define SPIM_GET_RXCLKDLY_RDDLYSEL() \ + ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos) + +/** + * @details Set sampling clock edge selection for received data + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_RDEDGE() \ + (SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \ + +/** + * @details Get sampling clock edge selection for received data + * \hideinitializer + */ +#define SPIM_CLR_RXCLKDLY_RDEDGE() \ + (SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk) + +/** + * @details Set mode bits data for continuous read mode + * \hideinitializer + */ +#define SPIM_SET_DMMCTL_CRMDAT(x) \ + do { \ + (SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) | ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \ + } while (0) + +/** + * @details Get mode bits data for continuous read mode + * \hideinitializer + */ +#define SPIM_GET_DMMCTL_CRMDAT() \ + ((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos) + +/** + * @details Set DMM mode SPI flash deselect time + * \hideinitializer + */ +#define SPIM_DMM_SET_DESELTIM(x) \ + do { \ + SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos); \ + } while (0) + +/** + * @details Get current DMM mode SPI flash deselect time setting + * \hideinitializer + */ +#define SPIM_DMM_GET_DESELTIM() \ + ((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos) + +/** + * @details Enable DMM mode burst wrap mode + * \hideinitializer + */ +#define SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk) + +/** + * @details Disable DMM mode burst wrap mode + * \hideinitializer + */ +#define SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk) + +/** + * @details Enable DMM mode continuous read mode + * \hideinitializer + */ +#define SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk) + +/** + * @details Disable DMM mode continuous read mode + * \hideinitializer + */ +#define SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk) + +/** + * @details Set DMM mode SPI flash active SCLK time + * \hideinitializer + */ +#define SPIM_DMM_SET_ACTSCLKT(x) \ + do { \ + SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk; \ + } while (0) + +/** + * @details Set SPI flash active SCLK time as SPIM default + * \hideinitializer + */ +#define SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk) + +/** + * @details Set dummy cycle number (Only for DMM mode and DMA mode) + * \hideinitializer + */ +#define SPIM_SET_DCNUM(x) \ + do { \ + SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk; \ + } while (0) + +/** + * @details Set dummy cycle number (Only for DMM mode and DMA mode) as SPIM default + * \hideinitializer + */ +#define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk) + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Function Prototypes */ +/*---------------------------------------------------------------------------------------------------------*/ + + +int SPIM_InitFlash(int clrWP); +uint32_t SPIM_GetSClkFreq(void); +void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit); +int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit); +int SPIM_Is4ByteModeEnable(uint32_t u32NBit); + +void SPIM_ChipErase(uint32_t u32NBit, int isSync); +void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync); + +void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat); +void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy); + +void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd); +void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync); + +void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl); +void SPIM_ExitDirectMapMode(void); + +void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit); + +/*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPIM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPIM_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/sys.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/sys.h new file mode 100644 index 00000000000..eadb0b86c85 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/sys.h @@ -0,0 +1,1500 @@ +/**************************************************************************//** + * @file SYS.h + * @version V3.0 + * @brief M480 Series SYS Driver Header File + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +#ifndef __SYS_H__ +#define __SYS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + +/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Module Reset Control Resister constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_RST ((0UL<<24) | SYS_IPRST0_PDMARST_Pos) /*!< Reset PDMA \hideinitializer*/ +#define EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) /*!< Reset EBI \hideinitializer*/ +#define EMAC_RST ((0UL<<24) | SYS_IPRST0_EMACRST_Pos) /*!< Reset EMAC \hideinitializer */ +#define SDH0_RST ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos) /*!< Reset SDH0 \hideinitializer */ +#define CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) /*!< Reset CRC \hideinitializer */ +#define HSUSBD_RST ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos) /*!< Reset HSUSBD \hideinitializer */ +#define CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) /*!< Reset CRPT \hideinitializer */ +#define SPIM_RST ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos) /*!< Reset SPIM \hideinitializer */ +#define USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos) /*!< Reset USBH \hideinitializer */ +#define SDH1_RST ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos) /*!< Reset SDH1 \hideinitializer */ + +#define GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) /*!< Reset GPIO \hideinitializer */ +#define TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) /*!< Reset TMR0 \hideinitializer */ +#define TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) /*!< Reset TMR1 \hideinitializer */ +#define TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) /*!< Reset TMR2 \hideinitializer */ +#define TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) /*!< Reset TMR3 \hideinitializer */ +#define ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) /*!< Reset ACMP01 \hideinitializer */ +#define I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) /*!< Reset I2C0 \hideinitializer */ +#define I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) /*!< Reset I2C1 \hideinitializer */ +#define I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) /*!< Reset I2C2 \hideinitializer */ +#define QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos) /*!< Reset QSPI0 \hideinitializer */ +#define SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) /*!< Reset SPI0 \hideinitializer */ +#define SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) /*!< Reset SPI1 \hideinitializer */ +#define SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) /*!< Reset SPI2 \hideinitializer */ +#define UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) /*!< Reset UART0 \hideinitializer */ +#define UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) /*!< Reset UART1 \hideinitializer */ +#define UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) /*!< Reset UART2 \hideinitializer */ +#define UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) /*!< Reset UART3 \hideinitializer */ +#define UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) /*!< Reset UART4 \hideinitializer */ +#define UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) /*!< Reset UART5 \hideinitializer */ +#define CAN0_RST ((4UL<<24) | SYS_IPRST1_CAN0RST_Pos) /*!< Reset CAN0 \hideinitializer */ +#define CAN1_RST ((4UL<<24) | SYS_IPRST1_CAN1RST_Pos) /*!< Reset CAN1 \hideinitializer */ +#define USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) /*!< Reset USBD \hideinitializer */ +#define EADC_RST ((4UL<<24) | SYS_IPRST1_EADCRST_Pos) /*!< Reset EADC \hideinitializer */ +#define I2S0_RST ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos) /*!< Reset I2S0 \hideinitializer */ + +#define SC0_RST ((8UL<<24) | SYS_IPRST2_SC0RST_Pos) /*!< Reset SC0 \hideinitializer */ +#define SC1_RST ((8UL<<24) | SYS_IPRST2_SC1RST_Pos) /*!< Reset SC1 \hideinitializer */ +#define SC2_RST ((8UL<<24) | SYS_IPRST2_SC2RST_Pos) /*!< Reset SC2 \hideinitializer */ +#define SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos) /*!< Reset SPI3 \hideinitializer */ +#define USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) /*!< Reset USCI0 \hideinitializer */ +#define USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos) /*!< Reset USCI1 \hideinitializer */ +#define DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) /*!< Reset DAC \hideinitializer */ +#define EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) /*!< Reset EPWM0 \hideinitializer */ +#define EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) /*!< Reset EPWM1 \hideinitializer */ +#define BPWM0_RST ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos) /*!< Reset BPWM0 \hideinitializer */ +#define BPWM1_RST ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos) /*!< Reset BPWM1 \hideinitializer */ +#define QEI0_RST ((8UL<<24) | SYS_IPRST2_QEI0RST_Pos) /*!< Reset QEI0 \hideinitializer */ +#define QEI1_RST ((8UL<<24) | SYS_IPRST2_QEI1RST_Pos) /*!< Reset QEI1 \hideinitializer */ +#define ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) /*!< Reset ECAP0 \hideinitializer */ +#define ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) /*!< Reset ECAP1 \hideinitializer */ +#define OPA_RST ((8UL<<24) | SYS_IPRST2_OPARST_Pos) /*!< Reset OPA \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brown Out Detector Threshold Voltage Selection constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_BODCTL_BOD_RST_EN (1UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable \hideinitializer */ +#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable \hideinitializer */ +#define SYS_BODCTL_BODVL_3_0V (7UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_8V (6UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_6V (5UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_4V (4UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_2V (3UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_0V (2UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V \hideinitializer */ +#define SYS_BODCTL_BODVL_1_8V (1UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V \hideinitializer */ +#define SYS_BODCTL_BODVL_1_6V (0UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* VREFCTL constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_VREFCTL_VREF_PIN (0x0UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin \hideinitializer */ +#define SYS_VREFCTL_VREF_1_6V (0x3UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V \hideinitializer */ +#define SYS_VREFCTL_VREF_2_0V (0x7UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V \hideinitializer */ +#define SYS_VREFCTL_VREF_2_5V (0xBUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V \hideinitializer */ +#define SYS_VREFCTL_VREF_3_0V (0xFUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V \hideinitializer */ +#define SYS_VREFCTL_VREF_AVDD (0x10UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = AVDD \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* USBPHY constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device \hideinitializer */ +#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */ +#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL << SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */ +#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_STD_USBD (0x0UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_STD_USBH (0x1UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB host \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_ID_DEPH (0x2UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< ID dependent device \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PLCTL constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_PLCTL_PLSEL_PL0 (0x0UL<GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ; + +*/ +/********************* Bit definition of GPA_MFPL register **********************/ +#define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<BODCTL |= SYS_BODCTL_BODIF_Msk) + +/** + * @brief Set Brown-out detector function to normal mode + * @param None + * @return None + * @details This macro set Brown-out detector to normal mode. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This macro disable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk) + +/** + * @brief Enable Brown-out detector function + * @param None + * @return None + * @details This macro enable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk) + +/** + * @brief Get Brown-out detector interrupt flag + * @param None + * @retval 0 Brown-out detect interrupt flag is not set. + * @retval >=1 Brown-out detect interrupt flag is set. + * @details This macro get Brown-out detector interrupt flag. + * \hideinitializer + */ +#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) + +/** + * @brief Get Brown-out detector status + * @param None + * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled. + * @retval >=1 System voltage is lower than BOD threshold voltage setting. + * @details This macro get Brown-out detector output status. + * If the BOD function is disabled, this function always return 0. + * \hideinitializer + */ +#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) + +/** + * @brief Enable Brown-out detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Enable Brown-out detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Set Brown-out detector function low power mode + * @param None + * @return None + * @details This macro set Brown-out detector to low power mode. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Set Brown-out detector voltage level + * @param[in] u32Level is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_3_0V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_1_6V + * @return None + * @details This macro set Brown-out detector voltage level. + * The write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level)) + +/** + * @brief Get reset source is from Brown-out detector reset + * @param None + * @retval 0 Previous reset source is not from Brown-out detector reset + * @retval >=1 Previous reset source is from Brown-out detector reset + * @details This macro get previous reset source is from Brown-out detect reset or not. + * \hideinitializer + */ +#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) + +/** + * @brief Get reset source is from CPU reset + * @param None + * @retval 0 Previous reset source is not from CPU reset + * @retval >=1 Previous reset source is from CPU reset + * @details This macro get previous reset source is from CPU reset. + * \hideinitializer + */ +#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) + +/** + * @brief Get reset source is from LVR Reset + * @param None + * @retval 0 Previous reset source is not from Low-Voltage-Reset + * @retval >=1 Previous reset source is from Low-Voltage-Reset + * @details This macro get previous reset source is from Low-Voltage-Reset. + * \hideinitializer + */ +#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) + +/** + * @brief Get reset source is from Power-on Reset + * @param None + * @retval 0 Previous reset source is not from Power-on Reset + * @retval >=1 Previous reset source is from Power-on Reset + * @details This macro get previous reset source is from Power-on Reset. + * \hideinitializer + */ +#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) + +/** + * @brief Get reset source is from reset pin reset + * @param None + * @retval 0 Previous reset source is not from reset pin reset + * @retval >=1 Previous reset source is from reset pin reset + * @details This macro get previous reset source is from reset pin reset. + * \hideinitializer + */ +#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) + +/** + * @brief Get reset source is from system reset + * @param None + * @retval 0 Previous reset source is not from system reset + * @retval >=1 Previous reset source is from system reset + * @details This macro get previous reset source is from system reset. + * \hideinitializer + */ +#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) + +/** + * @brief Get reset source is from window watch dog reset + * @param None + * @retval 0 Previous reset source is not from window watch dog reset + * @retval >=1 Previous reset source is from window watch dog reset + * @details This macro get previous reset source is from window watch dog reset. + * \hideinitializer + */ +#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) + +/** + * @brief Disable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro disable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk) + +/** + * @brief Enable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro enable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk) + +/** + * @brief Disable Power-on Reset function + * @param None + * @return None + * @details This macro disable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5) + +/** + * @brief Enable Power-on Reset function + * @param None + * @return None + * @details This macro enable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_POR() (SYS->PORCTL = 0) + +/** + * @brief Clear reset source flag + * @param[in] u32RstSrc is reset source. Including : + * - \ref SYS_RSTSTS_PORF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_CPULKRF_Msk + * @return None + * @details This macro clear reset source flag. + * \hideinitializer + */ +#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) ) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SYS_UnlockReg(void); +__STATIC_INLINE void SYS_LockReg(void); + +/** + * @brief Disable register write-protection function + * @param None + * @return None + * @details This function disable register write-protection function. + * To unlock the protected register to allow write access. + */ +__STATIC_INLINE void SYS_UnlockReg(void) +{ + do + { + SYS->REGLCTL = 0x59UL; + SYS->REGLCTL = 0x16UL; + SYS->REGLCTL = 0x88UL; + } + while(SYS->REGLCTL == 0UL); +} + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function is used to enable register write-protection function. + * To lock the protected register to forbid write access. + */ +__STATIC_INLINE void SYS_LockReg(void) +{ + SYS->REGLCTL = 0UL; +} + + +void SYS_ClearResetSrc(uint32_t u32Src); +uint32_t SYS_GetBODStatus(void); +uint32_t SYS_GetResetSrc(void); +uint32_t SYS_IsRegLocked(void); +uint32_t SYS_ReadPDID(void); +void SYS_ResetChip(void); +void SYS_ResetCPU(void); +void SYS_ResetModule(uint32_t u32ModuleIndex); +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); +void SYS_DisableBOD(void); +void SYS_SetPowerLevel(uint32_t u32PowerLevel); + + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/timer.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/timer.h new file mode 100644 index 00000000000..d8664d7fa53 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/timer.h @@ -0,0 +1,507 @@ +/**************************************************************************//** + * @file timer.h + * @version V1.00 + * @brief M480 series Timer Controller(Timer) driver header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx pin \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */ + +#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */ +#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */ +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */ + +#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */ + +#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */ +#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */ +#define TIMER_TRG_TO_EPWM (TIMER_TRGCTL_TRGEPWM_Msk) /*!< Each timer event as EPWM counter clock source \hideinitializer */ +#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion \hideinitializer */ +#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion \hideinitializer */ +#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer \hideinitializer */ + +/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Set Timer Compared Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF. + * + * @return None + * + * @details This macro is used to set timer compared value to adjust timer time-out interval. + * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n + * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n + * But if timer is operating at other modes, the timer up counter will restart counting and start from 0. + * \hideinitializer + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value)) + +/** + * @brief Set Timer Prescale Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF. + * + * @return None + * + * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n + * before it is fed into timer. + * \hideinitializer + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value)) + +/** + * @brief Check specify Timer Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * + * @details This macro is used to check if specify Timer counter is inactive or active. + * \hideinitializer + */ +#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0) + +/** + * @brief Select Toggle-output Pin + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32ToutSel Toggle-output pin selection, valid values are: + * - \ref TIMER_TOUT_PIN_FROM_TMX + * - \ref TIMER_TOUT_PIN_FROM_TMX_EXT + * + * @return None + * + * @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin. + * \hideinitializer + */ +#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer); +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer); +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer); + +/** + * @brief Start Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer counting. + */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop/suspend Timer counting. + */ +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Enable Timer Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n + * counter event interrupt or capture trigger interrupt. + * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC. + */ +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Disable Timer Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer interrupt wake-up function. + */ +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Start Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer capture function. + */ +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Stop Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop Timer capture function. + */ +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Disable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Enable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Disable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Enable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Disable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Enable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Disable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Get Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + * + * @details This function indicates timer time-out interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer time-out interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TIF_Msk; +} + +/** + * @brief Get Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + * + * @details This function indicates timer capture trigger interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return timer->EINTSTS; +} + +/** + * @brief Clear Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer capture trigger interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk; +} + +/** + * @brief Get Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer does not cause CPU wake-up + * @retval 1 Timer interrupt event cause CPU wake-up + * + * @details This function indicates timer interrupt event has waked up system or not. + */ +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears the timer wake-up system flag to 0. + */ +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TWKF_Msk; +} + +/** + * @brief Get Capture value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Capture Value + * + * @details This function reports the current 24-bit timer capture value. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->CAP; +} + +/** + * @brief Get Counter value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Counter Value + * + * @details This function reports the current 24-bit timer counter value. + */ +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->CNT; +} + +/** + * @brief Reset Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to reset current counter value and internal prescale counter value. + */ +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer) +{ + timer->CNT = 0UL; + while((timer->CNT&TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) + { + ; + } +} + + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt); +void TIMER_DisableFreqCounter(TIMER_T *timer); +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src); +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask); + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_H__ */ + + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/timer_pwm.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/timer_pwm.h new file mode 100644 index 00000000000..96a2cd1714c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/timer_pwm.h @@ -0,0 +1,745 @@ +/**************************************************************************//** + * @file timer_pwm.h + * @version V1.00 + * @brief M480 series Timer PWM Controller(Timer PWM) driver header file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_PWM_H__ +#define __TIMER_PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Channel Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */ +#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_UP_COUNT (0UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up count type \hideinitializer */ +#define TPWM_DOWN_COUNT (1UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Down count type \hideinitializer */ +#define TPWM_UP_DOWN_COUNT (2UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up-Down count type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */ +#define TPWM_ONE_SHOT_MODE (TIMER_PWMCTL_CNTMODE_Msk) /*!< One-shot mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */ +#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */ +#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */ +#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Trigger ADC Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TRIGGER_ADC_AT_ZERO_POINT (0UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_PERIOD_POINT (1UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT (2UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero or period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT (3UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter up count compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT (4UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter down count compare point event occurred \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ + + +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake \hideinitializer */ +#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Load Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */ +#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */ +#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin De-bounce Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */ +#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */ +#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */ +#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Synchronous Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */ +#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<ALTCTL = (1 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Disable PWM Counter Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available. + * @note All registers about PWM counter function will be cleared to 0 after executing this macro. + * \hideinitializer + */ +#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->ALTCTL = (0 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Enable Independent Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Enable Complementary Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Set Counter Type + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] type Timer PWM count type, could be one of the following type + * - \ref TPWM_UP_COUNT + * - \ref TPWM_DOWN_COUNT + * - \ref TPWM_UP_DOWN_COUNT + * + * @return None + * + * @details This macro is used to set Timer PWM counter type. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type)) + +/** + * @brief Start PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable PWM generator and start counter counting. + * \hideinitializer + */ +#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk) + +/** + * @brief Stop PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to stop PWM counter after current period is completed. + * \hideinitializer + */ +#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0) + +/** + * @brief Set Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFFF. + * + * @return None + * + * @details This macro is used to set the prescaler of specified TIMER PWM. + * @note If prescaler is 0, then there is no scaling in counter clock source. + * \hideinitializer + */ +#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler)) + +/** + * @brief Get Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0]) + * + * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1). + * \hideinitializer + */ +#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC) + +/** + * @brief Set Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period)) + +/** + * @brief Get Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0]) + * + * @details This macro is used to get the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD) + +/** + * @brief Set Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp)) + +/** + * @brief Get Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0]) + * + * @details This macro is used to get the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT) + +/** + * @brief Clear Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear counter of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk) + +/** + * @brief Software Trigger Brake Event + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] type Type of brake trigger. Valid values are: + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This macro is used to trigger brake event by writing PWMSWBRK register. + * \hideinitializer + */ +#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output function. Valid values are: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If the corresponding bit in u32ChMask parameter is 0, then output function will be disabled in this channel. + * \hideinitializer + */ +#define TPWM_ENABLE_OUTPUT(timer, ch) ((timer)->PWMPOEN = (ch)) + +/** + * @brief Set Output Inverse + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Set specified channel output is inversed or not. Valid values are: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output inverse of specified output pins. + * @note If u32ChMask parameter is 0, then output inverse function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_OUTPUT_INVERSE(timer, ch) ((timer)->PWMPOLCTL = (ch)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output mask function. Valid values are: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @param[in] level Output to high or low on specified mask channel. + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If u32ChMask parameter is 0, then output mask function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0) + +/** + * @brief Set Counter Synchronous Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] mode Synchronous mode. Possible options are: + * - \ref TPWM_CNTR_SYNC_DISABLE + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER2 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2 + * + * @return None + * + * @details This macro is used to set counter synchronous mode of specified Timer PWM module. + * @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and + * TIMER2~3 PWM counter synchronous by TIMER2 PWM. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode)) + +/** + * @brief Trigger Counter Synchronous + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to trigger synchronous event by specified TIMER PWM. + * @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n + * 2. STRGEN (PWMSTRG[0]) is write only and always read as 0. + * \hideinitializer + */ +#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk) + +/** + * @brief Enable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Disable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Get Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Zero event interrupt did not occur + * @retval 1 Zero event interrupt occurred + * + * @details This macro indicates zero event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0) + +/** + * @brief Clear Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears zero event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk) + +/** + * @brief Enable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Disable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Get Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Period event interrupt did not occur + * @retval 1 Period event interrupt occurred + * + * @details This macro indicates period event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0) + +/** + * @brief Clear Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears period event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk) + +/** + * @brief Enable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Disable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Get Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare up event interrupt did not occur + * @retval 1 Compare up event interrupt occurred + * + * @details This macro indicates compare up event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare up event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk) + +/** + * @brief Enable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Disable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Get Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare down event interrupt did not occur + * @retval 1 Compare down event interrupt occurred + * + * @details This macro indicates compare down event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare down event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk) + +/** + * @brief Get Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer PWM counter never counts to maximum value + * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF + * + * @details This macro indicates Timer PWM counter has count to 0xFFFF or not. + * \hideinitializer + */ +#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0) + +/** + * @brief Clear Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears reach maximum count status. + * \hideinitializer + */ +#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk) + +/** + * @brief Get Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Trigger ADC start conversion is not occur + * @retval 1 Specified counter compare event has trigger ADC start conversion + * + * @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear PWM counter compare event trigger ADC status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk) + +/** + * @brief Set Brake Event at Brake Pin High or Low-to-High + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * @note The default brake pin detection is high level or from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set Brake Event at Brake Pin Low or High-to-Low + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set External Brake Pin Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] pin The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<> 4ul)-2ul) + + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode2 divider + * + * @details This macro calculate UART baudrate mode2 divider. + * \hideinitializer + */ +#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul) + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data)) + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module + * + * @return The oldest data byte in RX FIFO. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UART_READ(uart) ((uart)->DAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not empty + * @retval >=1 Tx FIFO is empty + * + * @details This macro get Transmitter FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not empty + * @retval >=1 Rx FIFO is empty + * + * @details This macro get Receiver FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified UART port transmission is over. + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. + * It indicates if specified UART port transmission is over nor not. + * \hideinitializer + */ +#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos) + + +/** + * @brief Wait specified UART port transmission is over + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro wait specified UART port transmission is over. + * \hideinitializer + */ +#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)) + + +/** + * @brief Check RX is ready or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 The number of bytes in the RX FIFO is less than the RFITL + * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL + * + * @details This macro check receive data available interrupt flag is set or not. + * \hideinitializer + */ +#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 TX FIFO is full + * @retval 0 TX FIFO is not full + * + * @details This macro check TX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos) + + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 RX FIFO is full + * @retval 0 RX FIFO is not full + * + * @details This macro check RX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not full. + * @retval >=1 Tx FIFO is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not full. + * @retval >=1 Rx FIFO is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk) + + +/** + * @brief Enable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel)) + + +/** + * @brief Disable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel)) + + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_HWTOINT_Msk : In DMA Mode, Time-out Interrupt Indicator + * - \ref UART_INTSTS_HWMODINT_Msk : In DMA Mode, MODEM Status Interrupt Indicator + * - \ref UART_INTSTS_HWRLSINT_Msk : In DMA Mode, Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_HWBUFEIF_Msk : In DMA Mode, Buffer Error Interrupt Flag + * - \ref UART_INTSTS_HWTOIF_Msk : In DMA Mode, Time-out Interrupt Flag + * - \ref UART_INTSTS_HWMODIF_Msk : In DMA Mode, MODEM Interrupt Flag + * - \ref UART_INTSTS_HWRLSIF_Msk : In DMA Mode, Receive Line Status Flag + * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator + * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator + * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag + * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag + * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag + * - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag + * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag + * - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag + * - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0) + + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro clear RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Receiver detects a data that is not an address bit. + * @retval 1 Receiver detects a data that is an address bit. + * + * @details This macro get RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart); +__STATIC_INLINE void UART_SET_RTS(UART_T* uart); + + +/** + * @brief Set RTS pin to low + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to low. + */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + uart->MODEM &= ~UART_MODEM_RTS_Msk; +} + + +/** + * @brief Set RTS pin to high + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to high. + */ +__STATIC_INLINE void UART_SET_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk; +} + + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Close(UART_T* uart); +void UART_DisableFlowCtrl(UART_T* uart); +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_EnableFlowCtrl(UART_T* uart); +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Open(UART_T* uart, uint32_t u32baudrate); +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr); +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength); +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + + + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__UART_H__*/ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/usbd.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/usbd.h new file mode 100644 index 00000000000..5cf40f5e078 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/usbd.h @@ -0,0 +1,692 @@ +/**************************************************************************//** + * @file usbd.h + * @version V1.00 + * @brief M480 series USB driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __USBD_H__ +#define __USBD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_EXPORTED_STRUCT USBD Exported Struct + @{ +*/ +typedef struct s_usbd_info +{ + uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */ + uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */ + uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */ + uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */ + uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */ + uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */ + uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */ + +} S_USBD_INFO_T; /*!< Device description structure */ + +extern const S_USBD_INFO_T gsInfo; + +/*@}*/ /* end of group USBD_EXPORTED_STRUCT */ + + + + +/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants + @{ +*/ +#define USBD_BUF_BASE (USBD_BASE+0x100ul) /*!< USBD buffer base address \hideinitializer */ +#define USBD_MAX_EP 12ul /*!< Total EP number \hideinitializer */ + +#define EP0 0ul /*!< Endpoint 0 \hideinitializer */ +#define EP1 1ul /*!< Endpoint 1 \hideinitializer */ +#define EP2 2ul /*!< Endpoint 2 \hideinitializer */ +#define EP3 3ul /*!< Endpoint 3 \hideinitializer */ +#define EP4 4ul /*!< Endpoint 4 \hideinitializer */ +#define EP5 5ul /*!< Endpoint 5 \hideinitializer */ +#define EP6 6ul /*!< Endpoint 6 \hideinitializer */ +#define EP7 7ul /*!< Endpoint 7 \hideinitializer */ +#define EP8 8ul /*!< Endpoint 8 \hideinitializer */ +#define EP9 9ul /*!< Endpoint 9 \hideinitializer */ +#define EP10 10ul /*!< Endpoint 10 \hideinitializer */ +#define EP11 11ul /*!< Endpoint 11 \hideinitializer */ + +/** @cond HIDDEN_SYMBOLS */ +/* USB Request Type */ +#define REQ_STANDARD 0x00ul +#define REQ_CLASS 0x20ul +#define REQ_VENDOR 0x40ul + +/* USB Standard Request */ +#define GET_STATUS 0x00ul +#define CLEAR_FEATURE 0x01ul +#define SET_FEATURE 0x03ul +#define SET_ADDRESS 0x05ul +#define GET_DESCRIPTOR 0x06ul +#define SET_DESCRIPTOR 0x07ul +#define GET_CONFIGURATION 0x08ul +#define SET_CONFIGURATION 0x09ul +#define GET_INTERFACE 0x0Aul +#define SET_INTERFACE 0x0Bul +#define SYNC_FRAME 0x0Cul + +/* USB Descriptor Type */ +#define DESC_DEVICE 0x01ul +#define DESC_CONFIG 0x02ul +#define DESC_STRING 0x03ul +#define DESC_INTERFACE 0x04ul +#define DESC_ENDPOINT 0x05ul +#define DESC_QUALIFIER 0x06ul +#define DESC_OTHERSPEED 0x07ul +#define DESC_IFPOWER 0x08ul +#define DESC_OTG 0x09ul +#define DESC_BOS 0x0Ful +#define DESC_CAPABILITY 0x10ul + +/* USB Device Capability Type */ +#define CAP_WIRELESS 0x01ul +#define CAP_USB20_EXT 0x02ul + +/* USB HID Descriptor Type */ +#define DESC_HID 0x21ul +#define DESC_HID_RPT 0x22ul + +/* USB Descriptor Length */ +#define LEN_DEVICE 18ul +#define LEN_QUALIFIER 10ul +#define LEN_CONFIG 9ul +#define LEN_INTERFACE 9ul +#define LEN_ENDPOINT 7ul +#define LEN_OTG 5ul +#define LEN_BOS 5ul +#define LEN_HID 9ul +#define LEN_CCID 0x36ul +#define LEN_BOSCAP 7ul + +/* USB Endpoint Type */ +#define EP_ISO 0x01 +#define EP_BULK 0x02 +#define EP_INT 0x03 + +#define EP_INPUT 0x80 +#define EP_OUTPUT 0x00 + +/* USB Feature Selector */ +#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01ul +#define FEATURE_ENDPOINT_HALT 0x00ul +/** @endcond HIDDEN_SYMBOLS */ + +/******************************************************************************/ +/* USB Specific Macros */ +/******************************************************************************/ + +#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable \hideinitializer */ +#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 \hideinitializer */ + +#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable \hideinitializer */ +#define USBD_PWRDN USBD_ATTR_PWRDN_Msk /*!< PHY Turn-On \hideinitializer */ +#define USBD_PHY_EN USBD_ATTR_PHYEN_Msk /*!< PHY Enable \hideinitializer */ +#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable \hideinitializer */ + +#define USBD_INT_BUS USBD_INTEN_BUSIEN_Msk /*!< USB Bus Event Interrupt \hideinitializer */ +#define USBD_INT_USB USBD_INTEN_USBIEN_Msk /*!< USB Event Interrupt \hideinitializer */ +#define USBD_INT_FLDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt \hideinitializer */ +#define USBD_INT_WAKEUP (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk) /*!< USB No-Event-Wake-Up Interrupt \hideinitializer */ + +#define USBD_INTSTS_WAKEUP USBD_INTSTS_NEVWKIF_Msk /*!< USB No-Event-Wake-Up Interrupt Status \hideinitializer */ +#define USBD_INTSTS_FLDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status \hideinitializer */ +#define USBD_INTSTS_BUS USBD_INTSTS_BUSIF_Msk /*!< USB Bus Event Interrupt Status \hideinitializer */ +#define USBD_INTSTS_USB USBD_INTSTS_USBIF_Msk /*!< USB Event Interrupt Status \hideinitializer */ +#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event \hideinitializer */ +#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event \hideinitializer */ +#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event \hideinitializer */ +#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event \hideinitializer */ +#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event \hideinitializer */ +#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event \hideinitializer */ +#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event \hideinitializer */ +#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event \hideinitializer */ +#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event \hideinitializer */ +#define USBD_INTSTS_EP8 USBD_INTSTS_EPEVT8_Msk /*!< USB Endpoint 8 Event \hideinitializer */ +#define USBD_INTSTS_EP9 USBD_INTSTS_EPEVT9_Msk /*!< USB Endpoint 9 Event \hideinitializer */ +#define USBD_INTSTS_EP10 USBD_INTSTS_EPEVT10_Msk /*!< USB Endpoint 10 Event \hideinitializer */ +#define USBD_INTSTS_EP11 USBD_INTSTS_EPEVT11_Msk /*!< USB Endpoint 11 Event \hideinitializer */ + +#define USBD_STATE_USBRST USBD_ATTR_USBRST_Msk /*!< USB Bus Reset \hideinitializer */ +#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend \hideinitializer */ +#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume \hideinitializer */ +#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout \hideinitializer */ + +#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall \hideinitializer */ +#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall \hideinitializer */ + +#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos)/*!< Endpoint Disable \hideinitializer */ +#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_STATE_Pos)/*!< Out Endpoint \hideinitializer */ +#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_STATE_Pos)/*!< In Endpoint \hideinitializer */ +#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous \hideinitializer */ + + + +/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ +/** + * @brief Compare two input numbers and return maximum one. + * + * @param[in] a First number to be compared. + * @param[in] b Second number to be compared. + * + * @return Maximum value between a and b. + * + * @details If a > b, then return a. Otherwise, return b. + * \hideinitializer + */ +#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b)) + + +/** + * @brief Compare two input numbers and return minimum one + * + * @param[in] a First number to be compared + * @param[in] b Second number to be compared + * + * @return Minimum value between a and b + * + * @details If a < b, then return a. Otherwise, return b. + * \hideinitializer + */ +#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b)) + + +/** + * @brief Enable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB and PHY. + * \hideinitializer + */ +#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= 0x7D0)) + +/** + * @brief Disable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB. + * \hideinitializer + */ +#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN)) + +/** + * @brief Enable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB PHY. + * \hideinitializer + */ +#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN)) + +/** + * @brief Disable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB PHY. + * \hideinitializer + */ +#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN)) + +/** + * @brief Enable SE0. Force USB PHY transceiver to drive SE0. + * + * @param None + * + * @return None + * + * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus. + * \hideinitializer + */ +#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0)) + +/** + * @brief Disable SE0 + * + * @param None + * + * @return None + * + * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function. + * \hideinitializer + */ +#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0)) + +/** + * @brief Set USB device address + * + * @param[in] addr The USB device address. + * + * @return None + * + * @details Write USB device address to USB_FADDR register. + * \hideinitializer + */ +#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr)) + +/** + * @brief Get USB device address + * + * @param None + * + * @return USB device address + * + * @details Read USB_FADDR register to get USB device address. + * \hideinitializer + */ +#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR)) + +/** + * @brief Enable USB interrupt function + * + * @param[in] intr The combination of the specified interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. + * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS) + * + * @return None + * + * @details Enable USB related interrupt functions specified by intr parameter. + * \hideinitializer + */ +#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr)) + +/** + * @brief Get interrupt status + * + * @param None + * + * @return The value of USB_INTSTS register + * + * @details Return all interrupt flags of USB_INTSTS register. + * \hideinitializer + */ +#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS)) + +/** + * @brief Clear USB interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB) + * + * @return None + * + * @details Clear USB related interrupt flags specified by flag parameter. + * \hideinitializer + */ +#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag)) + +/** + * @brief Get endpoint status + * + * @param None + * + * @return The value of USB_EPSTS register. + * + * @details Return all endpoint status. + * \hideinitializer + */ +#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS)) + +/** + * @brief Get USB bus state + * + * @param None + * + * @return The value of USB_ATTR[3:0]. + * Bit 0 indicates USB bus reset status. + * Bit 1 indicates USB bus suspend status. + * Bit 2 indicates USB bus resume status. + * Bit 3 indicates USB bus time-out status. + * + * @details Return USB_ATTR[3:0] for USB bus events. + * \hideinitializer + */ +#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0xf)) + +/** + * @brief Check cable connection state + * + * @param None + * + * @retval 0 USB cable is not attached. + * @retval 1 USB cable is attached. + * + * @details Check the connection state by FLDET bit of USB_FLDET register. + * \hideinitializer + */ +#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)) + +/** + * @brief Stop USB transaction of the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk) + +/** + * @brief Set USB DATA1 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * \hideinitializer + */ +#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk) + +/** + * @brief Set USB DATA0 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * \hideinitializer + */ +#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)) + +/** + * @brief Set USB payload size (IN data) + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] size The transfer length. + * + * @return None + * + * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction. + * \hideinitializer + */ +#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)) + +/** + * @brief Get USB payload size (OUT data) + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 endpoint ID. This parameter could be 0 ~ 11. + * + * @return The value of USB_MXPLDx register. + * + * @details Get the data length of OUT data transaction by reading USB_MXPLDx register. + * \hideinitializer + */ +#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4)))) + +/** + * @brief Configure endpoint + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] config The USB configuration. + * + * @return None + * + * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID. + * \hideinitializer + */ +#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)) + +/** + * @brief Set USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] offset The SRAM offset. + * + * @return None + * + * @details This macro will set the SRAM offset for the specified endpoint ID. + * \hideinitializer + */ +#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)) + +/** + * @brief Get the offset of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return The offset of the specified endpoint buffer. + * + * @details This macro will return the SRAM offset of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4)))) + +/** + * @brief Set USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + * \hideinitializer + */ +#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0ul].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk) + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + * \hideinitializer + */ +#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk) + +/** + * @brief Get USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M480 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk) + +/** + * @brief To support byte access between USB SRAM and system SRAM + * + * @param[in] dest Destination pointer. + * + * @param[in] src Source pointer. + * + * @param[in] size Byte count. + * + * @return None + * + * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter. + * + */ +__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size) +{ + uint32_t volatile i=0ul; + + while(size--) + { + dest[i] = src[i]; + i++; + } +} + +/** + * @brief Set USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically. + * + */ +__STATIC_INLINE void USBD_SetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void USBD_ClearStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + * + */ +__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + break; + } + } + + return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL); +} + + +extern volatile uint8_t g_usbd_RemoteWakeupEn; + + +typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */ +typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */ +typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */ +typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */ + + +/*--------------------------------------------------------------------*/ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface); +void USBD_Start(void); +void USBD_GetSetupPacket(uint8_t *buf); +void USBD_ProcessSetupPacket(void); +void USBD_StandardRequest(void); +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size); +void USBD_CtrlIn(void); +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size); +void USBD_CtrlOut(void); +void USBD_SwReset(void); +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq); +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback); +void USBD_LockEpStall(uint32_t u32EpBitmap); + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__USBD_H__*/ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_i2c.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_i2c.h new file mode 100644 index 00000000000..b57621a5ff7 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_i2c.h @@ -0,0 +1,331 @@ +/**************************************************************************//** + * @file USCI_I2C.h + * @version V3.0 + * @brief M480 series USCI I2C(UI2C) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __USCI_I2C_H__ +#define __USCI_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + +/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C master event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_MASTER_EVENT +{ + MASTER_SEND_ADDRESS = 10, /*!< Master send address to Slave */ + MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */ + MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */ + MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */ + MASTER_SEND_DATA, /*!< Master Send Data to Slave */ + MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */ + MASTER_READ_DATA, /*!< Master Get Data from Slave */ + MASTER_STOP, /*!< Master send stop to Slave */ + MASTER_SEND_START /*!< Master send start to Slave */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C slave event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_SLAVE_EVENT +{ + SLAVE_ADDRESS_ACK = 100, /*!< Slave send address ACK */ + SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */ + SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */ + SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */ + SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_CTL_PTRG 0x20UL /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit \hideinitializer */ +#define UI2C_CTL_STA 0x08UL /*!< USCI_CTL setting for I2C control bits. It would set STA bit \hideinitializer */ +#define UI2C_CTL_STO 0x04UL /*!< USCI_CTL setting for I2C control bits. It would set STO bit \hideinitializer */ +#define UI2C_CTL_AA 0x02UL /*!< USCI_CTL setting for I2C control bits. It would set AA bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode \hideinitializer */ +#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C Wakeup Mode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle \hideinitializer */ +#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask \hideinitializer */ +#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask \hideinitializer */ +#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask \hideinitializer */ +#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask \hideinitializer */ +#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask \hideinitializer */ +#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask \hideinitializer */ +#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask \hideinitializer */ + +/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This macro sets the USCI_I2C protocol control register at one time + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Ctrl Set the register value of USCI_I2C control register. + * + * @return None + * + * @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, SI, ACK. + * \hideinitializer + */ +#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl)) + +/** + * @brief This macro only set START bit to protocol control register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register. + * \hideinitializer + */ +#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk) + +/** + * @brief This macro only set STOP bit to the control register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register. + * \hideinitializer + */ +#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk)) + +/** + * @brief This macro returns the data stored in data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Data + * + * @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus + * \hideinitializer + */ +#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT) + +/** + * @brief This macro writes the data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus + * \hideinitializer + */ +#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data)) + +/** + * @brief This macro returns time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 USCI_I2C bus time-out is not happened + * @retval 1 USCI_I2C bus time-out is happened + * + * @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared. + * \hideinitializer + */ +#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0) + +/** + * @brief This macro returns wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep. + * \hideinitializer + */ +#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief This macro is used to clear USCI_I2C wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details If USCI_I2C wake-up flag is set, use this macro to clear it. + * \hideinitializer + */ +#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk) + +/** + * @brief This macro disables the USCI_I2C 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function. + * \hideinitializer + */ +#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk)) + +/** + * @brief This macro enables the 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To enable USCI_I2C 10-bit address match function. + * \hideinitializer + */ +#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk) + +/** + * @brief This macro gets USCI_I2C protocol interrupt flag or bus status + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return A word data of USCI_I2C_PROTSTS register + * + * @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status. + * \hideinitializer + */ +#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS) + +/** + * @brief This macro clears specified protocol interrupt flag + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UI2C_PROTSTS_ACKIF_Msk + * - \ref UI2C_PROTSTS_ERRIF_Msk + * - \ref UI2C_PROTSTS_ARBLOIF_Msk + * - \ref UI2C_PROTSTS_NACKIF_Msk + * - \ref UI2C_PROTSTS_STORIF_Msk + * - \ref UI2C_PROTSTS_STARIF_Msk + * - \ref UI2C_PROTSTS_TOIF_Msk + * @return None + * + * @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag. + * \hideinitializer + */ +#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief This macro enables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function. + * \hideinitializer + */ +#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel)) + +/** + * @brief This macro disables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt function. + * \hideinitializer + */ +#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel)) + + +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock); +void UI2C_Close(UI2C_T *ui2c); +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c); +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack); +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask); +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c); +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock); +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_ClearIntFlag(UI2C_T* ui2c, uint32_t u32Mask); +uint32_t UI2C_GetData(UI2C_T *ui2c); +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data); +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode); +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask); +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt); +void UI2C_DisableTimeout(UI2C_T *ui2c); +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode); +void UI2C_DisableWakeup(UI2C_T *ui2c); +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr); +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen); +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen); +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen); + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_spi.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_spi.h new file mode 100644 index 00000000000..a951a85d2c4 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_spi.h @@ -0,0 +1,410 @@ +/****************************************************************************//** + * @file usci_spi.h + * @version V3.00 + * @brief M480 series USCI_SPI driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_SPI_H__ +#define __USCI_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + +/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants + @{ +*/ + +#define USPI_MODE_0 (0x0 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge \hideinitializer */ +#define USPI_MODE_1 (0x1 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge \hideinitializer */ +#define USPI_MODE_2 (0x2 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge \hideinitializer */ +#define USPI_MODE_3 (0x3 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge \hideinitializer */ + +#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define USPI_MASTER (0x0ul) /*!< Set as master \hideinitializer */ + +#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define USPI_SS_ACTIVE_HIGH (0x0ul) /*!< SS active high \hideinitializer */ +#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low \hideinitializer */ + +/* USCI_SPI Interrupt Mask */ +#define USPI_SSINACT_INT_MASK (0x001ul) /*!< Slave Slave Inactive interrupt mask \hideinitializer */ +#define USPI_SSACT_INT_MASK (0x002ul) /*!< Slave Slave Active interrupt mask \hideinitializer */ +#define USPI_SLVTO_INT_MASK (0x004ul) /*!< Slave Mode Time-out interrupt mask \hideinitializer */ +#define USPI_SLVBE_INT_MASK (0x008ul) /*!< Slave Mode Bit Count Error interrupt mask \hideinitializer */ +#define USPI_TXUDR_INT_MASK (0x010ul) /*!< Slave Transmit Under Run interrupt mask \hideinitializer */ +#define USPI_RXOV_INT_MASK (0x020ul) /*!< Receive Buffer Overrun interrupt mask \hideinitializer */ +#define USPI_TXST_INT_MASK (0x040ul) /*!< Transmit Start interrupt mask \hideinitializer */ +#define USPI_TXEND_INT_MASK (0x080ul) /*!< Transmit End interrupt mask \hideinitializer */ +#define USPI_RXST_INT_MASK (0x100ul) /*!< Receive Start interrupt mask \hideinitializer */ +#define USPI_RXEND_INT_MASK (0x200ul) /*!< Receive End interrupt mask \hideinitializer */ + +/* USCI_SPI Status Mask */ +#define USPI_BUSY_MASK (0x01ul) /*!< Busy status mask \hideinitializer */ +#define USPI_RX_EMPTY_MASK (0x02ul) /*!< RX empty status mask \hideinitializer */ +#define USPI_RX_FULL_MASK (0x04ul) /*!< RX full status mask \hideinitializer */ +#define USPI_TX_EMPTY_MASK (0x08ul) /*!< TX empty status mask \hideinitializer */ +#define USPI_TX_FULL_MASK (0x10ul) /*!< TX full status mask \hideinitializer */ +#define USPI_SSLINE_STS_MASK (0x20ul) /*!< USCI_SPI_SS line status mask \hideinitializer */ + +/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief Disable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Get the Rx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Rx buffer flag + * @retval 0: Rx buffer is not empty + * @retval 1: Rx buffer is empty + * \hideinitializer + */ +#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not empty + * @retval 1: Tx buffer is empty + * \hideinitializer + */ +#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer full flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not full + * @retval 1: Tx buffer is full + * \hideinitializer + */ +#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 ) + +/** + * @brief Get the datum read from RX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return data in Rx register + * \hideinitializer + */ +#define USPI_READ_RX(uspi) ((uspi)->RXDAT) + +/** + * @brief Write datum to TX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus. + * @return None + * \hideinitializer + */ +#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) ) + +/** + * @brief Set USCI_SPI_SS pin to high state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_HIGH(uspi) \ + do{ \ + (uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \ + (uspi)->PROTCTL = ((uspi)->PROTCTL & ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk)); \ + }while(0) + +/** + * @brief Set USCI_SPI_SS pin to low state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_LOW(uspi) \ + do{ \ + (uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set the length of suspend interval. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SuspCycle Decide the length of suspend interval. + * @return None + * \hideinitializer + */ +#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) ) + +/** + * @brief Set the USCI_SPI transfer sequence with LSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the USCI_SPI transfer sequence with MSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the data width of a USCI_SPI transaction. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Width The data width + * @return None + * \hideinitializer + */ +#define USPI_SET_DATA_WIDTH(uspi,u32Width) \ + do{ \ + if((u32Width) == 16ul){ \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \ + }else { \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \ + } \ + }while(0) + +/** + * @brief Get the USCI_SPI busy state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return USCI_SPI busy status + * @retval 0: USCI_SPI module is not busy + * @retval 1: USCI_SPI module is busy + * \hideinitializer + */ +#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 ) + +/** + * @brief Get the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Wakeup status. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + * \hideinitializer + */ +#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief Clear the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk) + +/** + * @brief Get protocol interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of protocol status register. + * \hideinitializer + */ +#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS) + +/** + * @brief Clear specified protocol interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_PROTSTS_SSACTIF_Msk + * - \ref USPI_PROTSTS_SSINAIF_Msk + * - \ref USPI_PROTSTS_SLVBEIF_Msk + * - \ref USPI_PROTSTS_SLVTOIF_Msk + * - \ref USPI_PROTSTS_RXENDIF_Msk + * - \ref USPI_PROTSTS_RXSTIF_Msk + * - \ref USPI_PROTSTS_TXENDIF_Msk + * - \ref USPI_PROTSTS_TXSTIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_PROT_INT_FLAG(uspi,u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief Get buffer interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of buffer status register. + * \hideinitializer + */ +#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS) + +/** + * @brief Clear specified buffer interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_BUFSTS_TXUDRIF_Msk + * - \ref USPI_BUFSTS_RXOVIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_BUF_INT_FLAG(uspi,u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag)) + +/** + * @brief Enable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ((uspi)->PROTIEN |= (u32IntSel)) + +/** + * @brief Disable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ((uspi)->PROTIEN &= ~ (u32IntSel)) + +/** + * @brief Enable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ((uspi)->BUFCTL |= (u32IntSel)) + +/** + * @brief Disable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ((uspi)->BUFCTL &= ~ (u32IntSel)) + +/** + * @brief Enable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ((uspi)->INTEN |= (u32IntSel)) + +/** + * @brief Disable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ((uspi)->INTEN &= ~ (u32IntSel)) + + +/** + * @brief Trigger RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_RX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_TX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk ) + +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void USPI_Close(USPI_T *uspi); +void USPI_ClearRxBuf(USPI_T *uspi); +void USPI_ClearTxBuf(USPI_T *uspi); +void USPI_DisableAutoSS(USPI_T *uspi); +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock); +uint32_t USPI_GetBusClock(USPI_T *uspi); +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask); +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask); +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask); +void USPI_EnableWakeup(USPI_T *uspi); +void USPI_DisableWakeup(USPI_T *uspi); + + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_SPI_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_uart.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_uart.h new file mode 100644 index 00000000000..636b2c4d239 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/usci_uart.h @@ -0,0 +1,438 @@ +/**************************************************************************//** + * @file usci_uart.h + * @version V3.00 + * @brief M480 series USCI UART (UUART) driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_UART_H__ +#define __USCI_UART_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_LINECTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_WORD_LEN_6 (6ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits \hideinitializer */ +#define UUART_WORD_LEN_7 (7ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits \hideinitializer */ +#define UUART_WORD_LEN_8 (8ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits \hideinitializer */ +#define UUART_WORD_LEN_9 (9ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_PROTCTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_PARITY_NONE (0x0ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity \hideinitializer */ +#define UUART_PARITY_ODD (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity \hideinitializer */ +#define UUART_PARITY_EVEN (0x3ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity \hideinitializer */ + +#define UUART_STOP_BIT_1 (0x0ul) /*!< UUART_PROTCTL setting for one stop bit \hideinitializer */ +#define UUART_STOP_BIT_2 (0x1ul) /*!< UUART_PROTCTL setting for two stop bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI UART interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_ABR_INT_MASK (0x002ul) /*!< Auto-baud rate interrupt mask \hideinitializer */ +#define UUART_RLS_INT_MASK (0x004ul) /*!< Receive line status interrupt mask \hideinitializer */ +#define UUART_BUF_RXOV_INT_MASK (0x008ul) /*!< Buffer RX overrun interrupt mask \hideinitializer */ +#define UUART_TXST_INT_MASK (0x010ul) /*!< TX start interrupt mask \hideinitializer */ +#define UUART_TXEND_INT_MASK (0x020ul) /*!< Tx end interrupt mask \hideinitializer */ +#define UUART_RXST_INT_MASK (0x040ul) /*!< RX start interrupt mask \hideinitializer */ +#define UUART_RXEND_INT_MASK (0x080ul) /*!< RX end interrupt mask \hideinitializer */ + + +/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data)) + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The oldest data byte in RX buffer. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UUART_READ(uuart) ((uuart)->RXDAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not empty + * @retval >=1 Tx buffer is empty + * + * @details This macro get Transmitter buffer empty register value. + * \hideinitializer + */ +#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not empty + * @retval >=1 Rx buffer is empty + * + * @details This macro get Receiver buffer empty register value. + * \hideinitializer + */ +#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified usci_uart port transmission is over. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. \n + * It indicates if specified usci_uart port transmission is over nor not. + * \hideinitializer + */ +#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos) + + +/** + * @brief Check specified usci_uart port receiver is empty. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx receiver is not empty + * @retval 1 Rx receiver is empty + * + * @details This macro return Receive Empty Flag register bit value. \n + * It indicates if specified usci_uart port receiver is empty nor not. + * \hideinitializer + */ +#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos) + + +/** + * @brief Wait specified usci_uart port transmission is over + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro wait specified usci_uart port transmission is over. + * \hideinitializer + */ +#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)) + + +/** + * @brief Check TX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 TX buffer is full + * @retval 0 TX buffer is not full + * + * @details This macro check TX buffer is full or not. + * \hideinitializer + */ +#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos) + + +/** + * @brief Check RX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 RX buffer is full + * @retval 0 RX buffer is not full + * + * @details This macro check RX buffer is full or not. + * \hideinitializer + */ +#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not full. + * @retval >=1 Tx buffer is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not full. + * @retval >=1 Rx buffer is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk) + + +/** + * @brief Enable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART protocol interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART protocol interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel)) + + +/** + * @brief Enable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART buffer interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART buffer interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel)) + + +/** + * @brief Enable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART transfer interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART transfer interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel)) + + +/** + * @brief Get protocol interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of protocol status register. + * + * @details This macro get protocol status register value. + * \hideinitializer + */ +#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS) + + +/** + * @brief Clear specified protocol interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator + * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag + * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag + * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag + * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag + * - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag + * - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag + * - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag + * - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag + * + * @return None + * + * @details This macro clear specified protocol interrupt flag. + * \hideinitializer + */ +#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag)) + + +/** + * @brief Get transmit/receive buffer interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of buffer status register. + * + * @details This macro get buffer status register value. + * \hideinitializer + */ +#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS) + + +/** + * @brief Clear specified buffer interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator + * + * @return None + * + * @details This macro clear specified buffer interrupt flag. + * \hideinitializer + */ +#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag)) + + +/** + * @brief Get wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Chip did not wake up from power-down mode. + * @retval 1 Chip waked up from power-down mode. + * + * @details This macro get wakeup flag. + * \hideinitializer + */ +#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 ) + + +/** + * @brief Clear wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro clear wakeup flag. + * \hideinitializer + */ +#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk) + + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask); +void UUART_Close(UUART_T* uuart); +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask); +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate); +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode); +void UUART_DisableWakeup(UUART_T* uuart); +void UUART_EnableFlowCtrl(UUART_T* uuart); +void UUART_DisableFlowCtrl(UUART_T* uuart); + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_UART_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/wdt.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/wdt.h new file mode 100644 index 00000000000..17dc9fac217 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/wdt.h @@ -0,0 +1,215 @@ +/**************************************************************************//** + * @file wdt.h + * @version V3.00 + * @brief M480 series WDT driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_H__ +#define __WDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */ + +/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Clear WDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out reset system flag. + * \hideinitializer + */ +#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk) + +/** + * @brief Clear WDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out interrupt flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk) + +/** + * @brief Clear WDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out wake-up system flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk) + +/** + * @brief Get WDT Time-out Reset Flag + * + * @param None + * + * @retval 0 WDT time-out reset system did not occur + * @retval 1 WDT time-out reset system occurred + * + * @details This macro indicates system has been reset by WDT time-out reset or not. + * \hideinitializer + */ +#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * + * @details This macro indicates WDT time-out interrupt occurred or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt does not cause CPU wake-up + * @retval 1 WDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates WDT time-out interrupt event has waked up system or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset WDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset the internal 18-bit WDT up counter value. + * @note If WDT is activated and time-out reset system function is enabled also, user should \n + * reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n + * reset system before the WDT time-out reset delay period expires. + * \hideinitializer + */ +#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void WDT_Close(void); +__STATIC_INLINE void WDT_EnableInt(void); +__STATIC_INLINE void WDT_DisableInt(void); + +/** + * @brief Stop WDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop WDT counting and disable WDT module. + */ +__STATIC_INLINE void WDT_Close(void) +{ + WDT->CTL = 0UL; + return; +} + +/** + * @brief Enable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_EnableInt(void) +{ + WDT->CTL |= WDT_CTL_INTEN_Msk; + return; +} + +/** + * @brief Disable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_DisableInt(void) +{ + /* Do not touch another write 1 clear bits */ + WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); + return; +} + +void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WDT_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/inc/wwdt.h b/bsp/nuvoton_m487/libraries/StdDriver/inc/wwdt.h new file mode 100644 index 00000000000..5212ab2e496 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/inc/wwdt.h @@ -0,0 +1,151 @@ +/**************************************************************************//** + * @file wwdt.h + * @version V3.00 + * @brief M480 series WWDT driver header file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_H__ +#define __WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */ + +/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Clear WWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT time-out reset system flag. + * \hideinitializer + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear WWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT compared match interrupt flag. + * \hideinitializer + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get WWDT Reset System Flag + * + * @param None + * + * @retval 0 WWDT time-out reset system did not occur + * @retval 1 WWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by WWDT time-out reset or not. + * \hideinitializer + */ +#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 WWDT compare match interrupt did not occur + * @retval 1 WWDT compare match interrupt occurred + * + * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not. + * \hideinitializer + */ +#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Counter + * + * @param None + * + * @return WWDT Counter Value + * + * @details This macro reflects the current WWDT counter value. + * \hideinitializer + */ +#define WWDT_GET_COUNTER() (WWDT->CNT) + +/** + * @brief Reload WWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the WWDT counter value to 0x3F. + * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n + * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n + * WWDT reset signal will generate immediately to reset system. + * \hideinitializer + */ +#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD) + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WWDT_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/acmp.c b/bsp/nuvoton_m487/libraries/StdDriver/src/acmp.c new file mode 100644 index 00000000000..65d4d7ab887 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/acmp.c @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file acmp.c + * @version V1.00 + * @brief M480 series Analog Comparator(ACMP) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + + +/** + * @brief Configure the specified ACMP module + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * @param[in] u32NegSrc Comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * + * @return None + * + * @details Configure hysteresis function, select the source of negative input and enable analog comparator. + */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel) +{ + acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk); +} + +/** + * @brief Close analog comparator + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * + * @return None + * + * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + */ +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum) +{ + acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk); +} + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/bpwm.c b/bsp/nuvoton_m487/libraries/StdDriver/src/bpwm.c new file mode 100644 index 00000000000..c8ff0eb3940 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/bpwm.c @@ -0,0 +1,744 @@ +/**************************************************************************//** + * @file bpwm.c + * @version V1.00 + * @brief M480 series BPWM driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + + +/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions + @{ +*/ + +/** + * @brief Configure BPWM capture and get the nearest unit time. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure BPWM capture and get the nearest unit time. + */ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t u32NearestUnitTimeNsec; + uint16_t u16Prescale = 1U, u16CNR = 0xFFFFU; + + if(bpwm == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32PWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(bpwm == BPWM0) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + u32PWMClockSrc /= 1000UL; + for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) + { + uint32_t u32Exit = 0U; + u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32PWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if (u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + if (!(1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))) + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + } + else + { + u32Exit = 1U; + } + if (u32Exit == 1U) + { + break; + } + else {} + } + + /* convert to real register value */ + /* all channels share a prescaler */ + u16Prescale -= 1U; + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u16Prescale); + + /* set BPWM to down count type(edge aligned) */ + (bpwm)->CTL1 = (1UL); + + BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned auto-reload mode + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect + * existing frequency of other channel. + */ +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + if(bpwm == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32PWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(bpwm == BPWM0) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */ + { + i = (u32PWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i < (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */ + i = u32PWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + /* all channels share a prescaler */ + u32Prescale -= 1U; + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale); + /* set BPWM to down count type(edge aligned) */ + (bpwm)->CTL1 = (1UL); + + u32CNR -= 1U; + BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR); + if(u32DutyCycle) + { + BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL - 1UL); + (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTLn_Msk | BPWM_WGCTL0_ZPCTLn_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum * (2U)) + (uint32_t)BPWM_WGCTL0_PRDPCTLn_Pos)); + (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTLn_Msk | BPWM_WGCTL1_CMPUCTLn_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * (2U) + (uint32_t)BPWM_WGCTL1_CMPDCTLn_Pos)); + } + else + { + BPWM_SET_CMR(bpwm, u32ChannelNum, 0U); + (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTLn_Msk | BPWM_WGCTL0_ZPCTLn_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL0_ZPCTLn_Pos)); + (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTLn_Msk | BPWM_WGCTL1_CMPUCTLn_Msk) << (u32ChannelNum * 2U)); + (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << (u32ChannelNum * 2U + (uint32_t)BPWM_WGCTL1_CMPDCTLn_Pos)); + } + + return(i); +} + +/** + * @brief Start BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to start BPWM module. + * @note All channels share one counter. + */ +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Stop BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM module. + * @note All channels share one period. + */ +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->PERIOD = 0U; +} + +/** + * @brief Stop BPWM generation immediately by clear channel enable bit + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM generation immediately by clear channel enable bit. + * @note All channels share one counter. + */ +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable selected channel to trigger ADC + */ +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4U) + { + (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8U)); + (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8U)); + } + else + { + (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) * 8U)); + (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) * 8U)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to disable selected channel to trigger ADC + */ +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4U) + { + (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8U)); + } + else + { + (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) * 8U)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag + */ +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (bpwm)->STATUS = (BPWM_STATUS_EADCTRGn_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel + */ +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRGn_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s) + */ +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN |= u32ChannelMask; + (bpwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s) + */ +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN &= ~u32ChannelMask; + (bpwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enables BPWM output generation of selected channel(s) + */ +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disables BPWM output generation of selected channel(s) + */ +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIFn_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \ + (((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIFn_Msk << u32ChannelNum)) ? 1UL : 0UL)); +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel + */ +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + + (bpwm)->INTEN &= ~((uint32_t)(BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel + */ +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = (BPWM_INTSTS_CMPUIFn_Msk | BPWM_INTSTS_CMPDIFn_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel + */ +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIFn_Msk | BPWM_INTSTS_CMPUIFn_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk; +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to enable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk; +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return zero interrupt flag of specified channel + * @retval 0 zero interrupt did not occur + * @retval 1 zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode PWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Set BPWM clock source + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32ClkSrcSel BPWM external clock source. + * - \ref BPWM_CLKSRC_BPWM_CLK + * - \ref BPWM_CLKSRC_TIMER0 + * - \ref BPWM_CLKSRC_TIMER1 + * - \ref BPWM_CLKSRC_TIMER2 + * - \ref BPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set BPWM clock source. + * @note All channels share channel 0's setting. + */ +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (bpwm)->CLKSRC = (u32ClkSrcSel); +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk; +} + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/can.c b/bsp/nuvoton_m487/libraries/StdDriver/src/can.c new file mode 100644 index 00000000000..7f17879b92d --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/can.c @@ -0,0 +1,1275 @@ +/**************************************************************************//** + * @file can.c + * @version V2.00 + * @brief M480 series CAN driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** @cond HIDDEN_SYMBOLS */ + +#if defined(CAN1) +static uint8_t gu8LockCanIf[2ul][2ul] = {0ul}; /* The chip has two CANs. */ +#elif defined(CAN0) || defined(CAN) +static uint8_t gu8LockCanIf[1ul][2ul] = {0ul}; /* The chip only has one CAN. */ +#endif + +#define RETRY_COUNTS (0x10000000ul) + +#define TSEG1_MIN 2ul +#define TSEG1_MAX 16ul +#define TSEG2_MIN 1ul +#define TSEG2_MAX 8ul +#define BRP_MIN 1ul +#define BRP_MAX 1024ul /* 6-bit BRP field + 4-bit BRPE field*/ +#define SJW_MAX 4ul +#define BRP_INC 1ul + +/* #define DEBUG_PRINTF printf */ +#define DEBUG_PRINTF(...) + +static uint32_t LockIF(CAN_T *tCAN); +static uint32_t LockIF_TL(CAN_T *tCAN); +static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo); +static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2); + +/** + * @brief Check if any interface is available then lock it for usage. + * @param[in] tCAN The pointer to CAN module base address. + * @retval 0 IF0 is free + * @retval 1 IF1 is free + * @retval 2 No IF is free + * @details Search the first free message interface, starting from 0. If a interface is + * available, set a flag to lock the interface. + */ +static uint32_t LockIF(CAN_T *tCAN) +{ + uint32_t u32CanNo; + uint32_t u32FreeIfNo; + uint32_t u32IntMask; + +#if defined(CAN1) + u32CanNo = (tCAN == CAN1) ? 1ul : 0ul; +#else /* defined(CAN0) || defined(CAN) */ + u32CanNo = 0ul; +#endif + + u32FreeIfNo = 2ul; + + /* Disable CAN interrupt */ + u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + + /* Check interface 1 is available or not */ + if((tCAN->IF[0ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) + { + if(gu8LockCanIf[u32CanNo][0ul] == 0ul) + { + gu8LockCanIf[u32CanNo][0ul] = 1u; + u32FreeIfNo = 0ul; + } + else + { + } + } + else + { + } + + /* Or check interface 2 is available or not */ + if(u32FreeIfNo == 2ul) + { + if((tCAN->IF[1ul].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) + { + if(gu8LockCanIf[u32CanNo][1ul] == 0ul) + { + gu8LockCanIf[u32CanNo][1ul] = 1u; + u32FreeIfNo = 1ul; + } + else + { + } + } + else + { + } + } + else + { + } + + /* Enable CAN interrupt */ + tCAN->CON |= u32IntMask; + + return u32FreeIfNo; +} + +/** + * @brief Check if any interface is available in a time limitation then lock it for usage. + * @param[in] tCAN The pointer to CAN module base address. + * @retval 0 IF0 is free + * @retval 1 IF1 is free + * @retval 2 No IF is free + * @details Search the first free message interface, starting from 0. If no interface is + * it will try again until time out. If a interface is available, set a flag to + * lock the interface. + */ +static uint32_t LockIF_TL(CAN_T *tCAN) +{ + uint32_t u32Count; + uint32_t u32FreeIfNo; + + for(u32Count = 0ul; u32Count < RETRY_COUNTS; u32Count++) + { + if((u32FreeIfNo = LockIF(tCAN)) != 2ul) + { + break; + } + else + { + } + } + + return u32FreeIfNo; +} + +/** + * @brief Release locked interface. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Info The interface number, 0 or 1. + * @return none + * @details Release the locked interface. + */ +static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo) +{ + uint32_t u32IntMask; + uint32_t u32CanNo; + + if(u32IfNo >= 2ul) + { + } + else + { +#if defined(CAN1) + u32CanNo = (tCAN == CAN1) ? 1ul : 0ul; +#else /* defined(CAN0) || defined(CAN) */ + u32CanNo = 0ul; +#endif + + /* Disable CAN interrupt */ + u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + + gu8LockCanIf[u32CanNo][u32IfNo] = 0u; + + /* Enable CAN interrupt */ + tCAN->CON |= u32IntMask; + } +} + +static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2) +{ + *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000; + if (*tseg2 < TSEG2_MIN) + { + *tseg2 = TSEG2_MIN; + } + else + { + } + + if (*tseg2 > TSEG2_MAX) + { + *tseg2 = TSEG2_MAX; + } + else + { + } + + *tseg1 = tseg - *tseg2; + if (*tseg1 > TSEG1_MAX) + { + *tseg1 = TSEG1_MAX; + *tseg2 = tseg - *tseg1; + } + else + { + } + + return 1000 * (tseg + 1 - *tseg2) / (tseg + 1); +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Enter initialization mode + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8Mask Following values can be used. + * \ref CAN_CON_DAR_Msk Disable automatic retransmission. + * \ref CAN_CON_EIE_Msk Enable error interrupt. + * \ref CAN_CON_SIE_Msk Enable status interrupt. + * \ref CAN_CON_IE_Msk CAN interrupt. + * @return None + * @details This function is used to set CAN to enter initialization mode and enable access bit timing + * register. After bit timing configuration ready, user must call CAN_LeaveInitMode() + * to leave initialization mode and lock bit timing register to let new configuration + * take effect. + */ +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask) +{ + tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk); +} + + +/** + * @brief Leave initialization mode + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to set CAN to leave initialization mode to let + * bit timing configuration take effect after configuration ready. + */ +void CAN_LeaveInitMode(CAN_T *tCAN) +{ + tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk)); + while(tCAN->CON & CAN_CON_INIT_Msk) + { + /* Check INIT bit is released */ + } +} + +/** + * @brief Wait message into message buffer in basic mode. + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to wait message into message buffer in basic mode. Please notice the + * function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode. + */ +void CAN_WaitMsg(CAN_T *tCAN) +{ + tCAN->STATUS = 0x0ul; /* clr status */ + + while(1) + { + if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) /* check new data */ + { + /* New Data IN */ + break; + } + else + { + } + + if(tCAN->STATUS & CAN_STATUS_RXOK_Msk) + { + /* Rx OK */ + } + else + { + } + + if(tCAN->STATUS & CAN_STATUS_LEC_Msk) + { + /* Error */ + } + else + { + } + } +} + +/** + * @brief Get current bit rate + * @param[in] tCAN The pointer to CAN module base address. + * @return Current Bit-Rate (kilo bit per second) + * @details Return current CAN bit rate according to the user bit-timing parameter settings + */ +uint32_t CAN_GetCANBitRate(CAN_T *tCAN) +{ + uint32_t u32Tseg1, u32Tseg2; + uint32_t u32Bpr; + + u32Tseg1 = (tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos; + u32Tseg2 = (tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos; + u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk) | (tCAN->BRPE << 6ul); + + return (SystemCoreClock / (u32Bpr + 1ul) / (u32Tseg1 + u32Tseg2 + 3ul)); +} + +/** + * @brief Switch the CAN into test mode. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8TestMask Specifies the configuration in test modes + * \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode + * \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode + * \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode + * \ref CAN_TEST_Tx_Msk Control CAN_TX pin bit field + * @return None + * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/ + * LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user + * must call CAN_LeaveInitMode() to let the setting take effect. + */ +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask) +{ + tCAN->CON |= CAN_CON_TEST_Msk; + tCAN->TEST = u8TestMask; +} + + +/** + * @brief Leave the test mode + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to Leave the test mode (switch into normal mode). + */ +void CAN_LeaveTestMode(CAN_T *tCAN) +{ + tCAN->CON |= CAN_CON_TEST_Msk; + tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk); + tCAN->CON &= (~CAN_CON_TEST_Msk); +} + +/** + * @brief Get the waiting status of a received message. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @retval non-zero The corresponding message object has a new data bit is set. + * @retval 0 No message object has new data. + * @details This function is used to get the waiting status of a received message. + */ +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj) +{ + return (u8MsgObj < 16ul ? tCAN->NDAT1 & (1ul << u8MsgObj) : tCAN->NDAT2 & (1ul << (u8MsgObj - 16ul))); +} + + +/** + * @brief Send CAN message in BASIC mode of test mode + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] pCanMsg Pointer to the message structure containing data to transmit. + * @return TRUE: Transmission OK + * FALSE: Check busy flag of interface 0 is timeout + * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API, + * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter + * basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode. + */ +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg) +{ + uint32_t i = 0ul; + int32_t rev = 1l; + + while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + } + + tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk); + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + tCAN->IF[0].ARB1 = 0ul; + tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2ul) ; + } + else + { + /* extended ID*/ + tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFFul; + tCAN->IF[0].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16ul | CAN_IF_ARB2_XTD_Msk; + + } + + if(pCanMsg->FrameType) + { + tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk; + } + else + { + tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk); + } + + tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC; + tCAN->IF[0].DAT_A1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]); + tCAN->IF[0].DAT_A2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]); + tCAN->IF[0].DAT_B1 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]); + tCAN->IF[0].DAT_B2 = (uint16_t)((uint16_t)((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]); + + /* request transmission*/ + tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk); + if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /* Cannot clear busy for sending ...*/ + rev = 0l; /* return FALSE */ + } + else + { + tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; /* sending */ + + for(i = 0ul; i < 0xFFFFFul; i++) + { + if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0ul) + { + break; + } + else + { + } + } + + if(i >= 0xFFFFFul) + { + /* Cannot send out... */ + rev = 0l; /* return FALSE */ + } + else + { + } + } + + return rev; +} + +/** + * @brief Get a message information in BASIC mode. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @return FALSE No any message received. + * TRUE Receive a message success. + * + */ +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = 1l; + + if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0ul) + { + /* In basic mode, receive data always save in IF2 */ + rev = 0; /* return FALSE */ + } + else + { + + tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk); + + tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FFul; + + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (tCAN->IF[1].ARB2 & 0x1FFFul) << 16; + pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1; + } + + pCanMsg->FrameType = (((tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) >> CAN_IF_ARB2_DIR_Pos)) ? 0ul : 1ul; + + pCanMsg->DLC = (uint8_t)(tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk); + pCanMsg->Data[0] = (uint8_t)(tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk); + pCanMsg->Data[1] = (uint8_t)((tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos); + pCanMsg->Data[2] = (uint8_t)(tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk); + pCanMsg->Data[3] = (uint8_t)((tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos); + pCanMsg->Data[4] = (uint8_t)(tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk); + pCanMsg->Data[5] = (uint8_t)((tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos); + pCanMsg->Data[6] = (uint8_t)(tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk); + pCanMsg->Data[7] = (uint8_t)((tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos); + } + + return rev; +} + +/** + * @brief Set Rx message object, include ID mask. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted + * This parameter can be one of the following values: + * \ref CAN_STD_ID (standard ID, 11-bit) + * \ref CAN_EXT_ID (extended ID, 29-bit) + * @param[in] u32id Specifies the identifier used for acceptance filtering. + * @param[in] u32idmask Specifies the identifier mask used for acceptance filtering. + * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator. + * This parameter can be one of the following values: + * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO. + * FALSE: for a FIFO receive object that is not the last one. + * @retval TRUE SUCCESS + * @retval FALSE No useful interface + * @details The function is used to configure a receive message object. + */ +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + /* Get and lock a free interface */ + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + /* Command Setting */ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + tCAN->IF[u32MsgIfNum].ARB1 = 0ul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2; + } + else + { + tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16; + } + + tCAN->IF[u32MsgIfNum].MASK1 = (u32idmask & 0xFFFFul); + tCAN->IF[u32MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFFul; + + /* tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */ + tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; + if(u8singleOrFifoLast) + { + tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk; + } + else + { + tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk); + } + + tCAN->IF[u32MsgIfNum].DAT_A1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_A2 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B2 = 0ul; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj; + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Set Rx message object + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted + * This parameter can be one of the following values: + * \ref CAN_STD_ID (standard ID, 11-bit) + * \ref CAN_EXT_ID (extended ID, 29-bit) + * @param[in] u32id Specifies the identifier used for acceptance filtering. + * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator. + * This parameter can be one of the following values: + * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO. + * FALSE: for a FIFO receive object that is not the last one. + * @retval TRUE SUCCESS + * @retval FALSE No useful interface + * @details The function is used to configure a receive message object. + */ +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + /* Get and lock a free interface */ + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + /* Command Setting */ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + tCAN->IF[u32MsgIfNum].ARB1 = 0ul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFul) << 2; + } + else + { + tCAN->IF[u32MsgIfNum].ARB1 = u32id & 0xFFFFul; + tCAN->IF[u32MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000ul) >> 16; + } + + /* tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; */ + tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; + if(u8singleOrFifoLast) + { + tCAN->IF[u32MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk; + } + else + { + tCAN->IF[u32MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk); + } + + tCAN->IF[u32MsgIfNum].DAT_A1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_A2 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B1 = 0ul; + tCAN->IF[u32MsgIfNum].DAT_B2 = 0ul; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj; + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Gets the message + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8Release Specifies the message release indicator. + * This parameter can be one of the following values: + * TRUE: the message object is released when getting the data. + * FALSE:the message object is not released. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * @retval TRUE Success + * @retval FALSE No any message received + * @details Gets the message, if received. + */ +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + if(!CAN_IsNewDataReceived(tCAN, u8MsgObj)) + { + rev = 0; /* return FALSE */ + } + else + { + /* Get and lock a free interface */ + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk); + + /* read the message contents*/ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk + | CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_CLRINTPND_Msk + | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0ul) + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u8MsgObj; + + while(tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + + if((tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0ul) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (tCAN->IF[u32MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2ul; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (((tCAN->IF[u32MsgIfNum].ARB2) & 0x1FFFul) << 16) | tCAN->IF[u32MsgIfNum].ARB1; + } + + pCanMsg->DLC = (uint8_t)(tCAN->IF[u32MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk); + pCanMsg->Data[0] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk); + pCanMsg->Data[1] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos); + pCanMsg->Data[2] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk); + pCanMsg->Data[3] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos); + pCanMsg->Data[4] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk); + pCanMsg->Data[5] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos); + pCanMsg->Data[6] = (uint8_t)(tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk); + pCanMsg->Data[7] = (uint8_t)((tCAN->IF[u32MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos); + + ReleaseIF(tCAN, u32MsgIfNum); + } + } + + return rev; +} + + +/** + * @brief Set bus baud-rate. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * + * @return u32CurrentBitRate Real baud-rate value. + * + * @details The function is used to set bus timing parameter according current clock and target baud-rate. + */ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate) +{ + long rate; + long best_error = 1000000000, error = 0; + int best_tseg = 0, best_brp = 0, brp = 0; + int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0; + int spt_error = 1000, spt = 0, sampl_pt; + uint64_t clock_freq = (uint64_t)0, u64PCLK_DIV = (uint64_t)1; + uint32_t sjw = (uint32_t)1; + + CAN_EnterInitMode(tCAN, (uint8_t)0); + + SystemCoreClockUpdate(); + if(tCAN == CAN0) + { + u64PCLK_DIV = (uint64_t)(CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk); + u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV); + } + else if(tCAN == CAN1) + { + u64PCLK_DIV = (uint64_t)((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) >> CLK_PCLKDIV_APB1DIV_Pos); + u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV); + } + + clock_freq = SystemCoreClock / u64PCLK_DIV; + + if(u32BaudRate >= (uint32_t)1000000) + { + u32BaudRate = (uint32_t)1000000; + } + + /* Use CIA recommended sample points */ + if (u32BaudRate > (uint32_t)800000) + { + sampl_pt = (int)750; + } + else if (u32BaudRate > (uint32_t)500000) + { + sampl_pt = (int)800; + } + else + { + sampl_pt = (int)875; + } + + /* tseg even = round down, odd = round up */ + for (tseg = (TSEG1_MAX + TSEG2_MAX) * 2ul + 1ul; tseg >= (TSEG1_MIN + TSEG2_MIN) * 2ul; tseg--) + { + tsegall = 1ul + tseg / 2ul; + /* Compute all possible tseg choices (tseg=tseg1+tseg2) */ + brp = clock_freq / (tsegall * u32BaudRate) + tseg % 2; + /* chose brp step which is possible in system */ + brp = (brp / BRP_INC) * BRP_INC; + + if ((brp < BRP_MIN) || (brp > BRP_MAX)) + { + continue; + } + rate = clock_freq / (brp * tsegall); + + error = u32BaudRate - rate; + + /* tseg brp biterror */ + if (error < 0) + { + error = -error; + } + if (error > best_error) + { + continue; + } + best_error = error; + if (error == 0) + { + spt = can_update_spt(sampl_pt, tseg / 2, &tseg1, &tseg2); + error = sampl_pt - spt; + if (error < 0) + { + error = -error; + } + if (error > spt_error) + { + continue; + } + spt_error = error; + } + best_tseg = tseg / 2; + best_brp = brp; + + if (error == 0) + { + break; + } + } + + spt = can_update_spt(sampl_pt, best_tseg, &tseg1, &tseg2); + + /* check for sjw user settings */ + /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */ + if (sjw > SJW_MAX) + { + sjw = SJW_MAX; + } + /* bt->sjw must not be higher than tseg2 */ + if (tseg2 < sjw) + { + sjw = tseg2; + } + + /* real bit-rate */ + u32BaudRate = clock_freq / (best_brp * (tseg1 + tseg2 + 1)); + + tCAN->BTIME = ((uint32_t)(tseg2 - 1ul) << CAN_BTIME_TSEG2_Pos) | ((uint32_t)(tseg1 - 1ul) << CAN_BTIME_TSEG1_Pos) | + ((uint32_t)(best_brp - 1ul) & CAN_BTIME_BRP_Msk) | (sjw << CAN_BTIME_SJW_Pos); + tCAN->BRPE = ((uint32_t)(best_brp - 1ul) >> 6) & 0x0Ful; + + /* printf("\n bitrate = %d \n", CAN_GetCANBitRate(tCAN)); */ + + CAN_LeaveInitMode(tCAN); + + return u32BaudRate; +} + +/** + * @brief The function is used to disable all CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * + * @return None + * + * @details No Status Change Interrupt and Error Status Interrupt will be generated. + */ +void CAN_Close(CAN_T *tCAN) +{ + CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)); +} + +/** + * @brief Set CAN operation mode and target baud-rate. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * @param[in] u32Mode The CAN operation mode. Valid values are: + * - \ref CAN_NORMAL_MODE Normal operation. + * - \ref CAN_BASIC_MODE Basic mode. + * @return u32CurrentBitRate Real baud-rate value. + * + * @details Set bus timing parameter according current clock and target baud-rate. + * In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. + */ +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode) +{ + uint32_t u32CurrentBitRate; + + u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate); + + if(u32Mode == CAN_BASIC_MODE) + { + CAN_EnterTestMode(tCAN, (uint8_t)CAN_TEST_BASIC_Msk); + } + else + { + } + + return u32CurrentBitRate; +} + +/** + * @brief The function is used to configure a transmit object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE No useful interface. + * @retval TRUE Config message object success. + * + * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM. + * They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission. + */ +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + /* update the contents needed for transmission*/ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + tCAN->IF[u32MsgIfNum].ARB1 = 0ul; + tCAN->IF[u32MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FFul) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk; + } + else + { + /* extended ID*/ + tCAN->IF[u32MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFFul; + tCAN->IF[u32MsgIfNum].ARB2 = ((pCanMsg->Id) & 0x1FFF0000ul) >> 16 | + CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk; + } + + if(pCanMsg->FrameType) + { + tCAN->IF[u32MsgIfNum].ARB2 |= CAN_IF_ARB2_DIR_Msk; + } + else + { + tCAN->IF[u32MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk); + } + + tCAN->IF[u32MsgIfNum].DAT_A1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[1] << 8)) | pCanMsg->Data[0]); + tCAN->IF[u32MsgIfNum].DAT_A2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[3] << 8)) | pCanMsg->Data[2]); + tCAN->IF[u32MsgIfNum].DAT_B1 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[5] << 8)) | pCanMsg->Data[4]); + tCAN->IF[u32MsgIfNum].DAT_B2 = (uint16_t)((uint16_t)(((uint16_t)pCanMsg->Data[7] << 8)) | pCanMsg->Data[6]); + + tCAN->IF[u32MsgIfNum].MCON = CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Set transmit request bit. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * + * @return TRUE: Start transmit message. + * + * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored. + */ +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum) +{ + int32_t rev = 1l; + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + rev = 0; /* return FALSE */ + } + else + { + tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk); + + /* read the message contents*/ + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk + | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + while(tCAN->IF[u32MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); + } + + return rev; +} + +/** + * @brief Enable CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Mask Interrupt Mask. Valid values are: + * - \ref CAN_CON_IE_Msk Module interrupt enable. + * - \ref CAN_CON_SIE_Msk Status change interrupt enable. + * - \ref CAN_CON_EIE_Msk Error interrupt enable. + * + * @return None + * + * @details The application software has two possibilities to follow the source of a message interrupt. + * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register. + */ +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask) +{ + tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) | + (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)); +} + +/** + * @brief Disable CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk). + * + * @return None + * + * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset. + */ +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask) +{ + tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk))); +} + + +/** + * @brief The function is used to configure a receive message object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure a receive message object success. + * + * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13]) + * will be set when a received Data Frame is accepted and stored in the Message Object. + */ +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32TimeOutCount = 0ul; + + while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)TRUE) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + rev = (int32_t)(FALSE); /* return FALSE */ + break; + } + else + { + } + } + + return rev; +} + +/** + * @brief The function is used to configure a receive message object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure a receive message object success. + * + * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13]) + * will be set when a received Data Frame is accepted and stored in the Message Object. + */ +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32TimeOutCount = 0ul; + + while(CAN_SetRxMsgObjAndMsk(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, u32IDMask, (uint8_t)TRUE) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + rev = (int32_t)FALSE; + break; + } + else + { + } + } + + return rev; +} + +/** + * @brief The function is used to configure several receive message objects. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31). + * @param[in] u32MsgCount the number of MSG RAM of the FIFO. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure receive message objects success. + * + * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception + * and transmission by buffering the data to be transferred. + */ +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID) +{ + int32_t rev = (int32_t)TRUE; + uint32_t i = 0ul; + uint32_t u32TimeOutCount; + uint32_t u32EOB_Flag = 0ul; + + for(i = 1ul; i < u32MsgCount; i++) + { + u32TimeOutCount = 0ul; + + u32MsgNum += (i - 1ul); + + if(i == u32MsgCount) + { + u32EOB_Flag = 1ul; + } + else + { + } + + while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)u32EOB_Flag) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + rev = (int32_t)FALSE; + break; + } + else + { + } + } + } + + return rev; +} + + +/** + * @brief Send CAN message. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n + * 2. When operation in normal mode: No useful interface. \n + * @retval TRUE Transmit Message success. + * + * @details The receive/transmit priority for the Message Objects is attached to the message number. + * Message Object 1 has the highest priority, while Message Object 32 has the lowest priority. + */ +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32Tmp; + + u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk); + + if((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp) + { + rev = CAN_BasicSendMsg(tCAN, pCanMsg); + } + else + { + if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == FALSE) + { + rev = (int32_t)FALSE; + } + else + { + CAN_TriggerTxMsg(tCAN, u32MsgNum); + } + } + + return rev; +} + + +/** + * @brief Gets the message, if received. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE No any message received. + * @retval TRUE Receive Message success. + * + * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception + * and transmission by buffering the data to be transferred. + */ +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + int32_t rev = (int32_t)TRUE; + uint32_t u32Tmp; + + u32Tmp = (tCAN->TEST & CAN_TEST_BASIC_Msk); + + if((tCAN->CON & CAN_CON_TEST_Msk) && u32Tmp) + { + rev = CAN_BasicReceiveMsg(tCAN, pCanMsg); + } + else + { + rev = CAN_ReadMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)TRUE, pCanMsg); + } + + return rev; +} + +/** + * @brief Clear interrupt pending bit. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * + * @return None + * + * @details An interrupt remains pending until the application software has cleared it. + */ +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum) +{ + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2ul) + { + u32MsgIfNum = 0ul; + } + else + { + } + + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1ul + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); +} + + +/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CAN_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/clk.c b/bsp/nuvoton_m487/libraries/StdDriver/src/clk.c new file mode 100644 index 00000000000..657cdefc941 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/clk.c @@ -0,0 +1,1232 @@ +/**************************************************************************//** + * @file clk.c + * @version V3.00 + * @brief M480 series CLK driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Disable clock divider output function + * @param None + * @return None + * @details This function disable clock divider output function. + */ +void CLK_DisableCKO(void) +{ + /* Disable CKO clock source */ + CLK_DisableModuleClock(CLKO_MODULE); +} + +/** + * @brief This function enable clock divider output module clock, + * enable clock divider output function and set frequency selection. + * @param[in] u32ClkSrc is frequency divider function clock source. Including : + * - \ref CLK_CLKSEL1_CLKOSEL_HXT + * - \ref CLK_CLKSEL1_CLKOSEL_LXT + * - \ref CLK_CLKSEL1_CLKOSEL_HCLK + * - \ref CLK_CLKSEL1_CLKOSEL_HIRC + * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15. + * @param[in] u32ClkDivBy1En is clock divided by one enabled. + * @return None + * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n + * The formula is: \n + * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n + * This function is just used to set CKO clock. + * User must enable I/O for CKO clock output pin by themselves. \n + */ +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) +{ + /* CKO = clock source / 2^(u32ClkDiv + 1) */ + CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); + + /* Enable CKO clock source */ + CLK_EnableModuleClock(CLKO_MODULE); + + /* Select CKO clock source */ + CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0UL); +} + +/** + * @brief Enter to Power-down mode + * @param None + * @return None + * @details This function is used to let system enter to Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_PowerDown(void) +{ + /* Set the processor uses deep sleep as its low power mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Set system Power-down enabled and Power-down entry condition */ + CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk; + + /* Chip enter Power-down mode after CPU run WFI instruction */ + __WFI(); +} + +/** + * @brief Enter to Idle mode + * @param None + * @return None + * @details This function let system enter to Idle mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_Idle(void) +{ + /* Set the processor uses sleep as its low power mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* Set chip in idle mode because of WFI command */ + CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; + + /* Chip enter idle mode after CPU run WFI instruction */ + __WFI(); +} + +/** + * @brief Get external high speed crystal clock frequency + * @param None + * @return External high frequency crystal frequency + * @details This function get external high frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHXTFreq(void) +{ + uint32_t u32Freq; + + if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) + { + u32Freq = __HXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + + +/** + * @brief Get external low speed crystal clock frequency + * @param None + * @return External low speed crystal clock frequency + * @details This function get external low frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetLXTFreq(void) +{ + uint32_t u32Freq; + if((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk) + { + u32Freq = __LXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + +/** + * @brief Get PCLK0 frequency + * @param None + * @return PCLK0 frequency + * @details This function get PCLK0 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLK0Freq(void) +{ + uint32_t u32Freq; + SystemCoreClockUpdate(); + +#if(1) + if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV2) + { + u32Freq = SystemCoreClock / 2UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV4) + { + u32Freq = SystemCoreClock / 4UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV8) + { + u32Freq = SystemCoreClock / 8UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV16) + { + u32Freq = SystemCoreClock / 16UL; + } + else + { + u32Freq = SystemCoreClock; + } + + +#else + if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0DIV2) + { + u32Freq = SystemCoreClock / 2UL; + } + else + { + u32Freq = SystemCoreClock; + } +#endif + + return u32Freq; +} + + +/** + * @brief Get PCLK1 frequency + * @param None + * @return PCLK1 frequency + * @details This function get PCLK1 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLK1Freq(void) +{ + uint32_t u32Freq; + SystemCoreClockUpdate(); + +#if(1) + if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV2) + { + u32Freq = SystemCoreClock / 2UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV4) + { + u32Freq = SystemCoreClock / 4UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV8) + { + u32Freq = SystemCoreClock / 8UL; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV16) + { + u32Freq = SystemCoreClock / 16UL; + } + else + { + u32Freq = SystemCoreClock; + } + + +#else + if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1DIV2) + { + u32Freq = SystemCoreClock / 2UL; + } + else + { + u32Freq = SystemCoreClock; + } +#endif + + return u32Freq; +} + + +/** + * @brief Get HCLK frequency + * @param None + * @return HCLK frequency + * @details This function get HCLK frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHCLKFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + + +/** + * @brief Get CPU frequency + * @param None + * @return CPU frequency + * @details This function get CPU frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetCPUFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + + +/** + * @brief Set HCLK frequency + * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is running up to 192MHz. + * @return HCLK frequency + * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_SetCoreClock(uint32_t u32Hclk) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* The range of u32Hclk is running up to 192 MHz */ + if(u32Hclk > FREQ_192MHZ) + { + u32Hclk = FREQ_192MHZ; + } + + /* Switch HCLK clock source to HIRC clock for safe */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk; + CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk); + + /* Configure PLL setting if HXT clock is enabled */ + if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk); + } + /* Configure PLL setting if HXT clock is not enabled */ + else + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk); + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + } + + /* Select HCLK clock source to PLL, + and update system core clock + */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL)); + + /* Disable HIRC if HIRC is disabled before setting core clock */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } + + /* Return actually HCLK frequency is PLL frequency divide 1 */ + return u32Hclk; +} + +/** + * @brief This function set HCLK clock source and HCLK clock divider + * @param[in] u32ClkSrc is HCLK clock source. Including : + * - \ref CLK_CLKSEL0_HCLKSEL_HXT + * - \ref CLK_CLKSEL0_HCLKSEL_LXT + * - \ref CLK_CLKSEL0_HCLKSEL_PLL + * - \ref CLK_CLKSEL0_HCLKSEL_LIRC + * - \ref CLK_CLKSEL0_HCLKSEL_HIRC + * @param[in] u32ClkDiv is HCLK clock divider. Including : + * - \ref CLK_CLKDIV0_HCLK(x) + * @return None + * @details This function set HCLK clock source and HCLK clock divider. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC; + + /* Apply new Divider */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; + + /* Switch HCLK to new HCLK source */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc; + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /* Disable HIRC if HIRC is disabled before switching HCLK source */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } +} + +/** + * @brief This function set selected module clock source and module clock divider + * @param[in] u32ModuleIdx is module index. + * @param[in] u32ClkSrc is module clock source. + * @param[in] u32ClkDiv is module clock divider. + * @return None + * @details Valid parameter combinations listed in following table: + * + * |Module index |Clock source |Divider | + * | :---------------- | :----------------------------------- | :-------------------------- | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HXT |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_PLL |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HIRC |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HCLK |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x | + * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PLL | x | + * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PCLK0 | x | + * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PLL | x | + * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PCLK1 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x | + * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PLL | x | + * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0 | x | + * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PLL | x | + * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1 | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK1 | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HXT | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) | + * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x | + * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) | + * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) | + * |\ref EMAC_MODULE | x |\ref CLK_CLKDIV3_EMAC(x) | + * + */ +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32sel = 0U, u32div = 0U; + + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + if(MODULE_CLKDIV(u32ModuleIdx) == 2U) + { + u32div = (uint32_t)&CLK->CLKDIV3; + } + else if (MODULE_CLKDIV(u32ModuleIdx) == 3U) + { + u32div = (uint32_t)&CLK->CLKDIV4; + } + else + { + u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U); + } + + /* Apply new divider */ + M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; + } + + if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4U); + /* Set new clock selection setting */ + M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; + } +} + +/** + * @brief Set SysTick clock source + * @param[in] u32ClkSrc is module clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * @return None + * @details This function set SysTick clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) +{ + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; + +} + +/** + * @brief Enable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * @return None + * @details This function enable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL |= u32ClkMask; +} + +/** + * @brief Disable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * @return None + * @details This function disable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL &= ~u32ClkMask; +} + +/** + * @brief Enable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref EMAC_MODULE + * - \ref SDH0_MODULE + * - \ref CRC_MODULE + * - \ref HSUSBD_MODULE + * - \ref CRPT_MODULE + * - \ref SPIM_MODULE + * - \ref USBH_MODULE + * - \ref SDH1_MODULE + * - \ref WDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref WWDT_MODULE + * - \ref ACMP01_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref CAN0_MODULE + * - \ref CAN1_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref EADC_MODULE + * - \ref I2S0_MODULE + * - \ref HSOTG_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref SPI3_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref DAC_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref OPA_MODULE + * @return None + * @details This function is used to enable module clock. + */ +void CLK_EnableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32tmpAddr = (uint32_t)&CLK->AHBCLK; + u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(volatile uint32_t *)u32tmpAddr |= u32tmpVal; +} + +/** + * @brief Disable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref EMAC_MODULE + * - \ref SDH0_MODULE + * - \ref CRC_MODULE + * - \ref HSUSBD_MODULE + * - \ref CRPT_MODULE + * - \ref SPIM_MODULE + * - \ref USBH_MODULE + * - \ref SDH1_MODULE + * - \ref WDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref WWDT_MODULE + * - \ref ACMP01_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref CAN0_MODULE + * - \ref CAN1_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref EADC_MODULE + * - \ref I2S0_MODULE + * - \ref HSOTG_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref SPI3_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref DAC_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref OPA_MODULE + * @return None + * @details This function is used to disable module clock. + */ +void CLK_DisableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32tmpAddr = (uint32_t)&CLK->AHBCLK; + u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(uint32_t *)u32tmpAddr &= u32tmpVal; +} + + +/** + * @brief Set PLL frequency + * @param[in] u32PllClkSrc is PLL clock source. Including : + * - \ref CLK_PLLCTL_PLLSRC_HXT + * - \ref CLK_PLLCTL_PLLSRC_HIRC + * @param[in] u32PllFreq is PLL frequency. + * @return PLL frequency + * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) +{ + uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32PllClk; + uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32basFreq; + + /* Disable PLL first to avoid unstable when setting PLL */ + CLK_DisablePLL(); + + /* PLL source clock is from HXT */ + if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + { + /* Enable HXT clock */ + CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; + + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + + /* Select PLL source clock from HXT */ + u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT; + u32PllSrcClk = __HXT; + + /* u32NR start from 2 */ + u32NR = 2UL; + } + + /* PLL source clock is from HIRC */ + else + { + /* Enable HIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Select PLL source clock from HIRC */ + u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC; + u32PllSrcClk = __HIRC; + + /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */ + u32NR = 4UL; + } + + if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ)) + { + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinNR = 0UL; + u32MinNF = 0UL; + u32MinNO = 0UL; + u32basFreq = u32PllFreq; + + for(u32NO = 1UL; u32NO <= 4UL; u32NO++) + { + /* Break when get good results */ + if (u32Min == 0UL) + { + break; + } + + if (u32NO != 3UL) + { + + if(u32NO == 4UL) + { + u32PllFreq = u32basFreq << 2; + } + else if(u32NO == 2UL) + { + u32PllFreq = u32basFreq << 1; + } + else + { + } + + for(u32NR = 2UL; u32NR <= 32UL; u32NR++) + { + /* Break when get good results */ + if (u32Min == 0UL) + { + break; + } + + u32Tmp = u32PllSrcClk / u32NR; + if((u32Tmp >= 4000000UL) && (u32Tmp <= 8000000UL)) + { + for(u32NF = 2UL; u32NF <= 513UL; u32NF++) + { + /* u32Tmp2 is shifted 2 bits to avoid overflow */ + u32Tmp2 = (((u32Tmp * 2UL) >> 2) * u32NF); + + if((u32Tmp2 >= FREQ_50MHZ) && (u32Tmp2 <= FREQ_125MHZ)) + { + u32Tmp3 = (u32Tmp2 > (u32PllFreq>>2)) ? u32Tmp2 - (u32PllFreq>>2) : (u32PllFreq>>2) - u32Tmp2; + if(u32Tmp3 < u32Min) + { + u32Min = u32Tmp3; + u32MinNR = u32NR; + u32MinNF = u32NF; + u32MinNO = u32NO; + + /* Break when get good results */ + if(u32Min == 0UL) + { + break; + } + } + } + } + } + } + } + } + + /* Enable and apply new PLL setting. */ + CLK->PLLCTL = u32CLK_SRC | ((u32MinNO - 1UL) << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL); + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* Actual PLL output clock frequency */ + u32PllClk = u32PllSrcClk / (u32MinNO * (u32MinNR)) * (u32MinNF) * 2UL; + } + else + { + /* Wrong frequency request. Just return default setting. */ + /* Apply default PLL setting and return */ + if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + { + CLK->PLLCTL = CLK_PLLCTL_192MHz_HXT; + } + else + { + CLK->PLLCTL = CLK_PLLCTL_192MHz_HIRC; + } + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* Actual PLL output clock frequency */ + u32PllClk = CLK_GetPLLClockFreq(); + } + + return u32PllClk; +} + +/** + * @brief Disable PLL + * @param None + * @return None + * @details This function set PLL in Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisablePLL(void) +{ + CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; +} + + +/** + * @brief This function check selected clock source status + * @param[in] u32ClkMask is selected clock source. Including : + * - \ref CLK_STATUS_HXTSTB_Msk + * - \ref CLK_STATUS_LXTSTB_Msk + * - \ref CLK_STATUS_HIRCSTB_Msk + * - \ref CLK_STATUS_LIRCSTB_Msk + * - \ref CLK_STATUS_PLLSTB_Msk + * @retval 0 clock is not stable + * @retval 1 clock is stable + * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms) + */ +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) +{ + int32_t i32TimeOutCnt = 2160000; + uint32_t u32Ret = 1U; + + while((CLK->STATUS & u32ClkMask) != u32ClkMask) + { + if(i32TimeOutCnt-- <= 0) + { + u32Ret = 0U; + break; + } + } + return u32Ret; +} + +/** + * @brief Enable System Tick counter + * @param[in] u32ClkSrc is System Tick clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK + * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. + * @return None + * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; + + /* Set System Tick clock source */ + if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK ) + { + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + } + else + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; + } + + /* Set System Tick reload value */ + SysTick->LOAD = u32Count; + + /* Clear System Tick current value and counter flag */ + SysTick->VAL = 0UL; + + /* Set System Tick interrupt enabled and counter enabled */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Disable System Tick counter + * @param None + * @return None + * @details This function disable System Tick counter. + */ +void CLK_DisableSysTick(void) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; +} + + +/** + * @brief Power-down mode selected + * @param[in] u32PDMode is power down mode index. Including : + * - \ref CLK_PMUCTL_PDMSEL_PD + * - \ref CLK_PMUCTL_PDMSEL_LLPD + * - \ref CLK_PMUCTL_PDMSEL_FWPD + * - \ref CLK_PMUCTL_PDMSEL_SPD0 + * - \ref CLK_PMUCTL_PDMSEL_SPD1 + * - \ref CLK_PMUCTL_PDMSEL_DPD + * @return None + * @details This function is used to set power-down mode. + * @note Must enable LIRC clock before entering to Standby Power-down Mode + */ + +void CLK_SetPowerDownMode(uint32_t u32PDMode) +{ + /* Enable LIRC clock before entering to Standby Power-down Mode */ + if((u32PDMode == CLK_PMUCTL_PDMSEL_SPD0) || (u32PDMode == CLK_PMUCTL_PDMSEL_SPD1)) + { + /* Enable LIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk; + + /* Wait for LIRC clock stable */ + CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); + } + + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode; +} + +/** + * @brief Set Wake-up pin trigger type at Deep Power down mode + * + * @param[in] u32TriggerType + * - \ref CLK_DPDWKPIN_RISING + * - \ref CLK_DPDWKPIN_FALLING + * - \ref CLK_DPDWKPIN_BOTHEDGE + * @return None + * + * @details This function is used to enable Wake-up pin trigger type. + */ + +void CLK_EnableDPDWKPin(uint32_t u32TriggerType) +{ + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType; +} + +/** + * @brief Get power manager wake up source + * + * @param[in] None + * @return None + * + * @details This function get power manager wake up source. + */ + +uint32_t CLK_GetPMUWKSrc(void) +{ + return (CLK->PMUSTS); +} + +/** + * @brief Set specified GPIO as wake up source at Stand-by Power down mode + * + * @param[in] u32Port GPIO port. It could be 0~3. + * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32TriggerType + * - \ref CLK_SPDWKPIN_RISING + * - \ref CLK_SPDWKPIN_FALLING + * @param[in] u32DebounceEn + * - \ref CLK_SPDWKPIN_DEBOUNCEEN + * - \ref CLK_SPDWKPIN_DEBOUNCEDIS + * @return None + * + * @details This function is used to set specified GPIO as wake up source + * at Stand-by Power down mode. + */ +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn) +{ + uint32_t u32tmpAddr = 0UL; + uint32_t u32tmpVal = 0UL; + + /* GPx Stand-by Power-down Wake-up Pin Select */ + u32tmpAddr = (uint32_t)&CLK->PASWKCTL; + u32tmpAddr += (0x4UL * u32Port); + + u32tmpVal = inpw((uint32_t *)u32tmpAddr); + u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) | + (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE; + outpw((uint32_t *)u32tmpAddr, u32tmpVal); +} + +/** + * @brief Get PLL clock frequency + * @param None + * @return PLL frequency + * @details This function get PLL frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPLLClockFreq(void) +{ + uint32_t u32PllFreq = 0UL, u32PllReg; + uint32_t u32FIN, u32NF, u32NR, u32NO; + uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U}; + + u32PllReg = CLK->PLLCTL; + + if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) + { + u32PllFreq = 0UL; /* PLL is in power down mode or fix low */ + } + else if((u32PllReg & CLK_PLLCTL_BP_Msk) == CLK_PLLCTL_BP_Msk) + { + if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + + u32PllFreq = u32FIN; + } + else + { + if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + /* PLL is output enabled in normal work mode */ + u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)]; + u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; + u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL; + + /* u32FIN is shifted 2 bits to avoid overflow */ + u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2) * 2UL; + } + + return u32PllFreq; +} + +/** + * @brief Get selected module clock source + * @param[in] u32ModuleIdx is module index. + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref WDT_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref CLKO_MODULE + * - \ref WWDT_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref RTC_MODULE + * - \ref I2S0_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * @return Selected module clock source setting + * @details This function get selected module clock source. + */ +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx) +{ + uint32_t u32sel = 0; + uint32_t u32SelTbl[4] = {0x0, 0x4, 0x8, 0xC}; + + /* Get clock source selection setting */ + if(u32ModuleIdx == EPWM0_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos); + else if(u32ModuleIdx == EPWM1_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos); + else if(u32ModuleIdx == BPWM0_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos); + else if(u32ModuleIdx == BPWM1_MODULE) + return ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos); + else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + /* Get clock source selection setting */ + return ((M32(u32sel) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx)); + } + else + return 0; +} + +/** + * @brief Get selected module clock divider number + * @param[in] u32ModuleIdx is module index. + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref EADC_MODULE + * - \ref SDH0_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref EMAC_MODULE + * - \ref SDH1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * @return Selected module clock divider number setting + * @details This function get selected module clock divider number. + */ +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx) +{ + uint32_t u32div = 0; + uint32_t u32DivTbl[4] = {0x0, 0x4, 0x8, 0x10}; + + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Get clock divider number setting */ + return ((M32(u32div) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx)); + } + else + return 0; +} + + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/crc.c b/bsp/nuvoton_m487/libraries/StdDriver/src/crc.c new file mode 100644 index 00000000000..900ed3ba1e6 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/crc.c @@ -0,0 +1,94 @@ +/**************************************************************************//** + * @file crc.c + * @version V1.00 + * @brief M480 CRC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions + @{ +*/ + +/** + * @brief CRC Open + * + * @param[in] u32Mode CRC operation polynomial mode. Valid values are: + * - \ref CRC_CCITT + * - \ref CRC_8 + * - \ref CRC_16 + * - \ref CRC_32 + * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with: + * - \ref CRC_CHECKSUM_COM + * - \ref CRC_CHECKSUM_RVS + * - \ref CRC_WDATA_COM + * - \ref CRC_WDATA_RVS + * @param[in] u32Seed Seed value. + * @param[in] u32DataLen CPU Write Data Length. Valid values are: + * - \ref CRC_CPU_WDATA_8 + * - \ref CRC_CPU_WDATA_16 + * - \ref CRC_CPU_WDATA_32 + * + * @return None + * + * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n + * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly. + */ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen) +{ + CRC->SEED = u32Seed; + CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk; + + /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */ + CRC->CTL |= CRC_CTL_CHKSINIT_Msk; +} + +/** + * @brief Get CRC Checksum + * + * @param[in] None + * + * @return Checksum Result + * + * @details This macro gets the CRC checksum result by current CRC polynomial mode. + */ +uint32_t CRC_GetChecksum(void) +{ + uint32_t ret; + + switch(CRC->CTL & CRC_CTL_CRCMODE_Msk) + { + case CRC_CCITT: + case CRC_16: + ret = (CRC->CHECKSUM & 0xFFFFU); + break; + case CRC_32: + ret = (CRC->CHECKSUM); + break; + case CRC_8: + ret = (CRC->CHECKSUM & 0xFFU); + break; + default: + ret = 0U; + break; + } + + return ret; +} + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/crypto.c b/bsp/nuvoton_m487/libraries/StdDriver/src/crypto.c new file mode 100644 index 00000000000..34b8a1ed0f0 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/crypto.c @@ -0,0 +1,1990 @@ +/**************************************************************************//** + * @file crypto.c + * @version V1.10 + * @brief Cryptographic Accelerator driver source file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "NuMicro.h" + +/** @cond HIDDEN_SYMBOLS */ + +#define ENABLE_DEBUG 0 + +#if ENABLE_DEBUG +#define CRPT_DBGMSG printf +#else +#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/** @cond HIDDEN_SYMBOLS */ + +static uint32_t g_AES_CTL[4]; +static uint32_t g_TDES_CTL[4]; + +static char hex_char_tbl[] = "0123456789abcdef"; + +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count); +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx); +static void Hex2Reg(char input[], uint32_t volatile reg[]); +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]); +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift); +static char ch2hex(char ch); +static int get_nibble_value(char c); + + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Open PRNG function + * @param[in] crpt Reference to Crypto module. + * @param[in] u32KeySize is PRNG key size, including: + * - \ref PRNG_KEY_SIZE_64 + * - \ref PRNG_KEY_SIZE_128 + * - \ref PRNG_KEY_SIZE_192 + * - \ref PRNG_KEY_SIZE_256 + * @param[in] u32SeedReload is PRNG seed reload or not, including: + * - \ref PRNG_SEED_CONT + * - \ref PRNG_SEED_RELOAD + * @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD. + * @return None + */ +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed) +{ + if (u32SeedReload) + { + crpt->PRNG_SEED = u32Seed; + } + + crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos); +} + +/** + * @brief Start to generate one PRNG key. + * @param[in] crpt Reference to Crypto module. + * @return None + */ +void PRNG_Start(CRPT_T *crpt) +{ + crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk; +} + +/** + * @brief Read the PRNG key. + * @param[in] crpt Reference to Crypto module. + * @param[out] u32RandKey The key buffer to store newly generated PRNG key. + * @return None + */ +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]) +{ + uint32_t i, wcnt; + + wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U; + + for (i = 0U; i < wcnt; i++) + { + u32RandKey[i] = crpt->PRNG_KEY[i]; + } + + crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk; +} + + +/** + * @brief Open AES encrypt/decrypt function. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32EncDec 1: AES encode; 0: AES decode + * @param[in] u32OpMode AES operation mode, including: + * - \ref AES_MODE_ECB + * - \ref AES_MODE_CBC + * - \ref AES_MODE_CFB + * - \ref AES_MODE_OFB + * - \ref AES_MODE_CTR + * - \ref AES_MODE_CBC_CS1 + * - \ref AES_MODE_CBC_CS2 + * - \ref AES_MODE_CBC_CS3 + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @param[in] u32SwapType is AES input/output data swap control, including: + * - \ref AES_NO_SWAP + * - \ref AES_OUT_SWAP + * - \ref AES_IN_SWAP + * - \ref AES_IN_OUT_SWAP + * @return None + */ +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, + uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType) +{ + crpt->AES_CTL = (u32Channel << CRPT_AES_CTL_CHANNEL_Pos) | + (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) | + (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) | + (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) | + (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos); + g_AES_CTL[u32Channel] = crpt->AES_CTL; +} + +/** + * @brief Start AES encrypt/decrypt + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32DMAMode AES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop AES encrypt/decrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous AES encrypt/decrypt. + * - \ref CRYPTO_DMA_LAST Last AES encrypt/decrypt of a series of AES_Start. + * @return None + */ +void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode) +{ + crpt->AES_CTL = g_AES_CTL[u32Channel]; + crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos); +} + +/** + * @brief Set AES keys + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32Keys An word array contains AES keys. + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @return None + */ +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) +{ + uint32_t i, wcnt, key_reg_addr; + + key_reg_addr = (uint32_t)&crpt->AES0_KEY[0] + (u32Channel * 0x3CUL); + wcnt = 4UL + u32KeySize*2UL; + + for (i = 0U; i < wcnt; i++) + { + outpw(key_reg_addr, au32Keys[i]); + key_reg_addr += 4UL; + } +} + +/** + * @brief Set AES initial vectors + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32IV A four entry word array contains AES initial vectors. + * @return None + */ +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]) +{ + uint32_t i, key_reg_addr; + + key_reg_addr = (uint32_t)&crpt->AES0_IV[0] + (u32Channel * 0x3CUL); + + for (i = 0U; i < 4U; i++) + { + outpw(key_reg_addr, au32IV[i]); + key_reg_addr += 4UL; + } +} + +/** + * @brief Set AES DMA transfer configuration. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32SrcAddr AES DMA source address + * @param[in] u32DstAddr AES DMA destination address + * @param[in] u32TransCnt AES DMA transfer byte count + * @return None + */ +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->AES0_SADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&crpt->AES0_DADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&crpt->AES0_CNT + (u32Channel * 0x3CUL); + outpw(reg_addr, u32TransCnt); +} + +/** + * @brief Open TDES encrypt/decrypt function. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32EncDec 1: TDES encode; 0: TDES decode + * @param[in] Is3DES 1: TDES; 0: DES + * @param[in] Is3Key 1: TDES 3 key mode; 0: TDES 2 key mode + * @param[in] u32OpMode TDES operation mode, including: + * - \ref TDES_MODE_ECB + * - \ref TDES_MODE_CBC + * - \ref TDES_MODE_CFB + * - \ref TDES_MODE_OFB + * - \ref TDES_MODE_CTR + * @param[in] u32SwapType is TDES input/output data swap control and word swap control, including: + * - \ref TDES_NO_SWAP + * - \ref TDES_WHL_SWAP + * - \ref TDES_OUT_SWAP + * - \ref TDES_OUT_WHL_SWAP + * - \ref TDES_IN_SWAP + * - \ref TDES_IN_WHL_SWAP + * - \ref TDES_IN_OUT_SWAP + * - \ref TDES_IN_OUT_WHL_SWAP + * @return None + */ +void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, + uint32_t u32OpMode, uint32_t u32SwapType) +{ + g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) | + (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) | + u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos); + if (Is3DES) + { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk; + } + if (Is3Key) + { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk; + } +} + +/** + * @brief Start TDES encrypt/decrypt + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32DMAMode TDES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop TDES encrypt/decrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous TDES encrypt/decrypt. + * - \ref CRYPTO_DMA_LAST Last TDES encrypt/decrypt of a series of TDES_Start. + * @return None + */ +void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode) +{ + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_START_Msk | (u32DMAMode << CRPT_TDES_CTL_DMALAST_Pos); + crpt->TDES_CTL = g_TDES_CTL[u32Channel]; +} + +/** + * @brief Set TDES keys + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] au32Keys The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word. + * @return None + */ +void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]) +{ + uint32_t i, reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_KEY1H + (0x40UL * u32Channel); + + for (i = 0U; i < 3U; i++) + { + outpw(reg_addr, au32Keys[i][0]); /* TDESn_KEYxH */ + reg_addr += 4UL; + outpw(reg_addr, au32Keys[i][1]); /* TDESn_KEYxL */ + reg_addr += 4UL; + } +} + +/** + * @brief Set TDES initial vectors + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32IVH TDES initial vector high word. + * @param[in] u32IVL TDES initial vector low word. + * @return None + */ +void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_IVH + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVH); + + reg_addr = (uint32_t)&crpt->TDES0_IVL + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVL); +} + +/** + * @brief Set TDES DMA transfer configuration. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32SrcAddr TDES DMA source address + * @param[in] u32DstAddr TDES DMA destination address + * @param[in] u32TransCnt TDES DMA transfer byte count + * @return None + */ +void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_SA + (u32Channel * 0x40UL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&crpt->TDES0_DA + (u32Channel * 0x40UL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&crpt->TDES0_CNT + (u32Channel * 0x40UL); + outpw(reg_addr, u32TransCnt); +} + +/** + * @brief Open SHA encrypt function. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32OpMode SHA operation mode, including: + * - \ref SHA_MODE_SHA1 + * - \ref SHA_MODE_SHA224 + * - \ref SHA_MODE_SHA256 + * - \ref SHA_MODE_SHA384 + * - \ref SHA_MODE_SHA512 + * @param[in] u32SwapType is SHA input/output data swap control, including: + * - \ref SHA_NO_SWAP + * - \ref SHA_OUT_SWAP + * - \ref SHA_IN_SWAP + * - \ref SHA_IN_OUT_SWAP + * @param[in] hmac_key_len HMAC key byte count + * @return None + */ +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len) +{ + crpt->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) | + (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos); + + if (hmac_key_len != 0UL) + { + crpt->HMAC_KEYCNT = hmac_key_len; + crpt->HMAC_CTL |= CRPT_HMAC_CTL_HMACEN_Msk; + } +} + +/** + * @brief Start SHA encrypt + * @param[in] crpt Reference to Crypto module. + * @param[in] u32DMAMode TDES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop SHA encrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous SHA encrypt. + * - \ref CRYPTO_DMA_LAST Last SHA encrypt of a series of SHA_Start. + * @return None + */ +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode) +{ + crpt->HMAC_CTL &= ~(0x7UL << CRPT_HMAC_CTL_DMALAST_Pos); + crpt->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos); +} + +/** + * @brief Set SHA DMA transfer + * @param[in] crpt Reference to Crypto module. + * @param[in] u32SrcAddr SHA DMA source address + * @param[in] u32TransCnt SHA DMA transfer byte count + * @return None + */ +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt) +{ + crpt->HMAC_SADDR = u32SrcAddr; + crpt->HMAC_DMACNT = u32TransCnt; +} + +/** + * @brief Read the SHA digest. + * @param[in] crpt Reference to Crypto module. + * @param[out] u32Digest The SHA encrypt output digest. + * @return None + */ +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]) +{ + uint32_t i, wcnt, reg_addr; + + i = (crpt->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos; + + if (i == SHA_MODE_SHA1) + { + wcnt = 5UL; + } + else if (i == SHA_MODE_SHA224) + { + wcnt = 7UL; + } + else if (i == SHA_MODE_SHA256) + { + wcnt = 8UL; + } + else if (i == SHA_MODE_SHA384) + { + wcnt = 12UL; + } + else + { + /* SHA_MODE_SHA512 */ + wcnt = 16UL; + } + + reg_addr = (uint32_t)&(crpt->HMAC_DGST[0]); + for (i = 0UL; i < wcnt; i++) + { + u32Digest[i] = inpw(reg_addr); + reg_addr += 4UL; + } +} + +/** @cond HIDDEN_SYMBOLS */ + +/*-----------------------------------------------------------------------------------------------*/ +/* */ +/* ECC */ +/* */ +/*-----------------------------------------------------------------------------------------------*/ + +#define ECCOP_POINT_MUL (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_MODULE (0x1UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_ADD (0x2UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_DOUBLE (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) + +#define MODOP_DIV (0x0UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_MUL (0x1UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_ADD (0x2UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_SUB (0x3UL << CRPT_ECC_CTL_MODOP_Pos) + +enum +{ + CURVE_GF_P, + CURVE_GF_2M, +}; + +/*-----------------------------------------------------*/ +/* Define elliptic curve (EC): */ +/*-----------------------------------------------------*/ + +typedef struct e_curve_t +{ + E_ECC_CURVE curve_id; + int32_t Echar; + char Ea[144]; + char Eb[144]; + char Px[144]; + char Py[144]; + int32_t Epl; + char Pp[176]; + int32_t Eol; + char Eorder[176]; + int32_t key_len; + int32_t irreducible_k1; + int32_t irreducible_k2; + int32_t irreducible_k3; + int32_t GF; +} ECC_CURVE; + +const ECC_CURVE _Curve[] = +{ + { + /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */ + CURVE_P_192, + 48, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC", /* "000000000000000000000000000000000000000000000003" */ + "64210519e59c80e70fa7e9ab72243049feb8deecc146b9b1", + "188da80eb03090f67cbf20eb43a18800f4ff0afd82ff1012", + "07192b95ffc8da78631011ed6b24cdd573f977a11e794811", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF", /* "6277101735386680763835789423207666416083908700390324961279" */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831", /* "6277101735386680763835789423176059013767194773182842284081" */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* NIST: Curve P-224 : y^2=x^3-ax+b (mod p) */ + CURVE_P_224, + 56, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE", /* "00000000000000000000000000000000000000000000000000000003" */ + "b4050a850c04b3abf54132565044b0b7d7bfd8ba270b39432355ffb4", + "b70e0cbd6bb4bf7f321390b94a03c1d356c21122343280d6115c1d21", + "bd376388b5f723fb4c22dfe6cd4375a05a07476444d5819985007e34", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "0026959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D", /* "0026959946667150639794667015087019625940457807714424391721682722368061" */ + 224, /* key_len */ + 9, + 8, + 3, + CURVE_GF_P + }, + { + /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */ + CURVE_P_256, + 64, /* Echar */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC", /* "0000000000000000000000000000000000000000000000000000000000000003" */ + "5ac635d8aa3a93e7b3ebbd55769886bc651d06b0cc53b0f63bce3c3e27d2604b", + "6b17d1f2e12c4247f8bce6e563a440f277037d812deb33a0f4a13945d898c296", + "4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5", + 78, /* Epl */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF", /* "115792089210356248762697446949407573530086143415290314195533631308867097853951" */ + 78, /* Eol */ + "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551", /* "115792089210356248762697446949407573529996955224135760342422259061068512044369" */ + 256, /* key_len */ + 10, + 5, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-384 : y^2=x^3-ax+b (mod p) */ + CURVE_P_384, + 96, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC", /* "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "b3312fa7e23ee7e4988e056be3f82d19181d9c6efe8141120314088f5013875ac656398d8a2ed19d2a85c8edd3ec2aef", + "aa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7", + "3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f", + 116, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF", /* "39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319" */ + 116, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973", /* "39402006196394479212279040100143613805079739270465446667946905279627659399113263569398956308152294913554433653942643" */ + 384, /* key_len */ + 12, + 3, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-521 : y^2=x^3-ax+b (mod p)*/ + CURVE_P_521, + 131, /* Echar */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC", /* "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "051953eb9618e1c9a1f929a21a0b68540eea2da725b99b315f3b8b489918ef109e156193951ec7e937b1652c0bd3bb1bf073573df883d2c34f1ef451fd46b503f00", + "0c6858e06b70404e9cd9e3ecb662395b4429c648139053fb521f828af606b4d3dbaa14b5e77efe75928fe1dc127a2ffa8de3348b3c1856a429bf97e7e31c2e5bd66", + "11839296a789a3bc0045c8a5fb42c7d1bd998f54449579b446817afbd17273e662c97ee72995ef42640c550b9013fad0761353c7086a272c24088be94769fd16650", + 157, /* Epl */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397656052122559640661454554977296311391480858037121987999716643812574028291115057151" */ + 157, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397655394245057746333217197532963996371363321113864768612440380340372808892707005449" */ + 521, /* key_len */ + 32, + 32, + 32, + CURVE_GF_P + }, + { + /* NIST: Curve B-163 : y^2+xy=x^3+ax^2+b */ + CURVE_B_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "20a601907b8c953ca1481eb10512f78744a3205fd", + "3f0eba16286a2d57ea0991168d4994637e8343e36", + "0d51fbc6c71a0094fa2cdd545b11c5c0c797324f1", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "40000000000000000000292FE77E70C12A4234C33", /* "5846006549323611672814742442876390689256843201587" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve B-233 : y^2+xy=x^3+ax^2+b */ + CURVE_B_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000001", + "066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad", + "0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b", + "1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "1000000000000000000000000000013E974E72F8A6922031D2603CFE0D7", /* "6901746346790563787434755862277025555839812737345013555379383634485463" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve B-283 : y^2+xy=x^3+ax^2+b */ + CURVE_B_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000001", + "27b680ac8b8596da5a4af8a19a0303fca97fd7645309fa2a581485af6263e313b79a2f5", + "5f939258db7dd90e1934f8c70b0dfec2eed25b8557eac9c80e2e198f8cdbecd86b12053", + "3676854fe24141cb98fe6d4b20d02b4516ff702350eddb0826779c813f0df45be8112f4", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF90399660FC938A90165B042A7CEFADB307", /* "7770675568902916283677847627294075626569625924376904889109196526770044277787378692871" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve B-409 : y^2+xy=x^3+ax^2+b */ + CURVE_B_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "021a5c2c8ee9feb5c4b9a753b7b476b7fd6422ef1f3dd674761fa99d6ac27c8a9a197b272822f6cd57a55aa4f50ae317b13545f", + "15d4860d088ddb3496b0c6064756260441cde4af1771d4db01ffe5b34e59703dc255a868a1180515603aeab60794e54bb7996a7", + "061b1cfab6be5f32bbfa78324ed106a7636b9c5a7bd198d0158aa4f5488d08f38514f1fdf4b4f40d2181b3681c364ba0273c706", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "10000000000000000000000000000000000000000000000000001E2AAD6A612F33307BE5FA47C3C9E052F838164CD37D9A21173", /* "661055968790248598951915308032771039828404682964281219284648798304157774827374805208143723762179110965979867288366567526771" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve B-571 : y^2+xy=x^3+ax^2+b */ + CURVE_B_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "2f40e7e2221f295de297117b7f3d62f5c6a97ffcb8ceff1cd6ba8ce4a9a18ad84ffabbd8efa59332be7ad6756a66e294afd185a78ff12aa520e4de739baca0c7ffeff7f2955727a", + "303001d34b856296c16c0d40d3cd7750a93d1d2955fa80aa5f40fc8db7b2abdbde53950f4c0d293cdd711a35b67fb1499ae60038614f1394abfa3b4c850d927e1e7769c8eec2d19", + "37bf27342da639b6dccfffeb73d69d78c6c27a6009cbbca1980f8533921e8a684423e43bab08a576291af8f461bb2a8b3531d2f0485c19b16e2f1516e23dd3c1a4827af1b8ac15b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE661CE18FF55987308059B186823851EC7DD9CA1161DE93D5174D66E8382E9BB2FE84E47", /* "3864537523017258344695351890931987344298927329706434998657235251451519142289560424536143999389415773083133881121926944486246872462816813070234528288303332411393191105285703" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* NIST: Curve K-163 : y^2+xy=x^3+ax^2+b */ + CURVE_K_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "00000000000000000000000000000000000000001", + "2fe13c0537bbc11acaa07d793de4e6d5e5c94eee8", + "289070fb05d38ff58321f2e800536d538ccdaa3d9", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "4000000000000000000020108A2E0CC0D99F8A5EF", /* "5846006549323611672814741753598448348329118574063" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve K-233 : y^2+xy=x^3+ax^2+b */ + CURVE_K_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000001", + "17232ba853a7e731af129f22ff4149563a419c26bf50a4c9d6eefad6126", + "1db537dece819b7f70f555a67c427a8cd9bf18aeb9b56e0c11056fae6a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "8000000000000000000000000000069D5BB915BCD46EFB1AD5F173ABDF", /* "3450873173395281893717377931138512760570940988862252126328087024741343" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve K-283 : y^2+xy=x^3+ax^2+b */ + CURVE_K_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000001", + "503213f78ca44883f1a3b8162f188e553cd265f23c1567a16876913b0c2ac2458492836", + "1ccda380f1c9e318d90f95d07e5426fe87e45c0e8184698e45962364e34116177dd2259", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9AE2ED07577265DFF7F94451E061E163C61", /* "3885337784451458141838923813647037813284811733793061324295874997529815829704422603873" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve K-409 : y^2+xy=x^3+ax^2+b */ + CURVE_K_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "060f05f658f49c1ad3ab1890f7184210efd0987e307c84c27accfb8f9f67cc2c460189eb5aaaa62ee222eb1b35540cfe9023746", + "1e369050b7c4e42acba1dacbf04299c3460782f918ea427e6325165e9ea10e3da5f6c42e9c55215aa9ca27a5863ec48d8e0286b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5F83B2D4EA20400EC4557D5ED3E3E7CA5B4B5C83B8E01E5FCF", /* "330527984395124299475957654016385519914202341482140609642324395022880711289249191050673258457777458014096366590617731358671" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve K-571 : y^2+xy=x^3+ax^2+b */ + CURVE_K_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "26eb7a859923fbc82189631f8103fe4ac9ca2970012d5d46024804801841ca44370958493b205e647da304db4ceb08cbbd1ba39494776fb988b47174dca88c7e2945283a01c8972", + "349dc807f4fbf374f4aeade3bca95314dd58cec9f307a54ffc61efc006d8a2c9d4979c0ac44aea74fbebbb9f772aedcb620b01a7ba7af1b320430c8591984f601cd4c143ef1c7a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "20000000000000000000000000000000000000000000000000000000000000000000000131850E1F19A63E4B391A8DB917F4138B630D84BE5D639381E91DEB45CFE778F637C1001", /* "1932268761508629172347675945465993672149463664853217499328617625725759571144780212268133978522706711834706712800825351461273674974066617311929682421617092503555733685276673" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* Koblitz: Curve secp192k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_192, + 48, /* Echar */ + "00000000000000000000000000000000000000000", + "00000000000000000000000000000000000000003", + "DB4FF10EC057E9AE26B07D0280B7F4341DA5D1B1EAE06C7D", + "9B2F2F6D9C5628A7844163D015BE86344082AA88D95E2F9D", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFEE37", /* p */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFE26F2FC170F69466A74DEFD8D", /* n */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Koblitz: Curve secp224k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_224, + 56, /* Echar */ + "00000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000005", + "A1455B334DF099DF30FC28A169A467E9E47075A90F7E650EB6B7A45C", + "7E089FED7FBA344282CAFBD6F7E319F7C0B0BD59E2CA4BDB556D61A5", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFE56D", /* p */ + 70, /* Eol */ + "0000000000000000000000000001DCE8D2EC6184CAF0A971769FB1F7", /* n */ + 224, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Koblitz: Curve secp256k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_256, + 64, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000007", + "79BE667EF9DCBBAC55A06295CE870B07029BFCDB2DCE28D959F2815B16F81798", + "483ADA7726A3C4655DA4FBFC0E1108A8FD17B448A68554199C47D08FFB10D4B8", + 78, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFC2F", /* p */ + 78, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBAAEDCE6AF48A03BBFD25E8CD0364141", /* n */ + 256, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP256r1 */ + CURVE_BP_256, + 64, /* Echar */ + "7D5A0975FC2C3057EEF67530417AFFE7FB8055C126DC5C6CE94A4B44F330B5D9", /* A */ + "26DC5C6CE94A4B44F330B5D9BBD77CBF958416295CF7E1CE6BCCDC18FF8C07B6", /* B */ + "8BD2AEB9CB7E57CB2C4B482FFC81B7AFB9DE27E1E3BD23C23A4453BD9ACE3262", /* x */ + "547EF835C3DAC4FD97F8461A14611DC9C27745132DED8E545C1D54C72F046997", /* y */ + 78, /* Epl */ + "A9FB57DBA1EEA9BC3E660A909D838D726E3BF623D52620282013481D1F6E5377", /* p */ + 78, /* Eol */ + "A9FB57DBA1EEA9BC3E660A909D838D718C397AA3B561A6F7901E0E82974856A7", /* q */ + 256, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP384r1 */ + CURVE_BP_384, + 96, /* Echar */ + "7BC382C63D8C150C3C72080ACE05AFA0C2BEA28E4FB22787139165EFBA91F90F8AA5814A503AD4EB04A8C7DD22CE2826", /* A */ + "04A8C7DD22CE28268B39B55416F0447C2FB77DE107DCD2A62E880EA53EEB62D57CB4390295DBC9943AB78696FA504C11", /* B */ + "1D1C64F068CF45FFA2A63A81B7C13F6B8847A3E77EF14FE3DB7FCAFE0CBD10E8E826E03436D646AAEF87B2E247D4AF1E", /* x */ + "8ABE1D7520F9C2A45CB1EB8E95CFD55262B70B29FEEC5864E19C054FF99129280E4646217791811142820341263C5315", /* y */ + 116, /* Epl */ + "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B412B1DA197FB71123ACD3A729901D1A71874700133107EC53", /* p */ + 116, /* Eol */ + "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B31F166E6CAC0425A7CF3AB6AF6B7FC3103B883202E9046565", /* q */ + 384, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP512r1 */ + CURVE_BP_512, + 128, /* Echar */ + "7830A3318B603B89E2327145AC234CC594CBDD8D3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CA", /* A */ + "3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CADC083E67984050B75EBAE5DD2809BD638016F723", /* B */ + "81AEE4BDD82ED9645A21322E9C4C6A9385ED9F70B5D916C1B43B62EEF4D0098EFF3B1F78E2D0D48D50D1687B93B97D5F7C6D5047406A5E688B352209BCB9F822", /* x */ + "7DDE385D566332ECC0EABFA9CF7822FDF209F70024A57B1AA000C55B881F8111B2DCDE494A5F485E5BCA4BD88A2763AED1CA2B2FA8F0540678CD1E0F3AD80892", /* y */ + 156, /* Epl */ + "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA703308717D4D9B009BC66842AECDA12AE6A380E62881FF2F2D82C68528AA6056583A48F3", /* p */ + 156, /* Eol */ + "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA70330870553E5C414CA92619418661197FAC10471DB1D381085DDADDB58796829CA90069", /* q */ + 512, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, +}; + +static ECC_CURVE *pCurve; +static ECC_CURVE Curve_Copy; + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve); +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve); +static void run_ecc_codec(CRPT_T *crpt, uint32_t mode); + +static char temp_hex_str[160]; + + +#if ENABLE_DEBUG +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ + int32_t i; + + printf("%s => ", str); + for (i = 0; i < count; i++) + { + printf("0x%08x ", regs[i]); + } + printf("\n"); +} +#else +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ +} +#endif + +static char ch2hex(char ch) +{ + if (ch <= '9') + { + ch = ch - '0'; + } + else if ((ch <= 'z') && (ch >= 'a')) + { + ch = ch - 'a' + 10U; + } + else + { + ch = ch - 'A' + 10U; + } + return ch; +} + +static void Hex2Reg(char input[], uint32_t volatile reg[]) +{ + char hex; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0; + + while (si >= 0) + { + val32 = 0UL; + for (i = 0UL; (i < 8UL) && (si >= 0); i++) + { + hex = ch2hex(input[si]); + val32 |= (uint32_t)hex << (i * 4UL); + si--; + } + reg[ri++] = val32; + } +} + +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift) +{ + uint32_t hex, carry; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0L; + carry = 0UL; + while (si >= 0) + { + val32 = 0UL; + for (i = 0UL; (i < 8UL) && (si >= 0L); i++) + { + hex = (uint32_t)ch2hex(input[si]); + hex <<= shift; + + val32 |= (uint32_t)((hex & 0xFUL) | carry) << (i * 4UL); + carry = (hex >> 4UL) & 0xFUL; + si--; + } + reg[ri++] = val32; + } + if (carry != 0UL) + { + reg[ri] = carry; + } +} + +/** + * @brief Extract specified nibble from an unsigned word in character format. + * For example: + * Suppose val32 is 0x786543210, get_Nth_nibble_char(val32, 3) will return a '3'. + * @param[in] val32 The input unsigned word + * @param[in] idx The Nth nibble to be extracted. + * @return The nibble in character format. + */ +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx) +{ + return hex_char_tbl[ (val32 >> (idx * 4U)) & 0xfU ]; +} + + +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]) +{ + int32_t idx, ri; + uint32_t i; + + output[count] = 0U; + idx = count - 1; + + for (ri = 0; idx >= 0; ri++) + { + for (i = 0UL; (i < 8UL) && (idx >= 0); i++) + { + output[idx] = get_Nth_nibble_char(reg[ri], i); + idx--; + } + } +} + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve) +{ + uint32_t i; + ECC_CURVE *ret = NULL; + + for (i = 0UL; i < sizeof(_Curve) / sizeof(ECC_CURVE); i++) + { + if (ecc_curve == _Curve[i].curve_id) + { + memcpy((char *)&Curve_Copy, &_Curve[i], sizeof(ECC_CURVE)); + ret = &Curve_Copy; /* (ECC_CURVE *)&_Curve[i]; */ + } + if (ret != NULL) + { + break; + } + } + return ret; +} + +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve) +{ + int32_t i, ret = 0; + + pCurve = get_curve(ecc_curve); + if (pCurve == NULL) + { + CRPT_DBGMSG("Cannot find curve %d!!\n", ecc_curve); + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_A[i] = 0UL; + crpt->ECC_B[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_N[i] = 0UL; + } + + Hex2Reg(pCurve->Ea, crpt->ECC_A); + Hex2Reg(pCurve->Eb, crpt->ECC_B); + Hex2Reg(pCurve->Px, crpt->ECC_X1); + Hex2Reg(pCurve->Py, crpt->ECC_Y1); + + CRPT_DBGMSG("Key length = %d\n", pCurve->key_len); + dump_ecc_reg("CRPT_ECC_CURVE_A", crpt->ECC_A, 10); + dump_ecc_reg("CRPT_ECC_CURVE_B", crpt->ECC_B, 10); + dump_ecc_reg("CRPT_ECC_POINT_X1", crpt->ECC_X1, 10); + dump_ecc_reg("CRPT_ECC_POINT_Y1", crpt->ECC_Y1, 10); + + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_N[0] = 0x1UL; + crpt->ECC_N[(pCurve->key_len) / 32] |= (1UL << ((pCurve->key_len) % 32)); + crpt->ECC_N[(pCurve->irreducible_k1) / 32] |= (1UL << ((pCurve->irreducible_k1) % 32)); + crpt->ECC_N[(pCurve->irreducible_k2) / 32] |= (1UL << ((pCurve->irreducible_k2) % 32)); + crpt->ECC_N[(pCurve->irreducible_k3) / 32] |= (1UL << ((pCurve->irreducible_k3) % 32)); + } + else + { + Hex2Reg(pCurve->Pp, crpt->ECC_N); + } + } + dump_ecc_reg("CRPT_ECC_CURVE_N", crpt->ECC_N, 10); + return ret; +} + +static int get_nibble_value(char c) +{ + if ((c >= '0') && (c <= '9')) + { + c = c - '0'; + } + + if ((c >= 'a') && (c <= 'f')) + { + c = c - 'a' + (char)10; + } + + if ((c >= 'A') && (c <= 'F')) + { + c = c - 'A' + (char)10; + } + return (int)c; +} + +static int ecc_strcmp(char *s1, char *s2) +{ + char c1, c2; + + while (*s1 == '0') s1++; + while (*s2 == '0') s2++; + + for ( ; *s1 || *s2; s1++, s2++) + { + if ((*s1 >= 'A') && (*s1 <= 'Z')) + c1 = *s1 + 32; + else + c1 = *s1; + + if ((*s2 >= 'A') && (*s2 <= 'Z')) + c2 = *s2 + 32; + else + c2 = *s2; + + if (c1 != c2) + return 1; + } + return 0; +} + +volatile uint32_t g_ECC_done, g_ECCERR_done; + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief ECC interrupt service routine. User application must invoke this function in + * his CRYPTO_IRQHandler() to let Crypto driver know ECC processing was done. + * @param[in] crpt Reference to Crypto module. + * @return none + */ +void ECC_Complete(CRPT_T *crpt) +{ + if (crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk) + { + g_ECC_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk; + /* printf("ECC done IRQ.\n"); */ + } + + if (crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk) + { + g_ECCERR_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk; + /* printf("ECCERRIF is set!!\n"); */ + } +} + +/** + * @brief Check if the private key is located in valid range of curve. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k The input private key. + * @return 1 Is valid. + * @return 0 Is not valid. + * @return -1 Invalid curve. + */ +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]) +{ + uint32_t i; + int ret = -1; + + pCurve = get_curve(ecc_curve); + if (pCurve == NULL) + { + ret = -1; + } + + if (strlen(private_k) < strlen(pCurve->Eorder)) + { + ret = 1; + } + + if (strlen(private_k) > strlen(pCurve->Eorder)) + { + ret = 0; + } + + for (i = 0UL; i < strlen(private_k); i++) + { + if (get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i])) + { + ret = 1; + break; + } + if (get_nibble_value(private_k[i]) > get_nibble_value(pCurve->Eorder[i])) + { + ret = 0; + break; + } + } + return ret; +} + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt Reference to Crypto module. + * @param[in] private_k The input private key. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] public_k1 The output public key 1. + * @param[out] public_k2 The output public key 2. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]) +{ + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(private_k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2); + } + + return ret; +} + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt Reference to Crypto module. + * @param[out] x1 The x-coordinate of input point. + * @param[out] y1 The y-coordinate of input point. + * @param[in] k The private key + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] x2 The x-coordinate of output point. + * @param[out] y2 The y-coordinate of output point. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]) +{ + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(x1, crpt->ECC_X1); + Hex2Reg(y1, crpt->ECC_Y1); + Hex2Reg(k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, x2); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, y2); + } + + return ret; +} + +/** + * @brief Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k One's own private key. + * @param[in] public_k1 The other party's publick key 1. + * @param[in] public_k2 The other party's publick key 2. + * @param[out] secret_z The ECC CDH secret Z. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]) +{ + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + if ((ecc_curve == CURVE_B_163) || (ecc_curve == CURVE_B_233) || (ecc_curve == CURVE_B_283) || + (ecc_curve == CURVE_B_409) || (ecc_curve == CURVE_B_571) || (ecc_curve == CURVE_K_163)) + { + Hex2RegEx(private_k, crpt->ECC_K, 1); + } + else if ((ecc_curve == CURVE_K_233) || (ecc_curve == CURVE_K_283) || + (ecc_curve == CURVE_K_409) || (ecc_curve == CURVE_K_571)) + { + Hex2RegEx(private_k, crpt->ECC_K, 2); + } + else + { + Hex2Reg(private_k, crpt->ECC_K); + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* set FSEL (Field selection) */ + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, secret_z); + } + + return ret; +} + +/** @cond HIDDEN_SYMBOLS */ + +static void run_ecc_codec(CRPT_T *crpt, uint32_t mode) +{ + if ((mode & CRPT_ECC_CTL_ECCOP_Msk) == ECCOP_MODULE) + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + else + { + if (pCurve->GF == (int)CURVE_GF_2M) + { + /* point */ + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | mode | CRPT_ECC_CTL_START_Msk; + while ((g_ECC_done | g_ECCERR_done) == 0UL) + { + } + + while (crpt->ECC_STS & CRPT_ECC_STS_BUSY_Msk) + { + } +} +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief ECDSA digital signature generation. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] d The private key. + * @param[in] k The selected random integer. + * @param[out] R R of the (R,S) pair digital signature + * @param[out] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *d, char *k, char *R, char *S) +{ + uint32_t volatile temp_result1[18], temp_result2[18]; + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + /* + * 1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1) + * (1) Use SHA to calculate e + */ + + /* 2. Select a random integer k form [1, n-1] + * (1) Notice that n is order, not prime modulus or irreducible polynomial function + */ + + /* + * 3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2 + * (1) Write the curve parameter A, B, and curve length M to corresponding registers + * (2) Write the prime modulus or irreducible polynomial function to N registers according + * (3) Write the point G(x, y) to X1, Y1 registers + * (4) Write the random integer k to K register + * (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Write the curve order and curve length to N ,M registers according + * (10) Write 0x0 to Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 * + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Read X1 registers to get r + */ + + /* 3-(4) Write the random integer k to K register */ + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_K); + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* 3-(9) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(10) Write 0x0 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* 3-(15) Read X1 registers to get r */ + for (i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result1, R); + + /* + * 4. Compute s = k ? 1 (e + d r)(mod n). If s = 0, go to step 2 + * (1) Write the curve order to N registers according + * (2) Write 0x1 to Y1 registers + * (3) Write the random integer k to X1 registers according + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set START(CRPT_ECC_CTL[0]) to 1 + * (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (8) Read X1 registers to get k^-1 + * (9) Write the curve order and curve length to N ,M registers + * (10) Write r, d to X1, Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Write the curve order to N registers + * (16) Write e to Y1 registers + * (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (19) Set START(CRPT_ECC_CTL[0]) to 1 + * (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (21) Write the curve order and curve length to N ,M registers + * (22) Write k^-1 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get s + */ + + /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */ + + /* 4-(1) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write 0x1 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 4-(3) Write the random integer k to X1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(7) output = %s\n", temp_hex_str); +#endif + + /* 4-(8) Read X1 registers to get k^-1 */ + + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("k^-1 = %s\n", temp_hex_str); +#endif + + /* 4-(9) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(10) Write r, d to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + } + + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + Hex2Reg(d, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(14) output = %s\n", temp_hex_str); +#endif + + /* 4-(15) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(16) Write e to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(20) output = %s\n", temp_hex_str); +#endif + + /* 4-(21) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(22) Write k^-1 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(27) Read X1 registers to get s */ + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result2, S); + + } /* ret == 0 */ + + return ret; +} + +/** + * @brief ECDSA dogotal signature verification. + * @param[in] crpt Reference to Crypto module. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] public_k1 The public key 1. + * @param[in] public_k2 The public key 2. + * @param[in] R R of the (R,S) pair digital signature + * @param[in] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + * @return -2 Verification failed. + */ +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *public_k1, char *public_k2, char *R, char *S) +{ + uint32_t temp_result1[18], temp_result2[18]; + uint32_t temp_x[18], temp_y[18]; + int32_t i, ret = 0; + + /* + * 1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid + * 2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation + * (1) Use SHA to calculate e + */ + + /* + * 3. Compute w = s^-1 (mod n) + * (1) Write the curve order to N registers + * (2) Write 0x1 to Y1 registers + * (3) Write s to X1 registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Read X1 registers to get w + */ + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + /* 3-(1) Write the curve order to N registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(2) Write 0x1 to Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 3-(3) Write s to X1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(S, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + + /* 3-(9) Read X1 registers to get w */ + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + CRPT_DBGMSG("e = %s\n", message); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("w = %s\n", temp_hex_str); + CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder); +#endif + + /* + * 4. Compute u1 = e w (mod n) and u2 = r w (mod n) + * (1) Write the curve order and curve length to N ,M registers + * (2) Write e, w to X1, Y1 registers + * (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1 registers to get u1 + * (8) Write the curve order and curve length to N ,M registers + * (9) Write r, w to X1, Y1 registers + * (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Read X1 registers to get u2 + */ + + /* 4-(1) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write e, w to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_X1); + + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(7) Read X1 registers to get u1 */ + for (i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("u1 = %s\n", temp_hex_str); +#endif + + /* 4-(8) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(9) Write r, w to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(R, crpt->ECC_X1); + + for (i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(14) Read X1 registers to get u2 */ + for (i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("u2 = %s\n", temp_hex_str); +#endif + + /* + * 5. Compute X (x1, y1) = u1 * G + u2 * Q + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + * (3) Write u1 to K registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1, Y1 registers to get u1*G + * (8) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (9) Write the public key Q(x,y) to X1, Y1 registers + * (10) Write u2 to K registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (15) Write the result data u1*G to X2, Y2 registers + * (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10 + * (17) Set START(CRPT_ECC_CTL[0]) to 1 + * (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (19) Read X1, Y1 registers to get X(x1, y1) + * (20) Write the curve order and curve length to N ,M registers + * (21) Write x1 to X1 registers + * (22) Write 0x0 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get x1 (mod n) + * + * 6. The signature is valid if x1 = r, otherwise it is invalid + */ + + /* + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + */ + ecc_init_curve(crpt, ecc_curve); + + /* (3) Write u1 to K registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result1[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* (7) Read X1, Y1 registers to get u1*G */ + for (i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str); +#endif + + /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* (9) Write the public key Q(x,y) to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* (10) Write u2 to K registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + for (i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + temp_result2[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str); +#endif + + /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* Write the result data u2*Q to X1, Y1 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + crpt->ECC_Y1[i] = temp_result2[i]; + } + + /* (15) Write the result data u1*G to X2, Y2 registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X2[i] = temp_x[i]; + crpt->ECC_Y2[i] = temp_y[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_ADD); + + /* (19) Read X1, Y1 registers to get X(x1, y1) */ + for (i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str); +#endif + + /* (20) Write the curve order and curve length to N ,M registers */ + for (i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* + * (21) Write x1 to X1 registers + * (22) Write 0x0 to Y1 registers + */ + for (i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_x[i]; + crpt->ECC_Y1[i] = 0UL; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str); + CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str); +#endif + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* (27) Read X1 registers to get x1 (mod n) */ + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str); + + /* 6. The signature is valid if x1 = r, otherwise it is invalid */ + + /* Compare with test pattern to check if r is correct or not */ + if (ecc_strcmp(temp_hex_str, R) != 0) + { + CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n"); + CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R); + ret = -2; + } + } /* ret == 0 */ + + return ret; +} + +/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRYPTO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/dac.c b/bsp/nuvoton_m487/libraries/StdDriver/src/dac.c new file mode 100644 index 00000000000..7a448596ea7 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/dac.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file dac.c + * @version V1.00 + * @brief M480 series DAC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions + @{ +*/ + +/** + * @brief This function make DAC module be ready to convert. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @param[in] u32TrgSrc Decides the trigger source. Valid values are: + * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger + * - \ref DAC_SOFTWARE_TRIGGER :Software trigger + * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger + * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger + * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger + * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger + * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger + * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger + * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger + * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger + * - \ref DAC_EPWM0_TRIGGER :EPWM0 trigger + * - \ref DAC_EPWM1_TRIGGER :EPWM1 trigger + * @return None + * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger. + * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register. + * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1, + * external STDAC pin, timer event, or EPWM event. + */ +void DAC_Open(DAC_T *dac, + uint32_t u32Ch, + uint32_t u32TrgSrc) +{ + dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk); + dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk); +} + +/** + * @brief Disable DAC analog power. + * @param[in] dac Base address of DAC module. + * @param[in] u32Ch Not used in M480 DAC. + * @return None + * @details Disable DAC analog power for saving power consumption. + */ +void DAC_Close(DAC_T *dac, uint32_t u32Ch) +{ + dac->CTL &= (~DAC_CTL_DACEN_Msk); +} + +/** + * @brief Set delay time for DAC to become stable. + * @param[in] dac Base address of DAC module. + * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds. + * @return Real DAC conversion settling time (micro second). + * @details For example, DAC controller clock speed is 160MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0xA0. + * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed. + */ +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay) +{ + + dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL); + + return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq()); +} + + + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/eadc.c b/bsp/nuvoton_m487/libraries/StdDriver/src/eadc.c new file mode 100644 index 00000000000..fa7c8d8c9d5 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/eadc.c @@ -0,0 +1,140 @@ +/**************************************************************************//** + * @file eadc.c + * @version V2.00 + * @brief M480 series EADC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions + @{ +*/ + +/** + * @brief This function make EADC_module be ready to convert. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32InputMode Decides the input mode. + * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode. + * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type. + * @return None + * @details This function is used to set analog input mode and enable A/D Converter. + * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1. + * @note + */ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode) +{ + eadc->CTL &= (~EADC_CTL_DIFFEN_Msk); + + eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk); + while (!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {} +} + +/** + * @brief Disable EADC_module. + * @param[in] eadc The pointer of the specified EADC module.. + * @return None + * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption. + */ +void EADC_Close(EADC_T *eadc) +{ + eadc->CTL &= ~EADC_CTL_ADCEN_Msk; +} + +/** + * @brief Configure the sample control logic module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerSrc Decides the trigger source. Valid values are: + * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger + * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger + * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger + * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger + * - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger + * - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger + * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger + * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger + * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger + * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger + * - \ref EADC_PWM0TG0_TRIGGER : PWM0TG0 trigger + * - \ref EADC_PWM0TG1_TRIGGER : PWM0TG1 trigger + * - \ref EADC_PWM0TG2_TRIGGER : PWM0TG2 trigger + * - \ref EADC_PWM0TG3_TRIGGER : PWM0TG3 trigger + * - \ref EADC_PWM0TG4_TRIGGER : PWM0TG4 trigger + * - \ref EADC_PWM0TG5_TRIGGER : PWM0TG5 trigger + * - \ref EADC_PWM1TG0_TRIGGER : PWM1TG0 trigger + * - \ref EADC_PWM1TG1_TRIGGER : PWM1TG1 trigger + * - \ref EADC_PWM1TG2_TRIGGER : PWM1TG2 trigger + * - \ref EADC_PWM1TG3_TRIGGER : PWM1TG3 trigger + * - \ref EADC_PWM1TG4_TRIGGER : PWM1TG4 trigger + * - \ref EADC_PWM1TG5_TRIGGER : PWM1TG5 trigger + * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15. + * @return None + * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source. + * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT). + */ +void EADC_ConfigSampleModule(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerSrc, \ + uint32_t u32Channel) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk); + eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel); +} + + +/** + * @brief Set trigger delay time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF. + * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are: + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16 + * @return None + * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15). + * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period. + */ +void EADC_SetTriggerDelayTime(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerDelayTime, \ + uint32_t u32DelayClockDivider) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk); + eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider); +} + +/** + * @brief Set ADC extend sample time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF. + * @return None + * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, + * user can extend A/D sampling time after trigger source is coming to get enough sampling time. + */ +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime) +{ + eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk; + + eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos); + +} + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/ebi.c b/bsp/nuvoton_m487/libraries/StdDriver/src/ebi.c new file mode 100644 index 00000000000..36aa0cea9b1 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/ebi.c @@ -0,0 +1,194 @@ +/**************************************************************************//** + * @file ebi.c + * @version V3.00 + * @brief M480 series External Bus Interface(EBI) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Initialize EBI for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode Set EBI bus operate mode. Valid values are: + * - \ref EBI_OPMODE_NORMAL + * - \ref EBI_OPMODE_CACCESS + * - \ref EBI_OPMODE_ADSEPARATE + * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are: + * - \ref EBI_CS_ACTIVE_HIGH + * - \ref EBI_CS_ACTIVE_LOW + * + * @return None + * + * @details This function is used to open specify EBI bank with different bus width, timing setting and \n + * active level of CS pin to access EBI device. + * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register. + */ +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index0 ); + volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 ); + + if(u32DataWidth == EBI_BUSWIDTH_8BIT) + { + *pu32EBICTL &= ~EBI_CTL_DW16_Msk; + } + else + { + *pu32EBICTL |= EBI_CTL_DW16_Msk; + } + + *pu32EBICTL |= u32BusMode; + + switch(u32TimingClass) + { + case EBI_TIMING_FASTEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_VERYFAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_FAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_NORMAL: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_SLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_VERYSLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_SLOWEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + default: + *pu32EBICTL &= ~EBI_CTL_EN_Msk; + break; + } +} + +/** + * @brief Disable EBI on specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * + * @return None + * + * @details This function is used to close specify EBI function. + */ +void EBI_Close(uint32_t u32Bank) +{ + uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index ); + + *pu32EBICTL &= ~EBI_CTL_EN_Msk; +} + +/** + * @brief Set EBI Bus Timing for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting. + * @param[in] u32MclkDiv Divider for MCLK. Valid values are: + * - \ref EBI_MCLKDIV_1 + * - \ref EBI_MCLKDIV_2 + * - \ref EBI_MCLKDIV_4 + * - \ref EBI_MCLKDIV_8 + * - \ref EBI_MCLKDIV_16 + * - \ref EBI_MCLKDIV_32 + * - \ref EBI_MCLKDIV_64 + * - \ref EBI_MCLKDIV_128 + * + * @return None + * + * @details This function is used to configure specify EBI bus timing for access EBI device. + */ +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index0 ); + volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 ); + + *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos); + *pu32EBITCTL = u32TimingConfig; +} + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/ecap.c b/bsp/nuvoton_m487/libraries/StdDriver/src/ecap.c new file mode 100644 index 00000000000..5287e6b3f90 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/ecap.c @@ -0,0 +1,117 @@ +/**************************************************************************//** + * @file ecap.c + * @version V3.00 + * @brief Enhanced Input Capture Timer (ECAP) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions + @{ +*/ + +/** + * @brief Enable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @param[in] u32FuncMask Input capture function select + * - \ref ECAP_DISABLE_COMPARE + * - \ref ECAP_COMPARE_FUNCTION + * @return None + * @details This macro enable input capture function and select compare and reload function. + */ +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask) +{ + /* Clear Input capture mode*/ + ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk); + + /* Enable Input Capture and set mode */ + ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask); +} + + + +/** + * @brief Disable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @return None + * @details This macro disable input capture function. + */ +void ECAP_Close(ECAP_T* ecap) +{ + /* Disable Input Capture*/ + ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk; +} + +/** + * @brief This macro is used to enable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel Mask + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will enable the input channel_n interrupt. + */ +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Enable input channel interrupt */ + ecap->CTL0 |= (u32Mask); + + /* Enable NVIC ECAP IRQ */ + if(ecap == (ECAP_T*)ECAP0) + { + NVIC_EnableIRQ((IRQn_Type)ECAP0_IRQn); + } + else + { + NVIC_EnableIRQ((IRQn_Type)ECAP1_IRQn); + } +} + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel number + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will disable the input channel_n interrupt. + */ +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Disable input channel interrupt */ + ecap->CTL0 &= ~(u32Mask); + + /* Disable NVIC ECAP IRQ */ + if(ecap == (ECAP_T*)ECAP0) + { + NVIC_DisableIRQ((IRQn_Type)ECAP0_IRQn); + } + else + { + NVIC_DisableIRQ((IRQn_Type)ECAP1_IRQn); + } +} + +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/emac.c b/bsp/nuvoton_m487/libraries/StdDriver/src/emac.c new file mode 100644 index 00000000000..73598f5cded --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/emac.c @@ -0,0 +1,985 @@ +/**************************************************************************//** + * @file emac.c + * @version V1.00 + * @brief M480 EMAC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EMAC_Driver EMAC Driver + @{ +*/ + + +/* Below are structure, definitions, static variables used locally by EMAC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ + +/** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants + @{ +*/ + +/* PHY Register Description */ +#define PHY_CNTL_REG 0x00UL /*!< PHY control register address */ +#define PHY_STATUS_REG 0x01UL /*!< PHY status register address */ +#define PHY_ID1_REG 0x02UL /*!< PHY ID1 register */ +#define PHY_ID2_REG 0x03UL /*!< PHY ID2 register */ +#define PHY_ANA_REG 0x04UL /*!< PHY auto-negotiation advertisement register */ +#define PHY_ANLPA_REG 0x05UL /*!< PHY auto-negotiation link partner availability register */ +#define PHY_ANE_REG 0x06UL /*!< PHY auto-negotiation expansion register */ + +/* PHY Control Register */ +#define PHY_CNTL_RESET_PHY (1UL << 15UL) +#define PHY_CNTL_DR_100MB (1UL << 13UL) +#define PHY_CNTL_ENABLE_AN (1UL << 12UL) +#define PHY_CNTL_POWER_DOWN (1UL << 11UL) +#define PHY_CNTL_RESTART_AN (1UL << 9UL) +#define PHY_CNTL_FULLDUPLEX (1UL << 8UL) + +/* PHY Status Register */ +#define PHY_STATUS_AN_COMPLETE (1UL << 5UL) +#define PHY_STATUS_LINK_VALID (1UL << 2UL) + +/* PHY Auto-negotiation Advertisement Register */ +#define PHY_ANA_DR100_TX_FULL (1UL << 8UL) +#define PHY_ANA_DR100_TX_HALF (1UL << 7UL) +#define PHY_ANA_DR10_TX_FULL (1UL << 6UL) +#define PHY_ANA_DR10_TX_HALF (1UL << 5UL) +#define PHY_ANA_IEEE_802_3_CSMA_CD (1UL << 0UL) + +/* PHY Auto-negotiation Link Partner Advertisement Register */ +#define PHY_ANLPA_DR100_TX_FULL (1UL << 8UL) +#define PHY_ANLPA_DR100_TX_HALF (1UL << 7UL) +#define PHY_ANLPA_DR10_TX_FULL (1UL << 6UL) +#define PHY_ANLPA_DR10_TX_HALF (1UL << 5UL) + +/* EMAC Tx/Rx descriptor's owner bit */ +#define EMAC_DESC_OWN_EMAC 0x80000000UL /*!< Set owner to EMAC */ +#define EMAC_DESC_OWN_CPU 0x00000000UL /*!< Set owner to CPU */ + +/* Rx Frame Descriptor Status */ +#define EMAC_RXFD_RTSAS 0x0080UL /*!< Time Stamp Available */ +#define EMAC_RXFD_RP 0x0040UL /*!< Runt Packet */ +#define EMAC_RXFD_ALIE 0x0020UL /*!< Alignment Error */ +#define EMAC_RXFD_RXGD 0x0010UL /*!< Receiving Good packet received */ +#define EMAC_RXFD_PTLE 0x0008UL /*!< Packet Too Long Error */ +#define EMAC_RXFD_CRCE 0x0002UL /*!< CRC Error */ +#define EMAC_RXFD_RXINTR 0x0001UL /*!< Interrupt on receive */ + +/* Tx Frame Descriptor's Control bits */ +#define EMAC_TXFD_TTSEN 0x08UL /*!< Tx time stamp enable */ +#define EMAC_TXFD_INTEN 0x04UL /*!< Tx interrupt enable */ +#define EMAC_TXFD_CRCAPP 0x02UL /*!< Append CRC */ +#define EMAC_TXFD_PADEN 0x01UL /*!< Padding mode enable */ + +/* Tx Frame Descriptor Status */ +#define EMAC_TXFD_TXINTR 0x0001UL /*!< Interrupt on Transmit */ +#define EMAC_TXFD_DEF 0x0002UL /*!< Transmit deferred */ +#define EMAC_TXFD_TXCP 0x0008UL /*!< Transmission Completion */ +#define EMAC_TXFD_EXDEF 0x0010UL /*!< Exceed Deferral */ +#define EMAC_TXFD_NCS 0x0020UL /*!< No Carrier Sense Error */ +#define EMAC_TXFD_TXABT 0x0040UL /*!< Transmission Abort */ +#define EMAC_TXFD_LC 0x0080UL /*!< Late Collision */ +#define EMAC_TXFD_TXHA 0x0100UL /*!< Transmission halted */ +#define EMAC_TXFD_PAU 0x0200UL /*!< Paused */ +#define EMAC_TXFD_SQE 0x0400UL /*!< SQE error */ +#define EMAC_TXFD_TTSAS 0x0800UL /*!< Time Stamp available */ + +/*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */ + +/** @addtogroup EMAC_EXPORTED_TYPEDEF EMAC Exported Type Defines + @{ +*/ + +/** Tx/Rx buffer descriptor structure */ +typedef struct +{ + uint32_t u32Status1; /*!< Status word 1 */ + uint32_t u32Data; /*!< Pointer to data buffer */ + uint32_t u32Status2; /*!< Status word 2 */ + uint32_t u32Next; /*!< Pointer to next descriptor */ + uint32_t u32Backup1; /*!< For backup descriptor fields over written by time stamp */ + uint32_t u32Backup2; /*!< For backup descriptor fields over written by time stamp */ +} EMAC_DESCRIPTOR_T; + +/** Tx/Rx buffer structure */ +typedef struct +{ + uint8_t au8Buf[1520]; +} EMAC_FRAME_T; + +/*@}*/ /* end of group EMAC_EXPORTED_TYPEDEF */ + +/* local variables */ +static volatile EMAC_DESCRIPTOR_T rx_desc[EMAC_RX_DESC_SIZE]; +static volatile EMAC_FRAME_T rx_buf[EMAC_RX_DESC_SIZE]; +static volatile EMAC_DESCRIPTOR_T tx_desc[EMAC_TX_DESC_SIZE]; +static volatile EMAC_FRAME_T tx_buf[EMAC_TX_DESC_SIZE]; + + +static uint32_t u32CurrentTxDesc, u32NextTxDesc, u32CurrentRxDesc; +static uint32_t s_u32EnableTs = 0UL; + +static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data); +static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr); +static void EMAC_PhyInit(void); +static void EMAC_TxDescInit(void); +static void EMAC_RxDescInit(void); +static uint32_t EMAC_Subsec2Nsec(uint32_t subsec); +static uint32_t EMAC_Nsec2Subsec(uint32_t nsec); + +/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions + @{ +*/ + +/** + * @brief Trigger EMAC Rx function + * @param None + * @return None + */ +#define EMAC_TRIGGER_RX() do{EMAC->RXST = 0UL;}while(0) + +/** + * @brief Trigger EMAC Tx function + * @param None + * @return None + */ +#define EMAC_TRIGGER_TX() do{EMAC->TXST = 0UL;}while(0) + + +/** + * @brief Write PHY register + * @param[in] u32Reg PHY register number + * @param[in] u32Addr PHY address, this address is board dependent + * @param[in] u32Data data to write to PHY register + * @return None + */ +static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data) +{ + /* Set data register */ + EMAC->MIIMDAT = u32Data ; + /* Set PHY address, PHY register address, busy bit and write bit */ + EMAC->MIIMCTL = u32Reg | (u32Addr << 8) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MIIMCTL_MDCON_Msk; + /* Wait write complete by polling busy bit. */ + while(EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) + { + ; + } + +} + +/** + * @brief Read PHY register + * @param[in] u32Reg PHY register number + * @param[in] u32Addr PHY address, this address is board dependent + * @return Value read from PHY register + */ +static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr) +{ + /* Set PHY address, PHY register address, busy bit */ + EMAC->MIIMCTL = u32Reg | (u32Addr << EMAC_MIIMCTL_PHYADDR_Pos) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk; + /* Wait read complete by polling busy bit */ + while(EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk) + { + ; + } + /* Get return data */ + return EMAC->MIIMDAT; +} + +/** + * @brief Initialize PHY chip, check for the auto-negotiation result. + * @param None + * @return None + */ +static void EMAC_PhyInit(void) +{ + uint32_t reg; + uint32_t i = 0UL; + + /* Reset Phy Chip */ + EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, PHY_CNTL_RESET_PHY); + + /* Wait until reset complete */ + while (1) + { + reg = EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) ; + if ((reg & PHY_CNTL_RESET_PHY)==0UL) + { + break; + } + } + while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID)) + { + if(i++ > 80000UL) /* Cable not connected */ + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + break; + } + } + + if(i <= 80000UL) + { + /* Configure auto negotiation capability */ + EMAC_MdioWrite(PHY_ANA_REG, EMAC_PHY_ADDR, PHY_ANA_DR100_TX_FULL | + PHY_ANA_DR100_TX_HALF | + PHY_ANA_DR10_TX_FULL | + PHY_ANA_DR10_TX_HALF | + PHY_ANA_IEEE_802_3_CSMA_CD); + /* Restart auto negotiation */ + EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) | PHY_CNTL_RESTART_AN); + + /* Wait for auto-negotiation complete */ + while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_AN_COMPLETE)) + { + ; + } + /* Check link valid again. Some PHYs needs to check result after link valid bit set */ + while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID)) + { + ; + } + + /* Check link partner capability */ + reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ; + if (reg & PHY_ANLPA_DR100_TX_FULL) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + } + else if (reg & PHY_ANLPA_DR100_TX_HALF) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + } + else if (reg & PHY_ANLPA_DR10_TX_FULL) + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + } + else + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + } + } +} + +/** + * @brief Initial EMAC Tx descriptors and get Tx descriptor base address + * @param None + * @return None + */ +static void EMAC_TxDescInit(void) +{ + uint32_t i; + + /* Get Frame descriptor's base address. */ + EMAC->TXDSA = (uint32_t)&tx_desc[0]; + u32NextTxDesc = u32CurrentTxDesc = (uint32_t)&tx_desc[0]; + + for(i = 0UL; i < EMAC_TX_DESC_SIZE; i++) + { + + if(s_u32EnableTs) + { + tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN; + } + else + { + tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN | EMAC_TXFD_TTSEN; + } + tx_desc[i].u32Data = (uint32_t)((uint32_t)&tx_buf[i]); + tx_desc[i].u32Backup1 = tx_desc[i].u32Data; + tx_desc[i].u32Status2 = 0UL; + tx_desc[i].u32Next = (uint32_t)&tx_desc[(i + 1UL) % EMAC_TX_DESC_SIZE]; + tx_desc[i].u32Backup2 = tx_desc[i].u32Next; + + } + +} + + +/** + * @brief Initial EMAC Rx descriptors and get Rx descriptor base address + * @param None + * @return None + */ +static void EMAC_RxDescInit(void) +{ + + uint32_t i; + + /* Get Frame descriptor's base address. */ + EMAC->RXDSA = (uint32_t)&rx_desc[0]; + u32CurrentRxDesc = (uint32_t)&rx_desc[0]; + + for(i = 0UL; i < EMAC_RX_DESC_SIZE; i++) + { + rx_desc[i].u32Status1 = EMAC_DESC_OWN_EMAC; + rx_desc[i].u32Data = (uint32_t)((uint32_t)&rx_buf[i]); + rx_desc[i].u32Backup1 = rx_desc[i].u32Data; + rx_desc[i].u32Status2 = 0UL; + rx_desc[i].u32Next = (uint32_t)&rx_desc[(i + 1UL) % EMAC_RX_DESC_SIZE]; + rx_desc[i].u32Backup2 = rx_desc[i].u32Next; + } + +} + +/** + * @brief Convert subsecond value to nano second + * @param[in] subsec Subsecond value to be convert + * @return Nano second + */ +static uint32_t EMAC_Subsec2Nsec(uint32_t subsec) +{ + /* 2^31 subsec == 10^9 ns */ + uint64_t i; + i = 1000000000ull * (uint64_t)subsec; + i >>= 31; + return((uint32_t)i); +} + +/** + * @brief Convert nano second to subsecond value + * @param[in] nsec Nano second to be convert + * @return Subsecond + */ +static uint32_t EMAC_Nsec2Subsec(uint32_t nsec) +{ + /* 10^9 ns = 2^31 subsec */ + uint64_t i; + i = (1ull << 31) * nsec; + i /= 1000000000ull; + return((uint32_t)i); +} + + +/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */ + + + +/** @endcond HIDDEN_SYMBOLS */ + + +/** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions + @{ +*/ + + +/** + * @brief Initialize EMAC interface, including descriptors, MAC address, and PHY. + * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address + * @return None + * @note This API configures EMAC to receive all broadcast and multicast packets, but could configure to other settings with + * \ref EMAC_ENABLE_RECV_BCASTPKT, \ref EMAC_DISABLE_RECV_BCASTPKT, \ref EMAC_ENABLE_RECV_MCASTPKT, and \ref EMAC_DISABLE_RECV_MCASTPKT + * @note Receive(RX) and transmit(TX) are not enabled yet, application must call \ref EMAC_ENABLE_RX and \ref EMAC_ENABLE_TX to + * enable receive and transmit function. + */ +void EMAC_Open(uint8_t *pu8MacAddr) +{ + /* Enable transmit and receive descriptor */ + EMAC_TxDescInit(); + EMAC_RxDescInit(); + + /* Set the CAM Control register and the MAC address value */ + EMAC_SetMacAddr(pu8MacAddr); + + /* Configure the MAC interrupt enable register. */ + EMAC->INTEN = EMAC_INTEN_RXIEN_Msk | + EMAC_INTEN_TXIEN_Msk | + EMAC_INTEN_RXGDIEN_Msk | + EMAC_INTEN_TXCPIEN_Msk | + EMAC_INTEN_RXBEIEN_Msk | + EMAC_INTEN_TXBEIEN_Msk | + EMAC_INTEN_RDUIEN_Msk | + EMAC_INTEN_TSALMIEN_Msk | + EMAC_INTEN_WOLIEN_Msk; + + /* Configure the MAC control register. */ + EMAC->CTL = EMAC_CTL_STRIPCRC_Msk | + EMAC_CTL_RMIIEN_Msk; + + /* Accept packets for us and all broadcast and multicast packets */ + EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk | + EMAC_CAMCTL_AMP_Msk | + EMAC_CAMCTL_ABP_Msk; + + /* Limit the max receive frame length to 1514 + 4 */ + EMAC->MRFL = 1518; + EMAC_PhyInit(); +} + +/** + * @brief This function stop all receive and transmit activity and disable MAC interface + * @param None + * @return None + */ + +void EMAC_Close(void) +{ + EMAC->CTL |= EMAC_CTL_RST_Msk; + while(EMAC->CTL & EMAC_CTL_RST_Msk) {} +} + +/** + * @brief Set the device MAC address + * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address + * @return None + */ +void EMAC_SetMacAddr(uint8_t *pu8MacAddr) +{ + EMAC_EnableCamEntry(0UL, pu8MacAddr); + +} + +/** + * @brief Fill a CAM entry for MAC address comparison. + * @param[in] u32Entry MAC entry to fill. Entry 0 is used to store device MAC address, do not overwrite the setting in it. + * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address + * @return None + */ +void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[]) +{ + uint32_t u32Lsw, u32Msw; + uint32_t reg; + u32Lsw = (uint32_t)(((uint32_t)pu8MacAddr[4] << 24) | + ((uint32_t)pu8MacAddr[5] << 16)); + u32Msw = (uint32_t)(((uint32_t)pu8MacAddr[0] << 24)| + ((uint32_t)pu8MacAddr[1] << 16)| + ((uint32_t)pu8MacAddr[2] << 8)| + (uint32_t)pu8MacAddr[3]); + + reg = (uint32_t)&EMAC->CAM0M + u32Entry * 2UL * 4UL; + *(uint32_t volatile *)reg = u32Msw; + reg = (uint32_t)&EMAC->CAM0L + u32Entry * 2UL * 4UL; + *(uint32_t volatile *)reg = u32Lsw; + + EMAC->CAMEN |= (1UL << u32Entry); +} + +/** + * @brief Disable a specified CAM entry + * @param[in] u32Entry CAM entry to be disabled + * @return None + */ +void EMAC_DisableCamEntry(uint32_t u32Entry) +{ + EMAC->CAMEN &= ~(1UL << u32Entry); +} + + +/** + * @brief Receive an Ethernet packet + * @param[in] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed) + * @param[in] pu32Size Received packet size (without 4 byte CRC). + * @return Packet receive success or not + * @retval 0 No packet available for receive + * @retval 1 A packet is received + * @note Return 0 doesn't guarantee the packet will be sent and received successfully. + */ +uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t u32Count = 0UL; + + /* Clear Rx interrupt flags */ + reg = EMAC->INTSTS; + EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all RX related interrupt status */ + + if (reg & EMAC_INTSTS_RXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while(1) {} + } + else + { + + /* Get Rx Frame Descriptor */ + desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + /* If we reach last recv Rx descriptor, leave the loop */ + if ((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) /* ownership=CPU */ + { + + status = desc->u32Status1 >> 16; + + /* If Rx frame is good, process received frame */ + if(status & EMAC_RXFD_RXGD) + { + /* lower 16 bit in descriptor status1 stores the Rx packet length */ + *pu32Size = desc->u32Status1 & 0xFFFFUL; + memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size); + u32Count = 1UL; + } + else + { + /* Save Error status if necessary */ + if (status & EMAC_RXFD_RP) {} + if (status & EMAC_RXFD_ALIE) {} + if (status & EMAC_RXFD_PTLE) {} + if (status & EMAC_RXFD_CRCE) {} + } + } + } + return(u32Count); +} + +/** + * @brief Receive an Ethernet packet and the time stamp while it's received + * @param[out] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed) + * @param[out] pu32Size Received packet size (without 4 byte CRC). + * @param[out] pu32Sec Second value while packet received + * @param[out] pu32Nsec Nano second value while packet received + * @return Packet receive success or not + * @retval 0 No packet available for receive + * @retval 1 A packet is received + * @note Return 0 doesn't guarantee the packet will be sent and received successfully. + * @note Largest Ethernet packet is 1514 bytes after stripped CRC, application must give + * a buffer large enough to store such packet + */ +uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t u32Count = 0UL; + + /* Clear Rx interrupt flags */ + reg = EMAC->INTSTS; + EMAC->INTSTS = reg & 0xFFFFUL; /* Clear all Rx related interrupt status */ + + if (reg & EMAC_INTSTS_RXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while(1) {} + } + else + { + + /* Get Rx Frame Descriptor */ + desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + /* If we reach last recv Rx descriptor, leave the loop */ + if(EMAC->CRXDSA != (uint32_t)desc) + { + if ((desc->u32Status1 | EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) /* ownership=CPU */ + { + + status = desc->u32Status1 >> 16; + + /* If Rx frame is good, process received frame */ + if(status & EMAC_RXFD_RXGD) + { + /* lower 16 bit in descriptor status1 stores the Rx packet length */ + *pu32Size = desc->u32Status1 & 0xFFFFUL; + memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size); + + *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */ + *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */ + + u32Count = 1UL; + } + else + { + /* Save Error status if necessary */ + if (status & EMAC_RXFD_RP) {} + if (status & EMAC_RXFD_ALIE) {} + if (status & EMAC_RXFD_PTLE) {} + if (status & EMAC_RXFD_CRCE) {} + } + } + } + } + return(u32Count); +} + +/** + * @brief Clean up process after a packet is received + * @param None + * @return None + * @details EMAC Rx interrupt service routine \b must call this API to release the resource use by receive process + * @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1 + */ +void EMAC_RecvPktDone(void) +{ + EMAC_DESCRIPTOR_T *desc; + /* Get Rx Frame Descriptor */ + desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc; + + /* Restore descriptor link list and data pointer they will be overwrite if time stamp enabled */ + desc->u32Data = desc->u32Backup1; + desc->u32Next = desc->u32Backup2; + + /* Get Next Frame Descriptor pointer to process */ + desc = (EMAC_DESCRIPTOR_T *)desc->u32Next; + + /* Save last processed Rx descriptor */ + u32CurrentRxDesc = (uint32_t)desc; + + /* Change ownership to DMA for next use */ + desc->u32Status1 |= EMAC_DESC_OWN_EMAC; + + EMAC_TRIGGER_RX(); +} + + +/** + * @brief Send an Ethernet packet + * @param[in] pu8Data Pointer to a buffer holds the packet to transmit + * @param[in] u32Size Packet size (without 4 byte CRC). + * @return Packet transmit success or not + * @retval 0 Transmit failed due to descriptor unavailable. + * @retval 1 Packet is copied to descriptor and triggered to transmit. + * @note Return 1 doesn't guarantee the packet will be sent and received successfully. + */ +uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status; + uint32_t ret = 0UL; + /* Get Tx frame descriptor & data pointer */ + desc = (EMAC_DESCRIPTOR_T *)u32NextTxDesc; + + status = desc->u32Status1; + + /* Check descriptor ownership */ + if((status & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) + { + memcpy((uint8_t *)desc->u32Data, pu8Data, u32Size); + + /* Set Tx descriptor transmit byte count */ + desc->u32Status2 = u32Size; + + /* Change descriptor ownership to EMAC */ + desc->u32Status1 |= EMAC_DESC_OWN_EMAC; + + /* Get next Tx descriptor */ + u32NextTxDesc = (uint32_t)(desc->u32Next); + + /* Trigger EMAC to send the packet */ + EMAC_TRIGGER_TX(); + ret = 1UL; + } + return(ret); +} + + +/** + * @brief Clean up process after packet(s) are sent + * @param None + * @return Number of packet sent between two function calls + * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDoneTS to + * release the resource use by transmit process + */ +uint32_t EMAC_SendPktDone(void) +{ + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t last_tx_desc; + uint32_t u32Count = 0UL; + + reg = EMAC->INTSTS; + /* Clear Tx interrupt flags */ + EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk); + + + if (reg & EMAC_INTSTS_TXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while(1) {} + } + else + { + /* Process the descriptor(s). */ + last_tx_desc = EMAC->CTXDSA ; + /* Get our first descriptor to process */ + desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc; + do + { + /* Descriptor ownership is still EMAC, so this packet haven't been send. */ + if(desc->u32Status1 & EMAC_DESC_OWN_EMAC) + { + break; + } + /* Get Tx status stored in descriptor */ + status = desc->u32Status2 >> 16UL; + if (status & EMAC_TXFD_TXCP) + { + u32Count++; + } + else + { + /* Do nothing here on error. */ + if (status & EMAC_TXFD_TXABT) {} + if (status & EMAC_TXFD_DEF) {} + if (status & EMAC_TXFD_PAU) {} + if (status & EMAC_TXFD_EXDEF) {} + if (status & EMAC_TXFD_NCS) {} + if (status & EMAC_TXFD_SQE) {} + if (status & EMAC_TXFD_LC) {} + if (status & EMAC_TXFD_TXHA) {} + } + + /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */ + desc->u32Data = desc->u32Backup1; + desc->u32Next = desc->u32Backup2; + /* go to next descriptor in link */ + desc = (EMAC_DESCRIPTOR_T *)desc->u32Next; + } + while (last_tx_desc != (uint32_t)desc); /* If we reach last sent Tx descriptor, leave the loop */ + /* Save last processed Tx descriptor */ + u32CurrentTxDesc = (uint32_t)desc; + } + return(u32Count); +} + +/** + * @brief Clean up process after a packet is sent, and get the time stamp while packet is sent + * @param[in] pu32Sec Second value while packet sent + * @param[in] pu32Nsec Nano second value while packet sent + * @return If a packet sent successfully + * @retval 0 No packet sent successfully, and the value in *pu32Sec and *pu32Nsec are meaningless + * @retval 1 A packet sent successfully, and the value in *pu32Sec and *pu32Nsec is the time stamp while packet sent + * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDone to + * release the resource use by transmit process + */ +uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec) +{ + + EMAC_DESCRIPTOR_T *desc; + uint32_t status, reg; + uint32_t u32Count = 0UL; + + reg = EMAC->INTSTS; + /* Clear Tx interrupt flags */ + EMAC->INTSTS = reg & (0xFFFF0000UL & ~EMAC_INTSTS_TSALMIF_Msk); + + + if (reg & EMAC_INTSTS_TXBEIF_Msk) + { + /* Bus error occurred, this is usually a bad sign about software bug and will occur again... */ + while(1) {} + } + else + { + /* Process the descriptor. + Get our first descriptor to process */ + desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc; + + /* Descriptor ownership is still EMAC, so this packet haven't been send. */ + if((desc->u32Status1 & EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) + { + /* Get Tx status stored in descriptor */ + status = desc->u32Status2 >> 16UL; + if (status & EMAC_TXFD_TXCP) + { + u32Count = 1UL; + *pu32Sec = desc->u32Next; /* second stores in descriptor's NEXT field */ + *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */ + } + else + { + /* Do nothing here on error. */ + if (status & EMAC_TXFD_TXABT) {} + if (status & EMAC_TXFD_DEF) {} + if (status & EMAC_TXFD_PAU) {} + if (status & EMAC_TXFD_EXDEF) {} + if (status & EMAC_TXFD_NCS) {} + if (status & EMAC_TXFD_SQE) {} + if (status & EMAC_TXFD_LC) {} + if (status & EMAC_TXFD_TXHA) {} + } + + /* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */ + desc->u32Data = desc->u32Backup1; + desc->u32Next = desc->u32Backup2; + /* go to next descriptor in link */ + desc = (EMAC_DESCRIPTOR_T *)desc->u32Next; + + /* Save last processed Tx descriptor */ + u32CurrentTxDesc = (uint32_t)desc; + } + } + + return(u32Count); +} + +/** + * @brief Enable IEEE1588 time stamp function and set current time + * @param[in] u32Sec Second value + * @param[in] u32Nsec Nano second value + * @return None + */ +void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec) +{ + double f; + uint32_t reg; + EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk; + EMAC->UPDSEC = u32Sec; /* Assume current time is 0 sec + 0 nano sec */ + EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + + /* PTP source clock is 160MHz (Real chip using PLL). Each tick is 6.25ns + Assume we want to set each tick to 100ns. + Increase register = (100 * 2^31) / (10^9) = 214.71 =~ 215 = 0xD7 + Addend register = 2^32 * tick_freq / (160MHz), where tick_freq = (2^31 / 215) MHz + From above equation, addend register = 2^63 / (160M * 215) ~= 268121280 = 0xFFB34C0 + So: + EMAC->TSIR = 0xD7; + EMAC->TSAR = 0x1E70C600; */ + f = (100.0 * 2147483648.0) / (1000000000.0) + 0.5; + EMAC->TSINC = (reg = (uint32_t)f); + f = (double)9223372036854775808.0 / ((double)(CLK_GetHCLKFreq()) * (double)reg); + EMAC->TSADDEND = (uint32_t)f; + EMAC->TSCTL |= (EMAC_TSCTL_TSUPDATE_Msk | EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); /* Fine update */ +} + +/** + * @brief Disable IEEE1588 time stamp function + * @param None + * @return None + */ +void EMAC_DisableTS(void) +{ + EMAC->TSCTL = 0UL; +} + +/** + * @brief Get current time stamp + * @param[out] pu32Sec Current second value + * @param[out] pu32Nsec Current nano second value + * @return None + */ +void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec) +{ + /* Must read TSLSR firstly. Hardware will preserve TSMSR value at the time TSLSR read. */ + *pu32Nsec = EMAC_Subsec2Nsec(EMAC->TSSUBSEC); + *pu32Sec = EMAC->TSSEC; +} + +/** + * @brief Set current time stamp + * @param[in] u32Sec Second value + * @param[in] u32Nsec Nano second value + * @return None + */ +void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec) +{ + /* Disable time stamp counter before update time value (clear EMAC_TSCTL_TSIEN_Msk) */ + EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk; + EMAC->UPDSEC = u32Sec; + EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + EMAC->TSCTL |= (EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); + +} + +/** + * @brief Enable alarm function and set alarm time + * @param[in] u32Sec Second value to trigger alarm + * @param[in] u32Nsec Nano second value to trigger alarm + * @return None + */ +void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec) +{ + + EMAC->ALMSEC = u32Sec; + EMAC->ALMSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + EMAC->TSCTL |= EMAC_TSCTL_TSALMEN_Msk; + +} + +/** + * @brief Disable alarm function + * @param None + * @return None + */ +void EMAC_DisableAlarm(void) +{ + + EMAC->TSCTL &= ~EMAC_TSCTL_TSALMEN_Msk; + +} + +/** + * @brief Add a offset to current time + * @param[in] u32Neg Offset is negative value (u32Neg == 1) or positive value (u32Neg == 0). + * @param[in] u32Sec Second value to add to current time + * @param[in] u32Nsec Nano second value to add to current time + * @return None + */ +void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec) +{ + EMAC->UPDSEC = u32Sec; + EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec); + if(u32Neg) + { + EMAC->UPDSUBSEC |= BIT31; /* Set bit 31 indicates this is a negative value */ + } + EMAC->TSCTL |= EMAC_TSCTL_TSUPDATE_Msk; + +} + +/** + * @brief Check Ethernet link status + * @param None + * @return Current link status, could be one of following value. + * - \ref EMAC_LINK_DOWN + * - \ref EMAC_LINK_100F + * - \ref EMAC_LINK_100H + * - \ref EMAC_LINK_10F + * - \ref EMAC_LINK_10H + * @note This API should be called regularly to sync EMAC setting with real connection status + */ +uint32_t EMAC_CheckLinkStatus(void) +{ + uint32_t reg, ret = EMAC_LINK_DOWN; + + /* Check link valid again */ + if(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID) + { + /* Check link partner capability */ + reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ; + if (reg & PHY_ANLPA_DR100_TX_FULL) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_100F; + } + else if (reg & PHY_ANLPA_DR100_TX_HALF) + { + EMAC->CTL |= EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_100H; + } + else if (reg & PHY_ANLPA_DR10_TX_FULL) + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL |= EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_10F; + } + else + { + EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; + EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; + ret = EMAC_LINK_10H; + } + } + return ret; +} + + +/*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EMAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/epwm.c b/bsp/nuvoton_m487/libraries/StdDriver/src/epwm.c new file mode 100644 index 00000000000..61cc2f30e6c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/epwm.c @@ -0,0 +1,1438 @@ +/**************************************************************************//** + * @file epwm.c + * @version V3.00 + * $Revision: 3 $ + * $Date: 16/06/23 11:14a $ + * @brief M480 series EPWM driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + + +/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions + @{ +*/ + +/** + * @brief Configure EPWM capture and get the nearest unit time. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure EPWM capture and get the nearest unit time. + */ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32EPWMClockSrc; + uint32_t u32NearestUnitTimeNsec; + uint32_t u16Prescale = 1U, u16CNR = 0xFFFFU; + + if(epwm == EPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk; + } + else /* (epwm == EPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32EPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(epwm == EPWM0) + { + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (epwm == EPWM1) */ + { + u32EPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + u32EPWMClockSrc /= 1000U; + for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) + { + uint32_t u32Exit = 0U; + u32NearestUnitTimeNsec = (1000000U * u16Prescale) / u32EPWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if(u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + if(!((1000000U * (u16Prescale + 1U) > (u32NearestUnitTimeNsec * u32EPWMClockSrc)))) + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + } + else + { + u32Exit = 1U; + } + if (u32Exit == 1U) + { + break; + } + else {} + } + + /* convert to real register value */ + /* every two channels share a prescaler */ + u16Prescale -= 1U; + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u16Prescale); + + /* set EPWM to down count type(edge aligned) */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~((1UL << EPWM_CTL1_CNTTYPE0_Pos) << (u32ChannelNum << 1U))) | (1UL << (u32ChannelNum << 1U)); + /* set EPWM to auto-reload mode */ + (epwm)->CTL1 &= ~((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum); + EPWM_SET_CNR(epwm, u32ChannelNum, u16CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect + * existing frequency of other channel. + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32Src; + uint32_t u32EPWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + if(epwm == EPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk; + } + else /* (epwm == EPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32EPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(epwm == EPWM0) + { + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (epwm == EPWM1) */ + { + u32EPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */ + { + i = (u32EPWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i < (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */ + i = u32EPWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + /* every two channels share a prescaler */ + u32Prescale -= 1U; + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale); + /* set EPWM to up counter type(edge aligned) and auto-reload mode */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~(((1UL << EPWM_CTL1_CNTTYPE0_Pos) << (u32ChannelNum << 1U))|((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum))); + + u32CNR -= 1U; + EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR); + EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 100U); + + (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~(((1UL << EPWM_WGCTL0_PRDPCTL0_Pos) | (1UL << EPWM_WGCTL0_ZPCTL0_Pos)) << (u32ChannelNum << 1U))) | \ + ((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos)); + (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~(((1UL << EPWM_WGCTL1_CMPDCTL0_Pos) | (1UL << EPWM_WGCTL1_CMPUCTL0_Pos)) << (u32ChannelNum << 1U))) | \ + ((uint32_t)EPWM_OUTPUT_LOW << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL1_CMPUCTL0_Pos)); + + return(i); +} + +/** + * @brief Start EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to start EPWM module. + */ +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN |= u32ChannelMask; +} + +/** + * @brief Stop EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM module. + */ +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->PERIOD[i] = 0U; + } + } +} + +/** + * @brief Stop EPWM generation immediately by clear channel enable bit + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM generation immediately by clear channel enable bit. + */ +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN &= ~u32ChannelMask; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref EPWM_TRG_ADC_EVEN_ZERO + * - \ref EPWM_TRG_ADC_EVEN_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_ODD_ZERO + * - \ref EPWM_TRG_ADC_ODD_PERIOD + * - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_ODD_COMPARE_UP + * - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN + * @return None + * @details This function is used to enable selected channel to trigger ADC. + */ +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4U) + { + (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3U)); + (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) << 3U)); + (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) << 3U)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger ADC. + */ +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4U) + { + (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3U)); + } + else + { + (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) << 3U)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag. + */ +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel. + */ +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum))?1UL:0UL); +} + +/** + * @brief Enable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions: + * - \ref EPWM_TRIGGER_DAC_ZERO + * - \ref EPWM_TRIGGER_DAC_PERIOD + * - \ref EPWM_TRIGGER_DAC_COMPARE_UP + * - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN + * @return None + * @details This function is used to enable selected channel to trigger DAC. + */ +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum); +} + +/** + * @brief Disable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger DAC. + */ +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | \ + EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum); +} + +/** + * @brief Clear selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @param[in] u32Condition The condition to trigger DAC. This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger DAC flag. + */ +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk; +} + +/** + * @brief Get selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @retval 0 The specified channel trigger DAC to start of conversion flag is not set + * @retval 1 The specified channel trigger DAC to start of conversion flag is set + * @details This function is used to get selected channel trigger DAC flag. + */ +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk)?1UL:0UL); +} + +/** + * @brief This function enable fault brake of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel + * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32BrakeSource Fault brake source, could be one of following source + * - \ref EPWM_FB_EDGE_ADCRM + * - \ref EPWM_FB_EDGE_ACMP0 + * - \ref EPWM_FB_EDGE_ACMP1 + * - \ref EPWM_FB_EDGE_BKP0 + * - \ref EPWM_FB_EDGE_BKP1 + * - \ref EPWM_FB_EDGE_SYS_CSS + * - \ref EPWM_FB_EDGE_SYS_BOD + * - \ref EPWM_FB_EDGE_SYS_RAM + * - \ref EPWM_FB_EDGE_SYS_COR + * - \ref EPWM_FB_LEVEL_ADCRM + * - \ref EPWM_FB_LEVEL_ACMP0 + * - \ref EPWM_FB_LEVEL_ACMP1 + * - \ref EPWM_FB_LEVEL_BKP0 + * - \ref EPWM_FB_LEVEL_BKP1 + * - \ref EPWM_FB_LEVEL_SYS_CSS + * - \ref EPWM_FB_LEVEL_SYS_BOD + * - \ref EPWM_FB_LEVEL_SYS_RAM + * - \ref EPWM_FB_LEVEL_SYS_COR + * @return None + * @details This function is used to enable fault brake of selected channel(s). + * The write-protection function should be disabled before using this function. + */ +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource) +{ + uint32_t i; + + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR)) + { + (epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk)); + (epwm)->FAILBRK |= (u32BrakeSource & 0xFU); + } + else + { + (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource; + } + } + + if(u32LevelMask & (1UL << i)) + { + if((i & 0x1U) == 0U) + { + /* set brake action as high level for even channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as high level for odd channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + else + { + if((i & 0x1U) == 0U) + { + /* set brake action as low level for even channel */ + (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as low level for odd channel */ + (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + } +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s). + */ +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN |= u32ChannelMask; + (epwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s). + */ +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN &= ~u32ChannelMask; + (epwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enable EPWM output generation of selected channel(s). + */ +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disable EPWM output generation of selected channel(s). + */ +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE. + * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either + * - \ref EPWM_CAPTURE_PDMA_RISING_LATCH + * - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH + * - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + * @note This function can only selects even or odd channel of pairs to do PDMA transfer. + */ +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode) +{ + uint32_t u32IsOddCh; + u32IsOddCh = u32ChannelNum & 0x1U; + (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1U) << 3U))) | \ + (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \ + u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Disables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + */ +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Enable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone. + * @return None + * @details This function is used to enable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + /* every two channels share the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTCNT_Msk; + (epwm)->DTCTL[(u32ChannelNum) >> 1U] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration; +} + +/** + * @brief Disable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + */ +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + /* every two channels shares the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTEN_Msk; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \ + (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL)); +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel. + */ +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((uint32_t)(EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel. + */ +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief This function enable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to enable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 |= (0x7UL << u32BrakeSource); +} + +/** + * @brief This function disable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to disable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource); +} + +/** + * @brief This function clear fault brake interrupt of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to clear fault brake interrupt of selected source. + * The write-protection function should be disabled before using this function. + */ +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource); +} + +/** + * @brief This function get fault brake interrupt flag of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source, could be either + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * @details This function is used to get fault brake interrupt flag of selected source. + */ +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + */ +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable period interrupt of selected channel. + */ +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear period interrupt of selected channel. + */ +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum); +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel. + */ +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable zero interrupt of selected channel. + */ +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable zero interrupt of selected channel. + */ +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear zero interrupt of selected channel. + */ +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Zero interrupt flag of specified channel + * @retval 0 Zero interrupt did not occur + * @retval 1 Zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + */ +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535. + * @param[in] u32IntAccSrc Interrupt flag accumulator source selection. + * - \ref EPWM_IFA_ZERO_POINT + * - \ref EPWM_IFA_PERIOD_POINT + * - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT + * - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable interrupt flag accumulator of selected channel. + */ +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc) +{ + (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \ + (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt) ); +} + +/** + * @brief Disable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to Disable interrupt flag accumulator of selected channel. + */ +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk)); +} + +/** + * @brief Enable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Clear interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTSTS = (1UL << (u32ChannelNum)); +} + +/** + * @brief Get interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 Accumulator interrupt did not occur + * @retval 1 Accumulator interrupt occurred + * @details This function is used to Get interrupt flag accumulator interrupt of selected channel. + */ +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Clear free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear free trigger duty interrupt flag of selected channel. + */ +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U)); +} + +/** + * @brief Get free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Free trigger duty interrupt did not occur + * @retval 1 Free trigger duty interrupt occurred + * @details This function is used to get free trigger duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U))) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Configure synchronization phase of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32SyncSrc EPWM synchronize source selection. + * - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR + * - \ref EPWM_SYNC_OUT_DISABLE + * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment after synchronizing. + * - \ref EPWM_PHS_DIR_DECREMENT + * - \ref EPWM_PHS_DIR_INCREMENT + * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535. + * @return None + * @details This function is used to configure synchronization phase of selected channel. + * @note Every two channels share the same setting. + */ +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase) +{ + /* every two channels shares the same setting */ + u32ChannelNum >>= 1U; + (epwm)->SYNC = (((epwm)->SYNC & ~(((3UL << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)) | ((1UL << EPWM_SYNC_PHSDIR0_Pos) << u32ChannelNum))) | \ + (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | ((u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U))); + (epwm)->PHS[(u32ChannelNum)] = u32StartPhase; +} + + +/** + * @brief Enable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U)); + } + } +} + +/** + * @brief Disable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U)); + } + } +} + +/** + * @brief Enable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector. + * The valid value is 0~7. + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM SYNC_IN noise filter function. + */ +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \ + ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk); +} + +/** + * @brief Disable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC_IN noise filter function. + */ +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm) +{ + (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk; +} + +/** + * @brief Enable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to enable EPWM SYNC input pin inverse function. + */ +void EPWM_EnableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk; +} + +/** + * @brief Disable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC input pin inverse function. + */ +void EPWM_DisableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk); +} + +/** + * @brief Set EPWM clock source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32ClkSrcSel EPWM external clock source. + * - \ref EPWM_CLKSRC_EPWM_CLK + * - \ref EPWM_CLKSRC_TIMER0 + * - \ref EPWM_CLKSRC_TIMER1 + * - \ref EPWM_CLKSRC_TIMER2 + * - \ref EPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set EPWM clock source. + * @note Every two channels share the same setting. + * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1. + */ +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1U) << 3U))) | \ + (u32ClkSrcSel << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Enable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM brake noise filter function. + */ +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3U))) | \ + (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3U)); +} + +/** + * @brief Disable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake noise filter function. + */ +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3U)); +} + +/** + * @brief Enable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to enable EPWM brake pin inverse function. + */ +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3U)); +} + +/** + * @brief Disable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake pin inverse function. + */ +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos)); +} + +/** + * @brief Set EPWM brake pin source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE. + * @return None + * @details This function is used to set EPWM brake pin source. + */ +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule) +{ + (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3U))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3U))); +} + +/** + * @brief Set EPWM leading edge blanking function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32TrigSrcSel Leading edge blanking source selection. + * - \ref EPWM_LEBCTL_SRCEN0 + * - \ref EPWM_LEBCTL_SRCEN2 + * - \ref EPWM_LEBCTL_SRCEN4 + * - \ref EPWM_LEBCTL_SRCEN0_2 + * - \ref EPWM_LEBCTL_SRCEN0_4 + * - \ref EPWM_LEBCTL_SRCEN2_4 + * - \ref EPWM_LEBCTL_SRCEN0_2_4 + * @param[in] u32TrigType Leading edge blanking trigger type. + * - \ref EPWM_LEBCTL_TRGTYPE_RISING + * - \ref EPWM_LEBCTL_TRGTYPE_FALLING + * - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING + * @param[in] u32BlankingCnt Leading Edge Blanking Counter. Valid values are between 1~512. + This counter value decides leading edge blanking window size, and this counter clock base is ECLK. + * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE). + * - \ref FALSE + * - \ref TRUE + * @return None + * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition. + * @note EPWM leading edge blanking function is only used for brake source from ACMP. + */ +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable) +{ + (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable); + /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */ + (epwm)->LEBCNT = (u32BlankingCnt) - 1U; +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + */ +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + */ +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum); +} + + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/fmc.c b/bsp/nuvoton_m487/libraries/StdDriver/src/fmc.c new file mode 100644 index 00000000000..82ecac75601 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/fmc.c @@ -0,0 +1,847 @@ +/**************************************************************************//** + * @file fmc.c + * @version V1.00 + * @brief M480 series FMC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include + +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + + +/** + * @brief Disable FMC ISP function. + * @return None + */ +void FMC_Close(void) +{ + FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk; +} + + +/** + * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 4096 bytes. + * @param[in] u32PageAddr Address of the flash page to be erased. + * It must be a 4096 bytes aligned address. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase(uint32_t u32PageAddr) +{ + int32_t ret = 0; + + if (u32PageAddr == FMC_SPROM_BASE) + { + ret = FMC_Erase_SPROM(); + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32PageAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + } + return ret; +} + + +/** + * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase SPROM. The page size is 4096 bytes. + * @return SPROM page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase_SPROM(void) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = FMC_SPROM_BASE; + FMC->ISPDAT = 0x0055AA03UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_BLOCK_ERASE command to erase a flash block. The block size is 4 pages. + * @param[in] u32BlockAddr Address of the flash block to be erased. + * It must be a 4 pages aligned address. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase_Block(uint32_t u32BlockAddr) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_BLOCK_ERASE; + FMC->ISPADDR = u32BlockAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block. + * @param[in] u32BankAddr Base address of the flash bank to be erased. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + */ +int32_t FMC_Erase_Bank(uint32_t u32BankAddr) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE; + FMC->ISPADDR = u32BankAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Get the current boot source. + * @return The current boot source. + * @retval 0 Is boot from APROM. + * @retval 1 Is boot from LDROM. + */ +int32_t FMC_GetBootSource (void) +{ + int32_t ret = 0; + + if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk) + { + ret = 1; + } + + return ret; +} + + +/** + * @brief Enable FMC ISP function + * @return None + */ +void FMC_Open(void) +{ + FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk; +} + + +/** + * @brief Execute FMC_ISPCMD_READ command to read a word from flash. + * @param[in] u32Addr Address of the flash location to be read. + * It must be a word aligned address. + * @return The word data read from specified flash address. + */ +uint32_t FMC_Read(uint32_t u32Addr) +{ + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = u32Addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + return FMC->ISPDAT; +} + + +/** + * @brief Execute FMC_ISPCMD_READ_64 command to read a double-word from flash. + * @param[in] u32addr Address of the flash location to be read. + * It must be a double-word aligned address. + * @param[out] u32data0 Place holder of word 0 read from flash address u32addr. + * @param[out] u32data1 Place holder of word 0 read from flash address u32addr+4. + * @return 0 Success + * @return -1 Failed + */ +int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + *u32data0 = FMC->MPDAT0; + *u32data1 = FMC->MPDAT1; + } + return ret; +} + + +/** + * @brief Get the base address of Data Flash if enabled. + * @retval The base address of Data Flash + */ +uint32_t FMC_ReadDataFlashBaseAddr(void) +{ + return FMC->DFBA; +} + +/** + * @brief Set boot source from LDROM or APROM after next software reset + * @param[in] i32BootSrc + * 1: Boot from LDROM + * 0: Boot from APROM + * @return None + * @details This function is used to switch APROM boot or LDROM boot. User need to call + * FMC_SetBootSource to select boot source first, then use CPU reset or + * System Reset Request to reset system. + */ +void FMC_SetBootSource(int32_t i32BootSrc) +{ + if(i32BootSrc) + { + FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */ + } + else + { + FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */ + } +} + +/** + * @brief Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash. + * @param[in] u32Addr Address of the flash location to be programmed. + * It must be a word aligned address. + * @param[in] u32Data The word data to be programmed. + * @return None + */ +void FMC_Write(uint32_t u32Addr, uint32_t u32Data) +{ + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = u32Data; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } +} + +/** + * @brief Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash. + * @param[in] u32addr Address of the flash location to be programmed. + * It must be a double-word aligned address. + * @param[in] u32data0 The word data to be programmed to flash address u32addr. + * @param[in] u32data1 The word data to be programmed to flash address u32addr+4. + * @return 0 Success + * @return -1 Failed + */ +int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64; + FMC->ISPADDR = u32addr; + FMC->MPDAT0 = u32data0; + FMC->MPDAT1 = u32data1; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + return ret; +} + + +/** + * @brief Program Multi-Word data into specified address of flash. + * @param[in] u32Addr Start flash address in APROM where the data chunk to be programmed into. + * This address must be 8-bytes aligned to flash address. + * @param[in] pu32Buf Buffer that carry the data chunk. + * @param[in] u32Len Length of the data chunk in bytes. + * @retval >=0 Number of data bytes were programmed. + * @return -1 Invalid address. + */ +int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len) +{ + int i, idx, retval = 0; + + if ((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0)) + { + return -1; + } + + u32Len = u32Len - (u32Len % 8); /* u32Len must be multiple of 8. */ + + idx = 0; + + while (u32Len >= 8) + { + FMC->ISPADDR = u32Addr; + FMC->MPDAT0 = pu32Buf[idx++]; + FMC->MPDAT1 = pu32Buf[idx++]; + FMC->MPDAT2 = pu32Buf[idx++]; + FMC->MPDAT3 = pu32Buf[idx++]; + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_MUL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + for (i = 16; i < FMC_MULTI_WORD_PROG_LEN; ) + { + while (FMC->MPSTS & (FMC_MPSTS_D0_Msk | FMC_MPSTS_D1_Msk)) + ; + retval += 8; + u32Len -= 8; + if (u32Len < 8) + { + return retval; + } + + if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk)) + { + /* printf(" [WARNING] busy cleared after D0D1 cleared!\n"); */ + i += 8; + break; + } + + FMC->MPDAT0 = pu32Buf[idx++]; + FMC->MPDAT1 = pu32Buf[idx++]; + + if (i == FMC_MULTI_WORD_PROG_LEN/4) + break; // done + + while (FMC->MPSTS & (FMC_MPSTS_D2_Msk | FMC_MPSTS_D3_Msk)) + ; + retval += 8; + u32Len -= 8; + if (u32Len < 8) + { + return retval; + } + + if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk)) + { + /* printf(" [WARNING] busy cleared after D2D3 cleared!\n"); */ + i += 8; + break; + } + + FMC->MPDAT2 = pu32Buf[idx++]; + FMC->MPDAT3 = pu32Buf[idx++]; + } + + if (i != FMC_MULTI_WORD_PROG_LEN) + { + /* printf(" [WARNING] Multi-word program interrupted at 0x%x !!\n", i); */ + return retval; + } + + while (FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) ; + + u32Addr += FMC_MULTI_WORD_PROG_LEN; + } + return retval; +} + + +/** + * @brief Program a 64-bits data to the specified OTP. + * @param[in] otp_num The OTP number. + * @param[in] low_word Low word of the 64-bits data. + * @param[in] high_word Low word of the 64-bits data. + * @retval 0 Success + * @retval -1 Program failed. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL; + FMC->ISPDAT = low_word; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL + 4UL; + FMC->ISPDAT = high_word; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + return ret; +} + +/** + * @brief Read the 64-bits data from the specified OTP. + * @param[in] otp_num The OTP number. + * @param[in] low_word Low word of the 64-bits data. + * @param[in] high_word Low word of the 64-bits data. + * @retval 0 Success + * @retval -1 Read failed. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL ; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + *low_word = FMC->MPDAT0; + *high_word = FMC->MPDAT1; + } + } + return ret; +} + +/** + * @brief Lock the specified OTP. + * @param[in] otp_num The OTP number. + * @retval 0 Success + * @retval -1 Failed to write OTP lock bits. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Lock_OTP(uint32_t otp_num) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL; + FMC->ISPDAT = 0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + return ret; +} + +/** + * @brief Check the OTP is locked or not. + * @param[in] otp_num The OTP number. + * @retval 1 OTP is locked. + * @retval 0 OTP is not locked. + * @retval -1 Failed to read OTP lock bits. + * @retval -2 Invalid OTP number. + */ +int32_t FMC_Is_OTP_Locked(uint32_t otp_num) +{ + int32_t ret = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + if (FMC->ISPDAT != 0xFFFFFFFFUL) + { + ret = 1; /* Lock work was progrmmed. OTP was locked. */ + } + } + } + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_READ command to read User Configuration. + * @param[out] u32Config A two-word array. + * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1. + * @param[in] u32Count Available word count in u32Config. + * @return Success or not. + * @retval 0 Success. + * @retval -1 Invalid parameter. + */ +int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count) +{ + int32_t ret = 0; + + u32Config[0] = FMC_Read(FMC_CONFIG_BASE); + + if (u32Count < 2UL) + { + ret = -1; + } + else + { + u32Config[1] = FMC_Read(FMC_CONFIG_BASE+4UL); + } + return ret; +} + + +/** + * @brief Execute ISP commands to erase then write User Configuration. + * @param[in] u32Config A two-word array. + * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1. + * @param[in] u32Count Always be 2 in this BSP. + * @return Success or not. + * @retval 0 Success. + * @retval -1 Invalid parameter. + */ +int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count) +{ + FMC_ENABLE_CFG_UPDATE(); + FMC_Erase(FMC_CONFIG_BASE); + FMC_Write(FMC_CONFIG_BASE, u32Config[0]); + FMC_Write(FMC_CONFIG_BASE+4UL, u32Config[1]); + FMC_DISABLE_CFG_UPDATE(); + return 0; +} + + +/** + * @brief Run CRC32 checksum calculation and get result. + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * @return Success or not. + * @retval 0 Success. + * @retval 0xFFFFFFFF Invalid parameter. + */ +uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret; + + if ((u32addr % 512UL) || (u32count % 512UL)) + { + ret = 0xFFFFFFFF; + } + else + { + FMC->ISPCMD = FMC_ISPCMD_RUN_CKS; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + FMC->ISPCMD = FMC_ISPCMD_READ_CKS; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + ret = FMC->ISPDAT; + } + + return ret; +} + + +/** + * @brief Run flash all one verification and get result. + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * @retval READ_ALLONE_YES The contents of verified flash area are 0xFFFFFFFF. + * @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xFFFFFFFF. + * @retval READ_ALLONE_CMD_FAIL Unexpected error occurred. + */ +uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret = READ_ALLONE_CMD_FAIL; + + FMC->ISPSTS = 0x80UL; /* clear check all one bit */ + + FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + do + { + FMC->ISPCMD = FMC_ISPCMD_READ_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + } + while (FMC->ISPDAT == 0UL); + + if (FMC->ISPDAT == READ_ALLONE_YES) + { + ret = FMC->ISPDAT; + } + + if (FMC->ISPDAT == READ_ALLONE_NOT) + { + ret = FMC->ISPDAT; + } + + return ret; +} + + +/** + * @brief Setup security key. + * @param[in] key Key 0~2 to be setup. + * @param[in] kpmax Maximum unmatched power-on counting number. + * @param[in] kemax Maximum unmatched counting number. + * @param[in] lock_CONFIG 1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG. + * @param[in] lock_SPROM 1: Security key lock SPROM to write-protect. 0: Don't lock SPROM. + * @retval 0 Success. + * @retval -1 Key is locked. Cannot overwrite the current key. + * @retval -2 Failed to erase flash. + * @retval -3 Failed to program key. + * @retval -4 Key lock function failed. + * @retval -5 CONFIG lock function failed. + * @retval -6 SPROM lock function failed. + * @retval -7 KPMAX function failed. + * @retval -8 KEMAX function failed. + */ +int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, + const int32_t lock_CONFIG, const int32_t lock_SPROM) +{ + uint32_t lock_ctrl = 0UL; + uint32_t u32KeySts; + int32_t ret = 0; + + if (FMC->KPKEYSTS != 0x200UL) + { + ret = -1; + } + + if (FMC_Erase(FMC_KPROM_BASE)) + { + ret = -2; + } + + if (FMC_Erase(FMC_KPROM_BASE+0x200UL)) + { + ret = -3; + } + + if (!lock_CONFIG) + { + lock_ctrl |= 0x1UL; + } + + if (!lock_SPROM) + { + lock_ctrl |= 0x2UL; + } + + if (ret == 0) + { + FMC_Write(FMC_KPROM_BASE, key[0]); + FMC_Write(FMC_KPROM_BASE+0x4UL, key[1]); + FMC_Write(FMC_KPROM_BASE+0x8UL, key[2]); + FMC_Write(FMC_KPROM_BASE+0xCUL, kpmax); + FMC_Write(FMC_KPROM_BASE+0x10UL, kemax); + FMC_Write(FMC_KPROM_BASE+0x14UL, lock_ctrl); + + while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { } + + u32KeySts = FMC->KPKEYSTS; + + if (!(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk)) + { + /* Security key lock failed! */ + ret = -4; + } + else if ((lock_CONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) || + ((!lock_CONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) + { + /* CONFIG lock failed! */ + ret = -5; + } + else if ((lock_SPROM && (!(u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) || + ((!lock_SPROM) && (u32KeySts & FMC_KPKEYSTS_SPFLAG_Msk))) + { + /* CONFIG lock failed! */ + ret = -6; + } + else if (((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != kpmax) + { + /* KPMAX failed! */ + ret = -7; + } + else if (((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != kemax) + { + /* KEMAX failed! */ + ret = -8; + } + } + return ret; +} + + +/** + * @brief Execute security key comparison. + * @param[in] key Key 0~2 to be compared. + * @retval 0 Key matched. + * @retval -1 Forbidden. Times of key comparison mismatch reach the maximum count. + * @retval -2 Key mismatched. + * @retval -3 No security key lock. Key comparison is not required. + */ +int32_t FMC_CompareSPKey(uint32_t key[3]) +{ + uint32_t u32KeySts; + int32_t ret = 0; + + if (FMC->KPKEYSTS & FMC_KPKEYSTS_FORBID_Msk) + { + /* FMC_CompareSPKey - FORBID! */ + ret = -1; + } + + if (!(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYLOCK_Msk)) + { + /* FMC_CompareSPKey - key is not locked! */ + ret = -3; + } + + if (ret == 0) + { + FMC->KPKEY0 = key[0]; + FMC->KPKEY1 = key[1]; + FMC->KPKEY2 = key[2]; + FMC->KPKEYTRG = FMC_KPKEYTRG_KPKEYGO_Msk | FMC_KPKEYTRG_TCEN_Msk; + + while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { } + + u32KeySts = FMC->KPKEYSTS; + + if (!(u32KeySts & FMC_KPKEYSTS_KEYMATCH_Msk)) + { + /* Key mismatched! */ + ret = -2; + } + else if (u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk) + { + /* Key matched, but still be locked! */ + ret = -2; + } + } + return ret; +} + + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/gpio.c b/bsp/nuvoton_m487/libraries/StdDriver/src/gpio.c new file mode 100644 index 00000000000..66adc594686 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/gpio.c @@ -0,0 +1,152 @@ +/**************************************************************************//** + * @file gpio.c + * @version V3.00 + * @brief M480 series GPIO driver source file + * + * @copyright (C) 2011~2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Set GPIO operation mode + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * @param[in] u32Mode Operation mode. It could be \n + * GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI. + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for(i = 0ul; i < GPIO_PIN_MAX; i++) + { + if((u32PinMask & (1ul << i))==(1ul << i)) + { + port->MODE = (port->MODE & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Enable GPIO interrupt + * + * @param[in] port GPIO port. It could be It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) +{ + port->INTTYPE = (port->INTTYPE&~(1ul<> 24) & 0xFFUL) << u32Pin); + port->INTEN = (port->INTEN&~(0x00010001ul<INTTYPE &= ~(1UL << u32Pin); + port->INTEN &= ~((0x00010001UL) << u32Pin); +} + +/** + * @brief Set GPIO slew rate control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * @param[in] u32Mode Slew rate mode. \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V) + * \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V) + * \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V) + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for(i = 0ul; i < GPIO_PIN_MAX; i++) + { + if(u32PinMask & (1ul << i)) + { + port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Set GPIO Pull-up and Pull-down control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32Mode The pin mode of specified GPIO pin. It could be + * \ref GPIO_PUSEL_DISABLE + * \ref GPIO_PUSEL_PULL_UP + * \ref GPIO_PUSEL_PULL_DOWN + * + * @return None + * + * @details Set the pin mode of specified GPIO pin. + */ +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for(i = 0ul; i < GPIO_PIN_MAX; i++) + { + if(u32PinMask & (1ul << i)) + { + port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2011~2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/hsusbd.c b/bsp/nuvoton_m487/libraries/StdDriver/src/hsusbd.c new file mode 100644 index 00000000000..37950014f9f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/hsusbd.c @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file hsusbd.c + * @version V1.00 + * @brief M480 HSUSBD driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSUSBD_Driver HSUSBD Driver + @{ +*/ + + +/** @addtogroup HSUSBD_EXPORTED_FUNCTIONS HSUSBD Exported Functions + @{ +*/ +/*--------------------------------------------------------------------------*/ +/** @cond HIDDEN_SYMBOLS */ +/* Global variables for Control Pipe */ +S_HSUSBD_CMD_T gUsbCmd; +S_HSUSBD_INFO_T *g_hsusbd_sInfo; + +HSUSBD_VENDOR_REQ g_hsusbd_pfnVendorRequest = NULL; +HSUSBD_CLASS_REQ g_hsusbd_pfnClassRequest = NULL; +HSUSBD_SET_INTERFACE_REQ g_hsusbd_pfnSetInterface = NULL; +uint32_t g_u32HsEpStallLock = 0ul; /* Bit map flag to lock specified EP when SET_FEATURE */ + +static uint8_t *g_hsusbd_CtrlInPointer = 0; +static uint32_t g_hsusbd_CtrlMaxPktSize = 64ul; +static uint8_t g_hsusbd_UsbConfig = 0ul; +static uint8_t g_hsusbd_UsbAltInterface = 0ul; +static uint8_t g_hsusbd_EnableTestMode = 0ul; +static uint8_t g_hsusbd_TestSelector = 0ul; + +#ifdef __ICCARM__ +#pragma data_alignment=4 +static uint8_t g_hsusbd_buf[12]; +#else +static uint8_t g_hsusbd_buf[12] __attribute__((aligned(4))); +#endif + +uint8_t g_hsusbd_Configured = 0ul; +uint8_t g_hsusbd_CtrlZero = 0ul; +uint8_t g_hsusbd_UsbAddr = 0ul; +uint8_t g_hsusbd_ShortPacket = 0ul; +uint32_t volatile g_hsusbd_DmaDone = 0ul; +uint32_t g_hsusbd_CtrlInSize = 0ul; +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief HSUSBD Initial + * + * @param[in] param Descriptor + * @param[in] pfnClassReq Class Request Callback Function + * @param[in] pfnSetInterface SetInterface Request Callback Function + * + * @return None + * + * @details This function is used to initial HSUSBD. + */ +void HSUSBD_Open(S_HSUSBD_INFO_T *param, HSUSBD_CLASS_REQ pfnClassReq, HSUSBD_SET_INTERFACE_REQ pfnSetInterface) +{ + g_hsusbd_sInfo = param; + g_hsusbd_pfnClassRequest = pfnClassReq; + g_hsusbd_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_hsusbd_CtrlMaxPktSize = g_hsusbd_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ + /* Enable PHY */ + HSUSBD_ENABLE_PHY(); + /* wait PHY clock ready */ + while (1) + { + HSUSBD->EP[EPA].EPMPS = 0x20ul; + if (HSUSBD->EP[EPA].EPMPS == 0x20ul) + { + break; + } + } + /* Force SE0, and then clear it to connect*/ + HSUSBD_SET_SE0(); +} + +/** + * @brief HSUSBD Start + * + * @param[in] None + * + * @return None + * + * @details This function is used to start transfer + */ +void HSUSBD_Start(void) +{ + HSUSBD_CLR_SE0(); +} + +/** + * @brief Process Setup Packet + * + * @param[in] None + * + * @return None + * + * @details This function is used to process Setup packet. + */ +void HSUSBD_ProcessSetupPacket(void) +{ + /* Setup packet process */ + gUsbCmd.bmRequestType = (uint8_t)(HSUSBD->SETUP1_0 & 0xfful); + gUsbCmd.bRequest = (uint8_t)((HSUSBD->SETUP1_0 >> 8) & 0xfful); + gUsbCmd.wValue = (uint16_t)HSUSBD->SETUP3_2; + gUsbCmd.wIndex = (uint16_t)HSUSBD->SETUP5_4; + gUsbCmd.wLength = (uint16_t)HSUSBD->SETUP7_6; + + /* USB device request in setup packet: offset 0, D[6..5]: 0=Standard, 1=Class, 2=Vendor, 3=Reserved */ + switch (gUsbCmd.bmRequestType & 0x60ul) + { + case REQ_STANDARD: + { + HSUSBD_StandardRequest(); + break; + } + case REQ_CLASS: + { + if (g_hsusbd_pfnClassRequest != NULL) + { + g_hsusbd_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: + { + if (g_hsusbd_pfnVendorRequest != NULL) + { + g_hsusbd_pfnVendorRequest(); + } + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } +} + +/** + * @brief Get Descriptor request + * + * @param[in] None + * + * @return None + * + * @details This function is used to process GetDescriptor request. + */ +int HSUSBD_GetDescriptor(void) +{ + uint32_t u32Len; + int val = 0; + + u32Len = gUsbCmd.wLength; + g_hsusbd_CtrlZero = (uint8_t)0ul; + + switch ((gUsbCmd.wValue & 0xff00ul) >> 8) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = Minimum(u32Len, LEN_DEVICE); + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8DevDesc, u32Len); + break; + } + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + if ((HSUSBD->OPER & 0x04ul) == 0x04ul) + { + u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8ConfigDesc, u32Len); + } + else + { + u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FullConfigDesc, u32Len); + } + + break; + } + /* Get Qualifier Descriptor */ + case DESC_QUALIFIER: + { + u32Len = Minimum(u32Len, LEN_QUALIFIER); + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8QualDesc, u32Len); + break; + } + /* Get Other Speed Descriptor - Full speed */ + case DESC_OTHERSPEED: + { + uint32_t u32TotalLen; + if ((HSUSBD->OPER & 0x04ul) == 0x04ul) + { + u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HSOtherConfigDesc, u32Len); + } + else + { + u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FSOtherConfigDesc, u32Len); + } + + break; + } + /* Get HID Descriptor */ + case DESC_HID: + { + u32Len = Minimum(u32Len, LEN_HID); + HSUSBD_MemCopy(g_hsusbd_buf, &g_hsusbd_sInfo->gu8ConfigDesc[LEN_CONFIG+LEN_INTERFACE], u32Len); + HSUSBD_PrepareCtrlIn(g_hsusbd_buf, u32Len); + break; + } + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + if ((HSUSBD->OPER & 0x04ul) == 0x04ul) + { + if (u32Len > g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful]) + { + u32Len = g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful]; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HidReportDesc[gUsbCmd.wIndex & 0xfful], u32Len); + } + else + { + if (u32Len > g_hsusbd_sInfo->gu32FSHidReportSize[gUsbCmd.wIndex & 0xfful]) + { + u32Len = g_hsusbd_sInfo->gu32FSHidReportSize[gUsbCmd.wIndex & 0xfful]; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FSHidReportDesc[gUsbCmd.wIndex & 0xfful], u32Len); + } + break; + } + /* Get String Descriptor */ + case DESC_STRING: + { + if((gUsbCmd.wValue & 0xfful) < 8ul) + { + if (u32Len > g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0]) + { + u32Len = g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0]; + if ((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful], u32Len); + } + else + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + val = 1; + } + break; + } + default: + /* Not support. Reply STALL. */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + val = 1; + break; + } + return val; +} + + +/** + * @brief Process USB standard request + * + * @param[in] None + * + * @return None + * + * @details This function is used to process USB Standard Request. + */ +void HSUSBD_StandardRequest(void) +{ + /* clear global variables for new request */ + g_hsusbd_CtrlInPointer = 0; + g_hsusbd_CtrlInSize = 0ul; + + if ((gUsbCmd.bmRequestType & 0x80ul) == 0x80ul) /* request data transfer direction */ + { + /* Device to host */ + switch (gUsbCmd.bRequest) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbConfig, 1ul); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + case GET_DESCRIPTOR: + { + if (!HSUSBD_GetDescriptor()) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + } + break; + } + case GET_INTERFACE: + { + /* Return current interface setting */ + HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbAltInterface, 1ul); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + case GET_STATUS: + { + /* Device */ + if (gUsbCmd.bmRequestType == 0x80ul) + { + if ((g_hsusbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) + { + g_hsusbd_buf[0] = (uint8_t)1ul; /* Self-Powered */ + } + else + { + g_hsusbd_buf[0] = (uint8_t)0ul; /* bus-Powered */ + } + } + /* Interface */ + else if (gUsbCmd.bmRequestType == 0x81ul) + { + g_hsusbd_buf[0] = (uint8_t)0ul; + } + /* Endpoint */ + else if (gUsbCmd.bmRequestType == 0x82ul) + { + uint8_t ep = (uint8_t)(gUsbCmd.wIndex & 0xFul); + g_hsusbd_buf[0] = (uint8_t)HSUSBD_GetStall((uint32_t)ep)? (uint8_t)1 : (uint8_t)0; + } + g_hsusbd_buf[1] = (uint8_t)0ul; + HSUSBD_PrepareCtrlIn(g_hsusbd_buf, 2ul); + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } + } + else + { + /* Host to device */ + switch (gUsbCmd.bRequest) + { + case CLEAR_FEATURE: + { + if((gUsbCmd.wValue & 0xfful) == FEATURE_ENDPOINT_HALT) + { + + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_u32HsEpStallLock is added to support it */ + epNum = (uint32_t)(gUsbCmd.wIndex & 0xFul); + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == epNum) && ((g_u32HsEpStallLock & (1ul << i)) == 0ul)) + { + HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xeful) | HSUSBD_EP_RSPCTL_TOGGLE; + } + } + } + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_ADDRESS: + { + g_hsusbd_UsbAddr = (uint8_t)gUsbCmd.wValue; + /* Status Stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_CONFIGURATION: + { + g_hsusbd_UsbConfig = (uint8_t)gUsbCmd.wValue; + g_hsusbd_Configured = (uint8_t)1ul; + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_FEATURE: + { + if ((gUsbCmd.wValue & 0x3ul) == 2ul) /* TEST_MODE */ + { + g_hsusbd_EnableTestMode = (uint8_t)1ul; + g_hsusbd_TestSelector = (uint8_t)(gUsbCmd.wIndex >> 8); + } + if ((gUsbCmd.wValue & 0x3ul) == 3ul) /* HNP ebable */ + { + HSOTG->CTL |= (HSOTG_CTL_HNPREQEN_Msk | HSOTG_CTL_BUSREQ_Msk); + } + + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_INTERFACE: + { + g_hsusbd_UsbAltInterface = (uint8_t)gUsbCmd.wValue; + if (g_hsusbd_pfnSetInterface != NULL) + { + g_hsusbd_pfnSetInterface((uint32_t)g_hsusbd_UsbAltInterface); + } + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } + } +} + +/** + * @brief Update Device State + * + * @param[in] None + * + * @return None + * + * @details This function is used to update Device state when Setup packet complete + */ +/** @cond HIDDEN_SYMBOLS */ +#define TEST_J 0x01ul +#define TEST_K 0x02ul +#define TEST_SE0_NAK 0x03ul +#define TEST_PACKET 0x04ul +#define TEST_FORCE_ENABLE 0x05ul +/** @endcond HIDDEN_SYMBOLS */ + +void HSUSBD_UpdateDeviceState(void) +{ + switch (gUsbCmd.bRequest) + { + case SET_ADDRESS: + { + HSUSBD_SET_ADDR(g_hsusbd_UsbAddr); + break; + } + case SET_CONFIGURATION: + { + if (g_hsusbd_UsbConfig == 0ul) + { + uint32_t volatile i; + /* Reset PID DATA0 */ + for (i=0ul; iEP[i].EPCFG & 0x1ul) == 0x1ul) + { + HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; + } + } + } + break; + } + case SET_FEATURE: + { + if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) + { + uint32_t idx; + idx = (uint32_t)(gUsbCmd.wIndex & 0xFul); + HSUSBD_SetStall(idx); + } + else if (g_hsusbd_EnableTestMode) + { + g_hsusbd_EnableTestMode = (uint8_t)0ul; + if (g_hsusbd_TestSelector == TEST_J) + { + HSUSBD->TEST = TEST_J; + } + else if (g_hsusbd_TestSelector == TEST_K) + { + HSUSBD->TEST = TEST_K; + } + else if (g_hsusbd_TestSelector == TEST_SE0_NAK) + { + HSUSBD->TEST = TEST_SE0_NAK; + } + else if (g_hsusbd_TestSelector == TEST_PACKET) + { + HSUSBD->TEST = TEST_PACKET; + } + else if (g_hsusbd_TestSelector == TEST_FORCE_ENABLE) + { + HSUSBD->TEST = TEST_FORCE_ENABLE; + } + } + break; + } + case CLEAR_FEATURE: + { + if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) + { + uint32_t idx; + idx = (uint32_t)(gUsbCmd.wIndex & 0xFul); + HSUSBD_ClearStall(idx); + } + break; + } + default: + break; + } +} + + +/** + * @brief Prepare Control IN transaction + * + * @param[in] pu8Buf Control IN data pointer + * @param[in] u32Size IN transfer size + * + * @return None + * + * @details This function is used to prepare Control IN transfer + */ +void HSUSBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + g_hsusbd_CtrlInPointer = pu8Buf; + g_hsusbd_CtrlInSize = u32Size; +} + + + +/** + * @brief Start Control IN transfer + * + * @param[in] None + * + * @return None + * + * @details This function is used to start Control IN + */ +void HSUSBD_CtrlIn(void) +{ + uint32_t volatile i, cnt; + uint8_t u8Value; + if(g_hsusbd_CtrlInSize >= g_hsusbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + cnt = g_hsusbd_CtrlMaxPktSize >> 2; + for (i=0ul; iCEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer; + g_hsusbd_CtrlInPointer = (uint8_t *)(g_hsusbd_CtrlInPointer + 4ul); + } + HSUSBD_START_CEP_IN(g_hsusbd_CtrlMaxPktSize); + g_hsusbd_CtrlInSize -= g_hsusbd_CtrlMaxPktSize; + } + else + { + /* Data size <= MXPLD */ + cnt = g_hsusbd_CtrlInSize >> 2; + for (i=0ul; iCEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer; + g_hsusbd_CtrlInPointer += 4ul; + } + + for (i=0ul; i<(g_hsusbd_CtrlInSize % 4ul); i++) + { + u8Value = *(uint8_t *)(g_hsusbd_CtrlInPointer+i); + outpb(&HSUSBD->CEPDAT, u8Value); + } + + HSUSBD_START_CEP_IN(g_hsusbd_CtrlInSize); + g_hsusbd_CtrlInPointer = 0; + g_hsusbd_CtrlInSize = 0ul; + } +} + +/** + * @brief Start Control OUT transaction + * + * @param[in] pu8Buf Control OUT data pointer + * @param[in] u32Size OUT transfer size + * + * @return None + * + * @details This function is used to start Control OUT transfer + */ +void HSUSBD_CtrlOut(uint8_t pu8Buf[], uint32_t u32Size) +{ + uint32_t volatile i; + while(1) + { + if ((HSUSBD->CEPINTSTS & HSUSBD_CEPINTSTS_RXPKIF_Msk) == HSUSBD_CEPINTSTS_RXPKIF_Msk) + { + for (i=0ul; iCEPDAT); + } + HSUSBD->CEPINTSTS = HSUSBD_CEPINTSTS_RXPKIF_Msk; + break; + } + } +} + +/** + * @brief Clear all software flags + * + * @param[in] None + * + * @return None + * + * @details This function is used to clear all software control flag + */ +void HSUSBD_SwReset(void) +{ + /* Reset all variables for protocol */ + g_hsusbd_UsbAddr = (uint8_t)0ul; + g_hsusbd_DmaDone = 0ul; + g_hsusbd_ShortPacket = (uint8_t)0ul; + g_hsusbd_Configured = (uint8_t)0ul; + + /* Reset USB device address */ + HSUSBD_SET_ADDR(0ul); +} + +/** + * @brief HSUSBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set HSUSBD vendor request callback function + */ +void HSUSBD_SetVendorRequest(HSUSBD_VENDOR_REQ pfnVendorReq) +{ + g_hsusbd_pfnVendorRequest = pfnVendorReq; +} + + +/*@}*/ /* end of group HSUSBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HSUSBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/i2c.c b/bsp/nuvoton_m487/libraries/StdDriver/src/i2c.c new file mode 100644 index 00000000000..ee937f56bd0 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/i2c.c @@ -0,0 +1,1468 @@ +/**************************************************************************//** + * @file i2c.c + * @version V3.00 + * @brief M480 series I2C driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief Enable specify I2C Controller and set Clock Divider + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C bus clock in Hz + * + * @return Actual I2C bus clock frequency + * + * @details The function enable the specify I2C Controller and set proper Clock Divider + * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock. + * I2C Bus clock = PCLK / (4*(divider+1). + * + */ +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if(i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + /* Enable I2C */ + i2c->CTL0 |= I2C_CTL0_I2CEN_Msk; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Disable specify I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Reset I2C Controller and disable specify I2C port. + * + */ + +void I2C_Close(I2C_T *i2c) +{ + /* Reset I2C Controller */ + if((uint32_t)i2c == I2C0_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk; + } + else if((uint32_t)i2c == I2C1_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk; + } + + /* Disable I2C */ + i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk; +} + +/** + * @brief Clear Time-out Counter flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag . + * + */ +void I2C_ClearTimeoutFlag(I2C_T *i2c) +{ + i2c->TOCTL |= I2C_TOCTL_TOIF_Msk; +} + +/** + * @brief Set Control bit of I2C Controller + * + * @param[in] i2c Specify I2C port + * @param[in] u8Start Set I2C START condition + * @param[in] u8Stop Set I2C STOP condition + * @param[in] u8Si Clear SI flag + * @param[in] u8Ack Set I2C ACK bit + * + * @return None + * + * @details The function set I2C Control bit of I2C Bus protocol. + * + */ +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + + if(u8Start) + { + u32Reg |= I2C_CTL_STA; + } + + if(u8Stop) + { + u32Reg |= I2C_CTL_STO; + } + + if(u8Si) + { + u32Reg |= I2C_CTL_SI; + } + + if(u8Ack) + { + u32Reg |= I2C_CTL_AA; + } + + i2c->CTL0 = (i2c->CTL0 & ~0x3CU) | u32Reg; +} + +/** + * @brief Disable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for disable I2C interrupt + * + */ +void I2C_DisableInt(I2C_T *i2c) +{ + i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Enable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for enable I2C interrupt + * + */ +void I2C_EnableInt(I2C_T *i2c) +{ + i2c->CTL0 |= I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Get I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * + * @return The actual I2C Bus clock in Hz + * + * @details To get the actual I2C Bus Clock frequency. + */ +uint32_t I2C_GetBusClockFreq(I2C_T *i2c) +{ + uint32_t u32Divider = i2c->CLKDIV; + uint32_t u32Pclk; + + if(i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + return (u32Pclk / ((u32Divider + 1U) << 2U)); +} + +/** + * @brief Set I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C Bus Clock in Hz + * + * @return The actual I2C Bus Clock in Hz + * + * @details To set the actual I2C Bus Clock frequency. + */ +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if(i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Get Interrupt Flag + * + * @param[in] i2c Specify I2C port + * + * @return I2C interrupt flag status + * + * @details To get I2C Bus interrupt flag. + */ +uint32_t I2C_GetIntFlag(I2C_T *i2c) +{ + uint32_t u32Value; + + if((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk) + { + u32Value = 1U; + } + else + { + u32Value = 0U; + } + + return u32Value; +} + +/** + * @brief Get I2C Bus Status Code + * + * @param[in] i2c Specify I2C port + * + * @return I2C Status Code + * + * @details To get I2C Bus Status Code. + */ +uint32_t I2C_GetStatus(I2C_T *i2c) +{ + return (i2c->STATUS0); +} + +/** + * @brief Read a Byte from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return I2C Data + * + * @details To read a bytes data from specify I2C port. + */ +uint8_t I2C_GetData(I2C_T *i2c) +{ + return (uint8_t)(i2c->DAT); +} + +/** + * @brief Send a byte to I2C Bus + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data The data to send to I2C bus + * + * @return None + * + * @details This function is used to write a byte to specified I2C port + */ +void I2C_SetData(I2C_T *i2c, uint8_t u8Data) +{ + i2c->DAT = u8Data; +} + +/** + * @brief Set 7-bit Slave Address and GC Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address register (0~3) + * @param[in] u8SlaveAddr 7-bit slave address + * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE) + * + * @return None + * + * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3) + * and enable GC Mode. + * + */ +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 2: + i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 3: + i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 0: + default: + i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + } +} + +/** + * @brief Configure the mask bits of 7-bit Slave Address + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3) + * @param[in] u8SlaveAddrMask A byte for slave address mask + * + * @return None + * + * @details This function is used to set 7-bit slave addresses. + * + */ +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 2: + i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 3: + i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 0: + default: + i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1U; + break; + } +} + +/** + * @brief Enable Time-out Counter Function and support Long Time-out + * + * @param[in] i2c Specify I2C port + * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1) + * + * @return None + * + * @details This function enable Time-out Counter function and configure DIV4 to support Long + * Time-out. + * + */ +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout) +{ + if(u8LongTimeout) + { + i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk; + } + else + { + i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk; + } + + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Disable Time-out Counter Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Time-out Counter function in I2CTOC register. + * + */ +void I2C_DisableTimeout(I2C_T *i2c) +{ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Enable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To enable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_EnableWakeup(I2C_T *i2c) +{ + i2c->WKCTL |= I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_DisableWakeup(I2C_T *i2c) +{ + i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +uint32_t I2C_SMBusGetStatus(I2C_T *i2c) +{ + return (i2c->BUSSTS); +} + +/** + * @brief Clear SMBus Interrupt Flag + * + * @param[in] i2c Specify I2C port + * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag + * + * @return None + * + * @details To clear flags of I2C_BUSSTS status register if interrupt set. + * + */ +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag) +{ + i2c->BUSSTS = u8SMBusIntFlag; +} + +/** + * @brief Set SMBus Bytes Counts of Transmission or Reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize) +{ + i2c->PKTSIZE = u32PktSize; +} + +/** + * @brief Init SMBus Host/Device Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0)) + * + * @return None + * + * @details Using SMBus communication must specify the port is a Host or a Device. + * + */ +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice) +{ + /* Clear BMHEN, BMDEN of BUSCTL Register */ + i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk); + + /* Set SMBus Host/Device Mode, and enable Bus Management*/ + if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE) + { + i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } + else + { + i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } +} + +/** + * @brief Disable SMBus function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode. + * + */ +void I2C_SMBusClose(I2C_T *i2c) +{ + + i2c->BUSCTL = 0x00U; +} + +/** + * @brief Enable SMBus PEC Transmit Function + * + * @param[in] i2c Specify I2C port + * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE) + * + * @return None + * + * @details When enable CRC check function, the Host or Device needs to transmit CRC byte. + * + */ +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn) +{ + i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk; + + if(u8PECTxEn) + { + i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk); + } + else + { + i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk; + } +} + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return A byte is packet error check value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c) +{ + return (uint8_t)i2c->PKTCRC; +} + +/** + * @brief Calculate Time-out of SMBus idle period + * + * @param[in] i2c Specify I2C port + * @param[in] us Time-out length(us) + * @param[in] u32Hclk I2C peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Idle state. + * + */ + +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk) +{ + uint32_t u32Div, u32Hclk_kHz; + + i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk; + u32Hclk_kHz = u32Hclk / 1000U; + u32Div = (((us * u32Hclk_kHz) / 1000U) >> 2U) - 1U; + if(u32Div > 255U) + { + i2c->BUSTOUT = 0xFFU; + } + else + { + i2c->BUSTOUT = u32Div; + } + +} + +/** + * @brief Calculate Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in active state. + * Time-out length is calculate the SCL line "one clock" pull low timing. + * + */ + +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->BUSTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + +/** + * @brief Calculate Cumulative Clock low Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Active state. + * Time-out length is calculate the SCL line "clocks" low cumulative timing. + * + */ + +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->CLKTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + + +/** + * @brief Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master write a byte data to Slave. + * + */ + +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + + I2C_START(i2c); + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, data); /* Write data to I2CDAT */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master write multi bytes data to Slave. + * + */ + +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write Data to I2CDAT */ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Send Slave address with write bit */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < 1u) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, data[u32txLen++]); + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < 1u) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] data[] A data array for write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < u32wLen) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write data to Register I2CDAT*/ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master to read a byte data from Slave. + * + */ +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify an address(2 bytes) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Addr = 1u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/i2s.c b/bsp/nuvoton_m487/libraries/StdDriver/src/i2s.c new file mode 100644 index 00000000000..50d3c99c23f --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/i2s.c @@ -0,0 +1,248 @@ +/**************************************************************************//** + * @file i2s.c + * @version V0.10 + * @brief M480 I2S driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s); + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s is the base address of I2S module. + * @return I2S source clock frequency (Hz). + */ +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s) +{ + uint32_t u32Freq, u32ClkSrcSel; + + /* get I2S selection clock source */ + u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S0SEL_Msk; + + switch (u32ClkSrcSel) + { + case CLK_CLKSEL3_I2S0SEL_HXT: + u32Freq = __HXT; + break; + + case CLK_CLKSEL3_I2S0SEL_PLL: + u32Freq = CLK_GetPLLClockFreq(); + break; + + case CLK_CLKSEL3_I2S0SEL_HIRC: + u32Freq = __HIRC; + break; + + case CLK_CLKSEL3_I2S0SEL_PCLK0: + u32Freq = (uint32_t)CLK_GetPCLK0Freq(); + break; + + default: + u32Freq = __HIRC; + break; + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * The sample rate may not be used from the parameter, it depends on system's clock settings, + * but real sample rate used by system will be returned for reference. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are: + * - \ref I2S_MODE_MASTER + * - \ref I2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are: + * - \ref I2S_DATABIT_8 + * - \ref I2S_DATABIT_16 + * - \ref I2S_DATABIT_24 + * - \ref I2S_DATABIT_32 + * @param[in] u32MonoData: Set audio data to mono or not. Valid values are: + * - \ref I2S_ENABLE_MONO + * - \ref I2S_DISABLE_MONO + * @param[in] u32DataFormat: Data format. This is also used to select I2S or PCM(TDM) function. Valid values are: + * - \ref I2S_FORMAT_I2S + * - \ref I2S_FORMAT_I2S_MSB + * - \ref I2S_FORMAT_I2S_LSB + * - \ref I2S_FORMAT_PCM + * - \ref I2S_FORMAT_PCM_MSB + * - \ref I2S_FORMAT_PCM_LSB + * @return Real sample rate. + */ +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat) +{ + uint16_t u16Divider; + uint32_t u32BitRate, u32SrcClk; + + SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk; + + i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat | I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + + u32BitRate = u32SampleRate * (((u32WordWidth>>4U) & 0x3U) + 1U) * 16U; + //u16Divider = (uint16_t)((u32SrcClk/u32BitRate) >> 1U) - 1U; + u16Divider = (uint16_t)((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U; + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8U); + + /* calculate real sample rate */ + u32BitRate = u32SrcClk / (2U*((uint32_t)u16Divider+1U)); + u32SampleRate = u32BitRate / ((((u32WordWidth>>4U) & 0x3U) + 1U) * 16U); + + i2s->CTL0 |= I2S_CTL0_I2SEN_Msk; + + return u32SampleRate; +} + +/** + * @brief Disable I2S function and I2S clock. + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_Close(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk; +} + +/** + * @brief This function enables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN |= u32Mask; +} + +/** + * @brief This function disables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN &= ~u32Mask; +} + +/** + * @brief Enable MCLK . + * @param[in] i2s is the base address of I2S module. + * @param[in] u32BusClock is the target MCLK clock + * @return Actual MCLK clock + */ +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock) +{ + uint8_t u8Divider; + uint32_t u32SrcClk, u32Reg, u32Clock; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + if (u32BusClock == u32SrcClk) + { + u8Divider = 0U; + } + else + { + u8Divider = (uint8_t)(u32SrcClk/u32BusClock) >> 1U; + } + + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider; + + i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk; + + u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk; + + if (u32Reg == 0U) + { + u32Clock = u32SrcClk; + } + else + { + u32Clock = ((u32SrcClk >> 1U) / u32Reg); + } + + return u32Clock; +} + +/** + * @brief Disable MCLK . + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_DisableMCLK(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->CTL1 = ((i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) | + (u32TxThreshold << I2S_CTL1_TXTH_Pos) | + (u32RxThreshold << I2S_CTL1_RXTH_Pos)); +} + + +/** + * @brief Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChannelWidth Channel width. Valid values are: + * - \ref I2S_TDM_WIDTH_8BIT + * - \ref I2S_TDM_WIDTH_16BIT + * - \ref I2S_TDM_WIDTH_24BIT + * - \ref I2S_TDM_WIDTH_32BIT + * @param[in] u32ChannelNum Channel number. Valid values are: + * - \ref I2S_TDM_2CH + * - \ref I2S_TDM_4CH + * - \ref I2S_TDM_6CH + * - \ref I2S_TDM_8CH + * @param[in] u32SyncWidth Width for sync pulse. Valid values are: + * - \ref I2S_TDM_SYNC_ONE_BCLK + * - \ref I2S_TDM_SYNC_ONE_CHANNEL + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth) +{ + i2s->CTL0 = ((i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) | + (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) | + (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) | + (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos)); +} + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/pdma.c b/bsp/nuvoton_m487/libraries/StdDriver/src/pdma.c new file mode 100644 index 00000000000..f5ffa361782 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/pdma.c @@ -0,0 +1,444 @@ +/**************************************************************************//** + * @file pdma.c + * @version V1.00 + * @brief M480 series PDMA driver source file + * + * @copyright (C) 2014~2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +static uint8_t u32ChSelect[PDMA_CH_MAX]; + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + + +/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions + @{ +*/ + +/** + * @brief PDMA Open + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable the PDMA channels. + */ +void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask) +{ + uint32_t i; + + for (i=0UL; iDSCT[i].CTL = 0UL; + u32ChSelect[i] = PDMA_MEM; + } + } + + pdma->CHCTL |= u32Mask; +} + +/** + * @brief PDMA Close + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details This function disable all PDMA channels. + */ +void PDMA_Close(PDMA_T * pdma) +{ + pdma->CHCTL = 0UL; +} + +/** + * @brief Set PDMA Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Width Data width. Valid values are + * - \ref PDMA_WIDTH_8 + * - \ref PDMA_WIDTH_16 + * - \ref PDMA_WIDTH_32 + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected channel data width and transfer count. + */ +void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) +{ + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); + pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos)); +} + +/** + * @brief Set PDMA Stride Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestLen Destination stride count + * @param[in] u32SrcLen Source stride count + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected stride mode. + */ +void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount) +{ + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + pdma->STRIDE[u32Ch].ASOCR =(u32DestLen<<16) | u32SrcLen; + pdma->STRIDE[u32Ch].STCR = u32TransCount; +} + +/** + * @brief Set PDMA Transfer Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32SrcAddr Source address + * @param[in] u32SrcCtrl Source control attribute. Valid values are + * - \ref PDMA_SAR_INC + * - \ref PDMA_SAR_FIX + * @param[in] u32DstAddr destination address + * @param[in] u32DstCtrl destination control attribute. Valid values are + * - \ref PDMA_DAR_INC + * - \ref PDMA_DAR_FIX + * + * @return None + * + * @details This function set the selected channel source/destination address and attribute. + */ +void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) +{ + pdma->DSCT[u32Ch].SA = u32SrcAddr; + pdma->DSCT[u32Ch].DA = u32DstAddr; + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); + pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); +} + +/** + * @brief Set PDMA Transfer Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Peripheral The selected peripheral. Valid values are + * - \ref PDMA_MEM + * - \ref PDMA_USB_TX + * - \ref PDMA_USB_RX + * - \ref PDMA_UART0_TX + * - \ref PDMA_UART0_RX + * - \ref PDMA_UART1_TX + * - \ref PDMA_UART1_RX + * - \ref PDMA_UART2_TX + * - \ref PDMA_UART2_RX + * - \ref PDMA_UART3_TX + * - \ref PDMA_UART3_RX + * - \ref PDMA_UART4_TX + * - \ref PDMA_UART4_RX + * - \ref PDMA_UART5_TX + * - \ref PDMA_UART5_RX + * - \ref PDMA_USCI0_TX + * - \ref PDMA_USCI0_RX + * - \ref PDMA_USCI1_TX + * - \ref PDMA_USCI1_RX + * - \ref PDMA_QSPI0_TX + * - \ref PDMA_QSPI0_RX + * - \ref PDMA_SPI0_TX + * - \ref PDMA_SPI0_RX + * - \ref PDMA_SPI1_TX + * - \ref PDMA_SPI1_RX + * - \ref PDMA_SPI2_TX + * - \ref PDMA_SPI2_RX + * - \ref PDMA_SPI3_TX + * - \ref PDMA_SPI3_RX + * - \ref PDMA_EPWM0_P1_RX + * - \ref PDMA_EPWM0_P2_RX + * - \ref PDMA_EPWM0_P3_RX + * - \ref PDMA_EPWM1_P1_RX + * - \ref PDMA_EPWM1_P2_RX + * - \ref PDMA_EPWM1_P3_RX + * - \ref PDMA_I2C0_TX + * - \ref PDMA_I2C0_RX + * - \ref PDMA_I2C1_TX + * - \ref PDMA_I2C1_RX + * - \ref PDMA_I2C2_TX + * - \ref PDMA_I2C2_RX + * - \ref PDMA_I2S0_TX + * - \ref PDMA_I2S0_RX + * - \ref PDMA_TMR0 + * - \ref PDMA_TMR1 + * - \ref PDMA_TMR2 + * - \ref PDMA_TMR3 + * - \ref PDMA_ADC_RX + * - \ref PDMA_DAC0_TX + * - \ref PDMA_DAC1_TX + * @param[in] u32ScatterEn Scatter-gather mode enable + * @param[in] u32DescAddr Scatter-gather descriptor address + * + * @return None + * + * @details This function set the selected channel transfer mode. Include peripheral setting. + */ +void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) +{ + u32ChSelect[u32Ch] = u32Peripheral; + switch(u32Ch) + { + case 0ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral; + break; + case 1ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos); + break; + case 2ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos); + break; + case 3ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos); + break; + case 4ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral; + break; + case 5ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos); + break; + case 6ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos); + break; + case 7ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos); + break; + case 8ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral; + break; + case 9ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos); + break; + case 10ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos); + break; + case 11ul: + pdma->REQSEL8_11 = (pdma->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos); + break; + case 12ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral; + break; + case 13ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC13_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC13_Pos); + break; + case 14ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC14_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC14_Pos); + break; + case 15ul: + pdma->REQSEL12_15 = (pdma->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC15_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC15_Pos); + break; + default: + break; + } + + if(u32ScatterEn) + { + pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + pdma->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA); + } + else + { + pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; + } +} + +/** + * @brief Set PDMA Burst Type and Size + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32BurstType Burst mode or single mode. Valid values are + * - \ref PDMA_REQ_SINGLE + * - \ref PDMA_REQ_BURST + * @param[in] u32BurstSize Set the size of burst mode. Valid values are + * - \ref PDMA_BURST_128 + * - \ref PDMA_BURST_64 + * - \ref PDMA_BURST_32 + * - \ref PDMA_BURST_16 + * - \ref PDMA_BURST_8 + * - \ref PDMA_BURST_4 + * - \ref PDMA_BURST_2 + * - \ref PDMA_BURST_1 + * + * @return None + * + * @details This function set the selected channel burst type and size. + */ +void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize) +{ + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); + pdma->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); +} + +/** + * @brief Enable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable timeout function of the selected channel(s). + */ +void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask) +{ + pdma->TOUTEN |= u32Mask; +} + +/** + * @brief Disable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function disable timeout function of the selected channel(s). + */ +void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask) +{ + pdma->TOUTEN &= ~u32Mask; +} + +/** + * @brief Set PDMA Timeout Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel, + * @param[in] u32OnOff Enable/disable time out function + * @param[in] u32TimeOutCnt Timeout count + * + * @return None + * + * @details This function set the timeout count. + * @note M480 only supported channel 0/1. + */ +void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) +{ + switch(u32Ch) + { + case 0ul: + pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt; + break; + case 1ul: + pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos); + break; + default: + break; + } +} + +/** + * @brief Trigger PDMA + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This function trigger the selected channel. + */ +void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch) +{ + if(u32ChSelect[u32Ch] == PDMA_MEM) + { + pdma->SWREQ = (1ul << u32Ch); + } + else {} +} + +/** + * @brief Enable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function enable the selected channel interrupt. + */ +void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + pdma->INTEN |= (1ul << u32Ch); + break; + case PDMA_INT_TEMPTY: + pdma->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + pdma->TOUTIEN |= (1ul << u32Ch); + break; + + default: + break; + } +} + +/** + * @brief Disable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function disable the selected channel interrupt. + */ +void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + pdma->INTEN &= ~(1ul << u32Ch); + break; + case PDMA_INT_TEMPTY: + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + pdma->TOUTIEN &= ~(1ul << u32Ch); + break; + + default: + break; + } +} + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2014~2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/qei.c b/bsp/nuvoton_m487/libraries/StdDriver/src/qei.c new file mode 100644 index 00000000000..4a890fc5aa3 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/qei.c @@ -0,0 +1,143 @@ +/**************************************************************************//** + * @file qei.c + * @version V3.00 + * @brief Quadrature Encoder Interface (QEI) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions + @{ +*/ + +/** + * @brief Close QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function reset QEI configuration and stop QEI counting. + */ +void QEI_Close(QEI_T* qei) +{ + /* Reset QEI configuration */ + qei->CTL = (uint32_t)0; +} + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function disable QEI specified interrupt. + */ +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel) +{ + /* Disable QEI specified interrupt */ + QEI_DISABLE_INT(qei, u32IntSel); + + /* Disable NVIC QEI IRQ */ + if(qei ==(QEI_T*)QEI0) + { + NVIC_DisableIRQ((IRQn_Type)QEI0_IRQn); + } + else + { + NVIC_DisableIRQ((IRQn_Type)QEI1_IRQn); + } +} + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function enable QEI specified interrupt. + */ +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel) +{ + /* Enable QEI specified interrupt */ + QEI_ENABLE_INT(qei, u32IntSel); + + /* Enable NVIC QEI IRQ */ + if(qei == (QEI_T*)QEI0) + { + NVIC_EnableIRQ(QEI0_IRQn); + } + else + { + NVIC_EnableIRQ(QEI1_IRQn); + } +} + +/** + * @brief Open QEI in specified mode and enable input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @param[in] u32Value The counter maximum value in compare-counting mode. + * @return None + * @details This function set QEI in specified mode and enable input. + */ +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value) +{ + /* Set QEI function configuration */ + /* Set QEI counting mode */ + /* Enable IDX, QEA and QEB input to QEI controller */ + qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk); + + /* Set QEI maximum count value in in compare-counting mode */ + qei->CNTMAX = u32Value; +} + +/** + * @brief Start QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function enable QEI function and start QEI counting. + */ +void QEI_Start(QEI_T* qei) +{ + /* Enable QEI controller function */ + qei->CTL |= QEI_CTL_QEIEN_Msk; +} + +/** + * @brief Stop QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function disable QEI function and stop QEI counting. + */ +void QEI_Stop(QEI_T* qei) +{ + /* Disable QEI controller function */ + qei->CTL &= (~QEI_CTL_QEIEN_Msk); +} + + +/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/qspi.c b/bsp/nuvoton_m487/libraries/StdDriver/src/qspi.c new file mode 100644 index 00000000000..d5bad7fb981 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/qspi.c @@ -0,0 +1,763 @@ +/**************************************************************************//** + * @file qspi.c + * @version V3.00 + * @brief M480 series QSPI driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief This function make QSPI module be ready to transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER) + * @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a QSPI transaction. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI peripheral clock. + * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0. + * The actual clock rate may be different from the target QSPI clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the + * actual QSPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the QSPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t QSPI_Open(QSPI_T *qspi, + uint32_t u32MasterSlave, + uint32_t u32QSPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U; + + if(u32DataWidth == 32U) + { + u32DataWidth = 0U; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32MasterSlave == QSPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + } + + /* Check clock source of QSPI */ + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0xFFU) + { + u32Div = 0xFFU; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + } + else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk; + + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + + return u32RetValue; +} + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will reset QSPI controller. + */ +void QSPI_Close(QSPI_T *qspi) +{ + /* Reset QSPI */ + SYS->IPRST1 |= SYS_IPRST1_QSPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_QSPI0RST_Msk; +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1. + */ +void QSPI_ClearRxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void QSPI_ClearTxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void QSPI_DisableAutoSS(QSPI_T *qspi) +{ + qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the QSPI bus clock. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + } + + /* Check clock source of SPI */ + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of QSPI bus clock. Only available in Master mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Actual QSPI bus clock frequency in Hz. + * @details This function will calculate the actual QSPI bus clock rate according to the QSPInSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t QSPI_GetBusClock(QSPI_T *qspi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of QSPI */ + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + /* Return QSPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1U)); +} + +/** + * @brief Enable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL |= QSPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get QSPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk; + /* Check unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_UNIT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk; + /* Check slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk; + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSINACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk; + /* Check slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVUR_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk; + /* Check slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVBE_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk; + /* Check slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_TXUF_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk; + /* Check TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk; + /* Check RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk; + /* Check RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk; + /* Check RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear QSPI related interrupt flags specified by u32Mask parameter. + */ +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + if(u32Mask & QSPI_UNIT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & QSPI_SSACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & QSPI_SSINACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & QSPI_SLVUR_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & QSPI_SLVBE_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & QSPI_TXUF_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXOV_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get QSPI status. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref QSPI_BUSY_MASK + * - \ref QSPI_RX_EMPTY_MASK + * - \ref QSPI_RX_FULL_MASK + * - \ref QSPI_TX_EMPTY_MASK + * - \ref QSPI_TX_FULL_MASK + * - \ref QSPI_TXRX_RESET_MASK + * - \ref QSPI_QSPIEN_STS_MASK + * - \ref QSPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get QSPI related status specified by u32Mask parameter. + */ +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0U, u32TmpValue; + + u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk; + /* Check busy status */ + if((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_BUSY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk; + /* Check RX empty flag */ + if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk; + /* Check RX full flag */ + if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk; + /* Check TX empty flag */ + if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk; + /* Check TX full flag */ + if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk; + /* Check TX/RX reset flag */ + if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TXRX_RESET_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_QSPIENSTS_Msk; + /* Check QSPIEN flag */ + if((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_QSPIEN_STS_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk; + /* Check QSPIx_SS line status */ + if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/rtc.c b/bsp/nuvoton_m487/libraries/StdDriver/src/rtc.c new file mode 100644 index 00000000000..eca33dea8c6 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/rtc.c @@ -0,0 +1,1067 @@ +/**************************************************************************//** + * @file rtc.c + * @version V3.00 + * @brief M480 series RTC driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @cond HIDDEN_SYMBOLS */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro, type and constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_GLOBALS + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay; +static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec; + +/** @endcond HIDDEN_SYMBOLS */ + + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Initialize RTC module and start counting + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This function is used to: \n + * 1. Write initial key to let RTC start count. \n + * 2. Input parameter indicates start date/time. \n + * 3. User has to make sure that parameters of RTC date/time are reasonable. \n + * @note Null pointer for using default starting date/time. + */ +void RTC_Open(S_RTC_TIME_DATA_T *sPt) +{ + RTC->INIT = RTC_INIT_KEY; + + if(RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + RTC->INIT = RTC_INIT_KEY; + while(RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + } + } + + if(sPt == 0) + { + } + else + { + /* Set RTC date and time */ + RTC_SetDateAndTime(sPt); + } +} + +/** + * @brief Disable RTC Clock + * + * @param None + * + * @return None + * + * @details This API will disable RTC peripheral clock and stops RTC counting. + */ +void RTC_Close(void) +{ + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; +} + +/** + * @brief Set Frequency Compensation Data + * + * @param[in] i32FrequencyX10000 Specify the RTC clock X10000, ex: 327736512 means 32773.6512. + * + * @return None + * + */ +void RTC_32KCalibration(int32_t i32FrequencyX10000) +{ + uint64_t u64Compensate; + + u64Compensate = (uint64_t)(0x2710000000000); + u64Compensate = (uint64_t)(u64Compensate / (uint64_t)i32FrequencyX10000); + + if(u64Compensate >= (uint64_t)0x400000) + { + u64Compensate = (uint64_t)0x3FFFFF; + } + + RTC_WaitAccessEnable(); + RTC->FREQADJ = (uint32_t)u64Compensate; +} + +/** + * @brief Get Current RTC Date and Time + * + * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the current RTC date and time value. + */ +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get [Date digit] data */ + g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos; + g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos; + g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos; + g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos; + g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos; + g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos; + + /* Get [Time digit] data */ + g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos; + g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos; + g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos; + g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos; + g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos; + g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10ul); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10ul); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10ul); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21ul) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20ul; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Get RTC Alarm Date and Time + * + * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the RTC alarm date and time setting. + */ +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get alarm [Date digit] data */ + RTC_WaitAccessEnable(); + g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos; + g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos; + g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos; + g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos; + g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos; + g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos; + + /* Get alarm [Time digit] data */ + RTC_WaitAccessEnable(); + g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos; + g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos; + g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos; + g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos; + g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos; + g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10ul); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10ul); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10ul); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21ul) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20ul; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + + } + else + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Update Current RTC Date and Time + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update current date and time to RTC. + */ +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCAL, u32RegTIME; + + if(sPt == 0ul) + { + } + else + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == RTC_PM) + { + sPt->u32Hour += 20ul; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set Day of the Week */ + RTC_WaitAccessEnable(); + RTC->WEEKDAY = sPt->u32DayOfWeek; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Current Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCAL = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCAL |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCAL |= ((sPt->u32Month / 10ul) << 12); + u32RegCAL |= ((sPt->u32Month % 10ul) << 8); + u32RegCAL |= ((sPt->u32Day / 10ul) << 4); + u32RegCAL |= (sPt->u32Day % 10ul); + + u32RegTIME = ((sPt->u32Hour / 10ul) << 20); + u32RegTIME |= ((sPt->u32Hour % 10ul) << 16); + u32RegTIME |= ((sPt->u32Minute / 10ul) << 12); + u32RegTIME |= ((sPt->u32Minute % 10ul) << 8); + u32RegTIME |= ((sPt->u32Second / 10ul) << 4); + u32RegTIME |= (sPt->u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender and Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + RTC->CAL = (uint32_t)u32RegCAL; + RTC_WaitAccessEnable(); + RTC->TIME = (uint32_t)u32RegTIME; + } +} + +/** + * @brief Update RTC Alarm Date and Time + * + * @param[in] sPt Specify the time property and alarm date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update alarm date and time setting to RTC. + */ +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCALM, u32RegTALM; + + if(sPt == 0) + { + } + else + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == RTC_PM) + { + sPt->u32Hour += 20ul; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Alarm Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCALM = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCALM |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCALM |= ((sPt->u32Month / 10ul) << 12); + u32RegCALM |= ((sPt->u32Month % 10ul) << 8); + u32RegCALM |= ((sPt->u32Day / 10ul) << 4); + u32RegCALM |= (sPt->u32Day % 10ul); + + u32RegTALM = ((sPt->u32Hour / 10ul) << 20); + u32RegTALM |= ((sPt->u32Hour % 10ul) << 16); + u32RegTALM |= ((sPt->u32Minute / 10ul) << 12); + u32RegTALM |= ((sPt->u32Minute % 10ul) << 8); + u32RegTALM |= ((sPt->u32Second / 10ul) << 4); + u32RegTALM |= (sPt->u32Second % 10ul); + + RTC_WaitAccessEnable(); + RTC->CALM = (uint32_t)u32RegCALM; + RTC_WaitAccessEnable(); + RTC->TALM = (uint32_t)u32RegTALM; + } +} + +/** + * @brief Update RTC Current Date + * + * @param[in] u32Year The year calendar digit of current RTC setting. + * @param[in] u32Month The month calendar digit of current RTC setting. + * @param[in] u32Day The day calendar digit of current RTC setting. + * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] + * + * @return None + * + * @details This API is used to update current date to RTC. + */ +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek) +{ + uint32_t u32RegCAL; + + u32RegCAL = ((u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCAL |= ((u32Month / 10ul) << 12); + u32RegCAL |= ((u32Month % 10ul) << 8); + u32RegCAL |= ((u32Day / 10ul) << 4); + u32RegCAL |= (u32Day % 10ul); + + /* Set Day of the Week */ + RTC_WaitAccessEnable(); + RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk; + + /* Set RTC Calender Loading */ + RTC_WaitAccessEnable(); + RTC->CAL = (uint32_t)u32RegCAL; +} + +/** + * @brief Update RTC Current Time + * + * @param[in] u32Hour The hour time digit of current RTC setting. + * @param[in] u32Minute The minute time digit of current RTC setting. + * @param[in] u32Second The second time digit of current RTC setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update current time to RTC. + */ +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTIME; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + { + u32Hour += 20ul; + } + + u32RegTIME = ((u32Hour / 10ul) << 20); + u32RegTIME |= ((u32Hour % 10ul) << 16); + u32RegTIME |= ((u32Minute / 10ul) << 12); + u32RegTIME |= ((u32Minute % 10ul) << 8); + u32RegTIME |= ((u32Second / 10ul) << 4); + u32RegTIME |= (u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(u32TimeMode == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + RTC_WaitAccessEnable(); + RTC->TIME = (uint32_t)u32RegTIME; +} + +/** + * @brief Update RTC Alarm Date + * + * @param[in] u32Year The year calendar digit of RTC alarm setting. + * @param[in] u32Month The month calendar digit of RTC alarm setting. + * @param[in] u32Day The day calendar digit of RTC alarm setting. + * + * @return None + * + * @details This API is used to update alarm date setting to RTC. + */ +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day) +{ + uint32_t u32RegCALM; + + u32RegCALM = ((u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCALM |= ((u32Month / 10ul) << 12); + u32RegCALM |= ((u32Month % 10ul) << 8); + u32RegCALM |= ((u32Day / 10ul) << 4); + u32RegCALM |= (u32Day % 10ul); + + RTC_WaitAccessEnable(); + + /* Set RTC Alarm Date */ + RTC->CALM = (uint32_t)u32RegCALM; +} + +/** + * @brief Update RTC Alarm Time + * + * @param[in] u32Hour The hour time digit of RTC alarm setting. + * @param[in] u32Minute The minute time digit of RTC alarm setting. + * @param[in] u32Second The second time digit of RTC alarm setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update alarm time setting to RTC. + */ +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTALM; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + { + u32Hour += 20ul; + } + + u32RegTALM = ((u32Hour / 10ul) << 20); + u32RegTALM |= ((u32Hour % 10ul) << 16); + u32RegTALM |= ((u32Minute / 10ul) << 12); + u32RegTALM |= ((u32Minute % 10ul) << 8); + u32RegTALM |= ((u32Second / 10ul) << 4); + u32RegTALM |= (u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(u32TimeMode == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set RTC Alarm Time */ + RTC_WaitAccessEnable(); + RTC->TALM = (uint32_t)u32RegTALM; +} + +/** + * @brief Set RTC Alarm Date Mask Function + * + * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled. + * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled. + * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm date mask function. + */ +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk) +{ + RTC_WaitAccessEnable(); + RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) | + ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) | + ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) | + ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) | + ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos); +} + +/** + * @brief Set RTC Alarm Time Mask Function + * + * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled. + * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled. + * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm time mask function. + */ +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk) +{ + RTC_WaitAccessEnable(); + RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) | + ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) | + ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) | + ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) | + ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos); +} + +/** + * @brief Get Day of the Week + * + * @param None + * + * @retval 0 Sunday + * @retval 1 Monday + * @retval 2 Tuesday + * @retval 3 Wednesday + * @retval 4 Thursday + * @retval 5 Friday + * @retval 6 Saturday + * + * @details This API is used to get day of the week of current RTC date. + */ +uint32_t RTC_GetDayOfWeek(void) +{ + return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk); +} + +/** + * @brief Set RTC Tick Period Time + * + * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n + * It consists of: + * - \ref RTC_TICK_1_SEC : Time tick is 1 second + * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second + * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second + * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second + * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second + * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second + * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second + * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second + * + * @return None + * + * @details This API is used to set RTC tick period time for each tick interrupt. + */ +void RTC_SetTickPeriod(uint32_t u32TickSelection) +{ + RTC_WaitAccessEnable(); + + RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection; +} + +/** + * @brief Enable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt + * + * @return None + * + * @details This API is used to enable the specify RTC interrupt function. + */ +void RTC_EnableInt(uint32_t u32IntFlagMask) +{ + RTC_WaitAccessEnable(); + RTC->INTEN |= u32IntFlagMask; +} + +/** + * @brief Disable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 Pin Event Detection interrupt + * + * @return None + * + * @details This API is used to disable the specify RTC interrupt function. + */ +void RTC_DisableInt(uint32_t u32IntFlagMask) +{ + RTC_WaitAccessEnable(); + RTC->INTEN &= ~u32IntFlagMask; + RTC_WaitAccessEnable(); + RTC->INTSTS = u32IntFlagMask; +} + +/** + * @brief Enable Spare Registers Access + * + * @param None + * + * @return None + * + * @details This API is used to enable the spare registers 0~19 can be accessed. + */ +void RTC_EnableSpareAccess(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Disable Spare Register + * + * @param None + * + * @return None + * + * @details This API is used to disable the spare register 0~19 cannot be accessed. + */ +void RTC_DisableSpareRegister(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Static Tamper Detect + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER5_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER0_SELECT + * + * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are + * - \ref RTC_TAMPER_HIGH_LEVEL_DETECT + * - \ref RTC_TAMPER_LOW_LEVEL_DETECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @return None + * + * @details This API is used to enable the tamper pin detect function with specify trigger condition. + */ +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32TmpReg = ( RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) | + (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos) ); + + for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1ul << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk|RTC_TAMPCTL_TAMP0LV_Msk|RTC_TAMPCTL_TAMP0DBEN_Msk) << (i*4ul)); + u32Reg |= (u32TmpReg << (i*4ul)); + } + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; + +} + +/** + * @brief Static Tamper Disable + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER5_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER0_SELECT + * + * @return None + * + * @details This API is used to disable the static tamper pin detect. + */ +void RTC_StaticTamperDisable(uint32_t u32TamperSelect) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk); + + for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1ul << i)) + { + u32Reg &= ~(u32TmpReg << (i*4ul)); + } + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Detect + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @param[in] u32Pair1Source Dynamic Pair 1 Input Source Select + * 0: Pair 1 source select tamper 2 + * 1: Pair 1 source select tamper 0 + * + * @param[in] u32Pair2Source Dynamic Pair 2 Input Source Select + * 0: Pair 2 source select tamper 4 + * 1: Pair 2 source select tamper 0 + * + * @return None + * + * @details This API is used to enable the dynamic tamper. + */ +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2Debounce, u32Tamper4Debounce; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk; + u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk; + + u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk | + RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk); + u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk); + u32Reg |= ((u32Pair1Source & 0x1ul) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1ul) << RTC_TAMPCTL_DYN2ISS_Pos); + + if(u32DebounceEn) + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | + RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + else + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + + for(i = 0ul; i < MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1ul << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i*8ul)); + u32Reg |= (u32TmpReg << (i*8ul)); + } + } + + if((u32Pair1Source) && (u32PairSel & RTC_PAIR1_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk; + u32Reg |= u32Tamper2Debounce; + } + + if((u32Pair2Source) && (u32PairSel & RTC_PAIR2_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk; + u32Reg |= u32Tamper4Debounce; + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Disable + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @return None + * + * @details This API is used to disable the dynamic tamper. + */ +void RTC_DynamicTamperDisable(uint32_t u32PairSel) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2En = 0ul, u32Tamper4En = 0ul; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + if((u32Reg & RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & RTC_PAIR1_SELECT)) + { + u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk; + } + + if((u32Reg & RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & RTC_PAIR2_SELECT)) + { + u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk; + } + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + + for(i = 0ul; i < MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1ul << i)) + { + u32Reg &= ~(u32TmpReg << ((i*8ul))); + } + } + + u32Reg |= (u32Tamper2En | u32Tamper4En); + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Config dynamic tamper + * + * @param[in] u32ChangeRate The dynamic tamper output change rate + * - \ref RTC_2POW10_CLK + * - \ref RTC_2POW11_CLK + * - \ref RTC_2POW12_CLK + * - \ref RTC_2POW13_CLK + * - \ref RTC_2POW14_CLK + * - \ref RTC_2POW15_CLK + * - \ref RTC_2POW16_CLK + * - \ref RTC_2POW17_CLK + * + * @param[in] u32SeedReload Reload new seed or not + * 0: not reload new seed + * 1: reload new seed + * + * @param[in] u32RefPattern Reference pattern + * - \ref REF_RANDOM_PATTERN + * - \ref REF_PREVIOUS_PATTERN + * - \ref REF_SEED + * + * @param[in] u32Seed Seed Value (0x0 ~ 0xFFFFFFFF) + * + * @return None + * + * @details This API is used to config dynamic tamper setting. + */ +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed) +{ + uint32_t u32Reg; + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk); + + u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1ul) << RTC_TAMPCTL_SEEDRLD_Pos) | + ((u32RefPattern & 0x3ul) << RTC_TAMPCTL_DYNSRC_Pos); + + RTC_WaitAccessEnable(); + RTC->TAMPSEED = u32Seed; /* need set seed value before re-load seed */ + RTC->TAMPCTL = u32Reg; +} + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/sc.c b/bsp/nuvoton_m487/libraries/StdDriver/src/sc.c new file mode 100644 index 00000000000..a03cddf5fb0 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/sc.c @@ -0,0 +1,399 @@ +/**************************************************************************//** + * @file sc.c + * @version V3.00 + * @brief M480 Smartcard(SC) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ +static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL}; + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions + @{ +*/ + +/** + * @brief This function indicates specified smartcard slot status + * @param[in] sc Base address of smartcard module + * @return Card insert status + * @retval TRUE Card insert + * @retval FALSE Card remove + */ +uint32_t SC_IsCardInserted(SC_T *sc) +{ + uint32_t ret; + /* put conditions into two variable to remove IAR compilation warning */ + uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos); + uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos); + + if((sc == SC0) && (u32CardStateIgnore[0] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if((sc == SC1) && (u32CardStateIgnore[1] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if((sc == SC2) && (u32CardStateIgnore[2] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if(cond1 != cond2) + { + ret = (uint32_t)FALSE; + } + else + { + ret = (uint32_t)TRUE; + } + return ret; +} + +/** + * @brief This function reset both transmit and receive FIFO of specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_ClearFIFO(SC_T *sc) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk); +} + +/** + * @brief This function disable specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_Close(SC_T *sc) +{ + sc->INTEN = 0UL; + while(sc->PINCTL & SC_PINCTL_SYNC_Msk) + { + ; + } + sc->PINCTL = 0UL; + sc->ALTCTL = 0UL; + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL = 0UL; +} + +/** + * @brief This function initialized smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32CardDet Card detect polarity, select the CD pin state which indicates card absent. Could be + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present + * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * @return None + */ +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR) +{ + uint32_t u32Reg = 0UL, u32Intf; + + if(sc == SC0) + { + u32Intf = 0UL; + } + else if(sc == SC1) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + if(u32CardDet != SC_PIN_STATE_IGNORE) + { + u32Reg = u32CardDet ? 0UL: SC_CTL_CDLV_Msk; + u32CardStateIgnore[u32Intf] = 0UL; + } + else + { + u32CardStateIgnore[u32Intf] = 1UL; + } + sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk; + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg; +} + +/** + * @brief This function reset specified smartcard module to its default state for activate smartcard + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_ResetReader(SC_T *sc) +{ + uint32_t u32Intf; + + if(sc == SC0) + { + u32Intf = 0UL; + } + else if(sc == SC1) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + /* Reset FIFO, enable auto de-activation while card removal */ + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk); + /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */ + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | + SC_CTL_CDDBSEL_Msk | + SC_CTL_TXRTY_Msk | + SC_CTL_TXRTYEN_Msk | + SC_CTL_RXRTY_Msk | + SC_CTL_RXRTYEN_Msk); + while(sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Enable auto convention, and all three smartcard internal timers */ + sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk; + /* Disable Rx timeout */ + sc->RXTOUT = 0UL; + /* 372 clocks per ETU by default */ + sc->ETUCTL= 371UL; + + + /* Enable necessary interrupt for smartcard operation */ + if(u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */ + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + else + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_CDIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + return; +} + +/** + * @brief This function block guard time (BGT) of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32 + * @return None + */ +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT) +{ + sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos); +} + +/** + * @brief This function character guard time (CGT) of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267 + * @return None + */ +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT) +{ + u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11UL: 12UL; + sc->EGT = u32CGT; +} + +/** + * @brief This function stop all smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + * @note This function stop the timers within smartcard module, \b not timer module + */ +void SC_StopAllTimer(SC_T *sc) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk); +} + +/** + * @brief This function configure and start a smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32TimerNum Timer to start. Valid values are 0, 1, 2. + * @param[in] u32Mode Timer operating mode, valid values are: + * - \ref SC_TMR_MODE_0 + * - \ref SC_TMR_MODE_1 + * - \ref SC_TMR_MODE_2 + * - \ref SC_TMR_MODE_3 + * - \ref SC_TMR_MODE_4 + * - \ref SC_TMR_MODE_5 + * - \ref SC_TMR_MODE_6 + * - \ref SC_TMR_MODE_7 + * - \ref SC_TMR_MODE_8 + * - \ref SC_TMR_MODE_F + * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs. + * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs + * @return None + * @note This function start the timer within smartcard module, \b not timer module + * @note Depend on the timer operating mode, timer may not start counting immediately + */ +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount) +{ + uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL)); + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + if(u32TimerNum == 0UL) + { + while(sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) + { + ; + } + sc->TMRCTL0 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) + { + while(sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) + { + ; + } + sc->TMRCTL1 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + while(sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) + { + ; + } + sc->TMRCTL2 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief This function stop a smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32TimerNum Timer to stop. Valid values are 0, 1, 2. + * @return None + * @note This function stop the timer within smartcard module, \b not timer module + */ +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + if(u32TimerNum == 0UL) + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief This function gets smartcard clock frequency. + * @param[in] sc Base address of smartcard module + * @return Smartcard frequency in kHz + */ +uint32_t SC_GetInterfaceClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk; + + if(sc == SC0) + { + u32Num = 0UL; + } + else if(sc == SC1) + { + u32Num = 1UL; + } + else + { + u32Num = 2UL; + } + + u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk; + + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32Clk = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32Clk = CLK_GetPCLK1Freq(); + } + else + { + u32Clk = CLK_GetPCLK0Freq(); + } + } + else + { + u32Clk = __HIRC; + } + + u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL) * 1000UL; + return u32Clk; +} + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/scuart.c b/bsp/nuvoton_m487/libraries/StdDriver/src/scuart.c new file mode 100644 index 00000000000..44a7890db5b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/scuart.c @@ -0,0 +1,241 @@ +/**************************************************************************//** + * @file scuart.c + * @version V3.00 + * @brief M480 Smartcard UART mode (SCUART) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +static uint32_t SCUART_GetClock(SC_T *sc); + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/** + * @brief The function is used to disable smartcard interface UART mode. + * @param sc The base address of smartcard module. + * @return None + */ +void SCUART_Close(SC_T* sc) +{ + sc->INTEN = 0UL; + sc->UARTCTL = 0UL; + sc->CTL = 0UL; + +} +/** @cond HIDDEN_SYMBOLS */ +/** + * @brief This function returns module clock of specified SC interface + * @param[in] sc The base address of smartcard module. + * @return Module clock of specified SC interface + */ +static uint32_t SCUART_GetClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk; + + if(sc == SC0) + { + u32Num = 0UL; + } + else if(sc == SC1) + { + u32Num = 1UL; + } + else + { + u32Num = 2UL; + } + + u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk; + + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32Clk = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32Clk = CLK_GetPCLK1Freq(); + } + else + { + u32Clk = CLK_GetPCLK0Freq(); + } + } + else + { + u32Clk = __HIRC; + } + + u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL); + + + return u32Clk; +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief This function use to enable smartcard module UART mode and set baudrate. + * @param[in] sc The base address of smartcard module. + * @param[in] u32baudrate Target baudrate of smartcard module. + * @return Actual baudrate of smartcard mode + * @details This function configures character width to 8 bits, 1 stop bit, and no parity. + * And can use \ref SCUART_SetLineConfig function to update these settings + * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate) +{ + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32baudrate >> 1) - 1UL) / u32baudrate - 1UL; + + /* Enable smartcard interface and stop bit = 1 */ + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; + /* Enable UART mode, disable parity and 8 bit per character */ + sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; + sc->ETUCTL = u32Div; + + return(u32Clk / (u32Div + 1UL)); +} + +/** + * @brief The function is used to read Rx data from RX FIFO. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8RxBuf The buffer to store receive the data + * @param[in] u32ReadBytes Target number of characters to receive + * @return Actual character number reads to buffer + * @note This function does not block and return immediately if there's no data available + */ +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++) + { + if(SCUART_GET_RX_EMPTY(sc)) /* no data available */ + { + break; + } + pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); /* get data from FIFO */ + } + + return u32Count; +} + +/** + * @brief This function use to configure smartcard UART mode line setting. + * @param[in] sc The base address of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change. + * @param[in] u32DataWidth The data length, could be + * - \ref SCUART_CHAR_LEN_5 + * - \ref SCUART_CHAR_LEN_6 + * - \ref SCUART_CHAR_LEN_7 + * - \ref SCUART_CHAR_LEN_8 + * @param[in] u32Parity The parity setting, could be + * - \ref SCUART_PARITY_NONE + * - \ref SCUART_PARITY_ODD + * - \ref SCUART_PARITY_EVEN + * @param[in] u32StopBits The stop bit length, could be + * - \ref SCUART_STOP_BIT_1 + * - \ref SCUART_STOP_BIT_2 + * @return Actual baudrate of smartcard + * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + if(u32Baudrate == 0UL) /* keep original baudrate setting */ + { + u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk; + } + else + { + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL)/ u32Baudrate - 1UL; + sc->ETUCTL = u32Div; + } + /* Set stop bit */ + sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; + /* Set character width and parity */ + sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; + + return(u32Clk / (u32Div + 1UL)); +} + +/** + * @brief This function use to set receive timeout count. + * @param[in] sc The base address of smartcard module. + * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF, + * set this value to 0 will disable timeout counter + * @return None + * @details The time-out counter resets and starts counting whenever the RX buffer received a + * new data word. Once the counter decrease to 1 and no new data is received or CPU + * does not read any data from FIFO, a receiver time-out interrupt will be generated. + */ +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC) +{ + sc->RXTOUT= u32TOC; +} + + +/** + * @brief This function is to write data into transmit FIFO to send data out. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO. + * @param[in] u32WriteBytes Number of data to send. + * @return None + * @note This function blocks until all data write into FIFO + */ +void SCUART_Write(SC_T* sc,uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++) + { + /* Wait 'til FIFO not full */ + while(SCUART_GET_TX_FULL(sc)) + { + ; + } + /* Write 1 byte to FIFO */ + sc->DAT = pu8TxBuf[u32Count]; + } +} + + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/sdh.c b/bsp/nuvoton_m487/libraries/StdDriver/src/sdh.c new file mode 100644 index 00000000000..5a807b698b2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/sdh.c @@ -0,0 +1,1262 @@ +/**************************************************************************//** + * @file SDH.c + * @version V1.00 + * @brief M480 SDH driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ +#define SDH_BLOCK_SIZE 512ul + +/** @cond HIDDEN_SYMBOLS */ + +/* global variables */ +/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */ +/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */ +/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */ +uint8_t g_u8R3Flag = 0ul; +uint8_t volatile g_u8SDDataReadyFlag = FALSE; + +static uint32_t _SDH_uR7_CMD = 0ul; +static uint32_t _SDH_ReferenceClock; + +#ifdef __ICCARM__ +#pragma data_alignment = 4 +static uint8_t _SDH_ucSDHCBuffer[512]; +#else +static uint8_t _SDH_ucSDHCBuffer[512] __attribute__((aligned(4))); +#endif + +int SDH_ok = 0; + +SDH_INFO_T SD0, SD1; + +void SDH_CheckRB(SDH_T *sdh) +{ + while(1) + { + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + if ((sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk) == SDH_INTSTS_DAT0STS_Msk) + { + break; + } + } +} + + +uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg) +{ + volatile uint32_t buf, val = 0ul; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)|(SDH_CTL_COEN_Msk); + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_COEN_Msk) == SDH_CTL_COEN_Msk) + { + if (pSD->IsCardInsert == 0ul) + { + val = SDH_NO_SD_CARD; + } + } + return val; +} + + +uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t ntickCount) +{ + volatile uint32_t buf; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk); + sdh->CTL = buf; + + if (ntickCount > 0ul) + { + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if(ntickCount-- == 0ul) + { + sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */ + return 2ul; + } + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + else + { + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + + if (_SDH_uR7_CMD) + { + uint32_t tmp0 = 0ul, tmp1= 0ul; + tmp1 = sdh->RESP1 & 0xfful; + tmp0 = sdh->RESP0 & 0xful; + if ((tmp1 != 0x55ul) && (tmp0 != 0x01ul)) + { + _SDH_uR7_CMD = 0ul; + return SDH_CMD8_ERROR; + } + } + + if (!g_u8R3Flag) + { + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return Successful; + } + else + { + return SDH_CRC7_ERROR; + } + } + else + { + /* ignore CRC error for R3 case */ + g_u8R3Flag = 0ul; + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return Successful; + } +} + + +uint32_t SDH_Swap32(uint32_t val) +{ + uint32_t buf; + + buf = val; + val <<= 24; + val |= (buf<<8) & 0xff0000ul; + val |= (buf>>8) & 0xff00ul; + val |= (buf>>24)& 0xfful; + return val; +} + +/* Get 16 bytes CID or CSD */ +uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t puR2ptr[]) +{ + uint32_t i, buf; + uint32_t tmpBuf[5]; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk); + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_R2EN_Msk) == SDH_CTL_R2EN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) + { + for (i=0ul; i<5ul; i++) + { + tmpBuf[i] = SDH_Swap32(sdh->FB[i]); + } + for (i=0ul; i<4ul; i++) + { + puR2ptr[i] = ((tmpBuf[i] & 0x00fffffful)<<8) | ((tmpBuf[i+1ul] & 0xff000000ul)>>24); + } + } + else + { + return SDH_CRC7_ERROR; + } + return Successful; +} + + +uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg) +{ + volatile uint32_t buf; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)| + (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + while ((sdh->CTL & SDH_CTL_DIEN_Msk) == SDH_CTL_DIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) + { + /* check CRC7 */ + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) + { + /* check CRC16 */ + return SDH_CRC16_ERROR; + } + return 0ul; +} + +/* there are 8 bits for divider0, maximum is 256 */ +#define SDH_CLK_DIV0_MAX 256ul + +void SDH_Set_clock(SDH_T *sdh, uint32_t sd_clock_khz) +{ + uint32_t rate, div1; + static uint32_t u32SD_ClkSrc = 0ul, u32SD_PwrCtl = 0ul; + + SYS_UnlockReg(); + + /* initial state, clock source use HIRC */ + if (sd_clock_khz <= 400ul) + { + u32SD_PwrCtl = CLK->PWRCTL; + if ((u32SD_PwrCtl & CLK_PWRCTL_HIRCEN_Msk) != 0x4ul) + { + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + } + + if (sdh == SDH0) + { + u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | CLK_CLKSEL0_SDH0SEL_HIRC; + } + else + { + u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH1SEL_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | CLK_CLKSEL0_SDH1SEL_HIRC; + } + _SDH_ReferenceClock = (__HIRC / 1000ul); + } + /* transfer state, clock source use sys_init() */ + else + { + CLK->PWRCTL = u32SD_PwrCtl; + if (sdh == SDH0) + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | u32SD_ClkSrc; + if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HXT) + { + _SDH_ReferenceClock = (CLK_GetHXTFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HIRC) + { + _SDH_ReferenceClock = (__HIRC / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_PLL) + { + _SDH_ReferenceClock = (CLK_GetPLLClockFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HCLK) + { + _SDH_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul); + } + } + else + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | u32SD_ClkSrc; + if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HXT) + { + _SDH_ReferenceClock = (CLK_GetHXTFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HIRC) + { + _SDH_ReferenceClock = (__HIRC / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_PLL) + { + _SDH_ReferenceClock = (CLK_GetPLLClockFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HCLK) + { + _SDH_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul); + } + } + + if(sd_clock_khz >= 50000ul) + { + sd_clock_khz = 50000ul; + } + } + rate = _SDH_ReferenceClock / sd_clock_khz; + + /* choose slower clock if system clock cannot divisible by wanted clock */ + if ((_SDH_ReferenceClock % sd_clock_khz) != 0ul) + { + rate++; + } + + if(rate >= SDH_CLK_DIV0_MAX) + { + rate = SDH_CLK_DIV0_MAX; + } + + /*--- calculate the second divider CLKDIV0[SDHOST_N]*/ + div1 = (rate - 1ul) & 0xFFul; + + /*--- setup register */ + if (sdh == SDH0) + { + CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk; + CLK->CLKDIV0 |= (div1 << CLK_CLKDIV0_SDH0DIV_Pos); + } + else + { + CLK->CLKDIV3 &= ~CLK_CLKDIV3_SDH1DIV_Msk; + CLK->CLKDIV3 |= (div1 << CLK_CLKDIV3_SDH1DIV_Pos); + } + return; +} + +uint32_t SDH_CardDetection(SDH_T *sdh) +{ + uint32_t i, val = TRUE; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + + if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) == SDH_INTEN_CDSRC_Msk) /* Card detect pin from GPIO */ + { + if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) /* Card remove */ + { + pSD->IsCardInsert = (uint8_t)FALSE; + val = FALSE; + } + else + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + } + else if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) != SDH_INTEN_CDSRC_Msk) + { + sdh->CTL |= SDH_CTL_CLKKEEP_Msk; + for(i= 0ul; i < 5000ul; i++) + { + } + + if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) /* Card insert */ + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + else + { + pSD->IsCardInsert = (uint8_t)FALSE; + val = FALSE; + } + + sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk; + } + + return val; +} + +uint32_t SDH_Init(SDH_T *sdh) +{ + uint32_t volatile i, status; + uint32_t resp; + uint32_t CIDBuffer[4]; + uint32_t volatile u32CmdTimeOut; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + /* set the clock to 300KHz */ + SDH_Set_clock(sdh, 300ul); + + /* power ON 74 clock */ + sdh->CTL |= SDH_CTL_CLK74OEN_Msk; + + while ((sdh->CTL & SDH_CTL_CLK74OEN_Msk) == SDH_CTL_CLK74OEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + SDH_SDCommand(sdh, 0ul, 0ul); /* reset all cards */ + for (i=0x1000ul; i>0ul; i--) + { + } + + /* initial SDHC */ + _SDH_uR7_CMD = 1ul; + u32CmdTimeOut = 0xFFFFFul; + + i = SDH_SDCmdAndRsp(sdh, 8ul, 0x00000155ul, u32CmdTimeOut); + if (i == Successful) + { + /* SD 2.0 */ + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + g_u8R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 2.7v-3.6v */ + resp = sdh->RESP0; + + while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + g_u8R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + } + if ((resp & 0x00400000ul) == 0x00400000ul) + { + pSD->CardType = SDH_TYPE_SD_HIGH; + } + else + { + pSD->CardType = SDH_TYPE_SD_LOW; + } + } + else + { + /* SD 1.1 */ + SDH_SDCommand(sdh, 0ul, 0ul); /* reset all cards */ + for (i=0x100ul; i>0ul; i--) + { + } + + i = SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + if (i == 2ul) /* MMC memory */ + { + + SDH_SDCommand(sdh, 0ul, 0ul); /* reset */ + for (i=0x100ul; i>0ul; i--) + { + } + + g_u8R3Flag = 1ul; + + if (SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut) != 2ul) /* eMMC memory */ + { + resp = sdh->RESP0; + while ((resp & 0x00800000ul) != 0x00800000ul) + { + /* check if card is ready */ + g_u8R3Flag = 1ul; + + SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut); /* high voltage */ + resp = sdh->RESP0; + } + + if ((resp & 0x00400000ul) == 0x00400000ul) + { + pSD->CardType = SDH_TYPE_EMMC; + } + else + { + pSD->CardType = SDH_TYPE_MMC; + } + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_ERR_DEVICE; + } + } + else if (i == 0ul) /* SD Memory */ + { + g_u8R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + g_u8R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + } + pSD->CardType = SDH_TYPE_SD_LOW; + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_INIT_ERROR; + } + } + + if (pSD->CardType != SDH_TYPE_UNKNOWN) + { + SDH_SDCmdAndRsp2(sdh, 2ul, 0x00ul, CIDBuffer); + if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x10000ul, 0ul)) != Successful) /* set RCA */ + { + return status; + } + pSD->RCA = 0x10000ul; + } + else + { + if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x00ul, 0ul)) != Successful) /* get RCA */ + { + return status; + } + else + { + pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000; + } + } + } + return Successful; +} + + +uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD) +{ + uint32_t volatile status=0ul; + uint16_t current_comsumption, busy_status0; + + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; + sdh->BLEN = 63ul; + + if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x00ffff01ul)) != Successful) + { + return Fail; + } + + current_comsumption = (uint16_t)_SDH_ucSDHCBuffer[0] << 8; + current_comsumption |= (uint16_t)_SDH_ucSDHCBuffer[1]; + if (!current_comsumption) + { + return Fail; + } + + busy_status0 = (uint16_t)_SDH_ucSDHCBuffer[28] << 8; + busy_status0 |= (uint16_t)_SDH_ucSDHCBuffer[29]; + + if (!busy_status0) /* function ready */ + { + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; + sdh->BLEN = 63ul; /* 512 bit */ + + if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x80ffff01ul)) != Successful) + { + return Fail; + } + + /* function change timing: 8 clocks */ + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + current_comsumption = (uint16_t)_SDH_ucSDHCBuffer[0] << 8; + current_comsumption |= (uint16_t)_SDH_ucSDHCBuffer[1]; + if (!current_comsumption) + { + return Fail; + } + + return Successful; + } + else + { + return Fail; + } +} + + +uint32_t SDH_SelectCardType(SDH_T *sdh) +{ + uint32_t volatile status=0ul; + uint32_t param; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + SDH_CheckRB(sdh); + + /* if SD card set 4bit */ + if (pSD->CardType == SDH_TYPE_SD_HIGH) + { + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; + sdh->BLEN = 0x07ul; /* 64 bit */ + sdh->DMACTL |= SDH_DMACTL_DMARST_Msk; + while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == 0x2); + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful) + { + return status; + } + + if ((_SDH_ucSDHCBuffer[0] & 0xful) == 0x2ul) + { + status = SDH_SwitchToHighSpeed(sdh, pSD); + if (status == Successful) + { + /* divider */ + SDH_Set_clock(sdh, SDHC_FREQ); + } + } + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) /* set bus width */ + { + return status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if (pSD->CardType == SDH_TYPE_SD_LOW) + { + sdh->DMASA = (uint32_t) _SDH_ucSDHCBuffer; + sdh->BLEN = 0x07ul; + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful) + { + return status; + } + + /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */ + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) + { + return status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if ((pSD->CardType == SDH_TYPE_MMC) ||(pSD->CardType == SDH_TYPE_EMMC)) + { + + if(pSD->CardType == SDH_TYPE_MMC) + { + sdh->CTL &= ~SDH_CTL_DBW_Msk; + } + + /*--- sent CMD6 to MMC card to set bus width to 4 bits mode */ + /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */ + param = (3ul << 24) | (183ul << 16) | (1ul << 8); + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, param, 0ul)) != Successful) + { + return status; + } + SDH_CheckRB(sdh); + + sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */ + + } + + if ((status = SDH_SDCmdAndRsp(sdh, 16ul, SDH_BLOCK_SIZE, 0ul)) != Successful) + { + return status; + } + sdh->BLEN = SDH_BLOCK_SIZE - 1ul; + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk; + + return Successful; +} + +void SDH_Get_SD_info(SDH_T *sdh) +{ + unsigned int R_LEN, C_Size, MULT, size; + uint32_t Buffer[4]; + //unsigned char *ptr; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + SDH_SDCmdAndRsp2(sdh, 9ul, pSD->RCA, Buffer); + + if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + /* for MMC/eMMC card */ + if ((Buffer[0] & 0xc0000000) == 0xc0000000) + { + /* CSD_STRUCTURE [127:126] is 3 */ + /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */ + SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul); + + //ptr = (uint8_t *)((uint32_t)_SDH_ucSDHCBuffer ); + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; + sdh->BLEN = 511ul; /* read 512 bytes for EXT_CSD */ + + if (SDH_SDCmdAndRspDataIn(sdh, 8ul, 0x00ul) == Successful) + { + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + pSD->totalSectorN = (uint32_t)_SDH_ucSDHCBuffer[215]<<24; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[214]<<16; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[213]<<8; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[212]; + pSD->diskSize = pSD->totalSectorN / 2ul; + } + } + else + { + /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */ + R_LEN = (Buffer[1] & 0x000f0000ul) >> 16; + C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30); + MULT = (Buffer[2] & 0x00038000ul) >> 15; + size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<diskSize = size / 1024ul; + pSD->totalSectorN = size / 512ul; + } + } + else + { + if ((Buffer[0] & 0xc0000000) != 0x0ul) + { + C_Size = ((Buffer[1] & 0x0000003ful) << 16) | ((Buffer[2] & 0xffff0000ul) >> 16); + size = (C_Size+1ul) * 512ul; /* Kbytes */ + + pSD->diskSize = size; + pSD->totalSectorN = size << 1; + } + else + { + R_LEN = (Buffer[1] & 0x000f0000ul) >> 16; + C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30); + MULT = (Buffer[2] & 0x00038000ul) >> 15; + size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<diskSize = size / 1024ul; + pSD->totalSectorN = size / 512ul; + } + } + pSD->sectorSize = (int)512; +} + +/** @endcond HIDDEN_SYMBOLS */ + + +/** + * @brief This function use to reset SD function and select card detection source and pin. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32CardDetSrc Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3) + * + * @return None + */ +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc) +{ + sdh->DMACTL = SDH_DMACTL_DMARST_Msk; + while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == SDH_DMACTL_DMARST_Msk) + { + } + + sdh->DMACTL = SDH_DMACTL_DMAEN_Msk; + + sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk; + while ((sdh->GCTL & SDH_GCTL_GCTLRST_Msk) == SDH_GCTL_GCTLRST_Msk) + { + } + + if (sdh == SDH0) + { + NVIC_EnableIRQ(SDH0_IRQn); + memset(&SD0, 0, sizeof(SDH_INFO_T)); + } + else if (sdh == SDH1) + { + NVIC_EnableIRQ(SDH1_IRQn); + memset(&SD1, 0, sizeof(SDH_INFO_T)); + } + else + { + } + + sdh->GCTL = SDH_GCTL_SDEN_Msk; + + if ((u32CardDetSrc & CardDetect_From_DAT3) == CardDetect_From_DAT3) + { + sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk; + } + else + { + sdh->INTEN |= SDH_INTEN_CDSRC_Msk; + } + sdh->INTEN |= SDH_INTEN_CDIEN_Msk; + + sdh->CTL |= SDH_CTL_CTLRST_Msk; + while ((sdh->CTL & SDH_CTL_CTLRST_Msk) == SDH_CTL_CTLRST_Msk) + { + } +} + +/** + * @brief This function use to initial SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return None + * + * @details This function is used to initial SD card. + * SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source. + * And then switch back to the user's setting. + */ +uint32_t SDH_Probe(SDH_T *sdh) +{ + uint32_t val; + + sdh->GINTEN = 0ul; + sdh->CTL &= ~SDH_CTL_SDNWR_Msk; + sdh->CTL |= 0x09ul << SDH_CTL_SDNWR_Pos; /* set SDNWR = 9 */ + sdh->CTL &= ~SDH_CTL_BLKCNT_Msk; + sdh->CTL |= 0x01ul << SDH_CTL_BLKCNT_Pos; /* set BLKCNT = 1 */ + sdh->CTL &= ~SDH_CTL_DBW_Msk; /* SD 1-bit data bus */ + + if(!(SDH_CardDetection(sdh))) + { + return SDH_NO_SD_CARD; + } + + if ((val = SDH_Init(sdh)) != 0ul) + { + return val; + } + + /* divider */ + if ((SD0.CardType == SDH_TYPE_MMC) || (SD1.CardType == SDH_TYPE_MMC)) + { + SDH_Set_clock(sdh, MMC_FREQ); + } + else + { + SDH_Set_clock(sdh, SD_FREQ); + } + SDH_Get_SD_info(sdh); + + if ((val = SDH_SelectCardType(sdh)) != 0ul) + { + return val; + } + + SDH_ok = 1; + return 0ul; +} + +/** + * @brief This function use to read data from SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[out] pu8BufAddr The buffer to receive the data from SD card. + * @param[in] u32StartSec The start read sector address. + * @param[in] u32SecCount The the read sector number of data + * + * @return None + */ +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile bIsSendCmd = FALSE, buf; + uint32_t volatile reg; + uint32_t volatile i, loop, status; + uint32_t blksize = SDH_BLOCK_SIZE; + + SDH_INFO_T *pSD; + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if (u32SecCount == 0ul) + { + return SDH_SELECT_ERROR; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + SDH_CheckRB(sdh); + + sdh->BLEN = blksize - 1ul; /* the actual byte count is equal to (SDBLEN+1) */ + + if ( (pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC) ) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * blksize; + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + + loop = u32SecCount / 255ul; + for (i=0ul; iCTL & ~SDH_CTL_CMDCODE_Msk; + reg = reg | 0xff0000ul; /* set BLK_CNT to 255 */ + if (bIsSendCmd == FALSE) + { + sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DIEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if(g_u8SDDataReadyFlag) + { + break; + } + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + } + + loop = u32SecCount % 255ul; + if (loop != 0ul) + { + g_u8SDDataReadyFlag = (uint8_t)FALSE; + reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk); + reg = reg & (~SDH_CTL_BLKCNT_Msk); + reg |= (loop << 16); /* setup SDCR_BLKCNT */ + + if (bIsSendCmd == FALSE) + { + sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DIEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + } + + if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + return Successful; +} + + +/** + * @brief This function use to write data to SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] pu8BufAddr The buffer to send the data to SD card. + * @param[in] u32StartSec The start write sector address. + * @param[in] u32SecCount The the write sector number of data. + * + * @return \ref SDH_SELECT_ERROR : u32SecCount is zero. \n + * \ref SDH_NO_SD_CARD : SD card be removed. \n + * \ref SDH_CRC_ERROR : CRC error happen. \n + * \ref SDH_CRC7_ERROR : CRC7 error happen. \n + * \ref Successful : Write data to SD card success. + */ +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile bIsSendCmd = FALSE; + uint32_t volatile reg; + uint32_t volatile i, loop, status; + + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if (u32SecCount == 0ul) + { + return SDH_SELECT_ERROR; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + SDH_CheckRB(sdh); + + /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */ + sdh->BLEN = SDH_BLOCK_SIZE - 1ul; + + if ((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC)) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE; /* set start address for SD CMD */ + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + loop = u32SecCount / 255ul; /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */ + for (i=0ul; iCTL & 0xff00c080; + reg = reg | 0xff0000ul; /* set BLK_CNT to 0xFF=255 */ + if (!bIsSendCmd) + { + sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DOEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul) + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + } + + loop = u32SecCount % 255ul; + if (loop != 0ul) + { + g_u8SDDataReadyFlag = (uint8_t)FALSE; + reg = (sdh->CTL & 0xff00c080) | (loop << 16); + if (!bIsSendCmd) + { + sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DOEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul) + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + } + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + + if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + } + + return Successful; +} + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + + + + + + + + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/spi.c b/bsp/nuvoton_m487/libraries/StdDriver/src/spi.c new file mode 100644 index 00000000000..b0115526187 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/spi.c @@ -0,0 +1,1442 @@ +/**************************************************************************//** + * @file spi.c + * @version V3.00 + * @brief M480 series SPI driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s); + +/** + * @brief This function make SPI module be ready to transfer. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) + * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a SPI transaction. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI peripheral clock. + * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0. + * The actual clock rate may be different from the target SPI clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the + * actual SPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPI_Open(SPI_T *spi, + uint32_t u32MasterSlave, + uint32_t u32SPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue=0U; + + /* Disable I2S mode */ + spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; + + if(u32DataWidth == 32U) + { + u32DataWidth = 0U; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32MasterSlave == SPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + } + else if(spi == SPI1) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + } + else if(spi == SPI2) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + } + } + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0xFFU) + { + u32Div = 0xFFU; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + } + else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(spi == SPI1) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(spi == SPI2) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will reset SPI controller. + */ +void SPI_Close(SPI_T *spi) +{ + if(spi == SPI0) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if(spi == SPI1) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if(spi == SPI2) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + /* Reset SPI */ + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1. + */ +void SPI_ClearRxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void SPI_ClearTxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void SPI_DisableAutoSS(SPI_T *spi) +{ + spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the SPI bus clock. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + else if(spi == SPI1) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + else if(spi == SPI2) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + else + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + } + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. + * @param[in] spi The pointer of the specified SPI module. + * @return Actual SPI bus clock frequency in Hz. + * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t SPI_GetBusClock(SPI_T *spi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + /* Return SPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1U)); +} + +/** + * @brief Enable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL |= SPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL &= ~SPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get SPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = spi->STATUS & SPI_STATUS_UNITIF_Msk; + /* Check unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_UNIT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSACTIF_Msk; + /* Check slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSINAIF_Msk; + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSINACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVURIF_Msk; + /* Check slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVUR_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVBEIF_Msk; + /* Check slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVBE_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXUFIF_Msk; + /* Check slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_TXUF_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXTHIF_Msk; + /* Check TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTHIF_Msk; + /* Check RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXOVIF_Msk; + /* Check RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTOIF_Msk; + /* Check RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear SPI related interrupt flags specified by u32Mask parameter. + */ +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + if(u32Mask & SPI_UNIT_INT_MASK) + { + spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & SPI_SSACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & SPI_SSINACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & SPI_SLVUR_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & SPI_SLVBE_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & SPI_TXUF_INT_MASK) + { + spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXOV_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXTO_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get SPI status. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref SPI_BUSY_MASK + * - \ref SPI_RX_EMPTY_MASK + * - \ref SPI_RX_FULL_MASK + * - \ref SPI_TX_EMPTY_MASK + * - \ref SPI_TX_FULL_MASK + * - \ref SPI_TXRX_RESET_MASK + * - \ref SPI_SPIEN_STS_MASK + * - \ref SPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0U, u32TmpValue; + + u32TmpValue = spi->STATUS & SPI_STATUS_BUSY_Msk; + /* Check busy status */ + if((u32Mask & SPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_BUSY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXEMPTY_Msk; + /* Check RX empty flag */ + if((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXFULL_Msk; + /* Check RX full flag */ + if((u32Mask & SPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXEMPTY_Msk; + /* Check TX empty flag */ + if((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXFULL_Msk; + /* Check TX full flag */ + if((u32Mask & SPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXRXRST_Msk; + /* Check TX/RX reset flag */ + if((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TXRX_RESET_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SPIENSTS_Msk; + /* Check SPIEN flag */ + if((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SPIEN_STS_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SSLINE_Msk; + /* Check SPIx_SS line status */ + if((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The pointer of the specified I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of SPI0SEL (CLKSEL2[27:26]). + */ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s) +{ + uint32_t u32Freq; + + if(i2s == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32Freq = CLK_GetPCLK1Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else if(i2s == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32Freq = CLK_GetPCLK0Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else if(i2s == SPI2) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32Freq = CLK_GetPCLK1Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32Freq = CLK_GetPCLK0Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below. + * - \ref SPII2S_MODE_MASTER + * - \ref SPII2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are listed below. + * - \ref SPII2S_DATABIT_8 + * - \ref SPII2S_DATABIT_16 + * - \ref SPII2S_DATABIT_24 + * - \ref SPII2S_DATABIT_32 + * @param[in] u32Channels Audio format. Valid values are listed below. + * - \ref SPII2S_MONO + * - \ref SPII2S_STEREO + * @param[in] u32DataFormat Data format. Valid values are listed below. + * - \ref SPII2S_FORMAT_I2S + * - \ref SPII2S_FORMAT_MSB + * - \ref SPII2S_FORMAT_PCMA + * - \ref SPII2S_FORMAT_PCMB + * @return Real sample rate of master mode or peripheral clock rate of slave mode. + * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters. + * Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled. + * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat) +{ + uint32_t u32Divider; + uint32_t u32BitRate, u32SrcClk, u32RetValue; + + /* Reset SPI/I2S */ + if(i2s == SPI0) + { + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if(i2s == SPI1) + { + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if(i2s == SPI2) + { + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } + + /* Configure I2S controller */ + i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat; + /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */ + i2s->FIFOCTL = SPII2S_FIFO_TX_LEVEL_WORD_2 | SPII2S_FIFO_RX_LEVEL_WORD_2; + + if(u32MasterSlave == SPI_MASTER) + { + /* Get the source clock rate */ + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + + /* Calculate the bit clock rate */ + u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U; + u32Divider = ((u32SrcClk / u32BitRate) >> 1U) - 1U; + //u32Divider = ((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U; + /* Set BCLKDIV setting */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos); + + /* Calculate bit clock rate */ + u32BitRate = u32SrcClk / ((u32Divider + 1U) * 2U); + /* Calculate real sample rate */ + u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U); + + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + + /* Return the real sample rate */ + u32RetValue = u32SampleRate; + } + else + { + /* Set BCLKDIV = 0 */ + i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk; + + if(i2s == SPI0) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(i2s == SPI1) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(i2s == SPI2) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Disable I2S function. + */ +void SPII2S_Close(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * @return None + * @details This function enables the interrupt according to the u32Mask parameter. + */ +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Enable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk; + } + + /* Enable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * @return None + * @details This function disables the interrupt according to the u32Mask parameter. + */ +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Disable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk; + } + + /* Disable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk; + } +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32BusClock The target MCLK clock rate. + * @return Actual MCLK clock rate + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock) +{ + uint32_t u32Divider; + uint32_t u32SrcClk, u32RetValue; + + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + if(u32BusClock == u32SrcClk) + { + u32Divider = 0U; + } + else + { + u32Divider = (u32SrcClk / u32BusClock) >> 1U; + /* MCLKDIV is a 6-bit width configuration. The maximum value is 0x3F. */ + if(u32Divider > 0x3FU) + { + u32Divider = 0x3FU; + } + } + + /* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos); + + /* Enable MCLK output */ + i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk; + + if(u32Divider == 0U) + { + u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */ + } + else + { + u32RetValue = ((u32SrcClk >> 1U) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */ + } + + return u32RetValue; +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output. + */ +void SPII2S_DisableMCLK(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/spim.c b/bsp/nuvoton_m487/libraries/StdDriver/src/spim.c new file mode 100644 index 00000000000..33fb1c64924 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/spim.c @@ -0,0 +1,1278 @@ +/**************************************************************************//** + * @file spim.c + * @version V1.00 + * @brief M480 series SPIM driver + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPIM_Driver SPIM Driver + @{ +*/ + +/** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions + @{ +*/ + + +/** @cond HIDDEN_SYMBOLS */ + + +#define ENABLE_DEBUG 0 + +#if ENABLE_DEBUG +#define SPIM_DBGMSG printf +#else +#define SPIM_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +static volatile uint8_t g_Supported_List[] = +{ + MFGID_WINBOND, + MFGID_MXIC, + MFGID_EON, + MFGID_ISSI, + MFGID_SPANSION +}; + +static void N_delay(int n); +static void SwitchNBitOutput(uint32_t u32NBit); +static void SwitchNBitInput(uint32_t u32NBit); +static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx); +static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx); +static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static int spim_is_write_done(uint32_t u32NBit); +static int spim_wait_write_done(uint32_t u32NBit); +static void spim_set_write_enable(int isEn, uint32_t u32NBit); +static void spim_enable_spansion_quad_mode(int isEn); +static void spim_eon_set_qpi_mode(int isEn); +static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit); +static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync); +static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, + uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync); + + +static void N_delay(int n) +{ + while (n-- > 0) + { + __NOP(); + } +} + +static void SwitchNBitOutput(uint32_t u32NBit) +{ + switch (u32NBit) + { + case 1UL: + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + break; + + case 2UL: + SPIM_ENABLE_DUAL_OUTPUT_MODE(); /* 2-bit, Output. */ + break; + + case 4UL: + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 4-bit, Output. */ + break; + + default: + break; + } +} + +static void SwitchNBitInput(uint32_t u32NBit) +{ + switch (u32NBit) + { + case 1UL: + SPIM_ENABLE_SING_INPUT_MODE(); /* 1-bit, Input. */ + break; + + case 2UL: + SPIM_ENABLE_DUAL_INPUT_MODE(); /* 2-bit, Input. */ + break; + + case 4UL: + SPIM_ENABLE_QUAD_INPUT_MODE(); /* 4-bit, Input. */ + break; + + default: + break; + } +} + + +/** + * @brief Write data to SPI slave. + * @param pu8TxBuf Transmit buffer. + * @param u32NTx Number of bytes to transmit. + * @return None. + */ +static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx) +{ + uint32_t buf_idx = 0UL; + + while (u32NTx) + { + uint32_t dataNum = 0UL, dataNum2; + + if (u32NTx >= 16UL) + { + dataNum = 4UL; + } + else if (u32NTx >= 12UL) + { + dataNum = 3UL; + } + else if (u32NTx >= 8UL) + { + dataNum = 2UL; + } + else if (u32NTx >= 4UL) + { + dataNum = 1UL; + } + + dataNum2 = dataNum; + while (dataNum2) + { + uint32_t tmp; + + memcpy(&tmp, &pu8TxBuf[buf_idx], 4U); + buf_idx += 4UL; + u32NTx -= 4UL; + + dataNum2 --; + /* *((__O uint32_t *) &SPIM->TX0 + dataNum2) = tmp; */ + SPIM->TX[dataNum2] = tmp; + } + + if (dataNum) + { + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(32UL); + SPIM_SET_DATA_NUM(dataNum); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + } + + if (u32NTx && (u32NTx < 4UL)) + { + uint32_t rnm, tmp; + + rnm = u32NTx; + memcpy(&tmp, &pu8TxBuf[buf_idx], u32NTx); + buf_idx += u32NTx; + u32NTx = 0UL; + SPIM->TX[0] = tmp; + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(rnm * 8UL); + SPIM_SET_DATA_NUM(1UL); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + } + } +} + +/** + * @brief Read data from SPI slave. + * @param pu8TxBuf Receive buffer. + * @param u32NRx Size of receive buffer in bytes. + * @return None. + */ +static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx) +{ + uint32_t buf_idx = 0UL; + + while (u32NRx) + { + uint32_t dataNum = 0UL; /* number of words */ + + if (u32NRx >= 16UL) + { + dataNum = 4UL; + } + else if (u32NRx >= 12UL) + { + dataNum = 3UL; + } + else if (u32NRx >= 8UL) + { + dataNum = 2UL; + } + else if (u32NRx >= 4UL) + { + dataNum = 1UL; + } + + if (dataNum) + { + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(32UL); + SPIM_SET_DATA_NUM(dataNum); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + } + + while (dataNum) + { + uint32_t tmp; + + tmp = SPIM->RX[dataNum-1UL]; + memcpy(&pu8RxBuf[buf_idx], &tmp, 4U); + buf_idx += 4UL; + dataNum --; + u32NRx -= 4UL; + } + + if (u32NRx && (u32NRx < 4UL)) + { + uint32_t tmp; + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(u32NRx * 8UL); + SPIM_SET_DATA_NUM(1UL); + SPIM_SET_GO(); + SPIM_WAIT_FREE(); + + tmp = SPIM->RX[0]; + memcpy(&pu8RxBuf[buf_idx], &tmp, u32NRx); + buf_idx += u32NRx; + u32NRx = 0UL; + } + } +} + +/** + * @brief Issue Read Status Register #1 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Write Status Register #1 command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSR, 0x00U}; /* 1-byte Write Status Register #1 command + 1-byte data. */ + + cmdBuf[1] = dataBuf[0]; + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Read Status Register #2 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR2}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Winbond Write Status Register command. This command write both Status Register-1 + * and Status Register-2. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[3] = {OPCODE_WRSR, 0U, 0U}; + + cmdBuf[1] = dataBuf[0]; + cmdBuf[2] = dataBuf[1]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +#if 0 /* not used */ +/** + * @brief Issue Write Status Register #3 command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSR3, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */ + cmdBuf[1] = dataBuf[0]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} +#endif + +/** + * @brief Issue Read Status Register #3 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR3}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +#if 0 /* not used */ +/** + * @brief Issue Write Security Register command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSCUR, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */ + cmdBuf[1] = dataBuf[0]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} +#endif + +/** + * @brief Issue Read Security Register command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSCUR}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Check if Erase/Write is done. + * @return 0: Not done. 1: Done. + */ +static int spim_is_write_done(uint32_t u32NBit) +{ + uint8_t status[1]; + SPIM_ReadStatusRegister(status, sizeof (status), u32NBit); + return ! (status[0] & SR_WIP); +} + +/** + * @brief Wait until Erase/Write done. + * @param u32NBit N-bit transmit/receive. + * @return 0 SPIM write done. + */ +static int spim_wait_write_done(uint32_t u32NBit) +{ + uint32_t count; + int ret = -1; + + for (count = 0UL; count < SystemCoreClock/1000UL; count++) + { + if (spim_is_write_done(u32NBit)) + { + ret = 0; + break; + } + } + if (ret != 0) + { + SPIM_DBGMSG("spim_wait_write_done time-out!!\n"); + } + return -1; +} + +/** + * @brief Issue Write Enable/disable command. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void spim_set_write_enable(int isEn, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {0U}; /* 1-byte Write Enable command. */ + cmdBuf[0] = isEn ? OPCODE_WREN : OPCODE_WRDI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Get SPIM serial clock. + * @return SPI serial clock. + * @details This function calculates the serial clock of SPI in Hz. + */ +uint32_t SPIM_GetSClkFreq(void) +{ + uint32_t clkDiv = SPIM_GET_CLOCK_DIVIDER(); + + return clkDiv ? SystemCoreClock / (clkDiv * 2U) : SystemCoreClock; +} + +/** + * @brief Initialize SPIM flash. + * @param clrWP Clear Write Protect or not. + * @return 0 Success. + * @return -1 Unrecognized manufacture ID or failed on reading manufacture ID. + */ +int SPIM_InitFlash(int clrWP) +{ + uint8_t idBuf[3]; + uint8_t cmdBuf[1]; + uint32_t i; + int32_t ret = -1; + + SPIM_SET_SS_ACTLVL(0); + + /* + * Because not sure in SPI or QPI mode, do QPI reset and then SPI reset. + */ + /* QPI Reset Enable */ + cmdBuf[0] = OPCODE_RSTEN; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* QPI Reset */ + cmdBuf[0] = OPCODE_RST; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* SPI ResetEnable */ + cmdBuf[0] = OPCODE_RSTEN; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* SPI Reset */ + cmdBuf[0] = OPCODE_RST; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (clrWP) + { + uint8_t dataBuf[] = {0x00U}; + + spim_set_write_enable(1, 1UL); /* Clear Block Protect. */ + SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), 1U); + spim_wait_write_done(1UL); + } + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), 1UL); + + /* printf("ID: 0x%x, 0x%x, px%x\n", idBuf[0], idBuf[1], idBuf[2]); */ + + for (i = 0UL; i < sizeof(g_Supported_List)/sizeof(g_Supported_List[0]); i++) + { + if (idBuf[0] == g_Supported_List[i]) + { + ret = 0; + } + } + if (ret != 0) + { + SPIM_DBGMSG("Flash initialize failed!! 0x%x\n", idBuf[0]); + } + return ret; +} + +/** + * @brief Issue JEDEC ID command. + * @param idBuf ID buffer. + * @param u32NRx Size of ID buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = { OPCODE_RDID }; /* 1-byte JEDEC ID command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(idBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @cond HIDDEN_SYMBOLS */ + +static void spim_enable_spansion_quad_mode(int isEn) +{ + uint8_t cmdBuf[3]; + uint8_t dataBuf[1], status1; + + cmdBuf[0] = 0x5U; /* Read Status Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + /* SPIM_DBGMSG("SR1 = 0x%x\n", dataBuf[0]); */ + + status1 = dataBuf[0]; + + cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */ + + spim_set_write_enable(1, 1UL); + + cmdBuf[0] = 0x1U; /* Write register */ + cmdBuf[1] = status1; + + if (isEn) + { + cmdBuf[2] = dataBuf[0] | 0x2U; /* set QUAD */ + } + else + { + cmdBuf[2] = dataBuf[0] & ~0x2U; /* clear QUAD */ + } + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, 3UL); + SPIM_SET_SS_EN(0); + + spim_set_write_enable(0, 1UL); + + + cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + + /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */ + N_delay(10000); +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Set Quad Enable/disable. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit) +{ + uint8_t idBuf[3]; + uint8_t dataBuf[2]; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + SPIM_DBGMSG("SPIM_SetQuadEnable - Flash ID is 0x%x\n", idBuf[0]); + + switch (idBuf[0]) + { + case MFGID_WINBOND: /* Winbond SPI flash */ + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); + if (isEn) + { + dataBuf[1] |= SR2_QE; + } + else + { + dataBuf[1] &= ~SR2_QE; + } + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); + spim_wait_write_done(u32NBit); + + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); + break; + + case MFGID_MXIC: /* MXIC SPI flash. */ + case MFGID_EON: + case MFGID_ISSI: /* ISSI SPI flash. */ + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + dataBuf[0] = isEn ? SR_QE : 0U; + SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), u32NBit); + spim_wait_write_done(u32NBit); + break; + + case MFGID_SPANSION: + spim_enable_spansion_quad_mode(isEn); + break; + + default: + break; + } +} + +/** + * @brief Enter/exit QPI mode. + * @param isEn Enable/disable. + * @return None. + */ +static void spim_eon_set_qpi_mode(int isEn) +{ + uint8_t cmdBuf[1]; /* 1-byte command. */ + + uint8_t status[1]; + SPIM_ReadStatusRegister(status, sizeof (status), 1UL); + SPIM_DBGMSG("Status: 0x%x\n", status[0]); + + if (isEn) /* Assume in SPI mode. */ + { + cmdBuf[0] = OPCODE_ENQPI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + } + else /* Assume in QPI mode. */ + { + cmdBuf[0] = OPCODE_EXQPI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(4UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + } + + SPIM_ReadStatusRegister(status, sizeof (status), 1UL); + SPIM_DBGMSG("Status: 0x%x\n", status[0]); +} + + +static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit) +{ + uint8_t cmdBuf[2]; + uint8_t dataBuf[1]; + + cmdBuf[0] = OPCODE_BRRD; + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, 1UL); + SwitchNBitInput(1UL); + spim_read(dataBuf, 1UL); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + SPIM_DBGMSG("Bank Address register= 0x%x\n", dataBuf[0]); + + cmdBuf[0] = OPCODE_BRWR; + + if (isEn) + { + cmdBuf[1] = dataBuf[0] | 0x80U; /* set EXTADD */ + } + else + { + cmdBuf[1] = dataBuf[0] & ~0x80U; /* clear EXTADD */ + } + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(1UL); + spim_write(cmdBuf, 2UL); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @cond HIDDEN_SYMBOLS */ + +/** + * @brief Query 4-byte address mode enabled or not. + * @param u32NBit N-bit transmit/receive. + * @return 0: 4-byte address mode disabled. 1: 4-byte address mode enabled. + */ +int SPIM_Is4ByteModeEnable(uint32_t u32NBit) +{ + int isEn = 0; + int isSupt = 0; + uint8_t idBuf[3]; + uint8_t dataBuf[1]; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + /* Based on Flash size, check if 4-byte address mode is supported. */ + switch (idBuf[0]) + { + case MFGID_WINBOND: + case MFGID_MXIC: + case MFGID_EON: + isSupt = (idBuf[2] < 0x19U) ? 0L : 1L; + break; + + case MFGID_ISSI: + isSupt = (idBuf[2] < 0x49U) ? 0L : 1L; + break; + + default: + break; + } + + if (isSupt != 0) + { + if (idBuf[0] == MFGID_WINBOND) + { + /* Winbond SPI flash. */ + SPIM_ReadStatusRegister3(dataBuf, sizeof (dataBuf), u32NBit); + isEn = !! (dataBuf[0] & SR3_ADR); + } + else if ((idBuf[0] == MFGID_MXIC) || (idBuf[0] ==MFGID_EON)) + { + /* MXIC/EON SPI flash. */ + SPIM_ReadSecurityRegister(dataBuf, sizeof (dataBuf), u32NBit); + isEn = !! (dataBuf[0] & SCUR_4BYTE); + } + } + + return isEn; +} + +/** @endcond HIDDEN_SYMBOLS */ + + +/** + * @brief Enter/Exit 4-byte address mode. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return 0 success + * -1 failed + */ +int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit) +{ + int isSupt = 0L, ret = -1; + uint8_t idBuf[3]; + uint8_t cmdBuf[1]; /* 1-byte Enter/Exit 4-Byte Mode command. */ + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + /* Based on Flash size, check if 4-byte address mode is supported. */ + switch (idBuf[0]) + { + case MFGID_WINBOND: + case MFGID_MXIC: + case MFGID_EON: + isSupt = (idBuf[2] < 0x19U) ? 0L : 1L; + break; + + case MFGID_ISSI: + isSupt = (idBuf[2] < 0x49U) ? 0L : 1L; + break; + + case MFGID_SPANSION: + SPIM_SPANSION_4Bytes_Enable(isEn, u32NBit); + isSupt = 1L; + ret = 0L; + break; + + default: + break; + } + + if ((isSupt) && (idBuf[0] != MFGID_SPANSION)) + { + cmdBuf[0] = isEn ? OPCODE_EN4B : OPCODE_EX4B; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* + * FIXME: Per test, 4BYTE Indicator bit doesn't set after EN4B, which + * doesn't match spec(MX25L25635E), so skip the check below. + */ + if (idBuf[0] != MFGID_MXIC) + { + if (isEn) + { + while (! SPIM_Is4ByteModeEnable(u32NBit)) { } + } + else + { + while (SPIM_Is4ByteModeEnable(u32NBit)) { } + } + } + ret = 0; + } + return ret; +} + +/** + * @brief Erase whole chip. + * @param u32NBit N-bit transmit/receive. + * @param isSync Block or not. + * @return None. + */ +void SPIM_ChipErase(uint32_t u32NBit, int isSync) +{ + uint8_t cmdBuf[] = { OPCODE_CHIP_ERASE }; /* 1-byte Chip Erase command. */ + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBit); + } +} + +/** + * @brief Erase one block. + * @param u32Addr Block to erase which contains the u32Addr. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u8ErsCmd Erase command. + * @param u32NBit N-bit transmit/receive. + * @param isSync Block or not. + * @return None. + */ +void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx = 0UL; + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + + cmdBuf[buf_idx++] = u8ErsCmd; + + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL); + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL); + } + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, buf_idx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBit); + } +} + + +/** @cond HIDDEN_SYMBOLS */ + +/** + * @brief Write data in the same page by I/O mode. + * @param u32Addr Start u32Address to write. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @param u32NBitCmd N-bit transmit command. + * @param u32NBitAddr N-bit transmit u32Address. + * @param u32NBitDat N-bit transmit/receive data. + * @param isSync Block or not. + * @return None. + */ +static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx; + + spim_set_write_enable(1, u32NBitCmd); /* Write Enable. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + + SwitchNBitOutput(u32NBitCmd); + cmdBuf[0] = wrCmd; + spim_write(cmdBuf, 1UL); /* Write out command. */ + + buf_idx = 0UL; + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + + SwitchNBitOutput(u32NBitAddr); + spim_write(cmdBuf, buf_idx); /* Write out u32Address. */ + + SwitchNBitOutput(u32NBitDat); + spim_write(pu8TxBuf, u32NTx); /* Write out data. */ + + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBitCmd); + } +} + +/** + * @brief Write data in the same page by Page Write mode. + * @param u32Addr Start u32Address to write. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @param isSync Block or not. + * @return None. + */ +static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, + uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync) +{ + if ((wrCmd == CMD_QUAD_PAGE_PROGRAM_WINBOND) || + (wrCmd == CMD_QUAD_PAGE_PROGRAM_MXIC)) + { + SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */ + } + else if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) + { + SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */ + spim_eon_set_qpi_mode(1); /* Enter QPI mode. */ + } + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEWRITE);/* Switch to Page Write mode. */ + SPIM_SET_SPIM_MODE(wrCmd); /* SPIM mode. */ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */ + + SPIM->SRAMADDR = (uint32_t) pu8TxBuf; /* SRAM u32Address. */ + SPIM->DMACNT = u32NTx; /* Transfer length. */ + SPIM->FADDR = u32Addr; /* Flash u32Address.*/ + SPIM_SET_GO(); /* Go. */ + + if (isSync) + { + SPIM_WAIT_FREE(); + } + + if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) + { + spim_eon_set_qpi_mode(0); /* Exit QPI mode. */ + } +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Write data to SPI Flash by sending commands manually (I/O mode). + * @param u32Addr: Start u32Address to write. + * @param is4ByteAddr: 4-byte u32Address or not. + * @param u32NTx: Number of bytes to write. + * @param pu8TxBuf: Transmit buffer. + * @param wrCmd: Write command. + * @param u32NBitCmd: N-bit transmit command. + * @param u32NBitAddr: N-bit transmit u32Address. + * @param u32NBitDat: N-bit transmit/receive data. + * @return None. + */ +void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat) +{ + uint32_t pageOffset, toWr; + uint32_t buf_idx = 0UL; + + pageOffset = u32Addr % 256UL; + + if ((pageOffset + u32NTx) <= 256UL) /* Do all the bytes fit onto one page ? */ + { + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, u32NTx, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + } + else + { + toWr = 256UL - pageOffset; /* Size of data remaining on the first page. */ + + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + + while (u32NTx) + { + toWr = 256UL; + if (toWr > u32NTx) + { + toWr = u32NTx; + } + + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + } + } +} + +/** + * @brief Read data from SPI Flash by sending commands manually (I/O mode). + * @param u32Addr Start u32Address to read. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NRx Number of bytes to read. + * @param pu8RxBuf Receive buffer. + * @param rdCmd Read command. + * @param u32NBitCmd N-bit transmit command. + * @param u32NBitAddr N-bit transmit u32Address. + * @param u32NBitDat N-bit transmit/receive data. + * @param u32NDummy Number of dummy bytes following address. + * @return None. + */ +void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx; + + SPIM_SET_SS_EN(1); /* CS activated. */ + + cmdBuf[0] = rdCmd; + SwitchNBitOutput(u32NBitCmd); + spim_write(cmdBuf, 1UL); /* Write out command. */ + + buf_idx = 0UL; + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + SwitchNBitOutput(u32NBitAddr); + spim_write(cmdBuf, buf_idx); /* Write out u32Address. */ + + buf_idx = 0UL; + while (u32NDummy --) + { + cmdBuf[buf_idx++] = 0x00U; + } + + /* Same bit mode as above. */ + spim_write(cmdBuf, buf_idx); /* Write out dummy bytes. */ + + SwitchNBitInput(u32NBitDat); + spim_read(pu8RxBuf, u32NRx); /* Read back data. */ + + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Write data to SPI Flash by Page Write mode. + * @param u32Addr Start address to write. + * @param is4ByteAddr 4-byte address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @return None. + */ +void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd) +{ + uint32_t pageOffset, toWr; + uint32_t buf_idx = 0UL; + + pageOffset = u32Addr % 256UL; + + if ((pageOffset + u32NTx) <= 256UL) + { + /* Do all the bytes fit onto one page ? */ + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, u32NTx, pu8TxBuf, wrCmd, 1); + } + else + { + toWr = 256UL - pageOffset; /* Size of data remaining on the first page. */ + + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1); + + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + + while (u32NTx) + { + toWr = 256UL; + if (toWr > u32NTx) + { + toWr = u32NTx; + } + + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1); + + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + } + } +} + +/** + * @brief Read data from SPI Flash by Page Read mode. + * @param u32Addr Start address to read. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NRx Number of bytes to read. + * @param pu8RxBuf Receive buffer. + * @param u32RdCmd Read command. + * @param isSync Block or not. + * @return None. + */ +void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], + uint32_t u32RdCmd, int isSync) +{ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEREAD); /* Switch to Page Read mode. */ + SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */ + + SPIM->SRAMADDR = (uint32_t) pu8RxBuf; /* SRAM u32Address. */ + SPIM->DMACNT = u32NRx; /* Transfer length. */ + SPIM->FADDR = u32Addr; /* Flash u32Address.*/ + SPIM_SET_GO(); /* Go. */ + + if (isSync) + { + SPIM_WAIT_FREE(); /* Wait for DMA done. */ + } +} + +/** + * @brief Enter Direct Map mode. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32RdCmd Read command. + * @param u32IdleIntvl Idle interval. + * @return None. + */ +void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl) +{ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-byte u32Address. */ + SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */ + SPIM_SET_IDL_INTVL(u32IdleIntvl); /* Idle interval. */ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_DIRECTMAP); /* Switch to Direct Map mode. */ +} + +/** + * @brief Exit Direct Map mode. + * @return None. + */ +void SPIM_ExitDirectMapMode(void) +{ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch back to Normal mode. */ +} + + +/*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPIM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/sys.c b/bsp/nuvoton_m487/libraries/StdDriver/src/sys.c new file mode 100644 index 00000000000..f0347d67497 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/sys.c @@ -0,0 +1,255 @@ +/**************************************************************************//** + * @file sys.c + * @version V1.00 + * @brief M480 series SYS driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + + +/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + +/** + * @brief Clear reset source + * @param[in] u32Src is system reset source. Including : + * - \ref SYS_RSTSTS_CPULKRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_PORF_Msk + * @return None + * @details This function clear the selected system reset source. + */ +void SYS_ClearResetSrc(uint32_t u32Src) +{ + SYS->RSTSTS |= u32Src; +} + +/** + * @brief Get Brown-out detector output status + * @param None + * @retval 0 System voltage is higher than BODVL setting or BODEN is 0. + * @retval 1 System voltage is lower than BODVL setting. + * @details This function get Brown-out detector output status. + */ +uint32_t SYS_GetBODStatus(void) +{ + return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos); +} + +/** + * @brief Get reset status register value + * @param None + * @return Reset source + * @details This function get the system reset status register value. + */ +uint32_t SYS_GetResetSrc(void) +{ + return (SYS->RSTSTS); +} + +/** + * @brief Check if register is locked nor not + * @param None + * @retval 0 Write-protection function is disabled. + * 1 Write-protection function is enabled. + * @details This function check register write-protection bit setting. + */ +uint32_t SYS_IsRegLocked(void) +{ + return SYS->REGLCTL & 1UL ? 0UL : 1UL; +} + +/** + * @brief Get product ID + * @param None + * @return Product ID + * @details This function get product ID. + */ +uint32_t SYS_ReadPDID(void) +{ + return SYS->PDID; +} + +/** + * @brief Reset chip with chip reset + * @param None + * @return None + * @details This function reset chip with chip reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetChip(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} + +/** + * @brief Reset chip with CPU reset + * @param None + * @return None + * @details This function reset CPU with CPU reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetCPU(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk; +} + +/** + * @brief Reset selected module + * @param[in] u32ModuleIndex is module index. Including : + * - \ref PDMA_RST + * - \ref EBI_RST + * - \ref EMAC_RST + * - \ref SDH0_RST + * - \ref CRC_RST + * - \ref HSUSBD_RST + * - \ref CRPT_RST + * - \ref SPIM_RST + * - \ref USBH_RST + * - \ref SDH1_RST + * - \ref GPIO_RST + * - \ref TMR0_RST + * - \ref TMR1_RST + * - \ref TMR2_RST + * - \ref TMR3_RST + * - \ref ACMP01_RST + * - \ref I2C0_RST + * - \ref I2C1_RST + * - \ref I2C2_RST + * - \ref QSPI0_RST + * - \ref SPI0_RST + * - \ref SPI1_RST + * - \ref SPI2_RST + * - \ref UART0_RST + * - \ref UART1_RST + * - \ref UART2_RST + * - \ref UART3_RST + * - \ref UART4_RST + * - \ref UART5_RST + * - \ref CAN0_RST + * - \ref CAN1_RST + * - \ref USBD_RST + * - \ref EADC_RST + * - \ref I2S0_RST + * - \ref SC0_RST + * - \ref SC1_RST + * - \ref SC2_RST + * - \ref SPI3_RST + * - \ref USCI0_RST + * - \ref USCI1_RST + * - \ref DAC_RST + * - \ref EPWM0_RST + * - \ref EPWM1_RST + * - \ref BPWM0_RST + * - \ref BPWM1_RST + * - \ref QEI0_RST + * - \ref QEI1_RST + * - \ref ECAP0_RST + * - \ref ECAP1_RST + * - \ref OPA_RST + * @return None + * @details This function reset selected module. + */ +void SYS_ResetModule(uint32_t u32ModuleIndex) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + /* Generate reset signal to the corresponding module */ + u32tmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL)); + u32tmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL)); + *(uint32_t *)u32tmpAddr |= u32tmpVal; + + /* Release corresponding module from reset state */ + u32tmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL)); + *(uint32_t *)u32tmpAddr &= u32tmpVal; +} + +/** + * @brief Enable and configure Brown-out detector function + * @param[in] i32Mode is reset or interrupt mode. Including : + * - \ref SYS_BODCTL_BOD_RST_EN + * - \ref SYS_BODCTL_BOD_INTERRUPT_EN + * @param[in] u32BODLevel is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_3_0V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_1_6V + * @return None + * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel) +{ + /* Enable Brown-out Detector function */ + SYS->BODCTL |= SYS_BODCTL_BODEN_Msk; + + /* Enable Brown-out interrupt or reset function */ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | (uint32_t)i32Mode; + + /* Select Brown-out Detector threshold voltage */ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel; +} + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This function disable Brown-out detector function. + * The register write-protection function should be disabled before using this function. + */ +void SYS_DisableBOD(void) +{ + SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; +} + +/** + * @brief Set Power Level + * @param[in] u32PowerLevel is power level setting. Including : + * - \ref SYS_PLCTL_PLSEL_PL0 + * - \ref SYS_PLCTL_PLSEL_PL1 + * @return None + * @details This function select power level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetPowerLevel(uint32_t u32PowerLevel) +{ + /* Set power voltage level */ + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel); +} + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/timer.c b/bsp/nuvoton_m487/libraries/StdDriver/src/timer.c new file mode 100644 index 00000000000..e5fbd9ef356 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/timer.c @@ -0,0 +1,352 @@ +/**************************************************************************//** + * @file timer.c + * @brief M480 Timer Controller(Timer) driver source file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Open Timer with Operate Mode and Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Mode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * @param[in] u32Freq Target working frequency + * + * @return Real timer working frequency + * + * @details This API is used to configure timer to operate in specified mode and frequency. + * If timer cannot work in target frequency, a closest frequency will be chose and returned. + * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling + * \ref TIMER_Start macro or program registers directly. + */ +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Cmpr = 0UL, u32Prescale = 0UL; + + /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */ + if(u32Freq > (u32Clk / 2UL)) + { + u32Cmpr = 2UL; + } + else + { + u32Cmpr = u32Clk / u32Freq; + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CTL = u32Mode | u32Prescale; + timer->CMP = u32Cmpr; + + return(u32Clk / (u32Cmpr * (u32Prescale + 1UL))); +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API stops timer counting and disable all timer interrupt function. + */ +void TIMER_Close(TIMER_T *timer) +{ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; +} + +/** + * @brief Create a specify Delay Time + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second). + * + * @return None + * + * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode. + * @note This API overwrites the register setting of the timer used to count the delay time. + * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay. + */ +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Prescale = 0UL, delay = (SystemCoreClock / u32Clk) + 1UL; + uint32_t u32Cmpr, u32NsecPerTick; + + /* Clear current timer configuration */ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; + + if(u32Clk <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */ + { + if(u32Usec < 1000UL) + { + u32Usec = 1000UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + else + { + if(u32Usec < 100UL) + { + u32Usec = 100UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + + if(u32Clk <= 1000000UL) + { + u32Prescale = 0UL; + u32NsecPerTick = 1000000000UL / u32Clk; + u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick; + } + else + { + u32Cmpr = u32Usec * (u32Clk / 1000000UL); + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CMP = u32Cmpr; + timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; + + /* When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. + And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. */ + for(; delay > 0UL; delay--) + { + __NOP(); + } + + while(timer->CTL & TIMER_CTL_ACTSTS_Msk) + { + ; + } +} + +/** + * @brief Enable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CapMode Timer capture mode. Could be + * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE + * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE + * @param[in] u32Edge Timer capture trigger edge. Possible values are + * - \ref TIMER_CAPTURE_EVENT_FALLING + * - \ref TIMER_CAPTURE_EVENT_RISING + * - \ref TIMER_CAPTURE_EVENT_FALLING_RISING + * - \ref TIMER_CAPTURE_EVENT_RISING_FALLING + * + * @return None + * + * @details This API is used to enable timer capture function with specify capture trigger edge \n + * to get current counter value or reset counter value to 0. + * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly. + */ +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) | + u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Disable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer capture function. + */ +void TIMER_DisableCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Edge Detection edge of counter pin. Could be ether + * - \ref TIMER_COUNTER_EVENT_FALLING, or + * - \ref TIMER_COUNTER_EVENT_RISING + * + * @return None + * + * @details This function is used to enable the timer counter function with specify detection edge. + * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly. + * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode. + */ +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge; + timer->CTL |= TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Disable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer event counter function. + */ +void TIMER_DisableEventCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Get Timer Clock Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Timer clock frequency + * + * @details This API is used to get the timer clock frequency. + * @note This API cannot return correct clock rate if timer source is from external clock input. + */ +uint32_t TIMER_GetModuleClock(TIMER_T *timer) +{ + uint32_t u32Src, u32Clk; + const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC}; + + if(timer == TIMER0) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; + } + else if(timer == TIMER1) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos; + } + else if(timer == TIMER2) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos; + } + else /* Timer 3 */ + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos; + } + + if(u32Src == 2UL) + { + if((timer == TIMER0) || (timer == TIMER1)) + { + u32Clk = CLK_GetPCLK0Freq(); + } + else + { + u32Clk = CLK_GetPCLK1Freq(); + } + } + else + { + u32Clk = au32Clk[u32Src]; + } + + return u32Clk; +} + + + +/** + * @brief This function is used to enable the Timer frequency counter function + * @param[in] timer The base address of Timer module. Can be \ref TIMER0 or \ref TIMER2 + * @param[in] u32DropCount This parameter has no effect in M480 series BSP + * @param[in] u32Timeout This parameter has no effect in M480 series BSP + * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE + * @return None + * @details This function is used to calculate input event frequency. After enable + * this function, a pair of timers, TIMER0 and TIMER1, or TIMER2 and TIMER3 + * will be configured for this function. The mode used to calculate input + * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical + * Reference Manual + */ +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt) +{ + TIMER_T *t; /* store the timer base to configure compare value */ + + t = (timer == TIMER0) ? TIMER1 : TIMER3; + + t->CMP = 0xFFFFFFUL; + t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL; + timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk; + + return; +} +/** + * @brief This function is used to disable the Timer frequency counter function. + * @param[in] timer The base address of Timer module + * @return None + */ +void TIMER_DisableFreqCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTRGEN_Msk; +} + + +/** + * @brief This function is used to select the interrupt source used to trigger other modules. + * @param[in] timer The base address of Timer module + * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be: + * - \ref TIMER_TRGSRC_TIMEOUT_EVENT + * - \ref TIMER_TRGSRC_CAPTURE_EVENT + * @return None + */ +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src) +{ + timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src; +} + +/** + * @brief This function is used to set modules trigger by timer interrupt + * @param[in] timer The base address of Timer module + * @param[in] u32Mask The mask of modules (EPWM, EADC, DAC and PDMA) trigger by timer. Is the combination of + * - \ref TIMER_TRG_TO_EPWM, + * - \ref TIMER_TRG_TO_EADC, + * - \ref TIMER_TRG_TO_DAC, and + * - \ref TIMER_TRG_TO_PDMA + * @return None + */ +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask) +{ + timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGEPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask; +} + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/timer_pwm.c b/bsp/nuvoton_m487/libraries/StdDriver/src/timer_pwm.c new file mode 100644 index 00000000000..5ae3a7ee5cc --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/timer_pwm.c @@ -0,0 +1,442 @@ +/**************************************************************************//** + * @file timer_pwm.c + * @brief M480 Timer PWM Controller(Timer PWM) driver source file + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions + @{ +*/ + +/** + * @brief Set PWM Counter Clock Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CntClkSrc PWM counter clock source, could be one of following source + * - \ref TPWM_CNTR_CLKSRC_TMR_CLK + * - \ref TPWM_CNTR_CLKSRC_TIMER0_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER1_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER2_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER3_INT + * + * @return None + * + * @details This function is used to set PWM counter clock source. + */ +void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc) +{ + (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc; +} + +/** + * @brief Configure PWM Output Frequency and Duty Cycle + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Frequency Target generator frequency. + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%... + * + * @return Nearest frequency clock in nano second + * + * @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode. + * @note This API is only available if Timer PWM counter clock source is from TMRx_CLK. + */ +uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockFreq, u32TargetFreq; + uint32_t u32Prescaler = 0x1000UL, u32Period, u32CMP; + + if((timer == TIMER0) || (timer == TIMER1)) + { + u32PWMClockFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PWMClockFreq = CLK_GetPCLK1Freq(); + } + + /* Calculate u16PERIOD and u16PSC */ + for(u32Prescaler = 1UL; u32Prescaler <= 0x1000UL; u32Prescaler++) + { + u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency; + + /* If target u32Period is larger than 0x10000, need to use a larger prescaler */ + if(u32Period <= 0x10000UL) + { + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */ + u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period; + + /* Set PWM to up count type */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos); + + /* Set PWM to auto-reload mode */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | TPWM_AUTO_RELOAD_MODE; + + /* Convert to real register value */ + TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL)); + + TPWM_SET_PERIOD(timer, (u32Period - 1UL)); + if(u32DutyCycle) + { + u32CMP = (u32DutyCycle * u32Period) / 100UL; + } + else + { + u32CMP = 0UL; + } + + TPWM_SET_CMPDAT(timer, u32CMP); + + return (u32TargetFreq); +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Disable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable Dead-time of selected channel. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableDeadTime(TIMER_T *timer) +{ + timer->PWMDTCTL = 0x0UL; +} + +/** + * @brief Enable PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable PWM generator and start counter counting. + */ +void TPWM_EnableCounter(TIMER_T *timer) +{ + timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Disable PWM Generator + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit. + */ +void TPWM_DisableCounter(TIMER_T *timer) +{ + timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Enable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Condition The condition to trigger ADC. It could be one of following conditions: + * - \ref TPWM_TRIGGER_ADC_AT_ZERO_POINT + * - \ref TPWM_TRIGGER_ADC_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT + * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT + * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT + * + * @return None + * + * @details This function is used to enable specified counter compare event to trigger ADC. + */ +void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition) +{ + timer->PWMEADCTS = TIMER_PWMEADCTS_TRGEN_Msk | u32Condition; +} + +/** + * @brief Disable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger ADC. + */ +void TPWM_DisableTriggerADC(TIMER_T *timer) +{ + timer->PWMEADCTS = 0x0UL; +} + +/** + * @brief Enable Fault Brake Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CH0Level PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32CH1Level PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32BrakeSource Fault brake source, combination of following source + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM + * + * @return None + * + * @details This function is used to enable fault brake function. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource) +{ + timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL); + timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) | + (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos); +} + +/** + * @brief Enable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to enable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 |= u32IntSource; +} + +/** + * @brief Disable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to disable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 &= ~u32IntSource; +} + +/** + * @brief Indicate Fault Brake Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * + * @details This function is used to indicate fault brake interrupt flag occurred or not of selected source. + */ +uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource))? 1UL : 0UL); +} + +/** + * @brief Clear Fault Brake Interrupt Flags + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to clear fault brake interrupt flags of selected source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTSTS1 = (0x3UL << u32IntSource); +} + +/** + * @brief Enable load mode of selected channel + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32LoadMode Timer PWM counter loading mode, could be one of following mode + * - \ref TPWM_LOAD_MODE_PERIOD + * - \ref TPWM_LOAD_MODE_IMMEDIATE + * - \ref TPWM_LOAD_MODE_CENTER + * + * @return None + * + * @details This function is used to enable load mode of selected channel. + * @note The default loading mode is period loading mode. + */ +void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode) +{ + timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode; +} + +/** + * @brief Enable brake pin noise filter function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinSrc The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @param[in] u32DebounceCnt This value controls the real debounce sample time. + * The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt). + * @param[in] u32ClkSrcSel Brake pin detector debounce clock source, could be one of following source + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_1 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_2 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_4 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_8 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_16 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_32 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_64 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_128 + * + * @return None + * + * @details This function is used to enable external brake pin detector noise filter function. + */ +void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel) +{ + timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) | + (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) | + (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) | + (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk; +} + +/** + * @brief Disable brake pin noise filter function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable external brake pin detector noise filter function. + */ +void TPWM_DisableBrakePinDebounce(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk; +} + + +/** + * @brief Enable brake pin inverse function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to enable PWM brake pin inverse function. + */ +void TPWM_EnableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Disable brake pin inverse function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to disable PWM brake pin inverse function. + */ +void TPWM_DisableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Set brake pin source + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinNum Brake pin selection. One of the following: + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @return None + * @details This function is used to set PWM brake pin source. + */ +void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum) +{ + timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos)); +} + + +/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_PWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/uart.c b/bsp/nuvoton_m487/libraries/StdDriver/src/uart.c new file mode 100644 index 00000000000..c54982fa6f1 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/uart.c @@ -0,0 +1,656 @@ +/**************************************************************************//** + * @file uart.c + * @version V3.00 + * @brief M480 series UART driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + +/** + * @brief Clear UART specified interrupt flag + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTSTS_LININT_Msk : LIN bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt + * + * @return None + * + * @details The function is used to clear UART specified interrupt flag. + */ + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag) +{ + + if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk; + uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */ + { + uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk; + } + else + { + } + + if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */ + { + uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk | + UART_WKSTS_RFRTWKF_Msk |UART_WKSTS_RS485WKF_Msk | + UART_WKSTS_TOUTWKF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */ + { + uart->INTSTS = UART_INTSTS_LINIF_Msk; + uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk | + UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk | + UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ; + } +} + + +/** + * @brief Disable UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART interrupt. + */ +void UART_Close(UART_T* uart) +{ + uart->INTEN = 0ul; +} + + +/** + * @brief Disable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART auto flow control. + */ +void UART_DisableFlowCtrl(UART_T* uart) +{ + uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk); +} + + +/** + * @brief Disable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt * + * + * @return None + * + * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ. + */ +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Disable UART specified interrupt */ + UART_DISABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +void UART_EnableFlowCtrl(UART_T* uart) +{ + /* Set RTS pin output is low level active */ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + + /* Set CTS pin input is low level active */ + uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + + /* Set RTS and CTS auto flow control enable */ + uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk; +} + + +/** + * @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module: + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt * + * + * @return None + * + * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + */ +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Enable UART specified interrupt */ + UART_ENABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Open and set UART function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The baudrate of UART module. + * + * @return None + * + * @details This function use to enable UART function and set baud-rate. + */ +void UART_Open(UART_T* uart, uint32_t u32baudrate) +{ + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div = 0ul; + + + if(uart==(UART_T*)UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart==(UART_T*)UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart==(UART_T*)UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart==(UART_T*)UART3) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart==(UART_T*)UART4) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart==(UART_T*)UART5) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + /* Select UART function */ + uart->FUNCSEL = UART_FUNCSEL_UART; + + /* Set UART line configuration */ + uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1; + + /* Set UART Rx and RTS trigger level */ + uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk); + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32Baud_Div > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } +} + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO. + * @param[in] u32ReadBytes The the read bytes number of data. + * + * @return u32Count Receive byte count + * + * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf. + */ +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */ + } + } + + return u32Count; + +} + + +/** + * @brief Set UART line configuration + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The register value of baudrate of UART module. + * If u32baudrate = 0, UART baudrate will not change. + * @param[in] u32data_width The data length of UART module. + * - \ref UART_WORD_LEN_5 + * - \ref UART_WORD_LEN_6 + * - \ref UART_WORD_LEN_7 + * - \ref UART_WORD_LEN_8 + * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module. + * - \ref UART_PARITY_NONE + * - \ref UART_PARITY_ODD + * - \ref UART_PARITY_EVEN + * - \ref UART_PARITY_MARK + * - \ref UART_PARITY_SPACE + * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module. + * - \ref UART_STOP_BIT_1 + * - \ref UART_STOP_BIT_1_5 + * - \ref UART_STOP_BIT_2 + * + * @return None + * + * @details This function use to config UART line setting. + */ +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div = 0ul; + + + if(uart==(UART_T*)UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart==(UART_T*)UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart==(UART_T*)UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart==(UART_T*)UART3) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart==(UART_T*)UART4) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart==(UART_T*)UART5) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + else + { + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32Baud_Div > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } + + /* Set UART line configuration */ + uart->LINE = u32data_width | u32parity | u32stop_bits; +} + + +/** + * @brief Set Rx timeout count + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32TOC Rx timeout counter. + * + * @return None + * + * @details This function use to set Rx timeout count. + */ +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC) +{ + /* Set time-out interrupt comparator */ + uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC); + + /* Set time-out counter enable */ + uart->INTEN |= UART_INTEN_TOCNTEN_Msk; +} + + +/** + * @brief Select and configure IrDA function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Buadrate The baudrate of UART module. + * @param[in] u32Direction The direction of UART module in IrDA mode: + * - \ref UART_IRDA_TXEN + * - \ref UART_IRDA_RXEN + * + * @return None + * + * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate. + */ +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction) +{ + uint32_t u32UartClkSrcSel=0ul, u32UartClkDivNum=0ul; + uint32_t u32ClkTbl[4ul] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32Baud_Div; + + /* Select IrDA function mode */ + uart->FUNCSEL = UART_FUNCSEL_IrDA; + + + if(uart==UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if(uart==UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if(uart==UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else if(uart==UART3) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + } + else if(uart==UART4) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + } + else if(uart==UART5) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + } + + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + u32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + else + { + } + + /* Set UART IrDA baud rate in mode 0 */ + if(u32Buadrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate); + + if(u32Baud_Div < 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div); + } + else + { + } + } + + /* Configure IrDA relative settings */ + if(u32Direction == UART_IRDA_RXEN) + { + uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/ + uart->IRDA &= ~UART_IRDA_TXEN_Msk; + } + else + { + uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/ + uart->IRDA |= UART_IRDA_TXEN_Msk; + } + +} + + +/** + * @brief Select and configure RS485 function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The operation mode(NMM/AUD/AAD). + * - \ref UART_ALTCTL_RS485NMM_Msk + * - \ref UART_ALTCTL_RS485AUD_Msk + * - \ref UART_ALTCTL_RS485AAD_Msk + * @param[in] u32Addr The RS485 address. + * + * @return None + * + * @details The function is used to set RS485 relative setting. + */ +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr) +{ + /* Select UART RS485 function mode */ + uart->FUNCSEL = UART_FUNCSEL_RS485; + + /* Set RS585 configuration */ + uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk); + uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos)); +} + + +/** + * @brief Select and configure LIN function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The LIN direction : + * - \ref UART_ALTCTL_LINTXEN_Msk + * - \ref UART_ALTCTL_LINRXEN_Msk + * @param[in] u32BreakLength The break field length. + * + * @return None + * + * @details The function is used to set LIN relative setting. + */ +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength) +{ + /* Select LIN function mode */ + uart->FUNCSEL = UART_FUNCSEL_LIN; + + /* Select LIN function setting : Tx enable, Rx enable and break field length */ + uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk); + uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos)); +} + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO. + * @param[out] u32WriteBytes The byte number of data. + * + * @return u32Count transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by UART. + */ +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0ul) /* Wait Tx empty and Time-out manner */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */ + } + } + + return u32Count; + +} + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + + + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/usbd.c b/bsp/nuvoton_m487/libraries/StdDriver/src/usbd.c new file mode 100644 index 00000000000..15f9b7392fa --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/usbd.c @@ -0,0 +1,729 @@ +/**************************************************************************//** + * @file usbd.c + * @version V1.00 + * @brief M480 USBD driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ + +/* Global variables for Control Pipe */ +uint8_t g_usbd_SetupPacket[8] = {0ul}; /*!< Setup packet buffer */ +volatile uint8_t g_usbd_RemoteWakeupEn = 0ul; /*!< Remote wake up function enable flag */ + +/** + * @cond HIDDEN_SYMBOLS + */ +static uint8_t *g_usbd_CtrlInPointer = 0; +static uint8_t *g_usbd_CtrlOutPointer = 0; +static volatile uint32_t g_usbd_CtrlInSize = 0ul; +static volatile uint32_t g_usbd_CtrlOutSize = 0ul; +static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0ul; +static volatile uint32_t g_usbd_UsbAddr = 0ul; +static volatile uint32_t g_usbd_UsbConfig = 0ul; +static volatile uint32_t g_usbd_CtrlMaxPktSize = 8ul; +static volatile uint32_t g_usbd_UsbAltInterface = 0ul; +static volatile uint8_t g_usbd_CtrlInZeroFlag = 0ul; +/** + * @endcond + */ + +const S_USBD_INFO_T *g_usbd_sInfo; /*!< A pointer for USB information structure */ + +VENDOR_REQ g_usbd_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */ +CLASS_REQ g_usbd_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */ +SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */ +SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */ +uint32_t g_u32EpStallLock = 0ul; /*!< Bit map flag to lock specified EP when SET_FEATURE */ + +/** + * @brief This function makes USBD module to be ready to use + * + * @param[in] param The structure of USBD information. + * @param[in] pfnClassReq USB Class request callback function. + * @param[in] pfnSetInterface USB Set Interface request callback function. + * + * @return None + * + * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus. + */ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface) +{ + g_usbd_sInfo = param; + g_usbd_pfnClassRequest = pfnClassReq; + g_usbd_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ + USBD->ATTR = 0x6D0ul; + /* Force SE0 */ + USBD_SET_SE0(); +} + +/** + * @brief This function makes USB host to recognize the device + * + * @param None + * + * @return None + * + * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer. + */ +void USBD_Start(void) +{ + /* Disable software-disconnect function */ + USBD_CLR_SE0(); + USBD->ATTR = 0x7D0ul; + + /* Clear USB-related interrupts before enable interrupt */ + USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + + /* Enable USB-related interrupts. */ + USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); +} + +/** + * @brief Get the received SETUP packet + * + * @param[in] buf A buffer pointer used to store 8-byte SETUP packet. + * + * @return None + * + * @details Store SETUP packet to a user-specified buffer. + * + */ +void USBD_GetSetupPacket(uint8_t *buf) +{ + USBD_MemCopy(buf, g_usbd_SetupPacket, 8ul); +} + +/** + * @brief Process SETUP packet + * + * @param None + * + * @return None + * + * @details Parse SETUP packet and perform the corresponding action. + * + */ +void USBD_ProcessSetupPacket(void) +{ + /* Get SETUP packet from USB buffer */ + USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8ul); + + /* Check the request type */ + switch(g_usbd_SetupPacket[0] & 0x60ul) + { + case REQ_STANDARD: + { + USBD_StandardRequest(); + break; + } + case REQ_CLASS: + { + if(g_usbd_pfnClassRequest != NULL) + { + g_usbd_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: + { + if(g_usbd_pfnVendorRequest != NULL) + { + g_usbd_pfnVendorRequest(); + } + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } +} + +/** + * @brief Process GetDescriptor request + * + * @param None + * + * @return None + * + * @details Parse GetDescriptor request and perform the corresponding action. + * + */ +void USBD_GetDescriptor(void) +{ + uint32_t u32Len; + + g_usbd_CtrlInZeroFlag = (uint8_t)0ul; + u32Len = 0ul; + u32Len = g_usbd_SetupPacket[7]; + u32Len <<= 8ul; + u32Len += g_usbd_SetupPacket[6]; + + switch(g_usbd_SetupPacket[3]) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE); + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len); + + break; + } + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + if (u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len); + + break; + } + + /* Get BOS Descriptor */ + case DESC_BOS: + { + u32Len = USBD_Minimum(u32Len, LEN_BOS+LEN_BOSCAP); + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8BosDesc, u32Len); + break; + } + /* Get HID Descriptor */ + case DESC_HID: + { + /* CV3.0 HID Class Descriptor Test, + Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */ + uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */ + u32Len = USBD_Minimum(u32Len, LEN_HID); + u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]]; + USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len); + + break; + } + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + if (u32Len > g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]) + { + u32Len = g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len); + break; + } + /* Get String Descriptor */ + case DESC_STRING: + { + /* Get String Descriptor */ + if(g_usbd_SetupPacket[2] < 4ul) + { + if (u32Len > g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]) + { + u32Len = g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]; + if ((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len); + + + break; + } + else + { + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + default: + /* Not support. Reply STALL.*/ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } +} + +/** + * @brief Process standard request + * + * @param None + * + * @return None + * + * @details Parse standard request and perform the corresponding action. + * + */ +void USBD_StandardRequest(void) +{ + uint32_t addr; + /* clear global variables for new request */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + + if((g_usbd_SetupPacket[0] & 0x80ul) == 0x80ul) /* request data transfer direction */ + { + /* Device to host */ + switch(g_usbd_SetupPacket[1]) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + /* Data stage */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)g_usbd_UsbConfig; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + case GET_DESCRIPTOR: + { + USBD_GetDescriptor(); + USBD_PrepareCtrlOut(0, 0ul); /* For status stage */ + break; + } + case GET_INTERFACE: + { + /* Return current interface setting */ + /* Data stage */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)g_usbd_UsbAltInterface; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + case GET_STATUS: + { + /* Device */ + if(g_usbd_SetupPacket[0] == 0x80ul) + { + uint8_t u8Tmp; + + u8Tmp = (uint8_t)0ul; + if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) + { + u8Tmp |= (uint8_t)1ul; /* Self-Powered/Bus-Powered.*/ + } + if ((g_usbd_sInfo->gu8ConfigDesc[7] & 0x20ul) == 0x20ul) + { + u8Tmp |= (uint8_t)(g_usbd_RemoteWakeupEn << 1ul); /* Remote wake up */ + } + + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = u8Tmp; + + } + /* Interface */ + else if(g_usbd_SetupPacket[0] == 0x81ul) + { + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)0ul; + } + /* Endpoint */ + else if(g_usbd_SetupPacket[0] == 0x82ul) + { + uint8_t ep = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)(USBD_GetStall(ep) ? 1ul : 0ul); + } + + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1ul; + M8(addr) = (uint8_t)0ul; + /* Data stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 2ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } + else + { + /* Host to device */ + switch(g_usbd_SetupPacket[1]) + { + case CLEAR_FEATURE: + { + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_u32EpStallLock is added to support it */ + epNum = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul); + for(i = 0ul; i < USBD_MAX_EP; i++) + { + if(((USBD->EP[i].CFG & 0xFul) == epNum) && ((g_u32EpStallLock & (1ul << i)) == 0ul)) + { + USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk; + USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + } + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_usbd_RemoteWakeupEn = (uint8_t)0; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + case SET_ADDRESS: + { + g_usbd_UsbAddr = g_usbd_SetupPacket[2]; + /* Status Stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + break; + } + case SET_CONFIGURATION: + { + g_usbd_UsbConfig = g_usbd_SetupPacket[2]; + + if(g_usbd_pfnSetConfigCallback) + { + g_usbd_pfnSetConfigCallback(); + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + case SET_FEATURE: + { + if( (g_usbd_SetupPacket[0] & 0xFul) == 0ul ) /* 0: device */ + { + if((g_usbd_SetupPacket[2] == 3ul) && (g_usbd_SetupPacket[3] == 0ul)) /* 3: HNP enable */ + { + OTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk); + } + } + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + USBD_SetStall((uint8_t)(g_usbd_SetupPacket[4] & 0xFul)); + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_usbd_RemoteWakeupEn = (uint8_t)1ul; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + break; + } + case SET_INTERFACE: + { + g_usbd_UsbAltInterface = g_usbd_SetupPacket[2]; + if(g_usbd_pfnSetInterface != NULL) + { + g_usbd_pfnSetInterface(g_usbd_UsbAltInterface); + } + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } +} + +/** + * @brief Prepare the first Control IN pipe + * + * @param[in] pu8Buf The pointer of data sent to USB host. + * @param[in] u32Size The IN transfer size. + * + * @return None + * + * @details Prepare data for Control IN transfer. + * + */ +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + uint32_t addr; + if(u32Size > g_usbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize; + USBD_SET_DATA1(EP0); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, pu8Buf, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + } + else + { + /* Data size <= MXPLD */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + USBD_SET_DATA1(EP0); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, pu8Buf, u32Size); + USBD_SET_PAYLOAD_LEN(EP0, u32Size); + } +} + +/** + * @brief Repeat Control IN pipe + * + * @param None + * + * @return None + * + * @details This function processes the remained data of Control IN transfer. + * + */ +void USBD_CtrlIn(void) +{ + uint32_t addr; + + if(g_usbd_CtrlInSize) + { + /* Process remained data */ + if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize; + } + else + { + /* Data size <= MXPLD */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize); + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + } + } + else + { + /* In ACK for Set address */ + if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS)) + { + addr = USBD_GET_ADDR(); + if((addr != g_usbd_UsbAddr) && (addr == 0ul)) + { + USBD_SET_ADDR(g_usbd_UsbAddr); + } + } + + /* For the case of data size is integral times maximum packet size */ + if(g_usbd_CtrlInZeroFlag) + { + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + g_usbd_CtrlInZeroFlag = (uint8_t)0ul; + } + } +} + +/** + * @brief Prepare the first Control OUT pipe + * + * @param[in] pu8Buf The pointer of data received from USB host. + * @param[in] u32Size The OUT transfer size. + * + * @return None + * + * @details This function is used to prepare the first Control OUT transfer. + * + */ +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size) +{ + g_usbd_CtrlOutPointer = pu8Buf; + g_usbd_CtrlOutSize = 0ul; + g_usbd_CtrlOutSizeLimit = u32Size; + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); +} + +/** + * @brief Repeat Control OUT pipe + * + * @param None + * + * @return None + * + * @details This function processes the successive Control OUT transfer. + * + */ +void USBD_CtrlOut(void) +{ + uint32_t u32Size; + uint32_t addr; + + if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + { + u32Size = USBD_GET_PAYLOAD_LEN(EP1); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1); + USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)addr, u32Size); + g_usbd_CtrlOutPointer += u32Size; + g_usbd_CtrlOutSize += u32Size; + + if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + { + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); + } + + } +} + +/** + * @brief Reset software flags + * + * @param None + * + * @return None + * + * @details This function resets all variables for protocol and resets USB device address to 0. + * + */ +void USBD_SwReset(void) +{ + uint32_t i; + + /* Reset all variables for protocol */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + g_usbd_CtrlOutPointer = 0; + g_usbd_CtrlOutSize = 0ul; + g_usbd_CtrlOutSizeLimit = 0ul; + g_u32EpStallLock = 0ul; + memset(g_usbd_SetupPacket, 0, 8ul); + + /* Reset PID DATA0 */ + for(i=0ul; iEP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + + /* Reset USB device address */ + USBD_SET_ADDR(0ul); +} + +/** + * @brief USBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set USBD vendor request callback function + */ +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq) +{ + g_usbd_pfnVendorRequest = pfnVendorReq; +} + +/** + * @brief The callback function which called when get SET CONFIGURATION request + * + * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request + * + * @return None + * + * @details This function is used to set the callback function which will be called at SET CONFIGURATION request. + */ +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback) +{ + g_usbd_pfnSetConfigCallback = pfnSetConfigCallback; +} + + +/** + * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request. + * + * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked + * + * @return None + * + * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request. + * If ep stall locked, user needs to reset USB device or re-configure device to clear it. + */ +void USBD_LockEpStall(uint32_t u32EpBitmap) +{ + g_u32EpStallLock = u32EpBitmap; +} + + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/usci_i2c.c b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_i2c.c new file mode 100644 index 00000000000..dfa5dcdafe2 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_i2c.c @@ -0,0 +1,1678 @@ +/****************************************************************************//** + * @file usci_i2c.c + * @version V3.00 + * @brief M480 series USCI I2C(UI2C) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This function makes USCI_I2C module be ready and set the wanted bus clock + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format). + */ +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if( ui2c == UI2C0 ) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */ + + /* Enable USCI_I2C protocol */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; + ui2c->CTL = 4U << UI2C_CTL_FUNMODE_Pos; + + /* Data format configuration */ + /* 8 bit data length */ + ui2c->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk; + ui2c->LINECTL |= 8U << UI2C_LINECTL_DWIDTH_Pos; + + /* MSB data format */ + ui2c->LINECTL &= ~UI2C_LINECTL_LSB_Msk; + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + ui2c->PROTCTL |= UI2C_PROTCTL_PROTEN_Msk; + + return ( u32Pclk / ((u32ClkDiv+1U)<<1U) ); +} + +/** + * @brief This function closes the USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Close USCI_I2C protocol function. + */ +void UI2C_Close(UI2C_T *ui2c) +{ + /* Disable USCI_I2C function */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; +} + +/** + * @brief This function clears the time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Clear time-out flag when time-out flag is set. + */ +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c) +{ + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; +} + +/** + * @brief This function sets the control bit of the USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Start Set START bit to USCI_I2C module. + * @param[in] u8Stop Set STOP bit to USCI_I2C module. + * @param[in] u8Ptrg Set PTRG bit to USCI_I2C module. + * @param[in] u8Ack Set ACK bit to USCI_I2C module. + * + * @return None + * + * @details The function set USCI_I2C control bit of USCI_I2C bus protocol. + */ +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + uint32_t u32Val = ui2c->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk); + + if (u8Start) + { + u32Reg |= UI2C_PROTCTL_STA_Msk; + } + if (u8Stop) + { + u32Reg |= UI2C_PROTCTL_STO_Msk; + } + if (u8Ptrg) + { + u32Reg |= UI2C_PROTCTL_PTRG_Msk; + } + if (u8Ack) + { + u32Reg |= UI2C_PROTCTL_AA_Msk; + } + + ui2c->PROTCTL = u32Val | u32Reg; +} + +/** + * @brief This function disables the interrupt of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to an interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details The function is used to disable USCI_I2C bus interrupt events. + */ +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Disable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk; + } + + /* Disable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk; + } + + /* Disable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk; + } + + /* Disable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk; + } + + /* Disable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Disable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk; + } + + /* Disable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function enables the interrupt of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * @return None + * + * @details The function is used to enable USCI_I2C bus interrupt events. + */ +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Enable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk; + } + + /* Enable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk; + } + + /* Enable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk; + } + + /* Enable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk; + } + + /* Enable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Enable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk; + } + + /* Enable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function returns the real bus clock of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details The function returns the actual USCI_I2C module bus clock. + */ +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c) +{ + uint32_t u32Divider; + uint32_t u32Pclk; + + if (ui2c == UI2C0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32Divider = (ui2c->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos; + + return ( u32Pclk / ((u32Divider+1U)<<1U) ); +} + +/** + * @brief This function sets bus clock frequency of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Use this function set USCI_I2C bus clock frequency and return actual bus clock. + */ +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if( ui2c == UI2C0 ) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */ + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + + return ( u32Pclk / ((u32ClkDiv+1U)<<1U) ); +} + +/** + * @brief This function gets the interrupt flag of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details Use this function to get USCI_I2C interrupt flag when module occurs interrupt event. + */ +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U; + uint32_t u32TmpValue; + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_TOIF_Msk; + /* Check Time-out Interrupt Flag */ + if((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_TO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STARIF_Msk; + /* Check Start Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STAR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STORIF_Msk; + /* Check Stop Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STOR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_NACKIF_Msk; + /* Check Non-Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_NACK_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk; + /* Check Arbitration Lost Interrupt Flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ARBLO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ERRIF_Msk; + /* Check Error Interrupt Flag */ + if((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ERR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ACKIF_Msk; + /* Check Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ACK_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief This function clears the interrupt flag of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag. + */ +void UI2C_ClearIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Clear Time-out Interrupt Flag */ + if(u32Mask & UI2C_TO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; + } + + /* Clear Start Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STAR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STARIF_Msk; + } + + /* Clear Stop Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STOR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STORIF_Msk; + } + + /* Clear Non-Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_NACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_NACKIF_Msk; + } + + /* Clear Arbitration Lost Interrupt Flag */ + if(u32Mask & UI2C_ARBLO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk; + } + + /* Clear Error Interrupt Flag */ + if(u32Mask & UI2C_ERR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ERRIF_Msk; + } + + /* Clear Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_ACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ACKIF_Msk; + } +} + +/** + * @brief This function returns the data stored in data register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return USCI_I2C data. + * + * @details To read a byte data from USCI_I2C module receive data register. + */ +uint32_t UI2C_GetData(UI2C_T *ui2c) +{ + return ( ui2c->RXDAT ); +} + +/** + * @brief This function writes a byte data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details To write a byte data to transmit data register to transmit data. + */ +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data) +{ + ui2c->TXDAT = u8Data; +} + +/** + * @brief Configure slave address and enable GC mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddr The slave address. + * @param[in] u8GCMode GC mode enable or not. Valid values are: + * - \ref UI2C_GCMODE_ENABLE + * - \ref UI2C_GCMODE_DISABLE + * + * @return None + * + * @details To configure USCI_I2C module slave address and GC mode. + */ +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode) +{ + if(u8SlaveNo) + { + ui2c->DEVADDR1 = u16SlaveAddr; + } + else + { + ui2c->DEVADDR0 = u16SlaveAddr; + } + + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) |u8GCMode; +} + +/** + * @brief Configure the mask bit of slave address. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddrMask The slave address mask. + * + * @return None + * + * @details To configure USCI_I2C module slave address mask bit. + * @note The corresponding address bit is "Don't Care". + */ +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask) +{ + if(u8SlaveNo) + { + ui2c->ADDRMSK1 = u16SlaveAddrMask; + } + else + { + ui2c->ADDRMSK0 = u16SlaveAddrMask; + } +} + +/** + * @brief This function enables time-out function and configures timeout counter + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32TimeoutCnt Timeout counter. Valid values are between 0~0x3FF + * + * @return None + * + * @details To enable USCI_I2C bus time-out function and set time-out counter. + */ +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt) +{ + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos); + ui2c->BRGEN = (ui2c->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function disables time-out function + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C bus time-out function. + */ +void UI2C_DisableTimeout(UI2C_T *ui2c) +{ + ui2c->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk; + ui2c->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function enables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8WakeupMode The wake-up mode selection. Valid values are: + * - \ref UI2C_DATA_TOGGLE_WK + * - \ref UI2C_ADDR_MATCH_WK + * + * @return None + * + * @details To enable USCI_I2C module wake-up function. + */ +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode) +{ + ui2c->WKCTL = (ui2c->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk); +} + +/** + * @brief This function disables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C module wake-up function. + */ +void UI2C_DisableWakeup(UI2C_T *ui2c) +{ + ui2c->WKCTL &= ~UI2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master write a byte data to Slave. + * + */ + +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master write multi bytes data to Slave. + * + */ + +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + if (u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 2U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u8Addr = 0; + } + else + { + if (u32txLen < u32wLen) + { + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master to read a byte data from Slave. + * + */ +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + eEvent = MASTER_READ_DATA; + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Err = 1U; + } + else + { + rdata = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; + + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < (u32rLen - 1U)) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + /* SLA+R ACK */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address(2 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Addr = 1U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/usci_spi.c b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_spi.c new file mode 100644 index 00000000000..760a540200c --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_spi.c @@ -0,0 +1,663 @@ +/****************************************************************************//** + * @file usci_spi.c + * @version V3.00 + * @brief M480 series USCI_SPI driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief This function make USCI_SPI module be ready to transfer. + * By default, the USCI_SPI transfer sequence is MSB first, the slave selection + * signal is active low and the automatic slave select function is disabled. In + * Slave mode, the u32BusClock must be NULL and the USCI_SPI clock + * divider setting will be 0. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are: + * - \ref USPI_SLAVE + * - \ref USPI_MASTER + * @param[in] u32SPIMode Decide the transfer timing. Valid values are: + * - \ref USPI_MODE_0 + * - \ref USPI_MODE_1 + * - \ref USPI_MODE_2 + * - \ref USPI_MODE_3 + * @param[in] u32DataWidth The data width of a USCI_SPI transaction. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv = 0ul; + uint32_t u32Pclk; + uint32_t u32UspiClk = 0ul; + + if(uspi == (USPI_T *)USPI0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + if(u32BusClock != 0ul) + { + u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */ + } + else {} + + /* Enable USCI_SPI protocol */ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; + uspi->CTL = 1ul << USPI_CTL_FUNMODE_Pos; + + /* Data format configuration */ + if(u32DataWidth == 16ul) + { + u32DataWidth = 0ul; + } + else {} + uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk; + uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos); + + /* MSB data format */ + uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk; + + /* Set slave selection signal active low */ + if(u32MasterSlave == USPI_MASTER) + { + uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk; + } + else + { + uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk; + } + + /* Set operating mode and transfer timing */ + uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk); + uspi->PROTCTL |= (u32MasterSlave | u32SPIMode); + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk; + + if(u32BusClock != 0ul) + { + u32UspiClk = (uint32_t)( u32Pclk / ((u32ClkDiv+1ul)<<1) ); + } + else {} + + return u32UspiClk; +} + +/** + * @brief Disable USCI_SPI function mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_Close(USPI_T *uspi) +{ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; +} + +/** + * @brief Clear Rx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearRxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk; +} + +/** + * @brief Clear Tx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearTxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk; +} + +/** + * @brief Disable the automatic slave select function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableAutoSS(USPI_T *uspi) +{ + uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave select function. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SSPinMask This parameter is not used. + * @param[in] u32ActiveLevel The active level of slave select signal. Valid values are: + * - \ref USPI_SS_ACTIVE_HIGH + * - \ref USPI_SS_ACTIVE_LOW + * @return None + */ +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel; + uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk; +} + +/** + * @brief Set the USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if(uspi == USPI0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */ + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + + return ( u32Pclk / ((u32ClkDiv+1ul)<<1) ); +} + +/** + * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Actual USCI_SPI bus clock frequency. + */ +uint32_t USPI_GetBusClock(USPI_T *uspi) +{ + uint32_t u32BusClk; + uint32_t u32ClkDiv; + + u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos; + + if(uspi == USPI0) + { + u32BusClk = (uint32_t)( CLK_GetPCLK0Freq() / ((u32ClkDiv+1ul)<<1) ); + } + else + { + u32BusClk = (uint32_t)( CLK_GetPCLK1Freq() / ((u32ClkDiv+1ul)<<1) ); + } + + return u32BusClk; +} + +/** + * @brief Enable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be enabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk; + } + else {} + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk; + } + else {} + /* Enable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk; + } + else {} + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk; + } + else {} + /* Enable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk; + } + else {} + /* Enable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk; + } + else {} + /* Enable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk; + } + else {} + /* Enable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk; + } + else {} + /* Enable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk; + } + else {} + /* Enable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk; + } + else {} +} + +/** + * @brief Disable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk; + } + else {} + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk; + } + else {} + /* Disable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk; + } + else {} + /* Disable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk; + } + else {} + /* Disable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk; + } + else {} + /* Disable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk; + } + else {} + /* Disable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk; + } + else {} + /* Disable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk; + } + else {} + /* Disable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk; + } + else {} + /* Disable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk; + } + else {} +} + +/** + * @brief Get interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return Interrupt flags of selected sources. + */ +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32TmpFlag; + uint32_t u32IntFlag = 0ul; + + /* Check slave selection signal inactive interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSINAIF_Msk; + if(((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK) && (u32TmpFlag==USPI_PROTSTS_SSINAIF_Msk) ) + { + u32IntFlag |= USPI_SSINACT_INT_MASK; + } + else {} + /* Check slave selection signal active interrupt flag */ + + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSACTIF_Msk; + if(((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk)) + { + u32IntFlag |= USPI_SSACT_INT_MASK; + } + else {} + + /* Check slave time-out interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVTOIF_Msk; + if(((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVTOIF_Msk)) + { + u32IntFlag |= USPI_SLVTO_INT_MASK; + } + else {} + + /* Check slave bit count error interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVBEIF_Msk; + if(((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVBEIF_Msk)) + { + u32IntFlag |= USPI_SLVBE_INT_MASK; + } + else {} + + /* Check TX under run interrupt flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk; + if(((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_TXUDRIF_Msk)) + { + u32IntFlag |= USPI_TXUDR_INT_MASK; + } + else {} + + /* Check RX overrun interrupt flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXOVIF_Msk; + if(((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_RXOVIF_Msk)) + { + u32IntFlag |= USPI_RXOV_INT_MASK; + } + else {} + + /* Check TX start interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXSTIF_Msk; + if(((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXSTIF_Msk)) + { + u32IntFlag |= USPI_TXST_INT_MASK; + } + else {} + + /* Check TX end interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXENDIF_Msk; + if(((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXENDIF_Msk)) + { + u32IntFlag |= USPI_TXEND_INT_MASK; + } + else {} + + /* Check RX start interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXSTIF_Msk; + if(((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXSTIF_Msk)) + { + u32IntFlag |= USPI_RXST_INT_MASK; + } + else {} + + /* Check RX end interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXENDIF_Msk; + if(((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXENDIF_Msk)) + { + u32IntFlag |= USPI_RXEND_INT_MASK; + } + else {} + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + /* Clear slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk; + } + else {} + /* Clear slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk; + } + else {} + /* Clear slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk; + } + else {} + /* Clear slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk; + } + else {} + /* Clear TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk; + } + else {} + /* Clear RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk; + } + else {} + /* Clear TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk; + } + else {} + /* Clear TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk; + } + else {} + /* Clear RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk; + } + else {} + + /* Clear RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk; + } + else {} +} + +/** + * @brief Get USCI_SPI status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref USPI_BUSY_MASK + * - \ref USPI_RX_EMPTY_MASK + * - \ref USPI_RX_FULL_MASK + * - \ref USPI_TX_EMPTY_MASK + * - \ref USPI_TX_FULL_MASK + * - \ref USPI_SSLINE_STS_MASK + * @return Flags of selected sources. + */ +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0ul; + uint32_t u32TmpFlag; + + /* Check busy status */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_BUSY_Msk; + if(((u32Mask & USPI_BUSY_MASK)==USPI_BUSY_MASK) && (u32TmpFlag & USPI_PROTSTS_BUSY_Msk)) + { + u32Flag |= USPI_BUSY_MASK; + } + else {} + + /* Check RX empty flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk; + if(((u32Mask & USPI_RX_EMPTY_MASK)==USPI_RX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_RXEMPTY_Msk)) + { + u32Flag |= USPI_RX_EMPTY_MASK; + } + else {} + + /* Check RX full flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXFULL_Msk; + if(((u32Mask & USPI_RX_FULL_MASK)==USPI_RX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_RXFULL_Msk)) + { + u32Flag |= USPI_RX_FULL_MASK; + } + else {} + + /* Check TX empty flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk; + if(((u32Mask & USPI_TX_EMPTY_MASK)==USPI_TX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_TXEMPTY_Msk)) + { + u32Flag |= USPI_TX_EMPTY_MASK; + } + else {} + + /* Check TX full flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXFULL_Msk; + if(((u32Mask & USPI_TX_FULL_MASK)==USPI_TX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_TXFULL_Msk)) + { + u32Flag |= USPI_TX_FULL_MASK; + } + else {} + + /* Check USCI_SPI_SS line status */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSLINE_Msk; + if(((u32Mask & USPI_SSLINE_STS_MASK)==USPI_SSLINE_STS_MASK) && (u32TmpFlag & USPI_PROTSTS_SSLINE_Msk)) + { + u32Flag |= USPI_SSLINE_STS_MASK; + } + else {} + return u32Flag; +} + +/** + * @brief Enable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_EnableWakeup(USPI_T *uspi) +{ + uspi->WKCTL |= USPI_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableWakeup(USPI_T *uspi) +{ + uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk; +} + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/usci_uart.c b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_uart.c new file mode 100644 index 00000000000..3aad6697c4b --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/usci_uart.c @@ -0,0 +1,701 @@ +/**************************************************************************//** + * @file usci_uart.c + * @version V3.00 + * @brief M480 series USCI UART (UUART) driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + +/** + * @brief Clear USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + + if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk; + } + + if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */ + { + uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk); + } + + if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */ + { + uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk; + } + + if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk; + } + + if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk; + } + + if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk; + } + + if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk; + } + +} + +/** + * @brief Get USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0ul; + uint32_t u32Tmp1, u32Tmp2; + + /* Check Auto-baud Rate Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_ABR_INT_MASK; + } + + /* Check Receive Line Status Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk)); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RLS_INT_MASK; + } + + /* Check Receive Buffer Over-run Error Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK); + u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_BUF_RXOV_INT_MASK; + } + + /* Check Transmit Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXST_INT_MASK; + } + + /* Check Transmit End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXEND_INT_MASK; + } + + /* Check Receive Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXST_INT_MASK; + } + + /* Check Receive End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXEND_INT_MASK; + } + + return u32IntFlag; + +} + + +/** + * @brief Disable USCI_UART function mode + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART function mode. + */ +void UUART_Close(UUART_T* uuart) +{ + uuart->CTL = 0ul; +} + + +/** + * @brief Disable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask) +{ + + /* Disable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk; + } + + /* Disable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Disable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk; + } + + /* Disable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk; + } + + /* Disable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk; + } + + /* Disable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Enable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to enable USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask) +{ + /* Enable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk; + } + + /* Enable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Enable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk; + } + + /* Enable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk; + } + + /* Enable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk; + } + + /* Enable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Open and set USCI_UART function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The baud rate of USCI_UART module. + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to enable USCI_UART function and set baud-rate. + */ +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + if( uuart == UUART0) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + u32Tmp = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + /* Enable USCI_UART protocol */ + uuart->CTL &= ~UUART_CTL_FUNMODE_Msk; + uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos; + + /* Set USCI_UART line configuration */ + uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk; + uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos); /* Set falling edge detection */ + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos); + + uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk; + + return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv); +} + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive buffer. + * @param[in] u32ReadBytes The read bytes number of data. + * + * @return Receive byte count + * + * @details The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf. + */ +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT; /* Get Data from USCI RX */ + } + + return u32Count; + +} + + +/** + * @brief Set USCI_UART line configuration + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The register value of baud rate of USCI_UART module. + * If u32baudrate = 0, USCI_UART baud rate will not change. + * @param[in] u32data_width The data length of USCI_UART module. + * - \ref UUART_WORD_LEN_6 + * - \ref UUART_WORD_LEN_7 + * - \ref UUART_WORD_LEN_8 + * - \ref UUART_WORD_LEN_9 + * @param[in] u32parity The parity setting (none/odd/even) of USCI_UART module. + * - \ref UUART_PARITY_NONE + * - \ref UUART_PARITY_ODD + * - \ref UUART_PARITY_EVEN + * @param[in] u32stop_bits The stop bit length (1/2 bit) of USCI_UART module. + * - \ref UUART_STOP_BIT_1 + * - \ref UUART_STOP_BIT_2 + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to config USCI_UART line setting. + */ +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + if(uuart == UUART0) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else /* UUART1 */ + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + if(u32baudrate != 0ul) + { + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos); + } + else + { + u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul; + u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul; + u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul; + } + + /* Set USCI_UART line configuration */ + uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width; + uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk | + UUART_PROTCTL_PARITYEN_Msk)) | u32parity; + uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk ) | u32stop_bits; + + return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv); +} + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8TxBuf The buffer to send the data to USCI transmission buffer. + * @param[out] u32WriteBytes The byte number of data. + * + * @return Transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by USCI_UART. + */ +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) /* Wait Tx empty */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */ + } + + return u32Count; + +} + + +/** + * @brief Enable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32WakeupMode The wakeup mode of USCI_UART module. + * - \ref UUART_PROTCTL_DATWKEN_Msk : Data wake-up Mode + * - \ref UUART_PROTCTL_CTSWKEN_Msk : nCTS wake-up Mode + * + * @return None + * + * @details The function is used to enable Wake-up function of USCI_UART. + */ +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode) +{ + uuart->PROTCTL |= u32WakeupMode; + uuart->WKCTL |= UUART_WKCTL_WKEN_Msk; +} + + +/** + * @brief Disable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable Wake-up function of USCI_UART. + */ +void UUART_DisableWakeup(UUART_T* uuart) +{ + uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk|UUART_PROTCTL_CTSWKEN_Msk); + uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk; +} + +/** + * @brief Enable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to enable USCI_UART auto flow control. + */ +void UUART_EnableFlowCtrl(UUART_T* uuart) +{ + /* Set RTS signal is low level active */ + uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk; + + /* Set CTS signal is low level active */ + uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk; + + /* Enable CTS and RTS auto flow control function */ + uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk; +} + +/** + * @brief Disable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART auto flow control. + */ +void UUART_DisableFlowCtrl(UUART_T* uuart) +{ + /* Disable CTS and RTS auto flow control function */ + uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk); +} + + + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/wdt.c b/bsp/nuvoton_m487/libraries/StdDriver/src/wdt.c new file mode 100644 index 00000000000..7506acf46b9 --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/wdt.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file wdt.c + * @version V3.00 + * @brief M480 series WDT driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Initialize WDT and start counting + * + * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are: + * - \ref WDT_TIMEOUT_2POW4 + * - \ref WDT_TIMEOUT_2POW6 + * - \ref WDT_TIMEOUT_2POW8 + * - \ref WDT_TIMEOUT_2POW10 + * - \ref WDT_TIMEOUT_2POW12 + * - \ref WDT_TIMEOUT_2POW14 + * - \ref WDT_TIMEOUT_2POW16 + * - \ref WDT_TIMEOUT_2POW18 + * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are: + * - \ref WDT_RESET_DELAY_1026CLK + * - \ref WDT_RESET_DELAY_130CLK + * - \ref WDT_RESET_DELAY_18CLK + * - \ref WDT_RESET_DELAY_3CLK + * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE. + * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n + * enable or disable WDT time-out reset system or wake-up system. + * @note Please make sure that Register Write-Protection Function has been disabled before using this function. + */ +void WDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + WDT->ALTCTL = u32ResetDelay; + + WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk | + (u32EnableReset << WDT_CTL_RSTEN_Pos) | + (u32EnableWakeup << WDT_CTL_WKEN_Pos); + return; +} + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/libraries/StdDriver/src/wwdt.c b/bsp/nuvoton_m487/libraries/StdDriver/src/wwdt.c new file mode 100644 index 00000000000..d909bd78efb --- /dev/null +++ b/bsp/nuvoton_m487/libraries/StdDriver/src/wwdt.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file wwdt.c + * @version V3.00 + * @brief M480 series WWDT driver source file + * + * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Open WWDT and start counting + * + * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are: + * - \ref WWDT_PRESCALER_1 + * - \ref WWDT_PRESCALER_2 + * - \ref WWDT_PRESCALER_4 + * - \ref WWDT_PRESCALER_8 + * - \ref WWDT_PRESCALER_16 + * - \ref WWDT_PRESCALER_32 + * - \ref WWDT_PRESCALER_64 + * - \ref WWDT_PRESCALER_128 + * - \ref WWDT_PRESCALER_192 + * - \ref WWDT_PRESCALER_256 + * - \ref WWDT_PRESCALER_384 + * - \ref WWDT_PRESCALER_512 + * - \ref WWDT_PRESCALER_768 + * - \ref WWDT_PRESCALER_1024 + * - \ref WWDT_PRESCALER_1536 + * - \ref WWDT_PRESCALER_2048 + * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F. + * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value. + * @note This WWDT_CTL register can be write only one time after chip is powered on or reset. + */ +void WWDT_Open(uint32_t u32PreScale, + uint32_t u32CmpValue, + uint32_t u32EnableInt) +{ + WWDT->CTL = u32PreScale | + (u32CmpValue << WWDT_CTL_CMPDAT_Pos) | + ((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0U) | + WWDT_CTL_WWDTEN_Msk; + return; +} + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton_m487/link.ld b/bsp/nuvoton_m487/link.ld new file mode 100644 index 00000000000..f792b66e840 --- /dev/null +++ b/bsp/nuvoton_m487/link.ld @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-16 bluebear233 first version + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 512K flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 160k /* 160K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x400; + +SECTIONS +{ + .vector : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + } > CODE = 0 + + .text : + { + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .stack : + { + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + _end = .; + + __ram_top = ORIGIN(DATA) + LENGTH(DATA); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/nuvoton_m487/rtconfig.h b/bsp/nuvoton_m487/rtconfig.h new file mode 100644 index 00000000000..5eb9dca57e1 --- /dev/null +++ b/bsp/nuvoton_m487/rtconfig.h @@ -0,0 +1,184 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX + +/* Memory Management */ + +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 1024 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_FILESYSTEMS_MAX 1 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 32 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 64 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + +#define RT_USING_LWIP +#define RT_USING_LWIP202 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 19 +#define RT_LWIP_PBUF_NUM 0 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 19 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 2920 +#define RT_LWIP_TCP_WND 2920 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 768 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_NETIF_LOOPBACK 0 + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* system packages */ + +/* RT-Thread GUI Engine */ + + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* miscellaneous packages */ + + +/* example package: hello */ + + +#endif diff --git a/bsp/nuvoton_m487/rtconfig.py b/bsp/nuvoton_m487/rtconfig.py new file mode 100644 index 00000000000..3223847a28b --- /dev/null +++ b/bsp/nuvoton_m487/rtconfig.py @@ -0,0 +1,132 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'C:/Program Files (x86)/GNU Tools ARM Embedded/6 2017-q2-update/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:\Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.5' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = '' +# BUILD = 'debug' + + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'g++' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + + if BUILD == 'debug': + DEVICE = DEVICE + ' -DDEBUG' + + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-nuc487.map -T link.ld ' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu=cortex-m4.fp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-nuc487.map --scatter nuc487_flash.sct' + + CFLAGS += ' --c99' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' ' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config nuc487_flash.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/nuvoton_m487/template.uvproj b/bsp/nuvoton_m487/template.uvproj new file mode 100644 index 00000000000..9a3bc4a384e --- /dev/null +++ b/bsp/nuvoton_m487/template.uvproj @@ -0,0 +1,400 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-m487 + 0x4 + ARM-ADS + + + M487JIDAE + Nuvoton + IRAM(0x20000000-0x20027FFF) IROM(0-0x7FFFF) CLOCK(192000000) CPUTYPE("Cortex-M4") FPU2 + + undefined + + 0 + + + + + + + + + + + SFD\Nuvoton\M481_v1.SFR + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + template + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 10 + + + + + + + + + + + + + + NULink\Nu_Link.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 0 + NULink\Nu_Link.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x28000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + diff --git a/bsp/nuvoton_nuc472/rtconfig.h b/bsp/nuvoton_nuc472/rtconfig.h index dccf59ecc83..9d1268a7ffb 100644 --- a/bsp/nuvoton_nuc472/rtconfig.h +++ b/bsp/nuvoton_nuc472/rtconfig.h @@ -66,6 +66,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* SECTION: Console options */ #define RT_USING_CONSOLE diff --git a/bsp/nv32f100x/rtconfig.h b/bsp/nv32f100x/rtconfig.h index 0279e205ae2..e5b146528e3 100644 --- a/bsp/nv32f100x/rtconfig.h +++ b/bsp/nv32f100x/rtconfig.h @@ -66,6 +66,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_HOOK #define RT_USING_CPU_USAGE /* SECTION: Console options */ diff --git a/bsp/nv32f100x/rtconfig.py b/bsp/nv32f100x/rtconfig.py index b2c7d0fdc66..7e1e24facd0 100644 --- a/bsp/nv32f100x/rtconfig.py +++ b/bsp/nv32f100x/rtconfig.py @@ -11,11 +11,13 @@ # cross_tool provides the cross compiler # EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = 'G:/iot/camera_studio-win32-20160903/camera_studio/tools/arm-2014.05/bin' + print('================ERROR============================') + print('Not support gcc yet!') + print('=================================================') + exit(0) elif CROSS_TOOL == 'keil': print('================ERROR============================') - print('Not support iar yet!') + print('Not support keil yet!') print('=================================================') exit(0) elif CROSS_TOOL == 'iar': diff --git a/bsp/qemu-vexpress-a9/.config b/bsp/qemu-vexpress-a9/.config index 05071cff278..f5d2fcdd764 100644 --- a/bsp/qemu-vexpress-a9/.config +++ b/bsp/qemu-vexpress-a9/.config @@ -15,6 +15,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=1024 CONFIG_RT_USING_TIMER_SOFT=y @@ -63,9 +64,11 @@ CONFIG_RT_USING_INTERRUPT_INFO=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x30102 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_A=y CONFIG_ARCH_ARM_CORTEX_A9=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components @@ -105,7 +108,7 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_WORKDIR=y CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=8 CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_MNTTABLE is not set CONFIG_RT_USING_DFS_ELMFAT=y @@ -138,20 +141,22 @@ CONFIG_RT_USING_DFS_RAMFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y CONFIG_RT_USING_I2C_BITOPS=y CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_PWM is not set CONFIG_RT_USING_MTD_NOR=y CONFIG_RT_USING_MTD_NAND=y CONFIG_RT_MTD_NAND_DEBUG=y # CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set CONFIG_RT_USING_RTC=y CONFIG_RT_USING_SOFT_RTC=y -# CONFIG_RTC_SYNC_USING_NTP is not set CONFIG_RT_USING_SDIO=y CONFIG_RT_SDIO_STACK_SIZE=512 CONFIG_RT_SDIO_THREAD_PRIORITY=15 @@ -160,10 +165,12 @@ CONFIG_RT_MMCSD_THREAD_PREORITY=22 CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_SDIO_DEBUG is not set CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set CONFIG_RT_USING_SPI_MSD=y CONFIG_RT_USING_SFUD=y CONFIG_RT_SFUD_USING_SFDP=y CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set # CONFIG_RT_DEBUG_SFUD is not set # CONFIG_RT_USING_W25QXX is not set # CONFIG_RT_USING_GD is not set @@ -216,6 +223,7 @@ CONFIG_SAL_PROTO_FAMILIES_NUM=4 CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP210 is not set CONFIG_RT_USING_LWIP_IPV6=y # CONFIG_RT_LWIP_IGMP is not set CONFIG_RT_LWIP_ICMP=y @@ -291,6 +299,8 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_LOG_TRACE_USING_LEVEL_DEBUG is not set # CONFIG_LOG_TRACE_USING_MEMLOG is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # RT-Thread online packages @@ -301,6 +311,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set @@ -326,6 +337,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set # # IoT Cloud @@ -334,6 +346,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set # # security packages @@ -362,6 +375,9 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set # # system packages @@ -378,6 +394,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers @@ -388,6 +405,11 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_AP3216C is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -401,10 +423,8 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set - -# -# sample package -# +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -413,11 +433,8 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_VEXPRESS_A9=y CONFIG_RT_USING_UART0=y CONFIG_RT_USING_UART1=y diff --git a/bsp/qemu-vexpress-a9/drivers/board.c b/bsp/qemu-vexpress-a9/drivers/board.c index 8be0a471033..3a50e4637c7 100644 --- a/bsp/qemu-vexpress-a9/drivers/board.c +++ b/bsp/qemu-vexpress-a9/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2018, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -16,58 +12,11 @@ #include #include "board.h" - -#define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00) -#define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04) -#define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08) -#define TIMER_CTRL_ONESHOT (1 << 0) -#define TIMER_CTRL_32BIT (1 << 1) -#define TIMER_CTRL_DIV1 (0 << 2) -#define TIMER_CTRL_DIV16 (1 << 2) -#define TIMER_CTRL_DIV256 (2 << 2) -#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ -#define TIMER_CTRL_PERIODIC (1 << 6) -#define TIMER_CTRL_ENABLE (1 << 7) - -#define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c) -#define TIMER_RIS(hw_base) __REG32(hw_base + 0x10) -#define TIMER_MIS(hw_base) __REG32(hw_base + 0x14) -#define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18) +#include "drv_timer.h" #define SYS_CTRL __REG32(REALVIEW_SCTL_BASE) -#define TIMER_HW_BASE REALVIEW_TIMER2_3_BASE - -static void rt_hw_timer_isr(int vector, void *param) -{ - rt_tick_increase(); - /* clear interrupt */ - TIMER_INTCLR(TIMER_HW_BASE) = 0x01; -} - -int rt_hw_timer_init(void) -{ - rt_uint32_t val; - - SYS_CTRL |= REALVIEW_REFCLK; - - /* Setup Timer0 for generating irq */ - val = TIMER_CTRL(TIMER_HW_BASE); - val &= ~TIMER_CTRL_ENABLE; - val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE); - TIMER_CTRL(TIMER_HW_BASE) = val; - - TIMER_LOAD(TIMER_HW_BASE) = 1000; - - /* enable timer */ - TIMER_CTRL(TIMER_HW_BASE) |= TIMER_CTRL_ENABLE; - - rt_hw_interrupt_install(IRQ_PBA8_TIMER2_3, rt_hw_timer_isr, RT_NULL, "tick"); - rt_hw_interrupt_umask(IRQ_PBA8_TIMER2_3); - - return 0; -} -INIT_BOARD_EXPORT(rt_hw_timer_init); +extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); void idle_wfi(void) { @@ -79,8 +28,9 @@ void idle_wfi(void) */ void rt_hw_board_init(void) { - /* initialzie hardware interrupt */ + /* initialize hardware interrupt */ rt_hw_interrupt_init(); + /* initialize system heap */ rt_system_heap_init(HEAP_BEGIN, HEAP_END); rt_components_board_init(); diff --git a/bsp/qemu-vexpress-a9/drivers/drv_timer.c b/bsp/qemu-vexpress-a9/drivers/drv_timer.c new file mode 100644 index 00000000000..a4701422026 --- /dev/null +++ b/bsp/qemu-vexpress-a9/drivers/drv_timer.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#include +#include +#include + +#include "board.h" + +#define TIMER01_HW_BASE 0x10011000 +#define TIMER23_HW_BASE 0x10012000 + +#define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00) +#define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04) +#define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08) +#define TIMER_CTRL_ONESHOT (1 << 0) +#define TIMER_CTRL_32BIT (1 << 1) +#define TIMER_CTRL_DIV1 (0 << 2) +#define TIMER_CTRL_DIV16 (1 << 2) +#define TIMER_CTRL_DIV256 (2 << 2) +#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ +#define TIMER_CTRL_PERIODIC (1 << 6) +#define TIMER_CTRL_ENABLE (1 << 7) + +#define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c) +#define TIMER_RIS(hw_base) __REG32(hw_base + 0x10) +#define TIMER_MIS(hw_base) __REG32(hw_base + 0x14) +#define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18) + +#define TIMER_LOAD(hw_base) __REG32(hw_base + 0x00) +#define TIMER_VALUE(hw_base) __REG32(hw_base + 0x04) +#define TIMER_CTRL(hw_base) __REG32(hw_base + 0x08) +#define TIMER_CTRL_ONESHOT (1 << 0) +#define TIMER_CTRL_32BIT (1 << 1) +#define TIMER_CTRL_DIV1 (0 << 2) +#define TIMER_CTRL_DIV16 (1 << 2) +#define TIMER_CTRL_DIV256 (2 << 2) +#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ +#define TIMER_CTRL_PERIODIC (1 << 6) +#define TIMER_CTRL_ENABLE (1 << 7) + +#define TIMER_INTCLR(hw_base) __REG32(hw_base + 0x0c) +#define TIMER_RIS(hw_base) __REG32(hw_base + 0x10) +#define TIMER_MIS(hw_base) __REG32(hw_base + 0x14) +#define TIMER_BGLOAD(hw_base) __REG32(hw_base + 0x18) + +#define SYS_CTRL __REG32(REALVIEW_SCTL_BASE) +#define TIMER_HW_BASE REALVIEW_TIMER2_3_BASE + +static void rt_hw_timer_isr(int vector, void *param) +{ + rt_tick_increase(); + /* clear interrupt */ + TIMER_INTCLR(TIMER_HW_BASE) = 0x01; +} + +int rt_hw_timer_init(void) +{ + rt_uint32_t val; + + SYS_CTRL |= REALVIEW_REFCLK; + + /* Setup Timer0 for generating irq */ + val = TIMER_CTRL(TIMER_HW_BASE); + val &= ~TIMER_CTRL_ENABLE; + val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE); + TIMER_CTRL(TIMER_HW_BASE) = val; + + TIMER_LOAD(TIMER_HW_BASE) = 1000; + + /* enable timer */ + TIMER_CTRL(TIMER_HW_BASE) |= TIMER_CTRL_ENABLE; + + rt_hw_interrupt_install(IRQ_PBA8_TIMER2_3, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_PBA8_TIMER2_3); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_timer_init); + +void timer_init(int timer, unsigned int preload) +{ + uint32_t val; + + if (timer == 0) + { + /* Setup Timer0 for generating irq */ + val = TIMER_CTRL(TIMER01_HW_BASE); + val &= ~TIMER_CTRL_ENABLE; + val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE); + TIMER_CTRL(TIMER01_HW_BASE) = val; + + TIMER_LOAD(TIMER01_HW_BASE) = preload; + + /* enable timer */ + TIMER_CTRL(TIMER01_HW_BASE) |= TIMER_CTRL_ENABLE; + } + else + { + /* Setup Timer1 for generating irq */ + val = TIMER_CTRL(TIMER23_HW_BASE); + val &= ~TIMER_CTRL_ENABLE; + val |= (TIMER_CTRL_32BIT | TIMER_CTRL_PERIODIC | TIMER_CTRL_IE); + TIMER_CTRL(TIMER23_HW_BASE) = val; + + TIMER_LOAD(TIMER23_HW_BASE) = preload; + + /* enable timer */ + TIMER_CTRL(TIMER23_HW_BASE) |= TIMER_CTRL_ENABLE; + } +} + +void timer_clear_pending(int timer) +{ + if (timer == 0) + { + TIMER_INTCLR(TIMER01_HW_BASE) = 0x01; + } + else + { + TIMER_INTCLR(TIMER23_HW_BASE) = 0x01; + } +} diff --git a/bsp/qemu-vexpress-a9/drivers/drv_timer.h b/bsp/qemu-vexpress-a9/drivers/drv_timer.h new file mode 100644 index 00000000000..718f5d43cf2 --- /dev/null +++ b/bsp/qemu-vexpress-a9/drivers/drv_timer.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-22 Jesven first version + */ + +#ifndef DRV_TIMER_H__ +#define DRV_TIMER_H__ + +void timer_init(int timer, unsigned int preload); +void timer_clear_pending(int timer); + +#endif diff --git a/bsp/qemu-vexpress-a9/link.lds b/bsp/qemu-vexpress-a9/link.lds index 51b2ced922f..9485b39e84e 100644 --- a/bsp/qemu-vexpress-a9/link.lds +++ b/bsp/qemu-vexpress-a9/link.lds @@ -11,6 +11,12 @@ SECTIONS *(.text) *(.text.*) + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; diff --git a/bsp/qemu-vexpress-a9/rtconfig.h b/bsp/qemu-vexpress-a9/rtconfig.h index 02d54c452ee..bf53cedf405 100644 --- a/bsp/qemu-vexpress-a9/rtconfig.h +++ b/bsp/qemu-vexpress-a9/rtconfig.h @@ -13,6 +13,7 @@ #define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK #define RT_IDEL_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 1024 #define RT_USING_TIMER_SOFT @@ -44,6 +45,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x30102 #define ARCH_ARM #define ARCH_ARM_CORTEX_A #define ARCH_ARM_CORTEX_A9 @@ -79,7 +81,7 @@ #define RT_USING_DFS #define DFS_USING_WORKDIR #define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 8 #define DFS_FD_MAX 16 #define RT_USING_DFS_ELMFAT @@ -102,6 +104,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN @@ -242,13 +245,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_VEXPRESS_A9 #define RT_USING_UART0 #define RT_USING_UART1 diff --git a/bsp/qemu-vexpress-a9/rtconfig.py b/bsp/qemu-vexpress-a9/rtconfig.py index 545ba76af9b..8ccd0227e45 100644 --- a/bsp/qemu-vexpress-a9/rtconfig.py +++ b/bsp/qemu-vexpress-a9/rtconfig.py @@ -2,7 +2,7 @@ # toolchains options ARCH='arm' -CPU='vexpress-a9' +CPU='cortex-a9' CROSS_TOOL='gcc' if os.getenv('RTT_CC'): @@ -32,7 +32,7 @@ DEVICE = ' -march=armv7-a -marm -msoft-float' CFLAGS = DEVICE + ' -Wall' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__ -I.' LINK_SCRIPT = 'link.lds' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors'+\ ' -T %s' % LINK_SCRIPT diff --git a/bsp/qemu-vexpress-gemini/.config b/bsp/qemu-vexpress-gemini/.config index 02c5ee7d12a..425f9a1eaed 100644 --- a/bsp/qemu-vexpress-gemini/.config +++ b/bsp/qemu-vexpress-gemini/.config @@ -118,6 +118,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/qemu-vexpress-gemini/rtconfig.h b/bsp/qemu-vexpress-gemini/rtconfig.h index a1dcba12482..7218fedca12 100644 --- a/bsp/qemu-vexpress-gemini/rtconfig.h +++ b/bsp/qemu-vexpress-gemini/rtconfig.h @@ -110,6 +110,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/raspi2/.config b/bsp/raspi2/.config index b9827ac3ed2..7db26a7cb19 100644 --- a/bsp/raspi2/.config +++ b/bsp/raspi2/.config @@ -108,6 +108,7 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/raspi2/rtconfig.h b/bsp/raspi2/rtconfig.h index 073c18bed2e..d0b692f9ab3 100644 --- a/bsp/raspi2/rtconfig.h +++ b/bsp/raspi2/rtconfig.h @@ -100,6 +100,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/realview-a8/rtconfig.h b/bsp/realview-a8/rtconfig.h index 2b196b44664..d06e81a0e1f 100644 --- a/bsp/realview-a8/rtconfig.h +++ b/bsp/realview-a8/rtconfig.h @@ -72,6 +72,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // #define RT_UART_RX_BUFFER_SIZE 64 // diff --git a/bsp/rm48x50/rtconfig.h b/bsp/rm48x50/rtconfig.h index a4189b93089..f7d9235a5b7 100644 --- a/bsp/rm48x50/rtconfig.h +++ b/bsp/rm48x50/rtconfig.h @@ -70,6 +70,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // #define RT_UART_RX_BUFFER_SIZE 64 //
diff --git a/bsp/rm48x50/rtconfig.py b/bsp/rm48x50/rtconfig.py index e0899cf38ed..0c11dc8d594 100644 --- a/bsp/rm48x50/rtconfig.py +++ b/bsp/rm48x50/rtconfig.py @@ -14,6 +14,10 @@ elif CROSS_TOOL == 'keil': PLATFORM = 'armcc' EXEC_PATH = 'C:/Keil' + print('================ERROR============================') + print('Not support keil yet!') + print('=================================================') + exit(0) elif CROSS_TOOL == 'iar': print('================ERROR============================') print('Not support IAR yet!') diff --git a/bsp/rx/rtconfig.h b/bsp/rx/rtconfig.h index e1d6cb3fe8c..364204696fb 100644 --- a/bsp/rx/rtconfig.h +++ b/bsp/rx/rtconfig.h @@ -66,6 +66,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* SECTION: Console options */ #define RT_USING_CONSOLE diff --git a/bsp/samd21/rtconfig.h b/bsp/samd21/rtconfig.h index 1ccf6616a0f..c22a5496e76 100644 --- a/bsp/samd21/rtconfig.h +++ b/bsp/samd21/rtconfig.h @@ -68,6 +68,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* SECTION: Console options */ #define RT_USING_CONSOLE diff --git a/bsp/samd21/rtconfig.py b/bsp/samd21/rtconfig.py index 2f2460e77b0..ce47aec5f0b 100644 --- a/bsp/samd21/rtconfig.py +++ b/bsp/samd21/rtconfig.py @@ -18,6 +18,10 @@ if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin' + print('================ERROR============================') + print('Not support gcc yet!') + print('=================================================') + exit(0) elif CROSS_TOOL == 'keil': PLATFORM = 'armcc' EXEC_PATH = 'C:/Keil' diff --git a/bsp/samd21/sam_d2x_asflib/SConscript b/bsp/samd21/sam_d2x_asflib/SConscript index 7561fea0fe3..d50a1213a9e 100644 --- a/bsp/samd21/sam_d2x_asflib/SConscript +++ b/bsp/samd21/sam_d2x_asflib/SConscript @@ -31,13 +31,19 @@ if rtconfig.DEVICE_SERIES == 'SAMD20': path += [cwd + '/sam0/', cwd + '/sam0/utils/cmsis/samd20/include/'] path += [cwd + '/sam0/utils/cmsis/samd20/source/'] src += Glob('./sam0/utils/cmsis/samd20/source/*.c') - src += Glob('./sam0/utils/cmsis/samd20/source/arm/*.s') + if rtconfig.CROSS_TOOL == 'gcc': + src += Glob('./sam0/utils/cmsis/samd20/source/gcc/*.s') + elif rtconfig.CROSS_TOOL == 'keil': + src += Glob('./sam0/utils/cmsis/samd20/source/arm/*.s') elif rtconfig.DEVICE_SERIES == 'SAMD21': #D21 path += [cwd + '/sam0/utils/cmsis/samd21/include/'] path += [cwd + '/sam0/utils/cmsis/samd21/source/'] src += Glob('./sam0/utils/cmsis/samd21/source/*.c') - src += Glob('./sam0/utils/cmsis/samd21/source/arm/*.s') + if rtconfig.CROSS_TOOL == 'gcc': + src += Glob('./sam0/utils/cmsis/samd21/source/gcc/*.s') + elif rtconfig.CROSS_TOOL == 'keil': + src += Glob('./sam0/utils/cmsis/samd21/source/arm/*.s') #sam0/drivers/system path += [cwd + '/sam0/drivers/system/'] @@ -68,8 +74,8 @@ elif rtconfig.DEVICE_SERIES == 'SAMD21': path += [cwd + '/sam0/drivers/sercom', cwd + '/sam0/drivers/sercom/usart'] src += Glob('./sam0/drivers/sercom/*.c') src += Glob('./sam0/drivers/sercom/usart/*.c') -SrcRemove(src, 'sercom_interrupt.c') -SrcRemove(src, 'usart_interrupt.c') +SrcRemove(src, './sam0/drivers/sercom/sercom_interrupt.c') +SrcRemove(src, './sam0/drivers/sercom/usart/usart_interrupt.c') CPPDEFINES += ['USART_CALLBACK_MODE=false'] #sam0/drivers/port diff --git a/bsp/simulator/.config b/bsp/simulator/.config index be55343ce75..dbb69fd3903 100644 --- a/bsp/simulator/.config +++ b/bsp/simulator/.config @@ -117,6 +117,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/simulator/rtconfig.h b/bsp/simulator/rtconfig.h index 995ab93c3b9..4955172df7b 100755 --- a/bsp/simulator/rtconfig.h +++ b/bsp/simulator/rtconfig.h @@ -108,6 +108,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/stm32f0x/drivers/usart.c b/bsp/stm32f0x/drivers/usart.c index 0c4aa15821c..56e39f1c94b 100644 --- a/bsp/stm32f0x/drivers/usart.c +++ b/bsp/stm32f0x/drivers/usart.c @@ -97,8 +97,9 @@ static int stm32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; - while (!(uart->uart_device->ISR & USART_FLAG_TXE)); + USART_ClearFlag(uart->uart_device,USART_FLAG_TC); uart->uart_device->TDR = c; + while (!(uart->uart_device->ISR & USART_FLAG_TC)); return 1; } diff --git a/bsp/stm32f0x/rtconfig.h b/bsp/stm32f0x/rtconfig.h index bee200136a6..0a71690b535 100644 --- a/bsp/stm32f0x/rtconfig.h +++ b/bsp/stm32f0x/rtconfig.h @@ -66,6 +66,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* SECTION: Console options */ #define RT_USING_CONSOLE diff --git a/bsp/stm32f107/.config b/bsp/stm32f107/.config index 855e8b01bde..ec1f16a5152 100644 --- a/bsp/stm32f107/.config +++ b/bsp/stm32f107/.config @@ -15,6 +15,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set @@ -61,16 +62,19 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" -# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_VER_NUM=0x30102 CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y CONFIG_ARCH_ARM_CORTEX_M3=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components # CONFIG_RT_USING_COMPONENTS_INIT=y -# CONFIG_RT_USING_USER_MAIN is not set +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features @@ -99,35 +103,7 @@ CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system # -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_DFS_FD_MAX=16 -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -CONFIG_RT_DFS_ELM_USE_LFN_3=y -CONFIG_RT_DFS_ELM_USE_LFN=3 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=2 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set -# CONFIG_RT_USING_DFS_NFS is not set +# CONFIG_RT_USING_DFS is not set # # Device Drivers @@ -135,21 +111,29 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_AUDIO is not set +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + # # Using USB # @@ -161,8 +145,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_POSIX is not set -# CONFIG_RT_USING_LWP is not set # # Network @@ -176,54 +158,7 @@ CONFIG_RT_USING_LIBC=y # # light weight TCP/IP stack # -CONFIG_RT_USING_LWIP=y -# CONFIG_RT_USING_LWIP141 is not set -CONFIG_RT_USING_LWIP202=y -# CONFIG_RT_USING_LWIP_IPV6 is not set -CONFIG_RT_LWIP_IGMP=y -CONFIG_RT_LWIP_ICMP=y -# CONFIG_RT_LWIP_SNMP is not set -CONFIG_RT_LWIP_DNS=y -CONFIG_RT_LWIP_DHCP=y -CONFIG_IP_SOF_BROADCAST=1 -CONFIG_IP_SOF_BROADCAST_RECV=1 - -# -# Static IPv4 Address -# -CONFIG_RT_LWIP_IPADDR="192.168.1.30" -CONFIG_RT_LWIP_GWADDR="192.168.1.1" -CONFIG_RT_LWIP_MSKADDR="255.255.255.0" -CONFIG_RT_LWIP_UDP=y -CONFIG_RT_LWIP_TCP=y -# CONFIG_RT_LWIP_RAW is not set -# CONFIG_RT_LWIP_PPP is not set -CONFIG_RT_MEMP_NUM_NETCONN=8 -CONFIG_RT_LWIP_PBUF_NUM=16 -CONFIG_RT_LWIP_RAW_PCB_NUM=4 -CONFIG_RT_LWIP_UDP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_SEG_NUM=40 -CONFIG_RT_LWIP_TCP_SND_BUF=8196 -CONFIG_RT_LWIP_TCP_WND=8196 -CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 -CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 -# CONFIG_LWIP_NO_RX_THREAD is not set -# CONFIG_LWIP_NO_TX_THREAD is not set -CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 -CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 -# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set -CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 -CONFIG_SO_REUSE=1 -CONFIG_LWIP_SO_RCVTIMEO=1 -CONFIG_LWIP_SO_SNDTIMEO=1 -CONFIG_LWIP_SO_RCVBUF=1 -# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set -CONFIG_LWIP_NETIF_LOOPBACK=0 -# CONFIG_RT_LWIP_STATS is not set -# CONFIG_RT_LWIP_DEBUG is not set +# CONFIG_RT_USING_LWIP is not set # # Modbus master and slave stack @@ -234,7 +169,6 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # AT commands # # CONFIG_RT_USING_AT is not set -# CONFIG_LWIP_USING_DHCPD is not set # # VBUS(Virtual Software BUS) @@ -246,6 +180,8 @@ CONFIG_LWIP_NETIF_LOOPBACK=0 # # CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set # # ARM CMSIS @@ -262,6 +198,7 @@ CONFIG_RT_USING_RTT_CMSIS=y # # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set @@ -287,6 +224,7 @@ CONFIG_RT_USING_RTT_CMSIS=y # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set # # IoT Cloud @@ -294,6 +232,8 @@ CONFIG_RT_USING_RTT_CMSIS=y # CONFIG_PKG_USING_ONENET is not set # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set # # security packages @@ -322,6 +262,9 @@ CONFIG_RT_USING_RTT_CMSIS=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set # # system packages @@ -335,14 +278,24 @@ CONFIG_RT_USING_RTT_CMSIS=y # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set # # peripheral libraries and drivers # -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages @@ -356,17 +309,21 @@ CONFIG_RT_USING_RTT_CMSIS=y # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # -# sample package -# -# CONFIG_PKG_USING_SAMPLES is not set - -# -# example package: hello +# samples: kernel and components samples # +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_SOC_STM32F1=y # CONFIG_RT_USING_UART1 is not set CONFIG_RT_USING_UART2=y # CONFIG_RT_USING_UART3 is not set +# CONFIG_BSP_USING_RTC is not set +CONFIG_BSP_USING_PIN=y diff --git a/bsp/stm32f107/applications/application.c b/bsp/stm32f107/applications/application.c deleted file mode 100644 index f220cb49173..00000000000 --- a/bsp/stm32f107/applications/application.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - * 2018-08-17 whj remove finsh_set_device add components - */ - -/** - * @addtogroup STM32 - */ -/*@{*/ - -#include -#include - -#ifdef RT_USING_DFS -#include -#include -#endif - -#ifdef RT_USING_LWIP -#include -#include -extern int lwip_system_init(void); -#endif - -#ifdef RT_USING_FINSH -#include -#include -#endif - -void rt_init_thread_entry(void* parameter) -{ -#ifdef RT_USING_COMPONENTS_INIT - /* initialization RT-Thread Components */ - rt_components_init(); -#endif - - { - extern void rt_platform_init(void); - rt_platform_init(); - } - - /* Filesystem Initialization */ -#if defined(RT_USING_DFS) && defined(RT_USING_DFS_ELMFAT) - /* initialize the device file system */ - dfs_init(); - - /* initialize the elm chan FatFS file system*/ - elm_init(); - - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - { - rt_kprintf("File System initialzation failed!\n"); - } -#endif /* RT_USING_DFS && RT_USING_DFS_ELMFAT */ - -#ifdef RT_USING_LWIP - /* initialize lwip stack */ - /* register ethernetif device */ - eth_system_device_init(); - - /* initialize lwip system */ - lwip_system_init(); - rt_kprintf("TCP/IP initialized!\n"); -#endif - -} - -int rt_application_init(void) -{ - rt_thread_t tid; - - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX/3, 20); - if (tid != RT_NULL) rt_thread_startup(tid); - - return 0; -} - -/*@}*/ diff --git a/bsp/stm32f107/applications/main.c b/bsp/stm32f107/applications/main.c new file mode 100644 index 00000000000..bf677172ad9 --- /dev/null +++ b/bsp/stm32f107/applications/main.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + * 2018-08-17 whj remove finsh_set_device add components + * 2018-12-17 whj Change the user interface to main + */ + +/** + * @addtogroup STM32 + */ +/*@{*/ + +#include +#include +#include + +int main(void) +{ + /* user app entry */ + return RT_EOK; +} + +/*@}*/ diff --git a/bsp/stm32f107/drivers/board.c b/bsp/stm32f107/drivers/board.c index 9013e5d07c8..8896047d1f9 100644 --- a/bsp/stm32f107/drivers/board.c +++ b/bsp/stm32f107/drivers/board.c @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2009-01-05 Bernard first implementation - * 2018-08-17 whj add to new rt_console_set_device + * 2018-08-17 whj add to new rt_console_set_device */ #include @@ -44,13 +44,13 @@ void NVIC_Configuration(void) */ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /** @@ -64,14 +64,18 @@ void rt_hw_board_init(void) /* Configure the SysTick */ SysTick_Config( SystemCoreClock / RT_TICK_PER_SECOND ); - rt_components_board_init(); - +#ifdef RT_USING_HEAP + rt_system_heap_init((void*)STM32_SRAM_BEGIN, (void*)STM32_SRAM_END); +#endif + + rt_components_board_init(); + rt_hw_usart_init(); #ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - + } /*@}*/ diff --git a/bsp/stm32f107/drivers/board.h b/bsp/stm32f107/drivers/board.h index 9b5dff53e33..cd9187fe1a0 100644 --- a/bsp/stm32f107/drivers/board.h +++ b/bsp/stm32f107/drivers/board.h @@ -36,7 +36,17 @@ #define STM32_SRAM_SIZE 64 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#define RT_USING_UART1 +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define STM32_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define STM32_SRAM_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define STM32_SRAM_BEGIN (&__bss_end) +#endif + #define RT_USING_SPI1 void rt_hw_board_init(void); diff --git a/bsp/stm32f107/drivers/stm32_eth.c b/bsp/stm32f107/drivers/stm32_eth.c index bd7317090fe..e4efba161b5 100644 --- a/bsp/stm32f107/drivers/stm32_eth.c +++ b/bsp/stm32f107/drivers/stm32_eth.c @@ -3141,7 +3141,7 @@ static void register_multicast_address(struct rt_stm32_eth *stm32_eth, const uin #endif /* (LWIP_IPV4 && LWIP_IGMP) || (LWIP_IPV6 && LWIP_IPV6_MLD) */ #if LWIP_IPV4 && LWIP_IGMP -static err_t igmp_mac_filter( struct netif *netif, const ip4_addr_t *ip4_addr, u8_t action ) +static err_t igmp_mac_filter( struct netif *netif, const ip4_addr_t *ip4_addr, enum netif_mac_filter_action action ) { uint8_t mac[6]; const uint8_t *p = (const uint8_t *)ip4_addr; @@ -3167,7 +3167,7 @@ static err_t igmp_mac_filter( struct netif *netif, const ip4_addr_t *ip4_addr, u #endif /* LWIP_IPV4 && LWIP_IGMP */ #if LWIP_IPV6 && LWIP_IPV6_MLD -static err_t mld_mac_filter( struct netif *netif, const ip6_addr_t *ip6_addr, u8_t action ) +static err_t mld_mac_filter( struct netif *netif, const ip6_addr_t *ip6_addr, enum netif_mac_filter_action action ) { uint8_t mac[6]; const uint8_t *p = (const uint8_t *)&ip6_addr->addr[3]; diff --git a/bsp/stm32f107/drivers/stm32f10x_conf.h b/bsp/stm32f107/drivers/stm32f10x_conf.h index 69b3fd49c90..6f5c6cdff04 100644 --- a/bsp/stm32f107/drivers/stm32f10x_conf.h +++ b/bsp/stm32f107/drivers/stm32f10x_conf.h @@ -51,7 +51,7 @@ /* Exported constants --------------------------------------------------------*/ /* Uncomment the line below to expanse the "assert_param" macro in the Standard Peripheral Library drivers code */ -#define USE_FULL_ASSERT 1 +/*#define USE_FULL_ASSERT 1*/ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT diff --git a/bsp/stm32f107/drivers/usart.c b/bsp/stm32f107/drivers/usart.c index 87c153e9752..e6a7d59535c 100644 --- a/bsp/stm32f107/drivers/usart.c +++ b/bsp/stm32f107/drivers/usart.c @@ -59,19 +59,19 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c USART_InitStructure.USART_BaudRate = cfg->baud_rate; - if (cfg->data_bits == DATA_BITS_8){ + if (cfg->data_bits == DATA_BITS_8) { USART_InitStructure.USART_WordLength = USART_WordLength_8b; } else if (cfg->data_bits == DATA_BITS_9) { USART_InitStructure.USART_WordLength = USART_WordLength_9b; } - if (cfg->stop_bits == STOP_BITS_1){ + if (cfg->stop_bits == STOP_BITS_1) { USART_InitStructure.USART_StopBits = USART_StopBits_1; - } else if (cfg->stop_bits == STOP_BITS_2){ + } else if (cfg->stop_bits == STOP_BITS_2) { USART_InitStructure.USART_StopBits = USART_StopBits_2; } - if (cfg->parity == PARITY_NONE){ + if (cfg->parity == PARITY_NONE) { USART_InitStructure.USART_Parity = USART_Parity_No; } else if (cfg->parity == PARITY_ODD) { USART_InitStructure.USART_Parity = USART_Parity_Odd; @@ -124,6 +124,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; + USART_ClearFlag(uart->uart_device,USART_FLAG_TC); uart->uart_device->DR = c; while (!(uart->uart_device->SR & USART_FLAG_TC)); @@ -271,9 +272,9 @@ void USART3_IRQHandler(void) static void RCC_Configuration(void) { - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); -#if defined(RT_USING_UART1) +#if defined(RT_USING_UART1) RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); #endif /* RT_USING_UART1 */ @@ -293,8 +294,9 @@ static void RCC_Configuration(void) RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); #endif /* RT_USING_UART2 */ -#if defined(RT_USING_UART3) +#if defined(RT_USING_UART3) RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3,ENABLE); GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE); #endif /* RT_USING_UART3 */ } @@ -311,7 +313,7 @@ static void GPIO_Configuration(void) GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX; GPIO_Init(UART1_GPIO, &GPIO_InitStructure); - /* Configure USART1 Tx (PA.09) as alternate function push-pull */ + /* Configure USART1 Tx (PA.09) as alternate function push-pull */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitStructure.GPIO_Pin = UART1_GPIO_TX; GPIO_Init(UART1_GPIO, &GPIO_InitStructure); @@ -333,7 +335,7 @@ static void GPIO_Configuration(void) GPIO_InitStructure.GPIO_Pin = UART3_GPIO_RX; GPIO_Init(UART3_GPIO, &GPIO_InitStructure); - /* Configure USART3 Tx (PC.10) as alternate function push-pull */ + /* Configure USART3 Tx (PC.10) as alternate function push-pull */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitStructure.GPIO_Pin = UART3_GPIO_TX; GPIO_Init(UART3_GPIO, &GPIO_InitStructure); @@ -394,8 +396,8 @@ void rt_hw_usart_init(void) uart = &uart3; config.baud_rate = BAUD_RATE_115200; - serial2.ops = &stm32_uart_ops; - serial2.config = config; + serial3.ops = &stm32_uart_ops; + serial3.config = config; NVIC_Configuration(&uart3); diff --git a/bsp/stm32f107/project.uvprojx b/bsp/stm32f107/project.uvprojx index 27a78833df3..e12a678b75b 100644 --- a/bsp/stm32f107/project.uvprojx +++ b/bsp/stm32f107/project.uvprojx @@ -346,7 +346,7 @@ STM32F10X_CL, RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER - applications;.;drivers;Libraries\STM32F10x_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\components\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m3;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix + applications;.;drivers;Libraries\STM32F10x_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\components\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m3;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common @@ -387,16 +387,9 @@ Applications - application.c + main.c 1 - applications\application.c - - - - - startup.c - 1 - applications\startup.c + applications\main.c @@ -430,13 +423,6 @@ drivers\platform.c - - - stm32_eth.c - 1 - drivers\stm32_eth.c - - gpio.c @@ -639,6 +625,13 @@ ..\..\src\components.c + + + cpu.c + 1 + ..\..\src\cpu.c + + device.c @@ -769,65 +762,6 @@ - - Filesystem - - - dfs.c - 1 - ..\..\components\dfs\src\dfs.c - - - - - dfs_file.c - 1 - ..\..\components\dfs\src\dfs_file.c - - - - - dfs_fs.c - 1 - ..\..\components\dfs\src\dfs_fs.c - - - - - dfs_posix.c - 1 - ..\..\components\dfs\src\dfs_posix.c - - - - - devfs.c - 1 - ..\..\components\dfs\filesystems\devfs\devfs.c - - - - - dfs_elm.c - 1 - ..\..\components\dfs\filesystems\elmfat\dfs_elm.c - - - - - ff.c - 1 - ..\..\components\dfs\filesystems\elmfat\ff.c - - - - - ccsbcs.c - 1 - ..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c - - - DeviceDrivers @@ -865,6 +799,13 @@ ..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + ringbuffer.c @@ -1018,13 +959,6 @@ ..\..\components\libc\compilers\armlibc\mem_std.c - - - stdio.c - 1 - ..\..\components\libc\compilers\armlibc\stdio.c - - stubs.c @@ -1039,259 +973,11 @@ ..\..\components\libc\compilers\armlibc\time.c - - - lwIP - - - sys_arch.c - 1 - ..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c - - - - - api_lib.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_lib.c - - - - - api_msg.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\api_msg.c - - - - - err.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\err.c - - - - - netbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netbuf.c - - - - - netdb.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netdb.c - - - - - netifapi.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\netifapi.c - - - - - sockets.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\sockets.c - - - - - tcpip.c - 1 - ..\..\components\net\lwip-2.0.2\src\api\tcpip.c - - - - - def.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\def.c - - - - - dns.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\dns.c - - - - - inet_chksum.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c - - - - - init.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\init.c - - - - - ip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ip.c - - - - - memp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\memp.c - - - - - netif.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\netif.c - - - - - pbuf.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\pbuf.c - - - - - raw.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\raw.c - - - - - stats.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\stats.c - - - - - sys.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\sys.c - - - - - tcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp.c - - - - - tcp_in.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_in.c - - - - - tcp_out.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\tcp_out.c - - - - - timeouts.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\timeouts.c - - - - - udp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\udp.c - - - - - ethernet.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernet.c - - - - - ethernetif.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c - - - - - lowpan6.c - 1 - ..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c - - - - - autoip.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c - - - - - dhcp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c - - - - - etharp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c - - - - - icmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c - - - - - igmp.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c - - - - - ip4.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c - - - - - ip4_addr.c - 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c - - - ip4_frag.c + gmtime_r.c 1 - ..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c + ..\..\components\libc\compilers\common\gmtime_r.c diff --git a/bsp/stm32f107/rtconfig.h b/bsp/stm32f107/rtconfig.h index bc4e8e42321..3cea36ea713 100644 --- a/bsp/stm32f107/rtconfig.h +++ b/bsp/stm32f107/rtconfig.h @@ -13,6 +13,7 @@ #define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK #define RT_IDEL_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_DEBUG @@ -38,6 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x30102 #define ARCH_ARM #define ARCH_ARM_CORTEX_M #define ARCH_ARM_CORTEX_M3 @@ -45,6 +47,9 @@ /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 /* C++ features */ @@ -66,32 +71,18 @@ /* Device virtual file system */ -#define RT_USING_DFS -#define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 -#define DFS_FD_MAX 16 -#define RT_USING_DFS_ELMFAT - -/* elm-chan's FatFs, Generic FAT Filesystem Module */ - -#define RT_DFS_ELM_CODE_PAGE 437 -#define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_USE_LFN_3 -#define RT_DFS_ELM_USE_LFN 3 -#define RT_DFS_ELM_MAX_LFN 255 -#define RT_DFS_ELM_DRIVES 2 -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 -#define RT_DFS_ELM_REENTRANT -#define RT_USING_DFS_DEVFS /* Device Drivers */ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN +/* Using WiFi */ + + /* Using USB */ @@ -106,42 +97,6 @@ /* light weight TCP/IP stack */ -#define RT_USING_LWIP -#define RT_USING_LWIP202 -#define RT_LWIP_IGMP -#define RT_LWIP_ICMP -#define RT_LWIP_DNS -#define RT_LWIP_DHCP -#define IP_SOF_BROADCAST 1 -#define IP_SOF_BROADCAST_RECV 1 - -/* Static IPv4 Address */ - -#define RT_LWIP_IPADDR "192.168.1.30" -#define RT_LWIP_GWADDR "192.168.1.1" -#define RT_LWIP_MSKADDR "255.255.255.0" -#define RT_LWIP_UDP -#define RT_LWIP_TCP -#define RT_MEMP_NUM_NETCONN 8 -#define RT_LWIP_PBUF_NUM 16 -#define RT_LWIP_RAW_PCB_NUM 4 -#define RT_LWIP_UDP_PCB_NUM 4 -#define RT_LWIP_TCP_PCB_NUM 4 -#define RT_LWIP_TCP_SEG_NUM 40 -#define RT_LWIP_TCP_SND_BUF 8196 -#define RT_LWIP_TCP_WND 8196 -#define RT_LWIP_TCPTHREAD_PRIORITY 10 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_PRIORITY 12 -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 -#define LWIP_NETIF_STATUS_CALLBACK 1 -#define SO_REUSE 1 -#define LWIP_SO_RCVTIMEO 1 -#define LWIP_SO_SNDTIMEO 1 -#define LWIP_SO_RCVBUF 1 -#define LWIP_NETIF_LOOPBACK 0 /* Modbus master and slave stack */ @@ -196,12 +151,10 @@ /* miscellaneous packages */ -/* sample package */ - - -/* example package: hello */ +/* samples: kernel and components samples */ #define SOC_STM32F1 #define RT_USING_UART2 +#define BSP_USING_PIN #endif diff --git a/bsp/stm32f10x-HAL/.config b/bsp/stm32f10x-HAL/.config index 3f583f6b34a..39706cd4966 100644 --- a/bsp/stm32f10x-HAL/.config +++ b/bsp/stm32f10x-HAL/.config @@ -91,6 +91,7 @@ CONFIG_FINSH_USING_MSH_ONLY=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/stm32f10x-HAL/drivers/drv_gpio.c b/bsp/stm32f10x-HAL/drivers/drv_gpio.c index 7fd20db49a8..e25adf33c2c 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_gpio.c +++ b/bsp/stm32f10x-HAL/drivers/drv_gpio.c @@ -788,17 +788,19 @@ rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, drv_clock_enable(gpio_pin); /* Configure GPIO_InitStructure */ GPIO_InitStruct.Pin = get_st_pin(gpio_pin); - GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; switch (pin_irq_hdr_tab[irqindex].mode) { case PIN_IRQ_MODE_RISING: + GPIO_InitStruct.Pull = GPIO_PULLDOWN; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; break; case PIN_IRQ_MODE_FALLING: + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; break; case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; break; } diff --git a/bsp/stm32f10x-HAL/drivers/drv_i2c.c b/bsp/stm32f10x-HAL/drivers/drv_i2c.c index 3109e95bd3d..7836103f9ce 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_i2c.c +++ b/bsp/stm32f10x-HAL/drivers/drv_i2c.c @@ -31,12 +31,12 @@ static void drv_i2c_gpio_init() GPIO_Initure.Pin = I2C_SCL_PIN; GPIO_Initure.Mode = GPIO_MODE_OUTPUT_OD; GPIO_Initure.Pull = GPIO_PULLUP; - GPIO_Initure.Speed = GPIO_SPEED_HIGH; + GPIO_Initure.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(I2C_SCL_PORT, &GPIO_Initure); GPIO_Initure.Pin = I2C_SDA_PIN; GPIO_Initure.Mode = GPIO_MODE_OUTPUT_OD; GPIO_Initure.Pull = GPIO_PULLUP; - GPIO_Initure.Speed = GPIO_SPEED_HIGH; + GPIO_Initure.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(I2C_SDA_PORT, &GPIO_Initure); HAL_GPIO_WritePin(I2C_SCL_PORT, I2C_SCL_PIN, GPIO_PIN_SET); HAL_GPIO_WritePin(I2C_SDA_PORT, I2C_SDA_PIN, GPIO_PIN_SET); diff --git a/bsp/stm32f10x-HAL/drivers/drv_usart.c b/bsp/stm32f10x-HAL/drivers/drv_usart.c index 26504699212..bd6b6cd984f 100644 --- a/bsp/stm32f10x-HAL/drivers/drv_usart.c +++ b/bsp/stm32f10x-HAL/drivers/drv_usart.c @@ -113,8 +113,9 @@ static int stm32_putc(struct rt_serial_device *serial, char c) struct stm32_uart *uart; RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; - while (__HAL_UART_GET_FLAG(&uart->huart, UART_FLAG_TXE) == RESET); + __HAL_UART_CLEAR_FLAG(&(uart->huart), UART_FLAG_TC); uart->huart.Instance->DR = c; + while (__HAL_UART_GET_FLAG(&(uart->huart), UART_FLAG_TC) == RESET); return 1; } diff --git a/bsp/stm32f10x-HAL/rtconfig.h b/bsp/stm32f10x-HAL/rtconfig.h index ad9537c4951..84514b603c1 100644 --- a/bsp/stm32f10x-HAL/rtconfig.h +++ b/bsp/stm32f10x-HAL/rtconfig.h @@ -83,6 +83,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/stm32f10x/.config b/bsp/stm32f10x/.config index 360fa61320c..7b1a9477ab0 100644 --- a/bsp/stm32f10x/.config +++ b/bsp/stm32f10x/.config @@ -121,6 +121,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_USING_CAN=y CONFIG_RT_CAN_USING_HDR=y # CONFIG_RT_USING_HWTIMER is not set diff --git a/bsp/stm32f10x/drivers/usart.c b/bsp/stm32f10x/drivers/usart.c index 3841a5c9f1d..1c61b184a65 100644 --- a/bsp/stm32f10x/drivers/usart.c +++ b/bsp/stm32f10x/drivers/usart.c @@ -45,6 +45,7 @@ struct stm32_uart { USART_TypeDef *uart_device; IRQn_Type irq; +#ifdef RT_SERIAL_USING_DMA struct stm32_uart_dma { /* dma channel */ @@ -58,9 +59,12 @@ struct stm32_uart /* last receive index */ rt_size_t last_recv_index; } dma; +#endif /* RT_SERIAL_USING_DMA */ }; +#ifdef RT_SERIAL_USING_DMA static void DMA_Configuration(struct rt_serial_device *serial); +#endif /* RT_SERIAL_USING_DMA */ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { @@ -107,7 +111,6 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg) { struct stm32_uart* uart; - rt_uint32_t ctrl_arg = (rt_uint32_t)(arg); RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; @@ -128,12 +131,14 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar /* enable interrupt */ USART_ITConfig(uart->uart_device, USART_IT_RXNE, ENABLE); break; +#ifdef RT_SERIAL_USING_DMA /* USART config */ case RT_DEVICE_CTRL_CONFIG : - if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { + if ((rt_uint32_t)(arg) == RT_DEVICE_FLAG_DMA_RX) { DMA_Configuration(serial); } break; +#endif /* RT_SERIAL_USING_DMA */ } return RT_EOK; } @@ -157,6 +162,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c) } else { + USART_ClearFlag(uart->uart_device,USART_FLAG_TC); uart->uart_device->DR = c; while (!(uart->uart_device->SR & USART_FLAG_TC)); } @@ -181,6 +187,7 @@ static int stm32_getc(struct rt_serial_device *serial) return ch; } +#ifdef RT_SERIAL_USING_DMA /** * Serial port receive idle process. This need add to uart idle ISR. * @@ -230,6 +237,7 @@ static void dma_rx_done_isr(struct rt_serial_device *serial) { DMA_ClearFlag(uart->dma.rx_gl_flag); } +#endif /* RT_SERIAL_USING_DMA */ /** * Uart common interrupt process. This need add to uart ISR. @@ -250,10 +258,12 @@ static void uart_isr(struct rt_serial_device *serial) { /* clear interrupt */ USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); } +#ifdef RT_SERIAL_USING_DMA if(USART_GetITStatus(uart->uart_device, USART_IT_IDLE) != RESET) { dma_uart_rx_idle_isr(serial); } +#endif /* RT_SERIAL_USING_DMA */ if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) { /* clear interrupt */ @@ -283,6 +293,7 @@ static const struct rt_uart_ops stm32_uart_ops = struct stm32_uart uart1 = { USART1, +#ifdef RT_SERIAL_USING_DMA USART1_IRQn, { DMA1_Channel5, @@ -290,6 +301,7 @@ struct stm32_uart uart1 = DMA1_Channel5_IRQn, 0, }, +#endif /* RT_SERIAL_USING_DMA */ }; struct rt_serial_device serial1; @@ -304,6 +316,7 @@ void USART1_IRQHandler(void) rt_interrupt_leave(); } +#ifdef RT_SERIAL_USING_DMA void DMA1_Channel5_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -313,6 +326,8 @@ void DMA1_Channel5_IRQHandler(void) { /* leave interrupt */ rt_interrupt_leave(); } +#endif /* RT_SERIAL_USING_DMA */ + #endif /* RT_USING_UART1 */ #if defined(RT_USING_UART2) @@ -320,6 +335,7 @@ void DMA1_Channel5_IRQHandler(void) { struct stm32_uart uart2 = { USART2, +#ifdef RT_SERIAL_USING_DMA USART2_IRQn, { DMA1_Channel6, @@ -327,6 +343,7 @@ struct stm32_uart uart2 = DMA1_Channel6_IRQn, 0, }, +#endif /* RT_SERIAL_USING_DMA */ }; struct rt_serial_device serial2; @@ -341,6 +358,7 @@ void USART2_IRQHandler(void) rt_interrupt_leave(); } +#ifdef RT_SERIAL_USING_DMA void DMA1_Channel6_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -350,6 +368,8 @@ void DMA1_Channel6_IRQHandler(void) { /* leave interrupt */ rt_interrupt_leave(); } +#endif /* RT_SERIAL_USING_DMA */ + #endif /* RT_USING_UART2 */ #if defined(RT_USING_UART3) @@ -357,6 +377,7 @@ void DMA1_Channel6_IRQHandler(void) { struct stm32_uart uart3 = { USART3, +#ifdef RT_SERIAL_USING_DMA USART3_IRQn, { DMA1_Channel3, @@ -364,6 +385,7 @@ struct stm32_uart uart3 = DMA1_Channel3_IRQn, 0, }, +#endif /* RT_SERIAL_USING_DMA */ }; struct rt_serial_device serial3; @@ -378,6 +400,7 @@ void USART3_IRQHandler(void) rt_interrupt_leave(); } +#ifdef RT_SERIAL_USING_DMA void DMA1_Channel3_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -387,6 +410,8 @@ void DMA1_Channel3_IRQHandler(void) { /* leave interrupt */ rt_interrupt_leave(); } +#endif /* RT_SERIAL_USING_DMA */ + #endif /* RT_USING_UART3 */ #if defined(RT_USING_UART4) @@ -394,6 +419,7 @@ void DMA1_Channel3_IRQHandler(void) { struct stm32_uart uart4 = { UART4, +#ifdef RT_SERIAL_USING_DMA UART4_IRQn, { DMA2_Channel3, @@ -401,6 +427,7 @@ struct stm32_uart uart4 = DMA2_Channel3_IRQn, 0, }, +#endif /* RT_SERIAL_USING_DMA */ }; struct rt_serial_device serial4; @@ -415,6 +442,7 @@ void UART4_IRQHandler(void) rt_interrupt_leave(); } +#ifdef RT_SERIAL_USING_DMA void DMA2_Channel3_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -424,6 +452,8 @@ void DMA2_Channel3_IRQHandler(void) { /* leave interrupt */ rt_interrupt_leave(); } +#endif /* RT_SERIAL_USING_DMA */ + #endif /* RT_USING_UART4 */ static void RCC_Configuration(void) @@ -520,6 +550,7 @@ static void NVIC_Configuration(struct stm32_uart* uart) NVIC_Init(&NVIC_InitStructure); } +#ifdef RT_SERIAL_USING_DMA static void DMA_Configuration(struct rt_serial_device *serial) { struct stm32_uart *uart = (struct stm32_uart *) serial->parent.user_data; struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; @@ -561,6 +592,7 @@ static void DMA_Configuration(struct rt_serial_device *serial) { NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); } +#endif /* RT_SERIAL_USING_DMA */ void rt_hw_usart_init(void) { diff --git a/bsp/stm32f10x/rtconfig.h b/bsp/stm32f10x/rtconfig.h index e41cb5fc105..e1d38b46678 100644 --- a/bsp/stm32f10x/rtconfig.h +++ b/bsp/stm32f10x/rtconfig.h @@ -112,6 +112,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_CAN #define RT_CAN_USING_HDR /* RT_USING_HWTIMER is not set */ diff --git a/bsp/stm32f40x/.config b/bsp/stm32f40x/.config index b7945e18203..a6a47ac6f37 100644 --- a/bsp/stm32f40x/.config +++ b/bsp/stm32f40x/.config @@ -135,6 +135,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/stm32f40x/drivers/stm32f4xx_eth.c b/bsp/stm32f40x/drivers/stm32f4xx_eth.c index 0ae4c19b97b..8db924875b9 100644 --- a/bsp/stm32f40x/drivers/stm32f4xx_eth.c +++ b/bsp/stm32f40x/drivers/stm32f4xx_eth.c @@ -3467,7 +3467,7 @@ static void register_multicast_address(struct rt_stm32_eth *stm32_eth, const uin #endif /* (LWIP_IPV4 && LWIP_IGMP) || (LWIP_IPV6 && LWIP_IPV6_MLD) */ #if LWIP_IPV4 && LWIP_IGMP -static err_t igmp_mac_filter( struct netif *netif, const ip4_addr_t *ip4_addr, u8_t action ) +static err_t igmp_mac_filter( struct netif *netif, const ip4_addr_t *ip4_addr, enum netif_mac_filter_action action ) { uint8_t mac[6]; const uint8_t *p = (const uint8_t *)ip4_addr; @@ -3493,7 +3493,7 @@ static err_t igmp_mac_filter( struct netif *netif, const ip4_addr_t *ip4_addr, u #endif /* LWIP_IPV4 && LWIP_IGMP */ #if LWIP_IPV6 && LWIP_IPV6_MLD -static err_t mld_mac_filter( struct netif *netif, const ip6_addr_t *ip6_addr, u8_t action ) +static err_t mld_mac_filter( struct netif *netif, const ip6_addr_t *ip6_addr, enum netif_mac_filter_action action ) { uint8_t mac[6]; const uint8_t *p = (const uint8_t *)&ip6_addr->addr[3]; diff --git a/bsp/stm32f40x/drivers/usart.c b/bsp/stm32f40x/drivers/usart.c index 0633c82cdd8..3caedd5ce05 100644 --- a/bsp/stm32f40x/drivers/usart.c +++ b/bsp/stm32f40x/drivers/usart.c @@ -66,6 +66,7 @@ struct stm32_uart { USART_TypeDef *uart_device; IRQn_Type irq; +#ifdef RT_SERIAL_USING_DMA struct stm32_uart_dma { /* dma stream */ @@ -81,9 +82,12 @@ struct stm32_uart /* last receive index */ rt_size_t last_recv_index; } dma; +#endif /* RT_SERIAL_USING_DMA */ }; - + +#ifdef RT_SERIAL_USING_DMA static void DMA_Configuration(struct rt_serial_device *serial); +#endif /* RT_SERIAL_USING_DMA */ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { @@ -130,7 +134,6 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg) { struct stm32_uart* uart; - rt_uint32_t ctrl_arg = (rt_uint32_t)(arg); RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; @@ -149,11 +152,13 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar /* enable interrupt */ USART_ITConfig(uart->uart_device, USART_IT_RXNE, ENABLE); break; +#ifdef RT_SERIAL_USING_DMA /* USART config */ case RT_DEVICE_CTRL_CONFIG : - if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { + if ((rt_uint32_t)(arg) == RT_DEVICE_FLAG_DMA_RX) { DMA_Configuration(serial); } +#endif /* RT_SERIAL_USING_DMA */ } return RT_EOK; @@ -166,8 +171,9 @@ static int stm32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; - while (!(uart->uart_device->SR & USART_FLAG_TXE)); + USART_ClearFlag(uart->uart_device,USART_FLAG_TC); uart->uart_device->DR = c; + while (!(uart->uart_device->SR & USART_FLAG_TC)); return 1; } @@ -189,6 +195,7 @@ static int stm32_getc(struct rt_serial_device *serial) return ch; } +#ifdef RT_SERIAL_USING_DMA /** * DMA initialize by DMA_InitStruct structure * @@ -277,6 +284,7 @@ static void dma_rx_done_isr(struct rt_serial_device *serial) DMA_ClearFlag(uart->dma.rx_stream, uart->dma.rx_flag); } } +#endif /* RT_SERIAL_USING_DMA */ /** * Uart common interrupt process. This need add to uart ISR. @@ -295,10 +303,12 @@ static void uart_isr(struct rt_serial_device *serial) /* clear interrupt */ USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE); } +#ifdef RT_SERIAL_USING_DMA if(USART_GetITStatus(uart->uart_device, USART_IT_IDLE) != RESET) { dma_uart_rx_idle_isr(serial); } +#endif /* RT_SERIAL_USING_DMA */ if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET) { /* clear interrupt */ @@ -324,6 +334,7 @@ static const struct rt_uart_ops stm32_uart_ops = struct stm32_uart uart1 = { USART1, +#ifdef RT_SERIAL_USING_DMA USART1_IRQn, { DMA2_Stream5, @@ -332,6 +343,7 @@ struct stm32_uart uart1 = DMA2_Stream5_IRQn, 0, }, +#endif /* RT_SERIAL_USING_DMA */ }; struct rt_serial_device serial1; @@ -346,6 +358,7 @@ void USART1_IRQHandler(void) rt_interrupt_leave(); } +#ifdef RT_SERIAL_USING_DMA void DMA2_Stream5_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -355,6 +368,8 @@ void DMA2_Stream5_IRQHandler(void) { /* leave interrupt */ rt_interrupt_leave(); } +#endif /* RT_SERIAL_USING_DMA */ + #endif /* RT_USING_UART1 */ #if defined(RT_USING_UART2) @@ -362,6 +377,7 @@ void DMA2_Stream5_IRQHandler(void) { struct stm32_uart uart2 = { USART2, +#ifdef RT_SERIAL_USING_DMA USART2_IRQn, { DMA1_Stream5, @@ -371,6 +387,7 @@ struct stm32_uart uart2 = 0, 0, }, +#endif /* RT_SERIAL_USING_DMA */ }; struct rt_serial_device serial2; @@ -385,6 +402,7 @@ void USART2_IRQHandler(void) rt_interrupt_leave(); } +#ifdef RT_SERIAL_USING_DMA void DMA1_Stream5_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -394,6 +412,8 @@ void DMA1_Stream5_IRQHandler(void) { /* leave interrupt */ rt_interrupt_leave(); } +#endif /* RT_SERIAL_USING_DMA */ + #endif /* RT_USING_UART2 */ #if defined(RT_USING_UART3) @@ -401,6 +421,7 @@ void DMA1_Stream5_IRQHandler(void) { struct stm32_uart uart3 = { USART3, +#ifdef RT_SERIAL_USING_DMA USART3_IRQn, { DMA1_Stream1, @@ -410,6 +431,7 @@ struct stm32_uart uart3 = 0, 0, }, +#endif /* RT_SERIAL_USING_DMA */ }; struct rt_serial_device serial3; @@ -424,6 +446,7 @@ void USART3_IRQHandler(void) rt_interrupt_leave(); } +#ifdef RT_SERIAL_USING_DMA void DMA1_Stream1_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -433,6 +456,8 @@ void DMA1_Stream1_IRQHandler(void) { /* leave interrupt */ rt_interrupt_leave(); } +#endif /* RT_SERIAL_USING_DMA */ + #endif /* RT_USING_UART3 */ #if defined(RT_USING_UART4) @@ -440,6 +465,7 @@ void DMA1_Stream1_IRQHandler(void) { struct stm32_uart uart4 = { UART4, +#ifdef RT_SERIAL_USING_DMA UART4_IRQn, { DMA1_Stream2, @@ -449,6 +475,7 @@ struct stm32_uart uart4 = 0, 0, }, +#endif /* RT_SERIAL_USING_DMA */ }; struct rt_serial_device serial4; @@ -463,6 +490,7 @@ void UART4_IRQHandler(void) rt_interrupt_leave(); } +#ifdef RT_SERIAL_USING_DMA void DMA1_Stream2_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -472,6 +500,8 @@ void DMA1_Stream2_IRQHandler(void) { /* leave interrupt */ rt_interrupt_leave(); } +#endif /* RT_SERIAL_USING_DMA */ + #endif /* RT_USING_UART4 */ #if defined(RT_USING_UART5) @@ -479,6 +509,7 @@ void DMA1_Stream2_IRQHandler(void) { struct stm32_uart uart5 = { UART5, +#ifdef RT_SERIAL_USING_DMA UART5_IRQn, { DMA1_Stream0, @@ -488,6 +519,7 @@ struct stm32_uart uart5 = 0, 0, }, +#endif /* RT_SERIAL_USING_DMA */ }; struct rt_serial_device serial5; @@ -502,6 +534,7 @@ void UART5_IRQHandler(void) rt_interrupt_leave(); } +#ifdef RT_SERIAL_USING_DMA void DMA1_Stream0_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -511,6 +544,8 @@ void DMA1_Stream0_IRQHandler(void) { /* leave interrupt */ rt_interrupt_leave(); } +#endif /* RT_SERIAL_USING_DMA */ + #endif /* RT_USING_UART5 */ static void RCC_Configuration(void) @@ -625,6 +660,7 @@ static void NVIC_Configuration(struct stm32_uart *uart) NVIC_Init(&NVIC_InitStructure); } +#ifdef RT_SERIAL_USING_DMA static void DMA_Configuration(struct rt_serial_device *serial) { struct stm32_uart *uart = (struct stm32_uart *) serial->parent.user_data; struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; @@ -652,6 +688,7 @@ static void DMA_Configuration(struct rt_serial_device *serial) { NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); } +#endif /* RT_SERIAL_USING_DMA */ int stm32_hw_usart_init(void) { diff --git a/bsp/stm32f40x/project.uvprojx b/bsp/stm32f40x/project.uvprojx index 3f2b878128d..ceed9f525c6 100644 --- a/bsp/stm32f40x/project.uvprojx +++ b/bsp/stm32f40x/project.uvprojx @@ -1,46 +1,43 @@ - 2.1 -
### uVision Project, (C) Keil Software
- rt-thread_stm32f4xx 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC + 5060528::V5.06 update 5 (build 528)::ARMCC 0 - STM32F407VG + STM32F407VGTx STMicroelectronics Keil.STM32F4xx_DFP.2.13.0 http://www.keil.com/pack IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VG$CMSIS\Flash\STM32F4xx_1024.FLM)) - 6103 - $$Device:STM32F407VG$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h - - - - - - - -DSTM32F40_41xxx - - - $$Device:STM32F407VG$CMSIS\SVD\STM32F40x.svd + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407VGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VGTx$CMSIS\SVD\STM32F40x.svd 0 0 - - - - - + + + + + 0 0 @@ -52,9 +49,9 @@ rtthread-stm32f4xx 1 0 - 0 + 1 1 - 1 + 0 .\build\ 1 0 @@ -62,8 +59,8 @@ 0 0 - - + + 0 0 0 @@ -72,8 +69,8 @@ 0 0 - - + + 0 0 0 @@ -82,15 +79,15 @@ 1 0 - fromelf --bin !L --output rtthread.bin - + fromelf --bin !L --output @H.bin + 0 0 0 0 0 - + 0 @@ -104,17 +101,17 @@ 0 0 3 - - + + 1 SARMCM3.DLL - -MPU -REMAP + -REMAP -MPU DCM.DLL -pCM4 SARMCM3.DLL - -MPU + -MPU TCM.DLL -pCM4 @@ -134,15 +131,15 @@ 0 1 1 - 4100 + 4096 1 - STLink\ST-LINKIII-KEIL.dll - - - - - + BIN\UL2CM3.DLL + + + + + 0 @@ -175,7 +172,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -307,7 +304,7 @@ 0x10000 - + 1 @@ -326,17 +323,17 @@ 0 0 0 - 1 - 1 - 1 - 1 + 0 + 0 + 0 + 0 0 0 0 - + RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER - + applications;.;drivers;Libraries\STM32F4xx_StdPeriph_Driver\inc;Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\pthreads;..\..\components\libc\time @@ -352,14 +349,14 @@ 0 0 - - - - + + + + - 1 + 0 0 0 0 @@ -367,13 +364,13 @@ 0 0x08000000 0x20000000 - - - - + + .\stm32_rom.sct + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + @@ -396,16 +393,22 @@ 1 drivers\board.c + + stm32f4xx_it.c 1 drivers\stm32f4xx_it.c + + usart.c 1 drivers\usart.c + + gpio.c 1 @@ -421,161 +424,225 @@ 1 Libraries\CMSIS\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + misc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\misc.c + + stm32f4xx_adc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_adc.c + + stm32f4xx_can.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_can.c + + stm32f4xx_crc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_crc.c + + stm32f4xx_cryp.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp.c + + stm32f4xx_cryp_aes.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_aes.c + + stm32f4xx_cryp_des.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_des.c + + stm32f4xx_cryp_tdes.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_tdes.c + + stm32f4xx_dac.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dac.c + + stm32f4xx_dbgmcu.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dbgmcu.c + + stm32f4xx_dcmi.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dcmi.c + + stm32f4xx_dma.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dma.c + + stm32f4xx_exti.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_exti.c + + stm32f4xx_flash.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_flash.c + + stm32f4xx_fsmc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_fsmc.c + + stm32f4xx_gpio.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_gpio.c + + stm32f4xx_hash.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash.c + + stm32f4xx_hash_md5.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_md5.c + + stm32f4xx_hash_sha1.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_sha1.c + + stm32f4xx_i2c.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_i2c.c + + stm32f4xx_iwdg.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_iwdg.c + + stm32f4xx_pwr.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_pwr.c + + stm32f4xx_rcc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rcc.c + + stm32f4xx_rng.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rng.c + + stm32f4xx_rtc.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rtc.c + + stm32f4xx_sdio.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_sdio.c + + stm32f4xx_spi.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_spi.c + + stm32f4xx_syscfg.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_syscfg.c + + stm32f4xx_tim.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c + + stm32f4xx_usart.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_usart.c + + stm32f4xx_wwdg.c 1 Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_wwdg.c + + startup_stm32f4xx.s 2 @@ -591,71 +658,106 @@ 1 ..\..\src\clock.c + + components.c 1 ..\..\src\components.c + + + + cpu.c + 1 + ..\..\src\cpu.c + + + device.c 1 ..\..\src\device.c + + idle.c 1 ..\..\src\idle.c + + ipc.c 1 ..\..\src\ipc.c + + irq.c 1 ..\..\src\irq.c + + kservice.c 1 ..\..\src\kservice.c + + mem.c 1 ..\..\src\mem.c + + memheap.c 1 ..\..\src\memheap.c + + mempool.c 1 ..\..\src\mempool.c + + object.c 1 ..\..\src\object.c + + scheduler.c 1 ..\..\src\scheduler.c + + signal.c 1 ..\..\src\signal.c + + thread.c 1 ..\..\src\thread.c + + timer.c 1 @@ -671,21 +773,29 @@ 1 ..\..\libcpu\arm\cortex-m4\cpuport.c + + context_rvds.S 2 ..\..\libcpu\arm\cortex-m4\context_rvds.S + + backtrace.c 1 ..\..\libcpu\arm\common\backtrace.c + + div0.c 1 ..\..\libcpu\arm\common\div0.c + + showmem.c 1 @@ -701,41 +811,57 @@ 1 ..\..\components\dfs\src\dfs.c + + dfs_file.c 1 ..\..\components\dfs\src\dfs_file.c + + dfs_fs.c 1 ..\..\components\dfs\src\dfs_fs.c + + dfs_posix.c 1 ..\..\components\dfs\src\dfs_posix.c + + poll.c 1 ..\..\components\dfs\src\poll.c + + select.c 1 ..\..\components\dfs\src\select.c + + devfs.c 1 ..\..\components\dfs\filesystems\devfs\devfs.c + + dfs_elm.c 1 ..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + ff.c 1 @@ -751,41 +877,57 @@ 1 ..\..\components\drivers\misc\pin.c + + serial.c 1 ..\..\components\drivers\serial\serial.c + + completion.c 1 ..\..\components\drivers\src\completion.c + + dataqueue.c 1 ..\..\components\drivers\src\dataqueue.c + + pipe.c 1 ..\..\components\drivers\src\pipe.c + + ringblk_buf.c 1 ..\..\components\drivers\src\ringblk_buf.c + + ringbuffer.c 1 ..\..\components\drivers\src\ringbuffer.c + + waitqueue.c 1 ..\..\components\drivers\src\waitqueue.c + + workqueue.c 1 @@ -801,76 +943,106 @@ 1 ..\..\components\finsh\shell.c + + symbol.c 1 ..\..\components\finsh\symbol.c + + cmd.c 1 ..\..\components\finsh\cmd.c + + msh.c 1 ..\..\components\finsh\msh.c + + msh_cmd.c 1 ..\..\components\finsh\msh_cmd.c + + msh_file.c 1 ..\..\components\finsh\msh_file.c + + finsh_compiler.c 1 ..\..\components\finsh\finsh_compiler.c + + finsh_error.c 1 ..\..\components\finsh\finsh_error.c + + finsh_heap.c 1 ..\..\components\finsh\finsh_heap.c + + finsh_init.c 1 ..\..\components\finsh\finsh_init.c + + finsh_node.c 1 ..\..\components\finsh\finsh_node.c + + finsh_ops.c 1 ..\..\components\finsh\finsh_ops.c + + finsh_parser.c 1 ..\..\components\finsh\finsh_parser.c + + finsh_var.c 1 ..\..\components\finsh\finsh_var.c + + finsh_vm.c 1 ..\..\components\finsh\finsh_vm.c + + finsh_token.c 1 @@ -886,26 +1058,36 @@ 1 ..\..\components\libc\compilers\armlibc\libc.c + + mem_std.c 1 ..\..\components\libc\compilers\armlibc\mem_std.c + + stdio.c 1 ..\..\components\libc\compilers\armlibc\stdio.c + + stubs.c 1 ..\..\components\libc\compilers\armlibc\stubs.c + + time.c 1 ..\..\components\libc\compilers\armlibc\time.c + + gmtime_r.c 1 @@ -921,61 +1103,85 @@ 1 ..\..\components\libc\pthreads\mqueue.c + + pthread.c 1 ..\..\components\libc\pthreads\pthread.c + + pthread_attr.c 1 ..\..\components\libc\pthreads\pthread_attr.c + + pthread_barrier.c 1 ..\..\components\libc\pthreads\pthread_barrier.c + + pthread_cond.c 1 ..\..\components\libc\pthreads\pthread_cond.c + + pthread_mutex.c 1 ..\..\components\libc\pthreads\pthread_mutex.c + + pthread_rwlock.c 1 ..\..\components\libc\pthreads\pthread_rwlock.c + + pthread_spin.c 1 ..\..\components\libc\pthreads\pthread_spin.c + + pthread_tls.c 1 ..\..\components\libc\pthreads\pthread_tls.c + + sched.c 1 ..\..\components\libc\pthreads\sched.c + + semaphore.c 1 ..\..\components\libc\pthreads\semaphore.c + + clock_time.c 1 ..\..\components\libc\time\clock_time.c + + posix_sleep.c 1 @@ -983,24 +1189,12 @@ - - ::CMSIS - - - - - - - - - - - - + + + - diff --git a/bsp/stm32f40x/rtconfig.h b/bsp/stm32f40x/rtconfig.h index 9482d19aa35..c855f42fad8 100644 --- a/bsp/stm32f40x/rtconfig.h +++ b/bsp/stm32f40x/rtconfig.h @@ -93,6 +93,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using USB */ diff --git a/bsp/stm32f40x/template.uvprojx b/bsp/stm32f40x/template.uvprojx index 367b472a681..89875ab0431 100644 --- a/bsp/stm32f40x/template.uvprojx +++ b/bsp/stm32f40x/template.uvprojx @@ -1,7 +1,7 @@ - 1.1 + 2.1
### uVision Project, (C) Keil Software
@@ -10,382 +10,380 @@ rt-thread_stm32f4xx 0x4 ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 - - STM32F407VG - STMicroelectronics - Keil.STM32F4xx_DFP.2.2.0 - http://www.keil.com/pack - IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) - 0 - $$Device:STM32F407VGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h - - - - - - - - - - $$Device:STM32F407VGTx$CMSIS\SVD\STM32F40x.svd - 0 - 0 - - - - ST\STM32F4xx\ - ST\STM32F4xx\ - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-stm32f4xx - 1 - 0 - 0 - 1 - 1 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - 0 - 8 - - - - - - - - - - - - - - STLink\ST-LINKIII-KEIL.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4100 - - STLink\ST-LINKIII-KEIL.dll - "" () - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 1 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x100000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 0 - 0x10000000 - 0x10000 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - + + STM32F407VGTx + STMicroelectronics + Keil.STM32F4xx_DFP.2.13.0 + http://www.keil.com/pack + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) + 0 + $$Device:STM32F407VGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F407VGTx$CMSIS\SVD\STM32F40x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-stm32f4xx + 1 + 0 + 1 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output @H.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\stm32_rom.sct + + + + + + + + + + + + + diff --git a/bsp/stm32f411-nucleo/.config b/bsp/stm32f411-nucleo/.config index a757505873e..f300370a169 100644 --- a/bsp/stm32f411-nucleo/.config +++ b/bsp/stm32f411-nucleo/.config @@ -92,6 +92,7 @@ CONFIG_FINSH_USING_MSH_ONLY=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/stm32f411-nucleo/drivers/drv_usart.c b/bsp/stm32f411-nucleo/drivers/drv_usart.c index a0a00886942..dacd1490ebe 100644 --- a/bsp/stm32f411-nucleo/drivers/drv_usart.c +++ b/bsp/stm32f411-nucleo/drivers/drv_usart.c @@ -155,8 +155,9 @@ static int drv_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct drv_uart *)serial->parent.user_data; - while((__HAL_UART_GET_FLAG(&uart->UartHandle, UART_FLAG_TXE) == RESET)); + __HAL_UART_CLEAR_FLAG(&(uart->UartHandle), UART_FLAG_TC); uart->UartHandle.Instance->DR = c; + while (__HAL_UART_GET_FLAG(&(uart->UartHandle), UART_FLAG_TC) == RESET); return 1; } diff --git a/bsp/stm32f411-nucleo/rtconfig.h b/bsp/stm32f411-nucleo/rtconfig.h index e3b684271c1..3a925c78b4a 100644 --- a/bsp/stm32f411-nucleo/rtconfig.h +++ b/bsp/stm32f411-nucleo/rtconfig.h @@ -70,6 +70,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* Using USB */ diff --git a/bsp/stm32f411-nucleo/template.emProject b/bsp/stm32f411-nucleo/template.emProject new file mode 100644 index 00000000000..cbbf266c656 --- /dev/null +++ b/bsp/stm32f411-nucleo/template.emProject @@ -0,0 +1,45 @@ + + + + + + + + + diff --git a/bsp/stm32f429-apollo/.config b/bsp/stm32f429-apollo/.config index 45c584c1885..604b56e5b25 100644 --- a/bsp/stm32f429-apollo/.config +++ b/bsp/stm32f429-apollo/.config @@ -132,6 +132,7 @@ CONFIG_RT_USING_DFS_ROMFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/stm32f429-apollo/drivers/Kconfig b/bsp/stm32f429-apollo/drivers/Kconfig index f9691bbe45f..39addd5bcdf 100644 --- a/bsp/stm32f429-apollo/drivers/Kconfig +++ b/bsp/stm32f429-apollo/drivers/Kconfig @@ -18,6 +18,11 @@ config RT_USING_SPI5 bool "Enable SPI5" default y +config RT_USING_SAI_AUDIO + select RT_USING_AUDIO + bool "Enable AUDIO" + default n + config RT_RTC_NAME string "The name of RTC device" default rtc diff --git a/bsp/stm32f429-apollo/drivers/SConscript b/bsp/stm32f429-apollo/drivers/SConscript index 3c05f05d71c..c8ba0bed2b0 100644 --- a/bsp/stm32f429-apollo/drivers/SConscript +++ b/bsp/stm32f429-apollo/drivers/SConscript @@ -2,8 +2,12 @@ from building import * cwd = GetCurrentDir() +# init src and inc vars +src = [] +inc = [] + # add the general drivers. -src = Split(""" +src += Split(""" board.c stm32f4xx_it.c usart.c @@ -12,6 +16,9 @@ drv_rtc.c drv_mpu.c """) +# add dwin basic include +inc += [cwd] + # add sdio driver if GetDepend('RT_USING_DFS'): src += ['drv_sdio_sd.c'] @@ -39,12 +46,15 @@ if GetDepend('RT_USING_SPI'): if GetDepend('RT_USING_SFUD'): src += ['drv_spi_flash.c'] +# add audio drivers. +if GetDepend('RT_USING_SAI_AUDIO'): + src += Glob('./audio/*.c') + inc += [cwd + "/audio"] + # add lcd drivers. if GetDepend('PKG_USING_GUIENGINE'): src += ['drv_lcd.c'] - -CPPPATH = [cwd] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = inc) Return('group') diff --git a/bsp/stm32f429-apollo/drivers/audio/drv_audio.h b/bsp/stm32f429-apollo/drivers/audio/drv_audio.h new file mode 100644 index 00000000000..e04a897a55a --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/audio/drv_audio.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + */ + +#ifndef __DRV_AUDIO_H__ +#define __DRV_AUDIO_H__ + +#include +#include +#include + +/* SAIA DMA Stream TX definitions */ +#define SAIA_TX_DMAx_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE() +#define SAIA_TX_DMAx_CLK_DISABLE() __HAL_RCC_DMA2_CLK_DISABLE() +#define SAIA_TX_DMAx_STREAM DMA2_Stream3 +#define SAIA_TX_DMAx_CHANNEL DMA_CHANNEL_0 +#define SAIA_TX_DMAx_IRQ DMA2_Stream3_IRQn +#define SAIA_TX_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD +#define SAIA_TX_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD +#define SAIA_TX_DMAx_IRQHandler DMA2_Stream3_IRQHandler + +/* SAIB DMA Stream TX definitions */ +#define SAIA_RX_DMAx_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE() +#define SAIA_RX_DMAx_CLK_DISABLE() __HAL_RCC_DMA2_CLK_DISABLE() +#define SAIA_RX_DMAx_STREAM DMA2_Stream5 +#define SAIA_RX_DMAx_CHANNEL DMA_CHANNEL_0 +#define SAIA_RX_DMAx_IRQ DMA2_Stream5_IRQn +#define SAIA_RX_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD +#define SAIA_RX_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD +#define SAIA_RX_DMAx_IRQHandler DMA2_Stream5_IRQHandler + +int SAIA_SampleRate_Set(uint32_t samplerate); +int rt_hw_audio_init(char *i2c_bus_name); + +#endif diff --git a/bsp/stm32f429-apollo/drivers/audio/drv_mic.c b/bsp/stm32f429-apollo/drivers/audio/drv_mic.c new file mode 100644 index 00000000000..873f37e9b76 --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/audio/drv_mic.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + */ + +#include +#include +#include + +#include + +#include "drv_audio.h" +#include "drv_wm8978.h" +#include + +#define DBG_ENABLE +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#define DBG_SECTION_NAME "MIC" +#include + +struct micphone_device +{ + struct rt_device parent; + rt_uint16_t *recv_fifo; + struct rt_audio_pipe record_pipe; + + /* i2c mode */ + struct rt_i2c_bus_device *i2c_device; +}; + +#define AUDIO_RECV_BUFFER_SIZE (2048) + +extern SAI_HandleTypeDef SAI1B_Handler; +extern DMA_HandleTypeDef SAI1_RXDMA_Handler; +extern SAI_HandleTypeDef SAI1A_Handler; +extern DMA_HandleTypeDef SAI1_TXDMA_Handler; + +static struct micphone_device micphone; +static uint16_t send_fifo[2] = {0, 0}; + +static void SAIB_Init(void) +{ + HAL_SAI_DeInit(&SAI1B_Handler); + SAI1B_Handler.Instance = SAI1_Block_B; + SAI1B_Handler.Init.AudioMode = SAI_MODESLAVE_RX; + SAI1B_Handler.Init.Synchro = SAI_SYNCHRONOUS; + SAI1B_Handler.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE; + SAI1B_Handler.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + SAI1B_Handler.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF; + SAI1B_Handler.Init.ClockSource = SAI_CLKSOURCE_PLLI2S; + SAI1B_Handler.Init.MonoStereoMode = SAI_MONOMODE; + SAI1B_Handler.Init.Protocol = SAI_FREE_PROTOCOL; + SAI1B_Handler.Init.DataSize = SAI_DATASIZE_16; + SAI1B_Handler.Init.FirstBit = SAI_FIRSTBIT_MSB; + SAI1B_Handler.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + + SAI1B_Handler.FrameInit.FrameLength = 64; + SAI1B_Handler.FrameInit.ActiveFrameLength = 32; + SAI1B_Handler.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + SAI1B_Handler.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + SAI1B_Handler.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + + SAI1B_Handler.SlotInit.FirstBitOffset = 0; + SAI1B_Handler.SlotInit.SlotSize = SAI_SLOTSIZE_32B; + SAI1B_Handler.SlotInit.SlotNumber = 2; + SAI1B_Handler.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1; + + HAL_SAI_Init(&SAI1B_Handler); + __HAL_SAI_ENABLE(&SAI1B_Handler); + + SAIA_RX_DMAx_CLK_ENABLE(); + __HAL_LINKDMA(&SAI1B_Handler, hdmarx, SAI1_RXDMA_Handler); + SAI1_RXDMA_Handler.Instance = SAIA_RX_DMAx_STREAM; + SAI1_RXDMA_Handler.Init.Channel = SAIA_RX_DMAx_CHANNEL; + SAI1_RXDMA_Handler.Init.Direction = DMA_PERIPH_TO_MEMORY; + SAI1_RXDMA_Handler.Init.PeriphInc = DMA_PINC_DISABLE; + SAI1_RXDMA_Handler.Init.MemInc = DMA_MINC_ENABLE; + SAI1_RXDMA_Handler.Init.PeriphDataAlignment = SAIA_RX_DMAx_PERIPH_DATA_SIZE; + SAI1_RXDMA_Handler.Init.MemDataAlignment = SAIA_RX_DMAx_MEM_DATA_SIZE; + SAI1_RXDMA_Handler.Init.Mode = DMA_CIRCULAR; + SAI1_RXDMA_Handler.Init.Priority = DMA_PRIORITY_MEDIUM; + SAI1_RXDMA_Handler.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + SAI1_RXDMA_Handler.Init.MemBurst = DMA_MBURST_SINGLE; + SAI1_RXDMA_Handler.Init.PeriphBurst = DMA_PBURST_SINGLE; + HAL_DMA_DeInit(&SAI1_RXDMA_Handler); + HAL_DMA_Init(&SAI1_RXDMA_Handler); + + HAL_NVIC_SetPriority(SAIA_RX_DMAx_IRQ, 0, 1); + HAL_NVIC_EnableIRQ(SAIA_RX_DMAx_IRQ); +} + +void SAIA_RX_DMAx_IRQHandler(void) +{ + HAL_DMA_IRQHandler(&SAI1_RXDMA_Handler); +} + +void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + if (hsai == &SAI1B_Handler) + { + rt_device_write(&micphone.record_pipe.parent, 0, micphone.recv_fifo, AUDIO_RECV_BUFFER_SIZE / 2); + } +} + +void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) +{ + if (hsai == &SAI1B_Handler) + { + rt_device_write(&micphone.record_pipe.parent, 0, micphone.recv_fifo + (AUDIO_RECV_BUFFER_SIZE / 4), AUDIO_RECV_BUFFER_SIZE / 2); + } +} + +static rt_err_t micphone_init(rt_device_t dev) +{ + SAIB_Init(); + + return RT_EOK; +} + +static rt_err_t micphone_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct micphone_device *mic = RT_NULL; + + mic = (struct micphone_device *)dev; + + if (oflag & RT_DEVICE_OFLAG_RDONLY) + { + LOG_I("Open Micphone Device!"); + + rt_device_open(&mic->record_pipe.parent, RT_DEVICE_OFLAG_RDONLY); + /* Disable DMA Interruption */ + __HAL_DMA_DISABLE_IT(&SAI1_TXDMA_Handler, DMA_IT_TC | DMA_IT_HT); + HAL_DMA_Start(&SAI1_TXDMA_Handler, (uint32_t)&send_fifo[0], (uint32_t)&SAI1_Block_A->DR, 2); + /* Start RX DMA */ + HAL_SAI_Receive_DMA(&SAI1B_Handler, (uint8_t *)(micphone.recv_fifo), AUDIO_RECV_BUFFER_SIZE / 2); + } + + return RT_EOK; +} + +static rt_size_t micphone_read(rt_device_t dev, rt_off_t pos, + void *buffer, rt_size_t size) +{ + struct micphone_device *mic = RT_NULL; + + mic = (struct micphone_device *)dev; + return rt_device_read(&mic->record_pipe.parent, pos, buffer, size); +} + +static rt_err_t micphone_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t value, result = RT_EOK; + + switch (cmd) + { + case CODEC_CMD_SET_VOLUME: + { + // TODO + break; + } + + case CODEC_CMD_SAMPLERATE: + { + value = *(int *)args; + LOG_I("Set Samplerate %d", value); + result = SAIA_SampleRate_Set(value); + break; + } + + default: + break; + } + + return result; +} + +static rt_err_t micphone_close(rt_device_t dev) +{ + struct micphone_device *mic = RT_NULL; + + mic = (struct micphone_device *)dev; + HAL_SAI_DMAStop(&SAI1A_Handler); + HAL_SAI_DMAStop(&SAI1B_Handler); + rt_device_close(&mic->record_pipe.parent); + LOG_I("Close Micphone Device!"); + + return RT_EOK; +} + +int rt_hw_micphone_init(char *i2c_bus_name) +{ + int result = RT_EOK; + struct micphone_device *mic = &micphone; + + if (mic->recv_fifo != RT_NULL) + { + return RT_EOK; + } + + mic->recv_fifo = rt_malloc(AUDIO_RECV_BUFFER_SIZE); + if (mic->recv_fifo == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + memset(mic->recv_fifo, 0, AUDIO_RECV_BUFFER_SIZE); + + mic->parent.type = RT_Device_Class_Sound; + mic->parent.init = micphone_init; + mic->parent.open = micphone_open; + mic->parent.control = micphone_control; + mic->parent.write = RT_NULL; + mic->parent.read = micphone_read; + mic->parent.close = micphone_close; + mic->parent.user_data = mic; + + /* register the device */ + rt_device_register(&mic->parent, "mic", RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_DMA_RX); + + rt_device_init(&mic->parent); + + { + rt_uint8_t *buffer = rt_malloc(AUDIO_RECV_BUFFER_SIZE); + if (buffer == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + memset(buffer, 0, AUDIO_RECV_BUFFER_SIZE); + + rt_audio_pipe_init(&mic->record_pipe, + "voice", + RT_PIPE_FLAG_FORCE_WR | RT_PIPE_FLAG_BLOCK_RD, + buffer, + AUDIO_RECV_BUFFER_SIZE); + } + + return RT_EOK; + +__exit: + if (mic->recv_fifo) + { + rt_free(mic->recv_fifo); + mic->recv_fifo = RT_NULL; + } + + return result; +} diff --git a/bsp/stm32f429-apollo/drivers/audio/drv_sound.c b/bsp/stm32f429-apollo/drivers/audio/drv_sound.c new file mode 100644 index 00000000000..43bbadf4124 --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/audio/drv_sound.c @@ -0,0 +1,594 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + */ + +#include +#include +#include + +#include +#include + +#include "drv_audio.h" +#include "drv_wm8978.h" +#include + +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_COLOR +#define DBG_SECTION_NAME "Sound" +#include + +/** + * Audio Memory Node Manage + */ +struct rt_data_node +{ + char *data_ptr; + rt_uint32_t data_size; +}; + +struct rt_data_node_list +{ + struct rt_data_node *node; + rt_uint32_t size; + rt_uint32_t read_index, write_index; + rt_uint32_t data_offset; + void (*read_complete)(struct rt_data_node *node, void *user_data); + void *user_data; +}; + +int rt_data_node_init(struct rt_data_node_list **node_list, rt_uint32_t size) +{ + int result = RT_EOK; + struct rt_data_node_list *list = RT_NULL; + struct rt_data_node *node = RT_NULL; + + list = rt_malloc(sizeof(struct rt_data_node_list)); + if (list == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + memset(list, 0, sizeof(struct rt_data_node_list)); + + node = rt_malloc(sizeof(struct rt_data_node) * size); + if (size == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + memset(node, 0, sizeof(struct rt_data_node)); + + list->node = node; + list->size = size; + list->read_index = 0; + list->write_index = 0; + list->data_offset = 0; + list->read_complete = RT_NULL; + list->user_data = 0; + + *node_list = list; + + return result; + +__exit: + if (list) + rt_free(list); + + if (node) + rt_free(node); + + return result; +} + +int rt_data_node_is_empty(struct rt_data_node_list *node_list) +{ + rt_uint32_t read_index, write_index; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + read_index = node_list->read_index; + write_index = node_list->write_index; + rt_hw_interrupt_enable(level); + + if (read_index == write_index) + { + return RT_TRUE; + } + else + { + return RT_FALSE; + } +} + +void wait_node_free(struct rt_data_node_list *node_list) +{ + while (node_list->read_index != node_list->write_index) + rt_thread_mdelay(5); +} + +int rt_data_node_write(struct rt_data_node_list *node_list, void *buffer, rt_uint32_t size) +{ + struct rt_data_node *node = RT_NULL; + rt_uint32_t read_index, write_index, next_index; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + read_index = node_list->read_index; + write_index = node_list->write_index; + rt_hw_interrupt_enable(level); + + next_index = write_index + 1; + if (next_index >= node_list->size) + next_index = 0; + + if (next_index == read_index) + { + rt_kprintf("[node]:node list full, write index = %d, read index = %d \n", write_index, read_index); + return -RT_ERROR; + } + + level = rt_hw_interrupt_disable(); + /* set node attribute */ + node = &node_list->node[write_index]; + node->data_ptr = (char *) buffer; + node->data_size = size; + node_list->write_index = next_index; + rt_hw_interrupt_enable(level); + + return size; +} + +int rt_data_node_read(struct rt_data_node_list *node_list, void *buffer, rt_uint32_t size) +{ + struct rt_data_node *node = RT_NULL; + rt_uint32_t read_index, write_index, next_index; + rt_int32_t remain_len, copy_size; + rt_uint32_t read_offset, data_offset; + rt_base_t level; + rt_uint32_t result = size; + + level = rt_hw_interrupt_disable(); + read_index = node_list->read_index; + write_index = node_list->write_index; + rt_hw_interrupt_enable(level); + + read_offset = 0; + if (read_index == write_index) + { + result = 0; + } + else + { + do + { + node = &node_list->node[node_list->read_index]; + data_offset = node_list->data_offset; + remain_len = node->data_size - data_offset; + if (size - read_offset > remain_len) + { + /* Full*/ + copy_size = remain_len; + } + else + { + /* reamain buffer */ + copy_size = size - read_offset; + } + + memcpy((char *)buffer + read_offset, node->data_ptr + data_offset, copy_size); + read_offset += copy_size; + data_offset += copy_size; + node_list->data_offset = data_offset; + + if (data_offset >= node->data_size) + { + /* notify transmitted complete. */ + if (node_list->read_complete != RT_NULL) + { + node_list->read_complete(node, node_list->user_data); + } + + level = rt_hw_interrupt_disable(); + read_index = node_list->read_index; + write_index = node_list->write_index; + rt_hw_interrupt_enable(level); + + next_index = read_index + 1; + if (next_index >= node_list->size) + next_index = 0; + + level = rt_hw_interrupt_disable(); + node_list->read_index = next_index; + node_list->data_offset = 0; + rt_hw_interrupt_enable(level); + + if (next_index == write_index) + { + result = read_offset; + break; + } + } + } + while (read_offset < size); + } + + return result; +} + +static void data_node_read_complete(struct rt_data_node *node, void *user_data) +{ + struct rt_device *dev = RT_NULL; + + dev = (struct rt_device *)user_data; + if (dev->tx_complete != RT_NULL) + { + dev->tx_complete(dev, node->data_ptr); + } +} + +/** + * RT-Thread Audio Device Driver + */ +struct sound_device +{ + struct rt_device parent; + struct rt_data_node_list *node_list; + + /* i2c mode */ + struct rt_i2c_bus_device *i2c_device; + + char *send_fifo; +}; + +#define AUDIO_SEND_BUFFER_SIZE (2048 * 2) + +SAI_HandleTypeDef SAI1B_Handler; +DMA_HandleTypeDef SAI1_RXDMA_Handler; +SAI_HandleTypeDef SAI1A_Handler; +DMA_HandleTypeDef SAI1_TXDMA_Handler; + +static struct sound_device *sound; + +static void SAIA_Init(void) +{ + HAL_SAI_DeInit(&SAI1A_Handler); + // SAI1A_Handler.Init.AudioFrequency = 44100; + SAI1A_Handler.Instance = SAI1_Block_A; + SAI1A_Handler.Init.AudioMode = SAI_MODEMASTER_TX; + SAI1A_Handler.Init.Synchro = SAI_ASYNCHRONOUS; + SAI1A_Handler.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE; + SAI1A_Handler.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + SAI1A_Handler.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY; + SAI1A_Handler.Init.ClockSource = SAI_CLKSOURCE_PLLI2S; + SAI1A_Handler.Init.MonoStereoMode = SAI_STEREOMODE; + SAI1A_Handler.Init.Protocol = SAI_FREE_PROTOCOL; + SAI1A_Handler.Init.DataSize = SAI_DATASIZE_16; + SAI1A_Handler.Init.FirstBit = SAI_FIRSTBIT_MSB; + SAI1A_Handler.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + + SAI1A_Handler.FrameInit.FrameLength = 64; + SAI1A_Handler.FrameInit.ActiveFrameLength = 32; + SAI1A_Handler.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + SAI1A_Handler.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + SAI1A_Handler.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + SAI1A_Handler.SlotInit.FirstBitOffset = 0; + SAI1A_Handler.SlotInit.SlotSize = SAI_SLOTSIZE_32B; + SAI1A_Handler.SlotInit.SlotNumber = 2; + SAI1A_Handler.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1; + + HAL_SAI_Init(&SAI1A_Handler); + __HAL_SAI_ENABLE(&SAI1A_Handler); + + /* DMA Configuration */ + SAIA_TX_DMAx_CLK_ENABLE(); + __HAL_LINKDMA(&SAI1A_Handler, hdmatx, SAI1_TXDMA_Handler); + SAI1_TXDMA_Handler.Instance = SAIA_TX_DMAx_STREAM; + SAI1_TXDMA_Handler.Init.Channel = SAIA_TX_DMAx_CHANNEL; + SAI1_TXDMA_Handler.Init.Direction = DMA_MEMORY_TO_PERIPH; + SAI1_TXDMA_Handler.Init.PeriphInc = DMA_PINC_DISABLE; + SAI1_TXDMA_Handler.Init.MemInc = DMA_MINC_ENABLE; + SAI1_TXDMA_Handler.Init.PeriphDataAlignment = SAIA_TX_DMAx_PERIPH_DATA_SIZE; + SAI1_TXDMA_Handler.Init.MemDataAlignment = SAIA_TX_DMAx_MEM_DATA_SIZE; + SAI1_TXDMA_Handler.Init.Mode = DMA_CIRCULAR; + SAI1_TXDMA_Handler.Init.Priority = DMA_PRIORITY_HIGH; + SAI1_TXDMA_Handler.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + SAI1_TXDMA_Handler.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL; + SAI1_TXDMA_Handler.Init.MemBurst = DMA_MBURST_SINGLE; + SAI1_TXDMA_Handler.Init.PeriphBurst = DMA_PBURST_SINGLE; + HAL_DMA_DeInit(&SAI1_TXDMA_Handler); + HAL_DMA_Init(&SAI1_TXDMA_Handler); + + HAL_NVIC_SetPriority(SAIA_TX_DMAx_IRQ, 0, 0); + HAL_NVIC_EnableIRQ(SAIA_TX_DMAx_IRQ); +} + +const uint16_t SAI_PSC_TBL[][5] = +{ + {800, 344, 7, 0, 12}, + {1102, 429, 2, 18, 2}, + {1600, 344, 7, 0, 6}, + {2205, 429, 2, 18, 1}, + {3200, 344, 7, 0, 3}, + {4410, 429, 2, 18, 0}, + {4800, 344, 7, 0, 2}, + {8820, 271, 2, 2, 1}, + {9600, 344, 7, 0, 1}, + {17640, 271, 2, 2, 0}, + {19200, 344, 7, 0, 0}, +}; + +void SAIA_DMA_Enable(void) +{ + SAI1_Block_A->CR1 |= SAI_xCR1_DMAEN; +} + +void SAIA_DMA_Disable(void) +{ + SAI1_Block_A->CR1 &= ~SAI_xCR1_DMAEN; +} + +int SAIA_SampleRate_Set(uint32_t samplerate) +{ + uint16_t i = 0; + + RCC_PeriphCLKInitTypeDef RCCSAI1_Sture; + for (i = 0; i < (sizeof(SAI_PSC_TBL) / 10); i++) + { + if ((samplerate / 10) == SAI_PSC_TBL[i][0]) + break; + } + if (i == (sizeof(SAI_PSC_TBL) / 10)) + return -RT_ERROR; + RCCSAI1_Sture.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S; + RCCSAI1_Sture.PLLI2S.PLLI2SN = (uint32_t)SAI_PSC_TBL[i][1]; + RCCSAI1_Sture.PLLI2S.PLLI2SQ = (uint32_t)SAI_PSC_TBL[i][2]; + RCCSAI1_Sture.PLLI2SDivQ = SAI_PSC_TBL[i][3] + 1; + HAL_RCCEx_PeriphCLKConfig(&RCCSAI1_Sture); + + __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(RCC_SAIACLKSOURCE_PLLI2S); + + __HAL_SAI_DISABLE(&SAI1A_Handler); + SAIA_DMA_Disable(); + SAI1A_Handler.Init.AudioFrequency = samplerate; + HAL_SAI_Init(&SAI1A_Handler); + SAIA_DMA_Enable(); + __HAL_SAI_ENABLE(&SAI1A_Handler); + + return RT_EOK; +} + +void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) +{ + GPIO_InitTypeDef GPIO_Initure; + __HAL_RCC_SAI1_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + + GPIO_Initure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6; + GPIO_Initure.Mode = GPIO_MODE_AF_PP; + GPIO_Initure.Pull = GPIO_PULLUP; + GPIO_Initure.Speed = GPIO_SPEED_HIGH; + GPIO_Initure.Alternate = GPIO_AF6_SAI1; + HAL_GPIO_Init(GPIOE, &GPIO_Initure); +} + +void SAIA_TX_DMAx_IRQHandler(void) +{ + HAL_DMA_IRQHandler(&SAI1_TXDMA_Handler); +} + +void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + int result; + struct sound_device *snd = sound; + + if (hsai == &SAI1A_Handler) + { + result = rt_data_node_is_empty(snd->node_list); + if (result) + { + rt_kprintf("# "); + memset(snd->send_fifo, 0, AUDIO_SEND_BUFFER_SIZE / 2); + } + else + { + memset(snd->send_fifo, 0, AUDIO_SEND_BUFFER_SIZE / 2); + rt_data_node_read(snd->node_list, snd->send_fifo, AUDIO_SEND_BUFFER_SIZE / 2); + } + } +} + +void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) +{ + int result; + struct sound_device *snd = sound; + + if (hsai == &SAI1A_Handler) + { + result = rt_data_node_is_empty(snd->node_list); + if (result) + { + rt_kprintf("* "); + memset(snd->send_fifo + (AUDIO_SEND_BUFFER_SIZE / 2), 0, AUDIO_SEND_BUFFER_SIZE / 2); + } + else + { + memset(snd->send_fifo + (AUDIO_SEND_BUFFER_SIZE / 2), 0, AUDIO_SEND_BUFFER_SIZE / 2); + rt_data_node_read(snd->node_list, snd->send_fifo + (AUDIO_SEND_BUFFER_SIZE / 2), AUDIO_SEND_BUFFER_SIZE / 2); + } + + } +} + +void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) +{ + rt_kprintf("x "); +} + + +static rt_err_t sound_init(rt_device_t dev) +{ + int result; + struct sound_device *snd = (struct sound_device *)dev; + + SAIA_Init(); + result = wm8978_init(snd->i2c_device); + + return result; +} + +static rt_err_t sound_open(rt_device_t dev, rt_uint16_t oflag) +{ + int result = RT_EOK; + struct sound_device *snd = (struct sound_device *)dev; + + LOG_I("Open Sound Device!"); + + /* Configure DMA transmit */ + result = HAL_SAI_Transmit_DMA(&SAI1A_Handler, (uint8_t *)(snd->send_fifo), AUDIO_SEND_BUFFER_SIZE / 2); + if (result != HAL_OK) + { + LOG_E("Start DMA Transmit Failed!"); + result = -RT_ERROR; + } + + return result; +} + +static rt_err_t sound_control(rt_device_t dev, int cmd, void *args) +{ + int value, result = RT_EOK; + struct sound_device *snd = (struct sound_device *)dev; + + switch (cmd) + { + case CODEC_CMD_SET_VOLUME: + value = *(int *)args; + if (value < 0 || value > 99) + { + LOG_W("Please volume level 0 ~ 99"); + result = -RT_EINVAL; + } + else + { + LOG_I("Set volume level to %d", value); + wm8978_set_volume(snd->i2c_device, value); + result = RT_EOK; + } + break; + + case CODEC_CMD_SAMPLERATE: + value = *(int *)args; + LOG_I("Set Samplerate %d", value); + SAIA_SampleRate_Set(value); + break; + + default: + result = RT_EOK; + } + return result; +} + +static rt_size_t sound_write(rt_device_t dev, rt_off_t pos, + const void *buffer, rt_size_t size) +{ + int result = RT_EOK; + struct sound_device *snd = (struct sound_device *)dev; + + result = rt_data_node_write(snd->node_list, (void *)buffer, size); + + return result; +} + +static rt_err_t sound_close(rt_device_t dev) +{ + HAL_SAI_DMAStop(&SAI1A_Handler); + LOG_I("Close Sound Device!"); + + return RT_EOK; +} + +int rt_hw_sound_hw_init(char *i2c_bus_name) +{ + int result = RT_EOK; + + if (sound != RT_NULL) + return RT_EOK; + + HAL_SAI_MspInit(NULL); + sound = rt_malloc(sizeof(struct sound_device)); + if (sound == RT_NULL) + { + LOG_E("malloc memory for sound device failed!"); + result = -RT_ENOMEM; + goto __exit; + } + memset(sound, 0, sizeof(struct sound_device)); + + sound->i2c_device = rt_i2c_bus_device_find(i2c_bus_name); + if (sound->i2c_device == RT_NULL) + { + LOG_E("i2c bus device %s not found!", i2c_bus_name); + result = -RT_ENOSYS; + goto __exit; + } + + sound->send_fifo = rt_malloc(AUDIO_SEND_BUFFER_SIZE); + if (sound->send_fifo == RT_NULL) + { + result = -RT_ENOMEM; + goto __exit; + } + memset(sound->send_fifo, 0, AUDIO_SEND_BUFFER_SIZE); + + rt_data_node_init(&sound->node_list, 10); + sound->node_list->read_complete = data_node_read_complete; + sound->node_list->user_data = sound; + + sound->parent.type = RT_Device_Class_Sound; + sound->parent.init = sound_init; + sound->parent.open = sound_open; + sound->parent.control = sound_control; + sound->parent.write = sound_write; + sound->parent.read = RT_NULL; + sound->parent.close = sound_close; + sound->parent.user_data = sound; + + /* register the device */ + rt_device_register(&sound->parent, "sound", RT_DEVICE_FLAG_WRONLY | RT_DEVICE_FLAG_DMA_TX); + rt_device_init(&sound->parent); + + return RT_EOK; + +__exit: + if (sound->send_fifo != RT_NULL) + { + rt_free(sound->send_fifo); + sound->send_fifo = RT_NULL; + } + + if (sound != RT_NULL) + { + rt_free(sound); + sound = RT_NULL; + } + + return result; +} + +extern int rt_hw_micphone_init(char *i2c_bus_name); + +int rt_hw_audio_init(char *i2c_bus_name) +{ + rt_hw_sound_hw_init(i2c_bus_name); + rt_hw_micphone_init(i2c_bus_name); + + return RT_EOK; +} diff --git a/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.c b/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.c new file mode 100644 index 00000000000..196a5b2107a --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.c @@ -0,0 +1,733 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + */ + +#include +#include + +#include "drv_wm8978.h" + + +/* Register Definitions */ +#define REG_SOFTWARE_RESET ((uint16_t)0) +#define REG_POWER_MANAGEMENT1 ((uint16_t)(1 << 9)) +#define REG_POWER_MANAGEMENT2 ((uint16_t)(2 << 9)) +#define REG_POWER_MANAGEMENT3 ((uint16_t)(3 << 9)) +#define REG_AUDIO_INTERFACE ((uint16_t)(4 << 9)) +#define REG_COMPANDING ((uint16_t)(5 << 9)) +#define REG_CLOCK_GEN ((uint16_t)(6 << 9)) +#define REG_ADDITIONAL ((uint16_t)(7 << 9)) +#define REG_GPIO ((uint16_t)(8 << 9)) +#define REG_JACK_DETECT1 ((uint16_t)(9 << 9)) +#define REG_DAC ((uint16_t)(10 << 9)) +#define REG_LEFT_DAC_VOL ((uint16_t)(11 << 9)) +#define REG_RIGHT_DAC_VOL ((uint16_t)(12 << 9)) +#define REG_JACK_DETECT2 ((uint16_t)(13 << 9)) +#define REG_ADC ((uint16_t)(14 << 9)) +#define REG_LEFT_ADC_VOL ((uint16_t)(15 << 9)) +#define REG_RIGHT_ADC_VOL ((uint16_t)(16 << 9)) +#define REG_EQ1 ((uint16_t)(18 << 9)) +#define REG_EQ2 ((uint16_t)(19 << 9)) +#define REG_EQ3 ((uint16_t)(20 << 9)) +#define REG_EQ4 ((uint16_t)(21 << 9)) +#define REG_EQ5 ((uint16_t)(22 << 9)) +#define REG_DAC_LIMITER1 ((uint16_t)(24 << 9)) +#define REG_DAC_LIMITER2 ((uint16_t)(25 << 9)) +#define REG_NOTCH_FILTER1 ((uint16_t)(27 << 9)) +#define REG_NOTCH_FILTER2 ((uint16_t)(28 << 9)) +#define REG_NOTCH_FILTER3 ((uint16_t)(29 << 9)) +#define REG_NOTCH_FILTER4 ((uint16_t)(30 << 9)) +#define REG_ALC1 ((uint16_t)(32 << 9)) +#define REG_ALC2 ((uint16_t)(33 << 9)) +#define REG_ALC3 ((uint16_t)(34 << 9)) +#define REG_NOISE_GATE ((uint16_t)(35 << 9)) +#define REG_PLL_N ((uint16_t)(36 << 9)) +#define REG_PLL_K1 ((uint16_t)(37 << 9)) +#define REG_PLL_K2 ((uint16_t)(38 << 9)) +#define REG_PLL_K3 ((uint16_t)(39 << 9)) +#define REG_3D ((uint16_t)(41 << 9)) +#define REG_BEEP ((uint16_t)(43 << 9)) +#define REG_INPUT ((uint16_t)(44 << 9)) +#define REG_LEFT_PGA_GAIN ((uint16_t)(45 << 9)) +#define REG_RIGHT_PGA_GAIN ((uint16_t)(46 << 9)) +#define REG_LEFT_ADC_BOOST ((uint16_t)(47 << 9)) +#define REG_RIGHT_ADC_BOOST ((uint16_t)(48 << 9)) +#define REG_OUTPUT ((uint16_t)(49 << 9)) +#define REG_LEFT_MIXER ((uint16_t)(50 << 9)) +#define REG_RIGHT_MIXER ((uint16_t)(51 << 9)) +#define REG_LOUT1_VOL ((uint16_t)(52 << 9)) +#define REG_ROUT1_VOL ((uint16_t)(53 << 9)) +#define REG_LOUT2_VOL ((uint16_t)(54 << 9)) +#define REG_ROUT2_VOL ((uint16_t)(55 << 9)) +#define REG_OUT3_MIXER ((uint16_t)(56 << 9)) +#define REG_OUT4_MIXER ((uint16_t)(57 << 9)) + +// R01 REG_POWER_MANAGEMENT1 +#define BUFDCOPEN (1 << 8) +#define OUT4MIXEN (1 << 7) +#define OUT3MIXEN (1 << 6) +#define PLLEN (1 << 5) +#define MICBEN (1 << 4) +#define BIASEN (1 << 3) +#define BUFIOEN (1 << 2) +#define VMIDSEL_OFF (0) +#define VMIDSEL_75K (1) +#define VMIDSEL_300K (2) +#define VMIDSEL_5K (3) + +// R02 REG_POWER_MANAGEMENT2 +#define ROUT1EN (1 << 8) +#define LOUT1EN (1 << 7) +#define SLEEP (1 << 6) +#define BOOSTENR (1 << 5) +#define BOOSTENL (1 << 4) +#define INPPGAENR (1 << 3) +#define INPPGAENL (1 << 2) +#define ADCENR (1 << 1) +#define ADCENL (1) + +// R03 REG_POWER_MANAGEMENT3 +#define OUT4EN (1 << 8) +#define OUT3EN (1 << 7) +#define LOUT2EN (1 << 6) +#define ROUT2EN (1 << 5) +#define RMIXEN (1 << 3) +#define LMIXEN (1 << 2) +#define DACENR (1 << 1) +#define DACENL (1) + +// R04 REG_AUDIO_INTERFACE +#define BCP_NORMAL (0) +#define BCP_INVERTED (1 << 8) +#define LRP_NORMAL (0) +#define LRP_INVERTED (1 << 7) +#define WL_16BITS (0) +#define WL_20BITS (1 << 5) +#define WL_24BITS (2 << 5) // Default value +#define WL_32BITS (3 << 5) +#define FMT_RIGHT_JUSTIFIED (0) +#define FMT_LEFT_JUSTIFIED (1 << 3) +#define FMT_I2S (2 << 3) // Default value +#define FMT_PCM (3 << 3) +#define DACLRSWAP (1 << 2) +#define ADCLRSWAP (1 << 1) +#define MONO (1) + +// R05 REG_COMPANDING +#define WL8 (1 << 5) +#define DAC_COMP_OFF (0) // Default value +#define DAC_COMP_ULAW (2 << 3) +#define DAC_COMP_ALAW (3 << 3) +#define ADC_COMP_OFF (0) // Default value +#define ADC_COMP_ULAW (2 << 1) +#define ADC_COMP_ALAW (3 << 1) +#define LOOPBACK (1) + +// R06 REG_CLOCK_GEN +#define CLKSEL_MCLK (0) +#define CLKSEL_PLL (1 << 8) // Default value +#define MCLK_DIV1 (0) +#define MCLK_DIV1_5 (1 << 5) +#define MCLK_DIV2 (2 << 5) // Default value +#define MCLK_DIV3 (3 << 5) +#define MCLK_DIV4 (4 << 5) +#define MCLK_DIV6 (5 << 5) +#define MCLK_DIV8 (6 << 5) +#define MCLK_DIV12 (7 << 5) +#define BCLK_DIV1 (0) // Default value +#define BCLK_DIV2 (1 << 2) +#define BCLK_DIV4 (2 << 2) +#define BCLK_DIV8 (3 << 2) +#define BCLK_DIV16 (4 << 2) +#define BCLK_DIV32 (5 << 2) +#define MS (1) + +// R07 REG_ADDITIONAL +#define WM_SR_48KHZ (0) // Default value +#define WM_SR_32KHZ (1 << 1) +#define WM_SR_24KHZ (2 << 1) +#define WM_SR_16KHZ (3 << 1) +#define WM_SR_12KHZ (4 << 1) +#define WM_SR_8KHZ (5 << 1) +#define SLOWCLKEN (1) + +// R08 REG_GPIO +#define OPCLK_DIV1 (0) // Default value +#define OPCLK_DIV2 (1 << 4) +#define OPCLK_DIV3 (2 << 4) +#define OPCLK_DIV4 (3 << 4) +#define GPIO1POL_NONINVERTED (0) // Default value +#define GPIO1POL_INVERTED (1 << 3) +#define GPIO1SEL_INPUT (0) // Default value +#define GPIO1SEL_TEMP_OK (2) +#define GPIO1SEL_AMUTE_ACTIVE (3) +#define GPIO1SEL_PLL_CLK_OP (4) +#define GPIO1SEL_PLL_LOCK (5) +#define GPIO1SEL_LOGIC1 (6) +#define GPIO1SEL_LOGIC0 (7) + +// R09 REG_JACK_DETECT1 +#define JD_VMID_EN1 (1 << 8) +#define JD_VMID_EN0 (1 << 7) +#define JD_EN (1 << 6) +#define JD_SEL_GPIO1 (0 << 4) // Default value +#define JD_SEL_GPIO2 (1 << 4) +#define JD_SEL_GPIO3 (2 << 4) + +// R10 REG_DAC +#define SOFTMUTE (1 << 6) +#define DACOSR128 (1 << 3) +#define AMUTE (1 << 2) +#define DACPOLR (1 << 1) +#define DACPOLL (1) + +// R11 & R12 REG_LEFT_DAC_VOL & REG_RIGHT_DAC_VOL +#define DACVU (1 << 8) +#define DACVOL_POS (0) +#define DACVOL_MASK (0xFF) + +// R13 REG_JACK_DETECT2 +#define JD_OUT4_EN1 (1 << 7) +#define JD_OUT3_EN1 (1 << 6) +#define JD_OUT2_EN1 (1 << 5) +#define JD_OUT1_EN1 (1 << 4) +#define JD_OUT4_EN0 (1 << 3) +#define JD_OUT3_EN0 (1 << 2) +#define JD_OUT2_EN0 (1 << 1) +#define JD_OUT1_EN0 (1) + +// R14 REG_ADC +#define HPFEN (1 << 8) +#define HPFAPP (1 << 7) +#define HPFCUT_POS (4) +#define HPFCUT_MASK (7) +#define HPFCUT_0 (0) +#define HPFCUT_1 (1 << 4) +#define HPFCUT_2 (2 << 4) +#define HPFCUT_3 (3 << 4) +#define HPFCUT_4 (4 << 4) +#define HPFCUT_5 (5 << 4) +#define HPFCUT_6 (6 << 4) +#define HPFCUT_7 (7 << 4) +#define ADCOSR128 (1 << 3) +#define ADCRPOL (1 << 1) +#define ADCLPOL (1) + +// R15 & R16 REG_LEFT_ADC_VOL & REG_RIGHT_ADC_VOL +#define ADCVU (1 << 8) +#define ADCVOL_POS (0) +#define ADCVOL_MASK (0xFF) + +// R18 REG_EQ1 +#define EQ3DMODE_ADC (0) +#define EQ3DMODE_DAC (1 << 8) // Default value +#define EQ1C_80HZ (0) +#define EQ1C_105HZ (1 << 5) // Default value +#define EQ1C_135HZ (2 << 5) +#define EQ1C_175HZ (3 << 5) + +// R19 REG_EQ2 +#define EQ2BW_NARROW (0) // Default value +#define EQ2BW_WIDE (1 << 8) +#define EQ2C_230HZ (0) +#define EQ2C_300HZ (1 << 5) // Default value +#define EQ2C_385HZ (2 << 5) +#define EQ2C_500HZ (3 << 5) + +// R20 REG_EQ3 +#define EQ3BW_NARROW (0) // Default value +#define EQ3BW_WIDE (1 << 8) +#define EQ3C_650HZ (0) +#define EQ3C_850HZ (1 << 5) // Default value +#define EQ3C_1_1KHZ (2 << 5) +#define EQ3C_1_4KHZ (3 << 5) + +// R21 REG_EQ4 +#define EQ4BW_NARROW (0) // Default value +#define EQ4BW_WIDE (1 << 8) +#define EQ4C_1_8KHZ (0) +#define EQ4C_2_4KHZ (1 << 5) // Default value +#define EQ4C_3_2KHZ (2 << 5) +#define EQ4C_4_1KHZ (3 << 5) + +// R22 REG_EQ5 +#define EQ5C_5_3KHZ (0) +#define EQ5C_6_9KHZ (1 << 5) // Default value +#define EQ5C_9KHZ (2 << 5) +#define EQ5C_11_7KHZ (3 << 5) + +// R18 - R22 +#define EQC_POS (5) +#define EQC_MASK (3) +#define EQG_POS (0) +#define EQG_MASK (31) + +// R24 REG_DAC_LIMITER1 +#define LIMEN (1 << 8) +#define LIMDCY_POS (4) +#define LIMDCY_MASK (15) +#define LIMDCY_750US (0) +#define LIMDCY_1_5MS (1 << 4) +#define LIMDCY_3MS (2 << 4) +#define LIMDCY_6MS (3 << 4) // Default value +#define LIMDCY_12MS (4 << 4) +#define LIMDCY_24MS (5 << 4) +#define LIMDCY_48MS (6 << 4) +#define LIMDCY_96MS (7 << 4) +#define LIMDCY_192MS (8 << 4) +#define LIMDCY_384MS (9 << 4) +#define LIMDCY_768MS (10 << 4) +#define LIMATK_POS (0) +#define LIMATK_MASK (15) +#define LIMATK_94US (0) +#define LIMATK_188US (1) +#define LIMATK_375US (2) // Default value +#define LIMATK_750US (3) +#define LIMATK_1_5MS (4) +#define LIMATK_3MS (5) +#define LIMATK_6MS (6) +#define LIMATK_12MS (7) +#define LIMATK_24MS (8) +#define LIMATK_48MS (9) +#define LIMATK_96MS (10) +#define LIMATK_192MS (11) + +// R25 REG_DAC_LIMITER2 +#define LIMLVL_POS (4) +#define LIMLVL_MASK (7) +#define LIMLVL_N1DB (0) // Default value +#define LIMLVL_N2DB (1 << 4) +#define LIMLVL_N3DB (2 << 4) +#define LIMLVL_N4DB (3 << 4) +#define LIMLVL_N5DB (4 << 4) +#define LIMLVL_N6DB (5 << 4) +#define LIMBOOST_POS (0) +#define LIMBOOST_MASK (15) +#define LIMBOOST_0DB (0) +#define LIMBOOST_1DB (1) +#define LIMBOOST_2DB (2) +#define LIMBOOST_3DB (3) +#define LIMBOOST_4DB (4) +#define LIMBOOST_5DB (5) +#define LIMBOOST_6DB (6) +#define LIMBOOST_7DB (7) +#define LIMBOOST_8DB (8) +#define LIMBOOST_9DB (9) +#define LIMBOOST_10DB (10) +#define LIMBOOST_11DB (11) +#define LIMBOOST_12DB (12) + +// R27 - R30 REG_NOTCH_FILTER1 - REG_NOTCH_FILTER4 +#define NFU (1 << 8) +#define NFEN (1 << 7) +#define NFA_POS (0) +#define NFA_MASK (127) + +// R32 REG_ALC1 +#define ALCSEL_OFF (0) // Default value +#define ALCSEL_RIGHT_ONLY (1 << 7) +#define ALCSEL_LEFT_ONLY (2 << 7) +#define ALCSEL_BOTH_ON (3 << 7) +#define ALCMAXGAIN_POS (3) +#define ALCMAXGAIN_MASK (7) +#define ALCMAXGAIN_N6_75DB (0) +#define ALCMAXGAIN_N0_75DB (1 << 3) +#define ALCMAXGAIN_5_25DB (2 << 3) +#define ALCMAXGAIN_11_25DB (3 << 3) +#define ALCMAXGAIN_17_25DB (4 << 3) +#define ALCMAXGAIN_23_25DB (5 << 3) +#define ALCMAXGAIN_29_25DB (6 << 3) +#define ALCMAXGAIN_35_25DB (7 << 3) // Default value +#define ALCMINGAIN_POS (0) +#define ALCMINGAIN_MASK (7) +#define ALCMINGAIN_N12DB (0) // Default value +#define ALCMINGAIN_N6DB (1) +#define ALCMINGAIN_0DB (2) +#define ALCMINGAIN_6DB (3) +#define ALCMINGAIN_12DB (4) +#define ALCMINGAIN_18DB (5) +#define ALCMINGAIN_24DB (6) +#define ALCMINGAIN_30DB (7) + +// R33 REG_ALC2 +#define ALCHLD_POS (4) +#define ALCHLD_MASK (15) +#define ALCHLD_0MS (0) // Default value +#define ALCHLD_2_67MS (1 << 4) +#define ALCHLD_5_33MS (2 << 4) +#define ALCHLD_10_67MS (3 << 4) +#define ALCHLD_21_33MS (4 << 4) +#define ALCHLD_42_67MS (5 << 4) +#define ALCHLD_85_33MS (6 << 4) +#define ALCHLD_170_67MS (7 << 4) +#define ALCHLD_341_33MS (8 << 4) +#define ALCHLD_682_67MS (9 << 4) +#define ALCHLD_1_36S (10 << 4) +#define ALCLVL_POS (0) +#define ALCLVL_MASK (15) +#define ALCLVL_N22_5DBFS (0) +#define ALCLVL_N21DBFS (1) +#define ALCLVL_N19_5DBFS (2) +#define ALCLVL_N18DBFS (3) +#define ALCLVL_N16_5DBFS (4) +#define ALCLVL_N15DBFS (5) +#define ALCLVL_N13_5DBFS (6) +#define ALCLVL_N12DBFS (7) +#define ALCLVL_N10_5DBFS (8) +#define ALCLVL_N9DBFS (9) +#define ALCLVL_N7_5DBFS (10) +#define ALCLVL_N6DBFS (11) // Default value +#define ALCLVL_N4_5DBFS (12) +#define ALCLVL_N3DBFS (13) +#define ALCLVL_N1_5DBFS (14) + +// R34 REG_ALC3 +#define ALCMODE_ALC (0) // Default value +#define ALCMODE_LIMITER (1 << 8) +#define ALCDCY_POS (4) +#define ALCDCY_MASK (15) +#define ALCDCY_0 (0) +#define ALCDCY_1 (1 << 4) +#define ALCDCY_2 (2 << 4) +#define ALCDCY_3 (3 << 4) // Default value +#define ALCDCY_4 (4 << 4) +#define ALCDCY_5 (5 << 4) +#define ALCDCY_6 (6 << 4) +#define ALCDCY_7 (7 << 4) +#define ALCDCY_8 (8 << 4) +#define ALCDCY_9 (9 << 4) +#define ALCDCY_10 (10 << 4) +#define ALCATK_POS (0) +#define ALCATK_MASK (15) +#define ALCATK_0 (0) +#define ALCATK_1 (1) +#define ALCATK_2 (2) // Default value +#define ALCATK_3 (3) +#define ALCATK_4 (4) +#define ALCATK_5 (5) +#define ALCATK_6 (6) +#define ALCATK_7 (7) +#define ALCATK_8 (8) +#define ALCATK_9 (9) +#define ALCATK_10 (10) + +// R35 REG_NOISE_GATE +#define NGEN (1 << 3) +#define NGTH_POS (0) +#define NGTH_MASK (7) +#define NGTH_N39DB (0) // Default value +#define NGTH_N45DB (1) +#define NGTH_N51DB (2) +#define NGTH_N57DB (3) +#define NGTH_N63DB (4) +#define NGTH_N69DB (5) +#define NGTH_N75DB (6) +#define NGTH_N81DB (7) + +// R36 REG_PLL_N +#define PLLPRESCALE (1 << 4) +#define PLLN_POS (0) +#define PLLN_MASK (15) + +// R37 - R39 REG_PLL_K1 - REG_PLL_K3 +#define PLLK1_POS (0) +#define PLLK1_MASK (63) +#define PLLK2_POS (0) +#define PLLK2_MASK (511) +#define PLLK3_POS (0) +#define PLLK3_MASK (511) + +// R41 REG_3D +#define DEPTH3D_POS (0) +#define DEPTH3D_MASK (15) +#define DEPTH3D_0 (0) // Default value +#define DEPTH3D_6_67 (1) +#define DEPTH3D_13_33 (2) +#define DEPTH3D_20 (3) +#define DEPTH3D_26_67 (4) +#define DEPTH3D_33_33 (5) +#define DEPTH3D_40 (6) +#define DEPTH3D_46_67 (7) +#define DEPTH3D_53_33 (8) +#define DEPTH3D_60 (9) +#define DEPTH3D_66_67 (10) +#define DEPTH3D_73_33 (11) +#define DEPTH3D_80 (12) +#define DEPTH3D_86_67 (13) +#define DEPTH3D_93_33 (14) +#define DEPTH3D_100 (15) + +// R43 REG_BEEP +#define MUTERPGA2INV (1 << 5) +#define INVROUT2 (1 << 4) +#define BEEPVOL_POS (1) +#define BEEPVOL_MASK (7) +#define BEEPVOL_N15DB (0) +#define BEEPVOL_N12DB (1 << 1) +#define BEEPVOL_N9DB (2 << 1) +#define BEEPVOL_N6DB (3 << 1) +#define BEEPVOL_N3DB (4 << 1) +#define BEEPVOL_0DB (5 << 1) +#define BEEPVOL_3DB (6 << 1) +#define BEEPVOL_6DB (7 << 1) +#define BEEPEN (1) + +// R44 REG_INPUT +#define MBVSEL_0_9AVDD (0) // Default value +#define MBVSEL_0_65AVDD (1 << 8) +#define R2_2INPVGA (1 << 6) +#define RIN2INPVGA (1 << 5) // Default value +#define RIP2INPVGA (1 << 4) // Default value +#define L2_2INPVGA (1 << 2) +#define LIN2INPVGA (1 << 1) // Default value +#define LIP2INPVGA (1) // Default value + +// R45 REG_LEFT_PGA_GAIN +#define INPPGAUPDATE (1 << 8) +#define INPPGAZCL (1 << 7) +#define INPPGAMUTEL (1 << 6) + +// R46 REG_RIGHT_PGA_GAIN +#define INPPGAZCR (1 << 7) +#define INPPGAMUTER (1 << 6) + +// R45 - R46 +#define INPPGAVOL_POS (0) +#define INPPGAVOL_MASK (63) + +// R47 REG_LEFT_ADC_BOOST +#define PGABOOSTL (1 << 8) // Default value +#define L2_2BOOSTVOL_POS (4) +#define L2_2BOOSTVOL_MASK (7) +#define L2_2BOOSTVOL_DISABLED (0) // Default value +#define L2_2BOOSTVOL_N12DB (1 << 4) +#define L2_2BOOSTVOL_N9DB (2 << 4) +#define L2_2BOOSTVOL_N6DB (3 << 4) +#define L2_2BOOSTVOL_N3DB (4 << 4) +#define L2_2BOOSTVOL_0DB (5 << 4) +#define L2_2BOOSTVOL_3DB (6 << 4) +#define L2_2BOOSTVOL_6DB (7 << 4) +#define AUXL2BOOSTVOL_POS (0) +#define AUXL2BOOSTVOL_MASK (7) +#define AUXL2BOOSTVOL_DISABLED (0) // Default value +#define AUXL2BOOSTVOL_N12DB (1) +#define AUXL2BOOSTVOL_N9DB (2) +#define AUXL2BOOSTVOL_N6DB (3) +#define AUXL2BOOSTVOL_N3DB (4) +#define AUXL2BOOSTVOL_0DB (5) +#define AUXL2BOOSTVOL_3DB (6) +#define AUXL2BOOSTVOL_6DB (7) + +// R48 REG_RIGHT_ADC_BOOST +#define PGABOOSTR (1 << 8) // Default value +#define R2_2BOOSTVOL_POS (4) +#define R2_2BOOSTVOL_MASK (7) +#define R2_2BOOSTVOL_DISABLED (0) // Default value +#define R2_2BOOSTVOL_N12DB (1 << 4) +#define R2_2BOOSTVOL_N9DB (2 << 4) +#define R2_2BOOSTVOL_N6DB (3 << 4) +#define R2_2BOOSTVOL_N3DB (4 << 4) +#define R2_2BOOSTVOL_0DB (5 << 4) +#define R2_2BOOSTVOL_3DB (6 << 4) +#define R2_2BOOSTVOL_6DB (7 << 4) +#define AUXR2BOOSTVOL_POS (0) +#define AUXR2BOOSTVOL_MASK (7) +#define AUXR2BOOSTVOL_DISABLED (0) // Default value +#define AUXR2BOOSTVOL_N12DB (1) +#define AUXR2BOOSTVOL_N9DB (2) +#define AUXR2BOOSTVOL_N6DB (3) +#define AUXR2BOOSTVOL_N3DB (4) +#define AUXR2BOOSTVOL_0DB (5) +#define AUXR2BOOSTVOL_3DB (6) +#define AUXR2BOOSTVOL_6DB (7) + +// R49 REG_OUTPUT +#define DACL2RMIX (1 << 6) +#define DACR2LMIX (1 << 5) +#define OUT4BOOST (1 << 4) +#define OUT3BOOST (1 << 3) +#define SPKBOOST (1 << 2) +#define TSDEN (1 << 1) +#define VROI (1) + +// R50 REG_LEFT_MIXER +#define AUXLMIXVOL_POS (6) +#define AUXLMIXVOL_MASK (7) +#define AUXLMIXVOL_N15DB (0) // Default value +#define AUXLMIXVOL_N12DB (1 << 6) +#define AUXLMIXVOL_N9DB (2 << 6) +#define AUXLMIXVOL_N6DB (3 << 6) +#define AUXLMIXVOL_N3DB (4 << 6) +#define AUXLMIXVOL_0DB (5 << 6) +#define AUXLMIXVOL_3DB (6 << 6) +#define AUXLMIXVOL_6DB (7 << 6) +#define AUXL2LMIX (1 << 5) +#define BYPLMIXVOL_POS (2) +#define BYPLMIXVOL_MASK (7) +#define BYPLMIXVOL_N15DB (0) // Default value +#define BYPLMIXVOL_N12DB (1 << 2) +#define BYPLMIXVOL_N9DB (2 << 2) +#define BYPLMIXVOL_N6DB (3 << 2) +#define BYPLMIXVOL_N3DB (4 << 2) +#define BYPLMIXVOL_0DB (5 << 2) +#define BYPLMIXVOL_3DB (6 << 2) +#define BYPLMIXVOL_6DB (7 << 2) +#define BYPL2LMIX (1 << 1) +#define DACL2LMIX (1) + +// R51 REG_RIGHT_MIXER +#define AUXRMIXVOL_POS (6) +#define AUXRMIXVOL_MASK (7) +#define AUXRMIXVOL_N15DB (0) // Default value +#define AUXRMIXVOL_N12DB (1 << 6) +#define AUXRMIXVOL_N9DB (2 << 6) +#define AUXRMIXVOL_N6DB (3 << 6) +#define AUXRMIXVOL_N3DB (4 << 6) +#define AUXRMIXVOL_0DB (5 << 6) +#define AUXRMIXVOL_3DB (6 << 6) +#define AUXRMIXVOL_6DB (7 << 6) +#define AUXR2RMIX (1 << 5) +#define BYPRMIXVOL_POS (2) +#define BYPRMIXVOL_MASK (7) +#define BYPRMIXVOL_N15DB (0) // Default value +#define BYPRMIXVOL_N12DB (1 << 2) +#define BYPRMIXVOL_N9DB (2 << 2) +#define BYPRMIXVOL_N6DB (3 << 2) +#define BYPRMIXVOL_N3DB (4 << 2) +#define BYPRMIXVOL_0DB (5 << 2) +#define BYPRMIXVOL_3DB (6 << 2) +#define BYPRMIXVOL_6DB (7 << 2) +#define BYPR2RMIX (1 << 1) +#define DACR2RMIX (1) + +// R52 - R55 REG_LOUT1_VOL - REG_ROUT2_VOL +#define HPVU (1 << 8) +#define SPKVU (1 << 8) +#define LOUT1ZC (1 << 7) +#define LOUT1MUTE (1 << 6) +#define ROUT1ZC (1 << 7) +#define ROUT1MUTE (1 << 6) +#define LOUT2ZC (1 << 7) +#define LOUT2MUTE (1 << 6) +#define ROUT2ZC (1 << 7) +#define ROUT2MUTE (1 << 6) +#define VOL_POS (0) +#define VOL_MASK (63) + +// R56 REG_OUT3_MIXER +#define OUT3MUTE (1 << 6) +#define OUT4_2OUT3 (1 << 3) +#define BYPL2OUT3 (1 << 2) +#define LMIX2OUT3 (1 << 1) +#define LDAC2OUT3 (1) + +// R57 REG_OUT4_MIXER +#define OUT4MUTE (1 << 6) +#define HALFSIG (1 << 5) +#define LMIX2OUT4 (1 << 4) +#define LDAC2OUT4 (1 << 3) +#define BYPR2OUT4 (1 << 2) +#define RMIX2OUT4 (1 << 1) +#define RDAC2OUT4 (1) + +static void write_reg(struct rt_i2c_bus_device *dev, rt_uint16_t s_data) +{ + struct rt_i2c_msg msg; + rt_uint8_t send_buffer[2]; + RT_ASSERT(dev != RT_NULL); + send_buffer[0] = (rt_uint8_t)(s_data >> 8); + send_buffer[1] = (rt_uint8_t)(s_data); + msg.addr = 0x1A; + msg.flags = RT_I2C_WR; + msg.len = 2; + msg.buf = send_buffer; + rt_i2c_transfer(dev, &msg, 1); +} + +/** + * @brief Init WM8978 Codec device. + * @param dev: I2C device handle + * @retval RT_EOK if correct communication, else wrong communication + */ +int wm8978_init(struct rt_i2c_bus_device *dev) +{ + write_reg(dev, REG_SOFTWARE_RESET); + + /* 1.5x boost power up sequence,Mute all outputs. */ + write_reg(dev, REG_LOUT1_VOL | LOUT1MUTE); + write_reg(dev, REG_ROUT1_VOL | ROUT1MUTE); + write_reg(dev, REG_LOUT2_VOL | LOUT2MUTE); + write_reg(dev, REG_ROUT2_VOL | ROUT2MUTE); + + /* Enable unused output chosen from L/ROUT2, OUT3 or OUT4. */ + write_reg(dev, REG_POWER_MANAGEMENT3 | OUT4EN); + /* Set BUFDCOPEN=1 and BUFIOEN=1 in register R1 */ + write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN); + /* Set SPKBOOST=1 in register R49. */ + write_reg(dev, REG_OUTPUT | SPKBOOST); + /* Set VMIDSEL[1:0] to required value in register R1. */ + write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K); + /* Set L/RMIXEN=1 and DACENL/R=1 in register R3.*/ + write_reg(dev, REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR); + /* Set BIASEN=1 in register R1. */ + write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K); + /* Set L/ROUT2EN=1 in register R3. */ + write_reg(dev, REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR | LOUT2EN | ROUT2EN); + /* Enable other mixers as required. */ + /* Enable other outputs as required. */ + write_reg(dev, REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR); + write_reg(dev, REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR | ADCENL | ADCENR); + + /* Digital inferface setup. */ + write_reg(dev, REG_AUDIO_INTERFACE | BCP_NORMAL | LRP_NORMAL | WL_16BITS | FMT_I2S); + + write_reg(dev, REG_ADDITIONAL | WM_SR_8KHZ); + + write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | MICBEN | BIASEN); + write_reg(dev, REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1); + + /* Enable DAC 128x oversampling. */ + write_reg(dev, REG_DAC | DACOSR128); + + /* Set LOUT2/ROUT2 in BTL operation. */ + write_reg(dev, REG_BEEP | INVROUT2); + + /* MIC config. */ + write_reg(dev, REG_INPUT | MBVSEL_0_65AVDD | RIN2INPVGA | RIP2INPVGA | LIN2INPVGA | LIP2INPVGA); + + /* MIC PGA -12db to 35.25db, 0.75setp default: 16(0db). */ + write_reg(dev, REG_LEFT_PGA_GAIN | INPPGAZCL | (36 & INPPGAVOL_MASK)); + write_reg(dev, REG_RIGHT_PGA_GAIN | INPPGAZCR | (36 & INPPGAVOL_MASK) | INPPGAUPDATE); + + write_reg(dev, REG_LEFT_ADC_BOOST | PGABOOSTL | L2_2BOOSTVOL_DISABLED | AUXL2BOOSTVOL_DISABLED); + write_reg(dev, REG_RIGHT_ADC_BOOST | PGABOOSTR | R2_2BOOSTVOL_DISABLED | AUXR2BOOSTVOL_DISABLED); + + /* Set output volume. */ + wm8978_set_volume(dev, 55); + + return RT_EOK; +} + +/** + * @brief Set WM8978 DAC volume level. + * @param dev: I2C device handle + * @param vol: volume level(0 ~ 99) + * @retval RT_EOK if correct communication, else wrong communication + */ +int wm8978_set_volume(struct rt_i2c_bus_device *dev, int vol) +{ + vol = 63 * vol / 100; + vol = (vol & VOL_MASK) << VOL_POS; + write_reg(dev, REG_LOUT1_VOL | vol); + write_reg(dev, REG_ROUT1_VOL | HPVU | vol); + write_reg(dev, REG_LOUT2_VOL | vol); + write_reg(dev, REG_ROUT2_VOL | SPKVU | vol); + + return RT_EOK; +} diff --git a/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.h b/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.h new file mode 100644 index 00000000000..483fea38fc5 --- /dev/null +++ b/bsp/stm32f429-apollo/drivers/audio/drv_wm8978.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + */ +#ifndef __DRV_WM8978_H__ +#define __DRV_WM8978_H__ + +#include +#include + +int wm8978_init(struct rt_i2c_bus_device *dev); +int wm8978_set_volume(struct rt_i2c_bus_device *dev, int vol); + +#endif diff --git a/bsp/stm32f429-apollo/drivers/drv_gpio.c b/bsp/stm32f429-apollo/drivers/drv_gpio.c index 6f7edddffaf..60170561507 100644 --- a/bsp/stm32f429-apollo/drivers/drv_gpio.c +++ b/bsp/stm32f429-apollo/drivers/drv_gpio.c @@ -1757,17 +1757,19 @@ rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, index->rcc(); /* Configure GPIO_InitStructure */ GPIO_InitStruct.Pin = index->pin; - GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; switch (pin_irq_hdr_tab[irqindex].mode) { case PIN_IRQ_MODE_RISING: + GPIO_InitStruct.Pull = GPIO_PULLDOWN; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; break; case PIN_IRQ_MODE_FALLING: + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; break; case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; break; } diff --git a/bsp/stm32f429-apollo/drivers/drv_spi.c b/bsp/stm32f429-apollo/drivers/drv_spi.c index 578b6e3c665..530b59b4378 100644 --- a/bsp/stm32f429-apollo/drivers/drv_spi.c +++ b/bsp/stm32f429-apollo/drivers/drv_spi.c @@ -539,7 +539,7 @@ struct stm32f4_spi stm32f4_spi5 = static struct rt_spi_bus spi5_bus; - +#ifdef SPI_USE_DMA /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -558,6 +558,7 @@ void DMA2_Stream4_IRQHandler(void) { HAL_DMA_IRQHandler(stm32f4_spi5.spi_handle.hdmatx); } +#endif /* SPI_USE_DMA */ #endif diff --git a/bsp/stm32f429-apollo/drivers/stm32f4xx_hal_conf.h b/bsp/stm32f429-apollo/drivers/stm32f4xx_hal_conf.h index a7633ed68a2..06c1599e2a1 100644 --- a/bsp/stm32f429-apollo/drivers/stm32f4xx_hal_conf.h +++ b/bsp/stm32f429-apollo/drivers/stm32f4xx_hal_conf.h @@ -71,7 +71,7 @@ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_RNG_MODULE_ENABLED */ #define HAL_RTC_MODULE_ENABLED /* */ -/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SAI_MODULE_ENABLED /* */ #define HAL_SD_MODULE_ENABLED /* */ #define HAL_SPI_MODULE_ENABLED /* #define HAL_TIM_MODULE_ENABLED */ diff --git a/bsp/stm32f429-apollo/drivers/usart.c b/bsp/stm32f429-apollo/drivers/usart.c index ecca8b73072..5ed0100dc3e 100644 --- a/bsp/stm32f429-apollo/drivers/usart.c +++ b/bsp/stm32f429-apollo/drivers/usart.c @@ -185,8 +185,9 @@ static int stm32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; - while((__HAL_UART_GET_FLAG(&uart->UartHandle, UART_FLAG_TXE) == RESET)); + __HAL_UART_CLEAR_FLAG(&(uart->UartHandle), UART_FLAG_TC); uart->UartHandle.Instance->DR = c; + while (__HAL_UART_GET_FLAG(&(uart->UartHandle), UART_FLAG_TC) == RESET); return 1; } diff --git a/bsp/stm32f429-apollo/rtconfig.h b/bsp/stm32f429-apollo/rtconfig.h index 4de160fe177..9c28c2c959a 100644 --- a/bsp/stm32f429-apollo/rtconfig.h +++ b/bsp/stm32f429-apollo/rtconfig.h @@ -90,6 +90,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_MTD_NAND diff --git a/bsp/stm32f429-armfly/.config b/bsp/stm32f429-armfly/.config index be7abc5df7f..b001018a9fc 100644 --- a/bsp/stm32f429-armfly/.config +++ b/bsp/stm32f429-armfly/.config @@ -134,6 +134,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/stm32f429-armfly/drivers/usart.c b/bsp/stm32f429-armfly/drivers/usart.c index ecca8b73072..5ed0100dc3e 100644 --- a/bsp/stm32f429-armfly/drivers/usart.c +++ b/bsp/stm32f429-armfly/drivers/usart.c @@ -185,8 +185,9 @@ static int stm32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; - while((__HAL_UART_GET_FLAG(&uart->UartHandle, UART_FLAG_TXE) == RESET)); + __HAL_UART_CLEAR_FLAG(&(uart->UartHandle), UART_FLAG_TC); uart->UartHandle.Instance->DR = c; + while (__HAL_UART_GET_FLAG(&(uart->UartHandle), UART_FLAG_TC) == RESET); return 1; } diff --git a/bsp/stm32f429-armfly/rtconfig.h b/bsp/stm32f429-armfly/rtconfig.h index 0f302ccee4d..b570ea5234c 100644 --- a/bsp/stm32f429-armfly/rtconfig.h +++ b/bsp/stm32f429-armfly/rtconfig.h @@ -92,6 +92,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN diff --git a/bsp/stm32f429-disco/.config b/bsp/stm32f429-disco/.config index a2d11a94c33..1a51abcea17 100644 --- a/bsp/stm32f429-disco/.config +++ b/bsp/stm32f429-disco/.config @@ -114,6 +114,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/stm32f429-disco/drivers/drv_lcd.c b/bsp/stm32f429-disco/drivers/drv_lcd.c index 6612f60928b..0b14234f8a5 100644 --- a/bsp/stm32f429-disco/drivers/drv_lcd.c +++ b/bsp/stm32f429-disco/drivers/drv_lcd.c @@ -919,8 +919,6 @@ FINSH_FUNCTION_EXPORT(lcd_blit_line, draw blit line in lcd display); static int rt_hw_lcd_init(void) { - _lcd_low_level_init(); - static struct rt_device lcd_device; static struct rt_device_graphic_ops ili9341_ops = @@ -932,6 +930,8 @@ static int rt_hw_lcd_init(void) ili9341_lcd_blit_line }; + _lcd_low_level_init(); + /* register lcd device */ lcd_device.type = RT_Device_Class_Graphic; lcd_device.init = lcd_init; diff --git a/bsp/stm32f429-disco/drivers/drv_touch.c b/bsp/stm32f429-disco/drivers/drv_touch.c index ea60c858c5d..8559b69f985 100644 --- a/bsp/stm32f429-disco/drivers/drv_touch.c +++ b/bsp/stm32f429-disco/drivers/drv_touch.c @@ -67,7 +67,10 @@ static int32_t touch_read (uint8_t reg, uint8_t *val) static int32_t touch_write(uint8_t reg, uint8_t val) { struct rt_i2c_msg msgs; - rt_uint8_t buf[2] = {reg, val}; + rt_uint8_t buf[2]; + + buf[0] = reg; + buf[1] = val; msgs.addr = TSC_I2C_ADDR; msgs.flags = RT_I2C_WR; diff --git a/bsp/stm32f429-disco/drivers/usart.c b/bsp/stm32f429-disco/drivers/usart.c index f7ba2ed277e..7509cbf64c3 100644 --- a/bsp/stm32f429-disco/drivers/usart.c +++ b/bsp/stm32f429-disco/drivers/usart.c @@ -185,8 +185,9 @@ static int stm32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; - while((__HAL_UART_GET_FLAG(&uart->UartHandle, UART_FLAG_TXE) == RESET)); + __HAL_UART_CLEAR_FLAG(&(uart->UartHandle), UART_FLAG_TC); uart->UartHandle.Instance->DR = c; + while (__HAL_UART_GET_FLAG(&(uart->UartHandle), UART_FLAG_TC) == RESET); return 1; } diff --git a/bsp/stm32f429-disco/rtconfig.h b/bsp/stm32f429-disco/rtconfig.h index 962f62bc558..91dd49c8722 100644 --- a/bsp/stm32f429-disco/rtconfig.h +++ b/bsp/stm32f429-disco/rtconfig.h @@ -75,6 +75,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN diff --git a/bsp/stm32f4xx-HAL/.config b/bsp/stm32f4xx-HAL/.config index 8be1f1789fd..210efe60dcc 100644 --- a/bsp/stm32f4xx-HAL/.config +++ b/bsp/stm32f4xx-HAL/.config @@ -88,6 +88,7 @@ CONFIG_FINSH_USING_MSH_ONLY=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_I2C is not set diff --git a/bsp/stm32f4xx-HAL/drivers/drv_gpio.c b/bsp/stm32f4xx-HAL/drivers/drv_gpio.c index f000da5ede9..61717b733f2 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_gpio.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_gpio.c @@ -1757,17 +1757,19 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, drv_clock_enable(gpio_pin); /* Configure GPIO_InitStructure */ GPIO_InitStruct.Pin = get_st_pin(gpio_pin); - GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; switch (pin_irq_hdr_tab[irqindex].mode) { case PIN_IRQ_MODE_RISING: + GPIO_InitStruct.Pull = GPIO_PULLDOWN; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; break; case PIN_IRQ_MODE_FALLING: + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; break; case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; break; } diff --git a/bsp/stm32f4xx-HAL/drivers/drv_usart.c b/bsp/stm32f4xx-HAL/drivers/drv_usart.c index db3321ab349..083cdfc39bc 100644 --- a/bsp/stm32f4xx-HAL/drivers/drv_usart.c +++ b/bsp/stm32f4xx-HAL/drivers/drv_usart.c @@ -122,8 +122,9 @@ static int drv_putc(struct rt_serial_device *serial, char c) struct drv_uart *uart; RT_ASSERT(serial != RT_NULL); uart = (struct drv_uart *)serial->parent.user_data; - while ((__HAL_UART_GET_FLAG(&uart->UartHandle, UART_FLAG_TXE) == RESET)); + __HAL_UART_CLEAR_FLAG(&(uart->UartHandle), UART_FLAG_TC); uart->UartHandle.Instance->DR = c; + while (__HAL_UART_GET_FLAG(&(uart->UartHandle), UART_FLAG_TC) == RESET); return 1; } diff --git a/bsp/stm32f4xx-HAL/rtconfig.h b/bsp/stm32f4xx-HAL/rtconfig.h index 8fe06d171c6..e490ee1f318 100644 --- a/bsp/stm32f4xx-HAL/rtconfig.h +++ b/bsp/stm32f4xx-HAL/rtconfig.h @@ -80,6 +80,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_I2C is not set */ diff --git a/bsp/stm32f4xx-HAL/stm32_rom.ld b/bsp/stm32f4xx-HAL/stm32_rom.ld index aa9c9b2af28..58851b43a22 100644 --- a/bsp/stm32f4xx-HAL/stm32_rom.ld +++ b/bsp/stm32f4xx-HAL/stm32_rom.ld @@ -80,6 +80,7 @@ SECTIONS .stack : { + _sstack = .; . = . + _system_stack_size; . = ALIGN(4); _estack = .; diff --git a/bsp/stm32f7-disco/.config b/bsp/stm32f7-disco/.config index 36452791a8b..9cdfcfa368b 100644 --- a/bsp/stm32f7-disco/.config +++ b/bsp/stm32f7-disco/.config @@ -92,6 +92,7 @@ CONFIG_FINSH_USING_MSH_DEFAULT=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/stm32f7-disco/drivers/drv_usart.c b/bsp/stm32f7-disco/drivers/drv_usart.c index 5d54d6903b6..f64f89e378b 100644 --- a/bsp/stm32f7-disco/drivers/drv_usart.c +++ b/bsp/stm32f7-disco/drivers/drv_usart.c @@ -106,8 +106,9 @@ static int drv_putc(struct rt_serial_device *serial, char c) struct drv_uart *uart; RT_ASSERT(serial != RT_NULL); uart = (struct drv_uart *)serial->parent.user_data; - while ((__HAL_UART_GET_FLAG(&uart->UartHandle, UART_FLAG_TXE) == RESET)); + __HAL_UART_CLEAR_IT(&(uart->UartHandle), UART_CLEAR_TCF); uart->UartHandle.Instance->TDR = c; + while (__HAL_UART_GET_FLAG(&(uart->UartHandle), UART_FLAG_TC) == RESET); return 1; } diff --git a/bsp/stm32f7-disco/rtconfig.h b/bsp/stm32f7-disco/rtconfig.h index abbe9d6f598..5d0a04aad74 100644 --- a/bsp/stm32f7-disco/rtconfig.h +++ b/bsp/stm32f7-disco/rtconfig.h @@ -70,6 +70,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using USB */ diff --git a/bsp/stm32h743-nucleo/.config b/bsp/stm32h743-nucleo/.config index bb13ccfc661..1576a11eff9 100644 --- a/bsp/stm32h743-nucleo/.config +++ b/bsp/stm32h743-nucleo/.config @@ -116,6 +116,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/stm32h743-nucleo/drivers/board.h b/bsp/stm32h743-nucleo/drivers/board.h index da8f6d155b7..e7ae774c860 100644 --- a/bsp/stm32h743-nucleo/drivers/board.h +++ b/bsp/stm32h743-nucleo/drivers/board.h @@ -33,16 +33,8 @@ #define EXT_SDRAM_END (EXT_SDRAM_BEGIN + EXT_SDRAM_SIZE) // -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) -#endif + +#define HEAP_BEGIN 0x24000000 // Internal SRAM memory size[Kbytes] <8-64> // Default: 64 diff --git a/bsp/stm32h743-nucleo/drivers/drv_usart.c b/bsp/stm32h743-nucleo/drivers/drv_usart.c index e8620b65eee..7ab3c61ccfc 100644 --- a/bsp/stm32h743-nucleo/drivers/drv_usart.c +++ b/bsp/stm32h743-nucleo/drivers/drv_usart.c @@ -30,6 +30,22 @@ #define USART1_RX_GPIO_PORT GPIOB #define USART1_RX_AF GPIO_AF7_USART1 +/* Definition for USART3 clock resources */ +#define USART3_CLK_ENABLE() __USART3_CLK_ENABLE() +#define USART3_RX_GPIO_CLK_ENABLE() __GPIOD_CLK_ENABLE() +#define USART3_TX_GPIO_CLK_ENABLE() __GPIOD_CLK_ENABLE() + +#define USART3_FORCE_RESET() __USART3_FORCE_RESET() +#define USART3_RELEASE_RESET() __USART3_RELEASE_RESET() + +/* Definition for USARTx Pins */ +#define USART3_TX_PIN GPIO_PIN_8 +#define USART3_TX_GPIO_PORT GPIOD +#define USART3_TX_AF GPIO_AF7_USART3 +#define USART3_RX_PIN GPIO_PIN_9 +#define USART3_RX_GPIO_PORT GPIOD +#define USART3_RX_AF GPIO_AF7_USART3 + /* STM32 uart driver */ struct stm32_uart { @@ -138,8 +154,9 @@ static int stm32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; - while (!(uart->UartHandle.Instance->ISR & UART_FLAG_TXE)); + __HAL_UART_CLEAR_FLAG(&(uart->UartHandle), UART_FLAG_TC); uart->UartHandle.Instance->TDR = c; + while (__HAL_UART_GET_FLAG(&(uart->UartHandle), UART_FLAG_TC) == RESET); return 1; } @@ -194,8 +211,33 @@ void USART1_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* RT_USING_UART1 */ +#endif /* RT_USING_UART3 */ +#if defined(RT_USING_UART3) +/* UART1 device driver structure */ + +static struct stm32_uart uart3; +struct rt_serial_device serial3; + +void USART3_IRQHandler(void) +{ + struct stm32_uart *uart; + + uart = &uart3; + + /* enter interrupt */ + rt_interrupt_enter(); + /* UART in mode Receiver ---------------------------------------------------*/ + if ((__HAL_UART_GET_IT(&uart->UartHandle, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(&uart->UartHandle, UART_IT_RXNE) != RESET)) + { + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(&uart->UartHandle, UART_RXDATA_FLUSH_REQUEST); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* RT_USING_UART3 */ /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example: @@ -232,6 +274,31 @@ void HAL_UART_MspInit(UART_HandleTypeDef *huart) /* NVIC for USART */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 1); HAL_NVIC_EnableIRQ(USART1_IRQn); + } + if (huart->Instance == USART3) + { + /* Enable GPIO TX/RX clock */ + USART3_TX_GPIO_CLK_ENABLE(); + USART3_RX_GPIO_CLK_ENABLE(); + /* Enable USARTx clock */ + USART3_CLK_ENABLE(); + + /* UART TX GPIO pin configuration */ + GPIO_InitStruct.Pin = USART3_TX_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = USART3_TX_AF; + HAL_GPIO_Init(USART3_TX_GPIO_PORT, &GPIO_InitStruct); + + /* UART RX GPIO pin configuration */ + GPIO_InitStruct.Pin = USART3_RX_PIN; + GPIO_InitStruct.Alternate = USART3_RX_AF; + HAL_GPIO_Init(USART3_RX_GPIO_PORT, &GPIO_InitStruct); + + /* NVIC for USART */ + HAL_NVIC_SetPriority(USART3_IRQn, 0, 1); + HAL_NVIC_EnableIRQ(USART3_IRQn); } } @@ -259,6 +326,21 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /* Disable the NVIC for UART */ HAL_NVIC_DisableIRQ(USART1_IRQn); + } + if (huart->Instance == USART3) + { + /* Reset peripherals */ + USART3_FORCE_RESET(); + USART3_RELEASE_RESET(); + + /* Disable peripherals and GPIO Clocks */ + /* Configure UART Tx as alternate function */ + HAL_GPIO_DeInit(USART3_TX_GPIO_PORT, USART3_TX_PIN); + /* Configure UART Rx as alternate function */ + HAL_GPIO_DeInit(USART3_RX_GPIO_PORT, USART3_RX_PIN); + + /* Disable the NVIC for UART */ + HAL_NVIC_DisableIRQ(USART3_IRQn); } } @@ -279,7 +361,18 @@ int stm32_hw_usart_init(void) RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* RT_USING_UART1 */ +#ifdef RT_USING_UART3 + uart = &uart3; + uart->UartHandle.Instance = USART3; + serial3.ops = &stm32_uart_ops; + serial3.config = config; + + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* RT_USING_UART3 */ return 0; } INIT_BOARD_EXPORT(stm32_hw_usart_init); diff --git a/bsp/stm32h743-nucleo/project.uvoptx b/bsp/stm32h743-nucleo/project.uvoptx index c1307fe873f..6f039361881 100644 --- a/bsp/stm32h743-nucleo/project.uvoptx +++ b/bsp/stm32h743-nucleo/project.uvoptx @@ -8,7 +8,7 @@ *.c *.s*; *.src; *.a* - *.obj + *.obj; *.o *.lib *.txt; *.h; *.inc *.plm @@ -28,7 +28,7 @@ 12000000 - 0 + 1 1 0 1 @@ -73,11 +73,11 @@ 0 - 0 + 1 0 1 - 0 + 18 0 1 @@ -101,6 +101,8 @@ 0 0 1 + 0 + 0 5 @@ -115,6 +117,11 @@ STLink\ST-LINKIII-KEIL_SWO.dll + + 0 + ST-LINKIII-KEIL_SWO + -U -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM) + 0 UL2CM3 @@ -160,8 +167,13 @@ + + + + 1 + 0 0 2 10000000 @@ -170,8 +182,8 @@ - Drivers - 0 + Applications + 1 0 0 0 @@ -182,8 +194,8 @@ 0 0 0 - drivers/board.c - board.c + applications\main.c + main.c 0 0 @@ -194,88 +206,64 @@ 0 0 0 - drivers/drv_led.c - drv_led.c + applications\sram.c + sram.c 0 0 + + + + Drivers + 1 + 0 + 0 + 0 - 1 + 2 3 1 0 0 0 - drivers/drv_mpu.c - drv_mpu.c + drivers\board.c + board.c 0 0 - 1 + 2 4 1 0 0 0 - drivers/drv_usart.c - drv_usart.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - drivers/lan8742a.c - lan8742a.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - drivers/stm32h7xx_it.c + drivers\stm32h7xx_it.c stm32h7xx_it.c 0 0 - - - - Applications - 0 - 0 - 0 - 0 2 - 7 + 5 1 0 0 0 - applications/main.c - main.c + drivers\drv_mpu.c + drv_mpu.c 0 0 2 - 8 + 6 1 0 0 0 - applications/sram.c - sram.c + drivers\drv_usart.c + drv_usart.c 0 0 @@ -283,30 +271,30 @@ CMSIS - 0 + 1 0 0 0 3 - 9 + 7 1 0 0 0 - Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c + Libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c system_stm32h7xx.c 0 0 3 - 10 + 8 2 0 0 0 - Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s + Libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\arm\startup_stm32h743xx.s startup_stm32h743xx.s 0 0 @@ -321,924 +309,924 @@ 0 4 - 11 + 9 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c stm32h7xx_hal.c 0 0 4 - 12 + 10 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc.c stm32h7xx_hal_adc.c 0 0 4 - 13 + 11 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc_ex.c stm32h7xx_hal_adc_ex.c 0 0 4 - 14 + 12 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cec.c stm32h7xx_hal_cec.c 0 0 4 - 15 + 13 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_comp.c stm32h7xx_hal_comp.c 0 0 4 - 16 + 14 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c stm32h7xx_hal_cortex.c 0 0 4 - 17 + 15 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc.c stm32h7xx_hal_crc.c 0 0 4 - 18 + 16 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc_ex.c stm32h7xx_hal_crc_ex.c 0 0 4 - 19 + 17 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp.c stm32h7xx_hal_cryp.c 0 0 4 - 20 + 18 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp_ex.c stm32h7xx_hal_cryp_ex.c 0 0 4 - 21 + 19 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac.c stm32h7xx_hal_dac.c 0 0 4 - 22 + 20 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac_ex.c stm32h7xx_hal_dac_ex.c 0 0 4 - 23 + 21 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dcmi.c stm32h7xx_hal_dcmi.c 0 0 4 - 24 + 22 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dfsdm.c stm32h7xx_hal_dfsdm.c 0 0 4 - 25 + 23 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c stm32h7xx_hal_dma.c 0 0 4 - 26 + 24 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma2d.c stm32h7xx_hal_dma2d.c 0 0 4 - 27 + 25 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c stm32h7xx_hal_dma_ex.c 0 0 4 - 28 + 26 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth.c stm32h7xx_hal_eth.c 0 0 4 - 29 + 27 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth_ex.c stm32h7xx_hal_eth_ex.c 0 0 4 - 30 + 28 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c stm32h7xx_hal_fdcan.c 0 0 4 - 31 + 29 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c stm32h7xx_hal_flash.c 0 0 4 - 32 + 30 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c stm32h7xx_hal_flash_ex.c 0 0 4 - 33 + 31 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c stm32h7xx_hal_gpio.c 0 0 4 - 34 + 32 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash.c stm32h7xx_hal_hash.c 0 0 4 - 35 + 33 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash_ex.c stm32h7xx_hal_hash_ex.c 0 0 4 - 36 + 34 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hcd.c stm32h7xx_hal_hcd.c 0 0 4 - 37 + 35 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hrtim.c stm32h7xx_hal_hrtim.c 0 0 4 - 38 + 36 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c stm32h7xx_hal_hsem.c 0 0 4 - 39 + 37 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c stm32h7xx_hal_i2c.c 0 0 4 - 40 + 38 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c stm32h7xx_hal_i2c_ex.c 0 0 4 - 41 + 39 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s.c stm32h7xx_hal_i2s.c 0 0 4 - 42 + 40 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s_ex.c stm32h7xx_hal_i2s_ex.c 0 0 4 - 43 + 41 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_irda.c stm32h7xx_hal_irda.c 0 0 4 - 44 + 42 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_iwdg.c stm32h7xx_hal_iwdg.c 0 0 4 - 45 + 43 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_jpeg.c stm32h7xx_hal_jpeg.c 0 0 4 - 46 + 44 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_lptim.c stm32h7xx_hal_lptim.c 0 0 4 - 47 + 45 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc.c stm32h7xx_hal_ltdc.c 0 0 4 - 48 + 46 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdios.c stm32h7xx_hal_mdios.c 0 0 4 - 49 + 47 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c stm32h7xx_hal_mdma.c 0 0 4 - 50 + 48 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc.c stm32h7xx_hal_mmc.c 0 0 4 - 51 + 49 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc_ex.c stm32h7xx_hal_mmc_ex.c 0 0 4 - 52 + 50 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nand.c stm32h7xx_hal_nand.c 0 0 4 - 53 + 51 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nor.c stm32h7xx_hal_nor.c 0 0 4 - 54 + 52 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp.c stm32h7xx_hal_opamp.c 0 0 4 - 55 + 53 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp_ex.c stm32h7xx_hal_opamp_ex.c 0 0 4 - 56 + 54 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c stm32h7xx_hal_pcd.c 0 0 4 - 57 + 55 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c stm32h7xx_hal_pcd_ex.c 0 0 4 - 58 + 56 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c stm32h7xx_hal_pwr.c 0 0 4 - 59 + 57 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c stm32h7xx_hal_pwr_ex.c 0 0 4 - 60 + 58 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c stm32h7xx_hal_qspi.c 0 0 4 - 61 + 59 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c stm32h7xx_hal_rcc.c 0 0 4 - 62 + 60 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c stm32h7xx_hal_rcc_ex.c 0 0 4 - 63 + 61 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng.c stm32h7xx_hal_rng.c 0 0 4 - 64 + 62 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc.c stm32h7xx_hal_rtc.c 0 0 4 - 65 + 63 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc_ex.c stm32h7xx_hal_rtc_ex.c 0 0 4 - 66 + 64 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai.c stm32h7xx_hal_sai.c 0 0 4 - 67 + 65 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai_ex.c stm32h7xx_hal_sai_ex.c 0 0 4 - 68 + 66 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd.c stm32h7xx_hal_sd.c 0 0 4 - 69 + 67 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd_ex.c stm32h7xx_hal_sd_ex.c 0 0 4 - 70 + 68 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sdram.c stm32h7xx_hal_sdram.c 0 0 4 - 71 + 69 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard.c stm32h7xx_hal_smartcard.c 0 0 4 - 72 + 70 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard_ex.c stm32h7xx_hal_smartcard_ex.c 0 0 4 - 73 + 71 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smbus.c stm32h7xx_hal_smbus.c 0 0 4 - 74 + 72 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spdifrx.c stm32h7xx_hal_spdifrx.c 0 0 4 - 75 + 73 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c stm32h7xx_hal_spi.c 0 0 4 - 76 + 74 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi_ex.c stm32h7xx_hal_spi_ex.c 0 0 4 - 77 + 75 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c stm32h7xx_hal_sram.c 0 0 4 - 78 + 76 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_swpmi.c stm32h7xx_hal_swpmi.c 0 0 4 - 79 + 77 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c stm32h7xx_hal_tim.c 0 0 4 - 80 + 78 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c stm32h7xx_hal_tim_ex.c 0 0 4 - 81 + 79 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c stm32h7xx_hal_uart.c 0 0 4 - 82 + 80 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c stm32h7xx_hal_uart_ex.c 0 0 4 - 83 + 81 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart.c stm32h7xx_hal_usart.c 0 0 4 - 84 + 82 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_wwdg.c stm32h7xx_hal_wwdg.c 0 0 4 - 85 + 83 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_fmc.c stm32h7xx_ll_fmc.c 0 0 4 - 86 + 84 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_sdmmc.c stm32h7xx_ll_sdmmc.c 0 0 4 - 87 + 85 1 0 0 0 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c stm32h7xx_ll_usb.c 0 0 @@ -1253,180 +1241,180 @@ 0 5 - 88 + 86 1 0 0 0 - ../../src/clock.c + ..\..\src\clock.c clock.c 0 0 5 - 89 + 87 1 0 0 0 - ../../src/components.c + ..\..\src\components.c components.c 0 0 5 - 90 + 88 1 0 0 0 - ../../src/device.c - device.c + ..\..\src\cpu.c + cpu.c 0 0 5 - 91 + 89 1 0 0 0 - ../../src/idle.c - idle.c + ..\..\src\device.c + device.c 0 0 5 - 92 + 90 1 0 0 0 - ../../src/ipc.c - ipc.c + ..\..\src\idle.c + idle.c 0 0 5 - 93 + 91 1 0 0 0 - ../../src/irq.c - irq.c + ..\..\src\ipc.c + ipc.c 0 0 5 - 94 + 92 1 0 0 0 - ../../src/kservice.c - kservice.c + ..\..\src\irq.c + irq.c 0 0 5 - 95 + 93 1 0 0 0 - ../../src/mem.c - mem.c + ..\..\src\kservice.c + kservice.c 0 0 5 - 96 + 94 1 0 0 0 - ../../src/memheap.c - memheap.c + ..\..\src\mem.c + mem.c 0 0 5 - 97 + 95 1 0 0 0 - ../../src/mempool.c + ..\..\src\mempool.c mempool.c 0 0 5 - 98 + 96 1 0 0 0 - ../../src/object.c + ..\..\src\object.c object.c 0 0 5 - 99 + 97 1 0 0 0 - ../../src/scheduler.c + ..\..\src\scheduler.c scheduler.c 0 0 5 - 100 + 98 1 0 0 0 - ../../src/signal.c + ..\..\src\signal.c signal.c 0 0 5 - 101 + 99 1 0 0 0 - ../../src/thread.c + ..\..\src\thread.c thread.c 0 0 5 - 102 + 100 1 0 0 0 - ../../src/timer.c + ..\..\src\timer.c timer.c 0 0 @@ -1441,60 +1429,60 @@ 0 6 - 103 + 101 1 0 0 0 - ../../libcpu/arm/cortex-m7/cpuport.c + ..\..\libcpu\arm\cortex-m7\cpuport.c cpuport.c 0 0 6 - 104 + 102 2 0 0 0 - ../../libcpu/arm/cortex-m7/context_rvds.S + ..\..\libcpu\arm\cortex-m7\context_rvds.S context_rvds.S 0 0 6 - 105 + 103 1 0 0 0 - ../../libcpu/arm/common/backtrace.c + ..\..\libcpu\arm\common\backtrace.c backtrace.c 0 0 6 - 106 + 104 1 0 0 0 - ../../libcpu/arm/common/div0.c + ..\..\libcpu\arm\common\div0.c div0.c 0 0 6 - 107 + 105 1 0 0 0 - ../../libcpu/arm/common/showmem.c + ..\..\libcpu\arm\common\showmem.c showmem.c 0 0 @@ -1502,336 +1490,172 @@ - DeviceDrivers + Filesystem 0 0 0 0 7 - 108 - 1 - 0 - 0 - 0 - ../../components/drivers/serial/serial.c - serial.c - 0 - 0 - - - 7 - 109 - 1 - 0 - 0 - 0 - ../../components/drivers/src/completion.c - completion.c - 0 - 0 - - - 7 - 110 + 106 1 0 0 0 - ../../components/drivers/src/dataqueue.c - dataqueue.c + ..\..\components\dfs\src\dfs.c + dfs.c 0 0 7 - 111 + 107 1 0 0 0 - ../../components/drivers/src/pipe.c - pipe.c + ..\..\components\dfs\src\dfs_file.c + dfs_file.c 0 0 7 - 112 + 108 1 0 0 0 - ../../components/drivers/src/ringbuffer.c - ringbuffer.c + ..\..\components\dfs\src\dfs_fs.c + dfs_fs.c 0 0 7 - 113 + 109 1 0 0 0 - ../../components/drivers/src/waitqueue.c - waitqueue.c + ..\..\components\dfs\src\dfs_posix.c + dfs_posix.c 0 0 7 - 114 + 110 1 0 0 0 - ../../components/drivers/src/workqueue.c - workqueue.c + ..\..\components\dfs\filesystems\devfs\devfs.c + devfs.c 0 0 - pthreads + DeviceDrivers 0 0 0 0 8 - 115 - 1 - 0 - 0 - 0 - ../../components/libc/pthreads/mqueue.c - mqueue.c - 0 - 0 - - - 8 - 116 - 1 - 0 - 0 - 0 - ../../components/libc/pthreads/pthread.c - pthread.c - 0 - 0 - - - 8 - 117 - 1 - 0 - 0 - 0 - ../../components/libc/pthreads/pthread_attr.c - pthread_attr.c - 0 - 0 - - - 8 - 118 - 1 - 0 - 0 - 0 - ../../components/libc/pthreads/pthread_barrier.c - pthread_barrier.c - 0 - 0 - - - 8 - 119 - 1 - 0 - 0 - 0 - ../../components/libc/pthreads/pthread_cond.c - pthread_cond.c - 0 - 0 - - - 8 - 120 + 111 1 0 0 0 - ../../components/libc/pthreads/pthread_mutex.c - pthread_mutex.c + ..\..\components\drivers\serial\serial.c + serial.c 0 0 8 - 121 + 112 1 0 0 0 - ../../components/libc/pthreads/pthread_rwlock.c - pthread_rwlock.c + ..\..\components\drivers\src\completion.c + completion.c 0 0 8 - 122 + 113 1 0 0 0 - ../../components/libc/pthreads/pthread_spin.c - pthread_spin.c + ..\..\components\drivers\src\dataqueue.c + dataqueue.c 0 0 8 - 123 + 114 1 0 0 0 - ../../components/libc/pthreads/pthread_tls.c - pthread_tls.c + ..\..\components\drivers\src\pipe.c + pipe.c 0 0 8 - 124 + 115 1 0 0 0 - ../../components/libc/pthreads/sched.c - sched.c + ..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c 0 0 8 - 125 + 116 1 0 0 0 - ../../components/libc/pthreads/semaphore.c - semaphore.c + ..\..\components\drivers\src\ringbuffer.c + ringbuffer.c 0 0 8 - 126 + 117 1 0 0 0 - ../../components/libc/time/clock_time.c - clock_time.c + ..\..\components\drivers\src\waitqueue.c + waitqueue.c 0 0 8 - 127 - 1 - 0 - 0 - 0 - ../../components/libc/time/posix_sleep.c - posix_sleep.c - 0 - 0 - - - - - libc - 0 - 0 - 0 - 0 - - 9 - 128 - 1 - 0 - 0 - 0 - ../../components/libc/compilers/armlibc/libc.c - libc.c - 0 - 0 - - - 9 - 129 - 1 - 0 - 0 - 0 - ../../components/libc/compilers/armlibc/libc_syms.c - libc_syms.c - 0 - 0 - - - 9 - 130 - 1 - 0 - 0 - 0 - ../../components/libc/compilers/armlibc/mem_std.c - mem_std.c - 0 - 0 - - - 9 - 131 - 1 - 0 - 0 - 0 - ../../components/libc/compilers/armlibc/stdio.c - stdio.c - 0 - 0 - - - 9 - 132 - 1 - 0 - 0 - 0 - ../../components/libc/compilers/armlibc/stubs.c - stubs.c - 0 - 0 - - - 9 - 133 + 118 1 0 0 0 - ../../components/libc/compilers/armlibc/time.c - time.c + ..\..\components\drivers\src\workqueue.c + workqueue.c 0 0 @@ -1844,193 +1668,193 @@ 0 0 - 10 - 134 + 9 + 119 1 0 0 0 - ../../components/finsh/shell.c + ..\..\components\finsh\shell.c shell.c 0 0 - 10 - 135 + 9 + 120 1 0 0 0 - ../../components/finsh/symbol.c + ..\..\components\finsh\symbol.c symbol.c 0 0 - 10 - 136 + 9 + 121 1 0 0 0 - ../../components/finsh/cmd.c + ..\..\components\finsh\cmd.c cmd.c 0 0 - 10 - 137 + 9 + 122 1 0 0 0 - ../../components/finsh/msh.c + ..\..\components\finsh\msh.c msh.c 0 0 - 10 - 138 + 9 + 123 1 0 0 0 - ../../components/finsh/msh_cmd.c + ..\..\components\finsh\msh_cmd.c msh_cmd.c 0 0 - 10 - 139 + 9 + 124 1 0 0 0 - ../../components/finsh/msh_file.c + ..\..\components\finsh\msh_file.c msh_file.c 0 0 - 10 - 140 + 9 + 125 1 0 0 0 - ../../components/finsh/finsh_compiler.c + ..\..\components\finsh\finsh_compiler.c finsh_compiler.c 0 0 - 10 - 141 + 9 + 126 1 0 0 0 - ../../components/finsh/finsh_error.c + ..\..\components\finsh\finsh_error.c finsh_error.c 0 0 - 10 - 142 + 9 + 127 1 0 0 0 - ../../components/finsh/finsh_heap.c + ..\..\components\finsh\finsh_heap.c finsh_heap.c 0 0 - 10 - 143 + 9 + 128 1 0 0 0 - ../../components/finsh/finsh_init.c + ..\..\components\finsh\finsh_init.c finsh_init.c 0 0 - 10 - 144 + 9 + 129 1 0 0 0 - ../../components/finsh/finsh_node.c + ..\..\components\finsh\finsh_node.c finsh_node.c 0 0 - 10 - 145 + 9 + 130 1 0 0 0 - ../../components/finsh/finsh_ops.c + ..\..\components\finsh\finsh_ops.c finsh_ops.c 0 0 - 10 - 146 + 9 + 131 1 0 0 0 - ../../components/finsh/finsh_parser.c + ..\..\components\finsh\finsh_parser.c finsh_parser.c 0 0 - 10 - 147 + 9 + 132 1 0 0 0 - ../../components/finsh/finsh_var.c + ..\..\components\finsh\finsh_var.c finsh_var.c 0 0 - 10 - 148 + 9 + 133 1 0 0 0 - ../../components/finsh/finsh_vm.c + ..\..\components\finsh\finsh_vm.c finsh_vm.c 0 0 - 10 - 149 + 9 + 134 1 0 0 0 - ../../components/finsh/finsh_token.c + ..\..\components\finsh\finsh_token.c finsh_token.c 0 0 @@ -2038,428 +1862,80 @@ - LwIP + libc 0 0 0 0 - 11 - 150 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/api_lib.c - api_lib.c - 0 - 0 - - - 11 - 151 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/api_msg.c - api_msg.c - 0 - 0 - - - 11 - 152 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/err.c - err.c - 0 - 0 - - - 11 - 153 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/netbuf.c - netbuf.c - 0 - 0 - - - 11 - 154 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/netdb.c - netdb.c - 0 - 0 - - - 11 - 155 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/netifapi.c - netifapi.c - 0 - 0 - - - 11 - 156 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/sockets.c - sockets.c - 0 - 0 - - - 11 - 157 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/api/tcpip.c - tcpip.c - 0 - 0 - - - 11 - 158 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/arch/sys_arch.c - sys_arch.c - 0 - 0 - - - 11 - 159 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/def.c - def.c - 0 - 0 - - - 11 - 160 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/dhcp.c - dhcp.c - 0 - 0 - - - 11 - 161 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/dns.c - dns.c - 0 - 0 - - - 11 - 162 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/init.c - init.c - 0 - 0 - - - 11 - 163 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/memp.c - memp.c - 0 - 0 - - - 11 - 164 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/netif.c - netif.c - 0 - 0 - - - 11 - 165 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/pbuf.c - pbuf.c - 0 - 0 - - - 11 - 166 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/raw.c - raw.c - 0 - 0 - - - 11 - 167 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/stats.c - stats.c - 0 - 0 - - - 11 - 168 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/sys.c - sys.c - 0 - 0 - - - 11 - 169 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/tcp.c - tcp.c - 0 - 0 - - - 11 - 170 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/tcp_in.c - tcp_in.c - 0 - 0 - - - 11 - 171 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/tcp_out.c - tcp_out.c - 0 - 0 - - - 11 - 172 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/timers.c - timers.c - 0 - 0 - - - 11 - 173 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/udp.c - udp.c - 0 - 0 - - - 11 - 174 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c - autoip.c - 0 - 0 - - - 11 - 175 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c - icmp.c - 0 - 0 - - - 11 - 176 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c - igmp.c - 0 - 0 - - - 11 - 177 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c - inet.c - 0 - 0 - - - 11 - 178 - 1 - 0 - 0 - 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c - inet_chksum.c - 0 - 0 - - - 11 - 179 + 10 + 135 1 0 0 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c - ip.c + ..\..\components\libc\compilers\armlibc\libc.c + libc.c 0 0 - 11 - 180 + 10 + 136 1 0 0 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c - ip_addr.c + ..\..\components\libc\compilers\armlibc\mem_std.c + mem_std.c 0 0 - 11 - 181 + 10 + 137 1 0 0 0 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c - ip_frag.c + ..\..\components\libc\compilers\armlibc\stdio.c + stdio.c 0 0 - 11 - 182 + 10 + 138 1 0 0 0 - ../../components/net/lwip-1.4.1/src/netif/etharp.c - etharp.c + ..\..\components\libc\compilers\armlibc\stubs.c + stubs.c 0 0 - 11 - 183 + 10 + 139 1 0 0 0 - ../../components/net/lwip-1.4.1/src/netif/ethernetif.c - ethernetif.c + ..\..\components\libc\compilers\armlibc\time.c + time.c 0 0 - 11 - 184 + 10 + 140 1 0 0 0 - ../../components/net/lwip-1.4.1/src/netif/slipif.c - slipif.c + ..\..\components\libc\compilers\common\gmtime_r.c + gmtime_r.c 0 0 diff --git a/bsp/stm32h743-nucleo/project.uvprojx b/bsp/stm32h743-nucleo/project.uvprojx index 46506c79160..f34e1cd7467 100644 --- a/bsp/stm32h743-nucleo/project.uvprojx +++ b/bsp/stm32h743-nucleo/project.uvprojx @@ -10,11 +10,13 @@ rt-thread_stm32h7xx 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 STM32H743ZITx STMicroelectronics - Keil.STM32H7xx_DFP.2.0.0 + Keil.STM32H7xx_DFP.2.2.0 http://www.keil.com/pack IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE @@ -52,7 +54,7 @@ 0 0 1 - 1 + 0 .\build\ 1 0 @@ -182,6 +184,7 @@ 0 0 2 + 0 1 0 8 @@ -318,13 +321,14 @@ 1 0 0 - 0 + 2 0 0 1 + 0 0 - 0 - 0 + 3 + 3 1 1 0 @@ -334,7 +338,7 @@ USE_HAL_DRIVER, RT_USING_ARM_LIBC, STM32H743xx - drivers;applications;.;Libraries/CMSIS/Device/ST/STM32H7xx/Include;Libraries/CMSIS/Include;Libraries/STM32H7xx_HAL_Driver/Inc;../../include;../../libcpu/arm/cortex-m7;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/libc/pthreads;../../components/libc/time;../../components/libc/compilers/armlibc;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif + applications;.;drivers;Libraries\CMSIS\Device\ST\STM32H7xx\Include;Libraries\CMSIS\Include;Libraries\STM32H7xx_HAL_Driver\Inc;..\..\include;..\..\libcpu\arm\cortex-m7;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common @@ -368,7 +372,7 @@ - --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) @@ -376,52 +380,42 @@ - Drivers + Applications - board.c - 1 - drivers/board.c - - - drv_led.c - 1 - drivers/drv_led.c - - - drv_mpu.c + main.c 1 - drivers/drv_mpu.c + applications\main.c - drv_usart.c + sram.c 1 - drivers/drv_usart.c + applications\sram.c + + + + Drivers + - lan8742a.c + board.c 1 - drivers/lan8742a.c + drivers\board.c stm32h7xx_it.c 1 - drivers/stm32h7xx_it.c + drivers\stm32h7xx_it.c - - - - Applications - - main.c + drv_mpu.c 1 - applications/main.c + drivers\drv_mpu.c - sram.c + drv_usart.c 1 - applications/sram.c + drivers\drv_usart.c @@ -431,12 +425,12 @@ system_stm32h7xx.c 1 - Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c + Libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c startup_stm32h743xx.s 2 - Libraries/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s + Libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\arm\startup_stm32h743xx.s @@ -446,387 +440,387 @@ stm32h7xx_hal.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c stm32h7xx_hal_adc.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc.c stm32h7xx_hal_adc_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc_ex.c stm32h7xx_hal_cec.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cec.c stm32h7xx_hal_comp.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_comp.c stm32h7xx_hal_cortex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c stm32h7xx_hal_crc.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc.c stm32h7xx_hal_crc_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc_ex.c stm32h7xx_hal_cryp.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp.c stm32h7xx_hal_cryp_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp_ex.c stm32h7xx_hal_dac.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac.c stm32h7xx_hal_dac_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac_ex.c stm32h7xx_hal_dcmi.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dcmi.c stm32h7xx_hal_dfsdm.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dfsdm.c stm32h7xx_hal_dma.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c stm32h7xx_hal_dma2d.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma2d.c stm32h7xx_hal_dma_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c stm32h7xx_hal_eth.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth.c stm32h7xx_hal_eth_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth_ex.c stm32h7xx_hal_fdcan.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c stm32h7xx_hal_flash.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c stm32h7xx_hal_flash_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c stm32h7xx_hal_gpio.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c stm32h7xx_hal_hash.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash.c stm32h7xx_hal_hash_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash_ex.c stm32h7xx_hal_hcd.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hcd.c stm32h7xx_hal_hrtim.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hrtim.c stm32h7xx_hal_hsem.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c stm32h7xx_hal_i2c.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c stm32h7xx_hal_i2c_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c stm32h7xx_hal_i2s.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s.c stm32h7xx_hal_i2s_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s_ex.c stm32h7xx_hal_irda.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_irda.c stm32h7xx_hal_iwdg.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_iwdg.c stm32h7xx_hal_jpeg.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_jpeg.c stm32h7xx_hal_lptim.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_lptim.c stm32h7xx_hal_ltdc.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc.c stm32h7xx_hal_mdios.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdios.c stm32h7xx_hal_mdma.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c stm32h7xx_hal_mmc.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc.c stm32h7xx_hal_mmc_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc_ex.c stm32h7xx_hal_nand.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nand.c stm32h7xx_hal_nor.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nor.c stm32h7xx_hal_opamp.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp.c stm32h7xx_hal_opamp_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp_ex.c stm32h7xx_hal_pcd.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c stm32h7xx_hal_pcd_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c stm32h7xx_hal_pwr.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c stm32h7xx_hal_pwr_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c stm32h7xx_hal_qspi.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c stm32h7xx_hal_rcc.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c stm32h7xx_hal_rcc_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c stm32h7xx_hal_rng.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng.c stm32h7xx_hal_rtc.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc.c stm32h7xx_hal_rtc_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc_ex.c stm32h7xx_hal_sai.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai.c stm32h7xx_hal_sai_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai_ex.c stm32h7xx_hal_sd.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd.c stm32h7xx_hal_sd_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd_ex.c stm32h7xx_hal_sdram.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sdram.c stm32h7xx_hal_smartcard.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard.c stm32h7xx_hal_smartcard_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard_ex.c stm32h7xx_hal_smbus.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smbus.c stm32h7xx_hal_spdifrx.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spdifrx.c stm32h7xx_hal_spi.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c stm32h7xx_hal_spi_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi_ex.c stm32h7xx_hal_sram.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c stm32h7xx_hal_swpmi.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_swpmi.c stm32h7xx_hal_tim.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c stm32h7xx_hal_tim_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c stm32h7xx_hal_uart.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c stm32h7xx_hal_uart_ex.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c stm32h7xx_hal_usart.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart.c stm32h7xx_hal_wwdg.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_wwdg.c stm32h7xx_ll_fmc.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_fmc.c stm32h7xx_ll_sdmmc.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_sdmmc.c stm32h7xx_ll_usb.c 1 - Libraries/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c + Libraries\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c @@ -836,77 +830,77 @@ clock.c 1 - ../../src/clock.c + ..\..\src\clock.c components.c 1 - ../../src/components.c + ..\..\src\components.c + + + cpu.c + 1 + ..\..\src\cpu.c device.c 1 - ../../src/device.c + ..\..\src\device.c idle.c 1 - ../../src/idle.c + ..\..\src\idle.c ipc.c 1 - ../../src/ipc.c + ..\..\src\ipc.c irq.c 1 - ../../src/irq.c + ..\..\src\irq.c kservice.c 1 - ../../src/kservice.c + ..\..\src\kservice.c mem.c 1 - ../../src/mem.c - - - memheap.c - 1 - ../../src/memheap.c + ..\..\src\mem.c mempool.c 1 - ../../src/mempool.c + ..\..\src\mempool.c object.c 1 - ../../src/object.c + ..\..\src\object.c scheduler.c 1 - ../../src/scheduler.c + ..\..\src\scheduler.c signal.c 1 - ../../src/signal.c + ..\..\src\signal.c thread.c 1 - ../../src/thread.c + ..\..\src\thread.c timer.c 1 - ../../src/timer.c + ..\..\src\timer.c @@ -916,172 +910,102 @@ cpuport.c 1 - ../../libcpu/arm/cortex-m7/cpuport.c + ..\..\libcpu\arm\cortex-m7\cpuport.c context_rvds.S 2 - ../../libcpu/arm/cortex-m7/context_rvds.S + ..\..\libcpu\arm\cortex-m7\context_rvds.S backtrace.c 1 - ../../libcpu/arm/common/backtrace.c + ..\..\libcpu\arm\common\backtrace.c div0.c 1 - ../../libcpu/arm/common/div0.c + ..\..\libcpu\arm\common\div0.c showmem.c 1 - ../../libcpu/arm/common/showmem.c + ..\..\libcpu\arm\common\showmem.c - DeviceDrivers + Filesystem - serial.c - 1 - ../../components/drivers/serial/serial.c - - - completion.c - 1 - ../../components/drivers/src/completion.c - - - dataqueue.c + dfs.c 1 - ../../components/drivers/src/dataqueue.c + ..\..\components\dfs\src\dfs.c - pipe.c + dfs_file.c 1 - ../../components/drivers/src/pipe.c + ..\..\components\dfs\src\dfs_file.c - ringbuffer.c + dfs_fs.c 1 - ../../components/drivers/src/ringbuffer.c + ..\..\components\dfs\src\dfs_fs.c - waitqueue.c + dfs_posix.c 1 - ../../components/drivers/src/waitqueue.c + ..\..\components\dfs\src\dfs_posix.c - workqueue.c + devfs.c 1 - ../../components/drivers/src/workqueue.c + ..\..\components\dfs\filesystems\devfs\devfs.c - pthreads + DeviceDrivers - mqueue.c - 1 - ../../components/libc/pthreads/mqueue.c - - - pthread.c - 1 - ../../components/libc/pthreads/pthread.c - - - pthread_attr.c - 1 - ../../components/libc/pthreads/pthread_attr.c - - - pthread_barrier.c - 1 - ../../components/libc/pthreads/pthread_barrier.c - - - pthread_cond.c - 1 - ../../components/libc/pthreads/pthread_cond.c - - - pthread_mutex.c - 1 - ../../components/libc/pthreads/pthread_mutex.c - - - pthread_rwlock.c - 1 - ../../components/libc/pthreads/pthread_rwlock.c - - - pthread_spin.c - 1 - ../../components/libc/pthreads/pthread_spin.c - - - pthread_tls.c - 1 - ../../components/libc/pthreads/pthread_tls.c - - - sched.c - 1 - ../../components/libc/pthreads/sched.c - - - semaphore.c - 1 - ../../components/libc/pthreads/semaphore.c - - - clock_time.c + serial.c 1 - ../../components/libc/time/clock_time.c + ..\..\components\drivers\serial\serial.c - posix_sleep.c + completion.c 1 - ../../components/libc/time/posix_sleep.c + ..\..\components\drivers\src\completion.c - - - - libc - - libc.c + dataqueue.c 1 - ../../components/libc/compilers/armlibc/libc.c + ..\..\components\drivers\src\dataqueue.c - libc_syms.c + pipe.c 1 - ../../components/libc/compilers/armlibc/libc_syms.c + ..\..\components\drivers\src\pipe.c - mem_std.c + ringblk_buf.c 1 - ../../components/libc/compilers/armlibc/mem_std.c + ..\..\components\drivers\src\ringblk_buf.c - stdio.c + ringbuffer.c 1 - ../../components/libc/compilers/armlibc/stdio.c + ..\..\components\drivers\src\ringbuffer.c - stubs.c + waitqueue.c 1 - ../../components/libc/compilers/armlibc/stubs.c + ..\..\components\drivers\src\waitqueue.c - time.c + workqueue.c 1 - ../../components/libc/compilers/armlibc/time.c + ..\..\components\drivers\src\workqueue.c @@ -1091,262 +1015,117 @@ shell.c 1 - ../../components/finsh/shell.c + ..\..\components\finsh\shell.c symbol.c 1 - ../../components/finsh/symbol.c + ..\..\components\finsh\symbol.c cmd.c 1 - ../../components/finsh/cmd.c + ..\..\components\finsh\cmd.c msh.c 1 - ../../components/finsh/msh.c + ..\..\components\finsh\msh.c msh_cmd.c 1 - ../../components/finsh/msh_cmd.c + ..\..\components\finsh\msh_cmd.c msh_file.c 1 - ../../components/finsh/msh_file.c + ..\..\components\finsh\msh_file.c finsh_compiler.c 1 - ../../components/finsh/finsh_compiler.c + ..\..\components\finsh\finsh_compiler.c finsh_error.c 1 - ../../components/finsh/finsh_error.c + ..\..\components\finsh\finsh_error.c finsh_heap.c 1 - ../../components/finsh/finsh_heap.c + ..\..\components\finsh\finsh_heap.c finsh_init.c 1 - ../../components/finsh/finsh_init.c + ..\..\components\finsh\finsh_init.c finsh_node.c 1 - ../../components/finsh/finsh_node.c + ..\..\components\finsh\finsh_node.c finsh_ops.c 1 - ../../components/finsh/finsh_ops.c + ..\..\components\finsh\finsh_ops.c finsh_parser.c 1 - ../../components/finsh/finsh_parser.c + ..\..\components\finsh\finsh_parser.c finsh_var.c 1 - ../../components/finsh/finsh_var.c + ..\..\components\finsh\finsh_var.c finsh_vm.c 1 - ../../components/finsh/finsh_vm.c + ..\..\components\finsh\finsh_vm.c finsh_token.c 1 - ../../components/finsh/finsh_token.c + ..\..\components\finsh\finsh_token.c - LwIP + libc - api_lib.c - 1 - ../../components/net/lwip-1.4.1/src/api/api_lib.c - - - api_msg.c - 1 - ../../components/net/lwip-1.4.1/src/api/api_msg.c - - - err.c - 1 - ../../components/net/lwip-1.4.1/src/api/err.c - - - netbuf.c - 1 - ../../components/net/lwip-1.4.1/src/api/netbuf.c - - - netdb.c - 1 - ../../components/net/lwip-1.4.1/src/api/netdb.c - - - netifapi.c - 1 - ../../components/net/lwip-1.4.1/src/api/netifapi.c - - - sockets.c - 1 - ../../components/net/lwip-1.4.1/src/api/sockets.c - - - tcpip.c - 1 - ../../components/net/lwip-1.4.1/src/api/tcpip.c - - - sys_arch.c - 1 - ../../components/net/lwip-1.4.1/src/arch/sys_arch.c - - - def.c - 1 - ../../components/net/lwip-1.4.1/src/core/def.c - - - dhcp.c - 1 - ../../components/net/lwip-1.4.1/src/core/dhcp.c - - - dns.c - 1 - ../../components/net/lwip-1.4.1/src/core/dns.c - - - init.c - 1 - ../../components/net/lwip-1.4.1/src/core/init.c - - - memp.c - 1 - ../../components/net/lwip-1.4.1/src/core/memp.c - - - netif.c - 1 - ../../components/net/lwip-1.4.1/src/core/netif.c - - - pbuf.c - 1 - ../../components/net/lwip-1.4.1/src/core/pbuf.c - - - raw.c - 1 - ../../components/net/lwip-1.4.1/src/core/raw.c - - - stats.c - 1 - ../../components/net/lwip-1.4.1/src/core/stats.c - - - sys.c - 1 - ../../components/net/lwip-1.4.1/src/core/sys.c - - - tcp.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp.c - - - tcp_in.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp_in.c - - - tcp_out.c - 1 - ../../components/net/lwip-1.4.1/src/core/tcp_out.c - - - timers.c - 1 - ../../components/net/lwip-1.4.1/src/core/timers.c - - - udp.c - 1 - ../../components/net/lwip-1.4.1/src/core/udp.c - - - autoip.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c - - - icmp.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c - - - igmp.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c - - - inet.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c - - - inet_chksum.c - 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c - - - ip.c + libc.c 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c + ..\..\components\libc\compilers\armlibc\libc.c - ip_addr.c + mem_std.c 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c + ..\..\components\libc\compilers\armlibc\mem_std.c - ip_frag.c + stdio.c 1 - ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c + ..\..\components\libc\compilers\armlibc\stdio.c - etharp.c + stubs.c 1 - ../../components/net/lwip-1.4.1/src/netif/etharp.c + ..\..\components\libc\compilers\armlibc\stubs.c - ethernetif.c + time.c 1 - ../../components/net/lwip-1.4.1/src/netif/ethernetif.c + ..\..\components\libc\compilers\armlibc\time.c - slipif.c + gmtime_r.c 1 - ../../components/net/lwip-1.4.1/src/netif/slipif.c + ..\..\components\libc\compilers\common\gmtime_r.c diff --git a/bsp/stm32h743-nucleo/rtconfig.h b/bsp/stm32h743-nucleo/rtconfig.h index e341d043f9e..7f092e5fa73 100644 --- a/bsp/stm32h743-nucleo/rtconfig.h +++ b/bsp/stm32h743-nucleo/rtconfig.h @@ -56,7 +56,7 @@ /* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_CONSOLE_DEVICE_NAME "uart3" /* RT-Thread Components */ @@ -108,6 +108,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/stm32l072/rtconfig.h b/bsp/stm32l072/rtconfig.h index 57be51ea767..5e750f5d1f6 100644 --- a/bsp/stm32l072/rtconfig.h +++ b/bsp/stm32l072/rtconfig.h @@ -66,6 +66,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_HOOK #define RT_USING_CPU_USAGE /* SECTION: Console options */ diff --git a/bsp/stm32l475-iot-disco/drivers/usart.c b/bsp/stm32l475-iot-disco/drivers/usart.c index fa5a68e7cb7..15f52ecedb8 100644 --- a/bsp/stm32l475-iot-disco/drivers/usart.c +++ b/bsp/stm32l475-iot-disco/drivers/usart.c @@ -185,8 +185,9 @@ static int stm32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = (struct stm32_uart *)serial->parent.user_data; - while((__HAL_UART_GET_FLAG(&uart->UartHandle, UART_FLAG_TXE) == RESET)); + __HAL_UART_CLEAR_FLAG(&(uart->UartHandle), UART_FLAG_TC); uart->UartHandle.Instance->TDR = c; + while (__HAL_UART_GET_FLAG(&(uart->UartHandle), UART_FLAG_TC) == RESET); return 1; } diff --git a/bsp/stm32l475-iot-disco/rtconfig.h b/bsp/stm32l475-iot-disco/rtconfig.h index 89428e1cf42..f7b00767d2a 100644 --- a/bsp/stm32l475-iot-disco/rtconfig.h +++ b/bsp/stm32l475-iot-disco/rtconfig.h @@ -61,6 +61,7 @@ #define RT_USING_DEVICE_IPC /* Using serial framework */ #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_UART1 #define RT_USING_UART2 diff --git a/bsp/stm32l476-nucleo/.config b/bsp/stm32l476-nucleo/.config index 44a239f90d3..529d8c5fb0e 100644 --- a/bsp/stm32l476-nucleo/.config +++ b/bsp/stm32l476-nucleo/.config @@ -105,6 +105,7 @@ CONFIG_FINSH_ARG_MAX=10 CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/stm32l476-nucleo/drivers/drv_gpio.c b/bsp/stm32l476-nucleo/drivers/drv_gpio.c index 7ebe789cd6c..be030ffca96 100644 --- a/bsp/stm32l476-nucleo/drivers/drv_gpio.c +++ b/bsp/stm32l476-nucleo/drivers/drv_gpio.c @@ -738,17 +738,19 @@ rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, index->rcc(); /* Configure GPIO_InitStructure */ GPIO_InitStruct.Pin = index->pin; - GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; switch (pin_irq_hdr_tab[irqindex].mode) { case PIN_IRQ_MODE_RISING: + GPIO_InitStruct.Pull = GPIO_PULLDOWN; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; break; case PIN_IRQ_MODE_FALLING: + GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; break; case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; break; } diff --git a/bsp/stm32l476-nucleo/drivers/drv_usart.c b/bsp/stm32l476-nucleo/drivers/drv_usart.c index c5f5e728a3f..a4ec08db077 100644 --- a/bsp/stm32l476-nucleo/drivers/drv_usart.c +++ b/bsp/stm32l476-nucleo/drivers/drv_usart.c @@ -141,8 +141,9 @@ static int drv_putc(struct rt_serial_device *serial, char c) uart = (struct drv_uart *)serial->parent.user_data; - while ((__HAL_UART_GET_FLAG(&uart->UartHandle, UART_FLAG_TXE) == RESET)); + __HAL_UART_CLEAR_FLAG(&(uart->UartHandle), UART_FLAG_TC); uart->UartHandle.Instance->TDR = c; + while (__HAL_UART_GET_FLAG(&(uart->UartHandle), UART_FLAG_TC) == RESET); return 1; } diff --git a/bsp/stm32l476-nucleo/rtconfig.h b/bsp/stm32l476-nucleo/rtconfig.h index 7be9f6b5b68..d1e5fd2e41a 100644 --- a/bsp/stm32l476-nucleo/rtconfig.h +++ b/bsp/stm32l476-nucleo/rtconfig.h @@ -71,6 +71,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* Using USB */ diff --git a/bsp/swm320-lq100/.config b/bsp/swm320-lq100/.config new file mode 100644 index 00000000000..53a718cb817 --- /dev/null +++ b/bsp/swm320-lq100/.config @@ -0,0 +1,377 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x30102 +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +# CONFIG_RT_USING_CAN is not set +CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +CONFIG_SOC_SWM320VET7=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_WDT is not set + +# +# UART Drivers +# +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set + +# +# SPI Drivers +# +# CONFIG_BSP_USING_SPI0 is not set +# CONFIG_BSP_USING_SPI1 is not set + +# +# I2C Drivers +# +# CONFIG_BSP_USING_I2C is not set + +# +# PWM Drivers +# +# CONFIG_BSP_USING_PWM0 is not set +# CONFIG_BSP_USING_PWM1 is not set +# CONFIG_BSP_USING_PWM2 is not set +# CONFIG_BSP_USING_PWM3 is not set + +# +# RTC Drivers +# +# CONFIG_BSP_USING_RTC is not set + +# +# HWtimer Drivers +# +# CONFIG_BSP_USING_HWTIMER0 is not set +# CONFIG_BSP_USING_HWTIMER1 is not set +# CONFIG_BSP_USING_HWTIMER2 is not set +# CONFIG_BSP_USING_HWTIMER3 is not set +# CONFIG_BSP_USING_HWTIMER4 is not set +# CONFIG_BSP_USING_HWTIMER5 is not set + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_EXT_SRAM is not set +# CONFIG_BSP_USING_NOR_FLASH is not set + +# +# Offboard Peripheral Drivers +# diff --git a/bsp/swm320-lq100/Kconfig b/bsp/swm320-lq100/Kconfig new file mode 100644 index 00000000000..5c6ef90e9c2 --- /dev/null +++ b/bsp/swm320-lq100/Kconfig @@ -0,0 +1,25 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_SWM320VET7 + bool + default y + +source "drivers/Kconfig" diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h new file mode 100644 index 00000000000..76aadca4901 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +//extern const q31_t realCoefAQ31[1024]; +//extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h new file mode 100644 index 00000000000..217f1d50e26 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h new file mode 100644 index 00000000000..f06a0713eb8 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h @@ -0,0 +1,7538 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvproj + * + * + * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2014 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY + #elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + + ((q15_t) x * (q15_t) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//SMMLA +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) //Keil + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h new file mode 100644 index 00000000000..5186cb48388 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h @@ -0,0 +1,711 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h new file mode 100644 index 00000000000..17e43984fcf --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h @@ -0,0 +1,822 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h new file mode 100644 index 00000000000..e1357c6735b --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h @@ -0,0 +1,1650 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h new file mode 100644 index 00000000000..bb6be1305d2 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h @@ -0,0 +1,1802 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h new file mode 100644 index 00000000000..242540f8b11 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h @@ -0,0 +1,2221 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 01. September 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000 + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0 + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0 + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0 + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/* Cache Level ID register */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* Cache Type register */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ + +/* Cache Size ID Register */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ + +/* Cache Size Selection Register */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ + +/* Instruction Tightly-Coupled Memory Control Register*/ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Registers */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ + +/* AHBS control register */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## Cache functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) + + +/** \brief Enable I-Cache + + The function turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable I-Cache + + The function turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate I-Cache + + The function invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); + #endif +} + + +/** \brief Enable D-Cache + + The function turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + __DSB(); + + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable D-Cache + + The function turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate D-Cache + + The function invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean D-Cache + + The function cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean & Invalidate D-Cache + + The function cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h new file mode 100644 index 00000000000..01089f1333b --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h new file mode 100644 index 00000000000..d14110b2abd --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h new file mode 100644 index 00000000000..ee58eee56dd --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h new file mode 100644 index 00000000000..79d9baa156d --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h @@ -0,0 +1,2548 @@ +#ifndef __SWM320_H__ +#define __SWM320_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ +typedef enum IRQn +{ + /****** Cortex-M0 Processor Exceptions Numbers **********************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** Cortex-M4 specific Interrupt Numbers ************************************************/ + GPIOA0_IRQn = 0, + GPIOA1_IRQn = 1, + GPIOA2_IRQn = 2, + GPIOA3_IRQn = 3, + GPIOA4_IRQn = 4, + GPIOA5_IRQn = 5, + GPIOA6_IRQn = 6, + GPIOA7_IRQn = 7, + GPIOB0_IRQn = 8, + GPIOB1_IRQn = 9, + GPIOB2_IRQn = 10, + GPIOB3_IRQn = 11, + GPIOB4_IRQn = 12, + GPIOB5_IRQn = 13, + GPIOB6_IRQn = 14, + GPIOB7_IRQn = 15, + GPIOC0_IRQn = 16, + GPIOC1_IRQn = 17, + GPIOC2_IRQn = 18, + GPIOC3_IRQn = 19, + GPIOC4_IRQn = 20, + GPIOC5_IRQn = 21, + GPIOC6_IRQn = 22, + GPIOC7_IRQn = 23, + GPIOM0_IRQn = 24, + GPIOM1_IRQn = 25, + GPIOM2_IRQn = 26, + GPIOM3_IRQn = 27, + GPIOM4_IRQn = 28, + GPIOM5_IRQn = 29, + GPIOM6_IRQn = 30, + GPIOM7_IRQn = 31, + DMA_IRQn = 32, + LCD_IRQn = 33, + NORFLC_IRQn = 34, + CAN_IRQn = 35, + PULSE_IRQn = 36, + WDT_IRQn = 37, + PWM_IRQn = 38, + UART0_IRQn = 39, + UART1_IRQn = 40, + UART2_IRQn = 41, + UART3_IRQn = 42, + UART4_IRQn = 43, + I2C0_IRQn = 44, + I2C1_IRQn = 45, + SPI0_IRQn = 46, + ADC0_IRQn = 47, + RTC_IRQn = 48, + ANAC_IRQn = 49, + SDIO_IRQn = 50, + GPIOA_IRQn = 51, + GPIOB_IRQn = 52, + GPIOC_IRQn = 53, + GPIOM_IRQn = 54, + GPION_IRQn = 55, + GPIOP_IRQn = 56, + ADC1_IRQn = 57, + FPU_IRQn = 58, + SPI1_IRQn = 59, + TIMR0_IRQn = 60, + TIMR1_IRQn = 61, + TIMR2_IRQn = 62, + TIMR3_IRQn = 63, + TIMR4_IRQn = 64, + TIMR5_IRQn = 65, +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< SWM320 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< SWM320 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#if defined(__CC_ARM) + #pragma anon_unions +#endif + +#include +#include "core_cm4.h" /* Cortex-M0 processor and core peripherals */ +#include "system_SWM320.h" + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +typedef struct +{ + __IO uint32_t CLKSEL; //Clock Select + + __IO uint32_t CLKDIV; + + __IO uint32_t CLKEN; //Clock Enable + + __IO uint32_t SLEEP; + + uint32_t RESERVED0[6]; + + __IO uint32_t RTCBKP_ISO; //[0] 1 RTC闁跨喐鏋婚幏鐑芥晸閹归顣幏閿嬬爱闁跨喐鏋婚幏鐑芥晸閼哄倿娼婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓锟� 0 RTC闁跨喐鏋婚幏鐑芥晸閹归顣幏閿嬬爱闁跨喐鏋婚幏椋庡幖闁跨喐鏋婚幏鐑芥晸閿燂拷 + + __IO uint32_t RTCWKEN; //[0] 1 娴ｅ潡鏁撻弬銈嗗RTC闁跨喐鏋婚幏鐑芥晸缁愭牜娅㈤幏鐑芥晸閺傘倖瀚� + + uint32_t RESERVED[52 + 64]; + + __IO uint32_t PAWKEN; //Port A Wakeup Enable + __IO uint32_t PBWKEN; + __IO uint32_t PCWKEN; + + uint32_t RESERVED2[1 + 4]; + + __IO uint32_t PAWKSR; //Port A Wakeup Status Register闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t PBWKSR; + __IO uint32_t PCWKSR; + + uint32_t RESERVED3[64 - 11]; + + __IO uint32_t REMAP; //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风úOM闁跨喐鏋婚幏閿嬪⒔闁跨喐鏋婚幏锟� 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风éLASH闁跨喐鏋婚幏閿嬪⒔闁跨喐鏋婚幏锟� + + __IO uint32_t RSTCR; //Reset Control Register + __IO uint32_t RSTSR; //Reset Status Register + + uint32_t RESERVED4[61 + 64]; + + __IO uint32_t BKP[3]; //闁跨喐鏋婚幏鐑芥晸閹归攱鍞婚幏鐑芥晸閹瑰嘲鐦庢潏鐐闁跨喐鏋婚幏锟� + + //RTC Power Domain: 0x4001E000 + uint32_t RESERVED5[(0x4001E000 - 0x40000508) / 4 - 1]; + + __IO uint32_t RTCBKP[8]; //RTC闁跨喐鏋婚幏閿嬬爱闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閹插瀚归柨鐔稿祹鐎靛嫯鎻幏鐑芥晸閺傘倖瀚� + + __IO uint32_t LRCCR; //Low speed RC Control Register + __IO uint32_t LRCTRIM0; //Low speed RC Trim + __IO uint32_t LRCTRIM1; + + uint32_t RESERVED6; + + __IO uint32_t RTCLDOTRIM; //RTC Power Domain LDO Trim + + //Analog Control: 0x40031000 + uint32_t RESERVED7[(0x40031000 - 0x4001E030) / 4 - 1]; + + __IO uint32_t HRCCR; //High speed RC Control Register + __IO uint32_t HRC20M; //[24:0] High speed RC Trim Value for 20MHz + __IO uint32_t HRC40M; //[24:0] High speed RC Trim Value for 40MHz + + uint32_t RESERVED8[3]; + + __IO uint32_t BGTRIM; + + __IO uint32_t TEMPCR; //闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄珱鐎靛嫯鎻幏鐑芥晸閺傘倖瀚� + + __IO uint32_t XTALCR; + + __IO uint32_t PLLCR; + __IO uint32_t PLLDIV; + __IO uint32_t PLLSET; + __IO uint32_t PLLLOCK; //[0] 1 PLL闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + + __IO uint32_t BODIE; + __IO uint32_t BODIF; + + __IO uint32_t ADC1IN7; + + __IO uint32_t BODCR; +} SYS_TypeDef; + +#define SYS_CLKSEL_LFCK_Pos 0 //Low Frequency Clock Source 0 LRC 1 PLL +#define SYS_CLKSEL_LFCK_Msk (0x01 << SYS_CLKSEL_LFCK_Pos) +#define SYS_CLKSEL_HFCK_Pos 1 //High Frequency Clock Source 0 HRC 1 XTAL +#define SYS_CLKSEL_HFCK_Msk (0x01 << SYS_CLKSEL_HFCK_Pos) +#define SYS_CLKSEL_SYS_Pos 2 //缁崵绮洪弮鍫曟晸閺傘倖瀚归柅澶愭晸閺傘倖瀚� 0 LFCK 1 HFCK +#define SYS_CLKSEL_SYS_Msk (0x01 << SYS_CLKSEL_SYS_Pos) + +#define SYS_CLKDIV_SYS_Pos 0 //缁崵绮洪弮鍫曟晸閹恒儱鍤栭幏鐑筋暥 0 1闁跨喐鏋婚幏鐑筋暥 1 2闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_SYS_Msk (0x01 << SYS_CLKDIV_SYS_Pos) +#define SYS_CLKDIV_PWM_Pos 1 //PWM 閺冨爼鏁撻幒銉ュ殩閹风兘顣� 0 1闁跨喐鏋婚幏鐑筋暥 1 8闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_PWM_Msk (0x01 << SYS_CLKDIV_PWM_Pos) +#define SYS_CLKDIV_SDRAM_Pos 2 //SDRAM閺冨爼鏁撻幒銉ュ殩閹风兘顣� 0 1闁跨喐鏋婚幏鐑筋暥 1 2闁跨喐鏋婚幏鐑筋暥 2 4闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_SDRAM_Msk (0x03 << SYS_CLKDIV_SDRAM_Pos) +#define SYS_CLKDIV_SDIO_Pos 4 //SDIO閺冨爼鏁撻幒銉ュ殩閹风兘顣� 0 1闁跨喐鏋婚幏鐑筋暥 1 2闁跨喐鏋婚幏鐑筋暥 2 4闁跨喐鏋婚幏鐑筋暥 3 8闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_SDIO_Msk (0x03 << SYS_CLKDIV_SDIO_Pos) + +#define SYS_CLKEN_GPIOA_Pos 0 +#define SYS_CLKEN_GPIOA_Msk (0x01 << SYS_CLKEN_GPIOA_Pos) +#define SYS_CLKEN_GPIOB_Pos 1 +#define SYS_CLKEN_GPIOB_Msk (0x01 << SYS_CLKEN_GPIOB_Pos) +#define SYS_CLKEN_GPIOC_Pos 2 +#define SYS_CLKEN_GPIOC_Msk (0x01 << SYS_CLKEN_GPIOC_Pos) +#define SYS_CLKEN_GPIOM_Pos 4 +#define SYS_CLKEN_GPIOM_Msk (0x01 << SYS_CLKEN_GPIOM_Pos) +#define SYS_CLKEN_GPION_Pos 5 +#define SYS_CLKEN_GPION_Msk (0x01 << SYS_CLKEN_GPION_Pos) +#define SYS_CLKEN_TIMR_Pos 6 +#define SYS_CLKEN_TIMR_Msk (0x01 << SYS_CLKEN_TIMR_Pos) +#define SYS_CLKEN_WDT_Pos 7 +#define SYS_CLKEN_WDT_Msk (0x01 << SYS_CLKEN_WDT_Pos) +#define SYS_CLKEN_ADC0_Pos 8 +#define SYS_CLKEN_ADC0_Msk (0x01 << SYS_CLKEN_ADC0_Pos) +#define SYS_CLKEN_PWM_Pos 9 +#define SYS_CLKEN_PWM_Msk (0x01 << SYS_CLKEN_PWM_Pos) +#define SYS_CLKEN_RTC_Pos 10 +#define SYS_CLKEN_RTC_Msk (0x01 << SYS_CLKEN_RTC_Pos) +#define SYS_CLKEN_UART0_Pos 11 +#define SYS_CLKEN_UART0_Msk (0x01 << SYS_CLKEN_UART0_Pos) +#define SYS_CLKEN_UART1_Pos 12 +#define SYS_CLKEN_UART1_Msk (0x01 << SYS_CLKEN_UART1_Pos) +#define SYS_CLKEN_UART2_Pos 13 +#define SYS_CLKEN_UART2_Msk (0x01 << SYS_CLKEN_UART2_Pos) +#define SYS_CLKEN_UART3_Pos 14 +#define SYS_CLKEN_UART3_Msk (0x01 << SYS_CLKEN_UART3_Pos) +#define SYS_CLKEN_UART4_Pos 15 +#define SYS_CLKEN_UART4_Msk (0x01 << SYS_CLKEN_UART4_Pos) +#define SYS_CLKEN_SPI0_Pos 16 +#define SYS_CLKEN_SPI0_Msk (0x01 << SYS_CLKEN_SPI0_Pos) +#define SYS_CLKEN_I2C0_Pos 17 +#define SYS_CLKEN_I2C0_Msk (0x01 << SYS_CLKEN_I2C0_Pos) +#define SYS_CLKEN_I2C1_Pos 18 +#define SYS_CLKEN_I2C1_Msk (0x01 << SYS_CLKEN_I2C1_Pos) +#define SYS_CLKEN_I2C2_Pos 19 +#define SYS_CLKEN_I2C2_Msk (0x01 << SYS_CLKEN_I2C2_Pos) +#define SYS_CLKEN_LCD_Pos 20 +#define SYS_CLKEN_LCD_Msk (0x01 << SYS_CLKEN_LCD_Pos) +#define SYS_CLKEN_GPIOP_Pos 21 +#define SYS_CLKEN_GPIOP_Msk (0x01 << SYS_CLKEN_GPIOP_Pos) +#define SYS_CLKEN_ANAC_Pos 22 //濡繝鏁撻弬銈嗗闁跨喐鏋婚幏鐑筋暥闁跨喓娈曢鈺傚敾閹风兘鏁撶紒鐐垫閹风兘鏁撻敓锟� +#define SYS_CLKEN_ANAC_Msk (0x01 << SYS_CLKEN_ANAC_Pos) +#define SYS_CLKEN_CRC_Pos 23 +#define SYS_CLKEN_CRC_Msk (0x01 << SYS_CLKEN_CRC_Pos) +#define SYS_CLKEN_RTCBKP_Pos 24 +#define SYS_CLKEN_RTCBKP_Msk (0x01 << SYS_CLKEN_RTCBKP_Pos) +#define SYS_CLKEN_CAN_Pos 25 +#define SYS_CLKEN_CAN_Msk (0x01 << SYS_CLKEN_CAN_Pos) +#define SYS_CLKEN_SDRAM_Pos 26 +#define SYS_CLKEN_SDRAM_Msk (0x01 << SYS_CLKEN_SDRAM_Pos) +#define SYS_CLKEN_NORFL_Pos 27 //NOR Flash +#define SYS_CLKEN_NORFL_Msk (0x01 << SYS_CLKEN_NORFL_Pos) +#define SYS_CLKEN_RAMC_Pos 28 +#define SYS_CLKEN_RAMC_Msk (0x01 << SYS_CLKEN_RAMC_Pos) +#define SYS_CLKEN_SDIO_Pos 29 +#define SYS_CLKEN_SDIO_Msk (0x01 << SYS_CLKEN_SDIO_Pos) +#define SYS_CLKEN_ADC1_Pos 30 +#define SYS_CLKEN_ADC1_Msk (0x01 << SYS_CLKEN_ADC1_Pos) +#define SYS_CLKEN_ALIVE_Pos 31 //CHIPALIVE闁跨喐鏋婚幏閿嬬爱闁跨喐鏋婚幏椋庨兇缂佺喐妞傞柨鐔告灮閹疯渹濞囬柨鐔告灮閹凤拷 +#define SYS_CLKEN_ALIVE_Msk (0x01 << SYS_CLKEN_ALIVE_Pos) + +#define SYS_SLEEP_SLEEP_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚�1闁跨喐鏋婚幏椋庨兇缂佺喖鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍LEEP濡€崇础 +#define SYS_SLEEP_SLEEP_Msk (0x01 << SYS_SLEEP_SLEEP_Pos) +#define SYS_SLEEP_DEEP_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚�1闁跨喐鏋婚幏椋庨兇缂佺喖鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍TOP SLEEP濡€崇础 +#define SYS_SLEEP_DEEP_Msk (0x01 << SYS_SLEEP_DEEP_Pos) + +#define SYS_RSTCR_SYS_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭化鑽ょ埠闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏椋庘€栭柨鐔告灮閹风兘鏁撻惃鍡氼啇閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define SYS_RSTCR_SYS_Msk (0x01 << SYS_RSTCR_SYS_Pos) +#define SYS_RSTCR_FLASH_Pos 1 //閸愶拷1闁跨喐鏋婚幏绋ASH闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_FLASH_Msk (0x01 << SYS_RSTCR_FLASH_Pos) +#define SYS_RSTCR_PWM_Pos 2 //閸愶拷1闁跨喐鏋婚幏绋癢M闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_PWM_Msk (0x01 << SYS_RSTCR_PWM_Pos) +#define SYS_RSTCR_CPU_Pos 3 //閸愶拷1闁跨喐鏋婚幏绋U闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_CPU_Msk (0x01 << SYS_RSTCR_CPU_Pos) +#define SYS_RSTCR_DMA_Pos 4 //閸愶拷1闁跨喐鏋婚幏绋A闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_DMA_Msk (0x01 << SYS_RSTCR_DMA_Pos) +#define SYS_RSTCR_NORFLASH_Pos 5 //閸愶拷1闁跨喐鏋婚幏绋甇R Flash闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_NORFLASH_Msk (0x01 << SYS_RSTCR_NORFLASH_Pos) +#define SYS_RSTCR_SRAM_Pos 6 //閸愶拷1闁跨喐鏋婚幏绋碦AM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_SRAM_Msk (0x01 << SYS_RSTCR_SRAM_Pos) +#define SYS_RSTCR_SDRAM_Pos 7 //閸愶拷1闁跨喐鏋婚幏绋碊RAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_SDRAM_Msk (0x01 << SYS_RSTCR_SDRAM_Pos) +#define SYS_RSTCR_SDIO_Pos 8 //閸愶拷1闁跨喐鏋婚幏绋碊IO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_SDIO_Msk (0x01 << SYS_RSTCR_SDIO_Pos) +#define SYS_RSTCR_LCD_Pos 9 //閸愶拷1闁跨喐鏋婚幏绋珻D闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_LCD_Msk (0x01 << SYS_RSTCR_LCD_Pos) +#define SYS_RSTCR_CAN_Pos 10 //閸愶拷1闁跨喐鏋婚幏绋N闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_CAN_Msk (0x01 << SYS_RSTCR_CAN_Pos) + +#define SYS_RSTSR_POR_Pos 0 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏绋癘R闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_POR_Msk (0x01 << SYS_RSTSR_POR_Pos) +#define SYS_RSTSR_BOD_Pos 1 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏绋D闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_BOD_Msk (0x01 << SYS_RSTSR_BOD_Pos) +#define SYS_RSTSR_PIN_Pos 2 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏鐑芥晸鐟欙綁鍎撮柨鐔告灮閹风兘鏁撻懘姘舵交閹疯渹缍呴柨鐔告灮閹峰嘲鍟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_PIN_Msk (0x01 << SYS_RSTSR_PIN_Pos) +#define SYS_RSTSR_WDT_Pos 3 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏绋篋T闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_WDT_Msk (0x01 << SYS_RSTSR_WDT_Pos) +#define SYS_RSTSR_SWRST_Pos 4 //Software Reset, 1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪澶哥串閹风兘鏁撻崣顐嫹1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_SWRST_Msk (0x01 << SYS_RSTSR_SWRST_Pos) + +#define SYS_LRCCR_OFF_Pos 0 //Low Speed RC Off +#define SYS_LRCCR_OFF_Msk (0x01 << SYS_LRCCR_OFF_Pos) + +#define SYS_LRCTRIM0_R_Pos 0 //LRC闁跨喕顢滅喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_R_Msk (0x7FFF << SYS_LRCTRIM0_R_Pos) +#define SYS_LRCTRIM0_M_Pos 15 //LRC闁跨喎褰ㄧ喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_M_Msk (0x3F << SYS_LRCTRIM2_M_Pos) +#define SYS_LRCTRIM0_F_Pos 21 //LRC缂佸棝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_F_Msk (0x7FF << SYS_LRCTRIM0_F_Pos) + +#define SYS_LRCTRIM1_U_Pos 0 //LRC U闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍� +#define SYS_LRCTRIM1_U_Msk (0x7FFF << SYS_LRCTRIM1_U_Pos) + +#define SYS_HRCCR_DBL_Pos 0 //Double Frequency 0 20MHz 1 40MHz +#define SYS_HRCCR_DBL_Msk (0x01 << SYS_HRCCR_DBL_Pos) +#define SYS_HRCCR_OFF_Pos 1 //High speed RC Off +#define SYS_HRCCR_OFF_Msk (0x01 << SYS_HRCCR_OFF_Pos) + +#define SYS_HRC20M_R_Pos 0 //HRC 20MHz闁跨喕顢滅喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_HRC20M_R_Msk (0x3FFF << SYS_HRC20M_R_Pos) +#define SYS_HRC20M_F_Pos 16 //HRC 20MHz缂佸棝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_HRC20M_F_Msk (0x7FF << SYS_HRC20M_F_Pos) + +#define SYS_HRC40M_R_Pos 0 //HRC 40MHz闁跨喕顢滅喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_HRC40M_R_Msk (0x3FFF << SYS_HRC40M_R_Pos) +#define SYS_HRC40M_F_Pos 16 //HRC 40MHz缂佸棝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_HRC40M_F_Msk (0x7FF << SYS_HRC40M_F_Pos) + +#define SYS_TEMPCR_OFF_Pos 0 //闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閹搭亝鍞婚幏锟� +#define SYS_TEMPCR_OFF_Msk (0x01 << SYS_TEMPCR_OFF_Pos) +#define SYS_TEMPCR_TRIM_Pos 4 //闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋礡IM +#define SYS_TEMPCR_TRIM_Msk (0x3F << SYS_TEMPCR_TRIM_Pos) + +#define SYS_XTALCR_EN_Pos 0 +#define SYS_XTALCR_EN_Msk (0x01 << SYS_XTALCR_EN_Pos) + +#define SYS_PLLCR_OUTEN_Pos 0 //閸欘亪鏁撻弬銈嗗LOCK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SYS_PLLCR_OUTEN_Msk (0x01 << SYS_PLLCR_OUTEN_Pos) +#define SYS_PLLCR_INSEL_Pos 1 //0 XTAL 1 HRC +#define SYS_PLLCR_INSEL_Msk (0x01 << SYS_PLLCR_INSEL_Pos) +#define SYS_PLLCR_OFF_Pos 2 +#define SYS_PLLCR_OFF_Msk (0x01 << SYS_PLLCR_OFF_Pos) + +#define SYS_PLLDIV_FBDIV_Pos 0 //PLL FeedBack闁跨喐鏋婚幏鐑筋暥闁跨喍鑼庢潏鐐闁跨喐鏋婚幏锟� +//VCO闁跨喐鏋婚幏鐑芥晸閻欙紕顣幏鐑芥晸閿燂拷 = PLL闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� / INDIV * 4 * FBDIV +//PLL闁跨喐鏋婚幏鐑芥晸閻欙紕顣幏鐑芥晸閿燂拷 = PLL闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� / INDIV * 4 * FBDIV / OUTDIV = VCO闁跨喐鏋婚幏鐑芥晸閻欙紕顣幏鐑芥晸閿燂拷 / OUTDIV +#define SYS_PLLDIV_FBDIV_Msk (0x1FF << SYS_PLLDIV_FBDIV_Pos) +#define SYS_PLLDIV_ADDIV_Pos 9 //ADC閺冨爼鏁撻幒銉ょ串閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋窩O闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄珱绾板瀚归柨鐔告灮閹烽攱妞傞柨鐔稿复閿濆繑瀚归柨鐔告灮閹风DDIV闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉绡圖C闁跨喐鏋婚幏鐤祮闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏锟� +#define SYS_PLLDIV_ADDIV_Msk (0x1F << SYS_PLLDIV_ADDIV_Pos) +#define SYS_PLLDIV_ADVCO_Pos 14 //0 VCO闁跨喐鏋婚幏鐑芥晸閿燂拷16闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏铚傝礋ADC閺冨爼鏁撻幒銉ょ串閹凤拷 1 VCO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�32闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏铚傝礋ADC閺冨爼鏁撻幒銉ょ串閹凤拷 2 VCO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�64闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏铚傝礋ADC閺冨爼鏁撻幒銉ょ串閹凤拷 +#define SYS_PLLDIV_ADVCO_Msk (0x03 << SYS_PLLDIV_ADVCO_Pos) +#define SYS_PLLDIV_INDIV_Pos 16 //PLL 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰┃鎰闁跨喐甯撮崙銈嗗妫帮拷 +#define SYS_PLLDIV_INDIV_Msk (0x1F << SYS_PLLDIV_INDIV_Pos) +#define SYS_PLLDIV_OUTDIV_Pos 24 //PLL 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄珱绾板瀚归柨鐕傛嫹0 8闁跨喐鏋婚幏鐑筋暥 1 4闁跨喐鏋婚幏鐑筋暥 0 2闁跨喐鏋婚幏鐑筋暥 +#define SYS_PLLDIV_OUTDIV_Msk (0x03 << SYS_PLLDIV_OUTDIV_Pos) + +#define SYS_PLLSET_LPFBW_Pos 0 //PLL Low Pass Filter Bandwidth +#define SYS_PLLSET_LPFBW_Msk (0x0F << SYS_PLLSET_LPFBW_Pos) +#define SYS_PLLSET_BIASADJ_Pos 4 //PLL Current Bias Adjustment +#define SYS_PLLSET_BIASADJ_Msk (0x03 << SYS_PLLSET_BIASADJ_Pos) +#define SYS_PLLSET_REFVSEL_Pos 6 //PLL Reference Voltage Select +#define SYS_PLLSET_REFVSEL_Msk (0x03 << SYS_PLLSET_REFVSEL_Pos) +#define SYS_PLLSET_CHPADJL_Pos 8 //PLL charge pump LSB current Adjustment +#define SYS_PLLSET_CHPADJL_Msk (0x07 << SYS_PLLSET_CHPADJL_Pos) +#define SYS_PLLSET_CHPADJM_Pos 11 //PLL charge pump MSB current Adjustment +#define SYS_PLLSET_CHPADJM_Msk (0x03 << SYS_PLLSET_CHPADJM_Pos) + +#define SYS_BODIE_1V9_Pos 0 //BOD 1.9V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚规担鍧楁晸閺傘倖瀚� +#define SYS_BODIE_1V9_Msk (0x01 << SYS_BODIE_1V9_Pos) +#define SYS_BODIE_2V2_Pos 1 //BOD 2.2V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚规担鍧楁晸閺傘倖瀚� +#define SYS_BODIE_2V2_Msk (0x01 << SYS_BODIE_2V2_Pos) + +#define SYS_BODIF_1V9_Pos 0 //BOD 1.9V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚归悩鑸碘偓渚€鏁撻弬銈嗗閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_BODIF_1V9_Msk (0x01 << SYS_BODIF_1V9_Pos) +#define SYS_BODIF_2V2_Pos 1 //BOD 2.2V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚归悩鑸碘偓渚€鏁撻弬銈嗗閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_BODIF_2V2_Msk (0x01 << SYS_BODIF_2V2_Pos) + +#define SYS_ADC1IN7_SEL_Pos 0 //ADC1濡繝鏁撻弬銈嗗濡繝鏁撻弬銈嗗闁岸鏁撻弬銈嗗7闁跨喐鏋婚幏锟�1 闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� 2 闁跨喐鏋婚幏閿嬬毉闁跨喓鐛ら敓锟� 3 RTC闁跨喐鏋婚幏閿嬬爱闁跨喐鏋婚幏绋 4 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰┃鎰版晸閺傘倖瀚笲G 5 PDM33 +#define SYS_ADC1IN7_SEL_Msk (0x0F << SYS_ADC1IN7_SEL_Pos) +#define SYS_ADC1IN7_IOON_Pos 4 //ADC1濡繝鏁撻弬銈嗗濡繝鏁撻弬銈嗗闁岸鏁撻弬銈嗗7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笽O闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_ADC1IN7_IOON_Msk (0x01 << SYS_ADC1IN7_IOON_Pos) + +#define SYS_BODCR_EN_Pos 0 +#define SYS_BODCR_EN_Msk (0x01 << SYS_BODCR_EN_Pos) + +typedef struct +{ + __IO uint32_t PORTA_SEL; //闁跨喐鏋婚幏绋癘RTA_SEL[2n+2:2n]闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规惔鏃堟晸閺傘倖瀚归崐濂告晸閺傘倖瀚归柨鐔告灮閹风òORTA.PINn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻惌顐ゎ劜閹风ěPIO闁跨喐鏋婚幏閿嬆侀柨鐔恍掗妴渚€鏁撻弬銈嗗闁跨喕顢滅粵澶屾閹风兘鏁撻弬銈嗗 + //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崐闂磋礋PORTA_PINn_FUNMUX閺冨爼鏁撻弬銈嗗PORTA.PINn闁跨喐鏋婚幏鐑芥晸閼存艾灏呴幏鐑解偓姘舵晸閺傘倖瀚筆ORTA_MUX闁跨喍鑼庢潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿复绾板瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 + __IO uint32_t PORTB_SEL; + + __IO uint32_t PORTC_SEL; + + uint32_t RESERVED[5]; + + __IO uint32_t PORTM_SEL0; + + __IO uint32_t PORTM_SEL1; + + uint32_t RESERVED2[2]; + + __IO uint32_t PORTN_SEL0; + + __IO uint32_t PORTN_SEL1; + + uint32_t RESERVED3[2]; + + __IO uint32_t PORTP_SEL0; + + __IO uint32_t PORTP_SEL1; + + uint32_t RESERVED4[46]; + + __IO uint32_t PORTA_MUX0; + + __IO uint32_t PORTA_MUX1; + + uint32_t RESERVED5[2]; + + __IO uint32_t PORTB_MUX0; + + __IO uint32_t PORTB_MUX1; + + uint32_t RESERVED6[2]; + + __IO uint32_t PORTC_MUX0; + + __IO uint32_t PORTC_MUX1; + + uint32_t RESERVED7[14]; + + __IO uint32_t PORTM_MUX0; + + __IO uint32_t PORTM_MUX1; + + __IO uint32_t PORTM_MUX2; + + __IO uint32_t PORTM_MUX3; + + __IO uint32_t PORTN_MUX0; + + __IO uint32_t PORTN_MUX1; + + __IO uint32_t PORTN_MUX2; + + uint32_t RESERVED8; + + __IO uint32_t PORTP_MUX0; + + __IO uint32_t PORTP_MUX1; + + __IO uint32_t PORTP_MUX2; + + __IO uint32_t PORTP_MUX3; + + uint32_t RESERVED9[28]; + + __IO uint32_t PORTA_PULLU; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� + + uint32_t RESERVED10[3]; + + __IO uint32_t PORTC_PULLU; + + uint32_t RESERVED11[3]; + + __IO uint32_t PORTM_PULLU; + + uint32_t RESERVED12[3]; + + __IO uint32_t PORTP_PULLU; + + uint32_t RESERVED13[51]; + + __IO uint32_t PORTB_PULLD; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� + + uint32_t RESERVED14[3]; + + __IO uint32_t PORTD_PULLD; + + uint32_t RESERVED15[3]; + + __IO uint32_t PORTN_PULLD; + + uint32_t RESERVED16[135]; + + __IO uint32_t PORTM_DRIVS; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰娲晸閺傘倖瀚� + + uint32_t RESERVED17[3]; + + __IO uint32_t PORTN_DRIVS; + + uint32_t RESERVED18[3]; + + __IO uint32_t PORTP_DRIVS; + + uint32_t RESERVED19[39]; + + __IO uint32_t PORTA_INEN; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� + + uint32_t RESERVED20[3]; + + __IO uint32_t PORTB_INEN; + + uint32_t RESERVED21[3]; + + __IO uint32_t PORTC_INEN; + + uint32_t RESERVED22[7]; + + __IO uint32_t PORTM_INEN; + + uint32_t RESERVED23[3]; + + __IO uint32_t PORTN_INEN; + + uint32_t RESERVED24[3]; + + __IO uint32_t PORTP_INEN; +} PORT_TypeDef; + +typedef struct +{ + __IO uint32_t DATA; +#define PIN0 0 +#define PIN1 1 +#define PIN2 2 +#define PIN3 3 +#define PIN4 4 +#define PIN5 5 +#define PIN6 6 +#define PIN7 7 +#define PIN8 8 +#define PIN9 9 +#define PIN10 10 +#define PIN11 11 +#define PIN12 12 +#define PIN13 13 +#define PIN14 14 +#define PIN15 15 +#define PIN16 16 +#define PIN17 17 +#define PIN18 18 +#define PIN19 19 +#define PIN20 20 +#define PIN21 21 +#define PIN22 22 +#define PIN23 23 +#define PIN24 24 + + __IO uint32_t DIR; //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 1 闁跨喐鏋婚幏鐑芥晸閿燂拷 + + __IO uint32_t INTLVLTRG; //Interrupt Level Trigger 1 闁跨喐鏋婚幏宄伴挬闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚� 0 闁跨喐鏋婚幏鐑芥晸閹搭亣鎻幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚� + + __IO uint32_t INTBE; //Both Edge闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笽NTLVLTRG闁跨喐鏋婚幏铚傝礋闁跨喐鏋婚幏鐑芥晸閹搭亣鎻幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚归弮鍫曟晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔告灮閹凤拷1闁跨喐鏋婚幏椋庛仛闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻閻氬瓨瀚归柨鐔兼應閺傘倖瀚归柨鐔稿焻鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎褰ㄩ弬顓ㄧ秶閹风兘鏁撻弬銈嗗0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗INTRISEEN闁鏁撻弬銈嗗 + + __IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷/闁跨喓顏喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏锟� 0 闁跨喖鎽弬銈嗗闁跨喐鏋婚幏锟�/闁跨喖鍙虹喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏锟� + + __IO uint32_t INTEN; //1 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗 0 闁跨喎褰ㄩ弬顓熸灮閹烽攱顒� + + __IO uint32_t INTRAWSTAT; //闁跨喎褰ㄩ弬顓犮€嬮幏椋庡禃閵夋棏浜烽幏閿嬬懞闁跨喐鏋婚幏椋庡禃閺傘倖瀚归懜婊堟晸閺傘倖瀚归柨鐔告灮閹峰嘲宓忕化濠氭晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� 1 闁跨喐鏋婚幏椋庡禃閺傘倖瀚归柨鐔告灮閹峰嘲宓忓ú妤呮晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨噦鎷� 0 濞岋繝鏁撻崣顐ゃ€嬮幏椋庡禃閺傘倖瀚归崡鍛婄闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + + __IO uint32_t INTSTAT; //INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0 + + __IO uint32_t INTCLR; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡绋款€掗柨鐔活敎閹惧懏瀚归柨鐔活敎娴兼瑦瀚归崨姗€鏁撻弬銈嗗閸楊噣鏁撻弬銈嗗闁跨喐鏋婚幏宄板祻闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 +} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t LDVAL; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲鈧ジ鏁撻弬銈嗗娴ｅ潡鏁撻弶鎵皑閹烽攱妞傞柨鐔告灮閹风兘鏁撻幒銉ㄦ彧閹风兘鏁撻弬銈嗗閸婂ジ鏁撻弬銈嗗婵鏁撻弬銈嗗闁跨喖鎽柅鎺斻€嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + + __I uint32_t CVAL; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崜宥呪偓濂告晸閺傘倖瀚筁DVAL-CVAL 闁跨喓鍗崇涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹哺缁楁梹鍞婚幏鐑芥晸閿燂拷 + + __IO uint32_t CTRL; +} TIMR_TypeDef; + +#define TIMR_CTRL_EN_Pos 0 //闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏锟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筎IMR闁跨喐鏋婚幏绋珼VAL闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸闁句即鈧帞銆嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define TIMR_CTRL_EN_Msk (0x01 << TIMR_CTRL_EN_Pos) +#define TIMR_CTRL_CLKSRC_Pos 1 //閺冨爼鏁撻弬銈嗗濠ф劙鏁撻弬銈嗗0 闁跨喕濡拠褎瀚圭化鑽ょ埠閺冨爼鏁撻弬銈嗗 1 闁跨喕袙闁劑鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨噦鎷� +#define TIMR_CTRL_CLKSRC_Msk (0x01 << TIMR_CTRL_CLKSRC_Pos) +#define TIMR_CTRL_CASCADE_Pos 2 //1 TIMRx闁跨喍鑼庣涵閿嬪闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏铚傝礋TIMRx-1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风柉妫旈柨鐕傛嫹 +#define TIMR_CTRL_CASCADE_Msk (0x01 << TIMR_CTRL_CASCADE_Pos) + +typedef struct +{ + __IO uint32_t PCTRL; //Pulse Control闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喍鑼庨敐蹇斿闁跨喐鏋婚幏鐑芥晸閻欌€崇槑鏉堢偓瀚归柨鐔告灮閹凤拷 + + __I uint32_t PCVAL; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓绮搁幉瀣闁跨喐鏋婚幏鐑芥晸鐟欐帞鍩滈敓锟� + + uint32_t RESERVED[2]; + + __IO uint32_t IE; + + __IO uint32_t IF; + + __IO uint32_t HALT; +} TIMRG_TypeDef; + +#define TIMRG_PCTRL_EN_Pos 0 //闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷32娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷0闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸鏉堝啰銆嬮幏鐑芥晸閺傘倖瀚� +#define TIMRG_PCTRL_EN_Msk (0x01 << TIMRG_PCTRL_EN_Pos) +#define TIMRG_PCTRL_HIGH_Pos 1 //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔煎徍绾板瀚归獮鎶芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔侯仾绾板瀚归獮鎶芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define TIMRG_PCTRL_HIGH_Msk (0x01 << TIMRG_PCTRL_HIGH_Pos) +#define TIMRG_PCTRL_CLKSRC_Pos 2 //閺冨爼鏁撻弬銈嗗濠ф劙鏁撻弬銈嗗0 闁跨喕濡拠褎瀚圭化鑽ょ埠閺冨爼鏁撻弬銈嗗 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴笟銉秶閹风兘鏁撻弬銈嗗闁跨喐褰导娆愬闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崐顒勬晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define TIMRG_PCTRL_CLKSRC_Msk (0x01 << TIMRG_PCTRL_CLKSRC_Pos) + +#define TIMRG_IE_TIMR0_Pos 0 +#define TIMRG_IE_TIMR0_Msk (0x01 << TIMRG_IE_TIMR0_Pos) +#define TIMRG_IE_TIMR1_Pos 1 +#define TIMRG_IE_TIMR1_Msk (0x01 << TIMRG_IE_TIMR1_Pos) +#define TIMRG_IE_TIMR2_Pos 2 +#define TIMRG_IE_TIMR2_Msk (0x01 << TIMRG_IE_TIMR2_Pos) +#define TIMRG_IE_TIMR3_Pos 3 +#define TIMRG_IE_TIMR3_Msk (0x01 << TIMRG_IE_TIMR3_Pos) +#define TIMRG_IE_TIMR4_Pos 4 +#define TIMRG_IE_TIMR4_Msk (0x01 << TIMRG_IE_TIMR4_Pos) +#define TIMRG_IE_TIMR5_Pos 5 +#define TIMRG_IE_TIMR5_Msk (0x01 << TIMRG_IE_TIMR5_Pos) +#define TIMRG_IE_PULSE_Pos 16 +#define TIMRG_IE_PULSE_Msk (0x01 << TIMRG_IE_PULSE_Pos) + +#define TIMRG_IF_TIMR0_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define TIMRG_IF_TIMR0_Msk (0x01 << TIMRG_IF_TIMR0_Pos) +#define TIMRG_IF_TIMR1_Pos 1 +#define TIMRG_IF_TIMR1_Msk (0x01 << TIMRG_IF_TIMR1_Pos) +#define TIMRG_IF_TIMR2_Pos 2 +#define TIMRG_IF_TIMR2_Msk (0x01 << TIMRG_IF_TIMR2_Pos) +#define TIMRG_IF_TIMR3_Pos 3 +#define TIMRG_IF_TIMR3_Msk (0x01 << TIMRG_IF_TIMR3_Pos) +#define TIMRG_IF_TIMR4_Pos 4 +#define TIMRG_IF_TIMR4_Msk (0x01 << TIMRG_IF_TIMR4_Pos) +#define TIMRG_IF_TIMR5_Pos 5 +#define TIMRG_IF_TIMR5_Msk (0x01 << TIMRG_IF_TIMR5_Pos) +#define TIMRG_IF_PULSE_Pos 16 +#define TIMRG_IF_PULSE_Msk (0x01 << TIMRG_IF_PULSE_Pos) + +#define TIMRG_HALT_TIMR0_Pos 0 //1 闁跨喐鏋婚幏宄颁粻闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define TIMRG_HALT_TIMR0_Msk (0x01 << TIMRG_HALT_TIMR0_Pos) +#define TIMRG_HALT_TIMR1_Pos 1 +#define TIMRG_HALT_TIMR1_Msk (0x01 << TIMRG_HALT_TIMR1_Pos) +#define TIMRG_HALT_TIMR2_Pos 2 +#define TIMRG_HALT_TIMR2_Msk (0x01 << TIMRG_HALT_TIMR2_Pos) +#define TIMRG_HALT_TIMR3_Pos 3 +#define TIMRG_HALT_TIMR3_Msk (0x01 << TIMRG_HALT_TIMR3_Pos) +#define TIMRG_HALT_TIMR4_Pos 4 +#define TIMRG_HALT_TIMR4_Msk (0x01 << TIMRG_HALT_TIMR4_Pos) +#define TIMRG_HALT_TIMR5_Pos 5 +#define TIMRG_HALT_TIMR5_Msk (0x01 << TIMRG_HALT_TIMR5_Pos) + +typedef struct +{ + __IO uint32_t DATA; + + __IO uint32_t CTRL; + + __IO uint32_t BAUD; + + __IO uint32_t FIFO; + + __IO uint32_t LINCR; + + union + { + __IO uint32_t CTSCR; + + __IO uint32_t RTSCR; + }; +} UART_TypeDef; + +#define UART_DATA_DATA_Pos 0 +#define UART_DATA_DATA_Msk (0x1FF << UART_DATA_DATA_Pos) +#define UART_DATA_VALID_Pos 9 //闁跨喐鏋婚幏绋TA闁跨喕顢滅拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弫鍫ユ晸娓氥儲鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴绾剟鏁撻弬銈嗗闁跨喐鏋婚幏锟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崣鏍晸閺傘倖瀚归柨鐔稿祹閻氬瓨瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_DATA_VALID_Msk (0x01 << UART_DATA_VALID_Pos) +#define UART_DATA_PAERR_Pos 10 //Parity Error +#define UART_DATA_PAERR_Msk (0x01 << UART_DATA_PAERR_Pos) + +#define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 闁跨喐鏋婚幏鐑芥晸閼哄倸鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓渚€鏁撻弬銈嗗濞岋繝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閹瑰嘲鍤栭幏鐑芥晸閺傘倖瀚� +#define UART_CTRL_TXIDLE_Msk (0x01 << UART_CTRL_TXIDLE_Pos) +#define UART_CTRL_TXFF_Pos 1 //TX FIFO Full +#define UART_CTRL_TXFF_Msk (0x01 << UART_CTRL_TXFF_Pos) +#define UART_CTRL_TXIE_Pos 2 //TX 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗: 1 TX FF 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸婄喎鐣鹃柨鐔告灮閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏锟� +#define UART_CTRL_TXIE_Msk (0x01 << UART_CTRL_TXIE_Pos) +#define UART_CTRL_RXNE_Pos 3 //RX FIFO Not Empty +#define UART_CTRL_RXNE_Msk (0x01 << UART_CTRL_RXNE_Pos) +#define UART_CTRL_RXIE_Pos 4 //RX 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗: 1 RX FF 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹鏉堟儳鍩岄柨鐔封偓鐔风暰闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻崣顐ヮ啇閹凤拷 +#define UART_CTRL_RXIE_Msk (0x01 << UART_CTRL_RXIE_Pos) +#define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflow闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define UART_CTRL_RXOV_Msk (0x01 << UART_CTRL_RXOV_Pos) +#define UART_CTRL_TXDOIE_Pos 6 //TX Done 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弶甯秶閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋FO闁跨喐鏋婚幏鐑芥晸閹活厼鍤栭幏鐑芥晸闁伴潧鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔惰寧鏉堢偓瀚归柨鐔告灮閹风兘鏁撶粣鏍ㄦ灮閹风兘鏁撻弬銈嗗闁跨喐褰弲鍐х串閹风兘鏁撻弬銈嗗缂佺喖鏁撴鐚存嫹 +#define UART_CTRL_TXDOIE_Msk (0x01 << UART_CTRL_TXDOIE_Pos) +#define UART_CTRL_EN_Pos 9 +#define UART_CTRL_EN_Msk (0x01 << UART_CTRL_EN_Pos) +#define UART_CTRL_LOOP_Pos 10 +#define UART_CTRL_LOOP_Msk (0x01 << UART_CTRL_LOOP_Pos) +#define UART_CTRL_BAUDEN_Pos 13 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崘锟�1 +#define UART_CTRL_BAUDEN_Msk (0x01 << UART_CTRL_BAUDEN_Pos) +#define UART_CTRL_TOIE_Pos 14 //TimeOut 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弶甯秶閹风兘鏁撻弬銈嗗闁跨喓笑绾板瀚归柨鐔荤窛闂堚晜瀚归柨鐔活敎閸戙倖瀚归柨鐔活殼閿涘瞼顒查幏鐑芥晸閺傘倖瀚� TOTIME/BAUDRAUD 闁跨喐鏋婚幏閿嬬梾闁跨喎褰ㄩ弬銈嗗闁跨喓笑绾板瀚归柨鐔兼應绾板瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_CTRL_TOIE_Msk (0x01 << UART_CTRL_TOIE_Pos) +#define UART_CTRL_BRKDET_Pos 15 //LIN Break Detect闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悰鍓хオIN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筊X闁跨喐鏋婚幏鐑芥晸鏉堝啰銆嬮幏椋庡禃閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�11娴ｅ秹鏁撻柊鐢殿暜閹峰嘲閽� +#define UART_CTRL_BRKDET_Msk (0x01 << UART_CTRL_BRKDET_Pos) +#define UART_CTRL_BRKIE_Pos 16 //LIN Break Detect 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗 +#define UART_CTRL_BRKIE_Msk (0x01 << UART_CTRL_BRKIE_Pos) +#define UART_CTRL_GENBRK_Pos 17 //Generate LIN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风ìIN Break +#define UART_CTRL_GENBRK_Msk (0x01 << UART_CTRL_GENBRK_Pos) +#define UART_CTRL_DATA9b_Pos 18 //1 9娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴 0 8娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴 +#define UART_CTRL_DATA9b_Msk (0x01 << UART_CTRL_DATA9b_Pos) +#define UART_CTRL_PARITY_Pos 19 //000 闁跨喐鏋婚幏閿嬬墡闁跨喐鏋婚幏锟� 001 闁跨喐鏋婚幏閿嬬墡闁跨喐鏋婚幏锟� 011 閸嬭埖鐗庨柨鐔告灮閹凤拷 101 闁跨喐鏆€鐠佽瀚规稉锟�1 111 闁跨喐鏆€鐠佽瀚规稉锟�0 +#define UART_CTRL_PARITY_Msk (0x07 << UART_CTRL_PARITY_Pos) +#define UART_CTRL_STOP2b_Pos 22 //1 2娴ｅ秴浠犲顫秴 0 1娴ｅ秴浠犲顫秴 +#define UART_CTRL_STOP2b_Msk (0x03 << UART_CTRL_STOP2b_Pos) +#define UART_CTRL_TOTIME_Pos 24 //TimeOut 閺冨爼鏁撻弬銈嗗 = TOTIME/(BAUDRAUD/10) 闁跨喐鏋婚幏锟� +//#define UART_CTRL_TOTIME_Msk (0xFF << UART_CTRL_TOTIME_Pos) 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濮ら敍锟� integer operation result is out of range +#define UART_CTRL_TOTIME_Msk ((uint32_t)0xFF << UART_CTRL_TOTIME_Pos) + +#define UART_BAUD_BAUD_Pos 0 //闁跨喐鏋婚幏鐑芥晸閼哄倽顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 = SYS_Freq/16/BAUD - 1 +#define UART_BAUD_BAUD_Msk (0x3FFF << UART_BAUD_BAUD_Pos) +#define UART_BAUD_TXD_Pos 14 //闁岸鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏椋庢纯闁跨喐甯寸拋瑙勫閸欐牠鏁撻弬銈嗗闁跨喐鏋婚幏绋礨D闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔荤窛閻ㄥ嫮顣幏宄伴挬 +#define UART_BAUD_TXD_Msk (0x01 << UART_BAUD_TXD_Pos) +#define UART_BAUD_RXD_Pos 15 //闁岸鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏椋庢纯闁跨喐甯寸拋瑙勫閸欐牠鏁撻弬銈嗗闁跨喐鏋婚幏绋瞂D闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔荤窛閻ㄥ嫮顣幏宄伴挬 +#define UART_BAUD_RXD_Msk (0x01 << UART_BAUD_RXD_Pos) +#define UART_BAUD_RXTOIF_Pos 16 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�&闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閸欘偅鏌囬幉瀣韫囷拷 = RXIF | TOIF +#define UART_BAUD_RXTOIF_Msk (0x01 << UART_BAUD_RXTOIF_Pos) +#define UART_BAUD_TXIF_Pos 17 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鍞婚幏宄扮箶 = TXTHRF & TXIE +#define UART_BAUD_TXIF_Msk (0x01 << UART_BAUD_TXIF_Pos) +#define UART_BAUD_BRKIF_Pos 18 //LIN Break Detect 闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨鐔告灮閹风兘鏁撻弬銈嗗閻涘墽绁狪N Break閺冨爼鏁撻弬銈嗗BRKIE=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔告灮閹疯渹缍� +#define UART_BAUD_BRKIF_Msk (0x01 << UART_BAUD_BRKIF_Pos) +#define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold Flag闁跨喐鏋婚幏绋瞂 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹鏉堟儳鍩岄柨鐔封偓鐔风暰闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风úXLVL >= RXTHR闁跨喐鏋婚幏閿嬫绾剟鏁撻弬銈嗗闁跨喐鏋婚幏锟�1 +#define UART_BAUD_RXTHRF_Msk (0x01 << UART_BAUD_RXTHRF_Pos) +#define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold Flag闁跨喐鏋婚幏绋礨 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸婄喎鐣鹃柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋礨LVL <= TXTHR闁跨喐鏋婚幏閿嬫绾剟鏁撻弬銈嗗闁跨喐鏋婚幏锟�1 +#define UART_BAUD_TXTHRF_Msk (0x01 << UART_BAUD_TXTHRF_Pos) +#define UART_BAUD_TOIF_Pos 21 //TimeOut 闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� TOTIME/BAUDRAUD 闁跨喐鏋婚幏閿嬬梾闁跨喎褰ㄩ弬銈嗗闁跨喓笑绾板瀚归柨鐔兼應绾板瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗TOIE=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔告灮閹疯渹缍� +#define UART_BAUD_TOIF_Msk (0x01 << UART_BAUD_TOIF_Pos) +#define UART_BAUD_RXIF_Pos 22 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鍞婚幏宄扮箶 = RXTHRF & RXIE +#define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos) +#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閺嶁€冲櫙闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� +#define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos) +#define UART_BAUD_ABRBIT_Pos 24 //Auto Baudrate Bit闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν绾攱瀚归柨鐔奉潟濞夈垽鏁撻弬銈嗗闁跨喓绮搁惃鍕€嬮幏鐑芥晸鏉炲じ绱幏鐑芥晸閺傘倖瀚归柨鐕傛嫹0 1娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0xFF +// 1 2娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴闁跨喐鏋婚幏锟�1娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0xFE +// 1 4娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴闁跨喐鏋婚幏锟�3娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0xF8 +// 1 8娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴闁跨喐鏋婚幏锟�7娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0x80 +#define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos) +#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error闁跨喐鏋婚幏锟�0 闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鐗庨崙鍡涙晸缂傚娅㈤幏锟� 1 闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鐗庨崙鍡椼亼闁跨喐鏋婚幏锟� +#define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos) +#define UART_BAUD_TXDOIF_Pos 27 //TX Done 闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋FO闁跨喐鏋婚幏鐑芥晸閹活厼鍤栭幏鐑芥晸闁伴潧鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔惰寧鏉堢偓瀚归柨鐔告灮閹风兘鏁撶粣鏍ㄦ灮閹风兘鏁撻弬銈嗗闁跨喐褰弲鍐х串閹风兘鏁撻弬銈嗗缂佺喖鏁撴鐚存嫹 +#define UART_BAUD_TXDOIF_Msk (0x01 << UART_BAUD_TXDOIF_Pos) + +#define UART_FIFO_RXLVL_Pos 0 //RX FIFO Level闁跨喐鏋婚幏绋瞂 FIFO 闁跨喐鏋婚幏鐑芥晸鐞涙鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define UART_FIFO_RXLVL_Msk (0xFF << UART_FIFO_RXLVL_Pos) +#define UART_FIFO_TXLVL_Pos 8 //TX FIFO Level闁跨喐鏋婚幏绋礨 FIFO 闁跨喐鏋婚幏鐑芥晸鐞涙鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define UART_FIFO_TXLVL_Msk (0xFF << UART_FIFO_TXLVL_Pos) +#define UART_FIFO_RXTHR_Pos 16 //RX FIFO Threshold闁跨喐鏋婚幏绋瞂闁跨喎褰ㄩ弬顓℃彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閻偓缍囬幏鐑芥晸閸欘偉顔愰幏铚傚▏闁跨喐鏋婚幏閿嬫 RXLVL >= RXTHR 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筊X闁跨喎褰ㄧ拋瑙勫 +#define UART_FIFO_RXTHR_Msk (0xFF << UART_FIFO_RXTHR_Pos) +#define UART_FIFO_TXTHR_Pos 24 //TX FIFO Threshold闁跨喐鏋婚幏绋礨闁跨喎褰ㄩ弬顓℃彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閻偓缍囬幏鐑芥晸閸欘偉顔愰幏铚傚▏闁跨喐鏋婚幏閿嬫 TXLVL <= TXTHR 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筎X闁跨喎褰ㄧ拋瑙勫 +//#define UART_FIFO_TXTHR_Msk (0xFF << UART_FIFO_TXTHR_Pos) 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濮ら敍锟� integer operation result is out of range +#define UART_FIFO_TXTHR_Msk ((uint32_t)0xFF << UART_FIFO_TXTHR_Pos) + +#define UART_LINCR_BRKDETIE_Pos 0 //闁跨喐鏋婚幏椋庡禃缁插儐N Break闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗 +#define UART_LINCR_BRKDETIE_Msk (0xFF << UART_LINCR_BRKDETIE_Pos) +#define UART_LINCR_BRKDETIF_Pos 1 //闁跨喐鏋婚幏椋庡禃缁插儐N Break闁跨喎褰ㄧ拋瑙勫閻樿埖鈧拷 +#define UART_LINCR_BRKDETIF_Msk (0xFF << UART_LINCR_BRKDETIF_Pos) +#define UART_LINCR_GENBRKIE_Pos 2 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筁IN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡鎼佹晸缂佺偟娅㈤幏鐑芥晸閿燂拷 +#define UART_LINCR_GENBRKIE_Msk (0xFF << UART_LINCR_GENBRKIE_Pos) +#define UART_LINCR_GENBRKIF_Pos 3 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筁IN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡鎼佹晸闂冭泛鍩￠敓锟� +#define UART_LINCR_GENBRKIF_Msk (0xFF << UART_LINCR_GENBRKIF_Pos) +#define UART_LINCR_GENBRK_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筁IN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤箼闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 +#define UART_LINCR_GENBRK_Msk (0xFF << UART_LINCR_GENBRK_Pos) + +#define UART_CTSCR_EN_Pos 0 //CTS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� +#define UART_CTSCR_EN_Msk (0x01 << UART_CTSCR_EN_Pos) +#define UART_CTSCR_POL_Pos 2 //CTS闁跨喕鍓奸崣椋庛€嬮幏鐑芥晸閻ㄥ棴缍囬幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弫鍫ユ晸閺傘倖瀚笴TS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉娲晸闁板灚鍞婚幏椋庛仛闁跨喐鏋婚幏鐑芥晸閻ㄥ棗鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_CTSCR_POL_Msk (0x01 << UART_CTSCR_POL_Pos) +#define UART_CTSCR_STAT_Pos 7 //CTS闁跨喕鍓奸崣椋庢畱绾板瀚归崜宥囧Ц閹拷 +#define UART_CTSCR_STAT_Msk (0x01 << UART_CTSCR_STAT_Pos) + +#define UART_RTSCR_EN_Pos 1 //RTS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� +#define UART_RTSCR_EN_Msk (0x01 << UART_RTSCR_EN_Pos) +#define UART_RTSCR_POL_Pos 3 //RTS闁跨喕鍓奸崣椋庛€嬮幏鐑芥晸閺傘倖瀚� 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弫鍫ユ晸閺傘倖瀚筊TS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉娲晸闁板灚鍞婚幏椋庛仛闁跨喐鏋婚幏鐑芥晸閻ㄥ棙鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_RTSCR_POL_Msk (0x01 << UART_RTSCR_POL_Pos) +#define UART_RTSCR_THR_Pos 4 //RTS闁跨喐鏋婚幏鐑芥晸閹搭亞娈戞潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崐锟� 0 1闁跨喕顢滈弬銈嗗 1 2闁跨喕顢滈弬銈嗗 2 4闁跨喕顢滈弬銈嗗 3 6闁跨喕顢滈弬銈嗗 +#define UART_RTSCR_THR_Msk (0x07 << UART_RTSCR_THR_Pos) +#define UART_RTSCR_STAT_Pos 8 //RTS闁跨喕鍓奸崣椋庢畱绾板瀚归崜宥囧Ц閹拷 +#define UART_RTSCR_STAT_Msk (0x01 << UART_RTSCR_STAT_Pos) + +typedef struct +{ + __IO uint32_t CTRL; + + __IO uint32_t DATA; + + __IO uint32_t STAT; + + __IO uint32_t IE; + + __IO uint32_t IF; +} SPI_TypeDef; + +#define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPI闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� = SYS_Freq/pow(2, CLKDIV+2) +#define SPI_CTRL_CLKDIV_Msk (0x07 << SPI_CTRL_CLKDIV_Pos) +#define SPI_CTRL_EN_Pos 3 +#define SPI_CTRL_EN_Msk (0x01 << SPI_CTRL_EN_Pos) +#define SPI_CTRL_SIZE_Pos 4 //Data Size Select, 閸欐牕鈧拷3--15闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭粈锟�4--16娴ｏ拷 +#define SPI_CTRL_SIZE_Msk (0x0F << SPI_CTRL_SIZE_Pos) +#define SPI_CTRL_CPHA_Pos 8 //0 闁跨喐鏋婚幏绋碈LK闁跨喍鑼庣喊澶嬪娑撯偓闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幋顏囶嚋閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 1 闁跨喐鏋婚幏绋碈LK闁跨喍鑼庣粭顒冾啇閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻鐠囇勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SPI_CTRL_CPHA_Msk (0x01 << SPI_CTRL_CPHA_Pos) +#define SPI_CTRL_CPOL_Pos 9 //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓渚€鏁撻弬銈嗗SCLK娑撴椽鏁撻柊鐢殿暜閹峰嘲閽� 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓渚€鏁撻弬銈嗗SCLK娑撴椽鏁撶粩顓狀暜閹峰嘲閽� +#define SPI_CTRL_CPOL_Msk (0x01 << SPI_CTRL_CPOL_Pos) +#define SPI_CTRL_FFS_Pos 10 //Frame Format Select, 0 SPI 1 TI SSI 2 SPI 3 SPI +#define SPI_CTRL_FFS_Msk (0x03 << SPI_CTRL_FFS_Pos) +#define SPI_CTRL_MSTR_Pos 12 //Master, 1 闁跨喐鏋婚幏閿嬆佸锟� 0 闁跨喐鏋婚幏閿嬆佸锟� +#define SPI_CTRL_MSTR_Msk (0x01 << SPI_CTRL_MSTR_Pos) +#define SPI_CTRL_FAST_Pos 13 //1 SPI闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� = SYS_Freq/2 0 SPI闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚归柨鐔告灮閹风ùPI->CTRL.CLKDIV闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_CTRL_FAST_Msk (0x01 << SPI_CTRL_FAST_Pos) +#define SPI_CTRL_FILTE_Pos 16 //1 闁跨喐鏋婚幏绋碢I闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲壖閸欓攱鏋婚幏鐑芥晸閺傘倖瀚归崢濠氭晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0 闁跨喐鏋婚幏绋碢I闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲壖閸欑柉顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲骞撻柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define SPI_CTRL_FILTE_Msk (0x01 << SPI_CTRL_FILTE_Pos) +#define SPI_CTRL_SSN_H_Pos 17 //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓绁砈N婵鏁撻弬銈嗗娑擄拷0 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓鐓崠鈩冨閸р偓闁跨喕顢滈鍡樺闁跨喓绮ㄧ亸鍝燬N闁跨喐鏋婚幏鐑芥晸缁旑厼搴滈幏鐑芥晸缁插LK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_CTRL_SSN_H_Msk (0x01 << SPI_CTRL_SSN_H_Pos) +#define SPI_CTRL_TFCLR_Pos 24 //TX FIFO Clear +#define SPI_CTRL_TFCLR_Msk (0x01 << SPI_CTRL_TFCLR_Pos) +#define SPI_CTRL_RFCLR_Pos 25 //RX FIFO Clear +#define SPI_CTRL_RFCLR_Msk (0x01 << SPI_CTRL_RFCLR_Pos) + +#define SPI_STAT_WTC_Pos 0 //Word Transmit Complete闁跨喐鏋婚幏閿嬬槨闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幓顓濈串閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幒銉嚋閹风兘鏁撻弬銈嗗闁跨噦鎷�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_STAT_WTC_Msk (0x01 << SPI_STAT_WTC_Pos) +#define SPI_STAT_TFE_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Empty +#define SPI_STAT_TFE_Msk (0x01 << SPI_STAT_TFE_Pos) +#define SPI_STAT_TFNF_Pos 2 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Not Full +#define SPI_STAT_TFNF_Msk (0x01 << SPI_STAT_TFNF_Pos) +#define SPI_STAT_RFNE_Pos 3 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Not Empty +#define SPI_STAT_RFNE_Msk (0x01 << SPI_STAT_RFNE_Pos) +#define SPI_STAT_RFF_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Full +#define SPI_STAT_RFF_Msk (0x01 << SPI_STAT_RFF_Pos) +#define SPI_STAT_RFOVF_Pos 5 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Overflow +#define SPI_STAT_RFOVF_Msk (0x01 << SPI_STAT_RFOVF_Pos) +#define SPI_STAT_TFLVL_Pos 6 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹闂堚晜瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0 TFNF=0閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�8闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚筎FNF=1閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1--7 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�1--7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SPI_STAT_TFLVL_Msk (0x07 << SPI_STAT_TFLVL_Pos) +#define SPI_STAT_RFLVL_Pos 9 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹闂堚晜瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0 RFF=1閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�8闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚� RFF=0閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1--7 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�1--7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SPI_STAT_RFLVL_Msk (0x07 << SPI_STAT_RFLVL_Pos) +#define SPI_STAT_BUSY_Pos 15 +#define SPI_STAT_BUSY_Msk (0x01 << SPI_STAT_BUSY_Pos) + +#define SPI_IE_RFOVF_Pos 0 +#define SPI_IE_RFOVF_Msk (0x01 << SPI_IE_RFOVF_Pos) +#define SPI_IE_RFF_Pos 1 +#define SPI_IE_RFF_Msk (0x01 << SPI_IE_RFF_Pos) +#define SPI_IE_RFHF_Pos 2 +#define SPI_IE_RFHF_Msk (0x01 << SPI_IE_RFHF_Pos) +#define SPI_IE_TFE_Pos 3 +#define SPI_IE_TFE_Msk (0x01 << SPI_IE_TFE_Pos) +#define SPI_IE_TFHF_Pos 4 +#define SPI_IE_TFHF_Msk (0x01 << SPI_IE_TFHF_Pos) +#define SPI_IE_WTC_Pos 8 //Word Transmit Complete +#define SPI_IE_WTC_Msk (0x01 << SPI_IE_WTC_Pos) +#define SPI_IE_FTC_Pos 9 //Frame Transmit Complete +#define SPI_IE_FTC_Msk (0x01 << SPI_IE_FTC_Pos) + +#define SPI_IF_RFOVF_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_IF_RFOVF_Msk (0x01 << SPI_IF_RFOVF_Pos) +#define SPI_IF_RFF_Pos 1 +#define SPI_IF_RFF_Msk (0x01 << SPI_IF_RFF_Pos) +#define SPI_IF_RFHF_Pos 2 +#define SPI_IF_RFHF_Msk (0x01 << SPI_IF_RFHF_Pos) +#define SPI_IF_TFE_Pos 3 +#define SPI_IF_TFE_Msk (0x01 << SPI_IF_TFE_Pos) +#define SPI_IF_TFHF_Pos 4 +#define SPI_IF_TFHF_Msk (0x01 << SPI_IF_TFHF_Pos) +#define SPI_IF_WTC_Pos 8 //Word Transmit Complete闁跨喐鏋婚幏閿嬬槨闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幓顓濈串閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幒銉嚋閹风兘鏁撻弬銈嗗闁跨噦鎷�1 +#define SPI_IF_WTC_Msk (0x01 << SPI_IF_WTC_Pos) +#define SPI_IF_FTC_Pos 9 //Frame Transmit Complete闁跨喐鏋婚幏绋篢C闁跨喐鏋婚幏铚傜秴閺冨爼鏁撻弬銈嗗TX FIFO闁跨喕顫楃粚铏规畱閿濆繑瀚归柨鐔告灮閹风éTC闁跨喐鏋婚幏铚傜秴 +#define SPI_IF_FTC_Msk (0x01 << SPI_IF_FTC_Pos) + +typedef struct +{ + __IO uint32_t CLKDIV; //[15:0] 闁跨喕顕犵亸鍡涙晸閼哄倽顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘顣堕柨鐔虹哺閸掑棛顣幏绋碈L妫版垿鏁撶紒鐐殿暜閹凤拷5闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风áLKDIV = SYS_Freq/5/SCL_Freq - 1 + + __IO uint32_t CTRL; + + __IO uint32_t MSTDAT; + + __IO uint32_t MSTCMD; + + __IO uint32_t SLVCR; + + __IO uint32_t SLVIF; + + __IO uint32_t SLVTX; + + __IO uint32_t SLVRX; +} I2C_TypeDef; + +#define I2C_CTRL_MSTIE_Pos 6 +#define I2C_CTRL_MSTIE_Msk (0x01 << I2C_CTRL_MSTIE_Pos) +#define I2C_CTRL_EN_Pos 7 +#define I2C_CTRL_EN_Msk (0x01 << I2C_CTRL_EN_Pos) + +#define I2C_MSTCMD_IF_Pos 0 //1 闁跨喎褰ㄧ粵澶庢彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡绋跨瑖闁跨喎褰ㄩ敓锟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑界氨闁跨喕濞囬幐銉嚋閹风兘鏁撻弬銈嗗闁跨喕濞囨导娆愬闁跨噦鎷�1闁跨喐鏋婚幏铚傜闁跨喐鏋婚幏鐑芥晸鐞涙濡潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 2闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔侯仾閸戙倖瀚归柨鐔告灮閹烽攱娼堥柨鐔告灮閹峰嘲銇� +#define I2C_MSTCMD_IF_Msk (0x01 << I2C_MSTCMD_IF_Pos) +#define I2C_MSTCMD_TIP_Pos 1 //Transmission In Process +#define I2C_MSTCMD_TIP_Msk (0x01 << I2C_MSTCMD_TIP_Pos) +#define I2C_MSTCMD_ACK_Pos 3 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喖鎽敐蹇斿0 闁跨喐鏋婚幏鐑芥晸闁扮數顏崙銈嗗闁跨喐鏋婚幏绋烠K 1 闁跨喐鏋婚幏鐑芥晸闁扮數顏崙銈嗗闁跨喐鏋婚幏绋瓵CK +#define I2C_MSTCMD_ACK_Msk (0x01 << I2C_MSTCMD_ACK_Pos) +#define I2C_MSTCMD_WR_Pos 4 // 闁跨喐鏋婚幏绋磍ave閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹绔存担宥呭晸1闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define I2C_MSTCMD_WR_Msk (0x01 << I2C_MSTCMD_WR_Pos) +#define I2C_MSTCMD_RD_Pos 5 //閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏绋磍ave闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱妞傞柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秴鍟�1闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风ī2C濡繝鏁撻弬銈嗗婢跺崬骞撻柨鐔告灮閹风兘鏁撶粩顓犳畱閸戙倖瀚归柨鐔告灮閹烽攱娼堥弮鍓佲€栭柨鐔告灮閹风兘鏁撻弬銈嗗1 +#define I2C_MSTCMD_RD_Msk (0x01 << I2C_MSTCMD_RD_Pos) +#define I2C_MSTCMD_BUSY_Pos 6 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閻涘墽绁砊ART娑斿鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秹鏁撻弬銈嗗1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽宓曠徊濂P娑斿鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秹鏁撻弬銈嗗0 +#define I2C_MSTCMD_BUSY_Msk (0x01 << I2C_MSTCMD_BUSY_Pos) +#define I2C_MSTCMD_STO_Pos 6 //閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍TOP闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define I2C_MSTCMD_STO_Msk (0x01 << I2C_MSTCMD_STO_Pos) +#define I2C_MSTCMD_RXACK_Pos 7 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶粔鍝ヮ暜閹风兘鏁撻弬銈嗗Slave闁跨喐鏋婚幏绋烠K娴ｅ秹鏁撻弬銈嗗0 闁跨喓笑绾板瀚笰CK 1 闁跨喓笑绾板瀚筃ACK +#define I2C_MSTCMD_RXACK_Msk (0x01 << I2C_MSTCMD_RXACK_Pos) +#define I2C_MSTCMD_STA_Pos 7 //閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍TART闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define I2C_MSTCMD_STA_Msk (0x01 << I2C_MSTCMD_STA_Pos) + +#define I2C_SLVCR_IM_RXEND_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楁瓕绶伴柨鐔活敎閿燂拷 +#define I2C_SLVCR_IM_RXEND_Msk (0x01 << I2C_SLVCR_IM_RXEND_Pos) +#define I2C_SLVCR_IM_TXEND_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楁瓕绶伴柨鐔活敎閿燂拷 +#define I2C_SLVCR_IM_TXEND_Msk (0x01 << I2C_SLVCR_IM_TXEND_Pos) +#define I2C_SLVCR_IM_STADET_Pos 2 //闁跨喐鏋婚幏椋庡禃閺傘倖瀚归柨鐔虹哺绾攱瀚归崡姝岀钒闁跨喕顢滈敓锟� +#define I2C_SLVCR_IM_STADET_Msk (0x01 << I2C_SLVCR_IM_STADET_Pos) +#define I2C_SLVCR_IM_STODET_Pos 3 //闁跨喐鏋婚幏椋庡禃闁扮绾ч惂鍛婂閸楁瓕绶伴柨鐔活敎閿燂拷 +#define I2C_SLVCR_IM_STODET_Msk (0x01 << I2C_SLVCR_IM_STODET_Pos) +#define I2C_SLVCR_IM_RDREQ_Pos 4 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎褰ㄩ弬顓熸灮閹烽攱顒� +#define I2C_SLVCR_IM_RDREQ_Msk (0x01 << I2C_SLVCR_IM_RDREQ_Pos) +#define I2C_SLVCR_IM_WRREQ_Pos 5 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏宄板晸闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鏋婚幏閿嬵剾 +#define I2C_SLVCR_IM_WRREQ_Msk (0x01 << I2C_SLVCR_IM_WRREQ_Pos) +#define I2C_SLVCR_ADDR7b_Pos 16 //1 7娴ｅ秹鏁撻弬銈嗗閸р偓濡€崇础 0 10娴ｅ秹鏁撻弬銈嗗閸р偓濡€崇础 +#define I2C_SLVCR_ADDR7b_Msk (0x01 << I2C_SLVCR_ADDR7b_Pos) +#define I2C_SLVCR_ACK_Pos 17 //1 鎼存棃鏁撻弬銈嗗ACK 0 鎼存棃鏁撻弬銈嗗NACK +#define I2C_SLVCR_ACK_Msk (0x01 << I2C_SLVCR_ACK_Pos) +#define I2C_SLVCR_SLAVE_Pos 18 //1 闁跨喐甯存导娆愬濡€崇础 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础 +#define I2C_SLVCR_SLAVE_Msk (0x01 << I2C_SLVCR_SLAVE_Pos) +#define I2C_SLVCR_DEBOUNCE_Pos 19 //閸樺鏁撻弬銈嗗闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� +#define I2C_SLVCR_DEBOUNCE_Msk (0x01 << I2C_SLVCR_DEBOUNCE_Pos) +#define I2C_SLVCR_ADDR_Pos 20 //闁跨喐甯存导娆愬闁跨喐鏋婚幏宄版絻 +#define I2C_SLVCR_ADDR_Msk (0x3FF << I2C_SLVCR_ADDR_Pos) + +#define I2C_SLVIF_RXEND_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楃ǹ顎掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_RXEND_Msk (0x01 << I2C_SLVIF_RXEND_Pos) +#define I2C_SLVIF_TXEND_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楃ǹ顎掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_TXEND_Msk (0x01 << I2C_SLVIF_TXEND_Pos) +#define I2C_SLVIF_STADET_Pos 2 //闁跨喐鏋婚幏椋庡禃閺傘倖瀚归柨鐔虹哺绾攱瀚归崡绋款€掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_STADET_Msk (0x01 << I2C_SLVIF_STADET_Pos) +#define I2C_SLVIF_STODET_Pos 3 //闁跨喐鏋婚幏椋庡禃闁扮绾ч惂鍛婂閸楃ǹ顎掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_STODET_Msk (0x01 << I2C_SLVIF_STODET_Pos) +#define I2C_SLVIF_RDREQ_Pos 4 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻� +#define I2C_SLVIF_RDREQ_Msk (0x01 << I2C_SLVIF_RDREQ_Pos) +#define I2C_SLVIF_WRREQ_Pos 5 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏宄板晸闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鍞婚幏宄扮箶 +#define I2C_SLVIF_WRREQ_Msk (0x01 << I2C_SLVIF_WRREQ_Pos) +#define I2C_SLVIF_ACTIVE_Pos 6 //slave 闁跨喐鏋婚幏閿嬫櫏 +#define I2C_SLVIF_ACTIVE_Msk (0x01 << I2C_SLVIF_ACTIVE_Pos) + +typedef struct +{ + __IO uint32_t CTRL; + + __IO uint32_t START; + + __IO uint32_t IE; + + __IO uint32_t IF; + + struct + { + __IO uint32_t STAT; + + __IO uint32_t DATA; + + uint32_t RESERVED[2]; + } CH[8]; + + __IO uint32_t CTRL1; + + __IO uint32_t CTRL2; + + uint32_t RESERVED[2]; + + __IO uint32_t CALIBSET; + + __IO uint32_t CALIBEN; +} ADC_TypeDef; + +#define ADC_CTRL_CH0_Pos 0 //闁岸鏁撻弬銈嗗闁鏁撻弬銈嗗 +#define ADC_CTRL_CH0_Msk (0x01 << ADC_CTRL_CH0_Pos) +#define ADC_CTRL_CH1_Pos 1 +#define ADC_CTRL_CH1_Msk (0x01 << ADC_CTRL_CH1_Pos) +#define ADC_CTRL_CH2_Pos 2 +#define ADC_CTRL_CH2_Msk (0x01 << ADC_CTRL_CH2_Pos) +#define ADC_CTRL_CH3_Pos 3 +#define ADC_CTRL_CH3_Msk (0x01 << ADC_CTRL_CH3_Pos) +#define ADC_CTRL_CH4_Pos 4 +#define ADC_CTRL_CH4_Msk (0x01 << ADC_CTRL_CH4_Pos) +#define ADC_CTRL_CH5_Pos 5 +#define ADC_CTRL_CH5_Msk (0x01 << ADC_CTRL_CH5_Pos) +#define ADC_CTRL_CH6_Pos 6 +#define ADC_CTRL_CH6_Msk (0x01 << ADC_CTRL_CH6_Pos) +#define ADC_CTRL_CH7_Pos 7 +#define ADC_CTRL_CH7_Msk (0x01 << ADC_CTRL_CH7_Pos) +#define ADC_CTRL_AVG_Pos 8 //0 1闁跨喕濞囩拠褎瀚归柨鐔告灮閹凤拷 1 2闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� 3 4闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� 7 8闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� 15 16闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� +#define ADC_CTRL_AVG_Msk (0x0F << ADC_CTRL_AVG_Pos) +#define ADC_CTRL_EN_Pos 12 +#define ADC_CTRL_EN_Msk (0x01 << ADC_CTRL_EN_Pos) +#define ADC_CTRL_CONT_Pos 13 //Continuous conversion闁跨喐鏋婚幏宄板涧闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴笟銉悏閺傘倖瀚归柨鐔告灮閹风兘鏁撻崣顐庡秵瀚归柨鐕傛嫹0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨鐔告灮閹风柉娴嗛柨鐔告灮閹风兘鏁撻弬銈嗗閻濆﹪鏁撶徊濂RT娴ｅ秹鏁撻惃鍡氼啇閹风兘鏁撻弬銈嗗闁跨喖鍙洪敍鑸碉細椤忓孩瀚归柨鐕傛嫹 +#define ADC_CTRL_CONT_Msk (0x01 << ADC_CTRL_CONT_Pos) // 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐褰幁銏″敾閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸闂冮浜烽幏鐑芥晸閺傘倖瀚归柨鐔活敎閹插瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸缁插ィART娴ｏ拷 +#define ADC_CTRL_TRIG_Pos 14 //鏉烆剟鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲绱￠柨鐔告灮閹凤拷0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔兼▉椤忓孩瀚归柨鐕傛嫹 1 PWM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_CTRL_TRIG_Msk (0x01 << ADC_CTRL_TRIG_Pos) +#define ADC_CTRL_CLKSRC_Pos 15 //0 VCO 1 HRC +#define ADC_CTRL_CLKSRC_Msk (0x01 << ADC_CTRL_CLKSRC_Pos) +#define ADC_CTRL_FIFOCLR_Pos 24 //[24] CH0_FIFO_CLR [25] CH1_FIFO_CLR ... [31] CH7_FIFO_CLR +#define ADC_CTRL_FIFOCLR_Msk (((uint32_t)0xFF) << ADC_CTRL_FIFOCLR_Pos) + +#define ADC_START_GO_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴笟銉悏閺傘倖瀚归幏銏ゆ晸閸欘偓鎷�1闁跨喐鏋婚幏绋烡C闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风柉娴嗛柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡喊澶嬪闁跨喐鏋婚幏閿嬆佸蹇涙晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨鐔告灮閹烽寮烽柨鐔稿复鐠囇勫闁跨喐鏋婚幏鐤箼闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归幃鏍村墾閹风兘鏁撶紓鎼厜閹风兘鏁撴笟銉悏閺傘倖瀚归崡銈夋晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸愶拷0閸嬫粍顒汚DC鏉烆剟鏁撻弬銈嗗 +#define ADC_START_GO_Msk (0x01 << ADC_START_GO_Pos) +#define ADC_START_BUSY_Pos 4 +#define ADC_START_BUSY_Msk (0x01 << ADC_START_BUSY_Pos) + +#define ADC_IE_CH0EOC_Pos 0 //End Of Convertion +#define ADC_IE_CH0EOC_Msk (0x01 << ADC_IE_CH0EOC_Pos) +#define ADC_IE_CH0OVF_Pos 1 //Overflow +#define ADC_IE_CH0OVF_Msk (0x01 << ADC_IE_CH0OVF_Pos) +#define ADC_IE_CH0HFULL_Pos 2 //FIFO Half Full +#define ADC_IE_CH0HFULL_Msk (0x01 << ADC_IE_CH0HFULL_Pos) +#define ADC_IE_CH0FULL_Pos 3 //FIFO Full +#define ADC_IE_CH0FULL_Msk (0x01 << ADC_IE_CH0FULL_Pos) +#define ADC_IE_CH1EOC_Pos 4 +#define ADC_IE_CH1EOC_Msk (0x01 << ADC_IE_CH1EOC_Pos) +#define ADC_IE_CH1OVF_Pos 5 +#define ADC_IE_CH1OVF_Msk (0x01 << ADC_IE_CH1OVF_Pos) +#define ADC_IE_CH1HFULL_Pos 6 +#define ADC_IE_CH1HFULL_Msk (0x01 << ADC_IE_CH1HFULL_Pos) +#define ADC_IE_CH1FULL_Pos 7 +#define ADC_IE_CH1FULL_Msk (0x01 << ADC_IE_CH1FULL_Pos) +#define ADC_IE_CH2EOC_Pos 8 +#define ADC_IE_CH2EOC_Msk (0x01 << ADC_IE_CH2EOC_Pos) +#define ADC_IE_CH2OVF_Pos 9 +#define ADC_IE_CH2OVF_Msk (0x01 << ADC_IE_CH2OVF_Pos) +#define ADC_IE_CH2HFULL_Pos 10 +#define ADC_IE_CH2HFULL_Msk (0x01 << ADC_IE_CH2HFULL_Pos) +#define ADC_IE_CH2FULL_Pos 11 +#define ADC_IE_CH2FULL_Msk (0x01 << ADC_IE_CH2FULL_Pos) +#define ADC_IE_CH3EOC_Pos 12 +#define ADC_IE_CH3EOC_Msk (0x01 << ADC_IE_CH3EOC_Pos) +#define ADC_IE_CH3OVF_Pos 13 +#define ADC_IE_CH3OVF_Msk (0x01 << ADC_IE_CH3OVF_Pos) +#define ADC_IE_CH3HFULL_Pos 14 +#define ADC_IE_CH3HFULL_Msk (0x01 << ADC_IE_CH3HFULL_Pos) +#define ADC_IE_CH3FULL_Pos 15 +#define ADC_IE_CH3FULL_Msk (0x01 << ADC_IE_CH3FULL_Pos) +#define ADC_IE_CH4EOC_Pos 16 +#define ADC_IE_CH4EOC_Msk (0x01 << ADC_IE_CH4EOC_Pos) +#define ADC_IE_CH4OVF_Pos 17 +#define ADC_IE_CH4OVF_Msk (0x01 << ADC_IE_CH4OVF_Pos) +#define ADC_IE_CH4HFULL_Pos 18 +#define ADC_IE_CH4HFULL_Msk (0x01 << ADC_IE_CH4HFULL_Pos) +#define ADC_IE_CH4FULL_Pos 19 +#define ADC_IE_CH4FULL_Msk (0x01 << ADC_IE_CH4FULL_Pos) +#define ADC_IE_CH5EOC_Pos 20 +#define ADC_IE_CH5EOC_Msk (0x01 << ADC_IE_CH5EOC_Pos) +#define ADC_IE_CH5OVF_Pos 21 +#define ADC_IE_CH5OVF_Msk (0x01 << ADC_IE_CH5OVF_Pos) +#define ADC_IE_CH5HFULL_Pos 22 +#define ADC_IE_CH5HFULL_Msk (0x01 << ADC_IE_CH5HFULL_Pos) +#define ADC_IE_CH5FULL_Pos 23 +#define ADC_IE_CH5FULL_Msk (0x01 << ADC_IE_CH5FULL_Pos) +#define ADC_IE_CH6EOC_Pos 24 +#define ADC_IE_CH6EOC_Msk (0x01 << ADC_IE_CH6EOC_Pos) +#define ADC_IE_CH6OVF_Pos 25 +#define ADC_IE_CH6OVF_Msk (0x01 << ADC_IE_CH6OVF_Pos) +#define ADC_IE_CH6HFULL_Pos 26 +#define ADC_IE_CH6HFULL_Msk (0x01 << ADC_IE_CH6HFULL_Pos) +#define ADC_IE_CH6FULL_Pos 27 +#define ADC_IE_CH6FULL_Msk (0x01 << ADC_IE_CH6FULL_Pos) +#define ADC_IE_CH7EOC_Pos 28 +#define ADC_IE_CH7EOC_Msk (0x01 << ADC_IE_CH7EOC_Pos) +#define ADC_IE_CH7OVF_Pos 29 +#define ADC_IE_CH7OVF_Msk (0x01 << ADC_IE_CH7OVF_Pos) +#define ADC_IE_CH7HFULL_Pos 30 +#define ADC_IE_CH7HFULL_Msk (0x01 << ADC_IE_CH7HFULL_Pos) +#define ADC_IE_CH7FULL_Pos 31 +//#define ADC_IE_CH7FULL_Msk (0x01 << ADC_IE_CH7FULL_Pos) 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濮ら敍锟� integer operation result is out of range +#define ADC_IE_CH7FULL_Msk ((uint32_t)0x01 << ADC_IE_CH7FULL_Pos) + +#define ADC_IF_CH0EOC_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0EOC_Msk (0x01 << ADC_IF_CH0EOC_Pos) +#define ADC_IF_CH0OVF_Pos 1 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0OVF_Msk (0x01 << ADC_IF_CH0OVF_Pos) +#define ADC_IF_CH0HFULL_Pos 2 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0HFULL_Msk (0x01 << ADC_IF_CH0HFULL_Pos) +#define ADC_IF_CH0FULL_Pos 3 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0FULL_Msk (0x01 << ADC_IF_CH0FULL_Pos) +#define ADC_IF_CH1EOC_Pos 4 +#define ADC_IF_CH1EOC_Msk (0x01 << ADC_IF_CH1EOC_Pos) +#define ADC_IF_CH1OVF_Pos 5 +#define ADC_IF_CH1OVF_Msk (0x01 << ADC_IF_CH1OVF_Pos) +#define ADC_IF_CH1HFULL_Pos 6 +#define ADC_IF_CH1HFULL_Msk (0x01 << ADC_IF_CH1HFULL_Pos) +#define ADC_IF_CH1FULL_Pos 7 +#define ADC_IF_CH1FULL_Msk (0x01 << ADC_IF_CH1FULL_Pos) +#define ADC_IF_CH2EOC_Pos 8 +#define ADC_IF_CH2EOC_Msk (0x01 << ADC_IF_CH2EOC_Pos) +#define ADC_IF_CH2OVF_Pos 9 +#define ADC_IF_CH2OVF_Msk (0x01 << ADC_IF_CH2OVF_Pos) +#define ADC_IF_CH2HFULL_Pos 10 +#define ADC_IF_CH2HFULL_Msk (0x01 << ADC_IF_CH2HFULL_Pos) +#define ADC_IF_CH2FULL_Pos 11 +#define ADC_IF_CH2FULL_Msk (0x01 << ADC_IF_CH2FULL_Pos) +#define ADC_IF_CH3EOC_Pos 12 +#define ADC_IF_CH3EOC_Msk (0x01 << ADC_IF_CH3EOC_Pos) +#define ADC_IF_CH3OVF_Pos 13 +#define ADC_IF_CH3OVF_Msk (0x01 << ADC_IF_CH3OVF_Pos) +#define ADC_IF_CH3HFULL_Pos 14 +#define ADC_IF_CH3HFULL_Msk (0x01 << ADC_IF_CH3HFULL_Pos) +#define ADC_IF_CH3FULL_Pos 15 +#define ADC_IF_CH3FULL_Msk (0x01 << ADC_IF_CH3FULL_Pos) +#define ADC_IF_CH4EOC_Pos 16 +#define ADC_IF_CH4EOC_Msk (0x01 << ADC_IF_CH4EOC_Pos) +#define ADC_IF_CH4OVF_Pos 17 +#define ADC_IF_CH4OVF_Msk (0x01 << ADC_IF_CH4OVF_Pos) +#define ADC_IF_CH4HFULL_Pos 18 +#define ADC_IF_CH4HFULL_Msk (0x01 << ADC_IF_CH4HFULL_Pos) +#define ADC_IF_CH4FULL_Pos 19 +#define ADC_IF_CH4FULL_Msk (0x01 << ADC_IF_CH4FULL_Pos) +#define ADC_IF_CH5EOC_Pos 20 +#define ADC_IF_CH5EOC_Msk (0x01 << ADC_IF_CH5EOC_Pos) +#define ADC_IF_CH5OVF_Pos 21 +#define ADC_IF_CH5OVF_Msk (0x01 << ADC_IF_CH5OVF_Pos) +#define ADC_IF_CH5HFULL_Pos 22 +#define ADC_IF_CH5HFULL_Msk (0x01 << ADC_IF_CH5HFULL_Pos) +#define ADC_IF_CH5FULL_Pos 23 +#define ADC_IF_CH5FULL_Msk (0x01 << ADC_IF_CH5FULL_Pos) +#define ADC_IF_CH6EOC_Pos 24 +#define ADC_IF_CH6EOC_Msk (0x01 << ADC_IF_CH6EOC_Pos) +#define ADC_IF_CH6OVF_Pos 25 +#define ADC_IF_CH6OVF_Msk (0x01 << ADC_IF_CH6OVF_Pos) +#define ADC_IF_CH6HFULL_Pos 26 +#define ADC_IF_CH6HFULL_Msk (0x01 << ADC_IF_CH6HFULL_Pos) +#define ADC_IF_CH6FULL_Pos 27 +#define ADC_IF_CH6FULL_Msk (0x01 << ADC_IF_CH6FULL_Pos) +#define ADC_IF_CH7EOC_Pos 28 +#define ADC_IF_CH7EOC_Msk (0x01 << ADC_IF_CH7EOC_Pos) +#define ADC_IF_CH7OVF_Pos 29 +#define ADC_IF_CH7OVF_Msk (0x01 << ADC_IF_CH7OVF_Pos) +#define ADC_IF_CH7HFULL_Pos 30 +#define ADC_IF_CH7HFULL_Msk (0x01 << ADC_IF_CH7HFULL_Pos) +#define ADC_IF_CH7FULL_Pos 31 +#define ADC_IF_CH7FULL_Msk (0x01 << ADC_IF_CH7FULL_Pos) + +#define ADC_STAT_EOC_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_STAT_EOC_Msk (0x01 << ADC_STAT_EOC_Pos) +#define ADC_STAT_OVF_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹鐎靛嫯鎻幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� +#define ADC_STAT_OVF_Msk (0x01 << ADC_STAT_OVF_Pos) +#define ADC_STAT_HFULL_Pos 2 +#define ADC_STAT_HFULL_Msk (0x01 << ADC_STAT_HFULL_Pos) +#define ADC_STAT_FULL_Pos 3 +#define ADC_STAT_FULL_Msk (0x01 << ADC_STAT_FULL_Pos) +#define ADC_STAT_EMPTY_Pos 4 +#define ADC_STAT_EMPTY_Msk (0x01 << ADC_STAT_EMPTY_Pos) + +#define ADC_CTRL1_RIN_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔封偓鐔稿闁跨喐鏋婚幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 1 105K 2 90K 3 75K 4 60K 5 45K 6 30K 7 15K +#define ADC_CTRL1_RIN_Msk (0x07 << ADC_CTRL1_RIN_Pos) + +#define ADC_CTRL2_RESET_Pos 0 //闁跨喐鏋婚幏鐑芥晸鐞涙顣幏鐤熅闁跨喐鏋婚幏铚傜秴 +#define ADC_CTRL2_RESET_Msk (0x01 << ADC_CTRL2_RESET_Pos) +#define ADC_CTRL2_ADCEVCM_Pos 1 //ADC External VCM闁跨喐鏋婚幏绋烡C闁跨喐鏋婚幏绋癎A闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔惰寧閿濆繑瀚归柨鐔哄珱缁愭牑妲勯幏鐑芥晸閿燂拷 +#define ADC_CTRL2_ADCEVCM_Msk (0x01 << ADC_CTRL2_ADCEVCM_Pos) +#define ADC_CTRL2_PGAIVCM_Pos 2 //PGA Internal VCM闁跨喐鏋婚幏绋癎A闁跨喐鏋婚幏鐑芥晸鐠囶偄鍙″Ο锟犳晸閺傘倖瀚归獮鎶解偓澶愭晸閺傘倖瀚� +#define ADC_CTRL2_PGAIVCM_Msk (0x01 << ADC_CTRL2_PGAIVCM_Pos) +#define ADC_CTRL2_PGAGAIN_Pos 3 //0 25.1dB 1 21.6dB 2 11.1dB 3 3.5dB 4 0dB(1.8V) 5 -2.9dB 6 -5.3dB +#define ADC_CTRL2_PGAGAIN_Msk (0x07 << ADC_CTRL2_PGAGAIN_Pos) +#define ADC_CTRL2_REFPOUT_Pos 23 //1 ADC 闁跨喕濡拠褎瀚� 1.2V REFP闁跨喐鏋婚幏宄板竾闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽宕扮缓宀碏P闁跨喐鏋婚幏鐑芥晸閼存熬缍囬幏鐑芥晸閺傘倖瀚归柨鐔诲Ν鐠囇勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤洣1.2V闁跨喕袙闁墽EFP閺冨爼鏁撻弬銈嗗閻線鏁撶紓瀛樺敾閹凤拷 +#define ADC_CTRL2_REFPOUT_Msk (0x01 << ADC_CTRL2_REFPOUT_Pos +#define ADC_CTRL2_CLKDIV_Pos 24 //閺冨爼鏁撻幒銉ュ殩閹风兘顣堕柨鐔告灮閹峰嘲褰ч柨鐔告灮閹烽攱妞傞柨鐔告灮閹烽攱绨稉绡怰C閺冨爼鏁撻弬銈嗗閺侊拷 +#define ADC_CTRL2_CLKDIV_Msk (0x1F << ADC_CTRL2_CLKDIV_Pos) +#define ADC_CTRL2_PGAVCM_Pos 29 +#define ADC_CTRL2_PGAVCM_Msk (((uint32_t)0x07) << ADC_CTRL2_PGAVCM_Pos) + +#define ADC_CALIBSET_OFFSET_Pos 0 +#define ADC_CALIBSET_OFFSET_Msk (0x1FF << ADC_CALIBSET_OFFSET_Pos) +#define ADC_CALIBSET_K_Pos 16 +#define ADC_CALIBSET_K_Msk (0x1FF << ADC_CALIBSET_K_Pos) + +#define ADC_CALIBEN_OFFSET_Pos 0 +#define ADC_CALIBEN_OFFSET_Msk (0x01 << ADC_CALIBEN_OFFSET_Pos) +#define ADC_CALIBEN_K_Pos 1 +#define ADC_CALIBEN_K_Msk (0x01 << ADC_CALIBEN_K_Pos) + +typedef struct +{ + __IO uint32_t MODE; //0 闁跨喐鏋婚幏鐑解偓姘佸蹇涙晸閺傘倖瀚笰闁跨喐鏋婚幏绋￠柨鐔告灮閹风柉鐭鹃柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + //1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏绋熼柨鐔告灮閹风ā闁跨喐鏋婚幏鐤熅闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶徊鍢怰A闁跨喐鏋婚幏绋↖GHA闁跨喐鏋婚幏鐑芥晸閻欌槄缍囬幏绋＄捄顖炴晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶槐姝岀熅闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸犳崘鎻幏鐑芥晸閺傘倖瀚归柨鐔烘たZA闁跨喐鏋婚幏绋B闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笰闁跨喐鏋婚幏绋＄捄顖炴晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归惉銉╂晸缂佺偞鍞婚幏鐑芥晸閿燂拷 + //2 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏宄版倱闁跨喐鏋婚幏鐑解偓姘佸蹇涙晸閺傘倖瀚归柨鐔告灮閹疯渹绔撮柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡悮瀛樺闁跨喓娈曠拋瑙勫閸嬫粍顒� + //3 闁跨喓娈曠粵瑙勫濡€崇础闁跨喐鏋婚幏绋熼柨鐔告灮閹风ā闁跨喐鏋婚幏鐤熅闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡拠褎瀚归柨鐔告灮閹疯渹绔撮柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸愩垽鏁撻弬銈嗗閻╂挳鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿疆娴兼瑦瀚归柨鐔告灮閹风兘鏁撻悪锛勵暜閹峰嘲绱￠柨鐔告灮閹风兘鏁撻幓顓濈串閹风兘鏁撻敓锟� + //4 闁跨喓娈曠粔棰佺串閹风兘鏁撻弬銈嗗濡€崇础闁跨喐鏋婚幏鐑芥晸閻ㄥ棛顒查幏閿嬆佸蹇涙晸闁板吀绱幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏鐑芥晸濡楁梻灏ㄩ幏锟� + + __IO uint32_t PERA; //[15:0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + + __IO uint32_t HIGHA; //[15:0] 闁跨喓顏喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏锟� + + __IO uint32_t DZA; //[9:0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻悪锛勵劜閹烽攱妞傞柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭亸蹇涙晸閺傘倖瀚笻IGHA + + __IO uint32_t PERB; + + __IO uint32_t HIGHB; + + __IO uint32_t DZB; + + __IO uint32_t INIOUT; //Init Output level闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻悪鈽呮嫹 +} PWM_TypeDef; + +#define PWM_INIOUT_PWMA_Pos 0 +#define PWM_INIOUT_PWMA_Msk (0x01 << PWM_INIOUT_PWMA_Pos) +#define PWM_INIOUT_PWMB_Pos 1 +#define PWM_INIOUT_PWMB_Msk (0x01 << PWM_INIOUT_PWMB_Pos) + +typedef struct +{ + __IO uint32_t FORCEH; + + __IO uint32_t ADTRG0A; + __IO uint32_t ADTRG0B; + + __IO uint32_t ADTRG1A; + __IO uint32_t ADTRG1B; + + __IO uint32_t ADTRG2A; + __IO uint32_t ADTRG2B; + + __IO uint32_t ADTRG3A; + __IO uint32_t ADTRG3B; + + __IO uint32_t ADTRG4A; + __IO uint32_t ADTRG4B; + + __IO uint32_t ADTRG5A; + __IO uint32_t ADTRG5B; + + uint32_t RESERVED[3]; + + __IO uint32_t HALT; //閸掑綊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + + __IO uint32_t CHEN; + + __IO uint32_t IE; + + __IO uint32_t IF; + + __IO uint32_t IM; //Interrupt Mask + + __IO uint32_t IRS; //Interrupt Raw Stat +} PWMG_TypeDef; + +#define PWMG_FORCEH_PWM0_Pos 0 +#define PWMG_FORCEH_PWM0_Msk (0x01 << PWMG_FORCEH_PWM0_Pos) +#define PWMG_FORCEH_PWM1_Pos 1 +#define PWMG_FORCEH_PWM1_Msk (0x01 << PWMG_FORCEH_PWM1_Pos) +#define PWMG_FORCEH_PWM2_Pos 2 +#define PWMG_FORCEH_PWM2_Msk (0x01 << PWMG_FORCEH_PWM2_Pos) +#define PWMG_FORCEH_PWM3_Pos 3 +#define PWMG_FORCEH_PWM3_Msk (0x01 << PWMG_FORCEH_PWM3_Pos) +#define PWMG_FORCEH_PWM4_Pos 4 +#define PWMG_FORCEH_PWM4_Msk (0x01 << PWMG_FORCEH_PWM4_Pos) +#define PWMG_FORCEH_PWM5_Pos 5 +#define PWMG_FORCEH_PWM5_Msk (0x01 << PWMG_FORCEH_PWM5_Pos) + +#define PWMG_ADTRG_VALUE_Pos 0 +#define PWMG_ADTRG_VALUE_Msk (0xFFFF << PWMG_ADTRG0A_VALUE_Pos) +#define PWMG_ADTRG_EVEN_Pos 16 //1 閸嬪爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鏅� 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define PWMG_ADTRG_EVEN_Msk (0x01 << PWMG_ADTRG0A_EVEN_Pos) +#define PWMG_ADTRG_EN_Pos 17 +#define PWMG_ADTRG_EN_Msk (0x01 << PWMG_ADTRG0A_EN_Pos) + +#define PWMG_HALT_EN_Pos 0 +#define PWMG_HALT_EN_Msk (0x01 << PWMG_HALT_EN_Pos) +#define PWMG_HALT_PWM0_Pos 1 +#define PWMG_HALT_PWM0_Msk (0x01 << PWMG_HALT_PWM0_Pos) +#define PWMG_HALT_PWM1_Pos 2 +#define PWMG_HALT_PWM1_Msk (0x01 << PWMG_HALT_PWM1_Pos) +#define PWMG_HALT_PWM2_Pos 3 +#define PWMG_HALT_PWM2_Msk (0x01 << PWMG_HALT_PWM2_Pos) +#define PWMG_HALT_PWM3_Pos 4 +#define PWMG_HALT_PWM3_Msk (0x01 << PWMG_HALT_PWM3_Pos) +#define PWMG_HALT_PWM4_Pos 5 +#define PWMG_HALT_PWM4_Msk (0x01 << PWMG_HALT_PWM4_Pos) +#define PWMG_HALT_PWM5_Pos 6 +#define PWMG_HALT_PWM5_Msk (0x01 << PWMG_HALT_PWM5_Pos) +#define PWMG_HALT_STOPCNT_Pos 7 //1 閸掑綊鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗PWM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎顫曢敍灞戒粻濮濄垽鏁撻弬銈嗗闁跨喐鏋婚幏锟� 0 閸掑綊鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗PWM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define PWMG_HALT_STOPCNT_Msk (0x01 << PWMG_HALT_STOPCNT_Pos) +#define PWMG_HALT_INLVL_Pos 8 //1 閸掑綊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崣鈺呮晸閻欌剝鏋婚幏鐑芥晸閸欘偓鎷� +#define PWMG_HALT_INLVL_Msk (0x01 << PWMG_HALT_INLVL_Pos) +#define PWMG_HALT_OUTLVL_Pos 9 //1 閸掑綊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏宄板渐闁跨喓瀚涢敓锟� +#define PWMG_HALT_OUTLVL_Msk (0x01 << PWMG_HALT_OUTLVL_Pos) +#define PWMG_HALT_STAT_Pos 10 //1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崚褰掓晸閺傘倖瀚� +#define PWMG_HALT_STAT_Msk (0x01 << PWMG_HALT_STAT_Pos) + +#define PWMG_CHEN_PWM0A_Pos 0 +#define PWMG_CHEN_PWM0A_Msk (0x01 << PWMG_CHEN_PWM0A_Pos) +#define PWMG_CHEN_PWM0B_Pos 1 +#define PWMG_CHEN_PWM0B_Msk (0x01 << PWMG_CHEN_PWM0B_Pos) +#define PWMG_CHEN_PWM1A_Pos 2 +#define PWMG_CHEN_PWM1A_Msk (0x01 << PWMG_CHEN_PWM1A_Pos) +#define PWMG_CHEN_PWM1B_Pos 3 +#define PWMG_CHEN_PWM1B_Msk (0x01 << PWMG_CHEN_PWM1B_Pos) +#define PWMG_CHEN_PWM2A_Pos 4 +#define PWMG_CHEN_PWM2A_Msk (0x01 << PWMG_CHEN_PWM2A_Pos) +#define PWMG_CHEN_PWM2B_Pos 5 +#define PWMG_CHEN_PWM2B_Msk (0x01 << PWMG_CHEN_PWM2B_Pos) +#define PWMG_CHEN_PWM3A_Pos 6 +#define PWMG_CHEN_PWM3A_Msk (0x01 << PWMG_CHEN_PWM3A_Pos) +#define PWMG_CHEN_PWM3B_Pos 7 +#define PWMG_CHEN_PWM3B_Msk (0x01 << PWMG_CHEN_PWM3B_Pos) +#define PWMG_CHEN_PWM4A_Pos 8 +#define PWMG_CHEN_PWM4A_Msk (0x01 << PWMG_CHEN_PWM4A_Pos) +#define PWMG_CHEN_PWM4B_Pos 9 +#define PWMG_CHEN_PWM4B_Msk (0x01 << PWMG_CHEN_PWM4B_Pos) +#define PWMG_CHEN_PWM5A_Pos 10 +#define PWMG_CHEN_PWM5A_Msk (0x01 << PWMG_CHEN_PWM5A_Pos) +#define PWMG_CHEN_PWM5B_Pos 11 +#define PWMG_CHEN_PWM5B_Msk (0x01 << PWMG_CHEN_PWM5B_Pos) + +#define PWMG_IE_NEWP0A_Pos 0 +#define PWMG_IE_NEWP0A_Msk (0x01 << PWMG_IE_NEWP0A_Pos) +#define PWMG_IE_NEWP0B_Pos 1 +#define PWMG_IE_NEWP0B_Msk (0x01 << PWMG_IE_NEWP0B_Pos) +#define PWMG_IE_NEWP1A_Pos 2 +#define PWMG_IE_NEWP1A_Msk (0x01 << PWMG_IE_NEWP1A_Pos) +#define PWMG_IE_NEWP1B_Pos 3 +#define PWMG_IE_NEWP1B_Msk (0x01 << PWMG_IE_NEWP1B_Pos) +#define PWMG_IE_NEWP2A_Pos 4 +#define PWMG_IE_NEWP2A_Msk (0x01 << PWMG_IE_NEWP2A_Pos) +#define PWMG_IE_NEWP2B_Pos 5 +#define PWMG_IE_NEWP2B_Msk (0x01 << PWMG_IE_NEWP2B_Pos) +#define PWMG_IE_NEWP3A_Pos 6 +#define PWMG_IE_NEWP3A_Msk (0x01 << PWMG_IE_NEWP3A_Pos) +#define PWMG_IE_NEWP3B_Pos 7 +#define PWMG_IE_NEWP3B_Msk (0x01 << PWMG_IE_NEWP3B_Pos) +#define PWMG_IE_NEWP4A_Pos 8 +#define PWMG_IE_NEWP4A_Msk (0x01 << PWMG_IE_NEWP4A_Pos) +#define PWMG_IE_NEWP4B_Pos 9 +#define PWMG_IE_NEWP4B_Msk (0x01 << PWMG_IE_NEWP4B_Pos) +#define PWMG_IE_NEWP5A_Pos 10 +#define PWMG_IE_NEWP5A_Msk (0x01 << PWMG_IE_NEWP5A_Pos) +#define PWMG_IE_NEWP5B_Pos 11 +#define PWMG_IE_NEWP5B_Msk (0x01 << PWMG_IE_NEWP5B_Pos) +#define PWMG_IE_HEND0A_Pos 12 +#define PWMG_IE_HEND0A_Msk (0x01 << PWMG_IE_HEND0A_Pos) +#define PWMG_IE_HEND0B_Pos 13 +#define PWMG_IE_HEND0B_Msk (0x01 << PWMG_IE_HEND0B_Pos) +#define PWMG_IE_HEND1A_Pos 14 +#define PWMG_IE_HEND1A_Msk (0x01 << PWMG_IE_HEND1A_Pos) +#define PWMG_IE_HEND1B_Pos 15 +#define PWMG_IE_HEND1B_Msk (0x01 << PWMG_IE_HEND1B_Pos) +#define PWMG_IE_HEND2A_Pos 16 +#define PWMG_IE_HEND2A_Msk (0x01 << PWMG_IE_HEND2A_Pos) +#define PWMG_IE_HEND2B_Pos 17 +#define PWMG_IE_HEND2B_Msk (0x01 << PWMG_IE_HEND2B_Pos) +#define PWMG_IE_HEND3A_Pos 18 +#define PWMG_IE_HEND3A_Msk (0x01 << PWMG_IE_HEND3A_Pos) +#define PWMG_IE_HEND3B_Pos 19 +#define PWMG_IE_HEND3B_Msk (0x01 << PWMG_IE_HEND3B_Pos) +#define PWMG_IE_HEND4A_Pos 20 +#define PWMG_IE_HEND4A_Msk (0x01 << PWMG_IE_HEND4A_Pos) +#define PWMG_IE_HEND4B_Pos 21 +#define PWMG_IE_HEND4B_Msk (0x01 << PWMG_IE_HEND4B_Pos) +#define PWMG_IE_HEND5A_Pos 22 +#define PWMG_IE_HEND5A_Msk (0x01 << PWMG_IE_HEND5A_Pos) +#define PWMG_IE_HEND5B_Pos 23 +#define PWMG_IE_HEND5B_Msk (0x01 << PWMG_IE_HEND5B_Pos) +#define PWMG_IE_HALT_Pos 24 +#define PWMG_IE_HALT_Msk (0x01 << PWMG_IE_HALT_Pos) + +#define PWMG_IF_NEWP0A_Pos 0 +#define PWMG_IF_NEWP0A_Msk (0x01 << PWMG_IF_NEWP0A_Pos) +#define PWMG_IF_NEWP0B_Pos 1 +#define PWMG_IF_NEWP0B_Msk (0x01 << PWMG_IF_NEWP0B_Pos) +#define PWMG_IF_NEWP1A_Pos 2 +#define PWMG_IF_NEWP1A_Msk (0x01 << PWMG_IF_NEWP1A_Pos) +#define PWMG_IF_NEWP1B_Pos 3 +#define PWMG_IF_NEWP1B_Msk (0x01 << PWMG_IF_NEWP1B_Pos) +#define PWMG_IF_NEWP2A_Pos 4 +#define PWMG_IF_NEWP2A_Msk (0x01 << PWMG_IF_NEWP2A_Pos) +#define PWMG_IF_NEWP2B_Pos 5 +#define PWMG_IF_NEWP2B_Msk (0x01 << PWMG_IF_NEWP2B_Pos) +#define PWMG_IF_NEWP3A_Pos 6 +#define PWMG_IF_NEWP3A_Msk (0x01 << PWMG_IF_NEWP3A_Pos) +#define PWMG_IF_NEWP3B_Pos 7 +#define PWMG_IF_NEWP3B_Msk (0x01 << PWMG_IF_NEWP3B_Pos) +#define PWMG_IF_NEWP4A_Pos 8 +#define PWMG_IF_NEWP4A_Msk (0x01 << PWMG_IF_NEWP4A_Pos) +#define PWMG_IF_NEWP4B_Pos 9 +#define PWMG_IF_NEWP4B_Msk (0x01 << PWMG_IF_NEWP4B_Pos) +#define PWMG_IF_NEWP5A_Pos 10 +#define PWMG_IF_NEWP5A_Msk (0x01 << PWMG_IF_NEWP5A_Pos) +#define PWMG_IF_NEWP5B_Pos 11 +#define PWMG_IF_NEWP5B_Msk (0x01 << PWMG_IF_NEWP5B_Pos) +#define PWMG_IF_HEND0A_Pos 12 +#define PWMG_IF_HEND0A_Msk (0x01 << PWMG_IF_HEND0A_Pos) +#define PWMG_IF_HEND0B_Pos 13 +#define PWMG_IF_HEND0B_Msk (0x01 << PWMG_IF_HEND0B_Pos) +#define PWMG_IF_HEND1A_Pos 14 +#define PWMG_IF_HEND1A_Msk (0x01 << PWMG_IF_HEND1A_Pos) +#define PWMG_IF_HEND1B_Pos 15 +#define PWMG_IF_HEND1B_Msk (0x01 << PWMG_IF_HEND1B_Pos) +#define PWMG_IF_HEND2A_Pos 16 +#define PWMG_IF_HEND2A_Msk (0x01 << PWMG_IF_HEND2A_Pos) +#define PWMG_IF_HEND2B_Pos 17 +#define PWMG_IF_HEND2B_Msk (0x01 << PWMG_IF_HEND2B_Pos) +#define PWMG_IF_HEND3A_Pos 18 +#define PWMG_IF_HEND3A_Msk (0x01 << PWMG_IF_HEND3A_Pos) +#define PWMG_IF_HEND3B_Pos 19 +#define PWMG_IF_HEND3B_Msk (0x01 << PWMG_IF_HEND3B_Pos) +#define PWMG_IF_HEND4A_Pos 20 +#define PWMG_IF_HEND4A_Msk (0x01 << PWMG_IF_HEND4A_Pos) +#define PWMG_IF_HEND4B_Pos 21 +#define PWMG_IF_HEND4B_Msk (0x01 << PWMG_IF_HEND4B_Pos) +#define PWMG_IF_HEND5A_Pos 22 +#define PWMG_IF_HEND5A_Msk (0x01 << PWMG_IF_HEND5A_Pos) +#define PWMG_IF_HEND5B_Pos 23 +#define PWMG_IF_HEND5B_Msk (0x01 << PWMG_IF_HEND5B_Pos) +#define PWMG_IF_HALT_Pos 24 +#define PWMG_IF_HALT_Msk (0x01 << PWMG_IF_HALT_Pos) + +#define PWMG_IM_NEWP0A_Pos 0 //Interrupt Mask +#define PWMG_IM_NEWP0A_Msk (0x01 << PWMG_IM_NEWP0A_Pos) +#define PWMG_IM_NEWP0B_Pos 1 +#define PWMG_IM_NEWP0B_Msk (0x01 << PWMG_IM_NEWP0B_Pos) +#define PWMG_IM_NEWP1A_Pos 2 +#define PWMG_IM_NEWP1A_Msk (0x01 << PWMG_IM_NEWP1A_Pos) +#define PWMG_IM_NEWP1B_Pos 3 +#define PWMG_IM_NEWP1B_Msk (0x01 << PWMG_IM_NEWP1B_Pos) +#define PWMG_IM_NEWP2A_Pos 4 +#define PWMG_IM_NEWP2A_Msk (0x01 << PWMG_IM_NEWP2A_Pos) +#define PWMG_IM_NEWP2B_Pos 5 +#define PWMG_IM_NEWP2B_Msk (0x01 << PWMG_IM_NEWP2B_Pos) +#define PWMG_IM_NEWP3A_Pos 6 +#define PWMG_IM_NEWP3A_Msk (0x01 << PWMG_IM_NEWP3A_Pos) +#define PWMG_IM_NEWP3B_Pos 7 +#define PWMG_IM_NEWP3B_Msk (0x01 << PWMG_IM_NEWP3B_Pos) +#define PWMG_IM_NEWP4A_Pos 8 +#define PWMG_IM_NEWP4A_Msk (0x01 << PWMG_IM_NEWP4A_Pos) +#define PWMG_IM_NEWP4B_Pos 9 +#define PWMG_IM_NEWP4B_Msk (0x01 << PWMG_IM_NEWP4B_Pos) +#define PWMG_IM_NEWP5A_Pos 10 +#define PWMG_IM_NEWP5A_Msk (0x01 << PWMG_IM_NEWP5A_Pos) +#define PWMG_IM_NEWP5B_Pos 11 +#define PWMG_IM_NEWP5B_Msk (0x01 << PWMG_IM_NEWP5B_Pos) +#define PWMG_IM_HEND0A_Pos 12 +#define PWMG_IM_HEND0A_Msk (0x01 << PWMG_IM_HEND0A_Pos) +#define PWMG_IM_HEND0B_Pos 13 +#define PWMG_IM_HEND0B_Msk (0x01 << PWMG_IM_HEND0B_Pos) +#define PWMG_IM_HEND1A_Pos 14 +#define PWMG_IM_HEND1A_Msk (0x01 << PWMG_IM_HEND1A_Pos) +#define PWMG_IM_HEND1B_Pos 15 +#define PWMG_IM_HEND1B_Msk (0x01 << PWMG_IM_HEND1B_Pos) +#define PWMG_IM_HEND2A_Pos 16 +#define PWMG_IM_HEND2A_Msk (0x01 << PWMG_IM_HEND2A_Pos) +#define PWMG_IM_HEND2B_Pos 17 +#define PWMG_IM_HEND2B_Msk (0x01 << PWMG_IM_HEND2B_Pos) +#define PWMG_IM_HEND3A_Pos 18 +#define PWMG_IM_HEND3A_Msk (0x01 << PWMG_IM_HEND3A_Pos) +#define PWMG_IM_HEND3B_Pos 19 +#define PWMG_IM_HEND3B_Msk (0x01 << PWMG_IM_HEND3B_Pos) +#define PWMG_IM_HEND4A_Pos 20 +#define PWMG_IM_HEND4A_Msk (0x01 << PWMG_IM_HEND4A_Pos) +#define PWMG_IM_HEND4B_Pos 21 +#define PWMG_IM_HEND4B_Msk (0x01 << PWMG_IM_HEND4B_Pos) +#define PWMG_IM_HEND5A_Pos 22 +#define PWMG_IM_HEND5A_Msk (0x01 << PWMG_IM_HEND5A_Pos) +#define PWMG_IM_HEND5B_Pos 23 +#define PWMG_IM_HEND5B_Msk (0x01 << PWMG_IM_HEND5B_Pos) +#define PWMG_IM_HALT_Pos 24 +#define PWMG_IM_HALT_Msk (0x01 << PWMG_IM_HALT_Pos) + +#define PWMG_IRS_NEWP0A_Pos 0 //Interrupt Raw State +#define PWMG_IRS_NEWP0A_Msk (0x01 << PWMG_IRS_NEWP0A_Pos) +#define PWMG_IRS_NEWP0B_Pos 1 +#define PWMG_IRS_NEWP0B_Msk (0x01 << PWMG_IRS_NEWP0B_Pos) +#define PWMG_IRS_NEWP1A_Pos 2 +#define PWMG_IRS_NEWP1A_Msk (0x01 << PWMG_IRS_NEWP1A_Pos) +#define PWMG_IRS_NEWP1B_Pos 3 +#define PWMG_IRS_NEWP1B_Msk (0x01 << PWMG_IRS_NEWP1B_Pos) +#define PWMG_IRS_NEWP2A_Pos 4 +#define PWMG_IRS_NEWP2A_Msk (0x01 << PWMG_IRS_NEWP2A_Pos) +#define PWMG_IRS_NEWP2B_Pos 5 +#define PWMG_IRS_NEWP2B_Msk (0x01 << PWMG_IRS_NEWP2B_Pos) +#define PWMG_IRS_NEWP3A_Pos 6 +#define PWMG_IRS_NEWP3A_Msk (0x01 << PWMG_IRS_NEWP3A_Pos) +#define PWMG_IRS_NEWP3B_Pos 7 +#define PWMG_IRS_NEWP3B_Msk (0x01 << PWMG_IRS_NEWP3B_Pos) +#define PWMG_IRS_NEWP4A_Pos 8 +#define PWMG_IRS_NEWP4A_Msk (0x01 << PWMG_IRS_NEWP4A_Pos) +#define PWMG_IRS_NEWP4B_Pos 9 +#define PWMG_IRS_NEWP4B_Msk (0x01 << PWMG_IRS_NEWP4B_Pos) +#define PWMG_IRS_NEWP5A_Pos 10 +#define PWMG_IRS_NEWP5A_Msk (0x01 << PWMG_IRS_NEWP5A_Pos) +#define PWMG_IRS_NEWP5B_Pos 11 +#define PWMG_IRS_NEWP5B_Msk (0x01 << PWMG_IRS_NEWP5B_Pos) +#define PWMG_IRS_HEND0A_Pos 12 +#define PWMG_IRS_HEND0A_Msk (0x01 << PWMG_IRS_HEND0A_Pos) +#define PWMG_IRS_HEND0B_Pos 13 +#define PWMG_IRS_HEND0B_Msk (0x01 << PWMG_IRS_HEND0B_Pos) +#define PWMG_IRS_HEND1A_Pos 14 +#define PWMG_IRS_HEND1A_Msk (0x01 << PWMG_IRS_HEND1A_Pos) +#define PWMG_IRS_HEND1B_Pos 15 +#define PWMG_IRS_HEND1B_Msk (0x01 << PWMG_IRS_HEND1B_Pos) +#define PWMG_IRS_HEND2A_Pos 16 +#define PWMG_IRS_HEND2A_Msk (0x01 << PWMG_IRS_HEND2A_Pos) +#define PWMG_IRS_HEND2B_Pos 17 +#define PWMG_IRS_HEND2B_Msk (0x01 << PWMG_IRS_HEND2B_Pos) +#define PWMG_IRS_HEND3A_Pos 18 +#define PWMG_IRS_HEND3A_Msk (0x01 << PWMG_IRS_HEND3A_Pos) +#define PWMG_IRS_HEND3B_Pos 19 +#define PWMG_IRS_HEND3B_Msk (0x01 << PWMG_IRS_HEND3B_Pos) +#define PWMG_IRS_HEND4A_Pos 20 +#define PWMG_IRS_HEND4A_Msk (0x01 << PWMG_IRS_HEND4A_Pos) +#define PWMG_IRS_HEND4B_Pos 21 +#define PWMG_IRS_HEND4B_Msk (0x01 << PWMG_IRS_HEND4B_Pos) +#define PWMG_IRS_HEND5A_Pos 22 +#define PWMG_IRS_HEND5A_Msk (0x01 << PWMG_IRS_HEND5A_Pos) +#define PWMG_IRS_HEND5B_Pos 23 +#define PWMG_IRS_HEND5B_Msk (0x01 << PWMG_IRS_HEND5B_Pos) +#define PWMG_IRS_HALT_Pos 24 +#define PWMG_IRS_HALT_Msk (0x01 << PWMG_IRS_HALT_Pos) + +typedef struct +{ + __IO uint32_t EN; //[0] ENABLE + + __IO uint32_t IE; //閸欘亪鏁撻弬銈嗗娑擄拷1閺冨爼鏁撻弬銈嗗IF[CHx]闁跨喐鏋婚幏绋A闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶紒鐐村敾閹风兘鏁撻弬銈嗗姒ф瑩鏁撴潪鍖℃嫹1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹绔撮惄鎾晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗0 + + __IO uint32_t IM; //闁跨喐鏋婚幏铚傝礋1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏铚傚▏IF[CHx]娑擄拷1闁跨喐鏋婚幏绌宮a_int娑旂喖鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崥顕€鏁撻敓锟�1 + + __IO uint32_t IF; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + + uint32_t RESERVED[12]; + + struct + { + __IO uint32_t CR; + + __IO uint32_t AM; //Adress Mode + + __IO uint32_t SRC; + + __IO uint32_t SRCSGADDR1; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + + __IO uint32_t SRCSGADDR2; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + + __IO uint32_t SRCSGADDR3; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + + __IO uint32_t SRCSGLEN; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + + __IO uint32_t DST; + + __IO uint32_t DSTSGADDR1; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + + __IO uint32_t DSTSGADDR2; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + + __IO uint32_t DSTSGADDR3; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + + __IO uint32_t DSTSGLEN; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + + uint32_t RESERVED[4]; + } CH[3]; +} DMA_TypeDef; + +#define DMA_IE_CH0_Pos 0 +#define DMA_IE_CH0_Msk (0x01 << DMA_IE_CH0_Pos) +#define DMA_IE_CH1_Pos 1 +#define DMA_IE_CH1_Msk (0x01 << DMA_IE_CH1_Pos) +#define DMA_IE_CH2_Pos 2 +#define DMA_IE_CH2_Msk (0x01 << DMA_IE_CH2_Pos) +#define DMA_IE_CH3_Pos 3 +#define DMA_IE_CH3_Msk (0x01 << DMA_IE_CH3_Pos) +#define DMA_IE_CH4_Pos 4 +#define DMA_IE_CH4_Msk (0x01 << DMA_IE_CH4_Pos) +#define DMA_IE_CH5_Pos 5 +#define DMA_IE_CH5_Msk (0x01 << DMA_IE_CH5_Pos) +#define DMA_IE_CH6_Pos 6 +#define DMA_IE_CH6_Msk (0x01 << DMA_IE_CH6_Pos) +#define DMA_IE_CH7_Pos 7 +#define DMA_IE_CH7_Msk (0x01 << DMA_IE_CH7_Pos) + +#define DMA_IM_CH0_Pos 0 +#define DMA_IM_CH0_Msk (0x01 << DMA_IM_CH0_Pos) +#define DMA_IM_CH1_Pos 1 +#define DMA_IM_CH1_Msk (0x01 << DMA_IM_CH1_Pos) +#define DMA_IM_CH2_Pos 2 +#define DMA_IM_CH2_Msk (0x01 << DMA_IM_CH2_Pos) +#define DMA_IM_CH3_Pos 3 +#define DMA_IM_CH3_Msk (0x01 << DMA_IM_CH3_Pos) +#define DMA_IM_CH4_Pos 4 +#define DMA_IM_CH4_Msk (0x01 << DMA_IM_CH4_Pos) +#define DMA_IM_CH5_Pos 5 +#define DMA_IM_CH5_Msk (0x01 << DMA_IM_CH5_Pos) +#define DMA_IM_CH6_Pos 6 +#define DMA_IM_CH6_Msk (0x01 << DMA_IM_CH6_Pos) +#define DMA_IM_CH7_Pos 7 +#define DMA_IM_CH7_Msk (0x01 << DMA_IM_CH7_Pos) + +#define DMA_IF_CH0_Pos 0 +#define DMA_IF_CH0_Msk (0x01 << DMA_IF_CH0_Pos) +#define DMA_IF_CH1_Pos 1 +#define DMA_IF_CH1_Msk (0x01 << DMA_IF_CH1_Pos) +#define DMA_IF_CH2_Pos 2 +#define DMA_IF_CH2_Msk (0x01 << DMA_IF_CH2_Pos) +#define DMA_IF_CH3_Pos 3 +#define DMA_IF_CH3_Msk (0x01 << DMA_IF_CH3_Pos) +#define DMA_IF_CH4_Pos 4 +#define DMA_IF_CH4_Msk (0x01 << DMA_IF_CH4_Pos) +#define DMA_IF_CH5_Pos 5 +#define DMA_IF_CH5_Msk (0x01 << DMA_IF_CH5_Pos) +#define DMA_IF_CH6_Pos 6 +#define DMA_IF_CH6_Msk (0x01 << DMA_IF_CH6_Pos) +#define DMA_IF_CH7_Pos 7 +#define DMA_IF_CH7_Msk (0x01 << DMA_IF_CH7_Pos) + +#define DMA_CR_LEN_Pos 0 //闁跨喐鏋婚幏鐑解偓姘舵晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐婢冪粵瑙勫闁跨喖銈洪敐蹇斿0闁跨喐鏋婚幏宄扮安1闁跨喕顢滈懞鍌︾秶閹风兘鏁撻弬銈嗗闁跨噦鎷�4096闁跨喕顢滈弬銈嗗 +#define DMA_CR_LEN_Msk (0xFFF << DMA_CR_LEN_Pos) +#define DMA_CR_RXEN_Pos 16 +#define DMA_CR_RXEN_Msk (0x01 << DMA_CR_RXEN_Pos) +#define DMA_CR_TXEN_Pos 17 +#define DMA_CR_TXEN_Msk (0x01 << DMA_CR_TXEN_Pos) +#define DMA_CR_AUTORE_Pos 18 //Auto Restart, 闁岸鏁撻弬銈嗗闁跨喕濡潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚瑰▎鐘绘晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨噦鎷� +#define DMA_CR_AUTORE_Msk (0x01 << DMA_CR_AUTORE_Pos) + +#define DMA_AM_SRCAM_Pos 0 //Address Mode 0 闁跨喐鏋婚幏宄版絻闁跨喐鏆€鐠佽瀚� 1 闁跨喐鏋婚幏宄版絻闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 2 scatter gather濡€崇础 +#define DMA_AM_SRCAM_Msk (0x03 << DMA_AM_SRCAM_Pos) +#define DMA_AM_DSTAM_Pos 8 +#define DMA_AM_DSTAM_Msk (0x03 << DMA_AM_DSTAM_Pos) +#define DMA_AM_BURST_Pos 16 +#define DMA_AM_BURST_Msk (0x01 << DMA_AM_BURST_Pos) + +typedef struct +{ + __IO uint32_t CR; //Control Register + + __O uint32_t CMD; //Command Register + + __I uint32_t SR; //Status Register + + __I uint32_t IF; //Interrupt Flag + + __IO uint32_t IE; //Interrupt Enable + + uint32_t RESERVED; + + __IO uint32_t BT0; //Bit Time Register 0 + + __IO uint32_t BT1; //Bit Time Register 1 + + uint32_t RESERVED2[3]; + + __I uint32_t ALC; //Arbitration Lost Capture, 闁跨喎濮憗浣筋啇閹峰嘲銇戦柨鐔告灮閹烽攱宕� + + __I uint32_t ECC; //Error code capture, 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鐧岄煫璇ф嫹 + + __IO uint32_t EWLIM; //Error Warning Limit, 闁跨喐鏋婚幏鐑芥晸鐟楃喐濮ら幘鍛闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + + __IO uint32_t RXERR; //RX闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + + __IO uint32_t TXERR; //TX闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + + union + { + struct //闁跨喕濡棃鈺傚娴ｅ秵妞傞柨鐔哄嵆鐠佽瀚归崘娆撴晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喖鎽拠褎瀚归柨鐔哄嵆閸戙倖瀚归柨鐔告灮閹凤拷 + { + __IO uint32_t ACR[4]; //Acceptance Check Register, 闁跨喐鏋婚幏鐑芥晸缁夌ǹ鐦庢潏鐐闁跨喐鏋婚幏锟� + + __IO uint32_t AMR[4]; //Acceptance Mask Register, 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍨槑鏉堢偓瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏宄扮安娴ｅ秴鍟�0闁跨喐鏋婚幏绋〥闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楃姵濯烽柨鐔告灮閹风兘鏁撻悪掳鍎婚幏鐑芥晸閿燂拷 + + uint32_t RESERVED[5]; + } FILTER; + + union //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬆佸蹇涙晸闁炬澘褰茬拋瑙勫閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴閺冨爼鏁撻弬銈嗗闁跨喓鍗抽崙銈嗗闁跨喐鏋婚幏锟� + { + struct + { + __O uint32_t INFO; + + __O uint32_t DATA[12]; + } TXFRAME; + + struct + { + __I uint32_t INFO; + + __I uint32_t DATA[12]; + } RXFRAME; + }; + }; + + __I uint32_t RMCNT; //Receive Message Count + + uint32_t RESERVED3[66]; + + struct //TXFRAME闁跨喍鑼庣拋瑙勫闁跨喐甯撮崠鈩冨 + { + __I uint32_t INFO; + + __I uint32_t DATA[12]; + } TXFRAME_R; +} CAN_TypeDef; + +#define CAN_CR_RST_Pos 0 +#define CAN_CR_RST_Msk (0x01 << CAN_CR_RST_Pos) +#define CAN_CR_LOM_Pos 1 //Listen Only Mode +#define CAN_CR_LOM_Msk (0x01 << CAN_CR_LOM_Pos) +#define CAN_CR_STM_Pos 2 //Self Test Mode, 闁跨喐鏋婚幏閿嬆佸蹇涙晸闁炬壆銆嬮幏铚傚▏濞岋繝鏁撻弬銈嗗鎼存棃鏁撻弬銈嗗CAN闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹绡冮柨鐔告灮閹风兘鏁撻惃鍡樺灇閻у憡瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define CAN_CR_STM_Msk (0x01 << CAN_CR_STM_Pos) +#define CAN_CR_AFM_Pos 3 //Acceptance Filter Mode, 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎澹欑拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗32娴ｅ秹鏁撻弬銈嗗 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎澹欑拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗16娴ｅ秹鏁撻弬銈嗗 +#define CAN_CR_AFM_Msk (0x01 << CAN_CR_AFM_Pos) +#define CAN_CR_SLEEP_Pos 4 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归惈锟犳晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶粩顓熸た閸斻劑鏁撻弬銈嗗闁跨喎褰ㄧ拋瑙勫閺冨爼鏁撻弬銈嗗闁跨喓鐛ょ拠褎瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濞囬敓锟� +#define CAN_CR_SLEEP_Msk (0x01 << CAN_CR_SLEEP_Pos) +#define CAN_CR_DMAEN_Pos 5 +#define CAN_CR_DMAEN_Msk (0x01 << CAN_CR_DMAEN_Pos) + +#define CAN_CMD_TXREQ_Pos 0 //Transmission Request +#define CAN_CMD_TXREQ_Msk (0x01 << CAN_CMD_TXREQ_Pos) +#define CAN_CMD_ABTTX_Pos 1 //Abort Transmission +#define CAN_CMD_ABTTX_Msk (0x01 << CAN_CMD_ABTTX_Pos) +#define CAN_CMD_RRB_Pos 2 //Release Receive Buffer +#define CAN_CMD_RRB_Msk (0x01 << CAN_CMD_RRB_Pos) +#define CAN_CMD_CLROV_Pos 3 //Clear Data Overrun +#define CAN_CMD_CLROV_Msk (0x01 << CAN_CMD_CLROV_Pos) +#define CAN_CMD_SRR_Pos 4 //Self Reception Request +#define CAN_CMD_SRR_Msk (0x01 << CAN_CMD_SRR_Pos) + +#define CAN_SR_RXDA_Pos 0 //Receive Data Available闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风éIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬩紖闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏宄板絿 +#define CAN_SR_RXDA_Msk (0x01 << CAN_SR_RXDA_Pos) +#define CAN_SR_RXOV_Pos 1 //Receive FIFO Overrun闁跨喐鏋婚幏鐑芥晸闁剧増鏋婚幏鐑芥晸缁夊摜顣幏鐑芥晸閺傘倖瀚归幁顖炴晸閺傘倖瀚归柨鐔诲Ν閺傘倖瀚归柨鐔告灮閹风éIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define CAN_SR_RXOV_Msk (0x01 << CAN_SR_RXOV_Pos) +#define CAN_SR_TXBR_Pos 2 //Transmit Buffer Release闁跨喐鏋婚幏锟�0 闁跨喐鏋婚幏鐑芥晸閼哄倽鎻幏鐑芥晸閺傘倖瀚归崜宥夋晸閺傘倖瀚规慨鍡涙晸閺傘倖瀚归崑婊堟晸閺傘倖瀚归柨鐔告灮閹风柉鐦柨鐔告灮閹风兘鏁撻崣顐ユ彧閹烽顣遍柨鐔告灮閹风兘鏁撴潏鍐挎嫹 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崘娆撴晸閺傘倖瀚归柨鐔兼應绾板瀚归柨鐔告灮閹烽攱浼呴柨鐔告灮閹风兘鏁撻弬銈嗗 +#define CAN_SR_TXBR_Msk (0x01 << CAN_SR_TXBR_Pos) +#define CAN_SR_TXOK_Pos 3 //Transmit OK闁跨喐鏋婚幏绌漸ccessfully completed +#define CAN_SR_TXOK_Msk (0x01 << CAN_SR_TXOK_Pos) +#define CAN_SR_RXBUSY_Pos 4 //Receive Busy闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閺傘倖瀚归柨鐔告灮閹凤拷 +#define CAN_SR_RXBUSY_Msk (0x01 << CAN_SR_RXBUSY_Pos) +#define CAN_SR_TXBUSY_Pos 5 //Transmit Busy闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閸戙倖瀚归柨鐔告灮閹凤拷 +#define CAN_SR_TXBUSY_Msk (0x01 << CAN_SR_TXBUSY_Pos) +#define CAN_SR_ERRWARN_Pos 6 //1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁垮骏鎷� Warning Limit +#define CAN_SR_ERRWARN_Msk (0x01 << CAN_SR_ERRWARN_Pos) +#define CAN_SR_BUSOFF_Pos 7 //1 CAN 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔侯仾閸忚櫕鍞婚幏椋庡Ц閹線鏁撻弬銈嗗濞岋繝鏁撻崣顐ヮ嚋閹风兘鏁撶拠顐㈠煂闁跨喐鏋婚幏鐑芥晸缁旑厽妞块崝锟� +#define CAN_SR_BUSOFF_Msk (0x01 << CAN_SR_BUSOFF_Pos) + +#define CAN_IF_RXDA_Pos 0 //IF.RXDA = SR.RXDA & IE.RXDA +#define CAN_IF_RXDA_Msk (0x01 << CAN_IF_RXDA_Pos) +#define CAN_IF_TXBR_Pos 1 //闁跨喐鏋婚幏绋〦.TXBR=1閺冨爼鏁撻弬銈嗗SR.TXBR闁跨喐鏋婚幏锟�0闁跨喐鏋婚幏鐑芥晸閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚规担锟� +#define CAN_IF_TXBR_Msk (0x01 << CAN_IF_TXBR_Pos) +#define CAN_IF_ERRWARN_Pos 2 //闁跨喐鏋婚幏绋〦.ERRWARN=1閺冨爼鏁撻弬銈嗗SR.ERRWARN闁跨喐鏋婚幏绋碦.BUSOFF 0-to-1 闁跨喐鏋婚幏锟� 1-to-0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚规担锟� +#define CAN_IF_ERRWARN_Msk (0x01 << CAN_IF_ERRWARN_Pos) +#define CAN_IF_RXOV_Pos 3 //IF.RXOV = SR.RXOV & IE.RXOV +#define CAN_IF_RXOV_Msk (0x01 << CAN_IF_RXOV_Pos) +#define CAN_IF_WKUP_Pos 4 //闁跨喐鏋婚幏绋〦.WKUP=1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庢蒋闁跨喐鏋婚幏閿嬆佸蹇涙晸闁炬壆顣幏绋N闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閻涚偓鏋婚幏鐑芥晸閺傘倖瀚归崨瀣澔椤曞灝绨㈢拠褎瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹 +#define CAN_IF_WKUP_Msk (0x01 << CAN_IF_WKUP_Pos) +#define CAN_IF_ERRPASS_Pos 5 // +#define CAN_IF_ERRPASS_Msk (0x01 << CAN_IF_ERRPASS_Pos) +#define CAN_IF_ARBLOST_Pos 6 //Arbitration Lost闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笽E.ARBLOST=1閺冨爼鏁撻弬銈嗗CAN闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗婢堕亶鏁撻崝顐ヮ梿閹插瀚圭仦閬嶆晸閺傘倖瀚规潏妤呮晸缂佺偛绨㈢拠褎瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹 +#define CAN_IF_ARBLOST_Msk (0x01 << CAN_IF_ARBLOST_Pos) +#define CAN_IF_BUSERR_Pos 7 //闁跨喐鏋婚幏绋〦.BUSERR=1閺冨爼鏁撻弬銈嗗CAN闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閻涚偓鏋婚幏鐑芥晸閺傘倖瀚归崣浠嬫晸閺傘倖瀚归柨鐔虹哺鎼村洩顕滈幏鐑芥晸閺傘倖瀚归柨鐔诲▏閿燂拷 +#define CAN_IF_BUSERR_Msk (0x01 << CAN_IF_BUSERR_Pos) + +#define CAN_IE_RXDA_Pos 0 +#define CAN_IE_RXDA_Msk (0x01 << CAN_IE_RXDA_Pos) +#define CAN_IE_TXBR_Pos 1 +#define CAN_IE_TXBR_Msk (0x01 << CAN_IE_TXBR_Pos) +#define CAN_IE_ERRWARN_Pos 2 +#define CAN_IE_ERRWARN_Msk (0x01 << CAN_IE_ERRWARN_Pos) +#define CAN_IE_RXOV_Pos 3 +#define CAN_IE_RXOV_Msk (0x01 << CAN_IE_RXOV_Pos) +#define CAN_IE_WKUP_Pos 4 +#define CAN_IE_WKUP_Msk (0x01 << CAN_IE_WKUP_Pos) +#define CAN_IE_ERRPASS_Pos 5 +#define CAN_IE_ERRPASS_Msk (0x01 << CAN_IE_ERRPASS_Pos) +#define CAN_IE_ARBLOST_Pos 6 +#define CAN_IE_ARBLOST_Msk (0x01 << CAN_IE_ARBLOST_Pos) +#define CAN_IE_BUSERR_Pos 7 +#define CAN_IE_BUSERR_Msk (0x01 << CAN_IE_BUSERR_Pos) + +#define CAN_BT0_BRP_Pos 0 //Baud Rate Prescaler闁跨喐鏋婚幏绋N閺冨爼鏁撻幋鎺戝礋娴ｏ拷=2*Tsysclk*(BRP+1) +#define CAN_BT0_BRP_Msk (0x3F << CAN_BT0_BRP_Pos) +#define CAN_BT0_SJW_Pos 6 //Synchronization Jump Width +#define CAN_BT0_SJW_Msk (0x03 << CAN_BT0_SJW_Pos) + +#define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CAN閺冨爼鏁撻幋鎺戝礋娴ｏ拷 * (TSEG1+1) +#define CAN_BT1_TSEG1_Msk (0x0F << CAN_BT1_TSEG1_Pos) +#define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CAN閺冨爼鏁撻幋鎺戝礋娴ｏ拷 * (TSEG2+1) +#define CAN_BT1_TSEG2_Msk (0x07 << CAN_BT1_TSEG2_Pos) +#define CAN_BT1_SAM_Pos 7 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0: sampled once 1: sampled three times +#define CAN_BT1_SAM_Msk (0x01 << CAN_BT1_SAM_Pos) + +#define CAN_ECC_SEGCODE_Pos 0 //Segment Code +#define CAN_ECC_SEGCODE_Msk (0x0F << CAN_ECC_SEGCODE_Pos) +#define CAN_ECC_DIR_Pos 4 //0 error occurred during transmission 1 during reception +#define CAN_ECC_DIR_Msk (0x01 << CAN_ECC_DIR_Pos) +#define CAN_ECC_ERRCODE_Pos 5 //Error Code闁跨喐鏋婚幏锟�0 Bit error 1 Form error 2 Stuff error 3 other error +#define CAN_ECC_ERRCODE_Msk (0x03 << CAN_ECC_ERRCODE_Pos) + +#define CAN_INFO_DLC_Pos 0 //Data Length Control +#define CAN_INFO_DLC_Msk (0x0F << CAN_INFO_DLC_Pos) +#define CAN_INFO_RTR_Pos 6 //Remote Frame闁跨喐鏋婚幏锟�1 鏉╂粓鏁撻弬銈嗗鐢拷 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭敮锟� +#define CAN_INFO_RTR_Msk (0x01 << CAN_INFO_RTR_Pos) +#define CAN_INFO_FF_Pos 7 //Frame Format闁跨喐鏋婚幏锟�0 闁跨喐鏋婚幏宄板櫙鐢囨晸閺傘倖瀚瑰锟� 1 闁跨喐鏋婚幏宄扮潔鐢囨晸閺傘倖瀚瑰锟� +#define CAN_INFO_FF_Msk (0x01 << CAN_INFO_FF_Pos) + +typedef struct +{ + __IO uint32_t IE; //[0] 娑擄拷0闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏绋〧[0]缂佹挳鏁撻弬銈嗗娑擄拷0 + + __IO uint32_t IF; //[0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔活敎闂堚晜瀚归柨鐔告灮閹风兘鏁撻弬銈嗗妤ｅ﹪鏁撻弬銈嗗闁跨喐鏋婚幏鐤禂闁跨喐鏋婚幏鐑芥晸缂佺偞鍞婚幏鐑芥晸閿燂拷1闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + + __IO uint32_t IM; //[0] 闁跨喐鏋婚幏鐑芥晸閻偄鐦庢潏鐐闁跨喐鏋婚幏铚傝礋1閺冨爼鏁撻弬銈嗗LCDC闁跨喐鏋婚幏鐑芥晸閸欘偅鏌囩拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸鏉堝啩缍嗙粵瑙勫闁跨喐鏋婚幏宄板祻瀹勶繝鏁撻弬銈嗗閽€宥嗗闁跨喐鏋婚幏鐑芥晸閿燂拷 + + __IO uint32_t START; + + __IO uint32_t SRCADDR; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰┃鎰版晸閺傘倖瀚归崸鈧柨鐔惰寧鏉堢偓瀚归柨鐔告灮閹风兘鏁撻弬銈嗗30娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + + __IO uint32_t CR0; + + __IO uint32_t CR1; + + __IO uint32_t PRECMDV; //闁跨喐鏋婚幏绋璓U闁跨喐甯撮崠鈩冨闁跨喎褰ㄩ敐蹇斿闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸撳秹鏁撻弬銈嗗RS闁跨喐鏋婚幏鐑芥晸闁扮數顣幏鐑芥晸閺傘倖瀚规稉鈧柨鐔惰寧閿濆繑瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔荤窛绾板瀚归崐锟� +} LCD_TypeDef; + +#define LCD_START_MPUEN_Pos 0 //0 RGB闁跨喐甯撮崠鈩冨 1 MPU闁跨喐甯撮崠鈩冨 +#define LCD_START_MPUEN_Msk (0x01 << LCD_START_MPUEN_Pos) +#define LCD_START_GO_Pos 1 //閸愶拷1闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幑鍑ょ秶閹风兘鏁撻弬銈嗗闁跨喐宓庢潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗鏉╂粓鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閿燂拷 +#define LCD_START_GO_Msk (0x01 << LCD_START_GO_Pos) +#define LCD_START_BURST_Pos 2 +#define LCD_START_BURST_Msk (0x01 << LCD_START_BURST_Pos) +#define LCD_START_POSTCMDE_Pos 3 //闁跨喐鏋婚幏铚傜昂闁跨喐鏋婚幏鐤洣闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崘娆撴晸閺傘倖瀚归幏鍥晸閺傘倖瀚归柨鐔活敎椤曞棙瀚归摶鍜佸劉闁跨喐褰搴㈠闁跨喐褰导娆愬闁跨噦鎷�0x80闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸鐞涙鎷� +#define LCD_START_POSTCMDE_Msk (0x01 << LCD_START_POSTCMDE_Pos) +#define LCD_START_POSTCMDV_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸鐞涙鎷濋幏鐑芥晸閺傘倖瀚归崘銏ゆ晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭化濠氭晸鐞涙顣幏鐑芥晸娓氥儺鍓ㄩ幏鐑芥晸閺傘倖瀚归柨鐕傛嫹0x80闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤洣闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define LCD_START_POSTCMDV_Msk (0xFFFF << LCD_START_POSTCMDV_Pos) + +#define LCD_CR0_VPIX_Pos 0 //闁跨喐鏋婚幏绌歰rtrait娑擄拷0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛闁跨喐鏋婚幏椋庢纯闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗妫ｆ鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閿燂拷0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹767 +//闁跨喐鏋婚幏绌歰rtrait娑擄拷1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛濮樻潙閽╅柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规＃妤呮晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹767 +#define LCD_CR0_VPIX_Msk (0x3FF << LCD_CR0_VPIX_Pos) +#define LCD_CR0_HPIX_Pos 10 //闁跨喐鏋婚幏绌歰rtrait娑擄拷0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛濮樻潙閽╅柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规＃妤呮晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹1023 +//闁跨喐鏋婚幏绌歰rtrait娑擄拷1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛闁跨喐鏋婚幏椋庢纯闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗妫ｆ鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閿燂拷0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹1023 +#define LCD_CR0_HPIX_Msk (0x3FF << LCD_CR0_HPIX_Pos) +#define LCD_CR0_DCLK_Pos 20 //0 DOTCLK娑撯偓閻╂挳鏁撻弬銈嗗鏉烇拷 1 DOTCLK闁跨喕濡崠鈩冨闁跨喐鏋婚幏閿嬫閸嬫粓鏁撻弬銈嗗1 +#define LCD_CR0_DCLK_Msk (0x01 << LCD_CR0_DCLK_Pos) +#define LCD_CR0_HLOW_Pos 21 //闁跨喐鏋婚幏鐑芥晸缁辩笌YNC闁跨喖鍙虹喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰Л闂堚晜瀚笵OTCLK闁跨喐鏋婚幏鐑芥晸閼哄偊缍囬幏锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define LCD_CR0_HLOW_Msk (0x03 << LCD_CR0_HLOW_Pos) + +#define LCD_CR0_DLEN_Pos 0 //MPU闁跨喐甯撮崠鈩冨閺冨爼鏁撻弬銈嗗闁跨喎澹欏▎陇顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐宓庣粵瑙勫闁跨喖銈洪敐蹇斿闁跨喐鏋婚幏铚傜秴娑撴椽鏁撶悰妤勫Ν閿濆繑瀚�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏锟� +#define LCD_CR0_DLEN_Msk (0x1FFFFF << LCD_CR0_DLEN_Pos) + +#define LCD_CR1_DIRV_Pos 0 //0 portrait=0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱膩瀵拷 1 portrait=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱膩瀵拷 +#define LCD_CR1_DIRV_Msk (0x01 << LCD_CR1_DIRV_Pos) +#define LCD_CR1_VFP_Pos 1 +#define LCD_CR1_VFP_Msk (0x07 << LCD_CR1_VFP_Pos) +#define LCD_CR1_VBP_Pos 4 +#define LCD_CR1_VBP_Msk (0x1F << LCD_CR1_VBP_Pos) +#define LCD_CR1_HFP_Pos 9 +#define LCD_CR1_HFP_Msk (0x1F << LCD_CR1_HFP_Pos) +#define LCD_CR1_HBP_Pos 14 +#define LCD_CR1_HBP_Msk (0x7F << LCD_CR1_HBP_Pos) +#define LCD_CR1_DCLKDIV_Pos 21 //DOTCLK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔惰寧閿濆繑瀚归柨鐔虹哺閹插瀚归幏銉ヮ潒闁跨喓瀚涚喊澶嬪姒鏁撻敓锟�0闁跨喐鏋婚幏椋庛仛2闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏锟�1闁跨喐鏋婚幏椋庛仛4闁跨喐鏋婚幏鐑筋暥 ... +#define LCD_CR1_DCLKDIV_Msk (0x1F << LCD_CR1_DCLKDIV_Pos) +#define LCD_CR1_DCLKINV_Pos 26 //1 闁跨喐鏋婚幏鐑芥晸缁辩睋TCLK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规惔鏃堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗DOTCLK闁跨喖鎽弬銈嗗闁跨喐鍩呯拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐宓庣喊澶嬪闁跨喐鏋婚幏锟� +#define LCD_CR1_DCLKINV_Msk (0x01 << LCD_CR1_DCLKINV_Pos) + +#define LCD_CR1_REG_Pos 0 //LCD_CR1_CMD_Pos閸欐牕鈧拷1閺冨爼鏁撻弬銈嗗闁跨喍鑼庢潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲鈧拷 +#define LCD_CR1_REG_Msk (0xFFFF << LCD_CR1_REG_Pos) +#define LCD_CR1_I80_Pos 16 //1 闁跨喐甯撮崠鈩冨娑撶瘨80 0 闁跨喐甯撮崠鈩冨娑撶瘲68 +#define LCD_CR1_I80_Msk (0x01 << LCD_CR1_I80_Pos) +#define LCD_CR1_CMD_Pos 17 //0 闁跨喐鏋婚幏鐑芥晸閹圭柉鎻幏鐑芥晸閹存帪绱濋柨鐔告灮閹风úS娑撴椽鏁撶粩顓狀暜閹峰嘲閽� 1 闁跨喐鏋婚幏鐑芥晸缁涘绱堕柨鐔稿灊閿涘矂鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归幏鍥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹ゲS娑撴椽鏁撻柊鐢殿暜閹峰嘲閽� +#define LCD_CR1_CMD_Msk (0x01 << LCD_CR1_CMD_Pos) +#define LCD_CR1_TTAIL_Pos 18 //CSn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻绾板瀚笴Sn闁跨喖鎽弬銈嗗闁跨喐鍩呯喊澶嬪閺冨爼鏁撻弬銈嗗 +#define LCD_CR1_TTAIL_Msk (0x07 << LCD_CR1_TTAIL_Pos) +#define LCD_CR1_TAH_Pos 21 //WRn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻绾板瀚笴Sn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻绾板瀚归弮鍫曟晸閺傘倖瀚� +#define LCD_CR1_TAH_Msk (0x03 << LCD_CR1_TAH_Pos) +#define LCD_CR1_TPWLW_Pos 23 //WRn闁跨喖鍙虹喊澶嬪楠炴娊鏁撴笟銉ь劜閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗 +#define LCD_CR1_TPWLW_Msk (0x07 << LCD_CR1_TPWLW_Pos) +#define LCD_CR1_TAS_Pos 26 //CSn闁跨喖鎽弬銈嗗闁跨喐鍩呯喊澶嬪WRn闁跨喖鎽弬銈嗗闁跨喐鍩呯喊澶嬪閺冨爼鏁撻弬銈嗗 +#define LCD_CR1_TAS_Msk (0x03 << LCD_CR1_TAS_Pos) + +typedef struct +{ + __IO uint32_t DMA_MEM_ADDR; + + __IO uint32_t BLK; //Block Size and Count + + __IO uint32_t ARG; //Argument + + __IO uint32_t CMD; //Command + + __IO uint32_t RESP[4]; //Response + + __IO uint32_t DATA; + + __IO uint32_t STAT; + + __IO uint32_t CR1; + + __IO uint32_t CR2; + + __IO uint32_t IF; + + __IO uint32_t IE; + + __IO uint32_t IM; + + __IO uint32_t CMD12ERR; + + __IO uint32_t INFO; + + __IO uint32_t MAXCURR; +} SDIO_TypeDef; + +#define SDIO_BLK_SIZE_Pos 0 //0x200 512闁跨喕顢滈弬銈嗗 0x400 1024闁跨喕顢滈弬銈嗗 0x800 2048闁跨喕顢滈弬銈嗗 +#define SDIO_BLK_SIZE_Msk (0xFFF << SDIO_BLK_SIZE_Pos) +#define SDIO_BLK_COUNT_Pos 16 //0 Stop Transfer 1 1闁跨喐鏋婚幏锟� 2 2闁跨喐鏋婚幏锟� ... ... +#define SDIO_BLK_COUNT_Msk (0xFFF << SDIO_BLK_COUNT_Pos) + +#define SDIO_CMD_DMAEN_Pos 0 +#define SDIO_CMD_DMAEN_Msk (0x01 << SDIO_CMD_DMAEN_Pos) +#define SDIO_CMD_BLKCNTEN_Pos 1 +#define SDIO_CMD_BLKCNTEN_Msk (0x01 << SDIO_CMD_BLKCNTEN_Pos) +#define SDIO_CMD_AUTOCMD12_Pos 2 +#define SDIO_CMD_AUTOCMD12_Msk (0x01 << SDIO_CMD_AUTOCMD12_Pos) +#define SDIO_CMD_DIRREAD_Pos 4 //0 Write, Host to Card 1 Read, Card to Host +#define SDIO_CMD_DIRREAD_Msk (0x01 << SDIO_CMD_DIRREAD_Pos) +#define SDIO_CMD_MULTBLK_Pos 5 //0 Single Block 1 Multiple Block +#define SDIO_CMD_MULTBLK_Msk (0x01 << SDIO_CMD_MULTBLK_Pos) +#define SDIO_CMD_RESPTYPE_Pos 16 //闁跨喐鏋婚幏宄扮安闁跨喐鏋婚幏鐑芥晸闁扮缍囬幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规惔锟� 1 136娴ｅ秹鏁撻弬銈嗗鎼达拷 2 48娴ｅ秹鏁撻弬銈嗗鎼达拷 3 48娴ｅ秹鏁撻弬銈嗗鎼存棃鏁撻弬銈嗗Busy after response +#define SDIO_CMD_RESPTYPE_Msk (0x03 << SDIO_CMD_RESPTYPE_Pos) +#define SDIO_CMD_CRCCHECK_Pos 19 //Command CRC Check Enable +#define SDIO_CMD_CRCCHECK_Msk (0x01 << SDIO_CMD_CRCCHECK_Pos) +#define SDIO_CMD_IDXCHECK_Pos 20 //Command Index Check Enable +#define SDIO_CMD_IDXCHECK_Msk (0x01 << SDIO_CMD_IDXCHECK_Pos) +#define SDIO_CMD_HAVEDATA_Pos 21 //0 No Data Present 1 Data Present +#define SDIO_CMD_HAVEDATA_Msk (0x01 << SDIO_CMD_HAVEDATA_Pos) +#define SDIO_CMD_CMDTYPE_Pos 22 //0 NORMAL 1 SUSPEND 2 RESUME 3 ABORT +#define SDIO_CMD_CMDTYPE_Msk (0x03 << SDIO_CMD_CMDTYPE_Pos) +#define SDIO_CMD_CMDINDX_Pos 24 //Command Index闁跨喐鏋婚幏绋D0-63闁跨喐鏋婚幏绋烠MD0-63 +#define SDIO_CMD_CMDINDX_Msk (0x3F << SDIO_CMD_CMDINDX_Pos) + +#define SDIO_CR1_4BIT_Pos 1 //1 4 bit mode 0 1 bit mode +#define SDIO_CR1_4BIT_Msk (0x01 << SDIO_CR1_4BIT_Pos) +#define SDIO_CR1_8BIT_Pos 5 //1 8 bit mode is selected 0 8 bit mode is not selected +#define SDIO_CR1_8BIT_Msk (0x01 << SDIO_CR1_8BIT_Pos) +#define SDIO_CR1_CDBIT_Pos 6 //0 No Card 1 Card Inserted +#define SDIO_CR1_CDBIT_Msk (0x01 << SDIO_CR1_CDBIT_Pos) +#define SDIO_CR1_CDSRC_Pos 7 //Card Detect Source, 1 CR1.CDBIT娴ｏ拷 0 SD_Detect闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SDIO_CR1_CDSRC_Msk (0x01 << SDIO_CR1_CDSRC_Pos) +#define SDIO_CR1_PWRON_Pos 8 //1 Power on 0 Power off +#define SDIO_CR1_PWRON_Msk (0x01 << SDIO_CR1_PWRON_Pos) +#define SDIO_CR1_VOLT_Pos 9 //7 3.3V 6 3.0V 5 1.8V +#define SDIO_CR1_VOLT_Msk (0x07 << SDIO_CR1_VOLT_Pos) + +#define SDIO_CR2_CLKEN_Pos 0 //Internal Clock Enable +#define SDIO_CR2_CLKEN_Msk (0x01 << SDIO_CR2_CLKEN_Pos) +#define SDIO_CR2_CLKRDY_Pos 1 //Internal Clock Stable/Ready +#define SDIO_CR2_CLKRDY_Msk (0x01 << SDIO_CR2_CLKRDY_Pos) +#define SDIO_CR2_SDCLKEN_Pos 2 //SDCLK Enable +#define SDIO_CR2_SDCLKEN_Msk (0x01 << SDIO_CR2_SDCLKEN_Pos) +#define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规０锟� 0x01 2闁跨喐鏋婚幏鐑筋暥 0x02 4闁跨喐鏋婚幏鐑筋暥 0x04 8闁跨喐鏋婚幏鐑筋暥 0x08 16闁跨喐鏋婚幏鐑筋暥 ... 0x80 256闁跨喐鏋婚幏鐑筋暥 +#define SDIO_CR2_SDCLKDIV_Msk (0xFF << SDIO_CR2_SDCLKDIV_Pos) +#define SDIO_CR2_TIMEOUT_Pos 16 //0000 TMCLK*2^13 +#define SDIO_CR2_TIMEOUT_Msk (0x0F << SDIO_CR2_TIMEOUT_Pos) +#define SDIO_CR2_RSTALL_Pos 24 //Software Reset for All +#define SDIO_CR2_RSTALL_Msk (0x01 << SDIO_CR2_RSTALL_Pos) +#define SDIO_CR2_RSTCMD_Pos 25 //Software Reset for CMD Line +#define SDIO_CR2_RSTCMD_Msk (0x01 << SDIO_CR2_RSTCMD_Pos) +#define SDIO_CR2_RSTDAT_Pos 26 //Software Reset for DAT Line +#define SDIO_CR2_RSTDAT_Msk (0x01 << SDIO_CR2_RSTDAT_Pos) + +#define SDIO_IF_CMDDONE_Pos 0 +#define SDIO_IF_CMDDONE_Msk (0x01 << SDIO_IF_CMDDONE_Pos) +#define SDIO_IF_TRXDONE_Pos 1 +#define SDIO_IF_TRXDONE_Msk (0x01 << SDIO_IF_TRXDONE_Pos) +#define SDIO_IF_BLKGAP_Pos 2 +#define SDIO_IF_BLKGAP_Msk (0x01 << SDIO_IF_BLKGAP_Pos) +#define SDIO_IF_DMADONE_Pos 3 +#define SDIO_IF_DMADONE_Msk (0x01 << SDIO_IF_DMADONE_Pos) +#define SDIO_IF_BUFWRRDY_Pos 4 +#define SDIO_IF_BUFWRRDY_Msk (0x01 << SDIO_IF_BUFWRRDY_Pos) +#define SDIO_IF_BUFRDRDY_Pos 5 +#define SDIO_IF_BUFRDRDY_Msk (0x01 << SDIO_IF_BUFRDRDY_Pos) +#define SDIO_IF_CARDINSR_Pos 6 +#define SDIO_IF_CARDINSR_Msk (0x01 << SDIO_IF_CARDINSR_Pos) +#define SDIO_IF_CARDRMOV_Pos 7 +#define SDIO_IF_CARDRMOV_Msk (0x01 << SDIO_IF_CARDRMOV_Pos) +#define SDIO_IF_CARD_Pos 8 +#define SDIO_IF_CARD_Msk (0x01 << SDIO_IF_CARD_Pos) +#define SDIO_IF_ERROR_Pos 15 +#define SDIO_IF_ERROR_Msk (0x01 << SDIO_IF_ERROR_Pos) +#define SDIO_IF_CMDTIMEOUT_Pos 16 +#define SDIO_IF_CMDTIMEOUT_Msk (0x01 << SDIO_IF_CMDTIMEOUT_Pos) +#define SDIO_IF_CMDCRCERR_Pos 17 +#define SDIO_IF_CMDCRCERR_Msk (0x01 << SDIO_IF_CMDCRCERR_Pos) +#define SDIO_IF_CMDENDERR_Pos 18 +#define SDIO_IF_CMDENDERR_Msk (0x01 << SDIO_IF_CMDENDCERR_Pos) +#define SDIO_IF_CMDIDXERR_Pos 19 +#define SDIO_IF_CMDIDXERR_Msk (0x01 << SDIO_IF_CMDIDXCERR_Pos) +#define SDIO_IF_DATTIMEOUT_Pos 20 +#define SDIO_IF_DATTIMEOUT_Msk (0x01 << SDIO_IF_DATTIMEOUT_Pos) +#define SDIO_IF_DATCRCERR_Pos 21 +#define SDIO_IF_DATCRCERR_Msk (0x01 << SDIO_IF_DATCRCERR_Pos) +#define SDIO_IF_DATENDERR_Pos 22 +#define SDIO_IF_DATENDERR_Msk (0x01 << SDIO_IF_DATENDCERR_Pos) +#define SDIO_IF_CURLIMERR_Pos 23 +#define SDIO_IF_CURLIMERR_Msk (0x01 << SDIO_IF_CURLIMERR_Pos) +#define SDIO_IF_CMD12ERR_Pos 24 +#define SDIO_IF_CMD12ERR_Msk (0x01 << SDIO_IF_CMD12ERR_Pos) +#define SDIO_IF_DMAERR_Pos 25 +#define SDIO_IF_DMAERR_Msk (0x01 << SDIO_IF_DMAERR_Pos) +#define SDIO_IF_RESPERR_Pos 28 +#define SDIO_IF_RESPERR_Msk (0x01 << SDIO_IF_RESPERR_Pos) + +#define SDIO_IE_CMDDONE_Pos 0 //Command Complete Status Enable +#define SDIO_IE_CMDDONE_Msk (0x01 << SDIO_IE_CMDDONE_Pos) +#define SDIO_IE_TRXDONE_Pos 1 //Transfer Complete Status Enable +#define SDIO_IE_TRXDONE_Msk (0x01 << SDIO_IE_TRXDONE_Pos) +#define SDIO_IE_BLKGAP_Pos 2 //Block Gap Event Status Enable +#define SDIO_IE_BLKGAP_Msk (0x01 << SDIO_IE_BLKGAP_Pos) +#define SDIO_IE_DMADONE_Pos 3 //DMA Interrupt Status Enable +#define SDIO_IE_DMADONE_Msk (0x01 << SDIO_IE_DMADONE_Pos) +#define SDIO_IE_BUFWRRDY_Pos 4 //Buffer Write Ready Status Enable +#define SDIO_IE_BUFWRRDY_Msk (0x01 << SDIO_IE_BUFWRRDY_Pos) +#define SDIO_IE_BUFRDRDY_Pos 5 //Buffer Read Ready Status Enable +#define SDIO_IE_BUFRDRDY_Msk (0x01 << SDIO_IE_BUFRDRDY_Pos) +#define SDIO_IE_CARDINSR_Pos 6 //Card Insertion Status Enable +#define SDIO_IE_CARDINSR_Msk (0x01 << SDIO_IE_CARDINSR_Pos) +#define SDIO_IE_CARDRMOV_Pos 7 //Card Removal Status Enable +#define SDIO_IE_CARDRMOV_Msk (0x01 << SDIO_IE_CARDRMOV_Pos) +#define SDIO_IE_CARD_Pos 8 +#define SDIO_IE_CARD_Msk (0x01 << SDIO_IE_CARD_Pos) +#define SDIO_IE_CMDTIMEOUT_Pos 16 //Command Timeout Error Status Enable +#define SDIO_IE_CMDTIMEOUT_Msk (0x01 << SDIO_IE_CMDTIMEOUT_Pos) +#define SDIO_IE_CMDCRCERR_Pos 17 //Command CRC Error Status Enable +#define SDIO_IE_CMDCRCERR_Msk (0x01 << SDIO_IE_CMDCRCERR_Pos) +#define SDIO_IE_CMDENDERR_Pos 18 //Command End Bit Error Status Enable +#define SDIO_IE_CMDENDERR_Msk (0x01 << SDIO_IE_CMDENDCERR_Pos) +#define SDIO_IE_CMDIDXERR_Pos 19 //Command Index Error Status Enable +#define SDIO_IE_CMDIDXERR_Msk (0x01 << SDIO_IE_CMDIDXCERR_Pos) +#define SDIO_IE_DATTIMEOUT_Pos 20 //Data Timeout Error Status Enable +#define SDIO_IE_DATTIMEOUT_Msk (0x01 << SDIO_IE_DATTIMEOUT_Pos) +#define SDIO_IE_DATCRCERR_Pos 21 //Data CRC Error Status Enable +#define SDIO_IE_DATCRCERR_Msk (0x01 << SDIO_IE_DATCRCERR_Pos) +#define SDIO_IE_DATENDERR_Pos 22 //Data End Bit Error Status Enable +#define SDIO_IE_DATENDERR_Msk (0x01 << SDIO_IE_DATENDCERR_Pos) +#define SDIO_IE_CURLIMERR_Pos 23 //Current Limit Error Status Enable +#define SDIO_IE_CURLIMERR_Msk (0x01 << SDIO_IE_CURLIMERR_Pos) +#define SDIO_IE_CMD12ERR_Pos 24 //Auto CMD12 Error Status Enable +#define SDIO_IE_CMD12ERR_Msk (0x01 << SDIO_IE_CMD12ERR_Pos) +#define SDIO_IE_DMAERR_Pos 25 //ADMA Error Status Enable +#define SDIO_IE_DMAERR_Msk (0x01 << SDIO_IE_DMAERR_Pos) +#define SDIO_IE_RESPERR_Pos 28 //Target Response Error Status Enable +#define SDIO_IE_RESPERR_Msk (0x01 << SDIO_IE_RESPERR_Pos) + +#define SDIO_IM_CMDDONE_Pos 0 +#define SDIO_IM_CMDDONE_Msk (0x01 << SDIO_IM_CMDDONE_Pos) +#define SDIO_IM_TRXDONE_Pos 1 +#define SDIO_IM_TRXDONE_Msk (0x01 << SDIO_IM_TRXDONE_Pos) +#define SDIO_IM_BLKGAP_Pos 2 +#define SDIO_IM_BLKGAP_Msk (0x01 << SDIO_IM_BLKGAP_Pos) +#define SDIO_IM_DMADONE_Pos 3 +#define SDIO_IM_DMADONE_Msk (0x01 << SDIO_IM_DMADONE_Pos) +#define SDIO_IM_BUFWRRDY_Pos 4 +#define SDIO_IM_BUFWRRDY_Msk (0x01 << SDIO_IM_BUFWRRDY_Pos) +#define SDIO_IM_BUFRDRDY_Pos 5 +#define SDIO_IM_BUFRDRDY_Msk (0x01 << SDIO_IM_BUFRDRDY_Pos) +#define SDIO_IM_CARDINSR_Pos 6 +#define SDIO_IM_CARDINSR_Msk (0x01 << SDIO_IM_CARDINSR_Pos) +#define SDIO_IM_CARDRMOV_Pos 7 +#define SDIO_IM_CARDRMOV_Msk (0x01 << SDIO_IM_CARDRMOV_Pos) +#define SDIO_IM_CARD_Pos 8 +#define SDIO_IM_CARD_Msk (0x01 << SDIO_IM_CARD_Pos) +#define SDIO_IM_CMDTIMEOUT_Pos 16 +#define SDIO_IM_CMDTIMEOUT_Msk (0x01 << SDIO_IM_CMDTIMEOUT_Pos) +#define SDIO_IM_CMDCRCERR_Pos 17 +#define SDIO_IM_CMDCRCERR_Msk (0x01 << SDIO_IM_CMDCRCERR_Pos) +#define SDIO_IM_CMDENDERR_Pos 18 +#define SDIO_IM_CMDENDERR_Msk (0x01 << SDIO_IM_CMDENDCERR_Pos) +#define SDIO_IM_CMDIDXERR_Pos 19 +#define SDIO_IM_CMDIDXERR_Msk (0x01 << SDIO_IM_CMDIDXCERR_Pos) +#define SDIO_IM_DATTIMEOUT_Pos 20 +#define SDIO_IM_DATTIMEOUT_Msk (0x01 << SDIO_IM_DATTIMEOUT_Pos) +#define SDIO_IM_DATCRCERR_Pos 21 +#define SDIO_IM_DATCRCERR_Msk (0x01 << SDIO_IM_DATCRCERR_Pos) +#define SDIO_IM_DATENDERR_Pos 22 +#define SDIO_IM_DATENDERR_Msk (0x01 << SDIO_IM_DATENDCERR_Pos) +#define SDIO_IM_CURLIMERR_Pos 23 +#define SDIO_IM_CURLIMERR_Msk (0x01 << SDIO_IM_CURLIMERR_Pos) +#define SDIO_IM_CMD12ERR_Pos 24 +#define SDIO_IM_CMD12ERR_Msk (0x01 << SDIO_IM_CMD12ERR_Pos) +#define SDIO_IM_DMAERR_Pos 25 +#define SDIO_IM_DMAERR_Msk (0x01 << SDIO_IM_DMAERR_Pos) +#define SDIO_IM_RESPERR_Pos 28 +#define SDIO_IM_RESPERR_Msk (0x01 << SDIO_IM_RESPERR_Pos) + +typedef struct +{ + __IO uint32_t DATA; + __IO uint32_t ADDR; + __IO uint32_t ERASE; + __IO uint32_t CACHE; + __IO uint32_t CFG0; + __IO uint32_t CFG1; + __IO uint32_t CFG2; + __IO uint32_t CFG3; + __IO uint32_t STAT; +} FLASH_Typedef; + +#define FLASH_ERASE_REQ_Pos 31 +#define FLASH_ERASE_REQ_Msk ((uint32_t)0x01 << FLASH_ERASE_REQ_Pos) + +#define FLASH_CACHE_PROG_Pos 2 +#define FLASH_CACHE_PROG_Msk (0x01 << FLASH_CACHE_PROG_Pos) +#define FLASH_CACHE_CLEAR_Pos 3 +#define FLASH_CACHE_CLEAR_Msk (0x01 << FLASH_CACHE_CLEAR_Pos) + +#define FLASH_STAT_ERASE_GOING_Pos 0 +#define FLASH_STAT_ERASE_GOING_Msk (0X01 << FLASH_STAT_ERASE_GOING_Pos) +#define FLASH_STAT_PROG_GOING_Pos 1 +#define FLASH_STAT_PROG_GOING_Msk (0x01 << FLASH_STAT_PROG_GOING_Pos) +#define FALSH_STAT_FIFO_EMPTY_Pos 3 +#define FLASH_STAT_FIFO_EMPTY_Msk (0x01 << FALSH_STAT_FIFO_EMPTY_Pos) +#define FALSH_STAT_FIFO_FULL_Pos 4 +#define FLASH_STAT_FIFO_FULL_Msk (0x01 << FALSH_STAT_FIFO_FULL_Pos) + +typedef struct +{ + __IO uint32_t CR; +} SRAMC_TypeDef; + +#define SRAMC_CR_RWTIME_Pos 0 //闁跨喐鏋婚幏宄板晸闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸旑偊娼婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閳藉懏瀚�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閳藉懏瀚归柨鐔告灮閹峰嘲鐨柨鐔告灮閹风兘鏁撻弬銈嗗娑擄拷4 +#define SRAMC_CR_RWTIME_Msk (0x0F << SRAMC_CR_RWTIME_Pos) +#define SRAMC_CR_BYTEIF_Pos 4 //闁跨喕袙闁娍RAM闁跨喐鏋婚幏鐑芥晸閹瑰嘲灏呴幏鐑界伐闁跨噦鎷�0 16娴ｏ拷 1 8娴ｏ拷 +#define SRAMC_CR_BYTEIF_Msk (0x01 << SRAMC_CR_BYTEIF_Pos) +#define SRAMC_CR_HBLBDIS_Pos 5 //1 ADDR[23:22]娑撴椽鏁撻弬銈嗗閸р偓闁跨喐鏋婚幏锟� 0 ADDR[23]娑撴椽鏁撻弬銈嗗闁跨喕顢滈弬銈嗗娴ｅ潡鏁撻弶甯秶閹风DDR[22]娑撴椽鏁撻弬銈嗗闁跨喕顢滈弬銈嗗娴ｅ潡鏁撻弬銈嗗 +#define SRAMC_CR_HBLBDIS_Msk (0x01 << SRAMC_CR_HBLBDIS_Pos) + +typedef struct +{ + __IO uint32_t CR0; + + __IO uint32_t CR1; + + __IO uint32_t REFRESH; + + __IO uint32_t NOPNUM; //[15:0] 闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔活敎椤旂偛搴滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱濮囬柨鐔告灮閹疯渹绻庨柨鐔虹ガOP闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + + __IO uint32_t LATCH; + + __IO uint32_t REFDONE; //[0] Frefresh Done闁跨喐鏋婚幏鐑芥晸鏉堝啰顣幏鐑芥晸缂佺偟銆嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +} SDRAMC_TypeDef; + +#define SDRAMC_CR0_BURSTLEN_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崣锟�2闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭粈绡塽rst Length娑擄拷4 +#define SDRAMC_CR0_BURSTLEN_Msk (0x07 << SDRAMC_CR0_BURSTLEN_Pos) +#define SDRAMC_CR0_CASDELAY_Pos 4 //CAS Latency闁跨喐鏋婚幏锟� 2 2 3 3 +#define SDRAMC_CR0_CASDELAY_Msk (0x07 << SDRAMC_CR0_CASDELAY_Pos) + +#define SDRAMC_CR1_TRP_Pos 0 +#define SDRAMC_CR1_TRP_Msk (0x07 << SDRAMC_CR1_TRP_Pos) +#define SDRAMC_CR1_TRCD_Pos 3 +#define SDRAMC_CR1_TRCD_Msk (0x07 << SDRAMC_CR1_TRCD_Pos) +#define SDRAMC_CR1_TRC_Pos 6 +#define SDRAMC_CR1_TRC_Msk (0x0F << SDRAMC_CR1_TRC_Pos) +#define SDRAMC_CR1_TRAS_Pos 10 +#define SDRAMC_CR1_TRAS_Msk (0x07 << SDRAMC_CR1_TRAS_Pos) +#define SDRAMC_CR1_TRRD_Pos 13 +#define SDRAMC_CR1_TRRD_Msk (0x03 << SDRAMC_CR1_TRRD_Pos) +#define SDRAMC_CR1_TMRD_Pos 15 +#define SDRAMC_CR1_TMRD_Msk (0x07 << SDRAMC_CR1_TMRD_Pos) +#define SDRAMC_CR1_32BIT_Pos 18 //SDRAMC闁跨喍鑼庨幒銉ュ皡閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏锟�1 32bit 0 16bit +#define SDRAMC_CR1_32BIT_Msk (0x01 << SDRAMC_CR1_32BIT_Pos) +#define SDRAMC_CR1_BANK_Pos 19 //SDRAM濮ｅ繘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建绾攱瀚归柨鐔告灮閹风⿰ank闁跨喐鏋婚幏锟�0 2 banks 1 4 banks +#define SDRAMC_CR1_BANK_Msk (0x01 << SDRAMC_CR1_BANK_Pos) +#define SDRAMC_CR1_CELL32BIT_Pos 20 //SDRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔告灮閹凤拷1 32bit 0 16bit +#define SDRAMC_CR1_CELL32BIT_Msk (0x01 << SDRAMC_CR1_CELL32BIT_Pos) +#define SDRAMC_CR1_CELLSIZE_Pos 21 //SDRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�0 64Mb 1 128Mb 2 256Mb 3 16Mb +#define SDRAMC_CR1_CELLSIZE_Msk (0x03 << SDRAMC_CR1_CELLSIZE_Pos) +#define SDRAMC_CR1_HIGHSPEED_Pos 23 //闁跨喐鏋婚幏绌恈lk闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�100MHz閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹璐�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹璐�0 +#define SDRAMC_CR1_HIGHSPEED_Msk (0x01 << SDRAMC_CR1_HIGHSPEED_Pos) + +#define SDRAMC_REFRESH_RATE_Pos 0 +#define SDRAMC_REFRESH_RATE_Msk (0xFFF << SDRAMC_REFRESH_RATE_Pos) +#define SDRAMC_REFRESH_EN_Pos 12 +#define SDRAMC_REFRESH_EN_Msk (0x01 << SDRAMC_REFRESH_EN_Pos) + +#define SDRAMC_LATCH_INEDGE_Pos 0 //闁跨喍鑼庨棃鈺傚闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓绁矰RAM闁跨喎褰ㄧ拋瑙勫闁跨喐鍩呯喊澶嬪闁跨喐鏋婚幏鐑芥晸閹瑰嚖缍囬幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1 闁跨喖鎽弬銈嗗闁跨喐鏋婚幏锟� +#define SDRAMC_LATCH_INEDGE_Msk (0x01 << SDRAMC_LATCH_INEDGE_Pos) +#define SDRAMC_LATCH_OUTEDGE_Pos 1 //闁跨喍鑼庨棃鈺傚闁跨喐鏋婚幏宄板箵闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔煎徍闂堚晜瀚筍DRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚�1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 0 闁跨喖鎽弬銈嗗闁跨喐鏋婚幏锟� +#define SDRAMC_LATCH_OUTEDGE_Msk (0x01 << SDRAMC_LATCH_OUTEDGE_Pos) +#define SDRAMC_LATCH_WAITST_Pos 2 +#define SDRAMC_LATCH_WAITST_Msk (0x01 << SDRAMC_LATCH_WAITST_Pos) + +typedef struct +{ + __IO uint32_t IE; + + __IO uint32_t IF; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + + __IO uint32_t IM; + + __IO uint32_t CR; + + __IO uint32_t ADDR; + + __IO uint32_t CMD; +} NORFLC_TypeDef; + +#define NORFLC_IE_FINISH_Pos 0 +#define NORFLC_IE_FINISH_Msk (0x01 << NORFLC_IE_FINISH_Pos) +#define NORFLC_IE_TIMEOUT_Pos 1 +#define NORFLC_IE_TIMEOUT_Msk (0x01 << NORFLC_IE_TIMEOUT_Pos) + +#define NORFLC_IF_FINISH_Pos 0 +#define NORFLC_IF_FINISH_Msk (0x01 << NORFLC_IF_FINISH_Pos) +#define NORFLC_IF_TIMEOUT_Pos 1 +#define NORFLC_IF_TIMEOUT_Msk (0x01 << NORFLC_IF_TIMEOUT_Pos) + +#define NORFLC_IM_FINISH_Pos 0 +#define NORFLC_IM_FINISH_Msk (0x01 << NORFLC_IM_FINISH_Pos) +#define NORFLC_IM_TIMEOUT_Pos 1 +#define NORFLC_IM_TIMEOUT_Msk (0x01 << NORFLC_IM_TIMEOUT_Pos) + +#define NORFLC_CR_RDTIME_Pos 0 //Oen闁跨喖鎽弬銈嗗闁跨喐鍩呴悮瀛樺闁跨喐鏋婚幏铚傜箮闁跨喓绮搁幉瀣闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭拠銈夋晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鍩呯喊澶嬪闁跨喐鏋婚幏鐑芥晸閹瑰皝妲勯幏锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define NORFLC_CR_RDTIME_Msk (0x1F << NORFLC_CR_RDTIME_Pos) +#define NORFLC_CR_WRTIME_Pos 5 //闁跨喐鏋婚幏鐑芥晸缁插穲n闁跨喍鑼庢担搴ｎ暜閹峰嘲閽╅柨鐔告灮閹峰嘲褰囬柨鐕傛嫹0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define NORFLC_CR_WRTIME_Msk (0x07 << NORFLC_CR_WRTIME_Pos) +#define NORFLC_CR_BYTEIF_Pos 8 //闁跨喕袙闁垷OR FLASH闁跨喐鏋婚幏鐑芥晸閹瑰嘲灏呴幏鐑界伐闁跨噦鎷�1 8娴ｏ拷 0 16娴ｏ拷 +#define NORFLC_CR_BYTEIF_Msk (0x01 << NORFLC_CR_BYTEIF_Pos) + +#define NORFLC_CMD_DATA_Pos 0 //闁跨喐鏋婚幏绋癛OGRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閿濆繑瀚笵ATA闁跨喐鏋婚幏鐤洣閸愭瑩鏁撻弬銈嗗NOR FLASH闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚归柨鐔告灮閹风úEAD闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閿濆繑瀚笵ATA闁跨喕顫楁潏鐐NOR FLASH闁跨喐鏋婚幏鐑芥晸閹搭亞顣幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define NORFLC_CMD_DATA_Msk (0xFFFF << NORFLC_CMD_DATA_Pos) +#define NORFLC_CMD_CMD_Pos 16 //闁跨喐鏋婚幏鐤洣閹笛囨晸閸欘偆顣幏鐑芥晸閺傘倖瀚归柨鐔虹摂閿涳拷0 READ 1 RESET 2 AUTOMATIC SELECT 3 PROGRAM 4 CHIP ERASE 5 SECTOR ERASE +#define NORFLC_CMD_CMD_Msk (0x07 << NORFLC_CMD_CMD_Pos) + +typedef struct +{ + __IO uint32_t CR; + + __O uint32_t DATAIN; + + __IO uint32_t INIVAL; + + __I uint32_t RESULT; +} CRC_TypeDef; + +#define CRC_CR_EN_Pos 0 +#define CRC_CR_EN_Msk (0x01 << CRC_CR_EN_Pos) +#define CRC_CR_OREV_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶憴鎺戝殩閹风柉娴� +#define CRC_CR_OREV_Msk (0x01 << CRC_CR_OREV_Pos) +#define CRC_CR_ONOT_Pos 2 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶憴鎺戝殩閹峰嘲褰囬柨鐔告灮閹凤拷 +#define CRC_CR_ONOT_Msk (0x01 << CRC_CR_ONOT_Pos) +#define CRC_CR_CRC16_Pos 3 //1 CRC16 0 CRC32 +#define CRC_CR_CRC16_Msk (0x01 << CRC_CR_CRC16_Pos) +#define CRC_CR_IBITS_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏娴ｅ秹鏁撻弬銈嗗 0 32娴ｏ拷 1 16娴ｏ拷 2 8娴ｏ拷 +#define CRC_CR_IBITS_Msk (0x03 << CRC_CR_IBITS_Pos) + +typedef struct +{ + __IO uint32_t MINSEC; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + + __IO uint32_t DATHUR; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + + __IO uint32_t MONDAY; //闁跨喐鏋婚幏鐑芥晸閺夋壆銆嬮幏鐑芥晸閺傘倖瀚� + + __IO uint32_t YEAR; //[11:0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶悰妞﹀秵瀚归柨鐕傛嫹1901-2199 + + __IO uint32_t MINSECAL; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + + __IO uint32_t DAYHURAL; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 + + __IO uint32_t LOAD; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹叓鐎靛嫯鎻幏鐑芥晸閺傘倖瀚归柨鐔峰建绾板瀚归崐鐓庢倱闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筊TC闁跨喎褰ㄩ敐蹇斿閸氬矂鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + + __IO uint32_t IE; + + __IO uint32_t IF; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + + __IO uint32_t EN; //[0] 1 RTC娴ｅ潡鏁撻弬銈嗗 + + __IO uint32_t CFGABLE; //[0] 1 RTC闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + + __IO uint32_t TRIM; //閺冨爼鏁撻幒銉ь暜閹风兘鏁撻弬銈嗗 + + __IO uint32_t TRIMM; //閺冨爼鏁撻弬銈嗗瀵邦噣鏁撻弬銈嗗闁跨喐鏋婚幏锟� +} RTC_TypeDef; + +#define RTC_LOAD_TIME_Pos 0 +#define RTC_LOAD_TIME_Msk (0x01 << RTC_LOAD_TIME_Pos) +#define RTC_LOAD_ALARM_Pos 1 +#define RTC_LOAD_ALARM_Msk (0x01 << RTC_LOAD_ALARM_Pos) + +#define RTC_MINSEC_SEC_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 +#define RTC_MINSEC_SEC_Msk (0x3F << RTC_MINSEC_SEC_Pos) +#define RTC_MINSEC_MIN_Pos 6 //闁跨喐鏋婚幏鐑芥晸閹恒儳銆嬮幏鐑芥晸閺傘倖瀚� +#define RTC_MINSEC_MIN_Msk (0x3F << RTC_MINSEC_MIN_Pos) + +#define RTC_DATHUR_HOUR_Pos 0 //鐏忓繑妞傞柨鐔告灮閹风兘鏁撻弬銈嗗 +#define RTC_DATHUR_HOUR_Msk (0x1F << RTC_DATHUR_HOUR_Pos) +#define RTC_DATHUR_DATE_Pos 5 //date of month +#define RTC_DATHUR_DATE_Msk (0x1F << RTC_DATHUR_DATE_Pos) + +#define RTC_MONDAY_DAY_Pos 0 //day of week +#define RTC_MONDAY_DAY_Msk (0x07 << RTC_MONDAY_DAY_Pos) +#define RTC_MONDAY_MON_Pos 3 //闁跨喖鎽禒鐣屻€嬮幏鐑芥晸閺傘倖瀚� +#define RTC_MONDAY_MON_Msk (0x0F << RTC_MONDAY_MON_Pos) + +#define RTC_MINSECAL_SEC_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define RTC_MINSECAL_SEC_Msk (0x3F << RTC_MINSECAL_SEC_Pos) +#define RTC_MINSECAL_MIN_Pos 6 //闁跨喐鏋婚幏鐑芥晸閹恒儱鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define RTC_MINSECAL_MIN_Msk (0x3F << RTC_MINSECAL_MIN_Pos) + +#define RTC_DAYHURAL_HOUR_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭亸蹇旀闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define RTC_DAYHURAL_HOUR_Msk (0x1F << RTC_DAYHURAL_HOUR_Pos) +#define RTC_DAYHURAL_SUN_Pos 5 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_SUN_Msk (0x01 << RTC_DAYHURAL_SUN_Pos) +#define RTC_DAYHURAL_MON_Pos 6 //闁跨喐鏋婚幏铚傜闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鏅� +#define RTC_DAYHURAL_MON_Msk (0x01 << RTC_DAYHURAL_MON_Pos) +#define RTC_DAYHURAL_TUE_Pos 7 //闁跨喐婢冪拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鏅� +#define RTC_DAYHURAL_TUE_Msk (0x01 << RTC_DAYHURAL_TUE_Pos) +#define RTC_DAYHURAL_WED_Pos 8 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_WED_Msk (0x01 << RTC_DAYHURAL_WED_Pos) +#define RTC_DAYHURAL_THU_Pos 9 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_THU_Msk (0x01 << RTC_DAYHURAL_THU_Pos) +#define RTC_DAYHURAL_FRI_Pos 10 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_FRI_Msk (0x01 << RTC_DAYHURAL_FRI_Pos) +#define RTC_DAYHURAL_SAT_Pos 11 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_SAT_Msk (0x01 << RTC_DAYHURAL_SAT_Pos) + +#define RTC_IE_SEC_Pos 0 //闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏铚傚▏闁跨喐鏋婚幏锟� +#define RTC_IE_SEC_Msk (0x01 << RTC_IE_SEC_Pos) +#define RTC_IE_MIN_Pos 1 +#define RTC_IE_MIN_Msk (0x01 << RTC_IE_MIN_Pos) +#define RTC_IE_HOUR_Pos 2 +#define RTC_IE_HOUR_Msk (0x01 << RTC_IE_HOUR_Pos) +#define RTC_IE_DATE_Pos 3 +#define RTC_IE_DATE_Msk (0x01 << RTC_IE_DATE_Pos) +#define RTC_IE_ALARM_Pos 4 +#define RTC_IE_ALARM_Msk (0x01 << RTC_IE_ALARM_Pos) + +#define RTC_IF_SEC_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define RTC_IF_SEC_Msk (0x01 << RTC_IF_SEC_Pos) +#define RTC_IF_MIN_Pos 1 +#define RTC_IF_MIN_Msk (0x01 << RTC_IF_MIN_Pos) +#define RTC_IF_HOUR_Pos 2 +#define RTC_IF_HOUR_Msk (0x01 << RTC_IF_HOUR_Pos) +#define RTC_IF_DATE_Pos 3 +#define RTC_IF_DATE_Msk (0x01 << RTC_IF_DATE_Pos) +#define RTC_IF_ALARM_Pos 4 +#define RTC_IF_ALARM_Msk (0x01 << RTC_IF_ALARM_Pos) + +#define RTC_TRIM_ADJ_Pos 0 //闁跨喐鏋婚幏鐑芥晸閼哄倻顣幏鐑芥晸閺傘倖瀚笲ASECNT闁跨喍鑼庣涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閿濆繑瀚规姗€鏁撻弬銈嗗娑擄拷32768闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔烘たEC娑擄拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤樁闁跨喐鏋婚幏鐑芥晸鏉炲尅鎷�32768-ADJ闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濞囬敓锟�32768+ADJ +#define RTC_TRIM_ADJ_Msk (0xFF << RTC_TRIM_ADJ_Pos) +#define RTC_TRIM_DEC_Pos 8 +#define RTC_TRIM_DEC_Msk (0x01 << RTC_TRIM_DEC_Pos) + +#define RTC_TRIMM_CYCLE_Pos 0 //闁跨喐鏋婚幏鐑芥晸閼哄倻銆嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗瀵邦噣鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹イNC娑擄拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄崟闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡喊澶嬪闁跨喐鏋婚幏铚傝礋(32768闁跨喐鏋婚幏绋烡J)+1,闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹(32768闁跨喐鏋婚幏绋烡J)-1 +//cycles=0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲浜曢柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绌媦cles=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筺娑擄拷2闁跨喐鏋婚幏绌媦cles=7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筺娑擄拷8闁跨喐鏋婚幏鐑芥晸閻ㄥ棜鎻幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define RTC_TRIMM_CYCLE_Msk (0x07 << RTC_TRIMM_CYCLE_Pos) +#define RTC_TRIMM_INC_Pos 3 +#define RTC_TRIMM_INC_Msk (0x01 << RTC_TRIMM_INC_Pos) + +typedef struct +{ + __IO uint32_t LOAD; //閸犲倿鏁撻弬銈嗗娴ｅ潡鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭憗鍛存晸閺傘倖瀚筁OAD閸婏拷 + + __I uint32_t VALUE; + + __IO uint32_t CR; + + __IO uint32_t IF; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷0閺冨墎鈥栭柨鐔告灮閹风兘鏁撻弬銈嗗娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偓鎷�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔活敎閿燂拷 + + __IO uint32_t FEED; //閸愶拷0x55閸犲倿鏁撻弬銈嗗 +} WDT_TypeDef; + +#define WDT_CR_EN_Pos 0 +#define WDT_CR_EN_Msk (0x01 << WDT_CR_EN_Pos) +#define WDT_CR_RSTEN_Pos 1 +#define WDT_CR_RSTEN_Msk (0x01 << WDT_CR_RSTEN_Pos) + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +#define RAM_BASE 0x20000000 +#define AHB_BASE 0x40000000 +#define APB_BASE 0x40010000 + +#define NORFLC_BASE 0x60000000 +#define NORFLM_BASE 0x61000000 + +#define SRAMC_BASE 0x68000000 +#define SRAMM_BASE 0x69000000 + +#define SDRAMC_BASE 0x78000000 +#define SDRAMM_BASE 0x70000000 + +/* AHB Peripheral memory map */ +#define SYS_BASE (AHB_BASE + 0x00000) + +#define DMA_BASE (AHB_BASE + 0x01000) + +#define LCD_BASE (AHB_BASE + 0x02000) + +#define CRC_BASE (AHB_BASE + 0x03000) + +#define SDIO_BASE (AHB_BASE + 0x04000) + +/* APB Peripheral memory map */ +#define PORT_BASE (APB_BASE + 0x00000) + +#define GPIOA_BASE (APB_BASE + 0x01000) +#define GPIOB_BASE (APB_BASE + 0x02000) +#define GPIOC_BASE (APB_BASE + 0x03000) +#define GPIOD_BASE (APB_BASE + 0x04000) +#define GPIOM_BASE (APB_BASE + 0x05000) +#define GPION_BASE (APB_BASE + 0x06000) +#define GPIOP_BASE (APB_BASE + 0x08000) + +#define TIMR0_BASE (APB_BASE + 0x07000) +#define TIMR1_BASE (APB_BASE + 0x0700C) +#define TIMR2_BASE (APB_BASE + 0x07018) +#define TIMR3_BASE (APB_BASE + 0x07024) +#define TIMR4_BASE (APB_BASE + 0x07030) +#define TIMR5_BASE (APB_BASE + 0x0703C) +#define TIMRG_BASE (APB_BASE + 0x07060) + +#define WDT_BASE (APB_BASE + 0x09000) + +#define PWM0_BASE (APB_BASE + 0x0A000) +#define PWM1_BASE (APB_BASE + 0x0A020) +#define PWM2_BASE (APB_BASE + 0x0A040) +#define PWM3_BASE (APB_BASE + 0x0A060) +#define PWM4_BASE (APB_BASE + 0x0A080) +#define PWM5_BASE (APB_BASE + 0x0A0A0) +#define PWMG_BASE (APB_BASE + 0x0A180) + +#define RTC_BASE (APB_BASE + 0x0B000) + +#define ADC0_BASE (APB_BASE + 0x0C000) +#define ADC1_BASE (APB_BASE + 0x0D000) + +#define FLASH_BASE (APB_BASE + 0x0F000) + +#define UART0_BASE (APB_BASE + 0x10000) +#define UART1_BASE (APB_BASE + 0x11000) +#define UART2_BASE (APB_BASE + 0x12000) +#define UART3_BASE (APB_BASE + 0x13000) + +#define I2C0_BASE (APB_BASE + 0x18000) +#define I2C1_BASE (APB_BASE + 0x19000) + +#define SPI0_BASE (APB_BASE + 0x1C000) +#define SPI1_BASE (APB_BASE + 0x1D000) + +#define CAN_BASE (APB_BASE + 0x20000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define SYS ((SYS_TypeDef *)SYS_BASE) + +#define PORT ((PORT_TypeDef *)PORT_BASE) + +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOM ((GPIO_TypeDef *)GPIOM_BASE) +#define GPION ((GPIO_TypeDef *)GPION_BASE) +#define GPIOP ((GPIO_TypeDef *)GPIOP_BASE) + +#define TIMR0 ((TIMR_TypeDef *)TIMR0_BASE) +#define TIMR1 ((TIMR_TypeDef *)TIMR1_BASE) +#define TIMR2 ((TIMR_TypeDef *)TIMR2_BASE) +#define TIMR3 ((TIMR_TypeDef *)TIMR3_BASE) +#define TIMR4 ((TIMR_TypeDef *)TIMR4_BASE) +#define TIMR5 ((TIMR_TypeDef *)TIMR5_BASE) +#define TIMRG ((TIMRG_TypeDef *)TIMRG_BASE) + +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define UART3 ((UART_TypeDef *)UART3_BASE) + +#define SPI0 ((SPI_TypeDef *)SPI0_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) + +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) + +#define ADC0 ((ADC_TypeDef *)ADC0_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) + +#define PWM0 ((PWM_TypeDef *)PWM0_BASE) +#define PWM1 ((PWM_TypeDef *)PWM1_BASE) +#define PWM2 ((PWM_TypeDef *)PWM2_BASE) +#define PWM3 ((PWM_TypeDef *)PWM3_BASE) +#define PWM4 ((PWM_TypeDef *)PWM4_BASE) +#define PWM5 ((PWM_TypeDef *)PWM5_BASE) +#define PWMG ((PWMG_TypeDef *)PWMG_BASE) + +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) + +#define DMA ((DMA_TypeDef *)DMA_BASE) + +#define CAN ((CAN_TypeDef *)CAN_BASE) + +#define LCD ((LCD_TypeDef *)LCD_BASE) + +#define CRC ((CRC_TypeDef *)CRC_BASE) + +#define RTC ((RTC_TypeDef *)RTC_BASE) + +#define WDT ((WDT_TypeDef *)WDT_BASE) + +#define FLASH ((FLASH_Typedef *)FLASH_BASE) + +#define SRAMC ((SRAMC_TypeDef *)SRAMC_BASE) + +#define NORFLC ((NORFLC_TypeDef *)NORFLC_BASE) + +#define SDRAMC ((SDRAMC_TypeDef *)SDRAMC_BASE) + +#include "SWM320_port.h" +#include "SWM320_gpio.h" +#include "SWM320_exti.h" +#include "SWM320_timr.h" +#include "SWM320_uart.h" +#include "SWM320_spi.h" +#include "SWM320_i2c.h" +#include "SWM320_pwm.h" +#include "SWM320_adc.h" +#include "SWM320_dma.h" +#include "SWM320_lcd.h" +#include "SWM320_can.h" +#include "SWM320_sdio.h" +#include "SWM320_flash.h" +#include "SWM320_norflash.h" +#include "SWM320_sdram.h" +#include "SWM320_crc.h" +#include "SWM320_rtc.h" +#include "SWM320_wdt.h" + +#endif //__SWM320_H__ diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s new file mode 100644 index 00000000000..025782b081d --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s @@ -0,0 +1,558 @@ +;****************************************************************************************************************************************** +; ļ: startup_SWM2400.s +; ˵: SWM2400Ƭļ +; ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +; ע: +; 汾: V1.1.0 20171025 +; ¼: +; +; +;****************************************************************************************************************************************** +; @attention +; +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +; -ECTION WITH THEIR PRODUCTS. +; +; COPYRIGHT 2012 Synwit Technology +;****************************************************************************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD GPIOA0_Handler + DCD GPIOA1_Handler + DCD GPIOA2_Handler + DCD GPIOA3_Handler + DCD GPIOA4_Handler + DCD GPIOA5_Handler + DCD GPIOA6_Handler + DCD GPIOA7_Handler + DCD GPIOB0_Handler + DCD GPIOB1_Handler + DCD GPIOB2_Handler + DCD GPIOB3_Handler + DCD GPIOB4_Handler + DCD GPIOB5_Handler + DCD GPIOB6_Handler + DCD GPIOB7_Handler + DCD GPIOC0_Handler + DCD GPIOC1_Handler + DCD GPIOC2_Handler + DCD GPIOC3_Handler + DCD GPIOC4_Handler + DCD GPIOC5_Handler + DCD GPIOC6_Handler + DCD GPIOC7_Handler + DCD GPIOM0_Handler + DCD GPIOM1_Handler + DCD GPIOM2_Handler + DCD GPIOM3_Handler + DCD GPIOM4_Handler + DCD GPIOM5_Handler + DCD GPIOM6_Handler + DCD GPIOM7_Handler + DCD DMA_Handler + DCD LCD_Handler + DCD NORFLC_Handler + DCD CAN_Handler + DCD PULSE_Handler + DCD WDT_Handler + DCD PWM_Handler + DCD UART0_Handler + DCD UART1_Handler + DCD UART2_Handler + DCD UART3_Handler + DCD 0 + DCD I2C0_Handler + DCD I2C1_Handler + DCD SPI0_Handler + DCD ADC0_Handler + DCD RTC_Handler + DCD ANAC_Handler + DCD SDIO_Handler + DCD GPIOA_Handler + DCD GPIOB_Handler + DCD GPIOC_Handler + DCD GPIOM_Handler + DCD GPION_Handler + DCD GPIOP_Handler + DCD ADC1_Handler + DCD FPU_Handler + DCD SPI1_Handler + DCD TIMR0_Handler + DCD TIMR1_Handler + DCD TIMR2_Handler + DCD TIMR3_Handler + DCD TIMR4_Handler + DCD TIMR5_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + + + AREA |.text|, CODE, READONLY + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +GPIOA0_Handler PROC + EXPORT GPIOA0_Handler [WEAK] + B . + ENDP + +GPIOA1_Handler PROC + EXPORT GPIOA1_Handler [WEAK] + B . + ENDP + +GPIOA2_Handler PROC + EXPORT GPIOA2_Handler [WEAK] + B . + ENDP + +GPIOA3_Handler PROC + EXPORT GPIOA3_Handler [WEAK] + B . + ENDP + +GPIOA4_Handler PROC + EXPORT GPIOA4_Handler [WEAK] + B . + ENDP + +GPIOA5_Handler PROC + EXPORT GPIOA5_Handler [WEAK] + B . + ENDP + +GPIOA6_Handler PROC + EXPORT GPIOA6_Handler [WEAK] + B . + ENDP + +GPIOA7_Handler PROC + EXPORT GPIOA7_Handler [WEAK] + B . + ENDP + +GPIOB0_Handler PROC + EXPORT GPIOB0_Handler [WEAK] + B . + ENDP + +GPIOB1_Handler PROC + EXPORT GPIOB1_Handler [WEAK] + B . + ENDP + +GPIOB2_Handler PROC + EXPORT GPIOB2_Handler [WEAK] + B . + ENDP + +GPIOB3_Handler PROC + EXPORT GPIOB3_Handler [WEAK] + B . + ENDP + +GPIOB4_Handler PROC + EXPORT GPIOB4_Handler [WEAK] + B . + ENDP + +GPIOB5_Handler PROC + EXPORT GPIOB5_Handler [WEAK] + B . + ENDP + +GPIOB6_Handler PROC + EXPORT GPIOB6_Handler [WEAK] + B . + ENDP + +GPIOB7_Handler PROC + EXPORT GPIOB7_Handler [WEAK] + B . + ENDP + +GPIOC0_Handler PROC + EXPORT GPIOC0_Handler [WEAK] + B . + ENDP + +GPIOC1_Handler PROC + EXPORT GPIOC1_Handler [WEAK] + B . + ENDP + +GPIOC2_Handler PROC + EXPORT GPIOC2_Handler [WEAK] + B . + ENDP + +GPIOC3_Handler PROC + EXPORT GPIOC3_Handler [WEAK] + B . + ENDP + +GPIOC4_Handler PROC + EXPORT GPIOC4_Handler [WEAK] + B . + ENDP + +GPIOC5_Handler PROC + EXPORT GPIOC5_Handler [WEAK] + B . + ENDP + +GPIOC6_Handler PROC + EXPORT GPIOC6_Handler [WEAK] + B . + ENDP + +GPIOC7_Handler PROC + EXPORT GPIOC7_Handler [WEAK] + B . + ENDP + +GPIOM0_Handler PROC + EXPORT GPIOM0_Handler [WEAK] + B . + ENDP + +GPIOM1_Handler PROC + EXPORT GPIOM1_Handler [WEAK] + B . + ENDP + +GPIOM2_Handler PROC + EXPORT GPIOM2_Handler [WEAK] + B . + ENDP + +GPIOM3_Handler PROC + EXPORT GPIOM3_Handler [WEAK] + B . + ENDP + +GPIOM4_Handler PROC + EXPORT GPIOM4_Handler [WEAK] + B . + ENDP + +GPIOM5_Handler PROC + EXPORT GPIOM5_Handler [WEAK] + B . + ENDP + +GPIOM6_Handler PROC + EXPORT GPIOM6_Handler [WEAK] + B . + ENDP + +GPIOM7_Handler PROC + EXPORT GPIOM7_Handler [WEAK] + B . + ENDP + +DMA_Handler PROC + EXPORT DMA_Handler [WEAK] + B . + ENDP + +LCD_Handler PROC + EXPORT LCD_Handler [WEAK] + B . + ENDP + +NORFLC_Handler PROC + EXPORT NORFLC_Handler [WEAK] + B . + ENDP + +CAN_Handler PROC + EXPORT CAN_Handler [WEAK] + B . + ENDP + +PULSE_Handler PROC + EXPORT PULSE_Handler [WEAK] + B . + ENDP + +WDT_Handler PROC + EXPORT WDT_Handler [WEAK] + B . + ENDP + +PWM_Handler PROC + EXPORT PWM_Handler [WEAK] + B . + ENDP + +UART0_Handler PROC + EXPORT UART0_Handler [WEAK] + B . + ENDP + +UART1_Handler PROC + EXPORT UART1_Handler [WEAK] + B . + ENDP + +UART2_Handler PROC + EXPORT UART2_Handler [WEAK] + B . + ENDP + +UART3_Handler PROC + EXPORT UART3_Handler [WEAK] + B . + ENDP + +I2C0_Handler PROC + EXPORT I2C0_Handler [WEAK] + B . + ENDP + +I2C1_Handler PROC + EXPORT I2C1_Handler [WEAK] + B . + ENDP + +SPI0_Handler PROC + EXPORT SPI0_Handler [WEAK] + B . + ENDP + +ADC0_Handler PROC + EXPORT ADC0_Handler [WEAK] + B . + ENDP + +RTC_Handler PROC + EXPORT RTC_Handler [WEAK] + B . + ENDP + +ANAC_Handler PROC + EXPORT ANAC_Handler [WEAK] + B . + ENDP + +SDIO_Handler PROC + EXPORT SDIO_Handler [WEAK] + B . + ENDP + +GPIOA_Handler PROC + EXPORT GPIOA_Handler [WEAK] + B . + ENDP + +GPIOB_Handler PROC + EXPORT GPIOB_Handler [WEAK] + B . + ENDP + +GPIOC_Handler PROC + EXPORT GPIOC_Handler [WEAK] + B . + ENDP + +GPIOM_Handler PROC + EXPORT GPIOM_Handler [WEAK] + B . + ENDP + +GPION_Handler PROC + EXPORT GPION_Handler [WEAK] + B . + ENDP + +GPIOP_Handler PROC + EXPORT GPIOP_Handler [WEAK] + B . + ENDP + +ADC1_Handler PROC + EXPORT ADC1_Handler [WEAK] + B . + ENDP + +FPU_Handler PROC + EXPORT FPU_Handler [WEAK] + B . + ENDP + +SPI1_Handler PROC + EXPORT SPI1_Handler [WEAK] + B . + ENDP + +TIMR0_Handler PROC + EXPORT TIMR0_Handler [WEAK] + B . + ENDP + +TIMR1_Handler PROC + EXPORT TIMR1_Handler [WEAK] + B . + ENDP + +TIMR2_Handler PROC + EXPORT TIMR2_Handler [WEAK] + B . + ENDP + +TIMR3_Handler PROC + EXPORT TIMR3_Handler [WEAK] + B . + ENDP + +TIMR4_Handler PROC + EXPORT TIMR4_Handler [WEAK] + B . + ENDP + +TIMR5_Handler PROC + EXPORT TIMR5_Handler [WEAK] + B . + ENDP + + ALIGN + + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s new file mode 100644 index 00000000000..c0bf32e04a1 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s @@ -0,0 +1,406 @@ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point.*/ + bl entry + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word GPIOA0_Handler + .word GPIOA1_Handler + .word GPIOA2_Handler + .word GPIOA3_Handler + .word GPIOA4_Handler + .word GPIOA5_Handler + .word GPIOA6_Handler + .word GPIOA7_Handler + .word GPIOB0_Handler + .word GPIOB1_Handler + .word GPIOB2_Handler + .word GPIOB3_Handler + .word GPIOB4_Handler + .word GPIOB5_Handler + .word GPIOB6_Handler + .word GPIOB7_Handler + .word GPIOC0_Handler + .word GPIOC1_Handler + .word GPIOC2_Handler + .word GPIOC3_Handler + .word GPIOC4_Handler + .word GPIOC5_Handler + .word GPIOC6_Handler + .word GPIOC7_Handler + .word GPIOM0_Handler + .word GPIOM1_Handler + .word GPIOM2_Handler + .word GPIOM3_Handler + .word GPIOM4_Handler + .word GPIOM5_Handler + .word GPIOM6_Handler + .word GPIOM7_Handler + .word DMA_Handler + .word LCD_Handler + .word NORFLC_Handler + .word CAN_Handler + .word PULSE_Handler + .word WDT_Handler + .word PWM_Handler + .word UART0_Handler + .word UART1_Handler + .word UART2_Handler + .word UART3_Handler + .word 0 + .word I2C0_Handler + .word I2C1_Handler + .word SPI0_Handler + .word ADC0_Handler + .word RTC_Handler + .word ANAC_Handler + .word SDIO_Handler + .word GPIOA_Handler + .word GPIOB_Handler + .word GPIOC_Handler + .word GPIOM_Handler + .word GPION_Handler + .word GPIOP_Handler + .word ADC1_Handler + .word FPU_Handler + .word SPI1_Handler + .word TIMR0_Handler + .word TIMR1_Handler + .word TIMR2_Handler + .word TIMR3_Handler + .word TIMR4_Handler + .word TIMR5_Handler +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak GPIOA0_Handler + .thumb_set GPIOA0_Handler,Default_Handler + + .weak GPIOA1_Handler + .thumb_set GPIOA1_Handler,Default_Handler + + .weak GPIOA2_Handler + .thumb_set GPIOA2_Handler,Default_Handler + + .weak GPIOA3_Handler + .thumb_set GPIOA3_Handler,Default_Handler + + .weak GPIOA4_Handler + .thumb_set GPIOA4_Handler,Default_Handler + + .weak GPIOA5_Handler + .thumb_set GPIOA5_Handler,Default_Handler + + .weak GPIOA6_Handler + .thumb_set GPIOA6_Handler,Default_Handler + + .weak GPIOA7_Handler + .thumb_set GPIOA7_Handler,Default_Handler + + .weak GPIOB0_Handler + .thumb_set GPIOB0_Handler,Default_Handler + + .weak GPIOB1_Handler + .thumb_set GPIOB1_Handler,Default_Handler + + .weak GPIOB2_Handler + .thumb_set GPIOB2_Handler,Default_Handler + + .weak GPIOB3_Handler + .thumb_set GPIOB3_Handler,Default_Handler + + .weak GPIOB4_Handler + .thumb_set GPIOB4_Handler,Default_Handler + + .weak GPIOB5_Handler + .thumb_set GPIOB5_Handler,Default_Handler + + .weak GPIOB6_Handler + .thumb_set GPIOB6_Handler,Default_Handler + + .weak GPIOB7_Handler + .thumb_set GPIOB7_Handler,Default_Handler + + .weak GPIOC0_Handler + .thumb_set GPIOC0_Handler,Default_Handler + + .weak GPIOC1_Handler + .thumb_set GPIOC1_Handler,Default_Handler + + .weak GPIOC2_Handler + .thumb_set GPIOC2_Handler,Default_Handler + + .weak GPIOC3_Handler + .thumb_set GPIOC3_Handler,Default_Handler + + .weak GPIOC4_Handler + .thumb_set GPIOC4_Handler,Default_Handler + + .weak GPIOC5_Handler + .thumb_set GPIOC5_Handler,Default_Handler + + .weak GPIOC6_Handler + .thumb_set GPIOC6_Handler,Default_Handler + + .weak GPIOC7_Handler + .thumb_set GPIOC7_Handler,Default_Handler + + .weak GPIOM0_Handler + .thumb_set GPIOM0_Handler,Default_Handler + + .weak GPIOM1_Handler + .thumb_set GPIOM1_Handler,Default_Handler + + .weak GPIOM2_Handler + .thumb_set GPIOM2_Handler,Default_Handler + + .weak GPIOM3_Handler + .thumb_set GPIOM3_Handler,Default_Handler + + .weak GPIOM4_Handler + .thumb_set GPIOM4_Handler,Default_Handler + + .weak GPIOM5_Handler + .thumb_set GPIOM5_Handler,Default_Handler + + .weak GPIOM6_Handler + .thumb_set GPIOM6_Handler,Default_Handler + + .weak GPIOM7_Handler + .thumb_set GPIOM7_Handler,Default_Handler + + .weak DMA_Handler + .thumb_set DMA_Handler,Default_Handler + + .weak LCD_Handler + .thumb_set LCD_Handler,Default_Handler + + .weak NORFLC_Handler + .thumb_set NORFLC_Handler,Default_Handler + + .weak CAN_Handler + .thumb_set CAN_Handler,Default_Handler + + .weak PULSE_Handler + .thumb_set PULSE_Handler,Default_Handler + + .weak WDT_Handler + .thumb_set WDT_Handler,Default_Handler + + .weak PWM_Handler + .thumb_set PWM_Handler,Default_Handler + + .weak UART0_Handler + .thumb_set UART0_Handler,Default_Handler + + .weak UART1_Handler + .thumb_set UART1_Handler,Default_Handler + + .weak UART2_Handler + .thumb_set UART2_Handler,Default_Handler + + .weak UART3_Handler + .thumb_set UART3_Handler,Default_Handler + + .weak I2C0_Handler + .thumb_set I2C0_Handler,Default_Handler + + .weak I2C1_Handler + .thumb_set I2C1_Handler,Default_Handler + + .weak SPI0_Handler + .thumb_set SPI0_Handler,Default_Handler + + .weak ADC0_Handler + .thumb_set ADC0_Handler,Default_Handler + + .weak RTC_Handler + .thumb_set RTC_Handler,Default_Handler + + .weak ANAC_Handler + .thumb_set ANAC_Handler,Default_Handler + + .weak SDIO_Handler + .thumb_set SDIO_Handler,Default_Handler + + .weak GPIOA_Handler + .thumb_set GPIOA_Handler,Default_Handler + + .weak GPIOB_Handler + .thumb_set GPIOB_Handler,Default_Handler + + .weak GPIOC_Handler + .thumb_set GPIOC_Handler,Default_Handler + + .weak GPIOM_Handler + .thumb_set GPIOM_Handler,Default_Handler + + .weak GPION_Handler + .thumb_set GPION_Handler,Default_Handler + + .weak GPIOP_Handler + .thumb_set GPIOP_Handler,Default_Handler + + .weak ADC1_Handler + .thumb_set ADC1_Handler,Default_Handler + + .weak FPU_Handler + .thumb_set FPU_Handler,Default_Handler + + .weak SPI1_Handler + .thumb_set SPI1_Handler,Default_Handler + + .weak TIMR0_Handler + .thumb_set TIMR0_Handler,Default_Handler + + .weak TIMR1_Handler + .thumb_set TIMR1_Handler,Default_Handler + + .weak TIMR2_Handler + .thumb_set TIMR2_Handler,Default_Handler + + .weak TIMR3_Handler + .thumb_set TIMR3_Handler,Default_Handler + + .weak TIMR4_Handler + .thumb_set TIMR4_Handler,Default_Handler + + .weak TIMR5_Handler + .thumb_set TIMR5_Handler,Default_Handler + diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s new file mode 100644 index 00000000000..baecc70d024 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s @@ -0,0 +1,464 @@ +;****************************************************************************************************************************************** +; 文件名称: startup_SWM2400.s +; 功能说明: SWM2400单片机的启动文件 +; 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +; 注意事项: +; 版本日期: V1.0.0 2016年1月30日 +; 升级记录: +; +; +;****************************************************************************************************************************************** +; @attention +; +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +; -ECTION WITH THEIR PRODUCTS. +; +; COPYRIGHT 2012 Synwit Technology +;****************************************************************************************************************************************** + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD GPIOA0_Handler + DCD GPIOA1_Handler + DCD GPIOA2_Handler + DCD GPIOA3_Handler + DCD GPIOA4_Handler + DCD GPIOA5_Handler + DCD GPIOA6_Handler + DCD GPIOA7_Handler + DCD GPIOB0_Handler + DCD GPIOB1_Handler + DCD GPIOB2_Handler + DCD GPIOB3_Handler + DCD GPIOB4_Handler + DCD GPIOB5_Handler + DCD GPIOB6_Handler + DCD GPIOB7_Handler + DCD GPIOC0_Handler + DCD GPIOC1_Handler + DCD GPIOC2_Handler + DCD GPIOC3_Handler + DCD GPIOC4_Handler + DCD GPIOC5_Handler + DCD GPIOC6_Handler + DCD GPIOC7_Handler + DCD GPIOM0_Handler + DCD GPIOM1_Handler + DCD GPIOM2_Handler + DCD GPIOM3_Handler + DCD GPIOM4_Handler + DCD GPIOM5_Handler + DCD GPIOM6_Handler + DCD GPIOM7_Handler + DCD DMA_Handler + DCD LCD_Handler + DCD NORFLC_Handler + DCD CAN_Handler + DCD TIMR_Handler + DCD WDT_Handler + DCD PWM_Handler + DCD UART0_Handler + DCD UART1_Handler + DCD UART2_Handler + DCD UART3_Handler + DCD 0 + DCD I2C0_Handler + DCD I2C1_Handler + DCD SPI0_Handler + DCD ADC0_Handler + DCD RTC_Handler + DCD ANAC_Handler + DCD SDIO_Handler + DCD GPIOA_Handler + DCD GPIOB_Handler + DCD GPIOC_Handler + DCD GPIOM_Handler + DCD GPION_Handler + DCD GPIOP_Handler + DCD ADC1_Handler + DCD FPU_Handler + DCD SPI1_Handler + + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK GPIOA0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA0_Handler + B GPIOA0_Handler + + PUBWEAK GPIOA1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA1_Handler + B GPIOA1_Handler + + PUBWEAK GPIOA2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA2_Handler + B GPIOA2_Handler + + PUBWEAK GPIOA3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA3_Handler + B GPIOA3_Handler + + PUBWEAK GPIOA4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA4_Handler + B GPIOA4_Handler + + PUBWEAK GPIOA5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA5_Handler + B GPIOA5_Handler + + PUBWEAK GPIOA6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA6_Handler + B GPIOA6_Handler + + PUBWEAK GPIOA7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA7_Handler + B GPIOA7_Handler + + PUBWEAK GPIOB0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB0_Handler + B GPIOB0_Handler + + PUBWEAK GPIOB1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB1_Handler + B GPIOB1_Handler + + PUBWEAK GPIOB2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB2_Handler + B GPIOB2_Handler + + PUBWEAK GPIOB3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB3_Handler + B GPIOB3_Handler + + PUBWEAK GPIOB4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB4_Handler + B GPIOB4_Handler + + PUBWEAK GPIOB5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB5_Handler + B GPIOB5_Handler + + PUBWEAK GPIOB6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB6_Handler + B GPIOB6_Handler + + PUBWEAK GPIOB7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB7_Handler + B GPIOB7_Handler + + PUBWEAK GPIOC0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC0_Handler + B GPIOC0_Handler + + PUBWEAK GPIOC1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC1_Handler + B GPIOC1_Handler + + PUBWEAK GPIOC2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC2_Handler + B GPIOC2_Handler + + PUBWEAK GPIOC3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC3_Handler + B GPIOC3_Handler + + PUBWEAK GPIOC4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC4_Handler + B GPIOC4_Handler + + PUBWEAK GPIOC5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC5_Handler + B GPIOC5_Handler + + PUBWEAK GPIOC6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC6_Handler + B GPIOC6_Handler + + PUBWEAK GPIOC7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC7_Handler + B GPIOC7_Handler + + PUBWEAK GPIOM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM0_Handler + B GPIOM0_Handler + + PUBWEAK GPIOM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM1_Handler + B GPIOM1_Handler + + PUBWEAK GPIOM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM2_Handler + B GPIOM2_Handler + + PUBWEAK GPIOM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM3_Handler + B GPIOM3_Handler + + PUBWEAK GPIOM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM4_Handler + B GPIOM4_Handler + + PUBWEAK GPIOM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM5_Handler + B GPIOM5_Handler + + PUBWEAK GPIOM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM6_Handler + B GPIOM6_Handler + + PUBWEAK GPIOM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM7_Handler + B GPIOM7_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK LCD_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_Handler + B LCD_Handler + + PUBWEAK NORFLC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NORFLC_Handler + B NORFLC_Handler + + PUBWEAK CAN_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN_Handler + B CAN_Handler + + PUBWEAK TIMR_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR_Handler + B TIMR_Handler + + PUBWEAK WDT_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT_Handler + B WDT_Handler + + PUBWEAK PWM_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM_Handler + B PWM_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK UART3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART3_Handler + B UART3_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK SPI0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_Handler + B SPI0_Handler + + PUBWEAK ADC0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_Handler + B ADC0_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ANAC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ANAC_Handler + B ANAC_Handler + + PUBWEAK SDIO_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_Handler + B SDIO_Handler + + PUBWEAK GPIOA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA_Handler + B GPIOA_Handler + + PUBWEAK GPIOB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB_Handler + B GPIOB_Handler + + PUBWEAK GPIOC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC_Handler + B GPIOC_Handler + + PUBWEAK GPIOM_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOM_Handler + B GPIOM_Handler + + PUBWEAK GPION_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPION_Handler + B GPION_Handler + + PUBWEAK GPIOP_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOP_Handler + B GPIOP_Handler + + PUBWEAK ADC1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_Handler + B ADC1_Handler + + PUBWEAK FPU_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_Handler + B FPU_Handler + + PUBWEAK SPI1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_Handler + B SPI1_Handler + + + END diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c new file mode 100644 index 00000000000..d6e7c618095 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c @@ -0,0 +1,215 @@ +/****************************************************************************************************************************************** +* 文件名称: system_SWM320.c +* 功能说明: SWM320单片机的时钟设置 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include +#include "SWM320.h" + +/****************************************************************************************************************************************** + * 系统时钟设定 + *****************************************************************************************************************************************/ +#define SYS_CLK_20MHz 0 //0 内部高频20MHz RC振荡器 +#define SYS_CLK_40MHz 1 //1 内部高频40MHz RC振荡器 +#define SYS_CLK_32KHz 2 //2 内部低频32KHz RC振荡器 +#define SYS_CLK_XTAL 3 //3 外部晶体振荡器（2-30MHz） +#define SYS_CLK_PLL 4 //4 片内锁相环输出 + +#define SYS_CLK SYS_CLK_PLL + +#define SYS_CLK_DIV_1 0 +#define SYS_CLK_DIV_2 1 + +#define SYS_CLK_DIV SYS_CLK_DIV_1 + +#define __HSI (20000000UL) //高速内部时钟 +#define __LSI (32000UL) //低速内部时钟 +#define __HSE (20000000UL) //高速外部时钟 + +/********************************** PLL 设定 ********************************************** + * VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV + * PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV + *****************************************************************************************/ +#define SYS_PLL_SRC SYS_CLK_XTAL //可取值SYS_CLK_20MHz、SYS_CLK_XTAL + +#define PLL_IN_DIV 5 + +#define PLL_FB_DIV 60 + +#define PLL_OUT_DIV8 0 +#define PLL_OUT_DIV4 1 +#define PLL_OUT_DIV2 2 + +#define PLL_OUT_DIV PLL_OUT_DIV8 + +uint32_t SystemCoreClock = (120000000UL); //System Clock Frequency (Core Clock) +uint32_t CyclesPerUs = ((120000000UL) / 1000000); //Cycles per micro second + +/****************************************************************************************************************************************** +* 函数名称: +* 功能说明: This function is used to update the variable SystemCoreClock and must be called whenever the core clock is changed +* 输 入: +* 输 出: +* 注意事项: +******************************************************************************************************************************************/ +void SystemCoreClockUpdate(void) +{ + if (SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) //SYS_CLK <= HFCK + { + if (SYS->CLKSEL & SYS_CLKSEL_HFCK_Msk) //HFCK <= XTAL + { + SystemCoreClock = __HSE; + } + else //HFCK <= HRC + { + if (SYS->HRCCR & SYS_HRCCR_DBL_Msk) //HRC = 40MHz + { + SystemCoreClock = __HSI * 2; + } + else //HRC = 20MHz + { + SystemCoreClock = __HSI; + } + } + } + else //SYS_CLK <= LFCK + { + if (SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) //LFCK <= PLL + { + if (SYS->PLLCR & SYS_PLLCR_INSEL_Msk) //PLL_SRC <= HRC + { + SystemCoreClock = __HSI; + } + else //PLL_SRC <= XTAL + { + SystemCoreClock = __HSE; + } + + SystemCoreClock = SystemCoreClock / PLL_IN_DIV * PLL_FB_DIV * 4 / (2 << (2 - PLL_OUT_DIV)); + } + else //LFCK <= LRC + { + SystemCoreClock = __LSI; + } + } + + if (SYS->CLKDIV & SYS_CLKDIV_SYS_Msk) + SystemCoreClock /= 2; +} + +/****************************************************************************************************************************************** +* 函数名称: +* 功能说明: The necessary initializaiton of systerm +* 输 入: +* 输 出: +* 注意事项: +******************************************************************************************************************************************/ +void SystemInit(void) +{ + uint32_t i; + + SYS->CLKEN |= (1 << SYS_CLKEN_ANAC_Pos); + + switch (SYS_CLK) + { + case SYS_CLK_20MHz: //0 内部高频20MHz RC振荡器 + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz + + SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + break; + + case SYS_CLK_40MHz: //1 内部高频40MHz RC振荡器 + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz + + SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + break; + + case SYS_CLK_32KHz: //2 内部低频32KHz RC振荡器 + SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); + + SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); + + for (i = 0; i < 20000; i++) + ; + + SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC + SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK + break; + + case SYS_CLK_XTAL: //3 外部晶体振荡器（2-30MHz） + SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); + + for (i = 0; i < 20000; i++) + ; + + SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + break; + + case SYS_CLK_PLL: //4 片内锁相环输出 + PLLInit(); + SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos); + + SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK <= PLL + SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK + break; + } + + SYS->CLKDIV &= ~SYS_CLKDIV_SYS_Msk; + SYS->CLKDIV |= (SYS_CLK_DIV << SYS_CLKDIV_SYS_Pos); + + SystemCoreClockUpdate(); +} + +void PLLInit(void) +{ + uint32_t i; + + if (SYS_PLL_SRC == SYS_CLK_20MHz) + { + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz + + SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC + } + else if (SYS_PLL_SRC == SYS_CLK_XTAL) + { + SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); + + for (i = 0; i < 20000; i++) + ; + + SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL + } + + SYS->PLLDIV &= ~(SYS_PLLDIV_INDIV_Msk | + SYS_PLLDIV_FBDIV_Msk | + SYS_PLLDIV_OUTDIV_Msk); + SYS->PLLDIV |= (PLL_IN_DIV << SYS_PLLDIV_INDIV_Pos) | + (PLL_FB_DIV << SYS_PLLDIV_FBDIV_Pos) | + (PLL_OUT_DIV << SYS_PLLDIV_OUTDIV_Pos); + + SYS->PLLCR &= ~(1 << SYS_PLLCR_OFF_Pos); + + while (SYS->PLLLOCK == 0) + ; //等待PLL锁定 +} diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h new file mode 100644 index 00000000000..4f44ccd3ab9 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h @@ -0,0 +1,24 @@ +#ifndef __SYSTEM_SWM320_H__ +#define __SYSTEM_SWM320_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern uint32_t CyclesPerUs; // Cycles per micro second + + +extern void SystemInit(void); + +extern void SystemCoreClockUpdate(void); + +extern void PLLInit(void); + + +#ifdef __cplusplus +} +#endif + +#endif //__SYSTEM_SWM320_H__ diff --git a/bsp/swm320-lq100/Libraries/SConscript b/bsp/swm320-lq100/Libraries/SConscript new file mode 100644 index 00000000000..92c6725dced --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SConscript @@ -0,0 +1,17 @@ +from building import * +import rtconfig +cwd = GetCurrentDir() +src = Glob('CMSIS/DeviceSupport/*.c') +CPPPATH = [cwd + '/CMSIS/CoreSupport', cwd + '/CMSIS/DeviceSupport', cwd + '/SWM320_StdPeriph_Driver'] + +src += Glob('SWM320_StdPeriph_Driver/*.c') + +if rtconfig.CROSS_TOOL == 'gcc': + src += ['CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['CMSIS/DeviceSupport/startup/arm/startup_SWM320.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['CMSIS/DeviceSupport/startup/iar/startup_SWM320.s'] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c new file mode 100644 index 00000000000..d6c48b10d4a --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c @@ -0,0 +1,522 @@ +/****************************************************************************************************************************************** +* 文件名称: SWM320_adc.c +* 功能说明: SWM320单片机的ADC数模转换器功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_adc.h" + +/****************************************************************************************************************************************** +* 函数名称: ADC_Init() +* 功能说明: ADC模数转换器初始化 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，有效值包括ADC0、ADC1 +* ADC_InitStructure * initStruct 包含ADC各相关定值的结构体 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct) +{ + switch ((uint32_t)ADCx) + { + case ((uint32_t)ADC0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_ADC0_Pos); + break; + + case ((uint32_t)ADC1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_ADC1_Pos); + break; + } + + ADC_Close(ADCx); //一些关键寄存器只能在ADC关闭时设置 + + if (initStruct->clk_src == ADC_CLKSRC_HRC) + { + ADCx->CTRL |= (1 << ADC_CTRL_CLKSRC_Pos); + + ADCx->CTRL2 &= ~ADC_CTRL2_CLKDIV_Msk; + ADCx->CTRL2 |= (initStruct->clk_div << ADC_CTRL2_CLKDIV_Pos); + } + else + { + if (SYS->PLLCR & SYS_PLLCR_OFF_Msk) + PLLInit(); + + ADCx->CTRL &= ~(1 << ADC_CTRL_CLKSRC_Pos); + + SYS->PLLDIV &= ~SYS_PLLDIV_ADVCO_Msk; + SYS->PLLDIV |= ((initStruct->clk_src - 2) << SYS_PLLDIV_ADVCO_Pos); + + SYS->PLLDIV &= ~SYS_PLLDIV_ADDIV_Msk; + SYS->PLLDIV |= (initStruct->clk_div << SYS_PLLDIV_ADDIV_Pos); + } + + ADCx->CTRL2 &= ~(ADC_CTRL2_ADCEVCM_Msk | ADC_CTRL2_PGAIVCM_Msk | ADC_CTRL2_PGAGAIN_Msk | ADC_CTRL2_PGAVCM_Msk); + ADCx->CTRL2 |= (0 << ADC_CTRL2_ADCEVCM_Pos) | + (PGA_VCM_INTERNAL << ADC_CTRL2_PGAIVCM_Pos) | + (6 << ADC_CTRL2_PGAGAIN_Pos) | + ((uint32_t)6 << ADC_CTRL2_PGAVCM_Pos); + + ADCx->CTRL &= ~(0xFF << ADC_CTRL_CH0_Pos); + ADCx->CTRL |= (initStruct->channels << ADC_CTRL_CH0_Pos); + + ADCx->CTRL &= ~(ADC_CTRL_AVG_Msk | ADC_CTRL_TRIG_Msk | ADC_CTRL_CONT_Msk); + ADCx->CTRL |= (initStruct->samplAvg << ADC_CTRL_AVG_Pos) | + (initStruct->trig_src << ADC_CTRL_TRIG_Pos) | + (initStruct->Continue << ADC_CTRL_CONT_Pos); + + ADCx->IF = 0xFFFFFFFF; //清除中断标志 + + ADCx->IE &= ~(ADC_IE_CH0EOC_Msk | ADC_IE_CH1EOC_Msk | ADC_IE_CH2EOC_Msk | ADC_IE_CH3EOC_Msk | + ADC_IE_CH4EOC_Msk | ADC_IE_CH5EOC_Msk | ADC_IE_CH6EOC_Msk | ADC_IE_CH7EOC_Msk); + ADCx->IE |= (((initStruct->EOC_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6EOC_Pos) | + (((initStruct->EOC_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7EOC_Pos); + + ADCx->IE &= ~(ADC_IE_CH0OVF_Msk | ADC_IE_CH1OVF_Msk | ADC_IE_CH2OVF_Msk | ADC_IE_CH3OVF_Msk | + ADC_IE_CH4OVF_Msk | ADC_IE_CH5OVF_Msk | ADC_IE_CH6OVF_Msk | ADC_IE_CH7OVF_Msk); + ADCx->IE |= (((initStruct->OVF_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6OVF_Pos) | + (((initStruct->OVF_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7OVF_Pos); + + ADCx->IE &= ~(ADC_IE_CH0HFULL_Msk | ADC_IE_CH1HFULL_Msk | ADC_IE_CH2HFULL_Msk | ADC_IE_CH3HFULL_Msk | + ADC_IE_CH4HFULL_Msk | ADC_IE_CH5HFULL_Msk | ADC_IE_CH6HFULL_Msk | ADC_IE_CH7HFULL_Msk); + ADCx->IE |= (((initStruct->HFULL_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6HFULL_Pos) | + (((initStruct->HFULL_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7HFULL_Pos); + + ADCx->IE &= ~(uint32_t)(ADC_IE_CH0FULL_Msk | ADC_IE_CH1FULL_Msk | ADC_IE_CH2FULL_Msk | ADC_IE_CH3FULL_Msk | + ADC_IE_CH4FULL_Msk | ADC_IE_CH5FULL_Msk | ADC_IE_CH6FULL_Msk | ADC_IE_CH7FULL_Msk); + ADCx->IE |= (((initStruct->FULL_IEn & ADC_CH0) ? 1 : 0) << ADC_IE_CH0FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH1) ? 1 : 0) << ADC_IE_CH1FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH2) ? 1 : 0) << ADC_IE_CH2FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH3) ? 1 : 0) << ADC_IE_CH3FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH4) ? 1 : 0) << ADC_IE_CH4FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH5) ? 1 : 0) << ADC_IE_CH5FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH6) ? 1 : 0) << ADC_IE_CH6FULL_Pos) | + (((initStruct->FULL_IEn & ADC_CH7) ? 1 : 0) << ADC_IE_CH7FULL_Pos); + + switch ((uint32_t)ADCx) + { + case ((uint32_t)ADC0): + if (initStruct->EOC_IEn | initStruct->OVF_IEn | initStruct->HFULL_IEn | initStruct->FULL_IEn) + { + NVIC_EnableIRQ(ADC0_IRQn); + } + else + { + NVIC_DisableIRQ(ADC0_IRQn); + } + break; + + case ((uint32_t)ADC1): + if (initStruct->EOC_IEn | initStruct->OVF_IEn | initStruct->HFULL_IEn | initStruct->FULL_IEn) + { + NVIC_EnableIRQ(ADC1_IRQn); + } + else + { + NVIC_DisableIRQ(ADC1_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_Open() +* 功能说明: ADC开启，可以软件启动、或硬件触发ADC转换 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_Open(ADC_TypeDef *ADCx) +{ + ADCx->CTRL |= (0x01 << ADC_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_Close() +* 功能说明: ADC关闭，无法软件启动、或硬件触发ADC转换 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_Close(ADC_TypeDef *ADCx) +{ + ADCx->CTRL &= ~(0x01 << ADC_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_Start() +* 功能说明: 软件触发模式下启动ADC转换 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_Start(ADC_TypeDef *ADCx) +{ + ADCx->START |= (0x01 << ADC_START_GO_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_Stop() +* 功能说明: 软件触发模式下停止ADC转换 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_Stop(ADC_TypeDef *ADCx) +{ + ADCx->START &= ~(0x01 << ADC_START_GO_Pos); +} + +static uint32_t chn2idx(uint32_t chn) +{ + uint32_t idx = 0; + + switch (chn) + { + case 0x01: + idx = 0; + break; + case 0x02: + idx = 1; + break; + case 0x04: + idx = 2; + break; + case 0x08: + idx = 3; + break; + case 0x10: + idx = 4; + break; + case 0x20: + idx = 5; + break; + case 0x40: + idx = 6; + break; + case 0x80: + idx = 7; + break; + } + + return idx; +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_Read() +* 功能说明: 从指定通道读取转换结果 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要读取转换结果的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: uint32_t 读取到的转换结果 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t dat = 0; + uint32_t idx = chn2idx(chn); + + dat = ADCx->CH[idx].DATA; + + ADCx->CH[idx].STAT = 0x01; //清除EOC标志 + + return dat; +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IsEOC() +* 功能说明: 指定通道是否End Of Conversion +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要查询状态的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->CH[idx].STAT & ADC_STAT_EOC_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_ChnSelect() +* 功能说明: ADC通道选通，模数转换会在选通的通道上依次采样转换 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chns 要选通的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_ChnSelect(ADC_TypeDef *ADCx, uint32_t chns) +{ + ADCx->CTRL &= ~(0xFF << ADC_CTRL_CH0_Pos); + ADCx->CTRL |= (chns << ADC_CTRL_CH0_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntEOCEn() +* 功能说明: 转换完成中断使能 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntEOCEn(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx * 4)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntEOCDis() +* 功能说明: 转换完成中断禁止 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntEOCDis(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx * 4)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntEOCClr() +* 功能说明: 转换完成中断标志清除 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntEOCClr(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx * 4)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntEOCStat() +* 功能说明: 转换完成中断状态 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx * 4))) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntOVFEn() +* 功能说明: 数据溢出中断使能 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntOVFEn(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx * 4 + 1)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntOVFDis() +* 功能说明: 数据溢出中断禁止 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntOVFDis(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx * 4 + 1)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntOVFClr() +* 功能说明: 数据溢出中断标志清除 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntOVFClr(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx * 4 + 1)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntOVFStat() +* 功能说明: 数据溢出中断状态 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx * 4 + 1))) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntHFULLEn() +* 功能说明: FIFO半满中断使能 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntHFULLEn(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx * 4 + 2)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntHFULLDis() +* 功能说明: FIFO半满中断禁止 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntHFULLDis(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx * 4 + 2)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntHFULLClr() +* 功能说明: FIFO半满中断标志清除 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntHFULLClr(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx * 4 + 2)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntHFULLStat() +* 功能说明: FIFO半满中断状态 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx * 4 + 2))) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntFULLEn() +* 功能说明: FIFO满中断使能 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntFULLEn(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE |= (0x01 << (idx * 4 + 3)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntFULLDis() +* 功能说明: FIFO满中断禁止 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IE &= ~(0x01 << (idx * 4 + 3)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntFULLClr() +* 功能说明: FIFO满中断标志清除 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + ADCx->IF = (0x01 << (idx * 4 + 3)); +} + +/****************************************************************************************************************************************** +* 函数名称: ADC_IntFULLStat() +* 功能说明: FIFO满中断状态 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn) +{ + uint32_t idx = chn2idx(chn); + + return (ADCx->IF & (0x01 << (idx * 4 + 3))) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h new file mode 100644 index 00000000000..b5906af9089 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h @@ -0,0 +1,83 @@ +#ifndef __SWM320_ADC_H__ +#define __SWM320_ADC_H__ + +typedef struct +{ + uint8_t clk_src; //ADC转换时钟源：ADC_CLKSRC_HRC、ADC_CLKSRC_VCO_DIV16、ADC_CLKSRC_VCO_DIV32、ADC_CLKSRC_VCO_DIV32 + uint8_t clk_div; //ADC转换时钟分频，取值1--31 + uint8_t channels; //ADC转换通道选中，ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） + uint8_t samplAvg; //采样取平均，触发启动ADC转换后，ADC在一个通道上连续采样、转换多次，并将它们的平均值作为该通道转换结果 + uint8_t trig_src; //ADC触发方式：ADC_TRIGSRC_SW、ADC_TRIGSRC_PWM、ADC_TRIGSRC_TIMR2、ADC_TRIGSRC_TIMR3 + uint8_t Continue; //在软件触发模式下：1 连续转换模式，启动后一直采样、转换，直到软件清除START位 + // 0 单次转换模式，转换完成后START位自动清除停止转换 + uint8_t EOC_IEn; //EOC中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） + uint8_t OVF_IEn; //OVF中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） + uint8_t HFULL_IEn; //FIFO半满中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） + uint8_t FULL_IEn; //FIFO 满中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） +} ADC_InitStructure; + +#define ADC_CH0 0x01 +#define ADC_CH1 0x02 +#define ADC_CH2 0x04 +#define ADC_CH3 0x08 +#define ADC_CH4 0x10 +#define ADC_CH5 0x20 +#define ADC_CH6 0x40 +#define ADC_CH7 0x80 + +#define ADC_CLKSRC_HRC 1 +#define ADC_CLKSRC_VCO_DIV16 2 +#define ADC_CLKSRC_VCO_DIV32 3 +#define ADC_CLKSRC_VCO_DIV64 4 + +#define ADC_AVG_SAMPLE1 0 +#define ADC_AVG_SAMPLE2 1 //一次启动连续采样、转换2次，并计算两次结果的平均值作为转换结果 +#define ADC_AVG_SAMPLE4 3 +#define ADC_AVG_SAMPLE8 7 +#define ADC_AVG_SAMPLE16 15 + +#define ADC_TRIGSRC_SW 0 //软件触发，即ADC->START.GO写1启动转换 +#define ADC_TRIGSRC_PWM 1 + +#define PGA_VCM_INTERNAL 1 //PGA输入共模电平由内部电路产生，ADC_REFP和ADC_REFN可悬空 +#define PGA_VCM_EXTERNAL 0 //PGA输入共模电平由外部引脚提供，(ADC_REFP + ADC_REFN) 电平值须与量程相同 + +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct); //ADC模数转换器初始化 +void ADC_Open(ADC_TypeDef *ADCx); //ADC开启，可以软件启动、或硬件触发ADC转换 +void ADC_Close(ADC_TypeDef *ADCx); //ADC关闭，无法软件启动、或硬件触发ADC转换 +void ADC_Start(ADC_TypeDef *ADCx); //启动指定ADC，开始模数转换 +void ADC_Stop(ADC_TypeDef *ADCx); //关闭指定ADC，停止模数转换 + +uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn); //从指定通道读取转换结果 +uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn); //指定通道是否End Of Conversion + +void ADC_ChnSelect(ADC_TypeDef *ADCx, uint32_t chns); + +void ADC_IntEOCEn(ADC_TypeDef *ADCx, uint32_t chn); //转换完成中断使能 +void ADC_IntEOCDis(ADC_TypeDef *ADCx, uint32_t chn); //转换完成中断禁止 +void ADC_IntEOCClr(ADC_TypeDef *ADCx, uint32_t chn); //转换完成中断标志清除 +uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn); //转换完成中断状态 + +void ADC_IntOVFEn(ADC_TypeDef *ADCx, uint32_t chn); //数据溢出中断使能 +void ADC_IntOVFDis(ADC_TypeDef *ADCx, uint32_t chn); //数据溢出中断禁止 +void ADC_IntOVFClr(ADC_TypeDef *ADCx, uint32_t chn); //数据溢出中断标志清除 +uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn); //数据溢出中断状态 + +void ADC_IntHFULLEn(ADC_TypeDef *ADCx, uint32_t chn); //FIFO半满中断使能 +void ADC_IntHFULLDis(ADC_TypeDef *ADCx, uint32_t chn); //FIFO半满中断禁止 +void ADC_IntHFULLClr(ADC_TypeDef *ADCx, uint32_t chn); //FIFO半满中断标志清除 +uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn); //FIFO半满中断状态 + +void ADC_IntFULLEn(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断使能 +void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断禁止 +void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断标志清除 +uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断状态 + +/* ADC 内部 1.2V REFP电压输出到外部REFP引脚，用于测量，或在需要1.2V外部REFP时节省成本 */ +#define ADC_TEST_INNER_REFP_OUT_EN(ADCx) (ADCx->CTRL3 |= (1 << ADC_CTRL3_REFP_OUT_Pos)) +#define ADC_TEST_INNER_REFP_OUT_DIS(ADCx) (ADCx->CTRL3 &= ~(1 << ADC_CTRL3_REFP_OUT_Pos)) + +#define ADC_TEST_ADC_PGA_EXT_VCM_EN(ADCx) (ADCx->CTRL3 |= (1 << ADC_CTRL3_EXTVCM_Pos)) +#define ADC_TEST_ADC_PGA_EXT_VCM_DIS(ADCx) (ADCx->CTRL3 &= ~(1 << ADC_CTRL3_EXTVCM_Pos)) + +#endif //__SWM320_ADC_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c new file mode 100644 index 00000000000..2f9a345b21c --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c @@ -0,0 +1,687 @@ +/****************************************************************************************************************************************** +* 文件名称: SWM320_can.c +* 功能说明: SWM320单片机的CAN模块驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_can.h" + +/****************************************************************************************************************************************** +* 函数名称: CAN_Init() +* 功能说明: CAN接口初始化 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* CAN_InitStructure * initStruct 包含CAN接口相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct) +{ + switch ((uint32_t)CANx) + { + case ((uint32_t)CAN): + SYS->CLKEN |= (0x01 << SYS_CLKEN_CAN_Pos); + break; + } + + CAN_Close(CANx); //一些关键寄存器只能在CAN关闭时设置 + + CANx->CR &= ~(CAN_CR_LOM_Msk | CAN_CR_STM_Msk | CAN_CR_AFM_Msk); + CANx->CR |= (initStruct->Mode << CAN_CR_LOM_Pos) | + (initStruct->FilterMode << CAN_CR_AFM_Pos); + + CANx->FILTER.AMR[3] = initStruct->FilterMask32b & 0xFF; + CANx->FILTER.AMR[2] = (initStruct->FilterMask32b >> 8) & 0xFF; + CANx->FILTER.AMR[1] = (initStruct->FilterMask32b >> 16) & 0xFF; + CANx->FILTER.AMR[0] = (initStruct->FilterMask32b >> 24) & 0xFF; + + CANx->FILTER.ACR[3] = initStruct->FilterCheck32b & 0xFF; + CANx->FILTER.ACR[2] = (initStruct->FilterCheck32b >> 8) & 0xFF; + CANx->FILTER.ACR[1] = (initStruct->FilterCheck32b >> 16) & 0xFF; + CANx->FILTER.ACR[0] = (initStruct->FilterCheck32b >> 24) & 0xFF; + + CANx->BT1 = (0 << CAN_BT1_SAM_Pos) | + (initStruct->CAN_BS1 << CAN_BT1_TSEG1_Pos) | + (initStruct->CAN_BS2 << CAN_BT1_TSEG2_Pos); + + CANx->BT0 = (initStruct->CAN_SJW << CAN_BT0_SJW_Pos) | + ((SystemCoreClock / 2 / initStruct->Baudrate / (1 + (initStruct->CAN_BS1 + 1) + (initStruct->CAN_BS2 + 1)) - 1) << CAN_BT0_BRP_Pos); + + CANx->RXERR = 0; //只能在复位模式下清除 + CANx->TXERR = 0; + + CANx->IE = (initStruct->RXNotEmptyIEn << CAN_IE_RXDA_Pos) | + (initStruct->RXOverflowIEn << CAN_IE_RXOV_Pos) | + (initStruct->ArbitrLostIEn << CAN_IE_ARBLOST_Pos) | + (initStruct->ErrPassiveIEn << CAN_IE_ERRPASS_Pos); + + switch ((uint32_t)CANx) + { + case ((uint32_t)CAN): + if (initStruct->RXNotEmptyIEn | initStruct->RXOverflowIEn | initStruct->ArbitrLostIEn | initStruct->ErrPassiveIEn) + { + NVIC_EnableIRQ(CAN_IRQn); + } + else + { + NVIC_DisableIRQ(CAN_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_Open() +* 功能说明: CAN接口打开 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_Open(CAN_TypeDef *CANx) +{ + CANx->CR &= ~(0x01 << CAN_CR_RST_Pos); //退出复位模式，进入工作模式 +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_Close() +* 功能说明: CAN接口关闭 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_Close(CAN_TypeDef *CANx) +{ + CANx->CR |= (0x01 << CAN_CR_RST_Pos); //进入复位模式，不能发送和接收数据 +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_Transmit() +* 功能说明: CAN发送数据 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* uint32_t format CAN_FRAME_STD 标准帧 CAN_FRAME_EXT 扩展帧 +* uint32_t id 消息ID +* uint8_t data[] 要发送的数据 +* uint32_t size 要发送的数据的个数 +* uint32_t once 只发送一次，即使发送失败（仲裁丢失、发送出错、NAK）也不尝试重发 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once) +{ + uint32_t i; + + if (format == CAN_FRAME_STD) + { + CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 3; + CANx->TXFRAME.DATA[1] = id << 5; + + for (i = 0; i < size; i++) + { + CANx->TXFRAME.DATA[i + 2] = data[i]; + } + } + else //if(format == CAN_FRAME_EXT) + { + CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 21; + CANx->TXFRAME.DATA[1] = id >> 13; + CANx->TXFRAME.DATA[2] = id >> 5; + CANx->TXFRAME.DATA[3] = id << 3; + + for (i = 0; i < size; i++) + { + CANx->TXFRAME.DATA[i + 4] = data[i]; + } + } + + if (CANx->CR & CAN_CR_STM_Msk) + { + CANx->CMD = (1 << CAN_CMD_SRR_Pos); + } + else + { + if (once == 0) + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos); + } + else + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos); + } + } +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_TransmitRequest() +* 功能说明: CAN发送远程请求，请求远程节点发送数据 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* uint32_t format CAN_FRAME_STD 标准帧 CAN_FRAME_EXT 扩展帧 +* uint32_t id 消息ID +* uint32_t once 只发送一次，即使发送失败（仲裁丢失、发送出错、NAK）也不尝试重发 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32_t once) +{ + if (format == CAN_FRAME_STD) + { + CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 3; + CANx->TXFRAME.DATA[1] = id << 5; + } + else //if(format == CAN_FRAME_EXT) + { + CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); + + CANx->TXFRAME.DATA[0] = id >> 21; + CANx->TXFRAME.DATA[1] = id >> 13; + CANx->TXFRAME.DATA[2] = id >> 5; + CANx->TXFRAME.DATA[3] = id << 3; + } + + if (once == 0) + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos); + } + else + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos); + } +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_Receive() +* 功能说明: CAN接收数据 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* CAN_RXMessage *msg 接收到的消息存储在此结构体变量中 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg) +{ + uint32_t i; + uint32_t format = (CANx->RXFRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos; + + msg->remote = (CANx->RXFRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos; + msg->size = (CANx->RXFRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos; + + if (format == CAN_FRAME_STD) + { + msg->id = (CANx->RXFRAME.DATA[0] << 3) | (CANx->RXFRAME.DATA[1] >> 5); + + for (i = 0; i < msg->size; i++) + { + msg->data[i] = CANx->RXFRAME.DATA[i + 2]; + } + } + else //if(format == CAN_FRAME_EXT) + { + msg->id = (CANx->RXFRAME.DATA[0] << 21) | (CANx->RXFRAME.DATA[1] << 13) | (CANx->RXFRAME.DATA[2] << 5) | (CANx->RXFRAME.DATA[3] >> 3); + + for (i = 0; i < msg->size; i++) + { + msg->data[i] = CANx->RXFRAME.DATA[i + 4]; + } + } + + CANx->CMD = (1 << CAN_CMD_RRB_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_TXComplete() +* 功能说明: 发送是否完成 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已经完成 0 还未完成 +* 注意事项: 发送被Abort也会触发发送完成，但不会触发发送成功 +******************************************************************************************************************************************/ +uint32_t CAN_TXComplete(CAN_TypeDef *CANx) +{ + return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_TXSuccess() +* 功能说明: 发送是否成功 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 发送成功 0 发送失败 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_TXSuccess(CAN_TypeDef *CANx) +{ + return (CANx->SR & CAN_SR_TXOK_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_AbortTransmit() +* 功能说明: 终止发送 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 正在进行的发送无法终止，但执行此命令后若发送失败不会再重发 +******************************************************************************************************************************************/ +void CAN_AbortTransmit(CAN_TypeDef *CANx) +{ + CANx->CMD = (1 << CAN_CMD_ABTTX_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_TXBufferReady() +* 功能说明: TX Buffer是否准备好可以写入消息 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已准备好 0 未准备好 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx) +{ + return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_RXDataAvailable() +* 功能说明: RX FIFO中是否有数据可读出 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 有数据可读出 0 没有数据 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx) +{ + return (CANx->SR & CAN_SR_RXDA_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_SetBaudrate() +* 功能说明: 设置波特率 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* uint32_t baudrate 波特率，即位传输速率 +* uint32_t CAN_BS1 CAN_BS1_1tq、CAN_BS1_2tq、... ... 、CAN_BS1_16tq +* uint32_t CAN_BS2 CAN_BS2_1tq、CAN_BS2_2tq、... ... 、CAN_BS2_8tq +* uint32_t CAN_SJW CAN_SJW_1tq、CAN_SJW_2tq、CAN_SJW_3tq、CAN_SJW_4tq +* 输 出: 无 +* 注意事项: 设置前需要先调用CAN_Close()关闭CAN模块 +******************************************************************************************************************************************/ +void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uint32_t CAN_BS2, uint32_t CAN_SJW) +{ + CANx->BT1 = (0 << CAN_BT1_SAM_Pos) | + (CAN_BS1 << CAN_BT1_TSEG1_Pos) | + (CAN_BS2 << CAN_BT1_TSEG2_Pos); + + CANx->BT0 = (CAN_SJW << CAN_BT0_SJW_Pos) | + ((SystemCoreClock / 2 / baudrate / (1 + (CAN_BS1 + 1) + (CAN_BS2 + 1)) - 1) << CAN_BT0_BRP_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_SetFilter32b() +* 功能说明: 设置接收滤波器，1个32位滤波器 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* uint32_t check 与mask一起决定了接收到的Message是否是自己需要的：check & (~mask) == ID & (~mask)的Message通过过滤 +* uint32_t mask +* 输 出: 无 +* 注意事项: 设置前需要先调用CAN_Close()关闭CAN模块 +******************************************************************************************************************************************/ +void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask) +{ + CANx->CR &= ~CAN_CR_AFM_Msk; + CANx->CR |= (CAN_FILTER_32b << CAN_CR_AFM_Pos); + + CANx->FILTER.AMR[0] = mask & 0xFF; + CANx->FILTER.AMR[1] = (mask >> 8) & 0xFF; + CANx->FILTER.AMR[2] = (mask >> 16) & 0xFF; + CANx->FILTER.AMR[3] = (mask >> 24) & 0xFF; + + CANx->FILTER.ACR[0] = check & 0xFF; + CANx->FILTER.ACR[1] = (check >> 8) & 0xFF; + CANx->FILTER.ACR[2] = (check >> 16) & 0xFF; + CANx->FILTER.ACR[3] = (check >> 24) & 0xFF; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_SetFilter16b() +* 功能说明: 设置接收滤波器，2个16位滤波器 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* uint16_t check1 与mask一起决定了接收到的Message是否是自己需要的：check & (~mask) == ID & (~mask)的Message通过过滤 +* uint16_t mask1 +* uint16_t check2 +* uint16_t mask2 +* 输 出: 无 +* 注意事项: 设置前需要先调用CAN_Close()关闭CAN模块 +******************************************************************************************************************************************/ +void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2) +{ + CANx->CR &= ~CAN_CR_AFM_Msk; + CANx->CR |= (CAN_FILTER_16b << CAN_CR_AFM_Pos); + + CANx->FILTER.AMR[0] = mask1 & 0xFF; + CANx->FILTER.AMR[1] = (mask1 >> 8) & 0xFF; + CANx->FILTER.AMR[2] = mask2 & 0xFF; + CANx->FILTER.AMR[3] = (mask2 >> 8) & 0xFF; + + CANx->FILTER.ACR[0] = check1 & 0xFF; + CANx->FILTER.ACR[1] = (check1 >> 8) & 0xFF; + CANx->FILTER.ACR[2] = check2 & 0xFF; + CANx->FILTER.ACR[3] = (check2 >> 8) & 0xFF; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTRXNotEmptyEn() +* 功能说明: 当RX FIFO中有数据时（非空）触发中断使能 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_RXDA_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTRXNotEmptyDis() +* 功能说明: 当RX FIFO中有数据时（非空）触发中断禁止 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_RXDA_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTRXNotEmptyStat() +* 功能说明: RX FIFO非空中断是否触发 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已触发 0 未触发 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_INTRXNotEmptyStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_RXDA_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTTXBufEmptyEn() +* 功能说明: 当TX Buffer空时触发中断使能 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_TXBR_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTTXBufEmptyDis() +* 功能说明: 当TX Buffer空时触发中断禁止 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_TXBR_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTTXBufEmptyStat() +* 功能说明: TX Buffer空中断是否触发 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已触发 0 未触发 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_INTTXBufEmptyStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTErrWarningEn() +* 功能说明: TXERR/RXERR计数值达到Error Warning Limit时触发中断使能 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTErrWarningEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_ERRWARN_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTErrWarningDis() +* 功能说明: TXERR/RXERR计数值达到Error Warning Limit时触发中断禁止 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTErrWarningDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_ERRWARN_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTErrWarningStat() +* 功能说明: TXERR/RXERR计数值达到Error Warning Limit中断是否触发 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已触发 0 未触发 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_INTErrWarningStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_ERRWARN_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTRXOverflowEn() +* 功能说明: RX FIFO 溢出时触发中断使能 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTRXOverflowEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_RXOV_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTRXOverflowDis() +* 功能说明: RX FIFO 溢出时触发中断禁止 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTRXOverflowDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_RXOV_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTRXOverflowStat() +* 功能说明: RX FIFO 溢出中断是否触发 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已触发 0 未触发 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_INTRXOverflowStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_RXOV_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTRXOverflowClear() +* 功能说明: RX FIFO 溢出中断清除 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTRXOverflowClear(CAN_TypeDef *CANx) +{ + CANx->CMD = (1 << CAN_CMD_CLROV_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTWakeupEn() +* 功能说明: 唤醒事件触发中断使能 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTWakeupEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_WKUP_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTWakeupDis() +* 功能说明: 唤醒事件触发中断禁止 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTWakeupDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_WKUP_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTWakeupStat() +* 功能说明: 唤醒事件中断是否触发 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已触发 0 未触发 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_INTWakeupStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_WKUP_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTErrPassiveEn() +* 功能说明: TXERR/RXERR计数值达到127时中断使能 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTErrPassiveEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_ERRPASS_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTErrPassiveDis() +* 功能说明: TXERR/RXERR计数值达到127时中断禁止 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTErrPassiveDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_ERRPASS_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTErrPassiveStat() +* 功能说明: TXERR/RXERR计数值达到127中断是否触发 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已触发 0 未触发 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_INTErrPassiveStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_ERRPASS_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTArbitrLostEn() +* 功能说明: 仲裁失败中断使能 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTArbitrLostEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_ARBLOST_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTArbitrLostDis() +* 功能说明: 仲裁失败中断禁止 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTArbitrLostDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_ARBLOST_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTArbitrLostStat() +* 功能说明: 仲裁失败中断是否触发 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已触发 0 未触发 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_INTArbitrLostStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_ARBLOST_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTBusErrorEn() +* 功能说明: 总线错误中断使能 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTBusErrorEn(CAN_TypeDef *CANx) +{ + CANx->IE |= (1 << CAN_IE_BUSERR_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTBusErrorDis() +* 功能说明: 总线错误中断禁止 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void CAN_INTBusErrorDis(CAN_TypeDef *CANx) +{ + CANx->IE &= ~(1 << CAN_IE_BUSERR_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: CAN_INTBusErrorStat() +* 功能说明: 总线错误中断是否触发 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已触发 0 未触发 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t CAN_INTBusErrorStat(CAN_TypeDef *CANx) +{ + return (CANx->IF & CAN_IF_BUSERR_Msk) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h new file mode 100644 index 00000000000..6a239c84b3c --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h @@ -0,0 +1,141 @@ +#ifndef __SWM320_CAN_H__ +#define __SWM320_CAN_H__ + +#define CAN_FRAME_STD 0 +#define CAN_FRAME_EXT 1 + +typedef struct +{ + uint8_t Mode; //CAN_MODE_NORMALCAN_MODE_LISTENCAN_MODE_SELFTEST + uint8_t CAN_BS1; //CAN_BS1_1tqCAN_BS1_2tq... ... CAN_BS1_16tq + uint8_t CAN_BS2; //CAN_BS2_1tqCAN_BS2_2tq... ... CAN_BS2_8tq + uint8_t CAN_SJW; //CAN_SJW_1tqCAN_SJW_2tqCAN_SJW_3tqCAN_SJW_4tq + uint32_t Baudrate; //ʣλʣȡֵ1--1000000 + uint8_t FilterMode; //CAN_FILTER_16bCAN_FILTER_32b + union + { + uint32_t FilterMask32b; //FilterCheck & (~FilterMask) == ID & (~FilterMask)Messageͨ + struct // 0 must match 1 don't care + { + uint16_t FilterMask16b1; + uint16_t FilterMask16b2; + }; + }; + union + { + uint32_t FilterCheck32b; + struct + { + uint16_t FilterCheck16b1; + uint16_t FilterCheck16b2; + }; + }; + uint8_t RXNotEmptyIEn; //FIFOǿգݿɶ + uint8_t RXOverflowIEn; //FIFOݶʧ + uint8_t ArbitrLostIEn; //ʧٲñɽշ + uint8_t ErrPassiveIEn; ///ʹֵﵽ127 +} CAN_InitStructure; + +#define CAN_MODE_NORMAL 0 //ģʽ +#define CAN_MODE_LISTEN 1 //ģʽ +#define CAN_MODE_SELFTEST 2 //Բģʽ + +#define CAN_BS1_1tq 0 +#define CAN_BS1_2tq 1 +#define CAN_BS1_3tq 2 +#define CAN_BS1_4tq 3 +#define CAN_BS1_5tq 4 +#define CAN_BS1_6tq 5 +#define CAN_BS1_7tq 6 +#define CAN_BS1_8tq 7 +#define CAN_BS1_9tq 8 +#define CAN_BS1_10tq 9 +#define CAN_BS1_11tq 10 +#define CAN_BS1_12tq 11 +#define CAN_BS1_13tq 12 +#define CAN_BS1_14tq 13 +#define CAN_BS1_15tq 14 +#define CAN_BS1_16tq 15 + +#define CAN_BS2_1tq 0 +#define CAN_BS2_2tq 1 +#define CAN_BS2_3tq 2 +#define CAN_BS2_4tq 3 +#define CAN_BS2_5tq 4 +#define CAN_BS2_6tq 5 +#define CAN_BS2_7tq 6 +#define CAN_BS2_8tq 7 + +#define CAN_SJW_1tq 0 +#define CAN_SJW_2tq 1 +#define CAN_SJW_3tq 2 +#define CAN_SJW_4tq 3 + +#define CAN_FILTER_16b 0 //16λ +#define CAN_FILTER_32b 1 //һ32λ + +typedef struct +{ + uint32_t id; //ϢID + uint8_t remote; //ϢǷΪԶ֡ + uint8_t data[8]; //յ + uint8_t size; //յݸ +} CAN_RXMessage; + + +void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct); +void CAN_Open(CAN_TypeDef *CANx); +void CAN_Close(CAN_TypeDef *CANx); + +void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once); +void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32_t once); +void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg); + +uint32_t CAN_TXComplete(CAN_TypeDef *CANx); +uint32_t CAN_TXSuccess(CAN_TypeDef *CANx); + +void CAN_AbortTransmit(CAN_TypeDef *CANx); + +uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx); +uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx); + +void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uint32_t CAN_BS2, uint32_t CAN_SJW); + +void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask); +void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2); + + +void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx); +void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx); +uint32_t CAN_INTRXNotEmptyStat(CAN_TypeDef *CANx); + +void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx); +void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx); +uint32_t CAN_INTTXBufEmptyStat(CAN_TypeDef *CANx); + +void CAN_INTErrWarningEn(CAN_TypeDef *CANx); +void CAN_INTErrWarningDis(CAN_TypeDef *CANx); +uint32_t CAN_INTErrWarningStat(CAN_TypeDef *CANx); + +void CAN_INTRXOverflowEn(CAN_TypeDef *CANx); +void CAN_INTRXOverflowDis(CAN_TypeDef *CANx); +uint32_t CAN_INTRXOverflowStat(CAN_TypeDef *CANx); +void CAN_INTRXOverflowClear(CAN_TypeDef *CANx); + +void CAN_INTWakeupEn(CAN_TypeDef *CANx); +void CAN_INTWakeupDis(CAN_TypeDef *CANx); +uint32_t CAN_INTWakeupStat(CAN_TypeDef *CANx); + +void CAN_INTErrPassiveEn(CAN_TypeDef *CANx); +void CAN_INTErrPassiveDis(CAN_TypeDef *CANx); +uint32_t CAN_INTErrPassiveStat(CAN_TypeDef *CANx); + +void CAN_INTArbitrLostEn(CAN_TypeDef *CANx); +void CAN_INTArbitrLostDis(CAN_TypeDef *CANx); +uint32_t CAN_INTArbitrLostStat(CAN_TypeDef *CANx); + +void CAN_INTBusErrorEn(CAN_TypeDef *CANx); +void CAN_INTBusErrorDis(CAN_TypeDef *CANx); +uint32_t CAN_INTBusErrorStat(CAN_TypeDef *CANx); + +#endif //__SWM320_CAN_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c new file mode 100644 index 00000000000..0258c90382e --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c @@ -0,0 +1,51 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_crc.c +* ˵: SWM320ƬCRCģ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_crc.h" + + +/****************************************************************************************************************************************** +* : CRC_Init() +* ˵: CRC ʼ +* : CRC_TypeDef * CRCx ָҪõCRCӿڣЧֵCRC +* uint32_t mode ģʽЧֵУCRC32_IN32CRC32_IN16CRC32_IN8CRC16_IN16CRC16_IN8 +* uint32_t out_not Ƿȡ +* uint32_t out_rev Ƿת +* uint32_t ini_val CRCʼֵ +* : +* ע: +******************************************************************************************************************************************/ +void CRC_Init(CRC_TypeDef *CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val) +{ + switch ((uint32_t)CRCx) + { + case ((uint32_t)CRC): + SYS->CLKEN |= (0x01 << SYS_CLKEN_CRC_Pos); + break; + } + + CRCx->CR = (1 << CRC_CR_EN_Pos) | + (mode << CRC_CR_CRC16_Pos) | + (out_not << CRC_CR_ONOT_Pos) | + (out_rev << CRC_CR_OREV_Pos); + + CRCx->INIVAL = ini_val; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h new file mode 100644 index 00000000000..947bf854556 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h @@ -0,0 +1,39 @@ +#ifndef __SWM320_CRC_H__ +#define __SWM320_CRC_H__ + + +#define CRC32_IN32 0 //CRC32㷨32λ +#define CRC32_IN16 2 //CRC32㷨16λ +#define CRC32_IN8 4 //CRC32㷨 8λ +#define CRC16_IN16 3 //CRC16㷨16λ +#define CRC16_IN8 5 //CRC16㷨 8λ + + +void CRC_Init(CRC_TypeDef *CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val); + + +/****************************************************************************************************************************************** +* : CRC_Write() +* ˵: CRCд +* : uint32_t data Ҫд +* : +* ע: +******************************************************************************************************************************************/ +static __INLINE void CRC_Write(uint32_t data) +{ + CRC->DATAIN = data; +} + +/****************************************************************************************************************************************** +* : CRC_Result() +* ˵: ȡCRC +* : +* : uint32_t CRC +* ע: +******************************************************************************************************************************************/ +static __INLINE uint32_t CRC_Result(void) +{ + return CRC->RESULT; +} + +#endif //__SWM320_CRC_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c new file mode 100644 index 00000000000..3abb4c4b3ac --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c @@ -0,0 +1,138 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_dma.c +* ˵: SWM320ƬDMA +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_dma.h" + +/****************************************************************************************************************************************** +* : DMA_CHM_Config() +* ˵: DMAͨãڴ洢䣨FlashRAM䣩 +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 +* uint32_t src_addr Դֶַ룬ַ2λ00 +* uint32_t src_addr_incr 0 ̶ַ 1 ַ +* uint32_t dst_addr Ŀĵֶַ룬ַ2λ00 +* uint32_t dst_addr_incr 0 ̶ַ 1 ַ +* uint32_t num_word Ҫ˵1024 +* uint32_t int_en жʹܣ1 ݰɺж 0 ݰɺ󲻲ж +* : +* ע: ΪԪֽ +******************************************************************************************************************************************/ +void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en) +{ + DMA->EN = 1; //ÿͨԼĿؿƣܿؿһֱ + + DMA_CH_Close(chn); //ǰȹرոͨ + + DMA->CH[chn].SRC = src_addr; + DMA->CH[chn].DST = dst_addr; + + DMA->CH[chn].CR = ((num_word * 4 - 1) << DMA_CR_LEN_Pos) | + (0 << DMA_CR_AUTORE_Pos); + + DMA->CH[chn].AM = (src_addr_incr << DMA_AM_SRCAM_Pos) | + (dst_addr_incr << DMA_AM_DSTAM_Pos) | + (0 << DMA_AM_BURST_Pos); + + DMA->IF = (1 << chn); //жϱ־ + DMA->IE |= (1 << chn); + if (int_en) DMA->IM &= ~(1 << chn); + else DMA->IM |= (1 << chn); + + if (int_en) + { + NVIC_EnableIRQ(DMA_IRQn); + } + else + { + //ܵNVIC_DisalbeIRQ(DMA_IRQn)ΪͨʹDMAж + } +} + +/****************************************************************************************************************************************** +* : DMA_CH_Open() +* ˵: DMAͨ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_Open(uint32_t chn) +{ + DMA->CH[chn].CR |= (1 << DMA_CR_TXEN_Pos); +} + +/****************************************************************************************************************************************** +* : DMA_CH_Close() +* ˵: DMAͨر +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_Close(uint32_t chn) +{ + DMA->CH[chn].CR &= ~(1 << DMA_CR_TXEN_Pos); +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTEn() +* ˵: DMAжʹܣݰɺ󴥷ж +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_INTEn(uint32_t chn) +{ + DMA->IM &= ~(1 << chn); +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTDis() +* ˵: DMAжϽֹݰɺ󲻴ж +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_INTDis(uint32_t chn) +{ + DMA->IM |= (1 << chn); +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTClr() +* ˵: DMAжϱ־ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_INTClr(uint32_t chn) +{ + DMA->IF = (1 << chn); +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTStat() +* ˵: DMAж״̬ѯ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 +* : uint32_t 1 ݰ 0 ݰδ +* ע: +******************************************************************************************************************************************/ +uint32_t DMA_CH_INTStat(uint32_t chn) +{ + return (DMA->IF & (1 << chn)) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h new file mode 100644 index 00000000000..fc4cd98ca8f --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h @@ -0,0 +1,20 @@ +#ifndef __SWM320_DMA_H__ +#define __SWM320_DMA_H__ + + +#define DMA_CH0 0 +#define DMA_CH1 1 +#define DMA_CH2 2 + + +void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en); //DMAͨãڴ洢䣨FlashRAM䣩 +void DMA_CH_Open(uint32_t chn); //DMAͨ +void DMA_CH_Close(uint32_t chn); //DMAͨر + +void DMA_CH_INTEn(uint32_t chn); //DMAжʹܣݰɺ󴥷ж +void DMA_CH_INTDis(uint32_t chn); //DMAжϽֹݰɺ󲻴ж +void DMA_CH_INTClr(uint32_t chn); //DMAжϱ־ +uint32_t DMA_CH_INTStat(uint32_t chn); //DMAж״̬ѯ1 ݰ 0 ݰδ + + +#endif //__SWM320_DMA_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c new file mode 100644 index 00000000000..0214767e6b4 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c @@ -0,0 +1,131 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_exti.c +* ˵: SWM320ƬⲿжϹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_exti.h" + +/****************************************************************************************************************************************** +* : EXTI_Init() +* ˵: ָⲿжϳʼ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t mode ЧֵEXTI_FALL_EDGEEXTI_RISE_EDGEEXTI_BOTH_EDGEEXTI_LOW_LEVELEXTI_HIGH_LEVEL +* : +* ע: GPIOAGPIOBGPIOCGPIOMPIN0--7żԽNVICежϣGPIOA0_IRQnҲԽNVICжϣGPIOA_IRQn +* Բڴ˺еNVIC_EnableIRQ()ʹNVICжϣӶԸҪNVIC_EnableIRQ(GPIOA0_IRQn)NVIC_EnableIRQ(GPIOA_IRQn) +******************************************************************************************************************************************/ +void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode) +{ + EXTI_Close(GPIOx, n); //ùؼĴǰȹر + + if (mode & 0x10) + { + GPIOx->INTLVLTRG |= (0x01 << n); //ƽ + + if (mode & 0x01) + GPIOx->INTRISEEN |= (0x01 << n); //ߵƽ + else + GPIOx->INTRISEEN &= ~(0x01 << n); //͵ƽ + } + else + { + GPIOx->INTLVLTRG &= ~(0x01 << n); //ش + + if (mode & 0x02) + { + GPIOx->INTBE |= (0x01 << n); //˫ش + } + else + { + GPIOx->INTBE &= ~(0x01 << n); //ش + + if (mode & 0x01) + GPIOx->INTRISEEN |= (0x01 << n); //ش + else + GPIOx->INTRISEEN &= ~(0x01 << n); //½ش + } + } + + GPIOx->INTCLR = (1 << n); //Ϊģʽÿܲж +} + +/****************************************************************************************************************************************** +* : EXTI_Open() +* ˵: ָⲿжϴ򿪣ʹܣ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: +******************************************************************************************************************************************/ +void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->INTEN |= (0x01 << n); +} + +/****************************************************************************************************************************************** +* : EXTI_Close() +* ˵: ָⲿжϹرգܣ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: +******************************************************************************************************************************************/ +void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->INTEN &= ~(0x01 << n); +} + +/****************************************************************************************************************************************** +* : EXTI_State() +* ˵: ָǷ񴥷ж +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : uint32_t 1 Ŵж 0 δж +* ע: +******************************************************************************************************************************************/ +uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n) +{ + return (GPIOx->INTSTAT >> n) & 0x01; +} + +/****************************************************************************************************************************************** +* : EXTI_RawState() +* ˵: ָǷ/жϴжϹرʱͨô˺ԲѯķʽǷ/жϴ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : uint32_t 1 /жϴ 0 δ/жϴ +* ע: +******************************************************************************************************************************************/ +uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n) +{ + return (GPIOx->INTRAWSTAT >> 1) & 0x01; +} + +/****************************************************************************************************************************************** +* : EXTI_Clear() +* ˵: ָⲿжжϱ־ٴνжϣ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: ֻشжϵı־ƽжϵı־޷ֻŵƽжϴӲԶ +******************************************************************************************************************************************/ +void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->INTCLR = (0x01 << n); +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h new file mode 100644 index 00000000000..f645fa69f85 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h @@ -0,0 +1,20 @@ +#ifndef __SWM320_EXTI_H__ +#define __SWM320_EXTI_H__ + +void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode); //ָⲿжϳʼ +void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n); //ָⲿжϴ򿪣ʹܣ +void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n); //ָⲿжϹرգܣ + +uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n); //ָǷ񴥷ж +uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n); //ָǷ/жϴжϹرʱͨô˺ԲѯķʽǷ/жϴ +void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n); //ָⲿжжϱ־ٴνжϣ + + +#define EXTI_FALL_EDGE 0x00 //½شж +#define EXTI_RISE_EDGE 0x01 //شж +#define EXTI_BOTH_EDGE 0x02 //˫شж +#define EXTI_LOW_LEVEL 0x10 //͵ƽж +#define EXTI_HIGH_LEVEL 0x11 //ߵƽж + + +#endif //__SWM320_EXTI_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c new file mode 100644 index 00000000000..fa619e566cc --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c @@ -0,0 +1,95 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_flash.c +* ˵: ʹоƬIAPܽƬFlashģEEPROMݣ󲻶ʧ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_flash.h" + + +__attribute__((section("PlaceInRAM"))) +static void switchTo80M(void) +{ + uint32_t i; + + for (i = 0; i < 50; i++) __NOP(); + + FLASH->CFG0 = 0x4bf; + FLASH->CFG1 = 0xabfc7a6e; + + for (i = 0; i < 50; i++) __NOP(); +} + +/****************************************************************************************************************************************** +* : FLASH_Erase() +* ˵: ƬFlash +* : uint32_t addr ַ +* : +* ע: +******************************************************************************************************************************************/ +void FLASH_Erase(uint32_t addr) +{ +// switchTo80M(); + + FLASH->ERASE = addr | ((uint32_t)1 << FLASH_ERASE_REQ_Pos); + while ((FLASH->STAT & FLASH_STAT_ERASE_GOING_Msk) == 0); + while ((FLASH->STAT & FLASH_STAT_ERASE_GOING_Msk) == 1); + + FLASH->ERASE = 0; + +// switchTo40M(); +} + +/****************************************************************************************************************************************** +* : FLASH_Write() +* ˵: ƬFlashд +* : uint32_t addr дַ +* uint32_t buff[] Ҫд +* uint32_t size ҪдݵĸΪλ +* : +* ע: +******************************************************************************************************************************************/ +void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t size) +{ + uint32_t i, j; + + switchTo80M(); + + FLASH->CACHE |= (1 << FLASH_CACHE_PROG_Pos); + + for (i = 0; i < size / 4; i++) + { + FLASH->ADDR = addr + i * 4 * 4; + + for (j = 0; j < 4; j++) + FLASH->DATA = buff[i * 4 + j]; + while ((FLASH->STAT & FLASH_STAT_FIFO_EMPTY_Msk) == 0) __NOP(); + } + if ((size % 4) != 0) + { + FLASH->ADDR = addr + i * 4 * 4; + + for (j = 0; j < size % 4; j++) + FLASH->DATA = buff[i * 4 + j]; + while ((FLASH->STAT & FLASH_STAT_FIFO_EMPTY_Msk) == 0) __NOP(); + } + while (FLASH->STAT & FLASH_STAT_PROG_GOING_Msk); + + FLASH->CACHE |= (1 << FLASH_CACHE_CLEAR_Pos); + FLASH->CACHE = 0; + +// switchTo40M(); +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h new file mode 100644 index 00000000000..5a4bfbb89f1 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h @@ -0,0 +1,9 @@ +#ifndef __SWM320_FLASH_H__ +#define __SWM320_FLASH_H__ + + +void FLASH_Erase(uint32_t addr); +void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t size); + + +#endif //__SWM320_FLASH_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c new file mode 100644 index 00000000000..dd81e75952d --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c @@ -0,0 +1,279 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_gpio.c +* ˵: SWM320Ƭͨ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_gpio.h" + + +/****************************************************************************************************************************************** +* : GPIO_Init() +* ˵: ųʼŷ衢衢© +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t dir ŷ0 1 +* uint32_t pull_up 裬0 ر 1 +* uint32_t pull_down 裬0 ر 1 +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down) +{ + switch ((uint32_t)GPIOx) + { + case ((uint32_t)GPIOA): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOA_Pos); + + PORT_Init(PORTA, n, 0, 1); //PORTA.PINnΪGPIOܣ뿪 + if (dir == 1) + { + GPIOA->DIR |= (0x01 << n); + } + else + { + GPIOA->DIR &= ~(0x01 << n); + } + + if (pull_up == 1) + PORT->PORTA_PULLU |= (0x01 << n); + else + PORT->PORTA_PULLU &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOB): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOB_Pos); + + PORT_Init(PORTB, n, 0, 1); //PORTB.PINnΪGPIOܣ뿪 + if (dir == 1) + { + GPIOB->DIR |= (0x01 << n); + } + else + { + GPIOB->DIR &= ~(0x01 << n); + } + + if (pull_down == 1) + PORT->PORTB_PULLD |= (0x01 << n); + else + PORT->PORTB_PULLD &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOC): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOC_Pos); + + PORT_Init(PORTC, n, 0, 1); //PORTC.PINnΪGPIOܣ뿪 + if (dir == 1) + { + GPIOC->DIR |= (0x01 << n); + } + else + { + GPIOC->DIR &= ~(0x01 << n); + } + + if (pull_up == 1) + PORT->PORTC_PULLU |= (0x01 << n); + else + PORT->PORTC_PULLU &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOM): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOM_Pos); + + PORT_Init(PORTM, n, 0, 1); //PORTM.PINnΪGPIOܣ뿪 + if (dir == 1) + { + GPIOM->DIR |= (0x01 << n); + } + else + { + GPIOM->DIR &= ~(0x01 << n); + } + + if (pull_up == 1) + PORT->PORTM_PULLU |= (0x01 << n); + else + PORT->PORTM_PULLU &= ~(0x01 << n); + break; + + case ((uint32_t)GPION): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPION_Pos); + + PORT_Init(PORTN, n, 0, 1); //PORTN.PINnΪGPIOܣ뿪 + if (dir == 1) + { + GPION->DIR |= (0x01 << n); + } + else + { + GPION->DIR &= ~(0x01 << n); + } + + if (pull_down == 1) + PORT->PORTN_PULLD |= (0x01 << n); + else + PORT->PORTN_PULLD &= ~(0x01 << n); + break; + + case ((uint32_t)GPIOP): + SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOP_Pos); + + PORT_Init(PORTP, n, 0, 1); //PORTP.PINnΪGPIOܣ뿪 + if (dir == 1) + { + GPIOP->DIR |= (0x01 << n); + } + else + { + GPIOP->DIR &= ~(0x01 << n); + } + + if (pull_up == 1) + PORT->PORTP_PULLU |= (0x01 << n); + else + PORT->PORTP_PULLU &= ~(0x01 << n); + break; + } +} + +/****************************************************************************************************************************************** +* : GPIO_SetBit() +* ˵: ָŵƽø +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->DATA |= (0x01 << n); +} + +/****************************************************************************************************************************************** +* : GPIO_ClrBit() +* ˵: ָŵƽõ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->DATA &= ~(0x01 << n); +} + +/****************************************************************************************************************************************** +* : GPIO_InvBit() +* ˵: ָŵƽת +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + GPIOx->DATA ^= (0x01 << n); +} + +/****************************************************************************************************************************************** +* : GPIO_GetBit() +* ˵: ȡָŵĵƽ״̬ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* : ָŵĵƽ״̬ 0 ͵ƽ 1 ߵƽ +* ע: +******************************************************************************************************************************************/ +uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + return ((GPIOx->DATA >> n) & 0x01); +} + +/****************************************************************************************************************************************** +* : GPIO_SetBits() +* ˵: ָĴnʼwλŵĵƽø +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t w ָҪŵƽøߵŵĸ +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + GPIOx->DATA |= (bits << n); +} + +/****************************************************************************************************************************************** +* : GPIO_ClrBits() +* ˵: ָĴnʼwλŵĵƽõ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t w ָҪŵƽõ͵ŵĸ +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + GPIOx->DATA &= ~(bits << n); +} + +/****************************************************************************************************************************************** +* : GPIO_InvBits() +* ˵: ָĴnʼwλŵĵƽת +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t w ָҪŵƽתŵĸ +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + GPIOx->DATA ^= (bits << n); +} + +/****************************************************************************************************************************************** +* : GPIO_GetBits() +* ˵: ȡָĴnʼwλŵĵƽ״̬ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t w ָҪŵƽøߵŵĸ +* : ָĴnʼwλŵĵƽ״̬ 0 ͵ƽ 1 ߵƽ +* ֵĵ0λʾnĵƽ״ֵ̬ĵ1λʾn+1ĵƽ״̬... ...ֵĵwλʾn+wĵƽ״̬ +* ע: +******************************************************************************************************************************************/ +uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + return ((GPIOx->DATA >> n) & bits); +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h new file mode 100644 index 00000000000..a0f84999bd1 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h @@ -0,0 +1,17 @@ +#ifndef __SWM320_GPIO_H__ +#define __SWM320_GPIO_H__ + + +void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down); //ųʼŷ衢 + +void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n); //ָŵƽø +void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n); //ָŵƽõ +void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n); //ָŵƽת +uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n); //ȡָŵĵƽ״̬ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽø +void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽõ +void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽת +uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //ȡָĴnʼwλŵĵƽ״̬ + + +#endif //__SWM320_GPIO_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c new file mode 100644 index 00000000000..34de5c5610c --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c @@ -0,0 +1,150 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_i2c.c +* ˵: SWM320ƬI2Cнӿڹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIES AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIEE. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIES ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_i2c.h" + +/****************************************************************************************************************************************** +* : I2C_Init() +* ˵: I2Cʼ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* I2C_InitStructure * initStruct I2C趨ֵĽṹ +* : +* ע: ģֻܹģʽ +******************************************************************************************************************************************/ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) +{ + switch ((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_I2C0_Pos); + break; + + case ((uint32_t)I2C1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_I2C1_Pos); + break; + } + + I2C_Close(I2Cx); //һЩؼĴֻI2Cرʱ + + if (initStruct->Master == 1) + { + I2Cx->CLKDIV = SystemCoreClock / 5 / initStruct->MstClk; + + I2Cx->MSTCMD = (I2Cx->MSTCMD & (~I2C_MSTCMD_IF_Msk)) | (1 << I2C_MSTCMD_IF_Pos); //ʹж֮ǰжϱ־ + I2Cx->CTRL &= ~I2C_CTRL_MSTIE_Msk; + I2Cx->CTRL |= (initStruct->MstIEn << I2C_CTRL_MSTIE_Pos); + + switch ((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + if (initStruct->MstIEn) + { + NVIC_EnableIRQ(I2C0_IRQn); + } + else + { + NVIC_DisableIRQ(I2C0_IRQn); + } + break; + + case ((uint32_t)I2C1): + if (initStruct->MstIEn) + { + NVIC_EnableIRQ(I2C1_IRQn); + } + else + { + NVIC_DisableIRQ(I2C1_IRQn); + } + break; + } + } + else + { + I2Cx->SLVCR |= (1 << I2C_SLVCR_SLAVE_Pos); + + I2Cx->SLVCR &= ~(I2C_SLVCR_ADDR7b_Msk | I2C_SLVCR_ADDR_Msk); + I2Cx->SLVCR |= (1 << I2C_SLVCR_ACK_Pos) | + (initStruct->Addr7b << I2C_SLVCR_ADDR7b_Pos) | + (initStruct->SlvAddr << I2C_SLVCR_ADDR_Pos); + + I2Cx->SLVIF = I2C_SLVIF_RXEND_Msk | I2C_SLVIF_TXEND_Msk | I2C_SLVIF_STADET_Msk | I2C_SLVIF_STODET_Msk; //жϱ־ + I2Cx->SLVCR &= ~(I2C_SLVCR_IM_RXEND_Msk | I2C_SLVCR_IM_TXEND_Msk | I2C_SLVCR_IM_STADET_Msk | I2C_SLVCR_IM_STODET_Msk | + I2C_SLVCR_IM_RDREQ_Msk | I2C_SLVCR_IM_WRREQ_Msk); + I2Cx->SLVCR |= ((initStruct->SlvRxEndIEn ? 0 : 1) << I2C_SLVCR_IM_RXEND_Pos) | + ((initStruct->SlvTxEndIEn ? 0 : 1) << I2C_SLVCR_IM_TXEND_Pos) | + ((initStruct->SlvSTADetIEn ? 0 : 1) << I2C_SLVCR_IM_STADET_Pos) | + ((initStruct->SlvSTODetIEn ? 0 : 1) << I2C_SLVCR_IM_STODET_Pos) | + ((initStruct->SlvRdReqIEn ? 0 : 1) << I2C_SLVCR_IM_RDREQ_Pos) | + ((initStruct->SlvWrReqIEn ? 0 : 1) << I2C_SLVCR_IM_WRREQ_Pos); + + switch ((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + if (initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn | + initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) + { + NVIC_EnableIRQ(I2C0_IRQn); + } + else + { + NVIC_DisableIRQ(I2C0_IRQn); + } + break; + + case ((uint32_t)I2C1): + if (initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn | + initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) + { + NVIC_EnableIRQ(I2C1_IRQn); + } + else + { + NVIC_DisableIRQ(I2C1_IRQn); + } + break; + } + } +} + +/****************************************************************************************************************************************** +* : I2C_Open() +* ˵: I2C򿪣շ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* : +* ע: +******************************************************************************************************************************************/ +void I2C_Open(I2C_TypeDef *I2Cx) +{ + I2Cx->CTRL |= (0x01 << I2C_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : I2C_Close() +* ˵: I2Cرգֹշ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* : +* ע: +******************************************************************************************************************************************/ +void I2C_Close(I2C_TypeDef *I2Cx) +{ + I2Cx->CTRL &= ~I2C_CTRL_EN_Msk; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h new file mode 100644 index 00000000000..769f5a2b557 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h @@ -0,0 +1,27 @@ +#ifndef __SWM320_I2C_H__ +#define __SWM320_I2C_H__ + +typedef struct +{ + uint8_t Master; //1 ģʽ + uint8_t Addr7b; //1 7λַ 0 10λַ + + uint32_t MstClk; //ʱƵ + uint8_t MstIEn; //ģʽжʹ + + uint16_t SlvAddr; //ӻַ + uint8_t SlvRxEndIEn; //ӻжʹ + uint8_t SlvTxEndIEn; //ӻжʹ + uint8_t SlvSTADetIEn; //ӻ⵽ʼжʹ + uint8_t SlvSTODetIEn; //ӻ⵽ֹжʹ + uint8_t SlvRdReqIEn; //ӻյжʹ + uint8_t SlvWrReqIEn; //ӻյджʹ +} I2C_InitStructure; + + +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct); + +void I2C_Open(I2C_TypeDef *I2Cx); +void I2C_Close(I2C_TypeDef *I2Cx); + +#endif //__SWM320_I2C_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c new file mode 100644 index 00000000000..742c5b35dde --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c @@ -0,0 +1,259 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_lcd.c +* ˵: SWM320ƬLCD +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_lcd.h" + +#include + +/****************************************************************************************************************************************** +* : LCD_Init() +* ˵: LCDʼ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* LCD_InitStructure * initStruct LCD趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct) +{ + switch ((uint32_t)LCDx) + { + case ((uint32_t)LCD): + SYS->CLKEN |= (0x01 << SYS_CLKEN_LCD_Pos); + break; + } + + if (initStruct->Interface == LCD_INTERFACE_RGB) + { + LCDx->START = (0 << LCD_START_MPUEN_Pos); + + if (initStruct->Dir == LCD_DIR_LANDSCAPE) + { + LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_HPIX_Pos) | + ((initStruct->VnPixel - 1) << LCD_CR0_VPIX_Pos) | + (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | + (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); + + LCDx->CR1 = (initStruct->Dir << LCD_CR1_DIRV_Pos) | + ((initStruct->Hfp - 1) << LCD_CR1_HFP_Pos) | + ((initStruct->Hbp - 1) << LCD_CR1_HBP_Pos) | + ((initStruct->Vfp - 1) << LCD_CR1_VFP_Pos) | + ((initStruct->Vbp - 1) << LCD_CR1_VBP_Pos) | + (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | + (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); + } + else + { + LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_VPIX_Pos) | + ((initStruct->VnPixel - 1) << LCD_CR0_HPIX_Pos) | + (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | + (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); + + LCDx->CR1 = (initStruct->Dir << LCD_CR1_DIRV_Pos) | + ((initStruct->Hfp - 1) << LCD_CR1_VFP_Pos) | + ((initStruct->Hbp - 1) << LCD_CR1_VBP_Pos) | + ((initStruct->Vfp - 1) << LCD_CR1_HFP_Pos) | + ((initStruct->Vbp - 1) << LCD_CR1_HBP_Pos) | + (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | + (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); + } + } + else if (initStruct->Interface == LCD_INTERFACE_I80) + { + LCDx->START = (1 << LCD_START_MPUEN_Pos); + + LCDx->CR1 = (1 << LCD_CR1_I80_Pos) | + (initStruct->T_CSf_WRf << LCD_CR1_TAS_Pos) | + (initStruct->T_WRnHold << LCD_CR1_TPWLW_Pos) | + (initStruct->T_WRr_CSr << LCD_CR1_TAH_Pos) | + (initStruct->T_CSr_CSf << LCD_CR1_TTAIL_Pos); + } + + LCDx->IE = 1; + LCDx->IF = 1; //־ + if (initStruct->IntEOTEn) LCD_INTEn(LCDx); + else LCD_INTDis(LCDx); + + switch ((uint32_t)LCDx) + { + case ((uint32_t)LCD): + if (initStruct->IntEOTEn) + { + NVIC_EnableIRQ(LCD_IRQn); + } + else + { + NVIC_DisableIRQ(LCD_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : LCD_Start() +* ˵: һݴ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : +* ע: +******************************************************************************************************************************************/ +void LCD_Start(LCD_TypeDef *LCDx) +{ + LCDx->START |= (1 << LCD_START_GO_Pos); +} + +/****************************************************************************************************************************************** +* : LCD_IsBusy() +* ˵: Ƿڽݴ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : uint32_t 1 ڴ 0 ݴ +* ע: +******************************************************************************************************************************************/ +uint32_t LCD_IsBusy(LCD_TypeDef *LCDx) +{ + return (LCDx->START & LCD_START_GO_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : LCD_I80_WriteReg() +* ˵: MPUӿʱдĴ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* uint16_t reg ҪдļĴʵַַ +* uint16_t val[] ĴֵַԶ +* uint16_t cnt ҪдļĴ +* : +* ע: +******************************************************************************************************************************************/ +void LCD_I80_WriteReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val[], uint16_t cnt) +{ + LCD->SRCADDR = (uint32_t)val; + LCD->CR0 &= ~LCD_CR0_DLEN_Msk; + LCD->CR0 |= ((cnt - 1) << LCD_CR0_DLEN_Pos); + + LCD->CR1 |= (1 << LCD_CR1_CMD_Pos); + LCD->CR1 &= ~LCD_CR1_REG_Msk; + LCD->CR1 |= (reg << LCD_CR1_REG_Pos); + + LCD_Start(LCDx); + while (LCD_IsBusy(LCDx)); +} + +/****************************************************************************************************************************************** +* : LCD_I80_WriteOneReg() +* ˵: MPUӿʱдĴ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* uint16_t reg ҪдļĴʵַ +* uint16_t val Ĵֵ +* : +* ע: +******************************************************************************************************************************************/ +void LCD_I80_WriteOneReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val) +{ + uint16_t buf[1] __attribute__((aligned(4))); + + buf[0] = val; + + LCD_I80_WriteReg(LCDx, reg, buf, 1); +} + +/****************************************************************************************************************************************** +* : LCD_I80_WriteData() +* ˵: MPUӿʱд +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* uint16_t val[] ҪдݣַԶ +* uint16_t cnt Ҫдݸ +* : +* ע: +******************************************************************************************************************************************/ +void LCD_I80_WriteData(LCD_TypeDef *LCDx, uint16_t val[], uint16_t cnt) +{ + LCD->SRCADDR = (uint32_t)val; + LCD->CR0 &= ~LCD_CR0_DLEN_Msk; + LCD->CR0 |= ((cnt - 1) << LCD_CR0_DLEN_Pos); + + LCD->CR1 &= ~(1 << LCD_CR1_CMD_Pos); + + LCD_Start(LCDx); + while (LCD_IsBusy(LCDx)); +} + +/****************************************************************************************************************************************** +* : LCD_I80_WriteOneData() +* ˵: MPUӿʱд +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* uint16_t val Ҫд +* : +* ע: +******************************************************************************************************************************************/ +void LCD_I80_WriteOneData(LCD_TypeDef *LCDx, uint16_t val) +{ + uint16_t buf[1] __attribute__((aligned(4))); + + buf[0] = val; + + LCD_I80_WriteData(LCDx, buf, 2); +} + +/****************************************************************************************************************************************** +* : LCD_INTEn() +* ˵: LCDжʹܣָȵݴʱж +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : +* ע: +******************************************************************************************************************************************/ +void LCD_INTEn(LCD_TypeDef *LCDx) +{ + LCDx->IM = 0; +} + +/****************************************************************************************************************************************** +* : LCD_INTDis() +* ˵: LCDжϽָֹȵݴʱж +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : +* ע: +******************************************************************************************************************************************/ +void LCD_INTDis(LCD_TypeDef *LCDx) +{ + LCDx->IM = 1; +} + +/****************************************************************************************************************************************** +* : LCD_INTClr() +* ˵: LCDжϱ־ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : +* ע: +******************************************************************************************************************************************/ +void LCD_INTClr(LCD_TypeDef *LCDx) +{ + LCDx->IF = 1; +} + +/****************************************************************************************************************************************** +* : LCD_INTStat() +* ˵: LCDж״̬ѯ +* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD +* : uint32_t 1 ָȵݴ 0 δָȵݴ +* ע: +******************************************************************************************************************************************/ +uint32_t LCD_INTStat(LCD_TypeDef *LCDx) +{ + return (LCDx->IF & 0x01) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h new file mode 100644 index 00000000000..0b9d9b53c36 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h @@ -0,0 +1,96 @@ +#ifndef __SWM320_LCD_H__ +#define __SWM320_LCD_H__ + + +typedef struct +{ + uint8_t Interface; //LCDӿڣLCD_INTERFACE_RGBLCD_INTERFACE_I80LCD_INTERFACE_M68 + + /* RGBͬӿڲ */ + uint8_t Dir; //LCD_DIR_LANDSCAPE LCD_DIR_PORTRAIT + uint16_t HnPixel; //ˮƽظȡֵ1024 + uint16_t VnPixel; //ֱظȡֵ 768 + uint8_t Hfp; //horizonal front porchȡֵ32 + uint8_t Hbp; //horizonal back porch ȡֵ128 + uint8_t Vfp; //vertical front porch ȡֵ8 + uint8_t Vbp; //vertical back porch ȡֵ32 + uint8_t ClkDiv; //ϵͳʱӾClkDivƵDOCCLK0 2Ƶ 1 4Ƶ 2 6Ƶ ... ... 31 64Ƶ + uint8_t SamplEdge; //ĻDOTCLKĸزݣLCD_SAMPLEDGE_RISELCD_SAMPLEDGE_FALL + uint8_t ClkAlways; //1 һֱDOTCLK 0 ֻڴʱDOTCLK + uint8_t HsyncWidth; //HSYNC͵ƽٸDOTCLKȡֵLCD_HSYNC_1DOTCLKLCD_HSYNC_2DOTCLKLCD_HSYNC_3DOTCLKLCD_HSYNC_4DOTCLK + + /* MPU8080ӿڲ */ + uint8_t T_CSf_WRf; //CSn½صWRn½صʱ䣬ȡֵ0--3 + uint8_t T_WRnHold; //WRn͵ƽijʱ䣬 ȡֵ0--7 + uint8_t T_WRr_CSr; //WRnصCSnصʱ䣬ȡֵ0--3 + uint8_t T_CSr_CSf; //CSnصCSn½صʱ䣬ȡֵ0--7 + + uint8_t IntEOTEn; //End of Transterɣжʹ +} LCD_InitStructure; + + +#define LCD_INTERFACE_RGB 0 +#define LCD_INTERFACE_I80 1 +#define LCD_INTERFACE_M68 2 + +#define LCD_DIR_LANDSCAPE 0 // +#define LCD_DIR_PORTRAIT 1 // + +#define LCD_SAMPLEDGE_RISE 0 //ĻDOTCLKز +#define LCD_SAMPLEDGE_FALL 1 //ĻDOTCLK½ز + +#define LCD_HSYNC_1DOTCLK 0 //1DOTCLK +#define LCD_HSYNC_2DOTCLK 1 +#define LCD_HSYNC_3DOTCLK 2 +#define LCD_HSYNC_4DOTCLK 3 + +#define LCD_CLKDIV_2 0 +#define LCD_CLKDIV_4 1 +#define LCD_CLKDIV_6 2 +#define LCD_CLKDIV_8 3 +#define LCD_CLKDIV_10 4 +#define LCD_CLKDIV_12 5 +#define LCD_CLKDIV_14 6 +#define LCD_CLKDIV_16 7 +#define LCD_CLKDIV_18 8 +#define LCD_CLKDIV_20 9 +#define LCD_CLKDIV_22 10 +#define LCD_CLKDIV_24 11 +#define LCD_CLKDIV_26 12 +#define LCD_CLKDIV_28 13 +#define LCD_CLKDIV_30 14 +#define LCD_CLKDIV_32 15 +#define LCD_CLKDIV_34 16 +#define LCD_CLKDIV_36 17 +#define LCD_CLKDIV_38 18 +#define LCD_CLKDIV_40 19 +#define LCD_CLKDIV_42 20 +#define LCD_CLKDIV_44 21 +#define LCD_CLKDIV_46 22 +#define LCD_CLKDIV_48 23 +#define LCD_CLKDIV_50 24 +#define LCD_CLKDIV_52 25 +#define LCD_CLKDIV_54 26 +#define LCD_CLKDIV_56 27 +#define LCD_CLKDIV_58 28 +#define LCD_CLKDIV_60 29 +#define LCD_CLKDIV_62 30 +#define LCD_CLKDIV_64 31 + + +void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct); +void LCD_Start(LCD_TypeDef *LCDx); +uint32_t LCD_IsBusy(LCD_TypeDef *LCDx); + +void LCD_I80_WriteReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val[], uint16_t cnt); +void LCD_I80_WriteOneReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val); +void LCD_I80_WriteData(LCD_TypeDef *LCDx, uint16_t data[], uint16_t cnt); +void LCD_I80_WriteOneData(LCD_TypeDef *LCDx, uint16_t val); + +void LCD_INTEn(LCD_TypeDef *LCDx); +void LCD_INTDis(LCD_TypeDef *LCDx); +void LCD_INTClr(LCD_TypeDef *LCDx); +uint32_t LCD_INTStat(LCD_TypeDef *LCDx); + + +#endif //__SWM320_LCD_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c new file mode 100644 index 00000000000..0d183cee36c --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c @@ -0,0 +1,174 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_norflash.c +* ˵: SWM320ƬNOR Flash +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_norflash.h" + + +/****************************************************************************************************************************************** +* : NORFL_Init() +* ˵: NOR Flashʼ +* : NORFL_InitStructure * initStruct NOR Flash趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void NORFL_Init(NORFL_InitStructure *initStruct) +{ + uint32_t i; + + // SRAMǰҪˢSDRAM + do + { + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + while (SDRAMC->REFDONE == 0); + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); + + for (i = 0; i < 1000; i++) __NOP(); + SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); + } + while (0); + + SYS->CLKEN |= (1 << SYS_CLKEN_NORFL_Pos); + + NORFLC->CR = ((initStruct->DataWidth == 8 ? 1 : 0) << NORFLC_CR_BYTEIF_Pos) | + (initStruct->WELowPulseTime << NORFLC_CR_WRTIME_Pos) | + (initStruct->OEPreValidTime << NORFLC_CR_RDTIME_Pos); + + NORFLC->IE = 3; + NORFLC->IF = 3; // жϱ־ + if (initStruct->OperFinishIEn) NORFLC->IM &= ~(1 << NORFLC_IM_FINISH_Pos); + else NORFLC->IM |= (1 << NORFLC_IM_FINISH_Pos); + if (initStruct->OperTimeoutIEn) NORFLC->IM &= ~(1 << NORFLC_IM_TIMEOUT_Pos); + else NORFLC->IM |= (1 << NORFLC_IM_TIMEOUT_Pos); +} + +/****************************************************************************************************************************************** +* : NORFL_ChipErase() +* ˵: NOR FlashƬ +* : +* : uint32_t 0 ɹ 1 ʱ +* ע: +******************************************************************************************************************************************/ +uint32_t NORFL_ChipErase(void) +{ + uint32_t res; + + NORFLC->CMD = (NORFL_CMD_CHIP_ERASE << NORFLC_CMD_CMD_Pos); + + while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; + else res = 1; + + NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; + + return res; +} + +/****************************************************************************************************************************************** +* : NORFL_SectorErase() +* ˵: NOR Flash +* : uint32_t addr Ҫʼַ +* : uint32_t 0 ɹ 1 ʱ +* ע: MX29LV128DB ǰ8Ϊ8K255Ϊ64K MX29LV128DT ǰ255Ϊ64K8Ϊ8K +******************************************************************************************************************************************/ +uint32_t NORFL_SectorErase(uint32_t addr) +{ + uint32_t res; + + NORFLC->ADDR = addr; + NORFLC->CMD = (NORFL_CMD_SECTOR_ERASE << NORFLC_CMD_CMD_Pos); + + while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; + else res = 1; + + NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; + + return res; +} + +/****************************************************************************************************************************************** +* : NORFL_Write() +* ˵: NOR Flashд +* : uint32_t addr Ҫдĵַ +* uint32_t data Ҫд +* : uint32_t 0 дɹ 1 д볬ʱ +* ע: ӲӣΪ16λʱд룻Ϊ8λʱֽд +******************************************************************************************************************************************/ +uint32_t NORFL_Write(uint32_t addr, uint32_t data) +{ + uint32_t res; + + NORFLC->ADDR = addr; + NORFLC->CMD = (NORFL_CMD_PROGRAM << NORFLC_CMD_CMD_Pos) | (data << NORFLC_CMD_DATA_Pos); + + while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; + else res = 1; + + NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; + + return res; +} + +/****************************************************************************************************************************************** +* : NORFL_Read() +* ˵: NOR Flash +* : uint32_t addr Ҫĵַ +* : uint32_t +* ע: ӲӣΪ16λʱֶΪ8λʱֽڶ +******************************************************************************************************************************************/ +uint32_t NORFL_Read(uint32_t addr) +{ + NORFLC->ADDR = addr; + NORFLC->CMD = (NORFL_CMD_READ << NORFLC_CMD_CMD_Pos); + + return (NORFLC->CMD & NORFLC_CMD_DATA_Msk); +} + +/****************************************************************************************************************************************** +* : NORFL_ReadID() +* ˵: NOR FlashID +* : uint32_t id_addr IDַ˲оƬصģÿоƬͬ +* : uint16_t ȡID +* ע: +******************************************************************************************************************************************/ +uint16_t NORFL_ReadID(uint32_t id_addr) +{ + uint16_t id; + + NORFLC->CMD = (NORFL_CMD_AUTO_SELECT << NORFLC_CMD_CMD_Pos); + + NORFLC->ADDR = id_addr; + NORFLC->CMD = (NORFL_CMD_READ << NORFLC_CMD_CMD_Pos); + + id = NORFLC->CMD & NORFLC_CMD_DATA_Msk; + + NORFLC->CMD = (NORFL_CMD_RESET << NORFLC_CMD_CMD_Pos); // ˳IDȡģʽ + + return id; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h new file mode 100644 index 00000000000..fc859268fb2 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h @@ -0,0 +1,39 @@ +#ifndef __SWM320_NORFLASH_H__ +#define __SWM320_NORFLASH_H__ + +typedef struct +{ + uint8_t DataWidth; // 816 + + uint8_t WELowPulseTime; // WE# pulse widthλΪϵͳʱڣֵΪ7 + uint8_t OEPreValidTime; // Valid data output after OE# lowλΪϵͳʱڣֵΪ15 + + uint8_t OperFinishIEn; // (д롢)жʹ + uint8_t OperTimeoutIEn; +} NORFL_InitStructure; + + + +void NORFL_Init(NORFL_InitStructure *initStruct); +uint32_t NORFL_ChipErase(void); +uint32_t NORFL_SectorErase(uint32_t addr); +uint32_t NORFL_Write(uint32_t addr, uint32_t data); +uint32_t NORFL_Read(uint32_t addr); +uint16_t NORFL_ReadID(uint32_t id_addr); + + +/* ǰ汾߶ֶֻ֧ +#define NORFL_Read8(addr) *((volatile uint8_t *)(NORFLM_BASE + addr)) +#define NORFL_Read16(addr) *((volatile uint16_t *)(NORFLM_BASE + addr)) */ +#define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr)) + + + +#define NORFL_CMD_READ 0 +#define NORFL_CMD_RESET 1 +#define NORFL_CMD_AUTO_SELECT 2 +#define NORFL_CMD_PROGRAM 3 +#define NORFL_CMD_CHIP_ERASE 4 +#define NORFL_CMD_SECTOR_ERASE 5 + +#endif // __SWM320_NORFLASH_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c new file mode 100644 index 00000000000..bc7a555a301 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c @@ -0,0 +1,221 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_port.c +* ˵: SWM320ƬĶ˿Źѡ⺯ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_port.h" + + +/****************************************************************************************************************************************** +* : PORT_Init() +* ˵: ˿Źѡ񣬿õĹܼ"SWM320_port.h"ļ +* : uint32_t PORTx ָPORT˿ڣЧֵPORTAPORTBPORTCPORTMPORTNPORTP +* uint32_t n ָPORTţЧֵPIN0PIN1PIN2... ... PIN22PIN23 +* uint32_t func ָ˿Ҫ趨Ĺܣȡֵ"SWM320_port.h"ļ +* uint32_t digit_in_en ʹ +* : +* ע: űnΪżʱfuncȡֵֻFUNMUX0ͷģFUNMUX0_UART0_RXD +* űnΪʱfuncȡֵֻFUNMUX1ͷģFUNMUX1_UART0_TXD +******************************************************************************************************************************************/ +void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en) +{ + switch ((uint32_t)PORTx) + { + case ((uint32_t)PORTA): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTA_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTA_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTA_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTA_MUX1 |= (func - 100) << ((n - 6) * 5); + } + } + + PORT->PORTA_SEL &= ~(0x03 << (n * 2)); + PORT->PORTA_SEL |= (func > 99 ? 1 : func) << (n * 2); + + PORT->PORTA_INEN &= ~(0x01 << n); + PORT->PORTA_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTB): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTB_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTB_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTB_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTB_MUX1 |= (func - 100) << ((n - 6) * 5); + } + } + + PORT->PORTB_SEL &= ~(0x03 << (n * 2)); + PORT->PORTB_SEL |= (func > 99 ? 1 : func) << (n * 2); + + PORT->PORTB_INEN &= ~(0x01 << n); + PORT->PORTB_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTC): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTC_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTC_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTC_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTC_MUX1 |= (func - 100) << ((n - 6) * 5); + } + } + + PORT->PORTC_SEL &= ~(0x03 << (n * 2)); + PORT->PORTC_SEL |= (func > 99 ? 1 : func) << (n * 2); + + PORT->PORTC_INEN &= ~(0x01 << n); + PORT->PORTC_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTM): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTM_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTM_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTM_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTM_MUX1 |= (func - 100) << ((n - 6) * 5); + } + else if (n < PIN18) + { + PORT->PORTM_MUX2 &= ~(0x1F << ((n - 12) * 5)); + PORT->PORTM_MUX2 |= (func - 100) << ((n - 12) * 5); + } + else if (n < PIN24) + { + PORT->PORTM_MUX3 &= ~(0x1F << ((n - 18) * 5)); + PORT->PORTM_MUX3 |= (func - 100) << ((n - 18) * 5); + } + } + + if (n < 16) + { + PORT->PORTM_SEL0 &= ~(0x03 << (n * 2)); + PORT->PORTM_SEL0 |= (func > 99 ? 1 : func) << (n * 2); + } + else + { + PORT->PORTM_SEL1 &= ~(0x03 << ((n - 16) * 2)); + PORT->PORTM_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2); + } + + PORT->PORTM_INEN &= ~(0x01 << n); + PORT->PORTM_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTN): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTN_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTN_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTN_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTN_MUX1 |= (func - 100) << ((n - 6) * 5); + } + else if (n < PIN18) + { + PORT->PORTN_MUX2 &= ~(0x1F << ((n - 12) * 5)); + PORT->PORTN_MUX2 |= (func - 100) << ((n - 12) * 5); + } + } + + if (n < 16) + { + PORT->PORTN_SEL0 &= ~(0x03 << (n * 2)); + PORT->PORTN_SEL0 |= (func > 99 ? 1 : func) << (n * 2); + } + else + { + PORT->PORTN_SEL1 &= ~(0x03 << ((n - 16) * 2)); + PORT->PORTN_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2); + } + + PORT->PORTN_INEN &= ~(0x01 << n); + PORT->PORTN_INEN |= (digit_in_en << n); + break; + + case ((uint32_t)PORTP): + if (func > 99) + { + if (n < PIN6) + { + PORT->PORTP_MUX0 &= ~(0x1F << (n * 5)); + PORT->PORTP_MUX0 |= (func - 100) << (n * 5); + } + else if (n < PIN12) + { + PORT->PORTP_MUX1 &= ~(0x1F << ((n - 6) * 5)); + PORT->PORTP_MUX1 |= (func - 100) << ((n - 6) * 5); + } + else if (n < PIN18) + { + PORT->PORTP_MUX2 &= ~(0x1F << ((n - 12) * 5)); + PORT->PORTP_MUX2 |= (func - 100) << ((n - 12) * 5); + } + else if (n < PIN24) + { + PORT->PORTP_MUX3 &= ~(0x1F << ((n - 18) * 5)); + PORT->PORTP_MUX3 |= (func - 100) << ((n - 18) * 5); + } + } + + if (n < 16) + { + PORT->PORTP_SEL0 &= ~(0x03 << (n * 2)); + PORT->PORTP_SEL0 |= (func > 99 ? 1 : func) << (n * 2); + } + else + { + PORT->PORTP_SEL1 &= ~(0x03 << ((n - 16) * 2)); + PORT->PORTP_SEL1 |= (func > 99 ? 1 : func) << ((n - 16) * 2); + } + + PORT->PORTP_INEN &= ~(0x01 << n); + PORT->PORTP_INEN |= (digit_in_en << n); + break; + } +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h new file mode 100644 index 00000000000..ff0fd9cdc91 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h @@ -0,0 +1,482 @@ +#ifndef __SWM320_PORT_H__ +#define __SWM320_PORT_H__ + +void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //˿Źѡȡֵ£ + +#define PORTA 0 +#define PORTB 1 +#define PORTC 2 +#define PORTM 3 +#define PORTN 4 +#define PORTP 5 + +#define PORTA_PIN0_GPIO 0 +#define PORTA_PIN0_FUNMUX 1 +#define PORTA_PIN0_SWCLK 2 + +#define PORTA_PIN1_GPIO 0 +#define PORTA_PIN1_FUNMUX 1 +#define PORTA_PIN1_SWDIO 2 + +#define PORTA_PIN2_GPIO 0 +#define PORTA_PIN2_FUNMUX 1 + +#define PORTA_PIN3_GPIO 0 +#define PORTA_PIN3_FUNMUX 1 + +#define PORTA_PIN4_GPIO 0 +#define PORTA_PIN4_FUNMUX 1 + +#define PORTA_PIN5_GPIO 0 +#define PORTA_PIN5_FUNMUX 1 + +#define PORTA_PIN6_GPIO 0 +#define PORTA_PIN6_FUNMUX 1 + +#define PORTA_PIN7_GPIO 0 +#define PORTA_PIN7_FUNMUX 1 + +#define PORTA_PIN8_GPIO 0 +#define PORTA_PIN8_FUNMUX 1 + +#define PORTA_PIN9_GPIO 0 +#define PORTA_PIN9_FUNMUX 1 +#define PORTA_PIN9_ADC0_IN7 3 + +#define PORTA_PIN10_GPIO 0 +#define PORTA_PIN10_FUNMUX 1 +#define PORTA_PIN10_ADC0_IN6 3 + +#define PORTA_PIN11_GPIO 0 +#define PORTA_PIN11_FUNMUX 1 +#define PORTA_PIN11_ADC0_IN5 3 + +#define PORTA_PIN12_GPIO 0 +#define PORTA_PIN12_ADC0_IN4 3 + + +#define PORTB_PIN0_GPIO 0 +#define PORTB_PIN0_FUNMUX 1 +#define PORTB_PIN0_SD_DETECT 2 + +#define PORTB_PIN1_GPIO 0 +#define PORTB_PIN1_FUNMUX 1 +#define PORTB_PIN1_SD_CLK 2 + +#define PORTB_PIN2_GPIO 0 +#define PORTB_PIN2_FUNMUX 1 +#define PORTB_PIN2_SD_CMD 2 + +#define PORTB_PIN3_GPIO 0 +#define PORTB_PIN3_FUNMUX 1 +#define PORTB_PIN3_SD_D0 2 + +#define PORTB_PIN4_GPIO 0 +#define PORTB_PIN4_FUNMUX 1 +#define PORTB_PIN4_SD_D1 2 + +#define PORTB_PIN5_GPIO 0 +#define PORTB_PIN5_FUNMUX 1 +#define PORTB_PIN5_SD_D2 2 + +#define PORTB_PIN6_GPIO 0 +#define PORTB_PIN6_FUNMUX 1 +#define PORTB_PIN6_SD_D3 2 + +#define PORTB_PIN7_GPIO 0 +#define PORTB_PIN7_FUNMUX 1 +#define PORTB_PIN7_SD_D4 2 + +#define PORTB_PIN8_GPIO 0 +#define PORTB_PIN8_FUNMUX 1 +#define PORTB_PIN8_SD_D5 2 + +#define PORTB_PIN9_GPIO 0 +#define PORTB_PIN9_FUNMUX 1 +#define PORTB_PIN9_SD_D6 2 + +#define PORTB_PIN10_GPIO 0 +#define PORTB_PIN10_FUNMUX 1 +#define PORTB_PIN10_SD_D7 2 + +#define PORTB_PIN11_GPIO 0 +#define PORTB_PIN11_FUNMUX 1 + +#define PORTB_PIN12_GPIO 0 + + +#define PORTC_PIN0_GPIO 0 +#define PORTC_PIN0_FUNMUX 1 + +#define PORTC_PIN1_GPIO 0 +#define PORTC_PIN1_FUNMUX 1 + +#define PORTC_PIN2_GPIO 0 +#define PORTC_PIN2_FUNMUX 1 + +#define PORTC_PIN3_GPIO 0 +#define PORTC_PIN3_FUNMUX 1 + +#define PORTC_PIN4_GPIO 0 +#define PORTC_PIN4_FUNMUX 1 +#define PORTC_PIN4_ADC1_IN3 3 + +#define PORTC_PIN5_GPIO 0 +#define PORTC_PIN5_FUNMUX 1 +#define PORTC_PIN5_ADC1_IN2 3 + +#define PORTC_PIN6_GPIO 0 +#define PORTC_PIN6_FUNMUX 1 +#define PORTC_PIN6_ADC1_IN1 3 + +#define PORTC_PIN7_GPIO 0 +#define PORTC_PIN7_FUNMUX 1 +#define PORTC_PIN7_ADC1_IN0 3 + + +#define PORTM_PIN0_GPIO 0 +#define PORTM_PIN0_FUNMUX 1 +#define PORTM_PIN0_NORFL_D15 2 + +#define PORTM_PIN1_GPIO 0 +#define PORTM_PIN1_FUNMUX 1 +#define PORTM_PIN1_NORFL_D14 2 + +#define PORTM_PIN2_GPIO 0 +#define PORTM_PIN2_FUNMUX 1 +#define PORTM_PIN2_NORFL_D13 2 + +#define PORTM_PIN3_GPIO 0 +#define PORTM_PIN3_FUNMUX 1 +#define PORTM_PIN3_NORFL_D12 2 + +#define PORTM_PIN4_GPIO 0 +#define PORTM_PIN4_FUNMUX 1 +#define PORTM_PIN4_NORFL_D11 2 + +#define PORTM_PIN5_GPIO 0 +#define PORTM_PIN5_FUNMUX 1 +#define PORTM_PIN5_NORFL_D10 2 + +#define PORTM_PIN6_GPIO 0 +#define PORTM_PIN6_FUNMUX 1 +#define PORTM_PIN6_NORFL_D9 2 + +#define PORTM_PIN7_GPIO 0 +#define PORTM_PIN7_FUNMUX 1 +#define PORTM_PIN7_NORFL_D8 2 + +#define PORTM_PIN8_GPIO 0 +#define PORTM_PIN8_FUNMUX 1 +#define PORTM_PIN8_NORFL_D7 2 + +#define PORTM_PIN9_GPIO 0 +#define PORTM_PIN9_FUNMUX 1 +#define PORTM_PIN9_NORFL_D6 2 + +#define PORTM_PIN10_GPIO 0 +#define PORTM_PIN10_FUNMUX 1 +#define PORTM_PIN10_NORFL_D5 2 + +#define PORTM_PIN11_GPIO 0 +#define PORTM_PIN11_FUNMUX 1 +#define PORTM_PIN11_NORFL_D4 2 + +#define PORTM_PIN12_GPIO 0 +#define PORTM_PIN12_FUNMUX 1 +#define PORTM_PIN12_NORFL_D3 2 + +#define PORTM_PIN13_GPIO 0 +#define PORTM_PIN13_FUNMUX 1 +#define PORTM_PIN13_NORFL_D2 2 + +#define PORTM_PIN14_GPIO 0 +#define PORTM_PIN14_FUNMUX 1 +#define PORTM_PIN14_NORFL_D1 2 + +#define PORTM_PIN15_GPIO 0 +#define PORTM_PIN15_FUNMUX 1 +#define PORTM_PIN15_NORFL_D0 2 + +#define PORTM_PIN16_GPIO 0 +#define PORTM_PIN16_FUNMUX 1 +#define PORTM_PIN16_NORFL_OEN 2 + +#define PORTM_PIN17_GPIO 0 +#define PORTM_PIN17_FUNMUX 1 +#define PORTM_PIN17_NORFL_WEN 2 + +#define PORTM_PIN18_GPIO 0 +#define PORTM_PIN18_FUNMUX 1 +#define PORTM_PIN18_NORFL_CSN 2 + +#define PORTM_PIN19_GPIO 0 +#define PORTM_PIN19_FUNMUX 1 +#define PORTM_PIN19_SDRAM_CSN 2 + +#define PORTM_PIN20_GPIO 0 +#define PORTM_PIN20_FUNMUX 1 +#define PORTM_PIN20_SRAM_CSN 2 + +#define PORTM_PIN21_GPIO 0 +#define PORTM_PIN21_FUNMUX 1 +#define PORTM_PIN21_SDRAM_CKE 2 + + +#define PORTN_PIN0_GPIO 0 +#define PORTN_PIN0_FUNMUX 1 +#define PORTN_PIN0_LCD_D0 2 +#define PORTN_PIN0_ADC1_IN4 3 + +#define PORTN_PIN1_GPIO 0 +#define PORTN_PIN1_FUNMUX 1 +#define PORTN_PIN1_LCD_D1 2 +#define PORTN_PIN1_ADC1_IN5 3 + +#define PORTN_PIN2_GPIO 0 +#define PORTN_PIN2_FUNMUX 1 +#define PORTN_PIN2_LCD_D2 2 +#define PORTN_PIN2_ADC1_IN6 3 + +#define PORTN_PIN3_GPIO 0 +#define PORTN_PIN3_FUNMUX 1 +#define PORTN_PIN3_LCD_D3 2 + +#define PORTN_PIN4_GPIO 0 +#define PORTN_PIN4_FUNMUX 1 +#define PORTN_PIN4_LCD_D4 2 + +#define PORTN_PIN5_GPIO 0 +#define PORTN_PIN5_FUNMUX 1 +#define PORTN_PIN5_LCD_D5 2 + +#define PORTN_PIN6_GPIO 0 +#define PORTN_PIN6_FUNMUX 1 +#define PORTN_PIN6_LCD_D6 2 + +#define PORTN_PIN7_GPIO 0 +#define PORTN_PIN7_FUNMUX 1 +#define PORTN_PIN7_LCD_D7 2 + +#define PORTN_PIN8_GPIO 0 +#define PORTN_PIN8_FUNMUX 1 +#define PORTN_PIN8_LCD_D8 2 + +#define PORTN_PIN9_GPIO 0 +#define PORTN_PIN9_FUNMUX 1 +#define PORTN_PIN9_LCD_D9 2 + +#define PORTN_PIN10_GPIO 0 +#define PORTN_PIN10_FUNMUX 1 +#define PORTN_PIN10_LCD_D10 2 + +#define PORTN_PIN11_GPIO 0 +#define PORTN_PIN11_FUNMUX 1 +#define PORTN_PIN11_LCD_D11 2 + +#define PORTN_PIN12_GPIO 0 +#define PORTN_PIN12_FUNMUX 1 +#define PORTN_PIN12_LCD_D12 2 + +#define PORTN_PIN13_GPIO 0 +#define PORTN_PIN13_FUNMUX 1 +#define PORTN_PIN13_LCD_D13 2 + +#define PORTN_PIN14_GPIO 0 +#define PORTN_PIN14_FUNMUX 1 +#define PORTN_PIN14_LCD_D14 2 + +#define PORTN_PIN15_GPIO 0 +#define PORTN_PIN15_FUNMUX 1 +#define PORTN_PIN15_LCD_D15 2 + +#define PORTN_PIN16_GPIO 0 +#define PORTN_PIN16_FUNMUX 1 +#define PORTN_PIN16_LCD_RD 2 +#define PORTN_PIN16_LCD_DOTCK 2 + +#define PORTN_PIN17_GPIO 0 +#define PORTN_PIN17_FUNMUX 1 +#define PORTN_PIN17_LCD_CS 2 +#define PORTN_PIN17_LCD_VSYNC 2 + +#define PORTN_PIN18_GPIO 0 +#define PORTN_PIN18_LCD_RS 2 +#define PORTN_PIN18_LCD_DATEN 2 //Data Enable + +#define PORTN_PIN19_GPIO 0 +#define PORTN_PIN19_LCD_WR 2 +#define PORTN_PIN19_LCD_HSYNC 2 + + +#define PORTP_PIN0_GPIO 0 +#define PORTP_PIN0_FUNMUX 1 +#define PORTP_PIN0_NORFL_A0 2 + +#define PORTP_PIN1_GPIO 0 +#define PORTP_PIN1_FUNMUX 1 +#define PORTP_PIN1_NORFL_A1 2 + +#define PORTP_PIN2_GPIO 0 +#define PORTP_PIN2_FUNMUX 1 +#define PORTP_PIN2_NORFL_A2 2 +#define PORTP_PIN2_SD_D7 3 + +#define PORTP_PIN3_GPIO 0 +#define PORTP_PIN3_FUNMUX 1 +#define PORTP_PIN3_NORFL_A3 2 +#define PORTP_PIN3_SD_D6 3 + +#define PORTP_PIN4_GPIO 0 +#define PORTP_PIN4_FUNMUX 1 +#define PORTP_PIN4_NORFL_A4 2 +#define PORTP_PIN4_SD_D5 3 + +#define PORTP_PIN5_GPIO 0 +#define PORTP_PIN5_FUNMUX 1 +#define PORTP_PIN5_NORFL_A5 2 +#define PORTP_PIN5_SD_D4 3 + +#define PORTP_PIN6_GPIO 0 +#define PORTP_PIN6_FUNMUX 1 +#define PORTP_PIN6_NORFL_A6 2 +#define PORTP_PIN6_SD_D3 3 + +#define PORTP_PIN7_GPIO 0 +#define PORTP_PIN7_FUNMUX 1 +#define PORTP_PIN7_NORFL_A7 2 +#define PORTP_PIN7_SD_D2 3 + +#define PORTP_PIN8_GPIO 0 +#define PORTP_PIN8_FUNMUX 1 +#define PORTP_PIN8_NORFL_A8 2 +#define PORTP_PIN8_SD_D1 3 + +#define PORTP_PIN9_GPIO 0 +#define PORTP_PIN9_FUNMUX 1 +#define PORTP_PIN9_NORFL_A9 2 +#define PORTP_PIN9_SD_D0 3 + +#define PORTP_PIN10_GPIO 0 +#define PORTP_PIN10_FUNMUX 1 +#define PORTP_PIN10_NORFL_A10 2 +#define PORTP_PIN10_SD_CMD 3 + +#define PORTP_PIN11_GPIO 0 +#define PORTP_PIN11_FUNMUX 1 +#define PORTP_PIN11_NORFL_A11 2 +#define PORTP_PIN11_SD_CLK 3 + +#define PORTP_PIN12_GPIO 0 +#define PORTP_PIN12_FUNMUX 1 +#define PORTP_PIN12_NORFL_A12 2 +#define PORTP_PIN12_SD_DETECT 3 + +#define PORTP_PIN13_GPIO 0 +#define PORTP_PIN13_FUNMUX 1 +#define PORTP_PIN13_NORFL_A13 2 +#define PORTP_PIN13_SDRAM_CLK 2 + +#define PORTP_PIN14_GPIO 0 +#define PORTP_PIN14_FUNMUX 1 +#define PORTP_PIN14_NORFL_A14 2 +#define PORTP_PIN14_SDRAM_CAS 2 + +#define PORTP_PIN15_GPIO 0 +#define PORTP_PIN15_FUNMUX 1 +#define PORTP_PIN15_NORFL_A15 2 +#define PORTP_PIN15_SDRAM_RAS 2 + +#define PORTP_PIN16_GPIO 0 +#define PORTP_PIN16_FUNMUX 1 +#define PORTP_PIN16_NORFL_A16 2 +#define PORTP_PIN16_SDRAM_LDQ 2 + +#define PORTP_PIN17_GPIO 0 +#define PORTP_PIN17_FUNMUX 1 +#define PORTP_PIN17_NORFL_A17 2 +#define PORTP_PIN17_SDRAM_UDQ 2 + +#define PORTP_PIN18_GPIO 0 +#define PORTP_PIN18_FUNMUX 1 +#define PORTP_PIN18_NORFL_A18 2 + +#define PORTP_PIN19_GPIO 0 +#define PORTP_PIN19_FUNMUX 1 +#define PORTP_PIN19_NORFL_A19 2 + +#define PORTP_PIN20_GPIO 0 +#define PORTP_PIN20_FUNMUX 1 +#define PORTP_PIN20_NORFL_A20 2 +#define PORTP_PIN20_SDRAM_BA0 2 + +#define PORTP_PIN21_GPIO 0 +#define PORTP_PIN21_FUNMUX 1 +#define PORTP_PIN21_NORFL_A21 2 +#define PORTP_PIN21_SDRAM_BA1 2 + +#define PORTP_PIN22_GPIO 0 +#define PORTP_PIN22_FUNMUX 1 +#define PORTP_PIN22_NORFL_A22 2 + +#define PORTP_PIN23_GPIO 0 +#define PORTP_PIN23_FUNMUX 1 +#define PORTP_PIN23_NORFL_A23 2 + + + +/* 궨ȡֵȫȷֵĻϡ100궨ֵӶ⺯ıд*/ +/* ЩֵżŵĹȡֵPIN0PIN2... */ +#define FUNMUX0_UART0_RXD 100 +#define FUNMUX0_UART1_RXD 101 +#define FUNMUX0_UART2_RXD 102 +#define FUNMUX0_UART3_RXD 103 +#define FUNMUX0_I2C0_SCL 105 +#define FUNMUX0_I2C1_SCL 106 +#define FUNMUX0_PWM0A_OUT 107 +#define FUNMUX0_PWM2A_OUT 108 +#define FUNMUX0_PWM4A_OUT 109 +#define FUNMUX0_PWM0B_OUT 110 +#define FUNMUX0_PWM2B_OUT 111 +#define FUNMUX0_PWM4B_OUT 112 +#define FUNMUX0_PWM_BREAK 113 +#define FUNMUX0_TIMR0_IN 114 +#define FUNMUX0_TIMR2_IN 115 +#define FUNMUX0_CAN_RX 116 +#define FUNMUX0_SPI0_SSEL 117 +#define FUNMUX0_SPI0_MOSI 118 +#define FUNMUX0_SPI1_SSEL 119 +#define FUNMUX0_SPI1_MOSI 120 +#define FUNMUX0_UART0_CTS 121 +#define FUNMUX0_UART1_CTS 122 +#define FUNMUX0_UART2_CTS 123 +#define FUNMUX0_UART3_CTS 124 + +/* ЩֵŵĹȡֵPIN1PIN3... */ +#define FUNMUX1_UART0_TXD 100 +#define FUNMUX1_UART1_TXD 101 +#define FUNMUX1_UART2_TXD 102 +#define FUNMUX1_UART3_TXD 103 +#define FUNMUX1_I2C0_SDA 105 +#define FUNMUX1_I2C1_SDA 106 +#define FUNMUX1_PWM1A_OUT 107 +#define FUNMUX1_PWM3A_OUT 108 +#define FUNMUX1_PWM5A_OUT 109 +#define FUNMUX1_PWM1B_OUT 110 +#define FUNMUX1_PWM3B_OUT 111 +#define FUNMUX1_PWM5B_OUT 112 +#define FUNMUX1_PULSE_IN 113 +#define FUNMUX1_TIMR1_IN 114 +#define FUNMUX1_TIMR3_IN 115 +#define FUNMUX1_CAN_TX 116 +#define FUNMUX1_SPI0_SCLK 117 +#define FUNMUX1_SPI0_MISO 118 +#define FUNMUX1_SPI1_SCLK 119 +#define FUNMUX1_SPI1_MISO 120 +#define FUNMUX1_UART0_RTS 121 +#define FUNMUX1_UART1_RTS 122 +#define FUNMUX1_UART2_RTS 123 +#define FUNMUX1_UART3_RTS 124 + + +#endif //__SWM320_PORT_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c new file mode 100644 index 00000000000..454d19e1975 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c @@ -0,0 +1,744 @@ +/****************************************************************************************************************************************** +* 文件名称: SWM320_pwm.c +* 功能说明: SWM320单片机的PWM功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_pwm.h" + +/****************************************************************************************************************************************** +* 函数名称: PWM_Init() +* 功能说明: PWM初始化 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* PWM_InitStructure * initStruct 包含PWM相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_Init(PWM_TypeDef *PWMx, PWM_InitStructure *initStruct) +{ + uint32_t bit_offset = 0; + + SYS->CLKEN |= (0x01 << SYS_CLKEN_PWM_Pos); + + SYS->CLKDIV &= ~SYS_CLKDIV_PWM_Msk; + SYS->CLKDIV |= (initStruct->clk_div << SYS_CLKDIV_PWM_Pos); + + PWM_Stop(PWMx, 1, 1); //一些关键寄存器只能在PWM停止时设置 + + PWMx->MODE = initStruct->mode; + + PWMx->PERA = initStruct->cycleA; + PWMx->HIGHA = initStruct->hdutyA; + PWMx->DZA = initStruct->deadzoneA; + + PWMx->PERB = initStruct->cycleB; + PWMx->HIGHB = initStruct->hdutyB; + PWMx->DZB = initStruct->deadzoneB; + + PWMx->INIOUT &= ~(PWM_INIOUT_PWMA_Msk | PWM_INIOUT_PWMB_Msk); + PWMx->INIOUT |= (initStruct->initLevelA << PWM_INIOUT_PWMA_Pos) | + (initStruct->initLevelB << PWM_INIOUT_PWMB_Pos); + + PWMG->IM = 0x00000000; + + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + bit_offset = 0; + break; + + case ((uint32_t)PWM1): + bit_offset = 2; + break; + + case ((uint32_t)PWM2): + bit_offset = 4; + break; + + case ((uint32_t)PWM3): + bit_offset = 6; + break; + + case ((uint32_t)PWM4): + bit_offset = 8; + break; + + case ((uint32_t)PWM5): + bit_offset = 10; + break; + } + + PWMG->IRS = ((0x01 << bit_offset) | (0x01 << (bit_offset + 1)) | (0x01 << (bit_offset + 12)) | (0x01 << (bit_offset + 13))); //清除中断标志 + PWMG->IE &= ~((0x01 << bit_offset) | (0x01 << (bit_offset + 1)) | (0x01 << (bit_offset + 12)) | (0x01 << (bit_offset + 13))); + PWMG->IE |= (initStruct->NCycleAIEn << bit_offset) | (initStruct->NCycleBIEn << (bit_offset + 1)) | + (initStruct->HEndAIEn << (bit_offset + 12)) | (initStruct->HEndBIEn << (bit_offset + 13)); + + if (initStruct->NCycleAIEn | initStruct->NCycleBIEn | initStruct->HEndAIEn | initStruct->HEndBIEn) + { + NVIC_EnableIRQ(PWM_IRQn); + } + else if ((PWMG->IE & (~((0x01 << bit_offset) | (0x01 << (bit_offset + 1)) | (0x01 << (bit_offset + 12)) | (0x01 << (bit_offset + 13))))) == 0) + { + NVIC_DisableIRQ(PWM_IRQn); + } +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_Start() +* 功能说明: 启动PWM，开始PWM输出 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chA 0 通道A不启动 1 通道A启动 +* uint32_t chB 0 通道B不启动 1 通道B启动 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_Start(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM0A_Pos) | (chB << PWMG_CHEN_PWM0B_Pos); + break; + + case ((uint32_t)PWM1): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM1A_Pos) | (chB << PWMG_CHEN_PWM1B_Pos); + break; + + case ((uint32_t)PWM2): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM2A_Pos) | (chB << PWMG_CHEN_PWM2B_Pos); + break; + + case ((uint32_t)PWM3): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM3A_Pos) | (chB << PWMG_CHEN_PWM3B_Pos); + break; + + case ((uint32_t)PWM4): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM4A_Pos) | (chB << PWMG_CHEN_PWM4B_Pos); + break; + + case ((uint32_t)PWM5): + PWMG->CHEN |= (chA << PWMG_CHEN_PWM5A_Pos) | (chB << PWMG_CHEN_PWM5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_Stop() +* 功能说明: 关闭PWM，停止PWM输出 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chA 0 通道A不关闭 1 通道A关闭 +* uint32_t chB 0 通道B不关闭 1 通道B关闭 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_Stop(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM0A_Pos) | (chB << PWMG_CHEN_PWM0B_Pos)); + break; + + case ((uint32_t)PWM1): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM1A_Pos) | (chB << PWMG_CHEN_PWM1B_Pos)); + break; + + case ((uint32_t)PWM2): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM2A_Pos) | (chB << PWMG_CHEN_PWM2B_Pos)); + break; + + case ((uint32_t)PWM3): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM3A_Pos) | (chB << PWMG_CHEN_PWM3B_Pos)); + break; + + case ((uint32_t)PWM4): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM4A_Pos) | (chB << PWMG_CHEN_PWM4B_Pos)); + break; + + case ((uint32_t)PWM5): + PWMG->CHEN &= ~((chA << PWMG_CHEN_PWM5A_Pos) | (chB << PWMG_CHEN_PWM5B_Pos)); + break; + } +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_SetCycle() +* 功能说明: 设置周期 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* uint16_t cycle 要设定的周期值 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_SetCycle(PWM_TypeDef *PWMx, uint32_t chn, uint16_t cycle) +{ + if (chn == PWM_CH_A) + PWMx->PERA = cycle; + else if (chn == PWM_CH_B) + PWMx->PERB = cycle; +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_GetCycle() +* 功能说明: 获取周期 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要查询哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: uint16_t 获取到的周期值 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn) +{ + uint16_t cycle = 0; + + if (chn == PWM_CH_A) + cycle = PWMx->PERA; + else if (chn == PWM_CH_B) + cycle = PWMx->PERB; + + return cycle; +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_SetHDuty() +* 功能说明: 设置高电平时长 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* uint16_t hduty 要设定的高电平时长 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_SetHDuty(PWM_TypeDef *PWMx, uint32_t chn, uint16_t hduty) +{ + if (chn == PWM_CH_A) + PWMx->HIGHA = hduty; + else if (chn == PWM_CH_B) + PWMx->HIGHB = hduty; +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_GetHDuty() +* 功能说明: 获取高电平时长 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要查询哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: uint16_t 获取到的高电平时长 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn) +{ + uint16_t hduty = 0; + + if (chn == PWM_CH_A) + hduty = PWMx->HIGHA; + else if (chn == PWM_CH_B) + hduty = PWMx->HIGHB; + + return hduty; +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_SetDeadzone() +* 功能说明: 设置死区时长 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* uint8_t deadzone 要设定的死区时长 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_SetDeadzone(PWM_TypeDef *PWMx, uint32_t chn, uint8_t deadzone) +{ + if (chn == PWM_CH_A) + PWMx->DZA = deadzone; + else if (chn == PWM_CH_B) + PWMx->DZB = deadzone; +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_GetDeadzone() +* 功能说明: 获取死区时长 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要查询哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: uint8_t 获取到的死区时长 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn) +{ + uint8_t deadzone = 0; + + if (chn == PWM_CH_A) + deadzone = PWMx->DZA; + else if (chn == PWM_CH_B) + deadzone = PWMx->DZB; + + return deadzone; +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_IntNCycleEn() +* 功能说明: 新周期开始中断使能 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_IntNCycleEn(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP0A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP1A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP2A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP3A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP4A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_NEWP5A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_NEWP5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_IntNCycleDis() +* 功能说明: 新周期开始中断禁能 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_IntNCycleDis(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP0A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP1A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP2A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP3A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP4A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP5A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_NEWP5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_IntNCycleClr() +* 功能说明: 新周期开始中断标志清除 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_IntNCycleClr(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP0A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP1A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP2A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP3A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP4A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_NEWP5A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_NEWP5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_IntNCycleStat() +* 功能说明: 新周期开始中断是否发生 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: uint32_t 1 新周期开始中断已发生 0 新周期开始中断未发生 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn) +{ + uint32_t int_stat = 0; + + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP0A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP0B_Msk); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP1A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP1B_Msk); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP2A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP2B_Msk); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP3A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP3B_Msk); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP4A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP4B_Msk); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_NEWP5A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_NEWP5B_Msk); + break; + } + + return int_stat; +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_IntHEndEn() +* 功能说明: 高电平结束中断使能 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_IntHEndEn(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND0A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND1A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND2A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND3A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND4A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IE |= (0x01 << PWMG_IE_HEND5A_Pos); + else + PWMG->IE |= (0x01 << PWMG_IE_HEND5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_IntHEndDis() +* 功能说明: 高电平结束中断禁能 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_IntHEndDis(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND0A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND1A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND2A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND3A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND4A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IE &= ~(0x01 << PWMG_IE_HEND5A_Pos); + else + PWMG->IE &= ~(0x01 << PWMG_IE_HEND5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_IntHEndClr() +* 功能说明: 高电平结束中断标志清除 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void PWM_IntHEndClr(PWM_TypeDef *PWMx, uint32_t chn) +{ + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND0A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND0B_Pos); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND1A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND1B_Pos); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND2A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND2B_Pos); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND3A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND3B_Pos); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND4A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND4B_Pos); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + PWMG->IRS = (0x01 << PWMG_IRS_HEND5A_Pos); + else + PWMG->IRS = (0x01 << PWMG_IRS_HEND5B_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* 函数名称: PWM_IntHEndStat() +* 功能说明: 高电平结束中断是否发生 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B +* 输 出: uint32_t 1 高电平结束中断已发生 0 高电平结束中断未发生 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t PWM_IntHEndStat(PWM_TypeDef *PWMx, uint32_t chn) +{ + uint32_t int_stat = 0; + + switch ((uint32_t)PWMx) + { + case ((uint32_t)PWM0): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND0A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND0B_Msk); + break; + + case ((uint32_t)PWM1): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND1A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND1B_Msk); + break; + + case ((uint32_t)PWM2): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND2A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND2B_Msk); + break; + + case ((uint32_t)PWM3): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND3A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND3B_Msk); + break; + + case ((uint32_t)PWM4): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND4A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND4B_Msk); + break; + + case ((uint32_t)PWM5): + if (chn == PWM_CH_A) + int_stat = (PWMG->IF & PWMG_IF_HEND5A_Msk); + else + int_stat = (PWMG->IF & PWMG_IF_HEND5B_Msk); + break; + } + + return int_stat; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h new file mode 100644 index 00000000000..888e0c5e393 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.h @@ -0,0 +1,57 @@ +#ifndef __SWM320_PWM_H__ +#define __SWM320_PWM_H__ + +typedef struct +{ + uint8_t clk_div; //PWM_CLKDIV_1、PWM_CLKDIV_8 + + uint8_t mode; //PWM_MODE_INDEP、PWM_MODE_COMPL、PWM_MODE_INDEP_CALIGN、PWM_MODE_COMPL_CALIGN + + uint16_t cycleA; //A路周期 + uint16_t hdutyA; //A路占空比 + uint16_t deadzoneA; //A路死区时长，取值0--1023 + uint8_t initLevelA; //A路初始输出电平，0 低电平 1 高电平 + + uint16_t cycleB; //B路周期 + uint16_t hdutyB; //B路占空比 + uint16_t deadzoneB; //B路死区时长，取值0--1023 + uint8_t initLevelB; //B路初始输出电平，0 低电平 1 高电平 + + uint8_t HEndAIEn; //A路高电平结束中断使能 + uint8_t NCycleAIEn; //A路新周期开始中断使能 + uint8_t HEndBIEn; //B路高电平结束中断使能 + uint8_t NCycleBIEn; //B路新周期开始中断使能 +} PWM_InitStructure; + +#define PWM_CLKDIV_1 0 +#define PWM_CLKDIV_8 1 + +#define PWM_MODE_INDEP 0 //A路和B路为两路独立输出 +#define PWM_MODE_COMPL 1 //A路和B路为一路互补输出 +#define PWM_MODE_INDEP_CALIGN 3 //A路和B路为两路独立输出，中心对齐 +#define PWM_MODE_COMPL_CALIGN 4 //A路和B路为一路互补输出，中心对齐 + +#define PWM_CH_A 0 +#define PWM_CH_B 1 + +void PWM_Init(PWM_TypeDef *PWMx, PWM_InitStructure *initStruct); //PWM初始化 +void PWM_Start(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB); //启动PWM，开始PWM输出 +void PWM_Stop(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB); //关闭PWM，停止PWM输出 + +void PWM_SetCycle(PWM_TypeDef *PWMx, uint32_t chn, uint16_t cycle); //设置周期 +uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn); //获取周期 +void PWM_SetHDuty(PWM_TypeDef *PWMx, uint32_t chn, uint16_t hduty); //设置高电平时长 +uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn); //获取高电平时长 +void PWM_SetDeadzone(PWM_TypeDef *PWMx, uint32_t chn, uint8_t deadzone); //设置死区时长 +uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn); //获取死区时长 + +void PWM_IntNCycleEn(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断使能 +void PWM_IntNCycleDis(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断禁能 +void PWM_IntNCycleClr(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断标志清除 +uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn); //新周期开始中断是否发生 +void PWM_IntHEndEn(PWM_TypeDef *PWMx, uint32_t chn); //高电平结束中断使能 +void PWM_IntHEndDis(PWM_TypeDef *PWMx, uint32_t chn); //高电平结束中断禁能 +void PWM_IntHEndClr(PWM_TypeDef *PWMx, uint32_t chn); //高电平结束中断标志清除 +uint32_t PWM_IntHEndStat(PWM_TypeDef *PWMx, uint32_t chn); //高电平结束中断是否发生 + +#endif //__SWM320_PWM_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c new file mode 100644 index 00000000000..60958799ed6 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c @@ -0,0 +1,413 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_rtc.c +* ˵: SWM320ƬRTC +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_rtc.h" + + +static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date); +/****************************************************************************************************************************************** +* : RTC_Init() +* ˵: RTCʼ +* : RTC_TypeDef * RTCx ָҪõRTCЧֵRTC +* RTC_InitStructure * initStruct RTC趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct) +{ + SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); + + SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); //RTCʹ32KHz RCʱ + + SYS->CLKEN |= (1 << SYS_CLKEN_RTC_Pos) | + ((uint32_t)1 << SYS_CLKEN_ALIVE_Pos); + + RTC_Stop(RTCx); + + while (RTCx->CFGABLE == 0); + + RTCx->MINSEC = (initStruct->Second << RTC_MINSEC_SEC_Pos) | + (initStruct->Minute << RTC_MINSEC_MIN_Pos); + + RTCx->DATHUR = (initStruct->Hour << RTC_DATHUR_HOUR_Pos) | + ((initStruct->Date - 1) << RTC_DATHUR_DATE_Pos); + + RTCx->MONDAY = (calcWeekDay(initStruct->Year, initStruct->Month, initStruct->Date) << RTC_MONDAY_DAY_Pos) | + ((initStruct->Month - 1) << RTC_MONDAY_MON_Pos); + + RTCx->YEAR = initStruct->Year - 1901; + + RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos; + + RTCx->IF = 0x1F; + RTCx->IE = (initStruct->SecondIEn << RTC_IE_SEC_Pos) | + (initStruct->MinuteIEn << RTC_IE_MIN_Pos); + + if (initStruct->SecondIEn | initStruct->MinuteIEn) + { + NVIC_EnableIRQ(RTC_IRQn); + } + else + { + NVIC_DisableIRQ(RTC_IRQn); + } +} + +/****************************************************************************************************************************************** +* : RTC_Start() +* ˵: RTC +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_Start(RTC_TypeDef *RTCx) +{ + RTCx->EN = 1; +} + +/****************************************************************************************************************************************** +* : RTC_Stop() +* ˵: ֹͣRTC +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_Stop(RTC_TypeDef *RTCx) +{ + RTCx->EN = 0; +} + +/****************************************************************************************************************************************** +* : RTC_GetDateTime() +* ˵: ȡǰʱ +* : RTC_TypeDef * RTCx ָҪõRTCЧֵRTC +* RTC_DateTime * dateTime ȡʱ䡢ֵָָĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime) +{ + dateTime->Year = RTCx->YEAR + 1901; + dateTime->Month = ((RTCx->MONDAY & RTC_MONDAY_MON_Msk) >> RTC_MONDAY_MON_Pos) + 1; + dateTime->Date = ((RTCx->DATHUR & RTC_DATHUR_DATE_Msk) >> RTC_DATHUR_DATE_Pos) + 1; + dateTime->Day = 1 << ((RTCx->MONDAY & RTC_MONDAY_DAY_Msk) >> RTC_MONDAY_DAY_Pos); + dateTime->Hour = (RTCx->DATHUR & RTC_DATHUR_HOUR_Msk) >> RTC_DATHUR_HOUR_Pos; + dateTime->Minute = (RTCx->MINSEC & RTC_MINSEC_MIN_Msk) >> RTC_MINSEC_MIN_Pos; + dateTime->Second = (RTCx->MINSEC & RTC_MINSEC_SEC_Msk) >> RTC_MINSEC_SEC_Pos; +} + +/****************************************************************************************************************************************** +* : RTC_AlarmSetup() +* ˵: RTC趨 +* : RTC_TypeDef * RTCx ָҪõRTCЧֵRTC +* RTC_AlarmStructure * alarmStruct RTC趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct) +{ + while (RTCx->CFGABLE == 0); + + RTCx->MINSECAL = (alarmStruct->Second << RTC_MINSECAL_SEC_Pos) | + (alarmStruct->Minute << RTC_MINSECAL_MIN_Pos); + + RTCx->DAYHURAL = (alarmStruct->Hour << RTC_DAYHURAL_HOUR_Pos) | + (alarmStruct->Days << RTC_DAYHURAL_SUN_Pos); + + RTCx->LOAD = 1 << RTC_LOAD_ALARM_Pos; + while (RTCx->LOAD & RTC_LOAD_ALARM_Msk); + + RTCx->IF = (1 << RTC_IF_ALARM_Pos); + RTCx->IE &= ~RTC_IE_ALARM_Msk; + RTCx->IE |= (alarmStruct->AlarmIEn << RTC_IE_ALARM_Pos); + + if (alarmStruct->AlarmIEn) NVIC_EnableIRQ(RTC_IRQn); +} + +/****************************************************************************************************************************************** +* : calcWeekDay() +* ˵: ָꡢ¡ڼ +* : uint32_t year +* uint32_t month +* uint32_t date +* : uint32_t 0 1 һ ... ... 6 +* ע: +******************************************************************************************************************************************/ +static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) +{ + uint32_t i, cnt = 0; + const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + + for (i = 1; i < month; i++) cnt += daysOfMonth[i]; + + cnt += date; + + if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3)) cnt += 1; + + cnt += (year - 1901) * 365; + + for (i = 1901; i < year; i++) + { + if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0))) cnt += 1; + } + + return (cnt + 1) % 7; +} + +/****************************************************************************************************************************************** +* : RTC_IntSecondEn() +* ˵: жʹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntSecondEn(RTC_TypeDef *RTCx) +{ + RTCx->IE |= (1 << RTC_IE_SEC_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntSecondDis() +* ˵: жϽֹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntSecondDis(RTC_TypeDef *RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_SEC_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntSecondClr() +* ˵: жϱ־ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntSecondClr(RTC_TypeDef *RTCx) +{ + RTCx->IF = (1 << RTC_IF_SEC_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntSecondStat() +* ˵: ж״̬ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx) +{ + return (RTCx->IF & RTC_IF_SEC_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : RTC_IntMinuteEn() +* ˵: жʹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntMinuteEn(RTC_TypeDef *RTCx) +{ + RTCx->IE |= (1 << RTC_IE_MIN_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntMinuteDis() +* ˵: жϽֹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntMinuteDis(RTC_TypeDef *RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_MIN_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntMinuteClr() +* ˵: жϱ־ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntMinuteClr(RTC_TypeDef *RTCx) +{ + RTCx->IF = (1 << RTC_IF_MIN_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntMinuteStat() +* ˵: ж״̬ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx) +{ + return (RTCx->IF & RTC_IF_MIN_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : RTC_IntHourEn() +* ˵: ʱжʹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntHourEn(RTC_TypeDef *RTCx) +{ + RTCx->IE |= (1 << RTC_IE_HOUR_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntHourDis() +* ˵: ʱжϽֹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntHourDis(RTC_TypeDef *RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_HOUR_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntHourClr() +* ˵: ʱжϱ־ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntHourClr(RTC_TypeDef *RTCx) +{ + RTCx->IF = (1 << RTC_IF_HOUR_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntHourStat() +* ˵: ʱж״̬ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : uint32_t 1 ʱжϷ 0 ʱжδ +* ע: +******************************************************************************************************************************************/ +uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx) +{ + return (RTCx->IF & RTC_IF_HOUR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : RTC_IntDateEn() +* ˵: жʹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntDateEn(RTC_TypeDef *RTCx) +{ + RTCx->IE |= (1 << RTC_IE_DATE_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntDateDis() +* ˵: жϽֹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntDateDis(RTC_TypeDef *RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_DATE_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntDateClr() +* ˵: жϱ־ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntDateClr(RTC_TypeDef *RTCx) +{ + RTCx->IF = (1 << RTC_IF_DATE_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntDateStat() +* ˵: ж״̬ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx) +{ + return (RTCx->IF & RTC_IF_DATE_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : RTC_IntAlarmEn() +* ˵: жʹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntAlarmEn(RTC_TypeDef *RTCx) +{ + RTCx->IE |= (1 << RTC_IE_ALARM_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntAlarmDis() +* ˵: жϽֹ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntAlarmDis(RTC_TypeDef *RTCx) +{ + RTCx->IE &= ~(1 << RTC_IE_ALARM_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntAlarmClr() +* ˵: жϱ־ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : +* ע: +******************************************************************************************************************************************/ +void RTC_IntAlarmClr(RTC_TypeDef *RTCx) +{ + RTCx->IF = (1 << RTC_IF_ALARM_Pos); +} + +/****************************************************************************************************************************************** +* : RTC_IntAlarmStat() +* ˵: ж״̬ +* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t RTC_IntAlarmStat(RTC_TypeDef *RTCx) +{ + return (RTCx->IF & RTC_IF_ALARM_Msk) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h new file mode 100644 index 00000000000..8c5d6f5d638 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h @@ -0,0 +1,76 @@ +#ifndef __SWM320_RTC_H__ +#define __SWM320_RTC_H__ + + +#define RTC_SUN 0x01 +#define RTC_MON 0x02 +#define RTC_TUE 0x04 +#define RTC_WED 0x08 +#define RTC_THU 0x10 +#define RTC_FRI 0x20 +#define RTC_SAT 0x40 + + +typedef struct +{ + uint16_t Year; + uint8_t Month; + uint8_t Date; + uint8_t Hour; + uint8_t Minute; + uint8_t Second; + uint8_t SecondIEn; + uint8_t MinuteIEn; +} RTC_InitStructure; + +typedef struct +{ + uint8_t Days; //RTC_SUNRTC_MONRTC_TUERTC_WEDRTC_THURTC_FRIRTC_SAT + uint8_t Hour; + uint8_t Minute; + uint8_t Second; + uint8_t AlarmIEn; +} RTC_AlarmStructure; + +typedef struct +{ + uint16_t Year; + uint8_t Month; + uint8_t Date; + uint8_t Day; //RTC_SUNRTC_MONRTC_TUERTC_WEDRTC_THURTC_FRIRTC_SAT + uint8_t Hour; + uint8_t Minute; + uint8_t Second; +} RTC_DateTime; + +void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct); +void RTC_Start(RTC_TypeDef *RTCx); +void RTC_Stop(RTC_TypeDef *RTCx); + +void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime); + +void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct); + + +void RTC_IntSecondEn(RTC_TypeDef *RTCx); +void RTC_IntSecondDis(RTC_TypeDef *RTCx); +void RTC_IntSecondClr(RTC_TypeDef *RTCx); +uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx); +void RTC_IntMinuteEn(RTC_TypeDef *RTCx); +void RTC_IntMinuteDis(RTC_TypeDef *RTCx); +void RTC_IntMinuteClr(RTC_TypeDef *RTCx); +uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx); +void RTC_IntHourEn(RTC_TypeDef *RTCx); +void RTC_IntHourDis(RTC_TypeDef *RTCx); +void RTC_IntHourClr(RTC_TypeDef *RTCx); +uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx); +void RTC_IntDateEn(RTC_TypeDef *RTCx); +void RTC_IntDateDis(RTC_TypeDef *RTCx); +void RTC_IntDateClr(RTC_TypeDef *RTCx); +uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx); +void RTC_IntAlarmEn(RTC_TypeDef *RTCx); +void RTC_IntAlarmDis(RTC_TypeDef *RTCx); +void RTC_IntAlarmClr(RTC_TypeDef *RTCx); +uint32_t RTC_IntAlarmStat(RTC_TypeDef *RTCx); + +#endif //__SWM320_RTC_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c new file mode 100644 index 00000000000..305ab427338 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c @@ -0,0 +1,436 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_sdio.c +* ˵: SWM320ƬSDIOӿ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: Ϊͨԡԡԣֻ֧512ֽΪλĶд +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_sdio.h" + + +SD_CardInfo SD_cardInfo; + +/****************************************************************************************************************************************** +* : SDIO_Init() +* ˵: SDIOдSDʼʼɸ4ģʽд512ֽڴС +* : +* : +* ע: +******************************************************************************************************************************************/ +uint32_t SDIO_Init(void) +{ + uint32_t resp, resps[4]; + + SYS->CLKDIV &= ~SYS_CLKDIV_SDIO_Msk; + if (SystemCoreClock > 80000000) //SDIOʱҪС52MHz + SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4 + else + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2 + + SYS->CLKEN |= (0x01 << SYS_CLKEN_SDIO_Pos); + + SDIO->CR2 = (1 << SDIO_CR2_RSTALL_Pos); + + SDIO->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | + (0 << SDIO_CR1_8BIT_Pos) | + (0 << SDIO_CR1_4BIT_Pos) | + (1 << SDIO_CR1_PWRON_Pos) | + (7 << SDIO_CR1_VOLT_Pos); + + SDIO->CR2 = (1 << SDIO_CR2_CLKEN_Pos) | + (1 << SDIO_CR2_SDCLKEN_Pos) | + (calcSDCLKDiv(SD_CLK_400KHz) << SDIO_CR2_SDCLKDIV_Pos) | + (0xC << SDIO_CR2_TIMEOUT_Pos); + + while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0); + + SDIO->IE = 0xFFFF01FF; + SDIO->IM = 0x00FF00FF; + + SDIO_SendCmd(SD_CMD_GO_IDLE_STATE, 0x00, SD_RESP_NO, 0, 0, 0); //CMD0: GO_IDLE_STATE + + + SDIO_SendCmd(SD_CMD_SEND_IF_COND, 0x1AA, SD_RESP_32b, &resp, 0, 0); //CMD8: SEND_IF_COND, ⹤ѹǷ֧SD 2.0 + + if (resp == 0x1AA) SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; + else SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; + + + do //ACMD41: SD_CMD_SD_APP_OP_COND + { + SDIO_SendCmd(SD_CMD_APP_CMD, 0x00, SD_RESP_32b, &resp, 0, 0); + + if (resp != 0x120) return SD_RES_ERR; //SDMMC + + if (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0) + SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x40000000, SD_RESP_32b, &resp, 0, 0); + else + SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x00000000, SD_RESP_32b, &resp, 0, 0); + } + while (((resp >> 31) & 0x01) == 0); //ϵûʱresp[31] == 0 + + if (((resp >> 30) & 0x01) == 1) SD_cardInfo.CardType = SDIO_HIGH_CAPACITY_SD_CARD; + + + SDIO_SendCmd(SD_CMD_ALL_SEND_CID, 0x00, SD_RESP_128b, resps, 0, 0); //CMD2: SD_CMD_ALL_SEND_CIDȡCID + + parseCID(resps); + + + SDIO_SendCmd(SD_CMD_SET_REL_ADDR, 0x00, SD_RESP_32b, &resp, 0, 0); //CMD3: SD_CMD_SET_REL_ADDRRCA + + SD_cardInfo.RCA = resp >> 16; + + + SDIO_SendCmd(SD_CMD_SEND_CSD, SD_cardInfo.RCA << 16, SD_RESP_128b, resps, 0, 0); //CMD9: SD_CMD_SEND_CSDȡCSD + + parseCSD(resps); + + if (SD_cardInfo.CardBlockSize < 0x200) return SD_RES_ERR; //ֻ֧512ֽΪλĶддλ벻С512 + + + SDIO->CR2 &= ~(SDIO_CR2_SDCLKEN_Msk | SDIO_CR2_SDCLKDIV_Msk); + SDIO->CR2 |= (1 << SDIO_CR2_SDCLKEN_Pos) | + (calcSDCLKDiv(SD_CLK_20MHz) << SDIO_CR2_SDCLKDIV_Pos); //ʼɣSDCLKл + + + SDIO_SendCmd(SD_CMD_SEL_DESEL_CARD, SD_cardInfo.RCA << 16, SD_RESP_32b_busy, &resp, 0, 0); //CMD7: ѡпStandyģʽTransferģʽ + + + SDIO_SendCmd(SD_CMD_APP_CMD, SD_cardInfo.RCA << 16, SD_RESP_32b, &resp, 0, 0); + + SDIO_SendCmd(SD_CMD_APP_SD_SET_BUSWIDTH, SD_BUSWIDTH_4b, SD_RESP_32b, &resp, 0, 0); //л4λģʽ + + SDIO->CR1 |= (1 << SDIO_CR1_4BIT_Pos); + + + SDIO_SendCmd(SD_CMD_SET_BLOCKLEN, 512, SD_RESP_32b, &resp, 0, 0); //̶Сλ512ֽ + + SDIO->BLK = 512; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* : SDIO_BlockWrite() +* ˵: SDд +* : uint32_t block_addr SDַÿ512ֽ +* uint32_t buff[] Ҫд +* : +* ע: +******************************************************************************************************************************************/ +void SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]) +{ + uint32_t i, resp, addr; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; + else addr = block_addr * 512; + + SDIO_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 0); + + while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0); + SDIO->IF = SDIO_IF_BUFWRRDY_Msk; + + for (i = 0; i < 512 / 4; i++) SDIO->DATA = buff[i]; + + SDIO->IF = SDIO_IF_TRXDONE_Msk; //?? + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0); + SDIO->IF = SDIO_IF_TRXDONE_Msk; +} + +/****************************************************************************************************************************************** +* : SDIO_BlockRead() +* ˵: SD +* : uint32_t block_addr SDַÿ512ֽ +* uint32_t buff[] +* : +* ע: +******************************************************************************************************************************************/ +void SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]) +{ + uint32_t i, resp, addr; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; + else addr = block_addr * 512; + + SDIO_SendCmd(SD_CMD_READ_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 1); + + while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0); + SDIO->IF = SDIO_IF_BUFRDRDY_Msk; + + for (i = 0; i < 512 / 4; i++) buff[i] = SDIO->DATA; + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0); + SDIO->IF = SDIO_IF_TRXDONE_Msk; +} + +/****************************************************************************************************************************************** +* : SDIO_SendCmd() +* ˵: SDIOSD +* : uint32_t cmd +* uint32_t arg +* uint32_t resp_type ӦͣȡֵSD_RESP_NOSD_RESP_32bSD_RESP_128bSD_RESP_32b_busy +* uint32_t *resp_data Ӧ +* uint32_t have_data Ƿݴ +* uint32_t data_read 1 SD 0 дSD +* : +* ע: +******************************************************************************************************************************************/ +void SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read) +{ + SDIO->ARG = arg; + SDIO->CMD = (cmd << SDIO_CMD_CMDINDX_Pos) | + (0 << SDIO_CMD_CMDTYPE_Pos) | + (have_data << SDIO_CMD_HAVEDATA_Pos) | + (0 << SDIO_CMD_IDXCHECK_Pos) | + (0 << SDIO_CMD_CRCCHECK_Pos) | + (resp_type << SDIO_CMD_RESPTYPE_Pos) | + (0 << SDIO_CMD_MULTBLK_Pos) | + (data_read << SDIO_CMD_DIRREAD_Pos) | + (0 << SDIO_CMD_BLKCNTEN_Pos); + + while ((SDIO->IF & SDIO_IF_CMDDONE_Msk) == 0); + SDIO->IF = SDIO_IF_CMDDONE_Msk; + + if (resp_type == SD_RESP_32b) + { + resp_data[0] = SDIO->RESP[0]; + } + else if (resp_type == SD_RESP_128b) + { + //ĴнCID/CSD[127-8]δRESP3-0[119-0]λCRC + //ʱ˳򣬽CID/CSD[127-8]resp_data0-3[127-8]8λ0x00 + resp_data[0] = (SDIO->RESP[3] << 8) + ((SDIO->RESP[2] >> 24) & 0xFF); + resp_data[1] = (SDIO->RESP[2] << 8) + ((SDIO->RESP[1] >> 24) & 0xFF); + resp_data[2] = (SDIO->RESP[1] << 8) + ((SDIO->RESP[0] >> 24) & 0xFF); + resp_data[3] = (SDIO->RESP[0] << 8) + 0x00; + } +} + + +void parseCID(uint32_t CID_Tab[4]) +{ + uint8_t tmp = 0; + + /*!< Byte 0 */ + tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ManufacturerID = tmp; + + /*!< Byte 1 */ + tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.OEM_AppliID = tmp << 8; + + /*!< Byte 2 */ + tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8); + SD_cardInfo.SD_cid.OEM_AppliID |= tmp; + + /*!< Byte 3 */ + tmp = (uint8_t)(CID_Tab[0] & 0x000000FF); + SD_cardInfo.SD_cid.ProdName1 = tmp << 24; + + /*!< Byte 4 */ + tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ProdName1 |= tmp << 16; + + /*!< Byte 5 */ + tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.ProdName1 |= tmp << 8; + + /*!< Byte 6 */ + tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8); + SD_cardInfo.SD_cid.ProdName1 |= tmp; + + /*!< Byte 7 */ + tmp = (uint8_t)(CID_Tab[1] & 0x000000FF); + SD_cardInfo.SD_cid.ProdName2 = tmp; + + /*!< Byte 8 */ + tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ProdRev = tmp; + + /*!< Byte 9 */ + tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.ProdSN = tmp << 24; + + /*!< Byte 10 */ + tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8); + SD_cardInfo.SD_cid.ProdSN |= tmp << 16; + + /*!< Byte 11 */ + tmp = (uint8_t)(CID_Tab[2] & 0x000000FF); + SD_cardInfo.SD_cid.ProdSN |= tmp << 8; + + /*!< Byte 12 */ + tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24); + SD_cardInfo.SD_cid.ProdSN |= tmp; + + /*!< Byte 13 */ + tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16); + SD_cardInfo.SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; + SD_cardInfo.SD_cid.ManufactDate = (tmp & 0x0F) << 8; + + /*!< Byte 14 */ + tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8); + SD_cardInfo.SD_cid.ManufactDate |= tmp; +} + +void parseCSD(uint32_t CSD_Tab[4]) +{ + uint8_t tmp = 0; + + /*!< Byte 0 */ + tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.CSDStruct = (tmp & 0xC0) >> 6; + SD_cardInfo.SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2; + SD_cardInfo.SD_csd.Reserved1 = tmp & 0x03; + + /*!< Byte 1 */ + tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.TAAC = tmp; + + /*!< Byte 2 */ + tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.NSAC = tmp; + + /*!< Byte 3 */ + tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF); + SD_cardInfo.SD_csd.MaxBusClkFrec = tmp; + + /*!< Byte 4 */ + tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.CardComdClasses = tmp << 4; + + /*!< Byte 5 */ + tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4; + SD_cardInfo.SD_csd.RdBlockLen = tmp & 0x0F; + + /*!< Byte 6 */ + tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.PartBlockRead = (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6; + SD_cardInfo.SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5; + SD_cardInfo.SD_csd.DSRImpl = (tmp & 0x10) >> 4; + SD_cardInfo.SD_csd.Reserved2 = 0; /*!< Reserved */ + + if ((SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || + (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) + { + SD_cardInfo.SD_csd.DeviceSize = (tmp & 0x03) << 10; + + /*!< Byte 7 */ + tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); + SD_cardInfo.SD_csd.DeviceSize |= (tmp) << 2; + + /*!< Byte 8 */ + tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; + + SD_cardInfo.SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; + SD_cardInfo.SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); + + /*!< Byte 9 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; + SD_cardInfo.SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; + SD_cardInfo.SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; + /*!< Byte 10 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; + + SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1) ; + SD_cardInfo.CardCapacity *= (1 << (SD_cardInfo.SD_csd.DeviceSizeMul + 2)); + SD_cardInfo.CardBlockSize = 1 << (SD_cardInfo.SD_csd.RdBlockLen); + SD_cardInfo.CardCapacity *= SD_cardInfo.CardBlockSize; + } + else if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + /*!< Byte 7 */ + tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); + SD_cardInfo.SD_csd.DeviceSize = (tmp & 0x3F) << 16; + + /*!< Byte 8 */ + tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); + + SD_cardInfo.SD_csd.DeviceSize |= (tmp << 8); + + /*!< Byte 9 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); + + SD_cardInfo.SD_csd.DeviceSize |= (tmp); + + /*!< Byte 10 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); + + SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1) * 512 * 1024; + SD_cardInfo.CardBlockSize = 512; + } + + SD_cardInfo.SD_csd.EraseGrSize = (tmp & 0x40) >> 6; + SD_cardInfo.SD_csd.EraseGrMul = (tmp & 0x3F) << 1; + + /*!< Byte 11 */ + tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF); + SD_cardInfo.SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.WrProtectGrSize = (tmp & 0x7F); + + /*!< Byte 12 */ + tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24); + SD_cardInfo.SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.ManDeflECC = (tmp & 0x60) >> 5; + SD_cardInfo.SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; + SD_cardInfo.SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; + + /*!< Byte 13 */ + tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16); + SD_cardInfo.SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; + SD_cardInfo.SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; + SD_cardInfo.SD_csd.Reserved3 = 0; + SD_cardInfo.SD_csd.ContentProtectAppli = (tmp & 0x01); + + /*!< Byte 14 */ + tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8); + SD_cardInfo.SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; + SD_cardInfo.SD_csd.CopyFlag = (tmp & 0x40) >> 6; + SD_cardInfo.SD_csd.PermWrProtect = (tmp & 0x20) >> 5; + SD_cardInfo.SD_csd.TempWrProtect = (tmp & 0x10) >> 4; + SD_cardInfo.SD_csd.FileFormat = (tmp & 0x0C) >> 2; + SD_cardInfo.SD_csd.ECC = (tmp & 0x03); +} + +uint32_t calcSDCLKDiv(uint32_t freq_sel) +{ + uint32_t regdiv = 0; + uint32_t clkdiv = 0; + + if (((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos) == 1) + clkdiv = SystemCoreClock / 2 / ((freq_sel == SD_CLK_400KHz) ? 300000 : 15000000); + else if (((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos) == 2) + clkdiv = SystemCoreClock / 4 / ((freq_sel == SD_CLK_400KHz) ? 300000 : 15000000); + + if (clkdiv > 128) regdiv = 0x80; + else if (clkdiv > 64) regdiv = 0x40; + else if (clkdiv > 32) regdiv = 0x20; + else if (clkdiv > 16) regdiv = 0x10; + else if (clkdiv > 8) regdiv = 0x08; + else if (clkdiv > 4) regdiv = 0x04; + else if (clkdiv > 2) regdiv = 0x02; + else if (clkdiv > 1) regdiv = 0x01; + else regdiv = 0x00; + + return regdiv; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h new file mode 100644 index 00000000000..1df6602159c --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h @@ -0,0 +1,139 @@ +#ifndef __SWM320_SDIO_H__ +#define __SWM320_SDIO_H__ + + +#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) +#define SD_CMD_SEND_OP_COND ((uint8_t)1) +#define SD_CMD_ALL_SEND_CID ((uint8_t)2) +#define SD_CMD_SET_REL_ADDR ((uint8_t)3) +#define SD_CMD_SET_DSR ((uint8_t)4) +#define SD_CMD_HS_SWITCH ((uint8_t)6) +#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) +#define SD_CMD_SEND_IF_COND ((uint8_t)8) +#define SD_CMD_SEND_CSD ((uint8_t)9) +#define SD_CMD_SEND_CID ((uint8_t)10) +#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) +#define SD_CMD_SEND_STATUS ((uint8_t)13) +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) +#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) +#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) +#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) +#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) +#define SD_CMD_PROG_CID ((uint8_t)26) +#define SD_CMD_PROG_CSD ((uint8_t)27) +#define SD_CMD_APP_CMD ((uint8_t)55) + +/*Following commands are SD Card Specific commands. + SDIO_APP_CMD should be sent before sending these commands. */ +#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) +#define SD_CMD_SD_APP_STAUS ((uint8_t)13) +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) +#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) +#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) +#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) +#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) + + +#define SD_RESP_NO 0 //0 Ӧ +#define SD_RESP_32b 2 //2 32λӦ +#define SD_RESP_128b 1 //1 128λӦ +#define SD_RESP_32b_busy 3 //3 32λӦcheck Busy after response + +#define SD_CLK_400KHz 0 +#define SD_CLK_20MHz 1 + +#define SD_BUSWIDTH_1b 0 +#define SD_BUSWIDTH_4b 2 + +#define SD_RES_OK 0 +#define SD_RES_ERR 1 + + +typedef struct +{ + __IO uint8_t CSDStruct; // CSD structure + __IO uint8_t SysSpecVersion; // System specification version + __IO uint8_t Reserved1; // Reserved + __IO uint8_t TAAC; // Data read access-time 1 + __IO uint8_t NSAC; // Data read access-time 2 in CLK cycles + __IO uint8_t MaxBusClkFrec; // Max. bus clock frequency + __IO uint16_t CardComdClasses; //< Card command classes + __IO uint8_t RdBlockLen; // Max. read data block length + __IO uint8_t PartBlockRead; // Partial blocks for read allowed + __IO uint8_t WrBlockMisalign; // Write block misalignment + __IO uint8_t RdBlockMisalign; // Read block misalignment + __IO uint8_t DSRImpl; // DSR implemented + __IO uint8_t Reserved2; // Reserved + __IO uint32_t DeviceSize; // Device Size + __IO uint8_t MaxRdCurrentVDDMin; // Max. read current @ VDD min + __IO uint8_t MaxRdCurrentVDDMax; // Max. read current @ VDD max + __IO uint8_t MaxWrCurrentVDDMin; // Max. write current @ VDD min + __IO uint8_t MaxWrCurrentVDDMax; // Max. write current @ VDD max + __IO uint8_t DeviceSizeMul; // Device size multiplier + __IO uint8_t EraseGrSize; // Erase group size + __IO uint8_t EraseGrMul; // Erase group size multiplier + __IO uint8_t WrProtectGrSize; // Write protect group size + __IO uint8_t WrProtectGrEnable; // Write protect group enable + __IO uint8_t ManDeflECC; // Manufacturer default ECC + __IO uint8_t WrSpeedFact; // Write speed factor + __IO uint8_t MaxWrBlockLen; // Max. write data block length + __IO uint8_t WriteBlockPaPartial; // Partial blocks for write allowed + __IO uint8_t Reserved3; // Reserded + __IO uint8_t ContentProtectAppli; // Content protection application + __IO uint8_t FileFormatGrouop; // File format group + __IO uint8_t CopyFlag; // Copy flag (OTP) + __IO uint8_t PermWrProtect; // Permanent write protection + __IO uint8_t TempWrProtect; // Temporary write protection + __IO uint8_t FileFormat; // File Format + __IO uint8_t ECC; // ECC code +} SD_CSD; + +typedef struct +{ + __IO uint8_t ManufacturerID; // ManufacturerID + __IO uint16_t OEM_AppliID; // OEM/Application ID + __IO uint32_t ProdName1; // Product Name part1 + __IO uint8_t ProdName2; // Product Name part2 + __IO uint8_t ProdRev; // Product Revision + __IO uint32_t ProdSN; // Product Serial Number + __IO uint8_t Reserved1; // Reserved1 + __IO uint16_t ManufactDate; // Manufacturing Date +} SD_CID; + + +#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) +#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) +#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) +#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) +#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) +#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) +#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) +#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) + + +typedef struct +{ + SD_CSD SD_csd; + SD_CID SD_cid; + uint64_t CardCapacity; // Card Capacity + uint32_t CardBlockSize; // Card Block Size + uint16_t RCA; + uint8_t CardType; +} SD_CardInfo; + + +extern SD_CardInfo SD_cardInfo; + +uint32_t SDIO_Init(void); +void SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]); +void SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]); + +void SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read); + +void parseCID(uint32_t CID_Tab[4]); +void parseCSD(uint32_t CID_Tab[4]); + +uint32_t calcSDCLKDiv(uint32_t freq_sel); + +#endif //__SWM320_SDIO_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c new file mode 100644 index 00000000000..f07af4ee515 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c @@ -0,0 +1,58 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_sdram.c +* ˵: SWM320ƬSDRAM +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_sdram.h" + +/****************************************************************************************************************************************** +* : SDRAM_Init() +* ˵: SDRAMʼ +* : SDRAM_InitStructure * initStruct NOR Flash趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void SDRAM_Init(SDRAM_InitStructure *initStruct) +{ + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + SYS->CLKDIV &= ~SYS_CLKDIV_SDRAM_Msk; + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDRAM_Pos); //2Ƶ + + SDRAMC->CR0 = (2 << SDRAMC_CR0_BURSTLEN_Pos) | //2 Burst LengthΪ4 + (2 << SDRAMC_CR0_CASDELAY_Pos); + + SDRAMC->CR1 = (initStruct->CellSize << SDRAMC_CR1_CELLSIZE_Pos) | + ((initStruct->CellWidth == 16 ? 0 : 1) << SDRAMC_CR1_CELL32BIT_Pos) | + (initStruct->CellBank << SDRAMC_CR1_BANK_Pos) | + ((initStruct->DataWidth == 16 ? 0 : 1) << SDRAMC_CR1_32BIT_Pos) | + (7 << SDRAMC_CR1_TMRD_Pos) | + (3 << SDRAMC_CR1_TRRD_Pos) | + (7 << SDRAMC_CR1_TRAS_Pos) | + (8 << SDRAMC_CR1_TRC_Pos) | + (3 << SDRAMC_CR1_TRCD_Pos) | + (3 << SDRAMC_CR1_TRP_Pos); + + SDRAMC->LATCH = 0x02; + + SDRAMC->REFRESH = (1 << SDRAMC_REFRESH_EN_Pos) | + (0x0FA << SDRAMC_REFRESH_RATE_Pos); + + while (SDRAMC->REFDONE == 0); +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h new file mode 100644 index 00000000000..c10d82fc12c --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h @@ -0,0 +1,23 @@ +#ifndef __SWM320_SDRAM_H__ +#define __SWM320_SDRAM_H__ + +typedef struct +{ + uint8_t DataWidth; // 1632 + + uint8_t CellSize; // SDRAM + uint8_t CellBank; // SDRAMмbank + uint8_t CellWidth; // SDRAMλ 1632 +} SDRAM_InitStructure; + +#define SDRAM_CELLSIZE_16Mb 3 +#define SDRAM_CELLSIZE_64Mb 0 +#define SDRAM_CELLSIZE_128Mb 1 +#define SDRAM_CELLSIZE_256Mb 2 + +#define SDRAM_CELLBANK_2 0 +#define SDRAM_CELLBANK_4 1 + +void SDRAM_Init(SDRAM_InitStructure *initStruct); + +#endif //__SWM320_SDRAM_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c new file mode 100644 index 00000000000..6c88ada2244 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c @@ -0,0 +1,447 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_spi.c +* ˵: SWM320ƬSPI +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_spi.h" + + +/****************************************************************************************************************************************** +* : SPI_Init() +* ˵: SPIͬнӿڳʼ֡趨ʱ趨ٶ趨ж趨FIFO趨 +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* SPI_InitStructure * initStruct SPI趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct) +{ + switch ((uint32_t)SPIx) + { + case ((uint32_t)SPI0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); + break; + + case ((uint32_t)SPI1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); //SPI0ʹͬһλʱʹ + break; + } + + SPI_Close(SPIx); //һЩؼĴֻSPIرʱ + + SPIx->CTRL &= ~(SPI_CTRL_FFS_Msk | SPI_CTRL_CPHA_Msk | SPI_CTRL_CPOL_Msk | + SPI_CTRL_SIZE_Msk | SPI_CTRL_MSTR_Msk | SPI_CTRL_CLKDIV_Msk | SPI_CTRL_SSN_H_Msk); + SPIx->CTRL |= (initStruct->FrameFormat << SPI_CTRL_FFS_Pos) | + (initStruct->SampleEdge << SPI_CTRL_CPHA_Pos) | + (initStruct->IdleLevel << SPI_CTRL_CPOL_Pos) | + ((initStruct->WordSize - 1) << SPI_CTRL_SIZE_Pos) | + (initStruct->Master << SPI_CTRL_MSTR_Pos) | + (initStruct->clkDiv << SPI_CTRL_CLKDIV_Pos) | + (0 << SPI_CTRL_SSN_H_Pos); + + SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); //жϱ־ + SPIx->IE &= ~(SPI_IE_RFHF_Msk | SPI_IE_TFHF_Msk | SPI_IE_FTC_Msk); + SPIx->IE |= (initStruct->RXHFullIEn << SPI_IE_RFHF_Pos) | + (initStruct->TXEmptyIEn << SPI_IE_TFHF_Pos) | + (initStruct->TXCompleteIEn << SPI_IE_FTC_Pos); + + switch ((uint32_t)SPIx) + { + case ((uint32_t)SPI0): + if (initStruct->RXHFullIEn | initStruct->TXEmptyIEn | initStruct->TXCompleteIEn) + { + NVIC_EnableIRQ(SPI0_IRQn); + } + else + { + NVIC_DisableIRQ(SPI0_IRQn); + } + break; + + case ((uint32_t)SPI1): + if (initStruct->RXHFullIEn | initStruct->TXEmptyIEn | initStruct->TXCompleteIEn) + { + NVIC_EnableIRQ(SPI1_IRQn); + } + else + { + NVIC_DisableIRQ(SPI1_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : SPI_Open() +* ˵: SPI򿪣շ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Open(SPI_TypeDef *SPIx) +{ + SPIx->CTRL |= (0x01 << SPI_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_Close() +* ˵: SPIرգֹշ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Close(SPI_TypeDef *SPIx) +{ + SPIx->CTRL &= ~SPI_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* : SPI_Read() +* ˵: ȡһ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t ȡ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_Read(SPI_TypeDef *SPIx) +{ + return SPIx->DATA; +} + +/****************************************************************************************************************************************** +* : SPI_Write() +* ˵: дһ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* uint32_t Ҫд +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Write(SPI_TypeDef *SPIx, uint32_t data) +{ + SPIx->DATA = data; +} + +/****************************************************************************************************************************************** +* : SPI_WriteWithWait() +* ˵: дһݲȴȫͳȥ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1SPI1 +* uint32_t Ҫд +* : +* ע: +******************************************************************************************************************************************/ +void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data) +{ + SPIx->STAT |= (1 << SPI_STAT_WTC_Pos); + + SPIx->DATA = data; + + while ((SPIx->STAT & SPI_STAT_WTC_Msk) == 0); +} + +/****************************************************************************************************************************************** +* : SPI_ReadWrite() +* ˵: һݣط͹нյ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* uint32_t data Ҫ͵ +* : uint32_t յ +* ע: ͬһSPIģ飬˺ӦSPI_Write()ãΪSPI_Write()SPI_STAT_RFNE״̬ +******************************************************************************************************************************************/ +uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data) +{ + SPIx->DATA = data; + while (!(SPIx->STAT & SPI_STAT_RFNE_Msk)); + + return SPIx->DATA; +} + +/****************************************************************************************************************************************** +* : SPI_IsRXEmpty() +* ˵: FIFOǷգԼSPI_Read() +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx) +{ + return (SPIx->STAT & SPI_STAT_RFNE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : SPI_IsTXFull() +* ˵: FIFOǷԼSPI_Write() +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFO +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx) +{ + return (SPIx->STAT & SPI_STAT_TFNF_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : SPI_IsTXEmpty() +* ˵: FIFOǷ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx) +{ + return (SPIx->STAT & SPI_STAT_TFE_Msk) ? 1 : 0; +} + + +/****************************************************************************************************************************************** +* : SPI_INTRXHalfFullEn() +* ˵: FIFOжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_RFHF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXHalfFullDis() +* ˵: FIFOжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_RFHF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXHalfFullStat() +* ˵: FIFOж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFOﵽ 0 FIFOδﵽ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_RFHF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTRXFullEn() +* ˵: FIFOжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXFullEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_RFF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXFullDis() +* ˵: FIFOжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXFullDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_RFF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXFullStat() +* ˵: FIFOж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFOδ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_RFF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTRXOverflowEn() +* ˵: FIFOжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_RFOVF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXOverflowDis() +* ˵: FIFOжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_RFOVF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXOverflowClr() +* ˵: FIFOжϱ־ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTRXOverflowStat() +* ˵: FIFOж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFOδ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_RFOVF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTTXHalfFullEn() +* ˵: FIFOжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_TFHF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXHalfFullDis() +* ˵: FIFOжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_TFHF_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXHalfFullStat() +* ˵: FIFOж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFOﵽ 0 FIFOδﵽ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_TFHF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTTXEmptyEn() +* ˵: FIFOжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_TFE_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXEmptyDis() +* ˵: FIFOжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_TFE_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXEmptyStat() +* ˵: FIFOж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_TFE_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : SPI_INTTXCompleteEn() +* ˵: FIFOҷλĴжʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_FTC_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXCompleteDis() +* ˵: FIFOҷλĴжϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_FTC_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXCompleteClr() +* ˵: FIFOҷλĴж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_FTC_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_INTTXCompleteStat() +* ˵: FIFOҷλĴж״̬ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 +* : uint32_t 1 FIFOҷλĴ 0 FIFOλĴǿ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_FTC_Msk) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h new file mode 100644 index 00000000000..3230c4a774f --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h @@ -0,0 +1,75 @@ +#ifndef __SWM320_SPI_H__ +#define __SWM320_SPI_H__ + +typedef struct +{ + uint8_t FrameFormat; //֡ʽSPI_FORMAT_SPISPI_FORMAT_TI_SSI + uint8_t SampleEdge; //SPI֡ʽ£ѡݲأSPI_FIRST_EDGESPI_SECOND_EDGE + uint8_t IdleLevel; //SPI֡ʽ£ѡʱݴʱʱߵĵƽSPI_LOW_LEVELSPI_HIGH_LEVEL + uint8_t WordSize; //ֳ, Чֵ4-16 + uint8_t Master; //1 ģʽ 0 ӻģʽ + uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDivЧֵSPI_CLKDIV_4SPI_CLKDIV_8... ... SPI_CLKDIV_512 + + uint8_t RXHFullIEn; //FIFOжʹ + uint8_t TXEmptyIEn; //FIFO жʹ + uint8_t TXCompleteIEn; //FIFO ҷλĴжʹ +} SPI_InitStructure; + +#define SPI_FORMAT_SPI 0 //Motorola SPI ʽ +#define SPI_FORMAT_TI_SSI 1 //TI SSI ʽ + +#define SPI_FIRST_EDGE 0 //һʱؿʼ +#define SPI_SECOND_EDGE 1 //ڶʱؿʼ + +#define SPI_LOW_LEVEL 0 //ʱʱֵ߱͵ƽ +#define SPI_HIGH_LEVEL 1 //ʱʱָ߱ߵƽ + +#define SPI_CLKDIV_4 0 +#define SPI_CLKDIV_8 1 +#define SPI_CLKDIV_16 2 +#define SPI_CLKDIV_32 3 +#define SPI_CLKDIV_64 4 +#define SPI_CLKDIV_128 5 +#define SPI_CLKDIV_256 6 +#define SPI_CLKDIV_512 7 + + + +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct); //SPIʼ +void SPI_Open(SPI_TypeDef *SPIx); //SPI򿪣շ +void SPI_Close(SPI_TypeDef *SPIx); //SPIرգֹշ + +uint32_t SPI_Read(SPI_TypeDef *SPIx); +void SPI_Write(SPI_TypeDef *SPIx, uint32_t data); +void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data); +uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data); + +uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx); //FIFOǷգԼSPI_Read() +uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx); //FIFOǷԼSPI_Write() +uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx); //FIFOǷ + + +void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx); +void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx); +uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx); +void SPI_INTRXFullEn(SPI_TypeDef *SPIx); +void SPI_INTRXFullDis(SPI_TypeDef *SPIx); +uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx); +void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx); +void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx); +void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx); +uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx); + +void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx); +void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx); +uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx); +void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx); +void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx); +uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx); +void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx); +void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx); +void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx); +uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx); + + +#endif //__SWM320_SPI_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c new file mode 100644 index 00000000000..769cc2e7790 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c @@ -0,0 +1,381 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_timr.c +* ˵: SWM320Ƭļ/ʱ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_timr.h" + + +/****************************************************************************************************************************************** +* : TIMR_Init() +* ˵: TIMRʱ/ʼ +* : TIMR_TypeDef * TIMRx ָҪõĶʱЧֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* uint32_t mode TIMR_MODE_TIMER ʱģʽ TIMR_MODE_COUNTER ģʽ +* uint32_t period ʱ/ +* uint32_t int_en жʹ +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en) +{ + SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos); + + TIMR_Stop(TIMRx); //һЩؼĴֻڶʱֹͣʱ + + TIMRx->CTRL &= ~TIMR_CTRL_CLKSRC_Msk; + TIMRx->CTRL |= mode << TIMR_CTRL_CLKSRC_Pos; + + TIMRx->LDVAL = period; + + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IF = (1 << TIMRG_IF_TIMR0_Pos); //ʹжǰжϱ־ + TIMRG->IE &= ~TIMRG_IE_TIMR0_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR0_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR0_IRQn); + break; + + case ((uint32_t)TIMR1): + TIMRG->IF = (1 << TIMRG_IF_TIMR1_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR1_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR1_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR1_IRQn); + break; + + case ((uint32_t)TIMR2): + TIMRG->IF = (1 << TIMRG_IF_TIMR2_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR2_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR2_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR2_IRQn); + break; + + case ((uint32_t)TIMR3): + TIMRG->IF = (1 << TIMRG_IF_TIMR3_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR3_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR3_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR3_IRQn); + break; + + case ((uint32_t)TIMR4): + TIMRG->IF = (1 << TIMRG_IF_TIMR4_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR4_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR4_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR4_IRQn); + break; + + case ((uint32_t)TIMR5): + TIMRG->IF = (1 << TIMRG_IF_TIMR5_Pos); + TIMRG->IE &= ~TIMRG_IE_TIMR5_Msk; + TIMRG->IE |= (int_en << TIMRG_IE_TIMR5_Pos); + + if (int_en) NVIC_EnableIRQ(TIMR5_IRQn); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_Start() +* ˵: ʱӳʼֵʼʱ/ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Start(TIMR_TypeDef *TIMRx) +{ + TIMRx->CTRL |= TIMR_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* : TIMR_Stop() +* ˵: ֹͣʱ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Stop(TIMR_TypeDef *TIMRx) +{ + TIMRx->CTRL &= ~TIMR_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* : TIMR_Halt() +* ˵: ͣʱֲֵ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Halt(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->HALT |= (0x01 << TIMRG_HALT_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_Resume() +* ˵: ָʱͣ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Resume(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->HALT &= ~(0x01 << TIMRG_HALT_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_SetPeriod() +* ˵: öʱ/ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* uint32_t period ʱ/ +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period) +{ + TIMRx->LDVAL = period; +} + +/****************************************************************************************************************************************** +* : TIMR_GetPeriod() +* ˵: ȡʱ/ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : uint32_t ǰʱ/ +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx) +{ + return TIMRx->LDVAL; +} + +/****************************************************************************************************************************************** +* : TIMR_GetCurValue() +* ˵: ȡǰֵ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : uint32_t ǰֵ +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx) +{ + return TIMRx->CVAL; +} + +/****************************************************************************************************************************************** +* : TIMR_INTEn() +* ˵: ʹж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_INTEn(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR0_Pos); + NVIC_EnableIRQ(TIMR0_IRQn); + break; + + case ((uint32_t)TIMR1): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR1_Pos); + NVIC_EnableIRQ(TIMR1_IRQn); + break; + + case ((uint32_t)TIMR2): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR2_Pos); + NVIC_EnableIRQ(TIMR2_IRQn); + break; + + case ((uint32_t)TIMR3): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR3_Pos); + NVIC_EnableIRQ(TIMR3_IRQn); + break; + + case ((uint32_t)TIMR4): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR4_Pos); + NVIC_EnableIRQ(TIMR4_IRQn); + break; + + case ((uint32_t)TIMR5): + TIMRG->IE |= (0x01 << TIMRG_IE_TIMR5_Pos); + NVIC_EnableIRQ(TIMR5_IRQn); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_INTDis() +* ˵: ж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_INTDis(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->IE &= ~(0x01 << TIMRG_IE_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_INTClr() +* ˵: жϱ־ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_INTClr(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR2_Pos); + break; + + case ((uint32_t)TIMR3): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR3_Pos); + break; + + case ((uint32_t)TIMR4): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR4_Pos); + break; + + case ((uint32_t)TIMR5): + TIMRG->IF = (0x01 << TIMRG_IF_TIMR5_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_INTStat() +* ˵: ȡж״̬ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 +* : uint32_t 0 TIMRxδж 1 TIMRxж +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx) +{ + switch ((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + return (TIMRG->IF & TIMRG_IF_TIMR0_Msk) ? 1 : 0; + + case ((uint32_t)TIMR1): + return (TIMRG->IF & TIMRG_IF_TIMR1_Msk) ? 1 : 0; + + case ((uint32_t)TIMR2): + return (TIMRG->IF & TIMRG_IF_TIMR2_Msk) ? 1 : 0; + + case ((uint32_t)TIMR3): + return (TIMRG->IF & TIMRG_IF_TIMR3_Msk) ? 1 : 0; + + case ((uint32_t)TIMR4): + return (TIMRG->IF & TIMRG_IF_TIMR4_Msk) ? 1 : 0; + + case ((uint32_t)TIMR5): + return (TIMRG->IF & TIMRG_IF_TIMR5_Msk) ? 1 : 0; + } + + return 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h new file mode 100644 index 00000000000..f92c0eaa735 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h @@ -0,0 +1,23 @@ +#ifndef __SWM320_TIMR_H__ +#define __SWM320_TIMR_H__ + +#define TIMR_MODE_TIMER 0 +#define TIMR_MODE_COUNTER 1 + +void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en); //ʱ/ʼ +void TIMR_Start(TIMR_TypeDef *TIMRx); //ʱӳʼֵʼʱ/ +void TIMR_Stop(TIMR_TypeDef *TIMRx); //ֹͣʱ +void TIMR_Halt(TIMR_TypeDef *TIMRx); //ͣʱֲֵ +void TIMR_Resume(TIMR_TypeDef *TIMRx); //ָʱͣ + +void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period); //öʱ/ +uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx); //ȡʱ/ +uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx); //ȡǰֵ + +void TIMR_INTEn(TIMR_TypeDef *TIMRx); //ʹж +void TIMR_INTDis(TIMR_TypeDef *TIMRx); //ж +void TIMR_INTClr(TIMR_TypeDef *TIMRx); //жϱ־ +uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx); //ȡж״̬ + + +#endif //__SWM320_TIMR_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c new file mode 100644 index 00000000000..46242efa014 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c @@ -0,0 +1,543 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_uart.c +* ˵: SWM320ƬUARTڹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: ûбдLINصĺ +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_uart.h" + + +/****************************************************************************************************************************************** +* : UART_Init() +* ˵: UARTڳʼ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* UART_InitStructure * initStruct UART趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct) +{ + switch ((uint32_t)UARTx) + { + case ((uint32_t)UART0): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART0_Pos); + break; + + case ((uint32_t)UART1): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART1_Pos); + break; + + case ((uint32_t)UART2): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART2_Pos); + break; + + case ((uint32_t)UART3): + SYS->CLKEN |= (0x01 << SYS_CLKEN_UART3_Pos); + break; + } + + UART_Close(UARTx); //һЩؼĴֻڴڹرʱ + + UARTx->CTRL |= (0x01 << UART_CTRL_BAUDEN_Pos); + UARTx->BAUD &= ~UART_BAUD_BAUD_Msk; + UARTx->BAUD |= ((SystemCoreClock / 16 / initStruct->Baudrate - 1) << UART_BAUD_BAUD_Pos); + + UARTx->CTRL &= ~(UART_CTRL_DATA9b_Msk | UART_CTRL_PARITY_Msk | UART_CTRL_STOP2b_Msk); + UARTx->CTRL |= (initStruct->DataBits << UART_CTRL_DATA9b_Pos) | + (initStruct->Parity << UART_CTRL_PARITY_Pos) | + (initStruct->StopBits << UART_CTRL_STOP2b_Pos); + + UARTx->FIFO &= ~(UART_FIFO_RXTHR_Msk | UART_FIFO_TXTHR_Msk); + UARTx->FIFO |= (initStruct->RXThreshold << UART_FIFO_RXTHR_Pos) | + (initStruct->TXThreshold << UART_FIFO_TXTHR_Pos); + + UARTx->CTRL &= ~UART_CTRL_TOTIME_Msk; + UARTx->CTRL |= (initStruct->TimeoutTime << UART_CTRL_TOTIME_Pos); + + UARTx->CTRL &= ~(UART_CTRL_RXIE_Msk | UART_CTRL_TXIE_Msk | UART_CTRL_TOIE_Msk); + UARTx->CTRL |= (initStruct->RXThresholdIEn << UART_CTRL_RXIE_Pos) | + (initStruct->TXThresholdIEn << UART_CTRL_TXIE_Pos) | + (initStruct->TimeoutIEn << UART_CTRL_TOIE_Pos); + + switch ((uint32_t)UARTx) + { + case ((uint32_t)UART0): + if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART0_IRQn); + } + else + { + NVIC_DisableIRQ(UART0_IRQn); + } + break; + + case ((uint32_t)UART1): + if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART1_IRQn); + } + else + { + NVIC_DisableIRQ(UART1_IRQn); + } + break; + + case ((uint32_t)UART2): + if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART2_IRQn); + } + else + { + NVIC_DisableIRQ(UART2_IRQn); + } + break; + + case ((uint32_t)UART3): + if (initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART3_IRQn); + } + else + { + NVIC_DisableIRQ(UART3_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : UART_Open() +* ˵: UARTڴ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_Open(UART_TypeDef *UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : UART_Close() +* ˵: UARTڹر +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_Close(UART_TypeDef *UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : UART_WriteByte() +* ˵: һֽ +* : UART_TypeDef * UARTx ָҪõUARTڣȡֵUART0UART1UART2UART3UART4 +* uint8_t data Ҫ͵ֽ +* : +* ע: +******************************************************************************************************************************************/ +void UART_WriteByte(UART_TypeDef *UARTx, uint8_t data) +{ + UARTx->DATA = data; +} + +/****************************************************************************************************************************************** +* : UART_ReadByte() +* ˵: ȡһֽݣָǷValid +* : UART_TypeDef * UARTx ָҪõUARTڣȡֵUART0UART1UART2UART3UART4 +* uint32_t * data յ +* : uint32_t 0 ޴ UART_ERR_PARITY żУ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data) +{ + uint32_t reg = UARTx->DATA; + + *data = (reg & UART_DATA_DATA_Msk); + + if (reg & UART_DATA_PAERR_Msk) return UART_ERR_PARITY; + + return 0; +} + +/****************************************************************************************************************************************** +* : UART_IsTXBusy() +* ˵: UARTǷڷ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 UARTڷ 0 ѷ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_IsTXBusy(UART_TypeDef *UARTx) +{ + return (UARTx->CTRL & UART_CTRL_TXIDLE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : UART_IsRXFIFOEmpty() +* ˵: FIFOǷΪգ˵ݿԶȡ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx) +{ + return (UARTx->CTRL & UART_CTRL_RXNE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : UART_IsTXFIFOFull() +* ˵: FIFOǷΪԼд +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 FIFO 0 FIFO +* ע: +******************************************************************************************************************************************/ +uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx) +{ + return (UARTx->CTRL & UART_CTRL_TXFF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_SetBaudrate() +* ˵: ò +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t baudrate ҪõIJ +* : +* ע: ҪڴڹʱIJʣʹô˺ǰȵUART_Close()رմ +******************************************************************************************************************************************/ +void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate) +{ + UARTx->BAUD &= ~UART_BAUD_BAUD_Msk; + UARTx->BAUD |= ((SystemCoreClock / 16 / baudrate) << UART_BAUD_BAUD_Pos); +} + +/****************************************************************************************************************************************** +* : UART_GetBaudrate() +* ˵: ѯ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t ǰ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_GetBaudrate(UART_TypeDef *UARTx) +{ + return (UARTx->BAUD & UART_BAUD_BAUD_Msk); +} + +/****************************************************************************************************************************************** +* : UART_CTSConfig() +* ˵: UART CTS +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t enable 1 ʹCTS 0 ֹCTS +* uint32_t polarity 0 CTSΪͱʾԷ 1 CTSΪ߱ʾԷ +* : +* ע: +******************************************************************************************************************************************/ +void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity) +{ + UARTx->CTSCR &= ~(UART_CTSCR_EN_Msk | UART_CTSCR_POL_Msk); + UARTx->CTSCR |= (enable << UART_CTSCR_EN_Pos) | + (polarity << UART_CTSCR_POL_Pos); +} + +/****************************************************************************************************************************************** +* : UART_CTSLineState() +* ˵: UART CTSߵǰ״̬ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 0 CTSߵǰΪ͵ƽ 1 CTSߵǰΪߵƽ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_CTSLineState(UART_TypeDef *UARTx) +{ + return (UARTx->CTSCR & UART_CTSCR_STAT_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_RTSConfig() +* ˵: UART RTS +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t enable 1 ʹRTS 0 ֹRTS +* uint32_t polarity 0 RTSͱʾԽ 1 RTS߱ʾԽ +* uint32_t threshold RTSصĴֵȡֵUART_RTS_1BYTEUART_RTS_2BYTEUART_RTS_4BYTEUART_RTS_6BYTE +* : +* ע: +******************************************************************************************************************************************/ +void UART_RTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold) +{ + UARTx->RTSCR &= ~(UART_RTSCR_EN_Msk | UART_RTSCR_POL_Msk | UART_RTSCR_THR_Msk); + UARTx->RTSCR |= (enable << UART_RTSCR_EN_Pos) | + (polarity << UART_RTSCR_POL_Pos) | + (threshold << UART_RTSCR_THR_Pos); +} + +/****************************************************************************************************************************************** +* : UART_RTSLineState() +* ˵: UART RTSߵǰ״̬ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 0 RTSߵǰΪ͵ƽ 1 RTSߵǰΪߵƽ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_RTSLineState(UART_TypeDef *UARTx) +{ + return (UARTx->RTSCR & UART_RTSCR_STAT_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_LINConfig() +* ˵: UART LIN +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t detectedIEn ⵽Breakжʹ +* uint32_t generatedIEn Breakжʹ +* : +* ע: +******************************************************************************************************************************************/ +void UART_LINConfig(UART_TypeDef *UARTx, uint32_t detectedIEn, uint32_t generatedIEn) +{ + UARTx->LINCR &= ~(UART_LINCR_BRKDETIE_Msk | UART_LINCR_GENBRKIE_Msk); + UARTx->LINCR |= (detectedIEn << UART_LINCR_BRKDETIE_Pos) | + (generatedIEn << UART_LINCR_GENBRKIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_LINGenerate() +* ˵: UART LIN/Break +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_LINGenerate(UART_TypeDef *UARTx) +{ + UARTx->LINCR |= (1 << UART_LINCR_GENBRK_Pos); +} + +/****************************************************************************************************************************************** +* : UART_LINIsDetected() +* ˵: UART LINǷ⵽Break +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 ⵽LIN Break 0 δ⵽LIN Break +* ע: +******************************************************************************************************************************************/ +uint32_t UART_LINIsDetected(UART_TypeDef *UARTx) +{ + return (UARTx->LINCR & UART_LINCR_BRKDETIE_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_LINIsGenerated() +* ˵: UART LIN BreakǷ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 LIN Break 0 LIN Breakδ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx) +{ + return (UARTx->LINCR & UART_LINCR_GENBRKIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_ABRStart() +* ˵: UART Զʼ⿪ʼ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t detectChar Զ⡢㲨ʵļַ +* 8λʱȡֵ0xFF0xFE0xF80x80ֱʾͷ뷢0xFF0xFE0xF80x80 +* 9λʱȡֵ0x1FF0x1FE0x1F80x180ֱʾͷ뷢0x1FF0x1FE0x1F80x180 +* : +* ע: ԶʼʱܿżУ +******************************************************************************************************************************************/ +void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar) +{ + uint32_t bits; + + if ((detectChar == 0xFF) || (detectChar == 0x1FF)) bits = 0; + else if ((detectChar == 0xFE) || (detectChar == 0x1FE)) bits = 1; + else if ((detectChar == 0xF8) || (detectChar == 0x1F8)) bits = 2; + else if ((detectChar == 0x80) || (detectChar == 0x180)) bits = 3; + else while (1); + + UARTx->BAUD &= ~(UART_BAUD_ABREN_Msk | UART_BAUD_ABRBIT_Msk); + UARTx->BAUD |= (1 << UART_BAUD_ABREN_Pos) | + (bits << UART_BAUD_ABRBIT_Pos); +} + +/****************************************************************************************************************************************** +* : UART_ABRIsDone() +* ˵: UART ԶǷ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 0 δ UART_ABR_RES_OK ɣҳɹ UART_ABR_RES_ERR ɣʧܡ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_ABRIsDone(UART_TypeDef *UARTx) +{ + if (UARTx->BAUD & UART_BAUD_ABREN_Msk) + { + return 0; + } + else if (UARTx->BAUD & UART_BAUD_ABRERR_Msk) + { + return UART_ABR_RES_ERR; + } + else + { + return UART_ABR_RES_OK; + } +} + +/****************************************************************************************************************************************** +* : UART_INTRXThresholdEn() +* ˵: RX FIFOݸ >= RXThresholdʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTRXThresholdEn(UART_TypeDef *UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_RXIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTRXThresholdDis() +* ˵: RX FIFOݸ >= RXThresholdʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTRXThresholdDis(UART_TypeDef *UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_RXIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTRXThresholdStat() +* ˵: ǷRX FIFOݸ >= RXThreshold +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 RX FIFOݸ >= RXThreshold 0 RX FIFOݸ < RXThreshold +* ע: RXIF = RXTHRF & RXIE +******************************************************************************************************************************************/ +uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx) +{ + return (UARTx->BAUD & UART_BAUD_RXIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_INTTXThresholdEn() +* ˵: TX FIFOݸ <= TXThresholdʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTXThresholdEn(UART_TypeDef *UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_TXIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTXThresholdDis() +* ˵: TX FIFOݸ <= TXThresholdʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTXThresholdDis(UART_TypeDef *UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_TXIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTXThresholdStat() +* ˵: ǷTX FIFOݸ <= TXThreshold +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 TX FIFOݸ <= TXThreshold 0 TX FIFOݸ > TXThreshold +* ע: TXIF = TXTHRF & TXIE +******************************************************************************************************************************************/ +uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx) +{ + return (UARTx->BAUD & UART_BAUD_TXIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_INTTimeoutEn() +* ˵: շʱʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTimeoutEn(UART_TypeDef *UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_TOIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTimeoutDis() +* ˵: շʱʱ ж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTimeoutDis(UART_TypeDef *UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_TOIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTimeoutStat() +* ˵: Ƿ˽ճʱ TimeoutTime/(Baudrate/10) ûRXϽյʱж +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 ˽ճʱ 0 δճʱ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx) +{ + return (UARTx->BAUD & UART_BAUD_TOIF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_INTTXDoneEn() +* ˵: FIFOҷλĴжʹ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTXDoneEn(UART_TypeDef *UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_TXDOIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTXDoneDis() +* ˵: FIFOҷλĴжϽֹ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTTXDoneDis(UART_TypeDef *UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_TXDOIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_INTTXDoneStat() +* ˵: FIFOҷλĴж״̬ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* : uint32_t 1 FIFOҷλĴ 0 FIFOλĴδ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx) +{ + return (UARTx->BAUD & UART_BAUD_TXDOIF_Msk) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h new file mode 100644 index 00000000000..1bc2ad3edc3 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h @@ -0,0 +1,95 @@ +#ifndef __SWM320_UART_H__ +#define __SWM320_UART_H__ + +typedef struct +{ + uint32_t Baudrate; + + uint8_t DataBits; //λλȡֵUART_DATA_8BITUART_DATA_9BIT + + uint8_t Parity; //żУλȡֵUART_PARITY_NONEUART_PARITY_ODDUART_PARITY_EVENUART_PARITY_ONEUART_PARITY_ZERO + + uint8_t StopBits; //ֹͣλλȡֵUART_STOP_1BITUART_STOP_2BIT + + uint8_t RXThreshold; //ȡֵ0--7 + uint8_t RXThresholdIEn; //RX FIFOݸ >= RXThresholdʱж + + uint8_t TXThreshold; //ȡֵ0--7 + uint8_t TXThresholdIEn; //TX FIFOݸ <= TXThresholdʱж + + uint8_t TimeoutTime; //ʱʱ = TimeoutTime/(Baudrate/10) + uint8_t TimeoutIEn; //ʱжϣ TimeoutTime/(Baudrate/10) ûRXϽյʱж +} UART_InitStructure; + + +#define UART_DATA_8BIT 0 +#define UART_DATA_9BIT 1 + +#define UART_PARITY_NONE 0 +#define UART_PARITY_ODD 1 +#define UART_PARITY_EVEN 3 +#define UART_PARITY_ONE 5 +#define UART_PARITY_ZERO 7 + +#define UART_STOP_1BIT 0 +#define UART_STOP_2BIT 1 + +#define UART_RTS_1BYTE 0 +#define UART_RTS_2BYTE 1 +#define UART_RTS_4BYTE 2 +#define UART_RTS_6BYTE 3 + +#define UART_ABR_RES_OK 1 +#define UART_ABR_RES_ERR 2 + +#define UART_ERR_FRAME 1 +#define UART_ERR_PARITY 2 +#define UART_ERR_NOISE 3 + + +void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct); //UARTڳʼ +void UART_Open(UART_TypeDef *UARTx); +void UART_Close(UART_TypeDef *UARTx); + +void UART_WriteByte(UART_TypeDef *UARTx, uint8_t data); //һֽ +uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data); //ȡһֽݣָǷValid + +uint32_t UART_IsTXBusy(UART_TypeDef *UARTx); +uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx); //FIFOǷգԼUART_ReadByte() +uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx); //FIFOǷԼUART_WriteByte() + + +void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate); //ò +uint32_t UART_GetBaudrate(UART_TypeDef *UARTx); //ȡǰʹõIJ + +void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity); +uint32_t UART_CTSLineState(UART_TypeDef *UARTx); + +void UART_RTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold); +uint32_t UART_RTSLineState(UART_TypeDef *UARTx); + +void UART_LINConfig(UART_TypeDef *UARTx, uint32_t detectedIEn, uint32_t generatedIEn); +void UART_LINGenerate(UART_TypeDef *UARTx); +uint32_t UART_LINIsDetected(UART_TypeDef *UARTx); +uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx); + +void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar); +uint32_t UART_ABRIsDone(UART_TypeDef *UARTx); + + +void UART_INTRXThresholdEn(UART_TypeDef *UARTx); +void UART_INTRXThresholdDis(UART_TypeDef *UARTx); +uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx); +void UART_INTTXThresholdEn(UART_TypeDef *UARTx); +void UART_INTTXThresholdDis(UART_TypeDef *UARTx); +uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx); +void UART_INTTimeoutEn(UART_TypeDef *UARTx); +void UART_INTTimeoutDis(UART_TypeDef *UARTx); +uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx); + +void UART_INTTXDoneEn(UART_TypeDef *UARTx); +void UART_INTTXDoneDis(UART_TypeDef *UARTx); +uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx); + + +#endif //__SWM320_UART_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c new file mode 100644 index 00000000000..04faf947d7e --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c @@ -0,0 +1,126 @@ +/****************************************************************************************************************************************** +* ļ: SWM320_wdt.c +* ˵: SWM320ƬWDTŹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_wdt.h" + + +/****************************************************************************************************************************************** +* : WDT_Init() +* ˵: WDTŹʼ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* uint32_t peroid ȡֵ0--4294967295λΪƬϵͳʱ +* uint32_t mode WDT_MODE_RESET ʱλ WDT_MODE_INTERRUPT ʱж +* : +* ע: λʹʱжϲãΪڽʱоƬֱӸλˣ޷Ӧж +******************************************************************************************************************************************/ +void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode) +{ + SYS->CLKEN |= (0x01 << SYS_CLKEN_WDT_Pos); + + WDT_Stop(WDTx); //ǰȹر + + WDTx->LOAD = peroid; + + if (mode == WDT_MODE_RESET) + { + NVIC_DisableIRQ(WDT_IRQn); + + WDTx->CR |= (1 << WDT_CR_RSTEN_Pos); + } + else //mode == WDT_MODE_INTERRUPT + { + NVIC_EnableIRQ(WDT_IRQn); + + WDTx->CR &= ~(1 << WDT_CR_RSTEN_Pos); + } +} + +/****************************************************************************************************************************************** +* : WDT_Start() +* ˵: ָWDTʼʱ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_Start(WDT_TypeDef *WDTx) +{ + WDTx->CR |= (0x01 << WDT_CR_EN_Pos); +} + +/****************************************************************************************************************************************** +* : WDT_Stop() +* ˵: رָWDTֹͣʱ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_Stop(WDT_TypeDef *WDTx) +{ + WDTx->CR &= ~(0x01 << WDT_CR_EN_Pos); +} + +/****************************************************************************************************************************************** +* : WDT_Feed() +* ˵: ι´װֵʼʱ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_Feed(WDT_TypeDef *WDTx) +{ + WDTx->FEED = 0x55; +} + +/****************************************************************************************************************************************** +* : WDT_GetValue() +* ˵: ȡָŹʱĵǰʱֵ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : int32_t Źǰֵ +* ע: +******************************************************************************************************************************************/ +int32_t WDT_GetValue(WDT_TypeDef *WDTx) +{ + return WDTx->VALUE; +} + +/****************************************************************************************************************************************** +* : WDT_INTClr() +* ˵: жϱ־ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_INTClr(WDT_TypeDef *WDTx) +{ + WDTx->IF = 1; +} + +/****************************************************************************************************************************************** +* : WDT_INTStat() +* ˵: ж״̬ѯ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : int32_t 1 ж 0 δж +* ע: +******************************************************************************************************************************************/ +uint32_t WDT_INTStat(WDT_TypeDef *WDTx) +{ + return WDTx->IF; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h new file mode 100644 index 00000000000..fd435c170ee --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h @@ -0,0 +1,19 @@ +#ifndef __SWM320_WDT_H__ +#define __SWM320_WDT_H__ + +#define WDT_MODE_RESET 0 +#define WDT_MODE_INTERRUPT 1 + +void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode); //WDTŹʼ +void WDT_Start(WDT_TypeDef *WDTx); //ָWDTʼʱ +void WDT_Stop(WDT_TypeDef *WDTx); //رָWDTֹͣʱ + +void WDT_Feed(WDT_TypeDef *WDTx); //ι´װֵʼʱ + +int32_t WDT_GetValue(WDT_TypeDef *WDTx); //ȡָŹʱĵǰʱֵ + + +void WDT_INTClr(WDT_TypeDef *WDTx); //жϱ־ +uint32_t WDT_INTStat(WDT_TypeDef *WDTx); //ж״̬ѯ + +#endif //__SWM320_WDT_H__ diff --git a/bsp/swm320-lq100/README.md b/bsp/swm320-lq100/README.md new file mode 100644 index 00000000000..119b9e7b4b5 --- /dev/null +++ b/bsp/swm320-lq100/README.md @@ -0,0 +1,124 @@ +# SWXT-LQ100-32102 V1.1 板级支持包 说明 + +标签： SYNWIT、Cortex-M4、SWM320VET7、国产MCU + +--- + +## 1. 简介 + +本文档为 SWXT-LQ100-32102 V1.1 的 BSP(板级支持包) 说明。 + +通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +SWXT-LQ100-32102 V1.1 开发板由华芯微特提供，可满足基础测试及高端开发需求。 + +开发板外观如下图所示： + +SWXT_LQ100-32102 V1.1 + +![SWXT-LQ100-32102](figures/SWXT-LQ100-32102.jpg "SWXT-LQ100-32102 V1.1") + +SWXT-LQ100-32102 V1.1 开发板板载资源如下： + +- MCU：SWM320VET7-50 ARM 32-bit Cortex-M4，主频 120MHz，512KB FLASH ，128KB SRAM，2.2～3.6V +- 常用外设 + - LED：1 个，D2 红绿蓝三色LED + - 按键：3 个，K1、K2、K3 + - Nor Flash S29GL128M + - SRAM IS62WV51216BLL +- 常用接口：USB打印接口，TFT LCD接口，SD卡接口 +- 调试接口：SWD + +更多详细信息请咨询[华芯微特技术支持][http://www.synwit.cn/support.html] + +### 1.2 MCU 简介 + +SWM320VET7 是 SYNWIT 公司的一款面向工业控制、白色家电、电机驱动等领域的芯片。包括如下硬件特性： + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| SWM320VET7 | +|CPU| ARM Cortex-M4 | +|主频| 120MHz | +|片内SRAM| 128KB | +|片内Flash| 512KB | + +## 2. 编译说明 + +本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 Jlink 仿真器下载程序，在通过 Jlink 连接开发板到 PC 的基础上，点击下载按钮即可下载程序到开发板 + +推荐熟悉 RT_Thread 的用户使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到 `bsp/swm320-lq100` 目录中，运行以下命令： + +`scons` + +来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中 rtthread.bin 可以烧写到设备中运行。 + +## 3. 烧写及执行 + +### 3.1 硬件连接 + +- 使用 USB B-Type 数据线连接开发板到 PC（注意：需要下载安装串口驱动支持 CH340 芯片，使用 MDK5 需要安装 SWM320 相关的 pack）。 + + > USB B-Type 数据线用于串口通讯，同时供电 + +- 使用 Jlink 连接开发板到 PC （需要 Jlink 驱动） + +将串口 0 引脚为：`[PA2/PA3]`和 USB 转串口模块 P2 相连，串口配置方式为115200-N-8-1。 + +当使用 [env工具](https://www.rt-thread.org/page/download.html) 正确编译产生出rtthread.bin映像文件后，可以使用 ISP 的方式来烧写到设备中。 + +**建议使用 keil 软件直接下载**。ISP 下载较复杂。 + +### 3.2 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到板子上的蓝色LED闪烁。串口打印RT-Thread的启动logo信息： + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Dec 11 2018 + 2006 - 2018 Copyright by rt-thread team +msh /> +``` + +## 4. 驱动支持情况及计划 + +|**板载外设** |**支持情况**|**备注** | +| ----------------- | :----------: | ----------------------- | +| Nor Flash | 支持 | | +| SDIO TF 卡 | 暂不支持 | | +| SRAM | 支持 | | +| TFT-LCD | 暂不支持 | 即将支持 | +|**片上外设** |**支持情况** |**备注** | +| GPIO | 支持 | PIN：1...100 | +| UART | 支持 | UART0 / UART1 / UART2 / UART3 | +| SPI | 支持 | SPI0 / SPI1 | +| I2C | 支持 | I2C0 IO模拟 | +| ADC | 暂不支持 | 即将支持 | +| PWM | 支持 | PWM0 / PWM1 /PWM2 /PWM3 其余两个后续补充| +| IWG | 支持 | | +| TIMER | 支持 | | +| RTC | 支持 | | +| CAN | 暂不支持 | | + +## 5. 联系人信息 + +维护人： + +-[Zohar_Lee](https://github.com/zohar123) email: lizhh@synwit.cn + +## 6. 参考 + +- 芯片[SWM320系列数据手册][http://www.synwit.cn/Public/Uploads/2018-11-05/5bdff49b396d1.pdf] + +- [ SWM320_LQFP100原理图](http://www.synwit.cn/Public/Uploads/2018-11-01/5bdab8ad2e5b9.pdf) + +- [ SWM320_LQFP64原理图](http://www.synwit.cn/Public/Uploads/2018-11-05/5bdfea74d5712.pdf) + +- [ keil pack及其他资料](http://www.synwit.cn/support-1/2.html) diff --git a/bsp/swm320-lq100/SConscript b/bsp/swm320-lq100/SConscript new file mode 100644 index 00000000000..1b1c7506a42 --- /dev/null +++ b/bsp/swm320-lq100/SConscript @@ -0,0 +1,11 @@ +from building import * + +cwd = GetCurrentDir() + +objs = [] +list = os.listdir(cwd) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +Return('objs') diff --git a/bsp/swm320-lq100/SConstruct b/bsp/swm320-lq100/SConstruct new file mode 100644 index 00000000000..331f1056f5d --- /dev/null +++ b/bsp/swm320-lq100/SConstruct @@ -0,0 +1,39 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map rtthread.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/swm320-lq100/applications/SConscript b/bsp/swm320-lq100/applications/SConscript new file mode 100644 index 00000000000..6452d391451 --- /dev/null +++ b/bsp/swm320-lq100/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/swm320-lq100/applications/main.c b/bsp/swm320-lq100/applications/main.c new file mode 100644 index 00000000000..004867b45c4 --- /dev/null +++ b/bsp/swm320-lq100/applications/main.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#include +#include +/* defined the LED pin: PA12 */ +#define LED_PIN 100 + +int main(void) +{ + int count = 1; + /* set LED4 pin mode to output */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/swm320-lq100/drivers/Kconfig b/bsp/swm320-lq100/drivers/Kconfig new file mode 100644 index 00000000000..64d5c992418 --- /dev/null +++ b/bsp/swm320-lq100/drivers/Kconfig @@ -0,0 +1,169 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_WDT + bool "Enable Watch Dog" + select RT_USING_WDT + default n + + menu "UART Drivers" + config BSP_USING_UART0 + bool "Enable UART0 PA2/3(R/T)" + select RT_USING_SERIAL + default y + + config BSP_USING_UART1 + bool "Enable UART1 PC2/3(R/T)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Enable UART2 PC4/5(R/T)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART3 + bool "Enable UART3 PC6/7(R/T)" + select RT_USING_SERIAL + default n + endmenu + + menu "SPI Drivers" + config BSP_USING_SPI0 + bool "Enable SPI0 BUS PC4/5/6(C/O/I)" + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI1 + bool "Enable SPI1 BUS PM5/C2/C3(C/O/I)" + select RT_USING_SPI + select RT_USING_PIN + default n + endmenu + + menu "I2C Drivers" + config BSP_USING_I2C + bool "Enable I2C BUS" + select RT_USING_I2C + select RT_USING_PIN + select RT_USING_I2C_BITOPS + default n + + if BSP_USING_I2C + + config BSP_I2C_SCL + int "I2C SCL Pin index" + default 98 + + config BSP_I2C_SDA + int "I2C SDA Pin index" + default 99 + + config BSP_I2C_BUS_NAME + string "i2c bus name" + default "i2c0" + endif + endmenu + + menu "PWM Drivers" + config BSP_USING_PWM0 + bool "Using PWM0 PA4/10(A/B)" + select RT_USING_PWM + default n + + config BSP_USING_PWM1 + bool "Using PWM1 PA5/9(A/B)" + select RT_USING_PWM + default n + + config BSP_USING_PWM2 + bool "Using PWM2 PP0/2(A/B)" + select RT_USING_PWM + default n + + config BSP_USING_PWM3 + bool "Using PWM3 PP1/3(A/B)" + select RT_USING_PWM + default n + endmenu + + menu "RTC Drivers" + config BSP_USING_RTC + bool "Using RTC" + select RT_USING_RTC + default n + endmenu + + menu "HWtimer Drivers" + config BSP_USING_HWTIMER0 + bool "Using timer0" + select RT_USING_HWTIMER + default n + + config BSP_USING_HWTIMER1 + bool "Using timer1" + select RT_USING_HWTIMER + default n + + config BSP_USING_HWTIMER2 + bool "Using timer2" + select RT_USING_HWTIMER + default n + + config BSP_USING_HWTIMER3 + bool "Using timer3" + select RT_USING_HWTIMER + default n + + config BSP_USING_HWTIMER4 + bool "Using timer4" + select RT_USING_HWTIMER + default n + + config BSP_USING_HWTIMER5 + bool "Using timer5" + select RT_USING_HWTIMER + default n + endmenu + endmenu + + menu "Onboard Peripheral Drivers" + menuconfig BSP_USING_EXT_SRAM + bool "Enable external sram" + select RT_USING_MEMHEAP + select RT_USING_MEMHEAP_AS_HEAP + default n + + if BSP_USING_EXT_SRAM + config BSP_EXT_SRAM_SIZE + hex "external sram size" + default 0x100000 + endif + + menuconfig BSP_USING_NOR_FLASH + bool "Enable mtd nor flash" + select RT_USING_MTD_NOR + select PKG_USING_FTL_SRC + default n + + if BSP_USING_NOR_FLASH + config BSP_NOR_FLASH_SIZE + hex "mtd nor flash size" + default 0x1000000 + config BSP_NOR_FLASH_SECTOR_SIZE + hex "mtd nor flsah sector" + default 0x10000 + endif + endmenu + + menu "Offboard Peripheral Drivers" + + endmenu + +endmenu diff --git a/bsp/swm320-lq100/drivers/SConscript b/bsp/swm320-lq100/drivers/SConscript new file mode 100644 index 00000000000..0d9187d78ae --- /dev/null +++ b/bsp/swm320-lq100/drivers/SConscript @@ -0,0 +1,56 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +""") + +# add gpio driver code +if GetDepend(['BSP_USING_GPIO']): + src += ['drv_gpio.c'] + +# add serial driver code +if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): + src += ['drv_uart.c'] + +# add spi driver code +if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'): + src += ['drv_spi.c'] + +# add i2c driver code +if GetDepend(['BSP_USING_I2C']): + src += ['drv_i2c.c'] + +# add sram driver code +if GetDepend(['BSP_USING_EXT_SRAM']): + src += ['drv_sram.c'] + +# add nor flash driver code +if GetDepend(['BSP_USING_NOR_FLASH']): + src += ['drv_nor_flash.c'] + +# add pwm driver code +if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3'): + src += ['drv_pwm.c'] + +# add rtc driver code +if GetDepend(['BSP_USING_RTC']): + src += ['drv_rtc.c'] + +# add hwtimer driver code +if GetDepend(['BSP_USING_WDT']): + src += ['drv_iwg.c'] + +# add hwtimer driver code +if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1') or GetDepend('BSP_USING_HWTIMER2') or GetDepend('BSP_USING_HWTIMER3') or GetDepend('BSP_USING_HWTIMER4') or GetDepend('BSP_USING_HWTIMER5'): + src += ['drv_hwtimer.c'] + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/swm320-lq100/drivers/board.c b/bsp/swm320-lq100/drivers/board.c new file mode 100644 index 00000000000..36e6a8f4ea1 --- /dev/null +++ b/bsp/swm320-lq100/drivers/board.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) + static struct rt_memheap system_heap; +#endif +static void bsp_clock_config(void) +{ + SystemInit(); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + SysTick->CTRL |= 0x00000004UL; +} +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#ifdef BSP_USING_EXT_SRAM + extern int rt_hw_sram_init(void); +#endif +void rt_hw_board_init() +{ + bsp_clock_config(); + +#ifdef BSP_USING_EXT_SRAM + rt_hw_sram_init(); +#endif +#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) + rt_system_heap_init((void *)EXT_SRAM_BEGIN, (void *)EXT_SRAM_END); + rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); +#elif defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} diff --git a/bsp/swm320-lq100/drivers/board.h b/bsp/swm320-lq100/drivers/board.h new file mode 100644 index 00000000000..702ef43e75a --- /dev/null +++ b/bsp/swm320-lq100/drivers/board.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#ifndef BOARD_H__ +#define BOARD_H__ +#include +#include +#define SRAM_BASE 0x20000000 +#define SRAM_SIZE 0x20000 + +#ifdef BSP_USING_EXT_SRAM + #define EXT_SRAM_BASE SRAMM_BASE + #define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE + #define EXT_SRAM_BEGIN EXT_SRAM_BASE + #define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) +#endif + +#define SRAM_END (SRAM_BASE + SRAM_SIZE) +#ifdef __CC_ARM + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section = "HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END SRAM_END +#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN) +extern void rt_hw_board_init(void); +#endif diff --git a/bsp/swm320-lq100/drivers/drv_gpio.c b/bsp/swm320-lq100/drivers/drv_gpio.c new file mode 100644 index 00000000000..b9d3d425834 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_gpio.c @@ -0,0 +1,598 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee 修复bug + */ + +#include +#include +#include +#include +#include +#include +#include + +typedef void (*pin_callback_t)(void *args); +struct pin +{ + uint32_t package_index; + const char *name; + GPIO_TypeDef *port; + uint32_t group_index; + IRQn_Type irq; + rt_uint32_t irq_mode; + pin_callback_t callback; + void *callback_args; +}; +typedef struct pin pin_t; + +#define SWM32_PIN(a, b, c, d) \ + { \ + a, #b, GPIO##c, d, GPIO##c##_IRQn \ + } +#define GPIO0 ((GPIO_TypeDef *)(0)) +#define GPIO0_IRQn (GPIOA0_IRQn) + +const static pin_t swm32_pin_map[] = +{ + SWM32_PIN(0, None, 0, 0), + SWM32_PIN(1, ADC0 CH3, 0, 0), + SWM32_PIN(2, ADC0 REFP, 0, 0), + SWM32_PIN(3, Cap0, 0, 0), + SWM32_PIN(4, B12, B, 12), + SWM32_PIN(5, RTC VDD, 0, 0), + SWM32_PIN(6, N14, N, 14), + SWM32_PIN(7, N13, N, 13), + SWM32_PIN(8, N12, N, 12), + SWM32_PIN(9, N11, N, 11), + SWM32_PIN(10, VDD 3.3V, 0, 0), + SWM32_PIN(11, VSS 3.3V, 0, 0), + SWM32_PIN(12, Cap 2, 0, 0), + SWM32_PIN(13, N9, N, 9), + SWM32_PIN(14, N10, N, 10), + SWM32_PIN(15, Cap 1, 0, 0), + SWM32_PIN(16, AVSS, 0, 0), + SWM32_PIN(17, AVDD, 0, 0), + SWM32_PIN(18, N2, N, 2), + SWM32_PIN(19, N1, N, 1), + SWM32_PIN(20, N0, N, 0), + SWM32_PIN(21, C4, C, 4), + SWM32_PIN(22, C5, C, 5), + SWM32_PIN(23, C6, C, 6), + SWM32_PIN(24, C7, C, 7), + SWM32_PIN(25, C2, C, 2), + SWM32_PIN(26, C3, C, 3), + SWM32_PIN(27, XHIN, 0, 0), + SWM32_PIN(28, XHOUT, 0, 0), + SWM32_PIN(29, RESET, 0, 0), + SWM32_PIN(30, M2, M, 2), + SWM32_PIN(31, M3, M, 3), + SWM32_PIN(32, M4, M, 4), + SWM32_PIN(33, M5, M, 5), + SWM32_PIN(34, M6, M, 6), + SWM32_PIN(35, M7, M, 7), + SWM32_PIN(36, M8, M, 8), + SWM32_PIN(37, M9, M, 9), + SWM32_PIN(38, M10, M, 10), + SWM32_PIN(39, M11, M, 11), + SWM32_PIN(40, M12, M, 12), + SWM32_PIN(41, M13, M, 13), + SWM32_PIN(42, M14, M, 14), + SWM32_PIN(43, M15, M, 15), + SWM32_PIN(44, M16, M, 16), + SWM32_PIN(45, M17, M, 17), + SWM32_PIN(46, M18, M, 18), + SWM32_PIN(47, M19, M, 19), + SWM32_PIN(48, M20, M, 20), + SWM32_PIN(49, M21, M, 21), + SWM32_PIN(50, VDDIO, 0, 0), + SWM32_PIN(51, M1, M, 1), + SWM32_PIN(52, M0, M, 0), + SWM32_PIN(53, P0, P, 0), + SWM32_PIN(54, P1, P, 1), + SWM32_PIN(55, P2, P, 2), + SWM32_PIN(56, P3, P, 3), + SWM32_PIN(57, P4, P, 4), + SWM32_PIN(58, P5, P, 5), + SWM32_PIN(59, P6, P, 6), + SWM32_PIN(60, P7, P, 7), + SWM32_PIN(61, P8, P, 8), + SWM32_PIN(62, P9, P, 9), + SWM32_PIN(63, P10, P, 10), + SWM32_PIN(64, P11, P, 11), + SWM32_PIN(65, P12, P, 12), + SWM32_PIN(66, P13, P, 13), + SWM32_PIN(67, P14, P, 14), + SWM32_PIN(68, P15, P, 15), + SWM32_PIN(69, P16, P, 16), + SWM32_PIN(70, P17, P, 17), + SWM32_PIN(71, P18, P, 18), + SWM32_PIN(72, P19, P, 19), + SWM32_PIN(73, P20, P, 20), + SWM32_PIN(74, P21, P, 21), + SWM32_PIN(75, P22, P, 22), + SWM32_PIN(76, P23, P, 23), + SWM32_PIN(77, B0, B, 0), + SWM32_PIN(78, A0, A, 0), + SWM32_PIN(79, A1, A, 1), + SWM32_PIN(80, A2, A, 2), + SWM32_PIN(81, A3, A, 3), + SWM32_PIN(82, A4, A, 4), + SWM32_PIN(83, A5, A, 5), + SWM32_PIN(84, VSSIO, 0, 0), + SWM32_PIN(85, C1, C, 1), + SWM32_PIN(86, N19, N, 19), + SWM32_PIN(87, N18, N, 18), + SWM32_PIN(88, N17, N, 17), + SWM32_PIN(89, N16, N, 16), + SWM32_PIN(90, N15, N, 15), + SWM32_PIN(91, N8, N, 8), + SWM32_PIN(92, N7, N, 7), + SWM32_PIN(93, N6, N, 6), + SWM32_PIN(94, N5, N, 5), + SWM32_PIN(95, N4, N, 4), + SWM32_PIN(96, N3, N, 3), + SWM32_PIN(97, A9, A, 9), + SWM32_PIN(98, A10, A, 10), + SWM32_PIN(99, A11, A, 11), + SWM32_PIN(100, A12, A, 12) +}; +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +static pin_t *get_pin(uint8_t pin) +{ + pin_t *index; + if (pin < ITEM_NUM(swm32_pin_map)) + { + index = (pin_t *)&swm32_pin_map[pin]; + if (index->port == GPIO0) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +}; + +static void swm320_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + pin_t *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + if (value) + { + GPIO_SetBit(index->port, index->group_index); + } + else + { + GPIO_ClrBit(index->port, index->group_index); + } +} + +static int swm320_pin_read(rt_device_t dev, rt_base_t pin) +{ + pin_t *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return PIN_LOW; + } + return GPIO_GetBit(index->port, index->group_index); +} + +static void swm320_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + pin_t *index; + int dir = 0; + int pull_up = 0; + int pull_down = 0; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + /* Configure GPIO_InitStructure */ + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + dir = 1; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + dir = 0; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + dir = 0; + pull_up = 1; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + dir = 0; + pull_down = 1; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + dir = 1; + pull_up = 1; + } + GPIO_Init(index->port, index->group_index, dir, pull_up, pull_down); +} + +static rt_err_t swm320_pin_attach_irq(struct rt_device *device, + rt_int32_t pin, + rt_uint32_t mode, + pin_callback_t cb, + void *args) +{ + pin_t *index; + rt_base_t level; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + level = rt_hw_interrupt_disable(); + index->callback = cb; + index->callback_args = args; + index->irq_mode = mode; + + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t swm320_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + pin_t *index; + rt_base_t level; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + level = rt_hw_interrupt_disable(); + index->callback = 0; + index->callback_args = 0; + index->irq_mode = 0; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t swm320_pin_irq_enable(struct rt_device *device, + rt_base_t pin, + rt_uint32_t enabled) +{ + pin_t *index; + rt_base_t level = 0; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_EINVAL; + } + if (enabled == PIN_IRQ_ENABLE) + { + switch (index->irq_mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_Init(index->port, index->group_index, 0, 0, 1); + EXTI_Init(index->port, index->group_index, EXTI_RISE_EDGE); + break; + case PIN_IRQ_MODE_FALLING: + GPIO_Init(index->port, index->group_index, 0, 1, 0); + EXTI_Init(index->port, index->group_index, EXTI_FALL_EDGE); + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_Init(index->port, index->group_index, 0, 1, 1); + EXTI_Init(index->port, index->group_index, EXTI_BOTH_EDGE); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + GPIO_Init(index->port, index->group_index, 0, 0, 1); + EXTI_Init(index->port, index->group_index, EXTI_HIGH_LEVEL); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + GPIO_Init(index->port, index->group_index, 0, 1, 0); + EXTI_Init(index->port, index->group_index, EXTI_LOW_LEVEL); + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + NVIC_EnableIRQ(index->irq); + EXTI_Open(index->port, index->group_index); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + NVIC_DisableIRQ(index->irq); + EXTI_Close(index->port, index->group_index); + } + else + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops swm320_pin_ops = +{ + swm320_pin_mode, + swm320_pin_write, + swm320_pin_read, + swm320_pin_attach_irq, + swm320_pin_detach_irq, + swm320_pin_irq_enable +}; + +int rt_hw_pin_init(void) +{ + int result; + result = rt_device_pin_register("pin", &swm320_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +void GPIOA_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPIOA) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void GPIOB_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPIOB) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void GPIOC_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPIOC) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void GPIOM_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPIOM) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void GPION_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPION) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void GPIOP_Handler(void) +{ + static int gpio[24]; + int index = 0; + static int init = 0; + pin_t *pin; + /* enter interrupt */ + rt_interrupt_enter(); + if (init == 0) + { + init = 1; + for (pin = (pin_t *)&swm32_pin_map[1]; + pin->package_index < ITEM_NUM(swm32_pin_map); + pin++) + { + if (pin->port == GPIOP) + { + gpio[index] = pin->package_index; + index++; + RT_ASSERT(index <= 24) + } + } + } + for (index = 0; index < 24; index++) + { + pin = get_pin(gpio[index]); + if (index != RT_NULL) + { + if (EXTI_State(pin->port, pin->group_index)) + { + EXTI_Clear(pin->port, pin->group_index); + if (pin->callback) + { + pin->callback(pin->callback_args); + } + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} diff --git a/bsp/swm320-lq100/drivers/drv_gpio.h b/bsp/swm320-lq100/drivers/drv_gpio.h new file mode 100644 index 00000000000..49932727266 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_gpio.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_hwtimer.c b/bsp/swm320-lq100/drivers/drv_hwtimer.c new file mode 100644 index 00000000000..b5f76660d5c --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_hwtimer.c @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#include +#include +#include +#include + +#define SWM320_HWTIMER_DEVICE(hwtimer) (struct swm320_hwtimer_dev *)(hwtimer) + +struct swm320_hwtimer_dev +{ + rt_hwtimer_t parent; + TIMR_TypeDef *hwtimer_periph; +}; + +#ifdef BSP_USING_HWTIMER0 +static struct swm320_hwtimer_dev hwtimer0; + +void TIMR0_Handler(void) +{ + TIMR_INTClr(TIMR0); + rt_device_hwtimer_isr(&hwtimer0.parent); + + if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) + { + TIMR_Stop(hwtimer0.hwtimer_periph); + } +} +#endif //BSP_USING_HWTIMER0 + +#ifdef BSP_USING_HWTIMER1 +static struct swm320_hwtimer_dev hwtimer1; + +void TIMR1_Handler(void) +{ + TIMR_INTClr(TIMR1); + rt_device_hwtimer_isr(&hwtimer1.parent); + + if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) + { + TIMR_Stop(hwtimer1.hwtimer_periph); + } +} +#endif //BSP_USING_HWTIMER1 + +#ifdef BSP_USING_HWTIMER2 +static struct swm320_hwtimer_dev hwtimer2; + +void TIMR2_Handler(void) +{ + TIMR_INTClr(TIMR2); + rt_device_hwtimer_isr(&hwtimer2.parent); + + if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode) + { + TIMR_Stop(hwtimer2.hwtimer_periph); + } +} +#endif //BSP_USING_HWTIMER2 + +#ifdef BSP_USING_HWTIMER3 +static struct swm320_hwtimer_dev hwtimer3; + +void TIMR3_Handler(void) +{ + TIMR_INTClr(TIMR3); + rt_device_hwtimer_isr(&hwtimer3.parent); + + if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode) + { + TIMR_Stop(hwtimer3.hwtimer_periph); + } +} +#endif //BSP_USING_HWTIMER3 + +#ifdef BSP_USING_HWTIMER4 +static struct swm320_hwtimer_dev hwtimer4; + +void TIMR4_Handler(void) +{ + TIMR_INTClr(TIMR4); + rt_device_hwtimer_isr(&hwtimer4.parent); + + if (HWTIMER_MODE_ONESHOT == hwtimer4.parent.mode) + { + TIMR_Stop(hwtimer4.hwtimer_periph); + } +} +#endif //BSP_USING_HWTIMER4 + +#ifdef BSP_USING_HWTIMER5 +static struct swm320_hwtimer_dev hwtimer5; + +void TIMR5_Handler(void) +{ + TIMR_INTClr(TIMR5); + rt_device_hwtimer_isr(&hwtimer5.parent); + + if (HWTIMER_MODE_ONESHOT == hwtimer5.parent.mode) + { + TIMR_Stop(hwtimer5.hwtimer_periph); + } +} +#endif //BSP_USING_HWTIMER5 + +static struct rt_hwtimer_info swm320_hwtimer_info = +{ + 120000000, /*时钟源为系统时钟*/ + 120000000, + 4294967295, /*32位计数器，2的32次方*/ + HWTIMER_CNTMODE_DW +}; + +static void swm320_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +{ + struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); + + RT_ASSERT(hwtimer != RT_NULL); + + if (1 == state) + { + TIMR_Init(hwtimer->hwtimer_periph, + TIMR_MODE_TIMER, + SystemCoreClock, + 1); + } + hwtimer->parent.freq = SystemCoreClock; + swm320_hwtimer_info.maxfreq = SystemCoreClock; + swm320_hwtimer_info.minfreq = SystemCoreClock; +} + +static rt_err_t swm320_hwtimer_start(rt_hwtimer_t *timer, + rt_uint32_t cnt, + rt_hwtimer_mode_t mode) +{ + struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); + + RT_ASSERT(hwtimer != RT_NULL); + + TIMR_SetPeriod(hwtimer->hwtimer_periph, cnt); + TIMR_Start(hwtimer->hwtimer_periph); + + return RT_EOK; +} + +static void swm320_hwtimer_stop(rt_hwtimer_t *timer) +{ + struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); + + RT_ASSERT(hwtimer != RT_NULL); + + TIMR_Stop(hwtimer->hwtimer_periph); +} + +static rt_uint32_t swm320_hwtimer_count_get(rt_hwtimer_t *timer) +{ + struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); + uint32_t hwtimer_count = 0; + + RT_ASSERT(hwtimer != RT_NULL); + + hwtimer_count = TIMR_GetCurValue(hwtimer->hwtimer_periph); + + return hwtimer_count; +} + +static rt_err_t swm320_hwtimer_control(rt_hwtimer_t *timer, + rt_uint32_t cmd, + void *args) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t freq = 0; + struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); + + RT_ASSERT(hwtimer != RT_NULL); + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + freq = *(rt_uint32_t*)args; + if (freq != SystemCoreClock) + { + ret = RT_EINVAL; + } + break; + case HWTIMER_CTRL_STOP: + TIMR_Stop(hwtimer->hwtimer_periph); + break; + default: + ret = RT_EINVAL; + break; + } + + return ret; +} + +static struct rt_hwtimer_ops swm320_hwtimer_ops = +{ + swm320_hwtimer_init, + swm320_hwtimer_start, + swm320_hwtimer_stop, + swm320_hwtimer_count_get, + swm320_hwtimer_control +}; + +int rt_hw_hwtimer_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_HWTIMER0 + hwtimer0.hwtimer_periph = TIMR0; + hwtimer0.parent.info = &swm320_hwtimer_info; + hwtimer0.parent.ops = &swm320_hwtimer_ops; + ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0); +#endif //BSP_USING_HWTIMER0 + +#ifdef BSP_USING_HWTIMER1 + hwtimer1.hwtimer_periph = TIMR1; + hwtimer1.parent.info = &swm320_hwtimer_info; + hwtimer1.parent.ops = &swm320_hwtimer_ops; + ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); +#endif //BSP_USING_HWTIMER1 + +#ifdef BSP_USING_HWTIMER2 + hwtimer2.hwtimer_periph = TIMR2; + hwtimer2.parent.info = &swm320_hwtimer_info; + hwtimer2.parent.ops = &swm320_hwtimer_ops; + ret = rt_device_hwtimer_register(&hwtimer2.parent, "timer2", &hwtimer2); +#endif //BSP_USING_HWTIMER2 + +#ifdef BSP_USING_HWTIMER3 + hwtimer3.hwtimer_periph = TIMR3; + hwtimer3.parent.info = &swm320_hwtimer_info; + hwtimer3.parent.ops = &swm320_hwtimer_ops; + ret = rt_device_hwtimer_register(&hwtimer3.parent, "timer3", &hwtimer3); +#endif //BSP_USING_HWTIMER3 + +#ifdef BSP_USING_HWTIMER4 + hwtimer4.hwtimer_periph = TIMR4; + hwtimer4.parent.info = &swm320_hwtimer_info; + hwtimer4.parent.ops = &swm320_hwtimer_ops; + ret = rt_device_hwtimer_register(&hwtimer4.parent, "timer4", &hwtimer4); +#endif //BSP_USING_HWTIMER4 + +#ifdef BSP_USING_HWTIMER5 + hwtimer5.hwtimer_periph = TIMR5; + hwtimer5.parent.info = &swm320_hwtimer_info; + hwtimer5.parent.ops = &swm320_hwtimer_ops; + ret = rt_device_hwtimer_register(&hwtimer5.parent, "timer5", &hwtimer5); +#endif //BSP_USING_HWTIMER5 + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_hwtimer_init); diff --git a/bsp/swm320-lq100/drivers/drv_hwtimer.h b/bsp/swm320-lq100/drivers/drv_hwtimer.h new file mode 100644 index 00000000000..6ec07dedde4 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_hwtimer.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_HWTIMER_H__ +#define DRV_HWTIMER_H__ + +int rt_hw_hwtimer_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_i2c.c b/bsp/swm320-lq100/drivers/drv_i2c.c new file mode 100644 index 00000000000..322d735a68b --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_i2c.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#include +#include +#include + +static void drv_set_sda(void *data, rt_int32_t state) +{ + rt_pin_mode(BSP_I2C_SDA, PIN_MODE_OUTPUT); + rt_pin_write(BSP_I2C_SDA, state); +} + +static void drv_set_scl(void *data, rt_int32_t state) +{ + rt_pin_mode(BSP_I2C_SCL, PIN_MODE_OUTPUT); + rt_pin_write(BSP_I2C_SCL, state); +} + +static rt_int32_t drv_get_sda(void *data) +{ + rt_pin_mode(BSP_I2C_SDA, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(BSP_I2C_SDA); +} + +static rt_int32_t drv_get_scl(void *data) +{ + rt_pin_mode(BSP_I2C_SCL, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(BSP_I2C_SCL); +} + +static void drv_udelay(rt_uint32_t us) +{ + int i = (SystemCoreClock / 4000000 * us); + while (i) + { + i--; + } +} + +static const struct rt_i2c_bit_ops drv_bit_ops = +{ + RT_NULL, + drv_set_sda, + drv_set_scl, + drv_get_sda, + drv_get_scl, + drv_udelay, + 1, + 100 +}; + +int rt_hw_i2c_init(void) +{ + static struct rt_i2c_bus_device i2c2_bus; + rt_memset((void *)&i2c2_bus, 0, sizeof(struct rt_i2c_bus_device)); + i2c2_bus.priv = (void *)&drv_bit_ops; + rt_i2c_bit_add_bus(&i2c2_bus, BSP_I2C_BUS_NAME); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); diff --git a/bsp/swm320-lq100/drivers/drv_i2c.h b/bsp/swm320-lq100/drivers/drv_i2c.h new file mode 100644 index 00000000000..01cbcd76692 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_i2c.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_I2C_H__ +#define DRV_I2C_H__ + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_iwg.c b/bsp/swm320-lq100/drivers/drv_iwg.c new file mode 100644 index 00000000000..c8cd408a081 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_iwg.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#include +#include "rtthread.h" +#include "rtdevice.h" + +static rt_err_t swm320_wdt_init(rt_watchdog_t *wdt) +{ + WDT_Init(WDT, SystemCoreClock / 2, WDT_MODE_INTERRUPT); + + return RT_EOK; +} + +static rt_err_t swm320_wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + *(uint32_t *)arg = WDT->LOAD; + break; + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + WDT_Stop(WDT); + WDT->LOAD = SystemCoreClock / 1000 * (*(uint32_t *)arg); + break; + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + *(uint32_t *)arg = WDT_GetValue(WDT); + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + WDT_Feed(WDT); + break; + case RT_DEVICE_CTRL_WDT_START: + WDT_Start(WDT); + break; + case RT_DEVICE_CTRL_WDT_STOP: + WDT_Stop(WDT); + break; + default: + break; + } + + return RT_EOK; +} + +rt_watchdog_t swm320_wdt; +const static struct rt_watchdog_ops swm320_wdt_ops = +{ + swm320_wdt_init, + swm320_wdt_control +}; + +int rt_hw_wdt_init(void) +{ + rt_err_t result = RT_EOK; + + swm320_wdt.ops = &swm320_wdt_ops; + + result = rt_hw_watchdog_register(&swm320_wdt, + "iwg", + RT_DEVICE_FLAG_RDWR, + WDT); + + return result; +} +INIT_BOARD_EXPORT(rt_hw_wdt_init); + +void WDT_Handler(void) +{ + WDT_INTClr(WDT); +} diff --git a/bsp/swm320-lq100/drivers/drv_iwg.h b/bsp/swm320-lq100/drivers/drv_iwg.h new file mode 100644 index 00000000000..f4e85df8a7a --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_iwg.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_IWG_H__ +#define DRV_IWG_H__ + +int rt_hw_wdt_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_nor_flash.c b/bsp/swm320-lq100/drivers/drv_nor_flash.c new file mode 100644 index 00000000000..7acfc640882 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_nor_flash.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#include +#include +#include +#include + +#define BLOCK_SIZE (64 * 1024) +#define FLASH_SIZE (BSP_NOR_FLASH_SIZE) +#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE) + +static struct rt_mutex flash_lock; + +/* RT-Thread MTD device interface */ +static long swm320_read_id(struct rt_mtd_nor_device *device) +{ + return 0xdeadbeef; +} + +static rt_size_t swm320_read(struct rt_mtd_nor_device *device, + rt_off_t position, + rt_uint8_t *data, + rt_size_t size) +{ + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); + memcpy(data, ((const void *)(NORFLM_BASE + position)), size); + rt_mutex_release(&flash_lock); + return size; +} + +static rt_size_t swm320_write(struct rt_mtd_nor_device *device, + rt_off_t position, + const rt_uint8_t *data, + rt_size_t size) +{ + rt_size_t i; + const rt_uint16_t *hwdata = (const rt_uint16_t *)data; + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); + for (i = 0; i < size / 2; i++) + { + NORFL_Write(position, hwdata[i]); + position += 2; + } + rt_mutex_release(&flash_lock); + return size; +} + +static rt_err_t swm320_erase_block(struct rt_mtd_nor_device *device, + rt_off_t offset, + rt_uint32_t length) +{ + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); + NORFL_SectorErase(offset); + rt_mutex_release(&flash_lock); + return RT_EOK; +} + +const static struct rt_mtd_nor_driver_ops mtd_ops = +{ + swm320_read_id, + swm320_read, + swm320_write, + swm320_erase_block +}; + +static rt_err_t hw_init() +{ + NORFL_InitStructure NORFL_InitStruct; + PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23 + PORT->PORTP_SEL1 = 0xAAAA; + + PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0 + PORT->PORTM_INEN = 0xFFFF; + + PORT->PORTM_SEL1 = 0x2AA; //PM16 => OEN, PM17 => WEN, PM18 => NORFL_CSN,PM19 => SDRAM_CSN, PM20 => SRAM_CSN, PM21 => SDRAM_CKE + + NORFL_InitStruct.DataWidth = 16; + NORFL_InitStruct.WELowPulseTime = 5; + NORFL_InitStruct.OEPreValidTime = 12; + NORFL_InitStruct.OperFinishIEn = 0; + NORFL_InitStruct.OperTimeoutIEn = 0; + NORFL_Init(&NORFL_InitStruct); + return RT_EOK; +} +static struct rt_mtd_nor_device mtd; +int rt_hw_norflash_init(void) +{ + hw_init(); + /* set page size and block size */ + mtd.block_size = BLOCK_SIZE; /* 64kByte */ + mtd.ops = &mtd_ops; + + /* initialize mutex */ + if (rt_mutex_init(&flash_lock, "nor", RT_IPC_FLAG_FIFO) != RT_EOK) + { + rt_kprintf("init sd lock mutex failed\n"); + return -RT_ERROR; + } + mtd.block_start = 0; + mtd.block_end = BLOCK_COUNTER; + + /* register MTD device */ + rt_mtd_nor_register_device("nor", &mtd); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_norflash_init); + +#ifdef RT_USING_FINSH +#include +void nor_erase(void) +{ + NORFL_ChipErase(); +} +MSH_CMD_EXPORT(nor_erase, erase all block in SPI flash); +#endif diff --git a/bsp/swm320-lq100/drivers/drv_nor_flash.h b/bsp/swm320-lq100/drivers/drv_nor_flash.h new file mode 100644 index 00000000000..86260be87ea --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_nor_flash.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_NOR_FLASH_H__ +#define DRV_NOR_FLASH_H__ + +int rt_hw_norflash_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_pwm.c b/bsp/swm320-lq100/drivers/drv_pwm.c new file mode 100644 index 00000000000..3d6f9203ef4 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_pwm.c @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#include +#include +#include +#include + +#define SWM320_PWM_DEVICE(pwm) (struct swm320_pwm_dev *)(pwm) + +#define SWM320_PWM_TIMER_SET(time) ((time) / 1000.0 * 120) + +struct swm320_pwm_dev +{ + struct rt_device_pwm parent; + PWM_TypeDef *pwm_periph; +}; + +static rt_err_t swm320_pwm_enable(void *user_data, + struct rt_pwm_configuration *cfg, + rt_bool_t enable) +{ + rt_err_t ret = RT_EOK; + + if (RT_TRUE == enable) + { + if (2 == cfg->channel) + { + PWM_Start((PWM_TypeDef *)user_data, 1, 1); + } + if (1 == cfg->channel) + { + PWM_Start((PWM_TypeDef *)user_data, 0, 1); + } + if (0 == cfg->channel) + { + PWM_Start((PWM_TypeDef *)user_data, 1, 0); + } + if (3 == cfg->channel) + { + PWM_Start((PWM_TypeDef *)user_data, 0, 0); + } + } + else if (RT_FALSE == enable) + { + if (2 == cfg->channel) + { + PWM_Stop((PWM_TypeDef *)user_data, 1, 1); + } + if (1 == cfg->channel) + { + PWM_Stop((PWM_TypeDef *)user_data, 0, 1); + } + if (0 == cfg->channel) + { + PWM_Stop((PWM_TypeDef *)user_data, 1, 0); + } + if (3 == cfg->channel) + { + PWM_Stop((PWM_TypeDef *)user_data, 0, 0); + } + } + else + { + ret = RT_ERROR; + } + + return ret; +} + +static rt_err_t swm320_pwm_control(struct rt_device_pwm *device, + int cmd, + void *arg) +{ + rt_err_t ret = RT_EOK; + struct swm320_pwm_dev *pwm = SWM320_PWM_DEVICE(device->parent.user_data); + struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(pwm != RT_NULL); + + switch (cmd) + { + case PWM_CMD_ENABLE: + + ret = swm320_pwm_enable((void *)pwm->pwm_periph, cfg, RT_TRUE); + break; + case PWM_CMD_DISABLE: + + ret = swm320_pwm_enable((void *)pwm->pwm_periph, cfg, RT_FALSE); + break; + case PWM_CMD_SET: + PWM_SetHDuty(pwm->pwm_periph, + cfg->channel, + SWM320_PWM_TIMER_SET(cfg->pulse)); + PWM_SetCycle(pwm->pwm_periph, + cfg->channel, + SWM320_PWM_TIMER_SET(cfg->period)); + break; + case PWM_CMD_GET: + cfg->pulse = PWM_GetHDuty(pwm->pwm_periph, cfg->channel); + break; + default: + break; + } + + return ret; +} + +const static struct rt_pwm_ops swm320_pwm_ops = +{ + swm320_pwm_control +}; + +int rt_hw_pwm_init(void) +{ + rt_err_t ret = RT_EOK; + PWM_InitStructure PWM_initStruct; + + PWM_initStruct.clk_div = PWM_CLKDIV_1; /* F_PWM = 120M/1 = 120M */ + PWM_initStruct.mode = PWM_MODE_INDEP; /* A路和B路独立输出 */ + PWM_initStruct.cycleA = SWM320_PWM_TIMER_SET(1000); + PWM_initStruct.hdutyA = SWM320_PWM_TIMER_SET(500); + PWM_initStruct.initLevelA = 1; + PWM_initStruct.cycleB = SWM320_PWM_TIMER_SET(1000); + PWM_initStruct.hdutyB = SWM320_PWM_TIMER_SET(250); + PWM_initStruct.initLevelB = 1; + PWM_initStruct.HEndAIEn = 0; + PWM_initStruct.NCycleAIEn = 0; + PWM_initStruct.HEndBIEn = 0; + PWM_initStruct.NCycleBIEn = 0; + +#ifdef BSP_USING_PWM0 + static struct swm320_pwm_dev pwm_dev0; + pwm_dev0.pwm_periph = PWM0; + PWM_Init(pwm_dev0.pwm_periph, &PWM_initStruct); + PORT_Init(PORTA, PIN4, FUNMUX0_PWM0A_OUT, 0); + PORT_Init(PORTA, PIN10, FUNMUX0_PWM0B_OUT, 0); + ret = rt_device_pwm_register(&pwm_dev0.parent, + "pwm0", + &swm320_pwm_ops, + &pwm_dev0); + +#endif + +#ifdef BSP_USING_PWM1 + static struct swm320_pwm_dev pwm_dev1; + pwm_dev1.pwm_periph = PWM1; + PWM_Init(pwm_dev1.pwm_periph, &PWM_initStruct); + PORT_Init(PORTA, PIN5, FUNMUX1_PWM1A_OUT, 0); + PORT_Init(PORTA, PIN9, FUNMUX1_PWM1B_OUT, 0); + ret = rt_device_pwm_register(&pwm_dev1.parent, + "pwm1", + &swm320_pwm_ops, + &pwm_dev1); +#endif + +#ifdef BSP_USING_PWM2 + static struct swm320_pwm_dev pwm_dev2; + pwm_dev2.pwm_periph = PWM2; + PWM_Init(pwm_dev2.pwm_periph, &PWM_initStruct); + PORT_Init(PORTP, PIN0, FUNMUX0_PWM2A_OUT, 0); + PORT_Init(PORTP, PIN2, FUNMUX0_PWM2B_OUT, 0); + ret = rt_device_pwm_register(&pwm_dev2.parent, + "pwm2", + &swm320_pwm_ops, + &pwm_dev2); +#endif + +#ifdef BSP_USING_PWM3 + static struct swm320_pwm_dev pwm_dev3; + pwm_dev3.pwm_periph = PWM3; + PWM_Init(pwm_dev3.pwm_periph, &PWM_initStruct); + PORT_Init(PORTP, PIN1, FUNMUX1_PWM3A_OUT, 0); + PORT_Init(PORTP, PIN3, FUNMUX1_PWM3B_OUT, 0); + ret = rt_device_pwm_register(&pwm_dev3.parent, + "pwm3", + &swm320_pwm_ops, + &pwm_dev3); +#endif + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); diff --git a/bsp/swm320-lq100/drivers/drv_pwm.h b/bsp/swm320-lq100/drivers/drv_pwm.h new file mode 100644 index 00000000000..94bbf0c7503 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_pwm.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_PWM_H__ +#define DRV_PWM_H__ + +int rt_hw_pwm_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_rtc.c b/bsp/swm320-lq100/drivers/drv_rtc.c new file mode 100644 index 00000000000..51597ba73dc --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_rtc.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#include +#include +#include +#include +#include +#include + +/** + * This function will get the weed day from a date. + * + * @param year the year of time + * @param month the month of time + * @param date the date of time + * + * @return the week day 0 ~ 6 : sun ~ sat + * + * @note No + */ +static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) +{ + uint32_t i, cnt = 0; + const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + + for (i = 1; i < month; i++) + cnt += daysOfMonth[i]; + + cnt += date; + + if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && + (month >= 3)) + cnt += 1; + + cnt += (year - 1901) * 365; + + for (i = 1901; i < year; i++) + { + if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0))) + cnt += 1; + } + + return (cnt + 1) % 7; +} + +static void RTC_SetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime) +{ + RTC_Stop(RTCx); + + while (RTCx->CFGABLE == 0); + + RTCx->MINSEC = (dateTime->Second << RTC_MINSEC_SEC_Pos) | + (dateTime->Minute << RTC_MINSEC_MIN_Pos); + + RTCx->DATHUR = (dateTime->Hour << RTC_DATHUR_HOUR_Pos) | + ((dateTime->Date - 1) << RTC_DATHUR_DATE_Pos); + + RTCx->MONDAY = (calcWeekDay(dateTime->Year, dateTime->Month, dateTime->Date) + << RTC_MONDAY_DAY_Pos) | + ((dateTime->Month - 1) << RTC_MONDAY_MON_Pos); + + RTCx->YEAR = dateTime->Year - 1901; + + RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos; + + RTC_Start(RTC); +} + +static rt_err_t swm320_rtc_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t result = RT_EOK; + + struct tm time_temp; + struct tm *pNow; + RTC_DateTime dateTime; + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + RTC_GetDateTime(RTC, &dateTime); + time_temp.tm_sec = dateTime.Second; + time_temp.tm_min = dateTime.Minute; + time_temp.tm_hour = dateTime.Hour; + time_temp.tm_mday = dateTime.Date; + time_temp.tm_mon = dateTime.Month - 1; + time_temp.tm_year = dateTime.Year - 1900; + *((time_t *)args) = mktime(&time_temp); + break; + case RT_DEVICE_CTRL_RTC_SET_TIME: + rt_enter_critical(); + /* converts calendar time time into local time. */ + pNow = localtime((const time_t *)args); + /* copy the statically located variable */ + memcpy(&time_temp, pNow, sizeof(struct tm)); + /* unlock scheduler. */ + rt_exit_critical(); + + dateTime.Hour = time_temp.tm_hour; + dateTime.Minute = time_temp.tm_min; + dateTime.Second = time_temp.tm_sec; + dateTime.Year = time_temp.tm_year + 1900; + dateTime.Month = time_temp.tm_mon + 1; + dateTime.Date = time_temp.tm_mday; + RTC_SetDateTime(RTC, &dateTime); + break; + case RT_DEVICE_CTRL_RTC_GET_ALARM: + + break; + case RT_DEVICE_CTRL_RTC_SET_ALARM: + + break; + default: + break; + } + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops swm320_rtc_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + swm320_rtc_control +}; +#endif + +int rt_hw_rtc_init(void) +{ + rt_err_t ret = RT_EOK; + static struct rt_device rtc_dev; + RTC_InitStructure RTC_initStruct; + + RTC_initStruct.Year = 2018; + RTC_initStruct.Month = 1; + RTC_initStruct.Date = 1; + RTC_initStruct.Hour = 12; + RTC_initStruct.Minute = 0; + RTC_initStruct.Second = 0; + RTC_initStruct.SecondIEn = 0; + RTC_initStruct.MinuteIEn = 0; + RTC_Init(RTC, &RTC_initStruct); + RTC_Start(RTC); + + rtc_dev.type = RT_Device_Class_RTC; + rtc_dev.rx_indicate = RT_NULL; + rtc_dev.tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + rtc_dev.ops = &swm320_rtc_ops; +#else + rtc_dev.init = RT_NULL; + rtc_dev.open = RT_NULL; + rtc_dev.close = RT_NULL; + rtc_dev.read = RT_NULL; + rtc_dev.write = RT_NULL; + rtc_dev.control = swm320_rtc_control; +#endif + + rtc_dev.user_data = RTC; + + ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); diff --git a/bsp/swm320-lq100/drivers/drv_rtc.h b/bsp/swm320-lq100/drivers/drv_rtc.h new file mode 100644 index 00000000000..f72d3d3d949 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_rtc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_RTC_H__ +#define DRV_RTC_H__ + +int rt_hw_rtc_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_spi.c b/bsp/swm320-lq100/drivers/drv_spi.c new file mode 100644 index 00000000000..e766f0ea819 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_spi.c @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#include +#include +#include +#include +#include + +#define SPIRXEVENT 0x01 +#define SPITXEVENT 0x02 +#define SPITIMEOUT 2 +#define SPICRCEN 0 + +struct swm320_spi +{ + SPI_TypeDef *swm320_spi; + struct rt_spi_configuration *cfg; +}; + +static rt_err_t swm320_spi_init(SPI_TypeDef *spix, + struct rt_spi_configuration *cfg) +{ + SPI_InitStructure SPI_initStruct; + if (cfg->mode & RT_SPI_SLAVE) + { + SPI_initStruct.Master = 0; + } + else + { + SPI_initStruct.Master = 1; + } + if (cfg->mode & RT_SPI_3WIRE) + { + return RT_EINVAL; + } + if (cfg->data_width == 8) + { + SPI_initStruct.WordSize = 8; + } + else if (cfg->data_width == 16) + { + SPI_initStruct.WordSize = 16; + } + else + { + return RT_EINVAL; + } + if (cfg->mode & RT_SPI_CPHA) + { + SPI_initStruct.SampleEdge = SPI_SECOND_EDGE; + } + else + { + SPI_initStruct.SampleEdge = SPI_FIRST_EDGE; + } + if (cfg->mode & RT_SPI_CPOL) + { + SPI_initStruct.IdleLevel = SPI_HIGH_LEVEL; + } + else + { + SPI_initStruct.IdleLevel = SPI_LOW_LEVEL; + } + if (cfg->max_hz >= SystemCoreClock / 4) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_4; + } + else if (cfg->max_hz >= SystemCoreClock / 8) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_8; + } + else if (cfg->max_hz >= SystemCoreClock / 16) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_16; + } + else if (cfg->max_hz >= SystemCoreClock / 32) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_32; + } + else if (cfg->max_hz >= SystemCoreClock / 64) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_64; + } + else if (cfg->max_hz >= SystemCoreClock / 128) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_128; + } + else if (cfg->max_hz >= SystemCoreClock / 256) + { + SPI_initStruct.clkDiv = SPI_CLKDIV_256; + } + else + { + /* min prescaler 512 */ + SPI_initStruct.clkDiv = SPI_CLKDIV_512; + } + SPI_initStruct.FrameFormat = SPI_FORMAT_SPI; + SPI_initStruct.RXHFullIEn = 0; + SPI_initStruct.TXEmptyIEn = 0; + SPI_initStruct.TXCompleteIEn = 0; + SPI_Init(spix, &SPI_initStruct); + SPI_Open(spix); + return RT_EOK; +} + +#define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2) +#define SPISEND_1(reg, ptr, datalen) \ + do \ + { \ + if (datalen == 8) \ + { \ + (reg) = *(rt_uint8_t *)(ptr); \ + } \ + else \ + { \ + (reg) = *(rt_uint16_t *)(ptr); \ + } \ + } while (0) +#define SPIRECV_1(reg, ptr, datalen) \ + do \ + { \ + if (datalen == 8) \ + { \ + *(rt_uint8_t *)(ptr) = (reg); \ + } \ + else \ + { \ + *(rt_uint16_t *)(ptr) = reg; \ + } \ + } while (0) + +static rt_err_t spitxrx1b(struct swm320_spi *hspi, void *rcvb, const void *sndb) +{ + rt_uint32_t padrcv = 0; + rt_uint32_t padsnd = 0xFF; + if (!rcvb && !sndb) + { + return RT_ERROR; + } + if (!rcvb) + { + rcvb = &padrcv; + } + if (!sndb) + { + sndb = &padsnd; + } + while (SPI_IsTXFull(hspi->swm320_spi)); + SPISEND_1(hspi->swm320_spi->DATA, sndb, hspi->cfg->data_width); + while (SPI_IsRXEmpty(hspi->swm320_spi)); + SPIRECV_1(hspi->swm320_spi->DATA, rcvb, hspi->cfg->data_width); + return RT_EOK; +} + +static rt_uint32_t swm320_spi_xfer(struct rt_spi_device *device, + struct rt_spi_message *message) +{ + rt_err_t res; + struct swm320_spi *hspi = (struct swm320_spi *)device->bus->parent.user_data; + struct swm320_spi_cs *cs = device->parent.user_data; + const rt_uint8_t *sndb = message->send_buf; + rt_uint8_t *rcvb = message->recv_buf; + rt_int32_t length = message->length; + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + if (message->cs_take) + { + rt_pin_write(cs->pin, 0); + } + while (length) + { + res = spitxrx1b(hspi, rcvb, sndb); + if (rcvb) + { + rcvb += SPISTEP(hspi->cfg->data_width); + } + if (sndb) + { + sndb += SPISTEP(hspi->cfg->data_width); + } + if (res != RT_EOK) + { + break; + } + length--; + } + /* Wait until Busy flag is reset before disabling SPI */ + while (!SPI_IsTXEmpty(hspi->swm320_spi) && !SPI_IsRXEmpty(hspi->swm320_spi)); + if (message->cs_release) + { + rt_pin_write(cs->pin, 1); + } + return message->length - length; +} + +static rt_err_t swm320_spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + struct swm320_spi *hspi = (struct swm320_spi *)device->bus->parent.user_data; + hspi->cfg = configuration; + return swm320_spi_init(hspi->swm320_spi, configuration); +} +const static struct rt_spi_ops swm320_spi_ops = +{ + .configure = swm320_spi_configure, + .xfer = swm320_spi_xfer, +}; + +#ifdef BSP_USING_SPI0 + static struct rt_spi_bus swm320_spi_bus0; + static struct swm320_spi swm320_spi0; +#endif //BSP_USING_SPI0 + +#ifdef BSP_USING_SPI1 + static struct rt_spi_bus swm320_spi_bus1; + static struct swm320_spi swm320_spi1; +#endif //BSP_USING_SPI1 + +static int swm320_spi_register_bus(SPI_TypeDef *SPIx, const char *name) +{ + struct rt_spi_bus *spi_bus; + struct swm320_spi *swm320_spi; + if (SPIx == SPI0) + { + PORT_Init(PORTC, PIN5, FUNMUX1_SPI0_SCLK, 0); + PORT_Init(PORTC, PIN6, FUNMUX0_SPI0_MOSI, 0); + PORT_Init(PORTC, PIN7, FUNMUX1_SPI0_MISO, 1); + spi_bus = &swm320_spi_bus0; + swm320_spi = &swm320_spi0; + } + else if (SPIx == SPI1) + { + PORT_Init(PORTM, PIN5, FUNMUX1_SPI1_SCLK, 0); + PORT_Init(PORTC, PIN2, FUNMUX0_SPI1_MOSI, 0); + PORT_Init(PORTC, PIN3, FUNMUX1_SPI1_MISO, 1); + spi_bus = &swm320_spi_bus1; + swm320_spi = &swm320_spi1; + } + else + { + return -1; + } + swm320_spi->swm320_spi = SPIx; + spi_bus->parent.user_data = swm320_spi; + return rt_spi_bus_register(spi_bus, name, &swm320_spi_ops); +} + +//cannot be used before completion init +static rt_err_t swm320_spi_bus_attach_device(rt_uint32_t pin, + const char *bus_name, + const char *device_name) +{ + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + struct swm320_spi_cs *cs_pin = (struct swm320_spi_cs *)rt_malloc(sizeof(struct swm320_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, 1); + return rt_spi_bus_attach_device(spi_device, + device_name, + bus_name, + (void *)cs_pin); +} + +int rt_hw_spi_init(void) +{ + int result = 0; +#ifdef BSP_USING_SPI0 + result = swm320_spi_register_bus(SPI0, "spi0"); +#endif +#ifdef BSP_USING_SPI1 + result = swm320_spi_register_bus(SPI1, "spi1"); +#endif + return result; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/swm320-lq100/drivers/drv_spi.h b/bsp/swm320-lq100/drivers/drv_spi.h new file mode 100644 index 00000000000..7e5366ab588 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_spi.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_SPI_H__ +#define DRV_SPI_H__ + +#include + +struct swm320_spi_cs +{ + rt_uint32_t pin; +}; + +//cannot be used before completion init +static rt_err_t swm320_spi_bus_attach_device(rt_uint32_t pin, + const char *bus_name, + const char *device_name); +int rt_hw_spi_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_sram.c b/bsp/swm320-lq100/drivers/drv_sram.c new file mode 100644 index 00000000000..b23c76beac6 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_sram.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#include +#include +#include +#include + +int rt_hw_sram_init(void) +{ + int i; + PORT->PORTP_SEL0 = 0xAAAAAAAA; /* PP0-23 => ADDR0-23 */ + PORT->PORTP_SEL1 = 0xAAAA; + PORT->PORTM_SEL0 = 0xAAAAAAAA; /* PM0-15 => DATA15-0 */ + PORT->PORTM_INEN |= 0xFFFF; + PORT->PORTM_SEL1 = 0x2AA; /* PM16 => OEN、PM17 => WEN、PM18 => NORFL_CSN、PM19 => SDRAM_CSN、PM20 => SRAM_CSN、PM21 => SDRAM_CKE */ + + /* 配置SRAM前需要刷新下SDRAM控制器 */ + + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + while (SDRAMC->REFDONE == 0); + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); + + for (i = 0; i < 1000; i++) + { + } + SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); + + SYS->CLKEN |= (1 << SYS_CLKEN_RAMC_Pos); + + SRAMC->CR = (9 << SRAMC_CR_RWTIME_Pos) | + (0 << SRAMC_CR_BYTEIF_Pos) | // 16位接口 + (0 << SRAMC_CR_HBLBDIS_Pos); // 使能字节、半字访问 + + return 0; +} diff --git a/bsp/swm320-lq100/drivers/drv_sram.h b/bsp/swm320-lq100/drivers/drv_sram.h new file mode 100644 index 00000000000..5f813197339 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_sram.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_SRAM_H__ +#define DRV_SRAM_H__ + +int rt_hw_sram_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/drv_uart.c b/bsp/swm320-lq100/drivers/drv_uart.c new file mode 100644 index 00000000000..fe02c4da553 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_uart.c @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + */ + +#include +#include +#include +#include +#include + +struct swm320_uart +{ + UART_TypeDef *uart; + IRQn_Type irq; +}; + +static rt_err_t swm320_uart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct swm320_uart *uart; + UART_InitStructure UART_initStruct; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct swm320_uart *)serial->parent.user_data; + NVIC_DisableIRQ(uart->irq); + UART_initStruct.Baudrate = cfg->baud_rate; + UART_initStruct.RXThreshold = 1; + UART_initStruct.RXThresholdIEn = 1; + UART_initStruct.TXThresholdIEn = 0; + UART_initStruct.TimeoutTime = 10; + UART_initStruct.TimeoutIEn = 0; + switch (cfg->data_bits) + { + case DATA_BITS_9: + UART_initStruct.DataBits = UART_DATA_9BIT; + break; + default: + UART_initStruct.DataBits = UART_DATA_8BIT; + break; + } + switch (cfg->stop_bits) + { + case STOP_BITS_2: + UART_initStruct.StopBits = UART_STOP_2BIT; + break; + default: + UART_initStruct.StopBits = UART_STOP_1BIT; + break; + } + switch (cfg->parity) + { + case PARITY_ODD: + UART_initStruct.Parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + UART_initStruct.Parity = UART_PARITY_EVEN; + break; + default: + UART_initStruct.Parity = UART_PARITY_NONE; + break; + } + UART_Init(uart->uart, &UART_initStruct); + UART_Open(uart->uart); + return RT_EOK; +} + +static rt_err_t swm320_uart_control(struct rt_serial_device *serial, + int cmd, void *arg) +{ + struct swm320_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct swm320_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + break; + } + return RT_EOK; +} + +static int swm320_uart_putc(struct rt_serial_device *serial, char c) +{ + struct swm320_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct swm320_uart *)serial->parent.user_data; + while (UART_IsTXBusy(uart->uart)); + uart->uart->DATA = c; + return 1; +} + +static int swm320_uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct swm320_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct swm320_uart *)serial->parent.user_data; + ch = -1; + if (UART_IsRXFIFOEmpty(uart->uart) == 0) + { + UART_ReadByte(uart->uart, (uint32_t *)&ch); + } + return ch; +} + +static const struct rt_uart_ops swm320_uart_ops = +{ + swm320_uart_configure, + swm320_uart_control, + swm320_uart_putc, + swm320_uart_getc, +}; + +#if defined(BSP_USING_UART0) +/* UART0 device driver structure */ +static struct swm320_uart uart0; +static struct rt_serial_device serial0; +void UART0_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_INTRXThresholdStat(uart0.uart) || UART_INTTimeoutStat(uart0.uart)) + { + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +/* UART1 device driver structure */ +static struct swm320_uart uart1; +static struct rt_serial_device serial1; +void UART1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_INTRXThresholdStat(uart1.uart) || UART_INTTimeoutStat(uart1.uart)) + { + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +/* UART2 device driver structure */ +static struct swm320_uart uart2; +static struct rt_serial_device serial2; +void UART2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_INTRXThresholdStat(uart2.uart) || UART_INTTimeoutStat(uart2.uart)) + { + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +/* UART3 device driver structure */ +static struct swm320_uart uart3; +static struct rt_serial_device serial3; +void UART3_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_INTRXThresholdStat(uart3.uart) || UART_INTTimeoutStat(uart3.uart)) + { + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +int rt_hw_uart_init(void) +{ + struct swm320_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef BSP_USING_UART0 + PORT_Init(PORTA, PIN2, FUNMUX0_UART0_RXD, 1); + PORT_Init(PORTA, PIN3, FUNMUX1_UART0_TXD, 0); + uart = &uart0; + uart->uart = UART0; + uart->irq = UART0_IRQn; + serial0.ops = &swm320_uart_ops; + serial0.config = config; + /* register UART0 device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART0 */ +#ifdef BSP_USING_UART1 + PORT_Init(PORTC, PIN2, FUNMUX0_UART1_RXD, 1); + PORT_Init(PORTC, PIN3, FUNMUX1_UART1_TXD, 0); + uart = &uart1; + uart->uart = UART1; + uart->irq = UART1_IRQn; + serial1.ops = &swm320_uart_ops; + serial1.config = config; + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART1 */ +#ifdef BSP_USING_UART2 + PORT_Init(PORTC, PIN4, FUNMUX0_UART2_RXD, 1); + PORT_Init(PORTC, PIN5, FUNMUX1_UART2_TXD, 0); + uart = &uart2; + uart->uart = UART2; + uart->irq = UART2_IRQn; + serial2.ops = &swm320_uart_ops; + serial2.config = config; + /* register UART2 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART2 */ +#ifdef BSP_USING_UART3 + PORT_Init(PORTC, PIN6, FUNMUX0_UART3_RXD, 1); + PORT_Init(PORTC, PIN7, FUNMUX1_UART3_TXD, 0); + uart = &uart3; + uart->uart = UART3; + uart->irq = UART3_IRQn; + serial3.ops = &swm320_uart_ops; + serial3.config = config; + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART3 */ + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/swm320-lq100/drivers/drv_uart.h b/bsp/swm320-lq100/drivers/drv_uart.h new file mode 100644 index 00000000000..67193a45d4c --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/swm320-lq100/drivers/linker_scripts/link.icf b/bsp/swm320-lq100/drivers/linker_scripts/link.icf new file mode 100644 index 00000000000..4d4eb646235 --- /dev/null +++ b/bsp/swm320-lq100/drivers/linker_scripts/link.icf @@ -0,0 +1,62 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x0; +define symbol __ICFEDIT_region_IROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region EROM_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__] + | mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__] + | mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] + | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] + | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +do not initialize { section .noinit }; +initialize by copy { readwrite }; +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in IROM_region { readonly }; +place in EROM_region { readonly section application_specific_ro }; +place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; +place in ERAM_region { readwrite section application_specific_rw }; \ No newline at end of file diff --git a/bsp/swm320-lq100/drivers/linker_scripts/link.lds b/bsp/swm320-lq100/drivers/linker_scripts/link.lds new file mode 100644 index 00000000000..2f6896cfb34 --- /dev/null +++ b/bsp/swm320-lq100/drivers/linker_scripts/link.lds @@ -0,0 +1,137 @@ +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 1024KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/swm320-lq100/drivers/linker_scripts/link.sct b/bsp/swm320-lq100/drivers/linker_scripts/link.sct new file mode 100644 index 00000000000..c7363fec458 --- /dev/null +++ b/bsp/swm320-lq100/drivers/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00080000 { ; load region size_region + ER_IROM1 0x00000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/swm320-lq100/figures/SWXT-LQ100-32102.jpg b/bsp/swm320-lq100/figures/SWXT-LQ100-32102.jpg new file mode 100644 index 00000000000..87e92b7e165 Binary files /dev/null and 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+ + 7 + 66 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_error.c + finsh_error.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_heap.c + finsh_heap.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_init.c + finsh_init.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_node.c + finsh_node.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_ops.c + finsh_ops.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_parser.c + finsh_parser.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_var.c + finsh_var.c + 0 + 0 + + + 7 + 73 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_vm.c + finsh_vm.c + 0 + 0 + + + 7 + 74 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_token.c + finsh_token.c + 0 + 0 + + + + diff --git a/bsp/swm320-lq100/project.uvprojx b/bsp/swm320-lq100/project.uvprojx new file mode 100644 index 00000000000..21a3d56d781 --- /dev/null +++ b/bsp/swm320-lq100/project.uvprojx @@ -0,0 +1,795 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + SWM320xE + Synwit + Synwit.SWM32_DFP.1.6.2 + http://www.synwit.com/pack + IRAM(0x20000000,0x20000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)) + 0 + $$Device:SWM320xE$CSL\SWM320\CMSIS\DeviceSupport\SWM320.h + + + + + + + + + + $$Device:SWM320xE$SVD\SWM320.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + applications;.;drivers;Libraries\CMSIS\CoreSupport;Libraries\CMSIS\DeviceSupport;Libraries\SWM320_StdPeriph_Driver;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + Applications + + + hwtimer_sample.c + 1 + applications\hwtimer_sample.c + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + Libraries + + + system_SWM320.c + 1 + Libraries\CMSIS\DeviceSupport\system_SWM320.c + + + SWM320_adc.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_adc.c + + + SWM320_can.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_can.c + + + SWM320_crc.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_crc.c + + + SWM320_dma.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_dma.c + + + SWM320_exti.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_exti.c + + + SWM320_flash.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_flash.c + + + SWM320_gpio.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c + + + SWM320_i2c.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c + + + SWM320_lcd.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c + + + SWM320_norflash.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_norflash.c + + + SWM320_port.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_port.c + + + SWM320_pwm.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c + + + SWM320_rtc.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c + + + SWM320_sdio.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c + + + SWM320_sdram.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c + + + SWM320_spi.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_spi.c + + + SWM320_timr.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_timr.c + + + SWM320_uart.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_uart.c + + + SWM320_wdt.c + 1 + Libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c + + + startup_SWM320.s + 2 + Libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s + + + + + Kernel + + + clock.c + 1 + ..\..\src\clock.c + + + components.c + 1 + ..\..\src\components.c + + + cpu.c + 1 + ..\..\src\cpu.c + + + device.c + 1 + ..\..\src\device.c + + + idle.c + 1 + ..\..\src\idle.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + irq.c + 1 + ..\..\src\irq.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + mem.c + 1 + ..\..\src\mem.c + + + memheap.c + 1 + ..\..\src\memheap.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + object.c + 1 + ..\..\src\object.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + signal.c + 1 + ..\..\src\signal.c + + + thread.c + 1 + ..\..\src\thread.c + + + timer.c + 1 + ..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + + + DeviceDrivers + + + hwtimer.c + 1 + ..\..\components\drivers\hwtimer\hwtimer.c + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + rt_drv_pwm.c + 1 + ..\..\components\drivers\misc\rt_drv_pwm.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + symbol.c + 1 + ..\..\components\finsh\symbol.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + + + + + + + + + + diff --git a/bsp/swm320-lq100/rtconfig.h b/bsp/swm320-lq100/rtconfig.h new file mode 100644 index 00000000000..8543660eab3 --- /dev/null +++ b/bsp/swm320-lq100/rtconfig.h @@ -0,0 +1,182 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x30102 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_HWTIMER +#define RT_USING_PIN +#define RT_USING_PWM + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_SWM320VET7 + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART0 + +/* SPI Drivers */ + + +/* I2C Drivers */ + + +/* PWM Drivers */ + + +/* RTC Drivers */ + + +/* HWtimer Drivers */ + + +/* Onboard Peripheral Drivers */ + + +/* Offboard Peripheral Drivers */ + + +#endif diff --git a/bsp/swm320-lq100/rtconfig.py b/bsp/swm320-lq100/rtconfig.py new file mode 100644 index 00000000000..c8f9102c768 --- /dev/null +++ b/bsp/swm320-lq100/rtconfig.py @@ -0,0 +1,137 @@ +# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad (REV D) + +import os +import sys +# toolchains options +CROSS_TOOL = 'gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +# device options +ARCH = 'arm' +CPU = 'cortex-m4' +FPU = 'fpv4-sp-d16' +FLOAT_ABI = 'softfp' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '/Users/zhangyihong/.env/gcc-arm-none-eabi-5_4-2016q3/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=' + FPU + ' -mfloat-abi=' + \ + FLOAT_ABI + ' -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -std=c99' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/LIB' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/arm/armcc/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' # + ' -D' + PART_TYPE + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "drivers/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + #LFLAGS += ' --silent' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/swm320-lq100/template.ewp b/bsp/swm320-lq100/template.ewp new file mode 100644 index 00000000000..2ff75d9abc0 --- /dev/null +++ b/bsp/swm320-lq100/template.ewp @@ -0,0 +1,2032 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/swm320-lq100/template.eww b/bsp/swm320-lq100/template.eww new file mode 100644 index 00000000000..bd036bb4c98 --- /dev/null +++ b/bsp/swm320-lq100/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/swm320-lq100/template.uvopt b/bsp/swm320-lq100/template.uvopt new file mode 100644 index 00000000000..0e93bee1432 --- /dev/null +++ b/bsp/swm320-lq100/template.uvopt @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + + 0 + Datasheet + DATASHTS\ST\STM32F4xx\DM00053488.pdf + + + 1 + Reference Manual + DATASHTS\ST\STM32F4xx\DM00031020.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U20090928 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/swm320-lq100/template.uvoptx b/bsp/swm320-lq100/template.uvoptx new file mode 100644 index 00000000000..bc15f1d3257 --- /dev/null +++ b/bsp/swm320-lq100/template.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FN1 -FC1000 -FD20000000 -FF0SWM320xE -FL080000 -FS00 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM) + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8002 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/swm320-lq100/template.uvprojx b/bsp/swm320-lq100/template.uvprojx new file mode 100644 index 00000000000..a8cdab71fcc --- /dev/null +++ b/bsp/swm320-lq100/template.uvprojx @@ -0,0 +1,388 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + SWM320xE + Synwit + Synwit.SWM32_DFP.1.6.2 + http://www.synwit.com/pack + IRAM(0x20000000,0x20000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)) + 0 + $$Device:SWM320xE$CSL\SWM320\CMSIS\DeviceSupport\SWM320.h + + + + + + + + + + $$Device:SWM320xE$SVD\SWM320.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/tm4c129x/.config b/bsp/tm4c129x/.config index ec901ddbe1a..d69bb47aa9e 100644 --- a/bsp/tm4c129x/.config +++ b/bsp/tm4c129x/.config @@ -8,17 +8,30 @@ # CONFIG_RT_NAME_MAX=8 CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_DEBUG=y CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_DEBUG_INIT=0 -# CONFIG_RT_DEBUG_THREAD is not set CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set # # Inter-Thread communication @@ -35,24 +48,32 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_MEMHEAP=y -CONFIG_RT_USING_HEAP=y +# CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y # # Kernel Device Object # CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_VER_NUM=0x30102 +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components # CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features @@ -63,9 +84,12 @@ CONFIG_RT_USING_USER_MAIN=y # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_CMD_SIZE=80 @@ -81,17 +105,34 @@ CONFIG_FINSH_CMD_SIZE=80 # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# # CONFIG_RT_USING_USB_HOST is not set # CONFIG_RT_USING_USB_DEVICE is not set @@ -102,8 +143,13 @@ CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set # -# Network stack +# Network +# + +# +# Socket abstraction layer # +# CONFIG_RT_USING_SAL is not set # # light weight TCP/IP stack @@ -111,6 +157,7 @@ CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_LWIP=y CONFIG_RT_USING_LWIP141=y # CONFIG_RT_USING_LWIP202 is not set +# CONFIG_RT_USING_LWIP210 is not set # CONFIG_RT_LWIP_IGMP is not set CONFIG_RT_LWIP_ICMP=y # CONFIG_RT_LWIP_SNMP is not set @@ -118,7 +165,6 @@ CONFIG_RT_LWIP_DNS=y CONFIG_RT_LWIP_DHCP=y CONFIG_IP_SOF_BROADCAST=1 CONFIG_IP_SOF_BROADCAST_RECV=1 -# CONFIG_LWIP_USING_DHCPD is not set # # Static IPv4 Address @@ -130,8 +176,7 @@ CONFIG_RT_LWIP_UDP=y CONFIG_RT_LWIP_TCP=y # CONFIG_RT_LWIP_RAW is not set # CONFIG_RT_LWIP_PPP is not set -# CONFIG_RT_LWIP_PPPOE is not set -# CONFIG_RT_LWIP_PPPOS is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 CONFIG_RT_LWIP_PBUF_NUM=16 CONFIG_RT_LWIP_RAW_PCB_NUM=4 CONFIG_RT_LWIP_UDP_PCB_NUM=4 @@ -142,6 +187,8 @@ CONFIG_RT_LWIP_TCP_WND=8196 CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 @@ -151,69 +198,165 @@ CONFIG_SO_REUSE=1 CONFIG_LWIP_SO_RCVTIMEO=1 CONFIG_LWIP_SO_SNDTIMEO=1 CONFIG_LWIP_SO_RCVBUF=1 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_DEBUG is not set # # Modbus master and slave stack # # CONFIG_RT_USING_MODBUS is not set -# CONFIG_RT_USING_NETUTILS is not set # -# RT-Thread UI Engine +# AT commands # -# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set # -# RT-Thread online packages +# VBUS(Virtual Software BUS) # +# CONFIG_RT_USING_VBUS is not set # -# system packages +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages # -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_SQLITE is not set # # IoT - internet of things # # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# # # Marvell WiFi # -# CONFIG_PKG_USING_MARVELLWIFI is not set +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set # # security packages # # CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set # # language packages # +# CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set # # multimedia packages # +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set # # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set # # miscellaneous packages # -# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # -# BSP_SPECIAL CONFIG +# samples: kernel and components samples # +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set CONFIG_RT_USING_UART0=y diff --git a/bsp/tm4c129x/drivers/drv_eth.c b/bsp/tm4c129x/drivers/drv_eth.c index baa46f1f014..f634b5465e0 100644 --- a/bsp/tm4c129x/drivers/drv_eth.c +++ b/bsp/tm4c129x/drivers/drv_eth.c @@ -248,11 +248,11 @@ volatile uint32_t g_ui32AbnormalInts; typedef struct { - /* inherit from ethernet device */ - struct eth_device parent; - tStellarisIF* dma_if; - /* for rx_thread async get pbuf */ - rt_mailbox_t rx_pbuf_mb; + /* inherit from ethernet device */ + struct eth_device parent; + tStellarisIF* dma_if; + /* for rx_thread async get pbuf */ + rt_mailbox_t rx_pbuf_mb; } net_device; typedef net_device* net_device_t; @@ -862,8 +862,8 @@ tivaif_receive(net_device_t dev) { #else //if(tcpip_input(pBuf, psNetif) != RT_EOK) - if((rt_mb_send(dev->rx_pbuf_mb, (rt_uint32_t)pBuf) != RT_EOK) || - (eth_device_ready(&(dev->parent)) != RT_EOK)) + if((rt_mb_send(dev->rx_pbuf_mb, (rt_uint32_t)pBuf) != RT_EOK) || + (eth_device_ready(&(dev->parent)) != RT_EOK)) { #endif /* drop the packet */ @@ -950,10 +950,10 @@ tivaif_process_phy_interrupt(net_device_t dev) */ ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); - /* - * Dummy read PHY REG EPHY_BMSR, it will force update the EPHY_STS register - */ - EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMSR); + /* + * Dummy read PHY REG EPHY_BMSR, it will force update the EPHY_STS register + */ + EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMSR); /* Read the current PHY status. */ ui16Status = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_STS); @@ -968,7 +968,7 @@ tivaif_process_phy_interrupt(net_device_t dev) netif_set_link_up(psNetif); #else //tcpip_callback((tcpip_callback_fn)netif_set_link_up, psNetif); - eth_device_linkchange(&(dev->parent), RT_TRUE); + eth_device_linkchange(&(dev->parent), RT_TRUE); #endif /* In this case we drop through since we may need to reconfigure @@ -982,7 +982,7 @@ tivaif_process_phy_interrupt(net_device_t dev) netif_set_link_down(psNetif); #else //tcpip_callback((tcpip_callback_fn)netif_set_link_down, psNetif); - eth_device_linkchange(&(dev->parent), RT_FALSE); + eth_device_linkchange(&(dev->parent), RT_FALSE); #endif } } @@ -1168,40 +1168,40 @@ void lwIPEthernetIntHandler(void) // OUI:00-12-37 (hex) Texas Instruments, only for test static int tiva_eth_mac_addr_init(void) { - int retVal =0; - uint32_t ulUser[2]; - uint8_t mac_addr[6]; - - MAP_FlashUserGet(&ulUser[0], &ulUser[1]); - if((ulUser[0] == 0xffffffff) || (ulUser[1] == 0xffffffff)) - { - rt_kprintf("Fail to get mac address from eeprom.\n"); - rt_kprintf("Using default mac address\n"); - // OUI:00-12-37 (hex) Texas Instruments, only for test - // Configure the hardware MAC address - ulUser[0] = 0x00371200; - ulUser[1] = 0x00563412; - //FlashUserSet(ulUser0, ulUser1); - retVal =-1; - } - - - //Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC - //address needed to program the hardware registers, then program the MAC - //address into the Ethernet Controller registers. - - mac_addr[0] = ((ulUser[0] >> 0) & 0xff); - mac_addr[1] = ((ulUser[0] >> 8) & 0xff); - mac_addr[2] = ((ulUser[0] >> 16) & 0xff); - mac_addr[3] = ((ulUser[1] >> 0) & 0xff); - mac_addr[4] = ((ulUser[1] >> 8) & 0xff); - mac_addr[5] = ((ulUser[1] >> 16) & 0xff); - - // + int retVal =0; + uint32_t ulUser[2]; + uint8_t mac_addr[6]; + + MAP_FlashUserGet(&ulUser[0], &ulUser[1]); + if((ulUser[0] == 0xffffffff) || (ulUser[1] == 0xffffffff)) + { + rt_kprintf("Fail to get mac address from eeprom.\n"); + rt_kprintf("Using default mac address\n"); + // OUI:00-12-37 (hex) Texas Instruments, only for test + // Configure the hardware MAC address + ulUser[0] = 0x00371200; + ulUser[1] = 0x00563412; + //FlashUserSet(ulUser0, ulUser1); + retVal =-1; + } + + + //Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC + //address needed to program the hardware registers, then program the MAC + //address into the Ethernet Controller registers. + + mac_addr[0] = ((ulUser[0] >> 0) & 0xff); + mac_addr[1] = ((ulUser[0] >> 8) & 0xff); + mac_addr[2] = ((ulUser[0] >> 16) & 0xff); + mac_addr[3] = ((ulUser[1] >> 0) & 0xff); + mac_addr[4] = ((ulUser[1] >> 8) & 0xff); + mac_addr[5] = ((ulUser[1] >> 16) & 0xff); + + // // Program the hardware with its MAC address (for filtering). // MAP_EMACAddrSet(EMAC0_BASE, 0, mac_addr); - return retVal; + return retVal; } void tiva_eth_lowlevel_init(void) @@ -1214,7 +1214,7 @@ static int tiva_eth_mac_addr_init(void) MAP_GPIOPinConfigure(GPIO_PF4_EN0LED1); GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0); GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_4); - + // // Enable the ethernet peripheral. // @@ -1243,7 +1243,7 @@ static int tiva_eth_mac_addr_init(void) // // Internal PHY is not present on this part so hang here. // - rt_kprintf("Internal PHY is not present on this part.\n"); + rt_kprintf("Internal PHY is not present on this part.\n"); while(1) { } @@ -1283,17 +1283,17 @@ static int tiva_eth_mac_addr_init(void) EMAC_MODE_TX_STORE_FORWARD | EMAC_MODE_TX_THRESHOLD_64_BYTES | EMAC_MODE_RX_THRESHOLD_64_BYTES), 0); - - EMACIntRegister(EMAC0_BASE, lwIPEthernetIntHandler); + + EMACIntRegister(EMAC0_BASE, lwIPEthernetIntHandler); } static rt_err_t eth_dev_init(rt_device_t device) { - net_device_t net_dev = (net_device_t)device; - struct netif *psNetif = (net_dev->parent.netif); - - LWIP_ASSERT("psNetif != NULL", (psNetif != NULL)); + net_device_t net_dev = (net_device_t)device; + struct netif *psNetif = (net_dev->parent.netif); + + LWIP_ASSERT("psNetif != NULL", (psNetif != NULL)); #if LWIP_NETIF_HOSTNAME /* Initialize interface hostname */ @@ -1320,91 +1320,91 @@ static rt_err_t eth_dev_init(rt_device_t device) /* control the interface */ static rt_err_t eth_dev_control(rt_device_t dev, int cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) - MAP_EMACAddrGet(EMAC0_BASE, 0, (uint8_t*)args); - else - return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) + MAP_EMACAddrGet(EMAC0_BASE, 0, (uint8_t*)args); + else + return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; } /* Open the interface */ static rt_err_t eth_dev_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } /* Close the interface */ static rt_err_t eth_dev_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } /* Read */ static rt_size_t eth_dev_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } /* Write */ static rt_size_t eth_dev_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t eth_dev_tx(rt_device_t dev, struct pbuf *p) { - return tivaif_transmit((net_device_t)dev, p); + return tivaif_transmit((net_device_t)dev, p); } static struct pbuf* eth_dev_rx(rt_device_t dev) { - rt_err_t result; - rt_uint32_t temp =0; - net_device_t net_dev = (net_device_t)dev; - result = rt_mb_recv(net_dev->rx_pbuf_mb, &temp, RT_WAITING_NO); - - return (result == RT_EOK)? (struct pbuf*)temp : RT_NULL; + rt_err_t result; + rt_uint32_t temp =0; + net_device_t net_dev = (net_device_t)dev; + result = rt_mb_recv(net_dev->rx_pbuf_mb, &temp, RT_WAITING_NO); + + return (result == RT_EOK)? (struct pbuf*)temp : RT_NULL; } int rt_hw_tiva_eth_init(void) { - rt_err_t result; - - /* Clock GPIO and etc */ - tiva_eth_lowlevel_init(); - tiva_eth_mac_addr_init(); - - /* init rt-thread device interface */ - eth_dev->parent.parent.init = eth_dev_init; - eth_dev->parent.parent.open = eth_dev_open; - eth_dev->parent.parent.close = eth_dev_close; - eth_dev->parent.parent.read = eth_dev_read; - eth_dev->parent.parent.write = eth_dev_write; - eth_dev->parent.parent.control = eth_dev_control; - eth_dev->parent.eth_rx = eth_dev_rx; - eth_dev->parent.eth_tx = eth_dev_tx; - - result = rt_mb_init(ð_rx_pbuf_mb, "epbuf", + rt_err_t result; + + /* Clock GPIO and etc */ + tiva_eth_lowlevel_init(); + tiva_eth_mac_addr_init(); + + /* init rt-thread device interface */ + eth_dev->parent.parent.init = eth_dev_init; + eth_dev->parent.parent.open = eth_dev_open; + eth_dev->parent.parent.close = eth_dev_close; + eth_dev->parent.parent.read = eth_dev_read; + eth_dev->parent.parent.write = eth_dev_write; + eth_dev->parent.parent.control = eth_dev_control; + eth_dev->parent.eth_rx = eth_dev_rx; + eth_dev->parent.eth_tx = eth_dev_tx; + + result = rt_mb_init(ð_rx_pbuf_mb, "epbuf", &rx_pbuf_mb_pool[0], sizeof(rx_pbuf_mb_pool)/4, RT_IPC_FLAG_FIFO); - RT_ASSERT(result == RT_EOK); - eth_dev->rx_pbuf_mb = ð_rx_pbuf_mb; - - - result = eth_device_init(&(eth_dev->parent), "e0"); - return result; + RT_ASSERT(result == RT_EOK); + eth_dev->rx_pbuf_mb = ð_rx_pbuf_mb; + + + result = eth_device_init(&(eth_dev->parent), "e0"); + return result; } // eth_device_init using malloc // We use INIT_COMPONENT_EXPORT insted of INIT_BOARD_EXPORT @@ -1416,28 +1416,28 @@ INIT_COMPONENT_EXPORT(rt_hw_tiva_eth_init); #include "finsh.h" void PHY_Read(uint8_t addr) { - uint16_t data = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, addr); - rt_kprintf("R PHY_REG[0x%02X] = 0x%04X\n", addr, data); + uint16_t data = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, addr); + rt_kprintf("R PHY_REG[0x%02X] = 0x%04X\n", addr, data); } FINSH_FUNCTION_EXPORT(PHY_Read, (add)); void PHY_Write(uint8_t addr , uint16_t data) { EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, addr, data); - rt_kprintf("W PHY_REG[0x%02X] = 0x%04X\n", addr, data); + rt_kprintf("W PHY_REG[0x%02X] = 0x%04X\n", addr, data); } FINSH_FUNCTION_EXPORT(PHY_Write, (add, data)); void PHY_SetAdd(uint8_t addr0, uint8_t addr1, uint8_t addr2, uint8_t addr3, uint8_t addr4, uint8_t addr5) { - uint32_t ulUser[2]; - ulUser[0] = (((addr2<<8)|addr1)<<8)|addr0; - ulUser[1] = (((addr5<<8)|addr4)<<8)|addr3; - - MAP_FlashUserSet(ulUser[0], ulUser[1]); - MAP_FlashUserSave(); - rt_kprintf("Save to EEPROM. please reboot."); + uint32_t ulUser[2]; + ulUser[0] = (((addr2<<8)|addr1)<<8)|addr0; + ulUser[1] = (((addr5<<8)|addr4)<<8)|addr3; + + MAP_FlashUserSet(ulUser[0], ulUser[1]); + MAP_FlashUserSave(); + rt_kprintf("Save to EEPROM. please reboot."); } FINSH_FUNCTION_EXPORT(PHY_SetAdd, (add0-add5)); #endif //RT_USING_FINSH diff --git a/bsp/tm4c129x/rtconfig.h b/bsp/tm4c129x/rtconfig.h index ec559845e21..0682cd79f1b 100644 --- a/bsp/tm4c129x/rtconfig.h +++ b/bsp/tm4c129x/rtconfig.h @@ -8,17 +8,18 @@ #define RT_NAME_MAX 8 #define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 -#define RT_DEBUG #define RT_USING_OVERFLOW_CHECK -#define RT_DEBUG_INIT 0 -/* RT_DEBUG_THREAD is not set */ #define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG /* Inter-Thread communication */ @@ -27,15 +28,13 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ #define RT_USING_MEMPOOL #define RT_USING_MEMHEAP -#define RT_USING_HEAP #define RT_USING_SMALL_MEM -/* RT_USING_SLAB is not set */ +#define RT_USING_HEAP /* Kernel Device Object */ @@ -43,70 +42,64 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -/* RT_USING_MODULE is not set */ +#define RT_VER_NUM 0x30102 /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 /* C++ features */ -/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ #define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" #define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ -/* FINSH_USING_MSH is not set */ /* Device virtual file system */ -/* RT_USING_DFS is not set */ /* Device Drivers */ #define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_I2C is not set */ -/* RT_USING_PIN is not set */ -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_RTC is not set */ -/* RT_USING_SDIO is not set */ -/* RT_USING_SPI is not set */ -/* RT_USING_WDT is not set */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ +#define RT_SERIAL_USING_DMA + +/* Using WiFi */ + + +/* Using USB */ + /* POSIX layer and C standard library */ #define RT_USING_LIBC -/* RT_USING_PTHREADS is not set */ -/* Network stack */ +/* Network */ + +/* Socket abstraction layer */ + /* light weight TCP/IP stack */ #define RT_USING_LWIP #define RT_USING_LWIP141 -/* RT_USING_LWIP202 is not set */ -/* RT_LWIP_IGMP is not set */ #define RT_LWIP_ICMP -/* RT_LWIP_SNMP is not set */ #define RT_LWIP_DNS #define RT_LWIP_DHCP #define IP_SOF_BROADCAST 1 #define IP_SOF_BROADCAST_RECV 1 -/* LWIP_USING_DHCPD is not set */ /* Static IPv4 Address */ @@ -115,10 +108,7 @@ #define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_UDP #define RT_LWIP_TCP -/* RT_LWIP_RAW is not set */ -/* RT_LWIP_PPP is not set */ -/* RT_LWIP_PPPOE is not set */ -/* RT_LWIP_PPPOS is not set */ +#define RT_MEMP_NUM_NETCONN 8 #define RT_LWIP_PBUF_NUM 16 #define RT_LWIP_RAW_PCB_NUM 4 #define RT_LWIP_UDP_PCB_NUM 4 @@ -132,62 +122,63 @@ #define RT_LWIP_ETHTHREAD_PRIORITY 12 #define RT_LWIP_ETHTHREAD_STACKSIZE 1024 #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 -/* RT_LWIP_REASSEMBLY_FRAG is not set */ #define LWIP_NETIF_STATUS_CALLBACK 1 #define SO_REUSE 1 #define LWIP_SO_RCVTIMEO 1 #define LWIP_SO_SNDTIMEO 1 #define LWIP_SO_RCVBUF 1 +#define LWIP_NETIF_LOOPBACK 0 /* Modbus master and slave stack */ -/* RT_USING_MODBUS is not set */ -/* RT_USING_NETUTILS is not set */ -/* RT-Thread UI Engine */ +/* AT commands */ -/* PKG_USING_GUIENGINE is not set */ -/* RT-Thread online packages */ +/* VBUS(Virtual Software BUS) */ -/* system packages */ -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_SQLITE is not set */ +/* Utilities */ + + +/* RT-Thread online packages */ /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_EZXML is not set */ + +/* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_MARVELLWIFI is not set */ + +/* Wiced WiFi */ + + +/* IoT Cloud */ + /* security packages */ -/* PKG_USING_MBEDTLS is not set */ /* language packages */ -/* PKG_USING_JERRYSCRIPT is not set */ /* multimedia packages */ + /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYLOGGER is not set */ + +/* system packages */ + + +/* peripheral libraries and drivers */ + /* miscellaneous packages */ -/* PKG_USING_HELLO is not set */ -/* BSP_SPECIAL CONFIG */ +/* samples: kernel and components samples */ #define RT_USING_UART0 diff --git a/bsp/tms320f28379d/.ccsproject b/bsp/tms320f28379d/.ccsproject new file mode 100644 index 00000000000..e3dbeec008c --- /dev/null +++ b/bsp/tms320f28379d/.ccsproject @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/bsp/tms320f28379d/.config b/bsp/tms320f28379d/.config new file mode 100644 index 00000000000..d62b1e40c82 --- /dev/null +++ b/bsp/tms320f28379d/.config @@ -0,0 +1,304 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_SOC_TMS320F28X=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +CONFIG_RT_THREAD_PRIORITY_8=y +# CONFIG_RT_THREAD_PRIORITY_32 is not set +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=8 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_ARCH_TIDSP=y +CONFIG_ARCH_TIDSP_C28X=y +CONFIG_ARCH_CPU_STACK_GROWS_UPWARD=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +# CONFIG_RT_USING_USER_MAIN is not set + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +# CONFIG_RT_USING_FINSH is not set + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set diff --git a/bsp/tms320f28379d/.cproject b/bsp/tms320f28379d/.cproject new file mode 100644 index 00000000000..d2f74c22d6d --- /dev/null +++ b/bsp/tms320f28379d/.cproject @@ -0,0 +1,182 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/tms320f28379d/.project b/bsp/tms320f28379d/.project new file mode 100644 index 00000000000..bab120e2b96 --- /dev/null +++ b/bsp/tms320f28379d/.project @@ -0,0 +1,39 @@ + + + rt-thread + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Kernel + 2 + PARENT-2-PROJECT_LOC/src + + + c28x + 2 + PARENT-2-PROJECT_LOC/libcpu/ti-dsp/c28x + + + diff --git a/bsp/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs b/bsp/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000000..f653028c53a --- /dev/null +++ b/bsp/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/bsp/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs b/bsp/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000000..2adc7b1ddeb --- /dev/null +++ b/bsp/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/bsp/tms320f28379d/.settings/org.eclipse.core.resources.prefs b/bsp/tms320f28379d/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000000..288ca292c62 --- /dev/null +++ b/bsp/tms320f28379d/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,20 @@ +eclipse.preferences.version=1 +encoding//Debug/Kernel/subdir_rules.mk=UTF-8 +encoding//Debug/Kernel/subdir_vars.mk=UTF-8 +encoding//Debug/applications/subdir_rules.mk=UTF-8 +encoding//Debug/applications/subdir_vars.mk=UTF-8 +encoding//Debug/c28x/subdir_rules.mk=UTF-8 +encoding//Debug/c28x/subdir_vars.mk=UTF-8 +encoding//Debug/drivers/subdir_rules.mk=UTF-8 +encoding//Debug/drivers/subdir_vars.mk=UTF-8 +encoding//Debug/libraries/common/source/subdir_rules.mk=UTF-8 +encoding//Debug/libraries/common/source/subdir_vars.mk=UTF-8 +encoding//Debug/libraries/headers/cmd/subdir_rules.mk=UTF-8 +encoding//Debug/libraries/headers/cmd/subdir_vars.mk=UTF-8 +encoding//Debug/libraries/headers/source/subdir_rules.mk=UTF-8 +encoding//Debug/libraries/headers/source/subdir_vars.mk=UTF-8 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/bsp/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd b/bsp/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd new file mode 100644 index 00000000000..b29ee84ff0c --- /dev/null +++ b/bsp/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd @@ -0,0 +1,135 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 + RAMGS15 : origin = 0x01B000, length = 0x001000 + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 + RAMGS13 : origin = 0x019000, length = 0x001000 + + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1 + .esysmem : >> RAMGS2 | RAMGS3 | RAMGS4 | RAMGS5 | RAMGS6 | RAMGS7 | RAMGS8 | RAMGS9 | RAMGS10 | RAMGS11 | RAMGS12 | RAMGS13 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/Kconfig b/bsp/tms320f28379d/Kconfig new file mode 100644 index 00000000000..de11cb4d792 --- /dev/null +++ b/bsp/tms320f28379d/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config SOC_TMS320F28X + bool + select ARCH_TIDSP_C28X + default y + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" diff --git a/bsp/tms320f28379d/README.md b/bsp/tms320f28379d/README.md new file mode 100644 index 00000000000..b1d60dfd6f8 --- /dev/null +++ b/bsp/tms320f28379d/README.md @@ -0,0 +1,53 @@ +# TMS320F28379D + + +## 1. 简介 + +TMS320F28379D BSP 基于 C2000 Delfino MCU F28379D LaunchPad 开发套件开发。 +TMS320F28379D 是一款功能强大的 32 位浮点微控制器单元 (MCU)，针对高级闭环控制应用而设计，例如工业驱动器和伺服电机控制、太阳能逆变器和转换器、数字电源、电力输送以及电力线通信。包括如下硬件特性： + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| TMS320F28379D | +|多核 CPU| 两个 TMS320C28x 32 位 CPU +|| 两个可编程控制律加速器 (CLA) | +|主频| 200MHz | +|CLA 频率| 200MHz | +|总处理能力| 800MIPS | +|片内SRAM| 204kB | +|片内Flash| 1MB | + +## 2. 编译说明 + +编译使用 Code Composer Studio，在 Code Composer Studio 8.1.0 使用 TI v18.1.3.LTS 编译器已测试编译通过。 + +## 3. 烧写及执行 + +连接开发板电源后，使用 CCS 中的烧写功能可直接通过板载 XDS100v2 仿真器烧写并执行。 + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| CPU Timer | 支持 | | +| GPIO | 支持 | | +| SCI | 开发中 | SCIA/B，预计2018年9月底实现 | +| ePWM | | 预计2019年10月支持 | +| ADC | | 预计2019年10月支持 | +| DAC | | 预计2019/Q4支持| +| I2C | | | +| SPI | | | +| CAN | | | +| eCAP | | | + +## 5. 联系人信息 + +维护人：xuzhuoyi < xzy476386434@vip.qq.com > + +## 6. 参考 + +* [C2000 Delfino MCU F28379D LaunchPad 开发套件][1] +* TMS320F28379D [相关技术文档][2] + + [1]: http://www.ti.com.cn/tool/cn/launchxl-f28379d + [2]: http://www.ti.com.cn/product/cn/tms320f28379d/technicaldocuments diff --git a/bsp/tms320f28379d/applications/application.c b/bsp/tms320f28379d/applications/application.c new file mode 100644 index 00000000000..cecd70fa394 --- /dev/null +++ b/bsp/tms320f28379d/applications/application.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + * 2014-04-27 Bernard make code cleanup. + */ + +#include +#include + +void rt_init_thread_entry(void* parameter) +{ + /* initialization RT-Thread Components */ + rt_components_init(); + +} + +int rt_application_init() +{ + rt_thread_t tid; + + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX/3, 20); + + if (tid != RT_NULL) + rt_thread_startup(tid); + + return 0; +} diff --git a/bsp/stm32f107/applications/startup.c b/bsp/tms320f28379d/applications/startup.c similarity index 77% rename from bsp/stm32f107/applications/startup.c rename to bsp/tms320f28379d/applications/startup.c index d64943c32ba..301e63a00a6 100644 --- a/bsp/stm32f107/applications/startup.c +++ b/bsp/tms320f28379d/applications/startup.c @@ -6,31 +6,20 @@ * Change Logs: * Date Author Notes * 2006-08-31 Bernard first implementation - * 2011-06-05 Bernard modify for STM32F107 version + * 2018-09-02 xuzhuoyi modify for TMS320F28379D version */ +#include #include #include + #include "board.h" -/** - * @addtogroup STM32 - */ /*@{*/ extern int rt_application_init(void); -#if defined(__CC_ARM) || defined(__CLANG_ARM) -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define STM32_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define STM32_SRAM_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define STM32_SRAM_BEGIN (&__bss_end) -#endif /******************************************************************************* * Function Name : assert_failed @@ -41,7 +30,7 @@ extern int __bss_end; * Output : None * Return : None *******************************************************************************/ -void assert_failed(u8* file, u32 line) +void assert_failed(uint16_t* file, uint32_t line) { rt_kprintf("\n\r Wrong parameter value detected on\r\n"); rt_kprintf(" file %s\r\n", file); @@ -70,10 +59,6 @@ void rtthread_startup(void) /* init timer system */ rt_system_timer_init(); -#ifdef RT_USING_HEAP - rt_system_heap_init((void*)STM32_SRAM_BEGIN, (void*)STM32_SRAM_END); -#endif - /* init scheduler system */ rt_system_scheduler_init(); diff --git a/bsp/tms320f28379d/drivers/board.c b/bsp/tms320f28379d/drivers/board.c new file mode 100644 index 00000000000..7960d80d1b7 --- /dev/null +++ b/bsp/tms320f28379d/drivers/board.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2018-09-02 xuzhuoyi modify for TMS320F28379D version + */ +#include +#include "board.h" +#include "F28x_Project.h" + +extern interrupt void RTOSINT_Handler(); + + +/** + * This is the timer interrupt service routine. + * + */ +interrupt void cpu_timer2_isr (void) +{ + CpuTimer2Regs.TCR.all = 0x8000; + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + /* leave interrupt */ + rt_interrupt_leave(); +} + + +/** + * This function will initial STM32 board. + */ +void rt_hw_board_init() +{ + /* Configure the system clock @ 84 Mhz */ + InitSysCtrl(); + + DINT; + InitPieCtrl(); + + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TIMER2_INT = &cpu_timer2_isr; + PieVectTable.RTOS_INT = &RTOSINT_Handler; + EDIS; + + InitCpuTimers(); + ConfigCpuTimer(&CpuTimer2, 200, 1000000 / RT_TICK_PER_SECOND); + CpuTimer2Regs.TCR.all = 0x4000; + IER |= M_INT14; + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} diff --git a/bsp/tms320f28379d/drivers/board.h b/bsp/tms320f28379d/drivers/board.h new file mode 100644 index 00000000000..2a221a73f9d --- /dev/null +++ b/bsp/tms320f28379d/drivers/board.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2018-09-02 xuzhuoyi modify for TMS320F28379D version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ +#include + +#define C28X_SRAM_END 0x00020000 + + +#define HEAP_BEGIN 0x0000E000 +#define HEAP_END C28X_SRAM_END +extern void rt_hw_board_init(void); +#endif + diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_CLA_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_CLA_lnk_cpu1.cmd new file mode 100644 index 00000000000..9bc86fabf85 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_CLA_lnk_cpu1.cmd @@ -0,0 +1,178 @@ +// The user must define CLA_C in the project linker settings if using the +// CLA C compiler +// Project Properties -> C2000 Linker -> Advanced Options -> Command File +// Preprocessing -> --define +#ifdef CLA_C +// Define a size for the CLA scratchpad area that will be used +// by the CLA compiler for local symbols and temps +// Also force references to the special symbols that mark the +// scratchpad are. +CLA_SCRATCHPAD_SIZE = 0x100; +--undef_sym=__cla_scratchpad_end +--undef_sym=__cla_scratchpad_start +#endif //CLA_C + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + /* RAMLS4 : origin = 0x00A000, length = 0x000800 */ + /* RAMLS5 : origin = 0x00A800, length = 0x000800 */ + RAMLS4_5 : origin = 0x00A000, length = 0x001000 + + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + EMIF2_CS0n : origin = 0x90000000, length = 0x10000000 + EMIF2_CS2n : origin = 0x00002000, length = 0x00001000 + + CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080 + CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : > FLASHB PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAMLS2 PAGE = 1 + .esysmem : > RAMLS2 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : > FLASHB PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + .em2_cs0 : > EMIF2_CS0n, PAGE = 1 + .em2_cs2 : > EMIF2_CS2n, PAGE = 1 + + /* CLA specific sections */ + Cla1Prog : LOAD = FLASHD, + RUN = RAMLS4_5, + LOAD_START(_Cla1funcsLoadStart), + LOAD_END(_Cla1funcsLoadEnd), + RUN_START(_Cla1funcsRunStart), + LOAD_SIZE(_Cla1funcsLoadSize), + PAGE = 0, ALIGN(4) + + CLADataLS0 : > RAMLS0, PAGE=0 + CLADataLS1 : > RAMLS1, PAGE=0 + + Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1 + CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMD0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMD0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + +#ifdef CLA_C + /* CLA C compiler sections */ + // + // Must be allocated to memory the CLA has write access to + // + CLAscratch : + { *.obj(CLAscratch) + . += CLA_SCRATCHPAD_SIZE; + *.obj(CLAscratch_end) } > RAMLS1, PAGE = 0 + + .scratchpad : > RAMLS1, PAGE = 0 + .bss_cla : > RAMLS1, PAGE = 0 + .const_cla : LOAD = FLASHB, + RUN = RAMLS1, + RUN_START(_Cla1ConstRunStart), + LOAD_START(_Cla1ConstLoadStart), + LOAD_SIZE(_Cla1ConstLoadSize), + PAGE = 0 +#endif //CLA_C +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_IQMATH_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_IQMATH_lnk_cpu1.cmd new file mode 100644 index 00000000000..afd9da2351d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_IQMATH_lnk_cpu1.cmd @@ -0,0 +1,134 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : > FLASHB PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAMLS5 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : > FLASHB PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* Allocate IQ math areas: */ + IQmath : > FLASHB, PAGE = 0, ALIGN(4) /* Math Code */ + IQmathTables : > FLASHC, PAGE = 0, ALIGN(4) +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_SGEN_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_SGEN_lnk_cpu1.cmd new file mode 100644 index 00000000000..ffcab867e81 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_SGEN_lnk_cpu1.cmd @@ -0,0 +1,147 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + .cio : > RAMGS2, PAGE = 1 + + /* Sine Table */ + SINTBL : > FLASHN, PAGE = 1 + + /* Data Log */ + DLOG : > RAMGS3, PAGE = 1 + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_TMU_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_TMU_lnk_cpu1.cmd new file mode 100644 index 00000000000..e2d9e19e0fe --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_TMU_lnk_cpu1.cmd @@ -0,0 +1,136 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2_GS4 : origin = 0x00E000, length = 0x003000 + /* + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + */ + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMGS1 PAGE = 1 + .ebss : > RAMGS2_GS4 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + .sysmem : > RAMGS1, PAGE = 1 + .cio : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_afe031_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_afe031_lnk_cpu1.cmd new file mode 100644 index 00000000000..323926d7837 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_afe031_lnk_cpu1.cmd @@ -0,0 +1,170 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x001800 + // RAMLS3 : origin = 0x009800, length = 0x000800 + // RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : >> RAMGS0 | RAMGS1 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + .cio : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + ramls2 : > RAMLS2, PAGE = 0 +// SINETABLE : > FLASHF PAGE = 0, ALIGN(4) + +fsk_corr_lib_data : > RAMGS5 PAGE = 1 /* Flash block for lib data */ + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 , + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 +SINETABLE : {} LOAD = FLASHF, + RUN = RAMLS2 , + LOAD_START(_SineTableLoadStart), + LOAD_SIZE(_SineTableLoadSize), + LOAD_END(_SineTableLoadEnd), + RUN_START(_SineTableRunStart), + RUN_SIZE(_SineTableRunSize), + RUN_END(_SineTableRunEnd), + PAGE = 0, ALIGN(4) + + #else +SINETABLE : LOAD = FLASHF, + RUN = RAMLS2 , + LOAD_START(_SineTableLoadStart), + LOAD_SIZE(_SineTableLoadSize), + LOAD_END(_SineTableLoadEnd), + RUN_START(_SineTableRunStart), + RUN_SIZE(_SineTableRunSize), + RUN_END(_SineTableRunEnd), + PAGE = 0, ALIGN(4) + + #endif +#endif + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1.cmd new file mode 100644 index 00000000000..b1dadb83512 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1.cmd @@ -0,0 +1,142 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + .cio : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1_far.cmd new file mode 100644 index 00000000000..f8744f39352 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu1_far.cmd @@ -0,0 +1,156 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + EMIF2_CS0n : origin = 0x90000000, length = 0x10000000 + EMIF2_CS2n : origin = 0x00002000, length = 0x00001000 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + .farbss : > EMIF1_CS0n, PAGE = 1 + + .em1_cs0 : > EMIF1_CS0n, PAGE = 1 + .em1_cs2 : > EMIF1_CS2n, PAGE = 1 + .em1_cs3 : > EMIF1_CS3n, PAGE = 1 + .em1_cs4 : > EMIF1_CS4n, PAGE = 1 + .em2_cs0 : > EMIF2_CS0n, PAGE = 1 + .em2_cs2 : > EMIF2_CS2n, PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + .farconst : > EMIF1_CS0n, PAGE = 1 + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2.cmd new file mode 100644 index 00000000000..038dfdbed84 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2.cmd @@ -0,0 +1,114 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000080, length = 0x000380 + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : > FLASHB PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAMLS5 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : > FLASHB PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2_far.cmd new file mode 100644 index 00000000000..bd7aff0faf6 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_FLASH_lnk_cpu2_far.cmd @@ -0,0 +1,120 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000080, length = 0x000380 + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(4) + .pinit : > FLASHB, PAGE = 0, ALIGN(4) + .text : > FLASHB PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > RAMLS5 PAGE = 1 + .esysmem : > RAMLS5 PAGE = 1 + .farbss : > EMIF1_CS0n, PAGE = 1 + /* Initalized sections go in Flash */ + .econst : > FLASHB PAGE = 0, ALIGN(4) + .switch : > FLASHB PAGE = 0, ALIGN(4) + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + .farconst : > EMIF1_CS0n, PAGE = 1 + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_CLA_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_CLA_lnk_cpu1.cmd new file mode 100644 index 00000000000..55100fcccbe --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_CLA_lnk_cpu1.cmd @@ -0,0 +1,135 @@ +// The user must define CLA_C in the project linker settings if using the +// CLA C compiler +// Project Properties -> C2000 Linker -> Advanced Options -> Command File +// Preprocessing -> --define +#ifdef CLA_C +// Define a size for the CLA scratchpad area that will be used +// by the CLA compiler for local symbols and temps +// Also force references to the special symbols that mark the +// scratchpad are. +CLA_SCRATCHPAD_SIZE = 0x100; +--undef_sym=__cla_scratchpad_end +--undef_sym=__cla_scratchpad_start +#endif //CLA_C + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMD1 : origin = 0x00B800, length = 0x000800 + /* RAMLS4 : origin = 0x00A000, length = 0x000800 */ + /* RAMLS5 : origin = 0x00A800, length = 0x000800 */ + RAMLS4_5 : origin = 0x00A000, length = 0x001000 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + EMIF2_CS0n : origin = 0x90000000, length = 0x10000000 + EMIF2_CS2n : origin = 0x00002000, length = 0x00001000 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080 + CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >> RAMM0 | RAMD0 | RAMD1, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS2, PAGE = 1 + .econst : > RAMLS3, PAGE = 1 + .esysmem : > RAMLS3, PAGE = 1 + Filter_RegsFile : > RAMGS0, PAGE = 1 + + .em1_cs0 : > EMIF1_CS0n, PAGE = 1 + .em1_cs2 : > EMIF1_CS2n, PAGE = 1 + .em1_cs3 : > EMIF1_CS3n, PAGE = 1 + .em1_cs4 : > EMIF1_CS4n, PAGE = 1 + .em2_cs0 : > EMIF2_CS0n, PAGE = 1 + .em2_cs2 : > EMIF2_CS2n, PAGE = 1 + + /* CLA specific sections */ + Cla1Prog : > RAMLS4_5, PAGE=0 + + CLADataLS0 : > RAMLS0, PAGE=1 + CLADataLS1 : > RAMLS1, PAGE=1 + + Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1 + CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1 + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + +#ifdef CLA_C + /* CLA C compiler sections */ + // + // Must be allocated to memory the CLA has write access to + // + CLAscratch : + { *.obj(CLAscratch) + . += CLA_SCRATCHPAD_SIZE; + *.obj(CLAscratch_end) } > RAMLS1, PAGE = 1 + + .scratchpad : > RAMLS1, PAGE = 1 + .bss_cla : > RAMLS1, PAGE = 1 + .const_cla : > RAMLS1, PAGE = 1 +#endif //CLA_C +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu1.cmd new file mode 100644 index 00000000000..690c322d800 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu1.cmd @@ -0,0 +1,38 @@ +/* Linker map for Soprano Shared Memory. */ + +MEMORY +{ +PAGE 0 : /* Program memory. This is a legacy description since the C28 has a unified memory model. */ + + +PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unified memory model. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +* =========================================================================== +* End of file. +* =========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu2.cmd new file mode 100644 index 00000000000..ca157058ee1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IPC_lnk_cpu2.cmd @@ -0,0 +1,37 @@ +/* Linker map for Soprano Shared Memory. */ + +MEMORY +{ +PAGE 0 : /* Program memory. This is a legacy description since the C28 has a unified memory model. */ + +PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unified memory model. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +* =========================================================================== +* End of file. +* =========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IQMATH_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IQMATH_lnk_cpu1.cmd new file mode 100644 index 00000000000..405efe5900e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_IQMATH_lnk_cpu1.cmd @@ -0,0 +1,103 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1_LS2 : origin = 0x008800, length = 0x001000 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMM0 | RAMD0 | RAMLS0 | RAMLS1_LS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + Filter_RegsFile : > RAMGS0, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 + + /* Allocate IQ math areas: */ + IQmath : > RAMLS0, PAGE = 0 /* Math Code */ + IQmathTables : > RAMLS1_LS2, PAGE = 0 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SGEN_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SGEN_lnk_cpu1.cmd new file mode 100644 index 00000000000..0f42056151d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SGEN_lnk_cpu1.cmd @@ -0,0 +1,106 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + Filter_RegsFile : > RAMGS0, PAGE = 1 + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + .cio : > RAMGS2, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* Sine Table */ + SINTBL : > RAMGS2, PAGE = 1 + + /* Data Log */ + DLOG : > RAMGS3, PAGE = 1 + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SWPrioritizedISR_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SWPrioritizedISR_lnk_cpu1.cmd new file mode 100644 index 00000000000..b5c4b58c78f --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_SWPrioritizedISR_lnk_cpu1.cmd @@ -0,0 +1,89 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + RAMGS0_2 : origin = 0x00C000, length = 0x003000 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMGS0_2, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_TMU_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_TMU_lnk_cpu1.cmd new file mode 100644 index 00000000000..22e06c6e580 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_TMU_lnk_cpu1.cmd @@ -0,0 +1,97 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMLS5 : origin = 0x00A800, length = 0x000800 + RAMGS0 : origin = 0x00C000, length = 0x001000 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2_GS4 : origin = 0x00E000, length = 0x003000 + /* + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + */ + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text :>> RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMLS5 | RAMGS0, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMGS1, PAGE = 1 + .ebss : > RAMGS2_GS4,PAGE = 1 + .econst : > RAMGS1, PAGE = 1 + .esysmem : > RAMGS1, PAGE = 1 + Filter_RegsFile : > RAMGS1, PAGE = 1 + + .sysmem : > RAMGS1, PAGE = 1 + .cio : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_afe031_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_afe031_lnk_cpu1.cmd new file mode 100644 index 00000000000..5da6b7958cd --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_afe031_lnk_cpu1.cmd @@ -0,0 +1,99 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS234 : origin = 0x009000, length = 0x001800 + // RAMLS3 : origin = 0x009800, length = 0x000800 + // RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMLS5 : origin = 0x00A800, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >> RAMD0 | RAMLS0 | RAMLS1, PAGE = 0 + .cinit : >RAMM0 , PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : >> RAMGS0, PAGE = 1 + .econst : >> RAMLS234, PAGE = 0 + .esysmem : > RAMLS5, PAGE = 0 + Filter_RegsFile : > RAMGS0, PAGE = 1 + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS3, PAGE = 1 + + SINETABLE : > RAMLS234 PAGE = 0 /* Ram block for SINETABLE data */ + fsk_corr_lib_data : > RAMGS5, PAGE = 1 /* Ram block for lib data */ + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1.cmd new file mode 100644 index 00000000000..1561ba58b72 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1.cmd @@ -0,0 +1,103 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + Filter_RegsFile : > RAMGS0, PAGE = 1 + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_USB.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_USB.cmd new file mode 100644 index 00000000000..0b470f5951a --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_USB.cmd @@ -0,0 +1,97 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x002000 + + + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS01 : origin = 0x008000, length = 0x001000 +/* RAMLS1 : origin = 0x008800, length = 0x000800 */ + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3_RAMLS4_RAMLS5 : origin = 0x009800, length = 0x001800 +/* RAMLS3 : origin = 0x009800, length = 0x000800 */ +/* RAMLS4 : origin = 0x00A000, length = 0x000800 */ +/* RAMLS5 : origin = 0x00A800, length = 0x000800 */ + + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >> RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3 | RAMGS4 | RAMGS5, PAGE = 0 + .cio : > RAMLS3_RAMLS4_RAMLS5, PAGE = 1 + .sysmem : > RAMD1, PAGE = 1 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : >> RAMLS01 | RAMLS2 | RAMLS3_RAMLS4_RAMLS5, PAGE = 1 + .econst : > RAMLS3_RAMLS4_RAMLS5, PAGE = 1 + .esysmem : > RAMLS3_RAMLS4_RAMLS5, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_far.cmd new file mode 100644 index 00000000000..709c0665579 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu1_far.cmd @@ -0,0 +1,121 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + EMIF2_CS0n : origin = 0x90000000, length = 0x10000000 + EMIF2_CS2n : origin = 0x00002000, length = 0x00001000 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMM0 | RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + + .farbss : > EMIF1_CS0n, PAGE = 1 + .farconst : > EMIF1_CS0n, PAGE = 1 + + .em1_cs0 : > EMIF1_CS0n, PAGE = 1 + .em1_cs2 : > EMIF1_CS2n, PAGE = 1 + .em1_cs3 : > EMIF1_CS3n, PAGE = 1 + .em1_cs4 : > EMIF1_CS4n, PAGE = 1 + .em2_cs0 : > EMIF2_CS0n, PAGE = 1 + .em2_cs2 : > EMIF2_CS2n, PAGE = 1 + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2.cmd new file mode 100644 index 00000000000..764ae4bea25 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2.cmd @@ -0,0 +1,75 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000080, length = 0x000380 + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2_far.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2_far.cmd new file mode 100644 index 00000000000..976309764d3 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_cpu2_far.cmd @@ -0,0 +1,83 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000080, length = 0x000380 + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + EMIF1_CS0n : origin = 0x80000000, length = 0x10000000 + EMIF1_CS2n : origin = 0x00100000, length = 0x00200000 + EMIF1_CS3n : origin = 0x00300000, length = 0x00080000 + EMIF1_CS4n : origin = 0x00380000, length = 0x00060000 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + + .farbss : > EMIF1_CS0n, PAGE = 1 + .farconst : > EMIF1_CS0n, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu1.cmd new file mode 100644 index 00000000000..d7f5abe0a1e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu1.cmd @@ -0,0 +1,92 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + SHARERAMGS2 : > RAMGS2, PAGE = 1 + SHARERAMGS3 : > RAMGS3, PAGE = 1 + SHARERAMGS4 : > RAMGS4, PAGE = 1 + SHARERAMGS5 : > RAMGS5, PAGE = 1 + SHARERAMGS6 : > RAMGS6, PAGE = 1 + SHARERAMGS7 : > RAMGS7, PAGE = 1 + SHARERAMGS8 : > RAMGS8, PAGE = 1 + SHARERAMGS9 : > RAMGS9, PAGE = 1 + SHARERAMGS10 : > RAMGS10, PAGE = 1 + SHARERAMGS11 : > RAMGS11, PAGE = 1 + SHARERAMGS12 : > RAMGS12, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS13 : > RAMGS13, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS14 : > RAMGS14, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS15 : > RAMGS15, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu2.cmd new file mode 100644 index 00000000000..da95201cf99 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_RAM_lnk_shared_cpu2.cmd @@ -0,0 +1,92 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000080, length = 0x000380 + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RESET : origin = 0x3FFFC0, length = 0x000002 + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + RAMGS11 : origin = 0x017000, length = 0x001000 + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + .stack : > RAMM1, PAGE = 1 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + SHARERAMGS2 : > RAMGS2, PAGE = 1 + SHARERAMGS3 : > RAMGS3, PAGE = 1 + SHARERAMGS4 : > RAMGS4, PAGE = 1 + SHARERAMGS5 : > RAMGS5, PAGE = 1 + SHARERAMGS6 : > RAMGS6, PAGE = 1 + SHARERAMGS7 : > RAMGS7, PAGE = 1 + SHARERAMGS8 : > RAMGS8, PAGE = 1 + SHARERAMGS9 : > RAMGS9, PAGE = 1 + SHARERAMGS10 : > RAMGS10, PAGE = 1 + SHARERAMGS11 : > RAMGS11, PAGE = 1 + SHARERAMGS12 : > RAMGS12, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS13 : > RAMGS13, PAGE = 1 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS14 : > RAMGS14, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + SHARERAMGS15 : > RAMGS15, PAGE = 0 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu1.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu1.cmd new file mode 100644 index 00000000000..ff0d4cb7516 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu1.cmd @@ -0,0 +1,68 @@ + +/* this linker command file is to be included if user wants to use the DCSM feature on the device + * DCSM means Dual Zone Code Security Module. + * This linker command file works as an addendum ot the already existing Flash/RAM linker command file + * that the project has. + * The sections in the *_ZoneSelectBlock.asm source file is linked as per the commands given in the file + * NOTE - please note fill=0xFFFF, this helps if users include this file in the project by mistake and + * doesn't provide the needed proper *_ZoneSelectBlock.asm sources . + * Please refer to the Blinky DCSM example in the controlsuite examples for proper usage of this. + * + * Once users are confident that they want to program the passwords in OTP, the DSECT section type can be removed. + * +*/ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + + /* Z1 OTP. LinkPointers */ + DCSM_OTP_Z1_LINKPOINTER : origin = 0x78000, length = 0x00000C + /* Z1 OTP. PSWDLOCK/RESERVED */ + DCSM_OTP_Z1_PSWDLOCK : origin = 0x78010, length = 0x000004 + /* Z1 OTP. CRCLOCK/RESERVED */ + DCSM_OTP_Z1_CRCLOCK : origin = 0x78014, length = 0x000004 + /* Z1 OTP. RESERVED/BOOTCTRL */ + DCSM_OTP_Z1_BOOTCTRL : origin = 0x7801C, length = 0x000004 + + /* DCSM Z1 Zone Select Contents (!!Movable!!) */ + /* Z1 OTP. Z1 password locations / Flash and RAM partitioning */ + DCSM_ZSEL_Z1_P0 : origin = 0x78020, length = 0x000010 + + /* Z2 OTP. LinkPointers */ + DCSM_OTP_Z2_LINKPOINTER : origin = 0x78200, length = 0x00000C + /* Z2 OTP. GPREG1/GPREG2 */ + DCSM_OTP_Z2_GPREG : origin = 0x7820C, length = 0x000004 + /* Z2 OTP. PSWDLOCK/RESERVED */ + DCSM_OTP_Z2_PSWDLOCK : origin = 0x78210, length = 0x000004 + /* Z2 OTP. CRCLOCK/RESERVED */ + DCSM_OTP_Z2_CRCLOCK : origin = 0x78214, length = 0x000004 + /* Z2 OTP. GPREG3/BOOTCTRL */ + DCSM_OTP_Z2_BOOTCTRL : origin = 0x7821C, length = 0x000004 + + /* DCSM Z1 Zone Select Contents (!!Movable!!) */ + /* Z2 OTP. Z2 password locations / Flash and RAM partitioning */ + DCSM_ZSEL_Z2_P0 : origin = 0x78220, length = 0x000010 + +} + +SECTIONS +{ + dcsm_otp_z1_linkpointer : > DCSM_OTP_Z1_LINKPOINTER PAGE = 0, type = DSECT + dcsm_otp_z1_pswdlock : > DCSM_OTP_Z1_PSWDLOCK PAGE = 0, type = DSECT + dcsm_otp_z1_crclock : > DCSM_OTP_Z1_CRCLOCK PAGE = 0, type = DSECT + dcsm_otp_z1_bootctrl : > DCSM_OTP_Z1_BOOTCTRL PAGE = 0, type = DSECT + dcsm_zsel_z1 : > DCSM_ZSEL_Z1_P0 PAGE = 0, type = DSECT + + dcsm_otp_z2_linkpointer : > DCSM_OTP_Z2_LINKPOINTER PAGE = 0, type = DSECT + dcsm_otp_z2_pswdlock : > DCSM_OTP_Z2_PSWDLOCK PAGE = 0, type = DSECT + dcsm_otp_z2_crclock : > DCSM_OTP_Z2_CRCLOCK PAGE = 0, type = DSECT + dcsm_otp_z2_bootctrl : > DCSM_OTP_Z2_BOOTCTRL PAGE = 0, type = DSECT + dcsm_zsel_z2 : > DCSM_ZSEL_Z2_P0 PAGE = 0, type = DSECT +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu2.cmd b/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu2.cmd new file mode 100644 index 00000000000..38111c8a18c --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/cmd/2837xD_dcsm_lnk_cpu2.cmd @@ -0,0 +1,44 @@ + +/* this linker command file is to be included if user wants to use the DCSM feature on the device + * DCSM means Dual Zone Code Security Module. + * This linker command file works as an addendum ot the already existing Flash/RAM linker command file + * that the project has. + * The sections in the *_ZoneSelectBlock.asm source file is linked as per the commands given in the file + * NOTEG - please note fill=0xFFFF, this helps if users include this file in the project by mistake and + * doesn't provide the needed *_ZoneSelectBlock.asm sources. + * Please refer to the Blinky DCSM example in the controlsuite examples for proper usage of this. +*/ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + + /* Part of Z1 OTP. LinkPointers/PSWD LOCK/CRC LOCK/JTAG lock/ Boot Ctrl */ + DCSM_OTP_Z1_P0 : origin = 0x78000, length = 0x000020 + /* Part of Z2 OTP. LinkPointers/PSWD LOCK/CRC LOCK/JTAG lock/ Boot Ctrl */ + DCSM_OTP_Z2_P0 : origin = 0x78200, length = 0x000020 + + /* DCSM Z1 Zone Select Contents (!!Movable!!) */ + /* Part of Z1 OTP. Z1 password locations / Flash and RAM partitioning */ + DCSM_ZSEL_Z1_P0 : origin = 0x78020, length = 0x000010 + + /* DCSM Z1 Zone Select Contents (!!Movable!!) */ + /* Part of Z2 OTP. Z2 password locations / Flash and RAM partitioning */ + DCSM_ZSEL_Z2_P0 : origin = 0x78220, length = 0x000010 +} + + +SECTIONS +{ + dcsm_otp_z1 : > DCSM_OTP_Z1_P0, PAGE = 0, type = DSECT + dcsm_otp_z2 : > DCSM_OTP_Z2_P0, PAGE = 0, type = DSECT + + dcsm_zsel_z1 : > DCSM_ZSEL_Z1_P0, PAGE = 0, type = DSECT + dcsm_zsel_z2 : > DCSM_ZSEL_Z2_P0, PAGE = 0, type = DSECT +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/Deprecated_F2837xD_DRL_UG.pdf b/bsp/tms320f28379d/libraries/common/deprecated/Deprecated_F2837xD_DRL_UG.pdf new file mode 100644 index 00000000000..759a3d87ffa Binary files /dev/null and b/bsp/tms320f28379d/libraries/common/deprecated/Deprecated_F2837xD_DRL_UG.pdf differ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.c new file mode 100644 index 00000000000..72343c50941 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.c @@ -0,0 +1,1919 @@ +//########################################################################### +// +// FILE: can.c +// +// TITLE: F2837xD CAN Initialization & Support Functions. +// +// NOTE: The CAN bus bridge uses a different addressing scheme in order to +// allow byte accesses. Because of this, 32-bit reads/writes can execute +// abnormally at higher optimization levels. The CAN driver functions +// have been adjusted to explicitly use two 16-bit read/writes to access +// the full 32-bit register where HWREGH(base + offset) represents the +// lower 16-bits and HWREGH(base + offset + 2) represents the upper +// 16-bits. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +//! \addtogroup can_api +//! @{ +//***************************************************************************** + +#include "F28x_Project.h" +#include +#include +#include "inc/hw_can.h" +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "driverlib/can.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" + +//***************************************************************************** +// This is the maximum number that can be stored as an 11bit Message +// identifier. +//***************************************************************************** +#define CAN_MAX_11BIT_MSG_ID (0x7ff) + +//***************************************************************************** +// This is used as the loop delay for accessing the CAN controller registers. +//***************************************************************************** + +// The maximum CAN bit timing divisor is 13. +#define CAN_MAX_BIT_DIVISOR (13) + +// The minimum CAN bit timing divisor is 5. +#define CAN_MIN_BIT_DIVISOR (5) + +// The maximum CAN pre-divisor is 1024. +#define CAN_MAX_PRE_DIVISOR (1024) + +// The minimum CAN pre-divisor is 1. +#define CAN_MIN_PRE_DIVISOR (1) + +//***************************************************************************** +// This table is used by the CANBitRateSet() API as the register defaults for +// the bit timing values. +//***************************************************************************** + +static const uint16_t g_ui16CANBitValues[] = +{ + 0x1100, // TSEG2 2, TSEG1 2, SJW 1, Divide 5 + 0x1200, // TSEG2 2, TSEG1 3, SJW 1, Divide 6 + 0x2240, // TSEG2 3, TSEG1 3, SJW 2, Divide 7 + 0x2340, // TSEG2 3, TSEG1 4, SJW 2, Divide 8 + 0x3340, // TSEG2 4, TSEG1 4, SJW 2, Divide 9 + 0x3440, // TSEG2 4, TSEG1 5, SJW 2, Divide 10 + 0x3540, // TSEG2 4, TSEG1 6, SJW 2, Divide 11 + 0x3640, // TSEG2 4, TSEG1 7, SJW 2, Divide 12 + 0x3740 // TSEG2 4, TSEG1 8, SJW 2, Divide 13 +}; + +//***************************************************************************** +//! \internal +//! Checks a CAN base address. +//! +//! \param ui32Base is the base address of the CAN controller. +//! +//! This function determines if a CAN controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +CANBaseValid(uint32_t ui32Base) +{ + return((ui32Base == CANA_BASE) || (ui32Base == CANB_BASE)); +} + +#endif + +//***************************************************************************** +//! \internal +//! +//! Returns the CAN controller interrupt number. +//! +//! \param ui32Base is the base address of the selected CAN controller +//! \param ucNumber is the interrupt line number requested, valid values are 0 +//! or 1 +//! +//! Given a CAN controller base address and interrupt line number, returns the +//! corresponding interrupt number. +//! +//! \return Returns a CAN interrupt number, or -1 if \e ui32Port is invalid. +// +//***************************************************************************** +static int32_t +CANIntNumberGet(uint32_t ui32Base, unsigned char ucNumber) +{ + int32_t lIntNumber; + + // Return the interrupt number for the given CAN controller. + switch(ui32Base) + { + // Return the interrupt number for CAN 0 + case CANA_BASE: + { + switch(ucNumber) + { + case 0: + { + lIntNumber = INT_CANA_0; + break; + } + case 1: + { + lIntNumber = INT_CANA_1; + break; + + } + default: + { + lIntNumber = -1; + break; + } + } + break; + } + + // Return the interrupt number for CAN 1 + case CANB_BASE: + { + switch(ucNumber) + { + case 0: + { + lIntNumber = INT_CANB_0; + break; + } + case 1: + { + lIntNumber = INT_CANB_1; + break; + + } + default: + { + lIntNumber = -1; + break; + } + } + break; + } + + // Return -1 to indicate a bad address was passed in. + default: + { + lIntNumber = -1; + } + } + return(lIntNumber); +} + +//***************************************************************************** +//! \internal +//! +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param pucData is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param pui32Register is an uint32_t pointer to the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller A, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param iSize is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. This function is rarely used outside of the CANMessageSet() +//! function. +//! +//! This function replaces the original CANWriteDataReg() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +static void +CANDataRegWrite(unsigned char *pucData, uint32_t *pui32Register, int16_t iSize) +{ + int16_t iIdx; + unsigned char * pucRegister = (unsigned char *) pui32Register; + + // Loop always copies 1 or 2 bytes per iteration. + for(iIdx = 0; iIdx < iSize; iIdx++ ) + { + // Write out the data 8 bits at a time. + HWREGB(pucRegister++) = pucData[iIdx]; + } +} + +//***************************************************************************** +//! \internal +//! +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param pucData is a pointer to the location to store the data read from the +//! CAN controller's data registers. +//! \param pui32Register is an uint32_t pointer to the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller A, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param iSize is the number of bytes to copy from the CAN controller. +//! +//! This function takes the steps necessary to copy data to a contiguous buffer +//! in memory from the non-contiguous data registers used by the CAN +//! controller. This function is rarely used outside of the CANMessageGet() +//! function. +//! +//! This function replaces the original CANReadDataReg() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +static void +CANDataRegRead(unsigned char *pucData, uint32_t *pui32Register, int16_t iSize) +{ + int16_t iIdx; + unsigned char * pucRegister = (unsigned char *) pui32Register; + + // Loop always copies 1 or 2 bytes per iteration. + for(iIdx = 0; iIdx < iSize; iIdx++ ) + { + // Read out the data + pucData[iIdx] = HWREGB(pucRegister++); + } +} + +//***************************************************************************** +// +//! Initializes the CAN controller after reset. +//! +//! \param ui32Base is the base address of the CAN controller. +//! +//! After reset, the CAN controller is left in the disabled state. However, +//! the memory used for message objects contains undefined values and must be +//! cleared prior to enabling the CAN controller the first time. This prevents +//! unwanted transmission or reception of data before the message objects are +//! configured. This function must be called before enabling the controller +//! the first time. +//! +//! \return None. +// +//***************************************************************************** +void +CANInit(uint32_t ui32Base) +{ + int16_t iMsg; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + + // Place CAN controller in init state, regardless of previous state. This + // will put controller in idle, and allow the message object RAM to be + // programmed. + + HWREGH(ui32Base + CAN_O_CTL) = CAN_CTL_INIT; + HWREGH(ui32Base + CAN_O_CTL) = CAN_CTL_SWR; + + // Wait for busy bit to clear + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) + { + } + + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid and is a "safe" condition to leave the message + // object. The same arb reg is used to program all the message objects. + HWREGH(ui32Base + CAN_O_IF1CMD + 2) = (CAN_IF1CMD_DIR | CAN_IF1CMD_ARB | + CAN_IF1CMD_CONTROL) >> 16; + HWREGH(ui32Base + CAN_O_IF1ARB) = 0; + HWREGH(ui32Base + CAN_O_IF1ARB + 2) = 0; + + HWREGH(ui32Base + CAN_O_IF1MCTL) = 0; + HWREGH(ui32Base + CAN_O_IF1MCTL + 2) = 0; + + HWREGH(ui32Base + CAN_O_IF2CMD + 2) = (CAN_IF2CMD_DIR | CAN_IF2CMD_ARB | + CAN_IF2CMD_CONTROL) >> 16; + HWREGH(ui32Base + CAN_O_IF2ARB) = 0; + HWREGH(ui32Base + CAN_O_IF2ARB + 2) = 0; + + HWREGH(ui32Base + CAN_O_IF2MCTL) = 0; + HWREGH(ui32Base + CAN_O_IF2MCTL + 2) = 0; + + // Loop through to program all 32 message objects + for(iMsg = 1; iMsg <= 32; iMsg+=2) + { + // Wait for busy bit to clear + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) + { + } + + // Initiate programming the message object + HWREGH(ui32Base + CAN_O_IF1CMD) = iMsg; + + // Wait for busy bit to clear + while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) + { + } + + // Initiate programming the message object + HWREGH(ui32Base + CAN_O_IF2CMD) = iMsg + 1; + } + + // Make sure that the interrupt and new data flags are updated for the + // message objects. + HWREGH(ui32Base + CAN_O_IF1CMD + 2) = (CAN_IF1CMD_TXRQST | + CAN_IF1CMD_CLRINTPND) >> 16; + HWREGH(ui32Base + CAN_O_IF2CMD + 2) = (CAN_IF2CMD_TXRQST | + CAN_IF2CMD_CLRINTPND) >> 16; + + // Loop through to program all 32 message objects + for(iMsg = 1; iMsg <= 32; iMsg+=2) + { + // Wait for busy bit to clear. + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) + { + } + + // Initiate programming the message object + HWREGH(ui32Base + CAN_O_IF1CMD) = iMsg; + + // Wait for busy bit to clear. + while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) + { + } + + // Initiate programming the message object + HWREGH(ui32Base + CAN_O_IF2CMD) = iMsg + 1; + } + + // Acknowledge any pending status interrupts. + HWREG(ui32Base + CAN_O_ES); +} + +//***************************************************************************** +// +//! Enables the CAN controller. +//! +//! \param ui32Base is the base address of the CAN controller to enable. +//! +//! Enables the CAN controller for message processing. Once enabled, the +//! controller will automatically transmit any pending frames, and process any +//! received frames. The controller can be stopped by calling CANDisable(). +//! Prior to calling CANEnable(), CANInit() should have been called to +//! initialize the controller and the CAN bus clock should be configured by +//! calling CANBitTimingSet(). +//! +//! \return None. +// +//***************************************************************************** +void +CANEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + + // Clear the init bit in the control register. + HWREGH(ui32Base + CAN_O_CTL) = HWREGH(ui32Base + CAN_O_CTL) & + ~CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Disables the CAN controller. +//! +//! \param ui32Base is the base address of the CAN controller to disable. +//! +//! Disables the CAN controller for message processing. When disabled, the +//! controller will no longer automatically process data on the CAN bus. The +//! controller can be restarted by calling CANEnable(). The state of the CAN +//! controller and the message objects in the controller are left as they were +//! before this call was made. +//! +//! \return None. +// +//***************************************************************************** +void +CANDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + + // Set the init bit in the control register. + HWREGH(ui32Base + CAN_O_CTL) = HWREGH(ui32Base + CAN_O_CTL) | + CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Select CAN peripheral clock source +//! +//! \param ui32Base is the base address of the CAN controller to disable. +//! \param ui16Source is the clock source to select for the given CAN +//! peripheral: \n +//! 0 - Selected CPU SYSCLKOUT (CPU1.Sysclk or CPU2.Sysclk) +//! (default at reset) \n +//! 1 - External Oscillator (OSC) clock (direct from X1/X2) \n +//! 2 - AUXCLKIN = GPIOn(GPIO19) +//! +//! Selects the desired clock source for use with a given CAN peripheral. +//! +//! \return None. +// +//***************************************************************************** +void CANClkSourceSelect(uint32_t ui32Base, uint16_t ui16Source) +{ + EALLOW; + switch(ui32Base) + { + case CANA_BASE: + { + ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = ui16Source; + } + + case CANB_BASE: + { + ClkCfgRegs.CLKSRCCTL2.bit.CANBBCLKSEL = ui16Source; + } + + default: + break; + } + EDIS; +} + +//***************************************************************************** +// +//! Reads the current settings for the CAN controller bit timing. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param pClkParms is a pointer to a structure to hold the timing parameters. +//! +//! This function reads the current configuration of the CAN controller bit +//! clock timing, and stores the resulting information in the structure +//! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the +//! values that are returned in the structure pointed to by \e pClkParms. +//! +//! This function replaces the original CANGetBitTiming() API and performs the +//! same actions. A macro is provided in can.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *pClkParms) +{ + uint32_t uBitReg; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT(pClkParms != 0); + + uBitReg = HWREG(ui32Base + CAN_O_BTR); + + // Set the phase 2 segment. + pClkParms->uPhase2Seg = ((uBitReg & CAN_BTR_TSEG2_M) >> 12) + 1; + + // Set the phase 1 segment. + pClkParms->uSyncPropPhase1Seg = ((uBitReg & CAN_BTR_TSEG1_M) >> 8) + 1; + + // Set the synchronous jump width. + pClkParms->uSJW = ((uBitReg & CAN_BTR_SJW_M) >> 6) + 1; + + // Set the pre-divider for the CAN bus bit clock. + pClkParms->uQuantumPrescaler = ((uBitReg & CAN_BTR_BRP_M) | + ((uBitReg & CAN_BTR_BRPE_M) >> 10)) + 1; +} + +//***************************************************************************** +// +//! This function is used to set the CAN bit timing values to a nominal setting +//! based on a desired bit rate. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32SourceClock is the clock frequency for the CAN peripheral in Hz. +//! \param ui32BitRate is the desired bit rate. +//! +//! This function will set the CAN bit timing for the bit rate passed in the +//! \e ui32BitRate parameter based on the \e ui32SourceClock parameter. The CAN +//! bit clock is calculated to be an average timing value that should work for +//! most systems. If tighter timing requirements are needed, then the +//! CANBitTimingSet() function is available for full customization of all of +//! the CAN bit timing values. Since not all bit rates can be matched +//! exactly, the bit rate is set to the value closest to the desired bit rate +//! without being higher than the \e ui32BitRate value. +//! +//! \return This function returns the bit rate that the CAN controller was +//! configured to use or it returns 0 to indicate that the bit rate was not +//! changed because the requested bit rate was not valid. +// +//***************************************************************************** +uint32_t +CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, uint32_t ui32BitRate) +{ + uint32_t ui32DesiredRatio; + uint32_t ui32CANBits; + uint32_t ui32PreDivide; + uint32_t ui32RegValue; + uint16_t ui16CANCTL; + + ASSERT(ui32BitRate != 0); + + // Calculate the desired clock rate. + ui32DesiredRatio = ui32SourceClock / ui32BitRate; + + // If the ratio of CAN bit rate to processor clock is too small or too + // large then return 0 indicating that no bit rate was set. + ASSERT(ui32DesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)); + ASSERT(ui32DesiredRatio >= (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR)); + + // Make sure that the Desired Ratio is not too large. This enforces the + // requirement that the bit rate is larger than requested. + if((ui32SourceClock / ui32DesiredRatio) > ui32BitRate) + { + ui32DesiredRatio += 1; + } + + // Check all possible values to find a matching value. + while(ui32DesiredRatio <= CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR) + { + // Loop through all possible CAN bit divisors. + for(ui32CANBits = CAN_MAX_BIT_DIVISOR; + ui32CANBits >= CAN_MIN_BIT_DIVISOR; + ui32CANBits--) + { + // For a given CAN bit divisor save the pre divisor. + ui32PreDivide = ui32DesiredRatio / ui32CANBits; + + // If the calculated divisors match the desired clock ratio then + // return these bit rate and set the CAN bit timing. + if((ui32PreDivide * ui32CANBits) == ui32DesiredRatio) + { + // Start building the bit timing value by adding the bit timing + // in time quanta. + ui32RegValue = + g_ui16CANBitValues[ui32CANBits - CAN_MIN_BIT_DIVISOR]; + + // To set the bit timing register, the controller must be + // placed + // in init mode (if not already), and also configuration change + // bit enabled. The state of the register should be saved + // so it can be restored. + + ui16CANCTL = HWREGH(ui32Base + CAN_O_CTL); + HWREGH(ui32Base + CAN_O_CTL) = ui16CANCTL | CAN_CTL_INIT | + CAN_CTL_CCE; + + // Now add in the pre-scalar on the bit rate. + ui32RegValue |= ((ui32PreDivide - 1) & CAN_BTR_BRP_M) | + (((ui32PreDivide - 1) << 10) & CAN_BTR_BRPE_M); + + // Set the clock bits in the and the bits of the + // pre-scalar. + HWREGH(ui32Base + CAN_O_BTR) = (ui32RegValue & + CAN_REG_WORD_MASK); + HWREGH(ui32Base + CAN_O_BTR + 2) = (ui32RegValue >> 16); + + // Restore the saved CAN Control register. + HWREGH(ui32Base + CAN_O_CTL) = ui16CANCTL; + + // Return the computed bit rate. + return(ui32SourceClock / ( ui32PreDivide * ui32CANBits)); + } + } + + // Move the divisor up one and look again. Only in rare cases are + // more than 2 loops required to find the value. + ui32DesiredRatio++; + } + return(0); +} + +//***************************************************************************** +// +//! Configures the CAN controller bit timing. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param pClkParms points to the structure with the clock parameters. +//! +//! Configures the various timing parameters for the CAN bus bit timing: +//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and +//! the Synchronization Jump Width. The values for Propagation and Phase +//! Buffer 1 segments are derived from the combination +//! \e pClkParms->uSyncPropPhase1Seg parameter. Phase Buffer 2 is determined +//! from the \e pClkParms->uPhase2Seg parameter. These two parameters, along +//! with \e pClkParms->uSJW are based in units of bit time quanta. The actual +//! quantum time is determined by the \e pClkParms->uQuantumPrescaler value, +//! which specifies the divisor for the CAN module clock. +//! +//! The total bit time, in quanta, will be the sum of the two Seg parameters, +//! as follows: +//! +//! bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1 +//! +//! Note that the Sync_Seg is always one quantum in duration, and will be added +//! to derive the correct duration of Prop_Seg and Phase1_Seg. +//! +//! The equation to determine the actual bit rate is as follows: +//! +//! CAN Clock / +//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1) * (\e uQuantumPrescaler)) +//! +//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1, +//! \e uQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be +//! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec. +//! +//! \return None. +// +//***************************************************************************** +void +CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *pClkParms) +{ + uint32_t uBitReg; + uint16_t uSavedInit; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT(pClkParms != 0); + + // The phase 1 segment must be in the range from 2 to 16. + ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) && + (pClkParms->uSyncPropPhase1Seg <= 16)); + + // The phase 2 segment must be in the range from 1 to 8. + ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8)); + + // The synchronous jump windows must be in the range from 1 to 4. + ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4)); + + // The CAN clock pre-divider must be in the range from 1 to 1024. + ASSERT((pClkParms->uQuantumPrescaler <= 1024) && + (pClkParms->uQuantumPrescaler >= 1)); + + // To set the bit timing register, the controller must be placed in init + // mode (if not already), and also configuration change bit enabled. State + // of the init bit should be saved so it can be restored at the end. + uSavedInit = HWREGH(ui32Base + CAN_O_CTL); + HWREGH(ui32Base + CAN_O_CTL) = uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE; + + // Set the bit fields of the bit timing register according to the parms. + uBitReg = ((pClkParms->uPhase2Seg - 1) << 12) & CAN_BTR_TSEG2_M; + uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BTR_TSEG1_M; + uBitReg |= ((pClkParms->uSJW - 1) << 6) & CAN_BTR_SJW_M; + uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BTR_BRP_M; + uBitReg |= ((pClkParms->uQuantumPrescaler - 1) << 10)& CAN_BTR_BRPE_M; + HWREGH(ui32Base + CAN_O_BTR) = uBitReg & CAN_REG_WORD_MASK; + HWREGH(ui32Base + CAN_O_BTR + 2) = uBitReg >> 16; + + // Clear the config change bit, and restore the init bit. + uSavedInit &= ~CAN_CTL_CCE; + + // If Init was not set before, then clear it. + if(uSavedInit & CAN_CTL_INIT) + { + uSavedInit &= ~CAN_CTL_INIT; + } + HWREGH(ui32Base + CAN_O_CTL) = uSavedInit; +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the CAN controller. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ucIntNumber is the interrupt line to register (0 or 1). +//! \param pfnHandler is a pointer to the function to be called when the +//! enabled CAN interrupts occur. +//! +//! This function registers the interrupt handler in the interrupt vector +//! table, and enables CAN interrupts on the interrupt controller; specific CAN +//! interrupt sources must be enabled using CANIntEnable(). The interrupt +//! handler being registered must clear the source of the interrupt using +//! CANIntClear(). +//! +//! If the application is using a static interrupt vector table stored in +//! flash, then it is not necessary to register the interrupt handler this way. +//! Instead, IntEnable() should be used to enable CAN interrupts on the +//! interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntRegister(uint32_t ui32Base, unsigned char ucIntNumber, + void (*pfnHandler)(void)) +{ + uint32_t ui32IntNumber; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + + // Get the actual interrupt number for this CAN controller. + ui32IntNumber = CANIntNumberGet(ui32Base, ucIntNumber); + + // Register the interrupt handler. + IntRegister(ui32IntNumber, pfnHandler); + + // Enable the CAN interrupt. + IntEnable(ui32IntNumber); +} + +//***************************************************************************** +//! Unregisters an interrupt handler for the CAN controller. +//! +//! \param ui32Base is the base address of the controller. +//! \param ucIntNumber is the interrupt line to un-register (0 or 1). +//! +//! This function unregisters the previously registered interrupt handler and +//! disables the interrupt on the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntUnregister(uint32_t ui32Base, unsigned char ucIntNumber) +{ + uint32_t ui32IntNumber; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + + // Get the actual interrupt number for this CAN controller. + ui32IntNumber = CANIntNumberGet(ui32Base, ucIntNumber); + + // Register the interrupt handler. + IntUnregister(ui32IntNumber); + + // Disable the CAN interrupt. + IntDisable(ui32IntNumber); +} + +//***************************************************************************** +// +//! Enables individual CAN controller interrupt sources. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific interrupt sources of the CAN controller. Only enabled +//! sources will cause a processor interrupt. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b CAN_INT_ERROR - a controller error condition has occurred +//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has +//! been detected +//! - \b CAN_INT_IE0 - allow CAN controller to generate interrupts on interrupt +//! line 0 +//! - \b CAN_INT_IE1 - allow CAN controller to generate interrupts on interrupt +//! line 1 +//! +//! In order to generate status or error interrupts, \b CAN_INT_IE0 must be +//! enabled. +//! Further, for any particular transaction from a message object to generate +//! an interrupt, that message object must have interrupts enabled (see +//! CANMessageSet()). \b CAN_INT_ERROR will generate an interrupt if the +//! controller enters the ``bus off'' condition, or if the error counters reach +//! a limit. \b CAN_INT_STATUS will generate an interrupt under quite a few +//! status conditions and may provide more interrupts than the application +//! needs to handle. When an interrupt occurs, use CANIntStatus() to determine +//! the cause. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0); + + // Enable the specified interrupts. + HWREGH(ui32Base + CAN_O_CTL) = (HWREGH(ui32Base + CAN_O_CTL) | + (ui32IntFlags & CAN_REG_WORD_MASK)); + + HWREGH(ui32Base + CAN_O_CTL + 2) = (HWREGH(ui32Base + CAN_O_CTL + 2) | + (ui32IntFlags >> 16)); +} + +//***************************************************************************** +// +//! Disables individual CAN controller interrupt sources. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specified CAN controller interrupt sources. Only enabled +//! interrupt sources can cause a processor interrupt. +//! +//! The \e ui32IntFlags parameter has the same definition as in the +//! CANIntEnable() function. +//! +//! \return None. +// +//***************************************************************************** +void +CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0); + + // Disable the specified interrupts. + HWREGH(ui32Base + CAN_O_CTL) = HWREGH(ui32Base + CAN_O_CTL) & + ~(ui32IntFlags & CAN_REG_WORD_MASK); + + HWREGH(ui32Base + CAN_O_CTL + 2) = HWREGH(ui32Base + CAN_O_CTL + 2) & + ~(ui32IntFlags >> 16); +} + +//***************************************************************************** +// +//! Returns the current CAN controller interrupt status. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param eIntStsReg indicates which interrupt status register to read +//! +//! Returns the value of one of two interrupt status registers. The interrupt +//! status register read is determined by the \e eIntStsReg parameter, which +//! can have one of the following values: +//! +//! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt +//! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message +//! objects +//! +//! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register +//! and indicates the cause of the interrupt. It will be a value of +//! \b CAN_INT_INT0ID_STATUS if the cause is a status interrupt. In this case, +//! the status register should be read with the CANStatusGet() function. +//! Calling this function to read the status will also clear the status +//! interrupt. If the value of the interrupt register is in the range 1-32, +//! then this indicates the number of the highest priority message object that +//! has an interrupt pending. The message object interrupt can be cleared by +//! using the CANIntClear() function, or by reading the message using +//! CANMessageGet() in the case of a received message. The interrupt handler +//! can read the interrupt status again to make sure all pending interrupts are +//! cleared before returning from the interrupt. +//! +//! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects +//! have pending interrupts. This can be used to discover all of the pending +//! interrupts at once, as opposed to repeatedly reading the interrupt register +//! by using \b CAN_INT_STS_CAUSE. +//! +//! \return Returns the value of one of the interrupt status registers. +// +//***************************************************************************** +uint32_t +CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg) +{ + uint32_t ui32Status; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + + // See which status the caller is looking for. + switch(eIntStsReg) + { + // The caller wants the global interrupt status for the CAN controller + // specified by ui32Base. + case CAN_INT_STS_CAUSE: + { + ui32Status = HWREG(ui32Base + CAN_O_INT); + break; + } + + // The caller wants the current message status interrupt for all + // messages. + case CAN_INT_STS_OBJECT: + { + // Read message object interrupt status + ui32Status = HWREG(ui32Base + CAN_O_IPEN_21); + break; + } + + // Request was for unknown status so just return 0. + default: + { + ui32Status = 0; + break; + } + } + // Return the interrupt status value + return(ui32Status); +} + +//***************************************************************************** +// +//! Clears a CAN interrupt source. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntClr is a value indicating which interrupt source to clear. +//! +//! This function can be used to clear a specific interrupt source. The +//! \e ui32IntClr parameter should be one of the following values: +//! +//! - \b CAN_INT_INTID_STATUS - Clears a status interrupt. +//! - 1-32 - Clears the specified message object interrupt +//! +//! It is not necessary to use this function to clear an interrupt. This +//! should only be used if the application wants to clear an interrupt source +//! without taking the normal interrupt action. +//! +//! Normally, the status interrupt is cleared by reading the controller status +//! using CANStatusGet(). A specific message object interrupt is normally +//! cleared by reading the message object using CANMessageGet(). +//! +//! \return None. +// +//***************************************************************************** +void +CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntClr == CAN_INT_INT0ID_STATUS) || + ((ui32IntClr>=1) && (ui32IntClr <=32))); + + if(ui32IntClr == CAN_INT_INT0ID_STATUS) + { + // Simply read and discard the status to clear the interrupt. + HWREG(ui32Base + CAN_O_ES); + } + else + { + // Wait to be sure that this interface is not busy. + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) + { + } + + // Only change the interrupt pending state by setting only the + // CAN_IF1CMD_CLRINTPND bit. + HWREGH(ui32Base + CAN_O_IF1CMD + 2) = CAN_IF1CMD_CLRINTPND >> 16; + + // Send the clear pending interrupt command to the CAN controller. + HWREGH(ui32Base + CAN_O_IF1CMD) = ui32IntClr & CAN_IF1CMD_MSG_NUM_M; + + // Wait to be sure that this interface is not busy. + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) + { + } + } +} + +//***************************************************************************** +// +//! Sets the CAN controller automatic retransmission behavior. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param bAutoRetry enables automatic retransmission. +//! +//! Enables or disables automatic retransmission of messages with detected +//! errors. If \e bAutoRetry is \b true, then automatic retransmission is +//! enabled, otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +void +CANRetrySet(uint32_t ui32Base, bool bAutoRetry) +{ + uint16_t ui16CtlReg; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + + ui16CtlReg = HWREGH(ui32Base + CAN_O_CTL); + + // Conditionally set the DAR bit to enable/disable auto-retry. + if(bAutoRetry) + { + // Clearing the DAR bit tells the controller to not disable the + // auto-retry of messages which were not transmitted or received + // correctly. + ui16CtlReg &= ~CAN_CTL_DAR; + } + else + { + // Setting the DAR bit tells the controller to disable the auto-retry + // of messages which were not transmitted or received correctly. + ui16CtlReg |= CAN_CTL_DAR; + } + + HWREGH(ui32Base + CAN_O_CTL) = ui16CtlReg; +} + +//***************************************************************************** +// +//! Returns the current setting for automatic retransmission. +//! +//! \param ui32Base is the base address of the CAN controller. +//! +//! Reads the current setting for the automatic retransmission in the CAN +//! controller and returns it to the caller. +//! +//! \return Returns \b true if automatic retransmission is enabled, \b false +//! otherwise. +// +//***************************************************************************** +bool +CANRetryGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + + // Read the disable automatic retry setting from the CAN controller. + if(HWREGH(ui32Base + CAN_O_CTL) & CAN_CTL_DAR) + { + // Automatic data retransmission is not enabled. + return(false); + } + + // Automatic data retransmission is enabled. + return(true); +} + +//***************************************************************************** +// +//! Reads one of the controller status registers. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param eStatusReg is the status register to read. +//! +//! Reads a status register of the CAN controller and returns it to the caller. +//! The different status registers are: +//! +//! - \b CAN_STS_CONTROL - the main controller status +//! - \b CAN_STS_TXREQUEST - bit mask of objects pending transmission +//! - \b CAN_STS_NEWDAT - bit mask of objects with new data +//! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration +//! +//! When reading the main controller status register, a pending status +//! interrupt will be cleared. This should be used in the interrupt handler +//! for the CAN controller if the cause is a status interrupt. The controller +//! status register fields are as follows: +//! +//! - \b CAN_STATUS_PDA - controller in local power down mode +//! - \b CAN_STATUS_WAKE_UP - controller initiated system wake up +//! - \b CAN_STATUS_PERR - parity error detected +//! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition +//! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96 +//! - \b CAN_STATUS_EPASS - CAN controller is in the error passive state +//! - \b CAN_STATUS_RXOK - a message was received successfully (independent of +//! any message filtering). +//! - \b CAN_STATUS_TXOK - a message was successfully transmitted +//! - \b CAN_STATUS_LEC_NONE - no error +//! - \b CAN_STATUS_LEC_STUFF - stuffing error detected +//! - \b CAN_STATUS_LEC_FORM - a format error occurred in the fixed format part +//! of a message +//! - \b CAN_STATUS_LEC_ACK - a transmitted message was not acknowledged +//! - \b CAN_STATUS_LEC_BIT1 - dominant level detected when trying to send in +//! recessive mode +//! - \b CAN_STATUS_LEC_BIT0 - recessive level detected when trying to send in +//! dominant mode +//! - \b CAN_STATUS_LEC_CRC - CRC error in received message +//! +//! The remaining status registers are 32-bit bit maps to the message objects. +//! They can be used to quickly obtain information about the status of all the +//! message objects without needing to query each one. They contain the +//! following information: +//! +//! - \b CAN_STS_TXREQUEST - if a message object's TxRequest bit is set, that +//! means that a transmission is pending on that object. The application can +//! use this to determine which objects are still waiting to send a message. +//! - \b CAN_STS_NEWDAT - if a message object's NewDat bit is set, that means +//! that a new message has been received in that object, and has not yet been +//! picked up by the host application +//! - \b CAN_STS_MSGVAL - if a message object's MsgVal bit is set, that means +//! it has a valid configuration programmed. The host application can use this +//! to determine which message objects are empty/unused. +//! +//! \return Returns the value of the status register. +// +//***************************************************************************** +uint32_t +CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg) +{ + uint32_t ui32Status; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + + switch(eStatusReg) + { + // Just return the global CAN status register since that is what was + // requested. + case CAN_STS_CONTROL: + { + ui32Status = HWREG(ui32Base + CAN_O_ES); + break; + } + + // Return objects with valid transmit requests + case CAN_STS_TXREQUEST: + { + ui32Status = HWREG(ui32Base + CAN_O_TXRQ_21); + break; + } + + // Return messages objects with new data + case CAN_STS_NEWDAT: + { + ui32Status = HWREG(ui32Base + CAN_O_NDAT_21); + break; + } + + // Return valid message objects + case CAN_STS_MSGVAL: + { + ui32Status = HWREG(ui32Base + CAN_O_MVAL_21); + break; + } + + // Unknown CAN status requested so return 0. + default: + { + ui32Status = 0; + break; + } + } + return(ui32Status); +} + +//***************************************************************************** +// +//! Reads the CAN controller error counter register. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param pui32RxCount is a pointer to storage for the receive error counter. +//! \param pui32TxCount is a pointer to storage for the transmit error counter. +//! +//! Reads the error counter register and returns the transmit and receive error +//! counts to the caller along with a flag indicating if the controller receive +//! counter has reached the error passive limit. The values of the receive and +//! transmit error counters are returned through the pointers provided as +//! parameters. +//! +//! After this call, \e *pui32RxCount will hold the current receive error count +//! and \e *pui32TxCount will hold the current transmit error count. +//! +//! \return Returns \b true if the receive error count has reached the error +//! passive limit, and \b false if the error count is below the error passive +//! limit. +// +//***************************************************************************** +bool +CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, + uint32_t *pui32TxCount) +{ + uint16_t ui16CANError; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + + // Read the current count of transmit/receive errors. + ui16CANError = HWREGH(ui32Base + CAN_O_ERRC); + + // Extract the error numbers from the register value. + *pui32RxCount = (ui16CANError & CAN_ERRC_REC_M) >> CAN_ERRC_REC_S; + *pui32TxCount = (ui16CANError & CAN_ERRC_TEC_M) >> CAN_ERRC_TEC_S; + + if(ui16CANError & CAN_ERRC_RP) + { + return(true); + } + + return(false); +} + +//***************************************************************************** +// +//! Configures a message object in the CAN controller. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32ObjID is the object number to configure (1-32). +//! \param pMsgObject is a pointer to a structure containing message object +//! settings. +//! \param eMsgType indicates the type of message for this object. +//! +//! This function is used to configure any one of the 32 message objects in the +//! CAN controller. A message object can be configured as any type of CAN +//! message object as well as several options for automatic transmission and +//! reception. This call also allows the message object to be configured to +//! generate interrupts on completion of message receipt or transmission. The +//! message object can also be configured with a filter/mask so that actions +//! are only taken when a message that meets certain parameters is seen on the +//! CAN bus. +//! +//! The \e eMsgType parameter must be one of the following values: +//! +//! - \b MSG_OBJ_TYPE_TX - CAN transmit message object. +//! - \b MSG_OBJ_TYPE_TX_REMOTE - CAN transmit remote request message object. +//! - \b MSG_OBJ_TYPE_RX - CAN receive message object. +//! - \b MSG_OBJ_TYPE_RX_REMOTE - CAN receive remote request message object. +//! - \b MSG_OBJ_TYPE_RXTX_REMOTE - CAN remote frame receive remote, then +//! transmit message object. +//! +//! The message object pointed to by \e pMsgObject must be populated by the +//! caller, as follows: +//! +//! - \e ui32MsgID - contains the message ID, either 11 or 29 bits. +//! - \e ui32MsgIDMask - mask of bits from \e ui32MsgID that must match if +//! identifier filtering is enabled. +//! - \e ui32Flags +//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to enable interrupt on transmission. +//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the +//! identifier mask specified by \e ui32MsgIDMask. +//! - \e ui32MsgLen - the number of bytes in the message data. This should be +//! non-zero even for a remote frame; it should match the expected bytes of the +//! data responding data frame. +//! - \e pucMsgData - points to a buffer containing up to 8 bytes of data for a +//! data frame. +//! +//! \b Example: To send a data frame or remote frame(in response to a remote +//! request), take the following steps: +//! +//! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX. +//! -# Set \e pMsgObject->ui32MsgID to the message ID. +//! -# Set \e pMsgObject->ui32Flags. Make sure to set \b MSG_OBJ_TX_INT_ENABLE to +//! allow an interrupt to be generated when the message is sent. +//! -# Set \e pMsgObject->ui32MsgLen to the number of bytes in the data frame. +//! -# Set \e pMsgObject->pucMsgData to point to an array containing the bytes +//! to send in the message. +//! -# Call this function with \e ui32ObjID set to one of the 32 object buffers. +//! +//! \b Example: To receive a specific data frame, take the following steps: +//! +//! -# Set \e eMsgObjType to \b MSG_OBJ_TYPE_RX. +//! -# Set \e pMsgObject->ui32MsgID to the full message ID, or a partial mask to +//! use partial ID matching. +//! -# Set \e pMsgObject->ui32MsgIDMask bits that should be used for masking +//! during comparison. +//! -# Set \e pMsgObject->ui32Flags as follows: +//! - Set \b MSG_OBJ_TX_INT_ENABLE flag to be interrupted when the data frame +//! is received. +//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering. +//! -# Set \e pMsgObject->ui32MsgLen to the number of bytes in the expected data +//! frame. +//! -# The buffer pointed to by \e pMsgObject->pucMsgData and +//! \e pMsgObject->ui32MsgLen are not used by this call as no data is present at +//! the time of the call. +//! -# Call this function with \e ui32ObjID set to one of the 32 object buffers. +//! +//! If you specify a message object buffer that already contains a message +//! definition, it will be overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, tCANMsgObject *pMsgObject, + tMsgObjType eMsgType) +{ + uint32_t ui32CmdMaskReg; + uint32_t ui32MaskReg; + uint32_t ui32ArbReg; + uint32_t ui32MsgCtrl; + bool bTransferData; + bool bUseExtendedID; + + bTransferData = 0; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0)); + ASSERT((eMsgType == MSG_OBJ_TYPE_TX) || + (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_RX) || + (eMsgType == MSG_OBJ_TYPE_RX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_TX_REMOTE) || + (eMsgType == MSG_OBJ_TYPE_RXTX_REMOTE)); + + // Wait for busy bit to clear + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) + { + } + + // See if we need to use an extended identifier or not. + if((pMsgObject->ui32MsgID > CAN_MAX_11BIT_MSG_ID) || + (pMsgObject->ui32Flags & MSG_OBJ_EXTENDED_ID)) + { + bUseExtendedID = 1; + } + else + { + bUseExtendedID = 0; + } + + // This is always a write to the Message object as this call is setting a + // message object. This call will also always set all size bits so it sets + // both data bits. The call will use the CONTROL register to set control + // bits so this bit needs to be set as well. + ui32CmdMaskReg = (CAN_IF1CMD_DIR | CAN_IF1CMD_DATA_A | CAN_IF1CMD_DATA_B | + CAN_IF1CMD_CONTROL); + + // Initialize the values to a known state before filling them in based on + // the type of message object that is being configured. + ui32ArbReg = 0; + ui32MsgCtrl = 0; + ui32MaskReg = 0; + + switch(eMsgType) + { + // Transmit message object. + case MSG_OBJ_TYPE_TX: + { + // Set the TXRQST bit and the reset the rest of the register. + ui32MsgCtrl |= CAN_IF1MCTL_TXRQST; + ui32ArbReg = CAN_IF1ARB_DIR; + bTransferData = 1; + break; + } + + // Transmit remote request message object + case MSG_OBJ_TYPE_TX_REMOTE: + { + // Set the TXRQST bit and the reset the rest of the register. + ui32MsgCtrl |= CAN_IF1MCTL_TXRQST; + ui32ArbReg = 0; + break; + } + + // Receive message object. + case MSG_OBJ_TYPE_RX: + { + // This clears the DIR bit along with everything else. The TXRQST + // bit was cleared by defaulting ui32MsgCtrl to 0. + ui32ArbReg = 0; + break; + } + + // Receive remote request message object. + case MSG_OBJ_TYPE_RX_REMOTE: + { + // The DIR bit is set to one for remote receivers. The TXRQST bit + // was cleared by defaulting ui32MsgCtrl to 0. + ui32ArbReg = CAN_IF1ARB_DIR; + + // Set this object so that it only indicates that a remote frame + // was received and allow for software to handle it by sending back + // a data frame. + ui32MsgCtrl = CAN_IF1MCTL_UMASK; + + // Use the full Identifier by default. + ui32MaskReg = CAN_IF1MSK_MSK_M; + + // Make sure to send the mask to the message object. + ui32CmdMaskReg |= CAN_IF1CMD_MASK; + break; + } + + // Remote frame receive remote, with auto-transmit message object. + case MSG_OBJ_TYPE_RXTX_REMOTE: + { + // Oddly the DIR bit is set to one for remote receivers. + ui32ArbReg = CAN_IF1ARB_DIR; + + // Set this object to auto answer if a matching identifier is seen. + ui32MsgCtrl = CAN_IF1MCTL_RMTEN | CAN_IF1MCTL_UMASK; + + // The data to be returned needs to be filled in. + bTransferData = 1; + break; + } + + // This case should never happen due to the ASSERT statement at the + // beginning of this function. + default: + { + return; + } + } + + // Configure the Mask Registers. + if(pMsgObject->ui32Flags & MSG_OBJ_USE_ID_FILTER) + { + if(bUseExtendedID) + { + // Set the 29 bits of Identifier mask that were requested. + ui32MaskReg = pMsgObject->ui32MsgIDMask & CAN_IF1MSK_MSK_M; + } + else + { + + // Put the 11 bit Mask Identifier into the upper bits of the field + // in the register. + ui32MaskReg = ((pMsgObject->ui32MsgIDMask << CAN_IF1ARB_STD_ID_S) & + CAN_IF1ARB_STD_ID_M); + } + } + + // If the caller wants to filter on the extended ID bit then set it. + if((pMsgObject->ui32Flags & MSG_OBJ_USE_EXT_FILTER) == + MSG_OBJ_USE_EXT_FILTER) + { + ui32MaskReg |= CAN_IF1MSK_MXTD; + } + + // The caller wants to filter on the message direction field. + if((pMsgObject->ui32Flags & MSG_OBJ_USE_DIR_FILTER) == + MSG_OBJ_USE_DIR_FILTER) + { + ui32MaskReg |= CAN_IF1MSK_MDIR; + } + + if(pMsgObject->ui32Flags & (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER | + MSG_OBJ_USE_EXT_FILTER)) + { + // Set the UMASK bit to enable using the mask register. + ui32MsgCtrl |= CAN_IF1MCTL_UMASK; + + // Set the MASK bit so that this gets transferred to the Message + // Object. + ui32CmdMaskReg |= CAN_IF1CMD_MASK; + } + + // Set the Arb bit so that this gets transferred to the Message object. + ui32CmdMaskReg |= CAN_IF1CMD_ARB; + + // Configure the Arbitration registers. + if(bUseExtendedID) + { + // Set the 29 bit version of the Identifier for this message object. + // Mark the message as valid and set the extended ID bit. + ui32ArbReg |= (pMsgObject->ui32MsgID & CAN_IF1ARB_ID_M) | + CAN_IF1ARB_MSGVAL | CAN_IF1ARB_XTD; + } + else + { + // Set the 11 bit version of the Identifier for this message object. + // The lower 18 bits are set to zero. + // Mark the message as valid. + ui32ArbReg |= ((pMsgObject->ui32MsgID << CAN_IF1ARB_STD_ID_S) & + CAN_IF1ARB_STD_ID_M) | CAN_IF1ARB_MSGVAL; + } + + // Set the data length since this is set for all transfers. This is also a + // single transfer and not a FIFO transfer so set EOB bit. + ui32MsgCtrl |= (pMsgObject->ui32MsgLen & CAN_IF1MCTL_DLC_M); + + // Mark this as the last entry if this is not the last entry in a FIFO. + if((pMsgObject->ui32Flags & MSG_OBJ_FIFO) == 0) + { + ui32MsgCtrl |= CAN_IF1MCTL_EOB; + } + + // Enable transmit interrupts if they should be enabled. + if(pMsgObject->ui32Flags & MSG_OBJ_TX_INT_ENABLE) + { + ui32MsgCtrl |= CAN_IF1MCTL_TXIE; + } + + // Enable receive interrupts if they should be enabled. + if(pMsgObject->ui32Flags & MSG_OBJ_RX_INT_ENABLE) + { + ui32MsgCtrl |= CAN_IF1MCTL_RXIE; + } + + // Write the data out to the CAN Data registers if needed. + if(bTransferData) + { + CANDataRegWrite(pMsgObject->pucMsgData, + (uint32_t *)(ui32Base + CAN_O_IF1DATA), + pMsgObject->ui32MsgLen); + } + + // Write out the registers to program the message object. + HWREGH(ui32Base + CAN_O_IF1CMD + 2) = ui32CmdMaskReg >> 16; + + HWREGH(ui32Base + CAN_O_IF1MSK) = ui32MaskReg & CAN_REG_WORD_MASK; + HWREGH(ui32Base + CAN_O_IF1MSK + 2) = ui32MaskReg >> 16; + + HWREGH(ui32Base + CAN_O_IF1ARB) = ui32ArbReg & CAN_REG_WORD_MASK; + HWREGH(ui32Base + CAN_O_IF1ARB + 2) = ui32ArbReg >> 16; + + HWREGH(ui32Base + CAN_O_IF1MCTL) = ui32MsgCtrl & CAN_REG_WORD_MASK; + + // Transfer the message object to the message object specific by ui32ObjID. + HWREGH(ui32Base + CAN_O_IF1CMD) = ui32ObjID & CAN_IF1CMD_MSG_NUM_M; + + return; +} + +//***************************************************************************** +// +//! Reads a CAN message from one of the message object buffers. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32ObjID is the object number to read (1-32). +//! \param pMsgObject points to a structure containing message object fields. +//! \param bClrPendingInt indicates whether an associated interrupt should be +//! cleared. +//! +//! This function is used to read the contents of one of the 32 message objects +//! in the CAN controller, and return it to the caller. The data returned is +//! stored in the fields of the caller-supplied structure pointed to by +//! \e pMsgObject. The data consists of all of the parts of a CAN message, +//! plus some control and status information. +//! +//! Normally this is used to read a message object that has received and stored +//! a CAN message with a certain identifier. However, this could also be used +//! to read the contents of a message object in order to load the fields of the +//! structure in case only part of the structure needs to be changed from a +//! previous setting. +//! +//! When using CANMessageGet, all of the same fields of the structure are +//! populated in the same way as when the CANMessageSet() function is used, +//! with the following exceptions: +//! +//! \e pMsgObject->ui32Flags: +//! +//! - \b MSG_OBJ_NEW_DATA indicates if this is new data since the last time it +//! was read +//! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on +//! this message object, and not read by the host before being overwritten. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, tCANMsgObject *pMsgObject, + bool bClrPendingInt) +{ + uint32_t ui32CmdMaskReg; + uint32_t ui32MaskReg; + uint32_t ui32ArbReg; + uint32_t ui32MsgCtrl; + + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32ObjID <= 32) && (ui32ObjID != 0)); + + // This is always a read to the Message object as this call is setting a + // message object. + ui32CmdMaskReg = (CAN_IF2CMD_DATA_A | CAN_IF2CMD_DATA_B | + CAN_IF2CMD_CONTROL | CAN_IF2CMD_MASK | CAN_IF2CMD_ARB); + + // Clear a pending interrupt and new data in a message object. + if(bClrPendingInt) + { + ui32CmdMaskReg |= CAN_IF2CMD_CLRINTPND | CAN_IF2CMD_TXRQST; + } + + // Set up the request for data from the message object. + HWREGH(ui32Base + CAN_O_IF2CMD + 2) = ui32CmdMaskReg >> 16; + + // Transfer the message object to the message object specified by ui32ObjID. + HWREGH(ui32Base + CAN_O_IF2CMD) = ui32ObjID & CAN_IF2CMD_MSG_NUM_M; + + // Wait for busy bit to clear + while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) + { + } + + // Read out the IF Registers. + ui32MaskReg = HWREG(ui32Base + CAN_O_IF2MSK); + ui32ArbReg = HWREG(ui32Base + CAN_O_IF2ARB); + ui32MsgCtrl = HWREG(ui32Base + CAN_O_IF2MCTL); + pMsgObject->ui32Flags = MSG_OBJ_NO_FLAGS; + + // Determine if this is a remote frame by checking the TXRQST and DIR bits. + if((!(ui32MsgCtrl & CAN_IF2MCTL_TXRQST) && (ui32ArbReg & CAN_IF2ARB_DIR)) || + ((ui32MsgCtrl & CAN_IF2MCTL_TXRQST) && (!(ui32ArbReg & CAN_IF2ARB_DIR)))) + { + pMsgObject->ui32Flags |= MSG_OBJ_REMOTE_FRAME; + } + + // Get the identifier out of the register, the format depends on size of + // the mask. + if(ui32ArbReg & CAN_IF2ARB_XTD) + { + // Set the 29 bit version of the Identifier for this message object. + pMsgObject->ui32MsgID = ui32ArbReg & CAN_IF2ARB_ID_M; + + pMsgObject->ui32Flags |= MSG_OBJ_EXTENDED_ID; + } + else + { + // The Identifier is an 11 bit value. + pMsgObject->ui32MsgID = (ui32ArbReg & + CAN_IF2ARB_STD_ID_M) >> CAN_IF2ARB_STD_ID_S; + } + + // Indicate that we lost some data. + if(ui32MsgCtrl & CAN_IF2MCTL_MSGLST) + { + pMsgObject->ui32Flags |= MSG_OBJ_DATA_LOST; + } + + // Set the flag to indicate if ID masking was used. + if(ui32MsgCtrl & CAN_IF2MCTL_UMASK) + { + if(ui32ArbReg & CAN_IF2ARB_XTD) + { + // The Identifier Mask is assumed to also be a 29 bit value. + pMsgObject->ui32MsgIDMask = (ui32MaskReg & CAN_IF2MSK_MSK_M); + + // If this is a fully specified Mask and a remote frame then don't + // set the MSG_OBJ_USE_ID_FILTER because the ID was not really + // filtered. + if((pMsgObject->ui32MsgIDMask != 0x1fffffff) || + ((pMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)) + { + pMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER; + } + } + else + { + // The Identifier Mask is assumed to also be an 11 bit value. + pMsgObject->ui32MsgIDMask = ((ui32MaskReg & CAN_IF2MSK_MSK_M) >> + 18); + + // If this is a fully specified Mask and a remote frame then don't + // set the MSG_OBJ_USE_ID_FILTER because the ID was not really + // filtered. + if((pMsgObject->ui32MsgIDMask != 0x7ff) || + ((pMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0)) + { + pMsgObject->ui32Flags |= MSG_OBJ_USE_ID_FILTER; + } + } + + // Indicate if the extended bit was used in filtering. + if(ui32MaskReg & CAN_IF2MSK_MXTD) + { + pMsgObject->ui32Flags |= MSG_OBJ_USE_EXT_FILTER; + } + + // Indicate if direction filtering was enabled. + if(ui32MaskReg & CAN_IF2MSK_MDIR) + { + pMsgObject->ui32Flags |= MSG_OBJ_USE_DIR_FILTER; + } + } + + // Set the interrupt flags. + if(ui32MsgCtrl & CAN_IF2MCTL_TXIE) + { + pMsgObject->ui32Flags |= MSG_OBJ_TX_INT_ENABLE; + } + if(ui32MsgCtrl & CAN_IF2MCTL_RXIE) + { + pMsgObject->ui32Flags |= MSG_OBJ_RX_INT_ENABLE; + } + + // See if there is new data available. + if(ui32MsgCtrl & CAN_IF2MCTL_NEWDAT) + { + // Get the amount of data needed to be read. + pMsgObject->ui32MsgLen = (ui32MsgCtrl & CAN_IF2MCTL_DLC_M); + + // Don't read any data for a remote frame, there is nothing valid in + // that buffer anyway. + if((pMsgObject->ui32Flags & MSG_OBJ_REMOTE_FRAME) == 0) + { + // Read out the data from the CAN registers. + CANDataRegRead(pMsgObject->pucMsgData, + (uint32_t *)(ui32Base + CAN_O_IF2DATA), + pMsgObject->ui32MsgLen); + } + + // Now clear out the new data flag. + HWREGH(ui32Base + CAN_O_IF2CMD + 2) = CAN_IF2CMD_TXRQST >> 16; + + // Transfer the message object to the message object specified by + // ui32ObjID. + HWREGH(ui32Base + CAN_O_IF2CMD) = ui32ObjID & CAN_IF2CMD_MSG_NUM_M; + + // Wait for busy bit to clear + while(HWREGH(ui32Base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) + { + } + + // Indicate that there is new data in this message. + pMsgObject->ui32Flags |= MSG_OBJ_NEW_DATA; + } + else + { + // Along with the MSG_OBJ_NEW_DATA not being set the amount of data + // needs to be set to zero if none was available. + pMsgObject->ui32MsgLen = 0; + } +} + +//***************************************************************************** +// +//! Clears a message object so that it is no longer used. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32ObjID is the message object number to disable (1-32). +//! +//! This function frees the specified message object from use. Once a message +//! object has been ``cleared,'' it will no longer automatically send or +//! receive messages, or generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +void +CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32ObjID >= 1) && (ui32ObjID <= 32)); + + // Wait for busy bit to clear + while(HWREGH(ui32Base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) + { + } + + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid. + HWREGH(ui32Base + CAN_O_IF1CMD + 2) = (CAN_IF1CMD_DIR | + CAN_IF1CMD_ARB) >> 16; + HWREGH(ui32Base + CAN_O_IF1ARB) = 0; + HWREGH(ui32Base + CAN_O_IF1ARB + 2) = 0; + + // Initiate programming the message object + HWREGH(ui32Base + CAN_O_IF1CMD) = ui32ObjID & CAN_IF1CMD_MSG_NUM_M; +} + +//***************************************************************************** +// +//! CAN Global interrupt Enable function. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific CAN interrupt in the global interrupt enable register +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! CAN_GLB_INT_CANINT0 -Global Interrupt Enable bit for CAN INT0 +//! CAN_GLB_INT_CANINT1 -Global Interrupt Enable bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +void +CANGlobalIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 | + CAN_GLB_INT_CANINT1)) == 0); + + //enable the requested interrupts + HWREGH(ui32Base + CAN_O_GLB_INT_EN) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Disable function. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Disables the specific CAN interrupt in the global interrupt enable register +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! CAN_GLB_INT_CANINT0 -Global Interrupt bit for CAN INT0 +//! CAN_GLB_INT_CANINT1 -Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +void +CANGlobalIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 | + CAN_GLB_INT_CANINT1)) == 0); + + //disable the requested interrupts + HWREGH(ui32Base + CAN_O_GLB_INT_EN) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Clear function. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Clear the specific CAN interrupt bit in the global interrupt flag register. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! CAN_GLB_INT_CANINT0 -Global Interrupt bit for CAN INT0 +//! CAN_GLB_INT_CANINT1 -Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +void +CANGlobalIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 | + CAN_GLB_INT_CANINT1)) == 0); + + //clear the requested interrupts + HWREGH(ui32Base + CAN_O_GLB_INT_CLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Status function. +//! +//! \param ui32Base is the base address of the CAN controller. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be checked. +//! +//! Get the status of the specific CAN interrupt bits in the global interrupt +//! flag register. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! CAN_GLB_INT_CANINT0 -Global Interrupt bit for CAN INT0 +//! CAN_GLB_INT_CANINT1 -Global Interrupt bit for CAN INT1 +//! +//! \return True if any of the requested interrupt bit(s) is (are) set. +// +//***************************************************************************** +bool +CANGlobalIntstatusGet(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(CANBaseValid(ui32Base)); + ASSERT((ui32IntFlags & ~(CAN_GLB_INT_CANINT0 | + CAN_GLB_INT_CANINT1)) == 0); + + //enable the requested interrupts + if(HWREGH(ui32Base + CAN_O_GLB_INT_FLG) & ui32IntFlags) + { + return true; + } + else + { + return false; + } +} + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.h new file mode 100644 index 00000000000..471d1fcc6d8 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/can.h @@ -0,0 +1,415 @@ +//########################################################################### +// +// FILE: can.h +// +// TITLE: Defines and Macros for the CAN controller. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __CAN_H__ +#define __CAN_H__ + +//***************************************************************************** +//! \addtogroup can_api +//! @{ +//***************************************************************************** + +//***************************************************************************** +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + + +#define CAN_INDEX_TO_BASE(idx) ((idx == 0) ? CAN_A_BASE : CAN_B_BASE) + +#define CAN_INDEX_TO_MSG_RAM_BASE(idx) ((idx == 0) ? CAN_A_MSG_RAM : CAN_B_MSG_RAM) + +#define CAN_REG_WORD_MASK (0xFFFFU) + +//**************************************************************************** +// These are the Defines to select CAN pin muxing when calling the functions +// ConfigCanPinMuxing(), ConfigGpioCanA() & ConfigGpioCanB() in F2837x_Can.c +//**************************************************************************** +#define CAN_A_GPIO4_GPIO5 1 //switch case 1 +#define CAN_A_GPIO19_GPIO18 2 //switch case 2 +#define CAN_A_GPIO31_GPIO30 3 //switch case 3 +#define CAN_A_GPIO37_GPIO36 4 //switch case 4 +#define CAN_A_GPIO63_GPIO62 5 //switch case 5 +#define CAN_A_GPIO71_GPIO70 6 //switch case 6 + +#define CAN_B_GPIO6_GPIO7 1 //switch case 1 +#define CAN_B_GPIO8_GPIO10 2 //switch case 2 +#define CAN_B_GPIO12_GPIO13 3 //switch case 3 +#define CAN_B_GPIO16_GPIO17 4 //switch case 4 +#define CAN_B_GPIO20_GPIO21 5 //switch case 5 +#define CAN_B_GPIO38_GPIO39 6 //switch case 6 +#define CAN_B_GPIO72_GPIO73 7 //switch case 7 + +//***************************************************************************** +// Miscellaneous defines for Message ID Types +//***************************************************************************** + +//***************************************************************************** +// These are the flags used by the tCANMsgObject.ui32Flags value when calling the +// CANMessageSet() and CANMessageGet() functions. +//***************************************************************************** + +//! This definition is used with the tCANMsgObject ui32Flags value and indicates +//! that transmit interrupts should be enabled, or are enabled. +#define MSG_OBJ_TX_INT_ENABLE 0x00000001 + +//! This indicates that receive interrupts should be enabled, or are +//! enabled. +#define MSG_OBJ_RX_INT_ENABLE 0x00000002 + +//! This indicates that a message object will use or is using an extended +//! identifier. +#define MSG_OBJ_EXTENDED_ID 0x00000004 + +//! This indicates that a message object will use or is using filtering +//! based on the object's message identifier. +#define MSG_OBJ_USE_ID_FILTER 0x00000008 + +//! This indicates that new data was available in the message object. +#define MSG_OBJ_NEW_DATA 0x00000080 + +//! This indicates that data was lost since this message object was last +//! read. +#define MSG_OBJ_DATA_LOST 0x00000100 + +//! This indicates that a message object will use or is using filtering +//! based on the direction of the transfer. If the direction filtering is +//! used, then ID filtering must also be enabled. +#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER) + +//! This indicates that a message object will use or is using message +//! identifier filtering based on the extended identifier. If the extended +//! identifier filtering is used, then ID filtering must also be enabled. +#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER) + +//! This indicates that a message object is a remote frame. +#define MSG_OBJ_REMOTE_FRAME 0x00000040 + +//! This indicates that this message object is part of a FIFO structure and +//! not the final message object in a FIFO. +#define MSG_OBJ_FIFO 0x00000200 + +//! This indicates that a message object has no flags set. +#define MSG_OBJ_NO_FLAGS 0x00000000 + +//***************************************************************************** +//! This define is used with the flag values to allow checking only status +//! flags and not configuration flags. +//***************************************************************************** +#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) + +//***************************************************************************** +//! The structure used for encapsulating all the items associated with a CAN +//! message object in the CAN controller. +//***************************************************************************** +typedef struct +{ + //! The CAN message identifier used for 11 or 29 bit identifiers. + uint32_t ui32MsgID; + + //! The message identifier mask used when identifier filtering is enabled. + uint32_t ui32MsgIDMask; + + //! This value holds various status flags and settings specified by + //! tCANObjFlags. + uint32_t ui32Flags; + + //! This value is the number of bytes of data in the message object. + uint32_t ui32MsgLen; + + //! This is a pointer to the message object's data. + unsigned char *pucMsgData; +} +tCANMsgObject; + +//***************************************************************************** +//! This structure is used for encapsulating the values associated with setting +//! up the bit timing for a CAN controller. The structure is used when calling +//! the CANGetBitTiming and CANSetBitTiming functions. +//***************************************************************************** +typedef struct +{ + //! This value holds the sum of the Synchronization, Propagation, and Phase + //! Buffer 1 segments, measured in time quanta. The valid values for this + //! setting range from 2 to 16. + uint16_t uSyncPropPhase1Seg; + + //! This value holds the Phase Buffer 2 segment in time quanta. The valid + //! values for this setting range from 1 to 8. + uint16_t uPhase2Seg; + + //! This value holds the Resynchronization Jump Width in time quanta. The + //! valid values for this setting range from 1 to 4. + uint16_t uSJW; + + //! This value holds the CAN_CLK divider used to determine time quanta. + //! The valid values for this setting range from 1 to 1023. + uint16_t uQuantumPrescaler; +} +tCANBitClkParms; + +//***************************************************************************** +//! This data type is used to identify the interrupt status register. This is +//! used when calling the CANIntStatus() function. +//***************************************************************************** +typedef enum +{ + //! Read the CAN interrupt status information. + CAN_INT_STS_CAUSE, + + //! Read a message object's interrupt status. + CAN_INT_STS_OBJECT +} +tCANIntStsReg; + +//***************************************************************************** +//! This data type is used to identify which of several status registers to +//! read when calling the CANStatusGet() function. +//***************************************************************************** +typedef enum +{ + //! Read the full CAN controller status. + CAN_STS_CONTROL, + + //! Read the full 32-bit mask of message objects with a transmit request + //! set. + CAN_STS_TXREQUEST, + + //! Read the full 32-bit mask of message objects with new data available. + CAN_STS_NEWDAT, + + //! Read the full 32-bit mask of message objects that are enabled. + CAN_STS_MSGVAL +} +tCANStsReg; + +//***************************************************************************** +// These definitions are used to specify interrupt sources to CANIntEnable() +// and CANIntDisable(). +//***************************************************************************** +//! This flag is used to allow a CAN controller to generate error +//! interrupts. +#define CAN_INT_ERROR 0x00000008 + +//! This flag is used to allow a CAN controller to generate status +//! interrupts. +#define CAN_INT_STATUS 0x00000004 + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 0 +#define CAN_INT_IE0 0x00000002 + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 1 +#define CAN_INT_IE1 0x00020000 + +// Defined to maintain compatibility with Stellaris Examples +#define CAN_INT_MASTER CAN_INT_IE0 + +//***************************************************************************** +// These definitions are used to specify the clock source to +// CANClkSourceSelect() +//***************************************************************************** +//! This flag is used to clock the CAN controller Selected CPU SYSCLKOUT +//! (CPU1.Sysclk or CPU2.Sysclk). +#define CAN_CLK_CPU_SYSCLKOUT 0 // PERx.SYSCLK (default on reset) + +//! This flag is used to clock the CAN controller with the X1/X2 oscillator +//! clock. +#define CAN_CLK_EXT_OSC 1 // External Oscillator (XTAL) + +//! This flag is used to clock the CAN controller with the clock from +//! AUXCLKIN (from GPIO) +#define CAN_CLK_AUXCLKIN 2 // AUXCLKIN (from GPIO) + + +//***************************************************************************** +//! This definition is used to determine the type of message object that will +//! be set up via a call to the CANMessageSet() API. +//***************************************************************************** +typedef enum +{ + //! Transmit message object. + MSG_OBJ_TYPE_TX, + + //! Transmit remote request message object + MSG_OBJ_TYPE_TX_REMOTE, + + //! Receive message object. + MSG_OBJ_TYPE_RX, + + //! Receive remote request message object. + MSG_OBJ_TYPE_RX_REMOTE, + + //! Remote frame receive remote, with auto-transmit message object. + MSG_OBJ_TYPE_RXTX_REMOTE +} +tMsgObjType; + +//***************************************************************************** +// The following enumeration contains all error or status indicators that can +// be returned when calling the CANStatusGet() function. +//***************************************************************************** +//! CAN controller is in local power down mode. +#define CAN_STATUS_PDA 0x00000400 + +//! CAN controller has initiated a system wakeup. +#define CAN_STATUS_WAKE_UP 0x00000200 + +//! CAN controller has detected a parity error. +#define CAN_STATUS_PERR 0x00000100 + +//! CAN controller has entered a Bus Off state. +#define CAN_STATUS_BUS_OFF 0x00000080 + +//! CAN controller error level has reached warning level. +#define CAN_STATUS_EWARN 0x00000040 + +//! CAN controller error level has reached error passive level. +#define CAN_STATUS_EPASS 0x00000020 + +//! A message was received successfully since the last read of this status. +#define CAN_STATUS_RXOK 0x00000010 + +//! A message was transmitted successfully since the last read of this +//! status. +#define CAN_STATUS_TXOK 0x00000008 + +//! This is the mask for the last error code field. +#define CAN_STATUS_LEC_MSK 0x00000007 + +//! There was no error. +#define CAN_STATUS_LEC_NONE 0x00000000 + +//! A bit stuffing error has occurred. +#define CAN_STATUS_LEC_STUFF 0x00000001 + +//! A formatting error has occurred. +#define CAN_STATUS_LEC_FORM 0x00000002 + +//! An acknowledge error has occurred. +#define CAN_STATUS_LEC_ACK 0x00000003 + +//! The bus remained a bit level of 1 for longer than is allowed. +#define CAN_STATUS_LEC_BIT1 0x00000004 + +//! The bus remained a bit level of 0 for longer than is allowed. +#define CAN_STATUS_LEC_BIT0 0x00000005 + +//! A CRC error has occurred. +#define CAN_STATUS_LEC_CRC 0x00000006 + +//***************************************************************************** +// The following macros are added for the new Global Interrupt EN/FLG/CLR +// register +//***************************************************************************** +//CANINT0 global interrupt bit +#define CAN_GLOBAL_INT_CANINT0 0x00000001 + +//CANINT1 global interrupt bit +#define CAN_GLOBAL_INT_CANINT1 0x00000002 + +//***************************************************************************** +// The following macros are missing in hw_can.h because of scripting +// but driverlib can.c needs them +//***************************************************************************** + +#define CAN_INT_INT0ID_STATUS 0x8000 + +#define CAN_IF1ARB_STD_ID_S 18 +#define CAN_IF1ARB_STD_ID_M 0x1FFC0000 // Standard Message Identifier + +#define CAN_IF2ARB_STD_ID_S 18 +#define CAN_IF2ARB_STD_ID_M 0x1FFC0000 // Standard Message Identifier + +//***************************************************************************** +// API Function prototypes +//***************************************************************************** +extern void CANClkSourceSelect(uint32_t ui32Base, uint16_t ucSource); +extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *pClkParms); +extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *pClkParms); +extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock, + uint32_t ui32BitRate); +extern void CANDisable(uint32_t ui32Base); +extern void CANEnable(uint32_t ui32Base); +extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount, + uint32_t *pui32TxCount); +extern void CANInit(uint32_t ui32Base); +extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr); +extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void CANIntRegister(uint32_t ui32Base, unsigned char ucIntNumber, + void (*pfnHandler)(void)); +extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg); +extern void CANIntUnregister(uint32_t ui32Base, unsigned char ucIntNumber); +extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID); +extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, + tCANMsgObject *pMsgObject, bool bClrPendingInt); +extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID, + tCANMsgObject *pMsgObject, tMsgObjType eMsgType); +extern bool CANRetryGet(uint32_t ui32Base); +extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry); +extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg); +extern void CANGlobalIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void CANGlobalIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void CANGlobalIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern bool CANGlobalIntstatusGet(uint32_t ui32Base, uint32_t ui32IntFlags); + +//***************************************************************************** +// Mark the end of the C bindings section for C++ compilers. +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + +#endif // __CAN_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/debug.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/debug.h new file mode 100644 index 00000000000..8d018c0c7c8 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/debug.h @@ -0,0 +1,75 @@ +//########################################################################### +// +// FILE: debug.h +// +// TITLE: Stellaris style debug header. Included for compatability. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** + + +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.c new file mode 100644 index 00000000000..5bff0345ab1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.c @@ -0,0 +1,411 @@ +//########################################################################### +// +// FILE: interrupt.c +// +// TITLE: Stellaris style wrapper driver for C28x PIE Interrupt Controller. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include "F28x_Project.h" + +#include "inc/hw_types.h" +#include "driverlib/interrupt.h" +#include +#include +#include + + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler. Whenever an interrupt is +//! unregisterd this handler takes it place. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void IntDefaultHandler(void) +{ + asm(" ESTOP0"); + return; +} + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! Allows the processor to respond to interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! bool, a compiler error will occur in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +bool +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + return __enable_interrupts() & 0x1; +} + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! Prevents the processor from receiving interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \note Previously, this function had no return value. As such, it was +//! possible to include interrupt.h and call this function without +//! having included hw_types.h. Now that the return is a +//! bool, a compiler error will occur in this case. The solution +//! is to include hw_types.h before including interrupt.h. +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +bool +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + return __disable_interrupts() & 0x1; +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +// +//! Assumes PIE is enabled +//! +//! \param ui32Interrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via IntEnable()), the handler function will be called in +//! interrupt context. Since the handler function can pre-empt other code, care +//! must be taken to protect memory or peripherals that are accessed by the +//! handler and other non-handler code. +//! +//! \return None. +// +//***************************************************************************** +void +IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)) +{ + EALLOW; + //Copy ISR address into PIE table + memcpy((uint16_t *) &PieVectTable + ((ui32Interrupt & 0xFFFF0000) >> 16)*2, (uint16_t *) &pfnHandler, sizeof(pfnHandler)); + EDIS; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ui32Interrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler should be called when the +//! given interrupt is asserted to the processor. The interrupt source will be +//! automatically disabled (via IntDisable()) if necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +IntUnregister(uint32_t ui32Interrupt) +{ + uint32_t temp; + + temp = (uint32_t) IntDefaultHandler; + + EALLOW; + //Copy default ISR address into PIE table + memcpy((uint16_t *) &PieVectTable + ((ui32Interrupt & 0xFFFF0000) >> 16)*2, (uint16_t *) &temp, sizeof(temp)); + EDIS; +} + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntEnable(uint32_t ui32Interrupt) +{ + uint16_t ui16IntsEnabled; + + ui32Interrupt = ui32Interrupt >> 16; + EALLOW; + //Ensure that PIE is enabled + PieCtrlRegs.PIECTRL.bit.ENPIE=1; + + ui16IntsEnabled = IntMasterDisable(); + + if (ui32Interrupt >= 0x20 && ui32Interrupt <= 0x7F) //Lower PIE table + { + //Enable Individual PIE interrupt + *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x20)/8))*2) |= 1 << ((ui32Interrupt-0x20)%8); + + // Wait for any pending interrupts to get to the CPU + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + + //Clear the CPU flag + IntIFRClear(1 << ((ui32Interrupt - 0x20)/8)); + + //Acknowlege any interrupts + PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x20)/8); + + //Enable PIE Group Interrupt + IER |= 1 << ((ui32Interrupt - 0x20)/8); + } + else if (ui32Interrupt >= 0x80) //Upper PIE table + { + //Enable Individual PIE interrupt + *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x80)/8))*2) |= 1 << (((ui32Interrupt-0x80)%8)+8); + + // Wait for any pending interrupts to get to the CPU + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + + //Clear the CPU flag + IntIFRClear(1 << ((ui32Interrupt - 0x80)/8)); + + //Acknowlege any interrupts + PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x80)/8); + + //Enable PIE Group Interrupt + IER |= 1 << ((ui32Interrupt - 0x80)/8); + } + else if (ui32Interrupt >= 0x0D && ui32Interrupt <= 0x10) //INT13, INT14, DLOGINT, & RTOSINT + { + //Enable PIE Group Interrupt + IER |= 1 << (ui32Interrupt - 1); + } + else + { + //Other interrupts + } + + EDIS; + + //Re-enable interrupts if they were enabled + if(!ui16IntsEnabled){ + IntMasterEnable(); + } +} + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ui32Interrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +void +IntDisable(uint32_t ui32Interrupt) +{ + uint16_t ui16IntsEnabled; + + ui32Interrupt = ui32Interrupt >> 16; + EALLOW; + + ui16IntsEnabled = IntMasterDisable(); + + if (ui32Interrupt >= 0x20 && ui32Interrupt <= 0x7F) //Lower PIE table + { + //Disable Individual PIE interrupt + *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x20)/8))*2) &= ~(1 << ((ui32Interrupt-0x20)%8)); + + // Wait for any pending interrupts to get to the CPU + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + + //Clear the CPU flag + IntIFRClear(1 << ((ui32Interrupt - 0x20)/8)); + + //Acknowlege any interrupts + PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x20)/8); + } + else if (ui32Interrupt >= 0x80) //Upper PIE table + { + //Disable Individual PIE interrupt + *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x80)/8))*2) &= ~(1 << (((ui32Interrupt-0x80)%8)+8)); + + // Wait for any pending interrupts to get to the CPU + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + + //Clear the CPU flag + IntIFRClear(1 << ((ui32Interrupt - 0x80)/8)); + + //Acknowlege any interrupts + PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x80)/8); + } + else if (ui32Interrupt >= 0x0D && ui32Interrupt <= 0x10) //INT13, INT14, DLOGINT, & RTOSINT //Work-around Case + { + //Disable PIE Group Interrupt + IER &= ~(1 << (ui32Interrupt - 1)); + } + else + { + //Other Interrupts + } + EDIS; + + //Re-enable interrupts if they were enabled + if(!ui16IntsEnabled){ + IntMasterEnable(); + } +} + +void IntIFRClear(uint16_t ui16Interrupts) +{ + switch(ui16Interrupts){ + case 0x0001: + IFR &= ~0x0001; + break; + case 0x0002: + IFR &= ~0x0002; + break; + case 0x0004: + IFR &= ~0x0004; + break; + case 0x0008: + IFR &= ~0x0008; + break; + case 0x0010: + IFR &= ~0x0010; + break; + case 0x0020: + IFR &= ~0x0020; + break; + case 0x0040: + IFR &= ~0x0040; + break; + case 0x0080: + IFR &= ~0x0080; + break; + case 0x0100: + IFR &= ~0x0100; + break; + case 0x0200: + IFR &= ~0x0200; + break; + case 0x0400: + IFR &= ~0x0400; + break; + case 0x0800: + IFR &= ~0x0800; + break; + case 0x1000: + IFR &= ~0x1000; + break; + case 0x2000: + IFR &= ~0x2000; + break; + case 0x4000: + IFR &= ~0x4000; + break; + case 0x8000: + IFR &= ~0x8000; + break; + default: + break; + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.h new file mode 100644 index 00000000000..d6104fba3fd --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/interrupt.h @@ -0,0 +1,81 @@ +//########################################################################### +// +// FILE: interrupt.h +// +// TITLE: Stellaris style wrapper driver for C28x PIE Interrupt Controller. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + extern bool IntMasterEnable(void); + extern bool IntMasterDisable(void); + extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); + extern void IntUnregister(uint32_t ui32Interrupt); + extern void IntEnable(uint32_t ui32Interrupt); + extern void IntDisable(uint32_t ui32Interrupt); + extern void IntIFRClear(uint16_t ui16Interrupts); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom.h new file mode 100644 index 00000000000..c085a00c61a --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom.h @@ -0,0 +1,44 @@ +//***************************************************************************** +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ROM_H__ +#define __ROM_H__ + + +#endif //__ROM_H__ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom_map.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom_map.h new file mode 100644 index 00000000000..7794c1a9d06 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rom_map.h @@ -0,0 +1,5082 @@ +//***************************************************************************** +// +// rom_map.h - Macros to facilitate calling functions in the ROM when they are +// available and in flash otherwise. +// +// Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ROM_MAP_H__ +#define __ROM_MAP_H__ + +//***************************************************************************** +// +// Macros for the ADC API. +// +//***************************************************************************** +#ifdef ROM_ADCSequenceDataGet +#define MAP_ADCSequenceDataGet \ + ROM_ADCSequenceDataGet +#else +#define MAP_ADCSequenceDataGet \ + ADCSequenceDataGet +#endif +#ifdef ROM_ADCIntDisable +#define MAP_ADCIntDisable \ + ROM_ADCIntDisable +#else +#define MAP_ADCIntDisable \ + ADCIntDisable +#endif +#ifdef ROM_ADCIntEnable +#define MAP_ADCIntEnable \ + ROM_ADCIntEnable +#else +#define MAP_ADCIntEnable \ + ADCIntEnable +#endif +#ifdef ROM_ADCIntStatus +#define MAP_ADCIntStatus \ + ROM_ADCIntStatus +#else +#define MAP_ADCIntStatus \ + ADCIntStatus +#endif +#ifdef ROM_ADCIntClear +#define MAP_ADCIntClear \ + ROM_ADCIntClear +#else +#define MAP_ADCIntClear \ + ADCIntClear +#endif +#ifdef ROM_ADCSequenceEnable +#define MAP_ADCSequenceEnable \ + ROM_ADCSequenceEnable +#else +#define MAP_ADCSequenceEnable \ + ADCSequenceEnable +#endif +#ifdef ROM_ADCSequenceDisable +#define MAP_ADCSequenceDisable \ + ROM_ADCSequenceDisable +#else +#define MAP_ADCSequenceDisable \ + ADCSequenceDisable +#endif +#ifdef ROM_ADCSequenceConfigure +#define MAP_ADCSequenceConfigure \ + ROM_ADCSequenceConfigure +#else +#define MAP_ADCSequenceConfigure \ + ADCSequenceConfigure +#endif +#ifdef ROM_ADCSequenceStepConfigure +#define MAP_ADCSequenceStepConfigure \ + ROM_ADCSequenceStepConfigure +#else +#define MAP_ADCSequenceStepConfigure \ + ADCSequenceStepConfigure +#endif +#ifdef ROM_ADCSequenceOverflow +#define MAP_ADCSequenceOverflow \ + ROM_ADCSequenceOverflow +#else +#define MAP_ADCSequenceOverflow \ + ADCSequenceOverflow +#endif +#ifdef ROM_ADCSequenceOverflowClear +#define MAP_ADCSequenceOverflowClear \ + ROM_ADCSequenceOverflowClear +#else +#define MAP_ADCSequenceOverflowClear \ + ADCSequenceOverflowClear +#endif +#ifdef ROM_ADCSequenceUnderflow +#define MAP_ADCSequenceUnderflow \ + ROM_ADCSequenceUnderflow +#else +#define MAP_ADCSequenceUnderflow \ + ADCSequenceUnderflow +#endif +#ifdef ROM_ADCSequenceUnderflowClear +#define MAP_ADCSequenceUnderflowClear \ + ROM_ADCSequenceUnderflowClear +#else +#define MAP_ADCSequenceUnderflowClear \ + ADCSequenceUnderflowClear +#endif +#ifdef ROM_ADCProcessorTrigger +#define MAP_ADCProcessorTrigger \ + ROM_ADCProcessorTrigger +#else +#define MAP_ADCProcessorTrigger \ + ADCProcessorTrigger +#endif +#ifdef ROM_ADCHardwareOversampleConfigure +#define MAP_ADCHardwareOversampleConfigure \ + ROM_ADCHardwareOversampleConfigure +#else +#define MAP_ADCHardwareOversampleConfigure \ + ADCHardwareOversampleConfigure +#endif +#ifdef ROM_ADCComparatorConfigure +#define MAP_ADCComparatorConfigure \ + ROM_ADCComparatorConfigure +#else +#define MAP_ADCComparatorConfigure \ + ADCComparatorConfigure +#endif +#ifdef ROM_ADCComparatorRegionSet +#define MAP_ADCComparatorRegionSet \ + ROM_ADCComparatorRegionSet +#else +#define MAP_ADCComparatorRegionSet \ + ADCComparatorRegionSet +#endif +#ifdef ROM_ADCComparatorReset +#define MAP_ADCComparatorReset \ + ROM_ADCComparatorReset +#else +#define MAP_ADCComparatorReset \ + ADCComparatorReset +#endif +#ifdef ROM_ADCComparatorIntDisable +#define MAP_ADCComparatorIntDisable \ + ROM_ADCComparatorIntDisable +#else +#define MAP_ADCComparatorIntDisable \ + ADCComparatorIntDisable +#endif +#ifdef ROM_ADCComparatorIntEnable +#define MAP_ADCComparatorIntEnable \ + ROM_ADCComparatorIntEnable +#else +#define MAP_ADCComparatorIntEnable \ + ADCComparatorIntEnable +#endif +#ifdef ROM_ADCComparatorIntStatus +#define MAP_ADCComparatorIntStatus \ + ROM_ADCComparatorIntStatus +#else +#define MAP_ADCComparatorIntStatus \ + ADCComparatorIntStatus +#endif +#ifdef ROM_ADCComparatorIntClear +#define MAP_ADCComparatorIntClear \ + ROM_ADCComparatorIntClear +#else +#define MAP_ADCComparatorIntClear \ + ADCComparatorIntClear +#endif +#ifdef ROM_ADCReferenceSet +#define MAP_ADCReferenceSet \ + ROM_ADCReferenceSet +#else +#define MAP_ADCReferenceSet \ + ADCReferenceSet +#endif +#ifdef ROM_ADCReferenceGet +#define MAP_ADCReferenceGet \ + ROM_ADCReferenceGet +#else +#define MAP_ADCReferenceGet \ + ADCReferenceGet +#endif +#ifdef ROM_ADCPhaseDelaySet +#define MAP_ADCPhaseDelaySet \ + ROM_ADCPhaseDelaySet +#else +#define MAP_ADCPhaseDelaySet \ + ADCPhaseDelaySet +#endif +#ifdef ROM_ADCPhaseDelayGet +#define MAP_ADCPhaseDelayGet \ + ROM_ADCPhaseDelayGet +#else +#define MAP_ADCPhaseDelayGet \ + ADCPhaseDelayGet +#endif +#ifdef ROM_ADCResolutionSet +#define MAP_ADCResolutionSet \ + ROM_ADCResolutionSet +#else +#define MAP_ADCResolutionSet \ + ADCResolutionSet +#endif +#ifdef ROM_ADCResolutionGet +#define MAP_ADCResolutionGet \ + ROM_ADCResolutionGet +#else +#define MAP_ADCResolutionGet \ + ADCResolutionGet +#endif + +//***************************************************************************** +// +// Macros for the CAN API. +// +//***************************************************************************** +#ifdef ROM_CANIntClear +#define MAP_CANIntClear \ + ROM_CANIntClear +#else +#define MAP_CANIntClear \ + CANIntClear +#endif +#ifdef ROM_CANInit +#define MAP_CANInit \ + ROM_CANInit +#else +#define MAP_CANInit \ + CANInit +#endif +#ifdef ROM_CANEnable +#define MAP_CANEnable \ + ROM_CANEnable +#else +#define MAP_CANEnable \ + CANEnable +#endif +#ifdef ROM_CANDisable +#define MAP_CANDisable \ + ROM_CANDisable +#else +#define MAP_CANDisable \ + CANDisable +#endif +#ifdef ROM_CANBitTimingSet +#define MAP_CANBitTimingSet \ + ROM_CANBitTimingSet +#else +#define MAP_CANBitTimingSet \ + CANBitTimingSet +#endif +#ifdef ROM_CANBitTimingGet +#define MAP_CANBitTimingGet \ + ROM_CANBitTimingGet +#else +#define MAP_CANBitTimingGet \ + CANBitTimingGet +#endif +#ifdef ROM_CANMessageSet +#define MAP_CANMessageSet \ + ROM_CANMessageSet +#else +#define MAP_CANMessageSet \ + CANMessageSet +#endif +#ifdef ROM_CANMessageGet +#define MAP_CANMessageGet \ + ROM_CANMessageGet +#else +#define MAP_CANMessageGet \ + CANMessageGet +#endif +#ifdef ROM_CANStatusGet +#define MAP_CANStatusGet \ + ROM_CANStatusGet +#else +#define MAP_CANStatusGet \ + CANStatusGet +#endif +#ifdef ROM_CANMessageClear +#define MAP_CANMessageClear \ + ROM_CANMessageClear +#else +#define MAP_CANMessageClear \ + CANMessageClear +#endif +#ifdef ROM_CANIntEnable +#define MAP_CANIntEnable \ + ROM_CANIntEnable +#else +#define MAP_CANIntEnable \ + CANIntEnable +#endif +#ifdef ROM_CANIntDisable +#define MAP_CANIntDisable \ + ROM_CANIntDisable +#else +#define MAP_CANIntDisable \ + CANIntDisable +#endif +#ifdef ROM_CANIntStatus +#define MAP_CANIntStatus \ + ROM_CANIntStatus +#else +#define MAP_CANIntStatus \ + CANIntStatus +#endif +#ifdef ROM_CANRetryGet +#define MAP_CANRetryGet \ + ROM_CANRetryGet +#else +#define MAP_CANRetryGet \ + CANRetryGet +#endif +#ifdef ROM_CANRetrySet +#define MAP_CANRetrySet \ + ROM_CANRetrySet +#else +#define MAP_CANRetrySet \ + CANRetrySet +#endif +#ifdef ROM_CANErrCntrGet +#define MAP_CANErrCntrGet \ + ROM_CANErrCntrGet +#else +#define MAP_CANErrCntrGet \ + CANErrCntrGet +#endif +#ifdef ROM_CANBitRateSet +#define MAP_CANBitRateSet \ + ROM_CANBitRateSet +#else +#define MAP_CANBitRateSet \ + CANBitRateSet +#endif + +//***************************************************************************** +// +// Macros for the Comparator API. +// +//***************************************************************************** +#ifdef ROM_ComparatorIntClear +#define MAP_ComparatorIntClear \ + ROM_ComparatorIntClear +#else +#define MAP_ComparatorIntClear \ + ComparatorIntClear +#endif +#ifdef ROM_ComparatorConfigure +#define MAP_ComparatorConfigure \ + ROM_ComparatorConfigure +#else +#define MAP_ComparatorConfigure \ + ComparatorConfigure +#endif +#ifdef ROM_ComparatorRefSet +#define MAP_ComparatorRefSet \ + ROM_ComparatorRefSet +#else +#define MAP_ComparatorRefSet \ + ComparatorRefSet +#endif +#ifdef ROM_ComparatorValueGet +#define MAP_ComparatorValueGet \ + ROM_ComparatorValueGet +#else +#define MAP_ComparatorValueGet \ + ComparatorValueGet +#endif +#ifdef ROM_ComparatorIntEnable +#define MAP_ComparatorIntEnable \ + ROM_ComparatorIntEnable +#else +#define MAP_ComparatorIntEnable \ + ComparatorIntEnable +#endif +#ifdef ROM_ComparatorIntDisable +#define MAP_ComparatorIntDisable \ + ROM_ComparatorIntDisable +#else +#define MAP_ComparatorIntDisable \ + ComparatorIntDisable +#endif +#ifdef ROM_ComparatorIntStatus +#define MAP_ComparatorIntStatus \ + ROM_ComparatorIntStatus +#else +#define MAP_ComparatorIntStatus \ + ComparatorIntStatus +#endif + +//***************************************************************************** +// +// Macros for the EEPROM API. +// +//***************************************************************************** +#ifdef ROM_EEPROMRead +#define MAP_EEPROMRead \ + ROM_EEPROMRead +#else +#define MAP_EEPROMRead \ + EEPROMRead +#endif +#ifdef ROM_EEPROMBlockCountGet +#define MAP_EEPROMBlockCountGet \ + ROM_EEPROMBlockCountGet +#else +#define MAP_EEPROMBlockCountGet \ + EEPROMBlockCountGet +#endif +#ifdef ROM_EEPROMBlockHide +#define MAP_EEPROMBlockHide \ + ROM_EEPROMBlockHide +#else +#define MAP_EEPROMBlockHide \ + EEPROMBlockHide +#endif +#ifdef ROM_EEPROMBlockLock +#define MAP_EEPROMBlockLock \ + ROM_EEPROMBlockLock +#else +#define MAP_EEPROMBlockLock \ + EEPROMBlockLock +#endif +#ifdef ROM_EEPROMBlockPasswordSet +#define MAP_EEPROMBlockPasswordSet \ + ROM_EEPROMBlockPasswordSet +#else +#define MAP_EEPROMBlockPasswordSet \ + EEPROMBlockPasswordSet +#endif +#ifdef ROM_EEPROMBlockProtectGet +#define MAP_EEPROMBlockProtectGet \ + ROM_EEPROMBlockProtectGet +#else +#define MAP_EEPROMBlockProtectGet \ + EEPROMBlockProtectGet +#endif +#ifdef ROM_EEPROMBlockProtectSet +#define MAP_EEPROMBlockProtectSet \ + ROM_EEPROMBlockProtectSet +#else +#define MAP_EEPROMBlockProtectSet \ + EEPROMBlockProtectSet +#endif +#ifdef ROM_EEPROMBlockUnlock +#define MAP_EEPROMBlockUnlock \ + ROM_EEPROMBlockUnlock +#else +#define MAP_EEPROMBlockUnlock \ + EEPROMBlockUnlock +#endif +#ifdef ROM_EEPROMIntClear +#define MAP_EEPROMIntClear \ + ROM_EEPROMIntClear +#else +#define MAP_EEPROMIntClear \ + EEPROMIntClear +#endif +#ifdef ROM_EEPROMIntDisable +#define MAP_EEPROMIntDisable \ + ROM_EEPROMIntDisable +#else +#define MAP_EEPROMIntDisable \ + EEPROMIntDisable +#endif +#ifdef ROM_EEPROMIntEnable +#define MAP_EEPROMIntEnable \ + ROM_EEPROMIntEnable +#else +#define MAP_EEPROMIntEnable \ + EEPROMIntEnable +#endif +#ifdef ROM_EEPROMIntStatus +#define MAP_EEPROMIntStatus \ + ROM_EEPROMIntStatus +#else +#define MAP_EEPROMIntStatus \ + EEPROMIntStatus +#endif +#ifdef ROM_EEPROMMassErase +#define MAP_EEPROMMassErase \ + ROM_EEPROMMassErase +#else +#define MAP_EEPROMMassErase \ + EEPROMMassErase +#endif +#ifdef ROM_EEPROMProgram +#define MAP_EEPROMProgram \ + ROM_EEPROMProgram +#else +#define MAP_EEPROMProgram \ + EEPROMProgram +#endif +#ifdef ROM_EEPROMProgramNonBlocking +#define MAP_EEPROMProgramNonBlocking \ + ROM_EEPROMProgramNonBlocking +#else +#define MAP_EEPROMProgramNonBlocking \ + EEPROMProgramNonBlocking +#endif +#ifdef ROM_EEPROMSizeGet +#define MAP_EEPROMSizeGet \ + ROM_EEPROMSizeGet +#else +#define MAP_EEPROMSizeGet \ + EEPROMSizeGet +#endif +#ifdef ROM_EEPROMStatusGet +#define MAP_EEPROMStatusGet \ + ROM_EEPROMStatusGet +#else +#define MAP_EEPROMStatusGet \ + EEPROMStatusGet +#endif +#ifdef ROM_EEPROMInit +#define MAP_EEPROMInit \ + ROM_EEPROMInit +#else +#define MAP_EEPROMInit \ + EEPROMInit +#endif + +//***************************************************************************** +// +// Macros for the EPI API. +// +//***************************************************************************** +#ifdef ROM_EPIIntStatus +#define MAP_EPIIntStatus \ + ROM_EPIIntStatus +#else +#define MAP_EPIIntStatus \ + EPIIntStatus +#endif +#ifdef ROM_EPIModeSet +#define MAP_EPIModeSet \ + ROM_EPIModeSet +#else +#define MAP_EPIModeSet \ + EPIModeSet +#endif +#ifdef ROM_EPIDividerSet +#define MAP_EPIDividerSet \ + ROM_EPIDividerSet +#else +#define MAP_EPIDividerSet \ + EPIDividerSet +#endif +#ifdef ROM_EPIConfigSDRAMSet +#define MAP_EPIConfigSDRAMSet \ + ROM_EPIConfigSDRAMSet +#else +#define MAP_EPIConfigSDRAMSet \ + EPIConfigSDRAMSet +#endif +#ifdef ROM_EPIConfigGPModeSet +#define MAP_EPIConfigGPModeSet \ + ROM_EPIConfigGPModeSet +#else +#define MAP_EPIConfigGPModeSet \ + EPIConfigGPModeSet +#endif +#ifdef ROM_EPIConfigHB8Set +#define MAP_EPIConfigHB8Set \ + ROM_EPIConfigHB8Set +#else +#define MAP_EPIConfigHB8Set \ + EPIConfigHB8Set +#endif +#ifdef ROM_EPIConfigHB16Set +#define MAP_EPIConfigHB16Set \ + ROM_EPIConfigHB16Set +#else +#define MAP_EPIConfigHB16Set \ + EPIConfigHB16Set +#endif +#ifdef ROM_EPIAddressMapSet +#define MAP_EPIAddressMapSet \ + ROM_EPIAddressMapSet +#else +#define MAP_EPIAddressMapSet \ + EPIAddressMapSet +#endif +#ifdef ROM_EPINonBlockingReadConfigure +#define MAP_EPINonBlockingReadConfigure \ + ROM_EPINonBlockingReadConfigure +#else +#define MAP_EPINonBlockingReadConfigure \ + EPINonBlockingReadConfigure +#endif +#ifdef ROM_EPINonBlockingReadStart +#define MAP_EPINonBlockingReadStart \ + ROM_EPINonBlockingReadStart +#else +#define MAP_EPINonBlockingReadStart \ + EPINonBlockingReadStart +#endif +#ifdef ROM_EPINonBlockingReadStop +#define MAP_EPINonBlockingReadStop \ + ROM_EPINonBlockingReadStop +#else +#define MAP_EPINonBlockingReadStop \ + EPINonBlockingReadStop +#endif +#ifdef ROM_EPINonBlockingReadCount +#define MAP_EPINonBlockingReadCount \ + ROM_EPINonBlockingReadCount +#else +#define MAP_EPINonBlockingReadCount \ + EPINonBlockingReadCount +#endif +#ifdef ROM_EPINonBlockingReadAvail +#define MAP_EPINonBlockingReadAvail \ + ROM_EPINonBlockingReadAvail +#else +#define MAP_EPINonBlockingReadAvail \ + EPINonBlockingReadAvail +#endif +#ifdef ROM_EPINonBlockingReadGet32 +#define MAP_EPINonBlockingReadGet32 \ + ROM_EPINonBlockingReadGet32 +#else +#define MAP_EPINonBlockingReadGet32 \ + EPINonBlockingReadGet32 +#endif +#ifdef ROM_EPINonBlockingReadGet16 +#define MAP_EPINonBlockingReadGet16 \ + ROM_EPINonBlockingReadGet16 +#else +#define MAP_EPINonBlockingReadGet16 \ + EPINonBlockingReadGet16 +#endif +#ifdef ROM_EPINonBlockingReadGet8 +#define MAP_EPINonBlockingReadGet8 \ + ROM_EPINonBlockingReadGet8 +#else +#define MAP_EPINonBlockingReadGet8 \ + EPINonBlockingReadGet8 +#endif +#ifdef ROM_EPIFIFOConfig +#define MAP_EPIFIFOConfig \ + ROM_EPIFIFOConfig +#else +#define MAP_EPIFIFOConfig \ + EPIFIFOConfig +#endif +#ifdef ROM_EPIWriteFIFOCountGet +#define MAP_EPIWriteFIFOCountGet \ + ROM_EPIWriteFIFOCountGet +#else +#define MAP_EPIWriteFIFOCountGet \ + EPIWriteFIFOCountGet +#endif +#ifdef ROM_EPIIntEnable +#define MAP_EPIIntEnable \ + ROM_EPIIntEnable +#else +#define MAP_EPIIntEnable \ + EPIIntEnable +#endif +#ifdef ROM_EPIIntDisable +#define MAP_EPIIntDisable \ + ROM_EPIIntDisable +#else +#define MAP_EPIIntDisable \ + EPIIntDisable +#endif +#ifdef ROM_EPIIntErrorStatus +#define MAP_EPIIntErrorStatus \ + ROM_EPIIntErrorStatus +#else +#define MAP_EPIIntErrorStatus \ + EPIIntErrorStatus +#endif +#ifdef ROM_EPIIntErrorClear +#define MAP_EPIIntErrorClear \ + ROM_EPIIntErrorClear +#else +#define MAP_EPIIntErrorClear \ + EPIIntErrorClear +#endif + +//***************************************************************************** +// +// Macros for the Ethernet API. +// +//***************************************************************************** +#ifdef ROM_EthernetIntClear +#define MAP_EthernetIntClear \ + ROM_EthernetIntClear +#else +#define MAP_EthernetIntClear \ + EthernetIntClear +#endif +#ifdef ROM_EthernetInitExpClk +#define MAP_EthernetInitExpClk \ + ROM_EthernetInitExpClk +#else +#define MAP_EthernetInitExpClk \ + EthernetInitExpClk +#endif +#ifdef ROM_EthernetConfigSet +#define MAP_EthernetConfigSet \ + ROM_EthernetConfigSet +#else +#define MAP_EthernetConfigSet \ + EthernetConfigSet +#endif +#ifdef ROM_EthernetConfigGet +#define MAP_EthernetConfigGet \ + ROM_EthernetConfigGet +#else +#define MAP_EthernetConfigGet \ + EthernetConfigGet +#endif +#ifdef ROM_EthernetMACAddrSet +#define MAP_EthernetMACAddrSet \ + ROM_EthernetMACAddrSet +#else +#define MAP_EthernetMACAddrSet \ + EthernetMACAddrSet +#endif +#ifdef ROM_EthernetMACAddrGet +#define MAP_EthernetMACAddrGet \ + ROM_EthernetMACAddrGet +#else +#define MAP_EthernetMACAddrGet \ + EthernetMACAddrGet +#endif +#ifdef ROM_EthernetEnable +#define MAP_EthernetEnable \ + ROM_EthernetEnable +#else +#define MAP_EthernetEnable \ + EthernetEnable +#endif +#ifdef ROM_EthernetDisable +#define MAP_EthernetDisable \ + ROM_EthernetDisable +#else +#define MAP_EthernetDisable \ + EthernetDisable +#endif +#ifdef ROM_EthernetPacketAvail +#define MAP_EthernetPacketAvail \ + ROM_EthernetPacketAvail +#else +#define MAP_EthernetPacketAvail \ + EthernetPacketAvail +#endif +#ifdef ROM_EthernetSpaceAvail +#define MAP_EthernetSpaceAvail \ + ROM_EthernetSpaceAvail +#else +#define MAP_EthernetSpaceAvail \ + EthernetSpaceAvail +#endif +#ifdef ROM_EthernetPacketGetNonBlocking +#define MAP_EthernetPacketGetNonBlocking \ + ROM_EthernetPacketGetNonBlocking +#else +#define MAP_EthernetPacketGetNonBlocking \ + EthernetPacketGetNonBlocking +#endif +#ifdef ROM_EthernetPacketGet +#define MAP_EthernetPacketGet \ + ROM_EthernetPacketGet +#else +#define MAP_EthernetPacketGet \ + EthernetPacketGet +#endif +#ifdef ROM_EthernetPacketPutNonBlocking +#define MAP_EthernetPacketPutNonBlocking \ + ROM_EthernetPacketPutNonBlocking +#else +#define MAP_EthernetPacketPutNonBlocking \ + EthernetPacketPutNonBlocking +#endif +#ifdef ROM_EthernetPacketPut +#define MAP_EthernetPacketPut \ + ROM_EthernetPacketPut +#else +#define MAP_EthernetPacketPut \ + EthernetPacketPut +#endif +#ifdef ROM_EthernetIntEnable +#define MAP_EthernetIntEnable \ + ROM_EthernetIntEnable +#else +#define MAP_EthernetIntEnable \ + EthernetIntEnable +#endif +#ifdef ROM_EthernetIntDisable +#define MAP_EthernetIntDisable \ + ROM_EthernetIntDisable +#else +#define MAP_EthernetIntDisable \ + EthernetIntDisable +#endif +#ifdef ROM_EthernetIntStatus +#define MAP_EthernetIntStatus \ + ROM_EthernetIntStatus +#else +#define MAP_EthernetIntStatus \ + EthernetIntStatus +#endif +#ifdef ROM_EthernetPHYWrite +#define MAP_EthernetPHYWrite \ + ROM_EthernetPHYWrite +#else +#define MAP_EthernetPHYWrite \ + EthernetPHYWrite +#endif +#ifdef ROM_EthernetPHYRead +#define MAP_EthernetPHYRead \ + ROM_EthernetPHYRead +#else +#define MAP_EthernetPHYRead \ + EthernetPHYRead +#endif +#ifdef ROM_EthernetPHYAddrSet +#define MAP_EthernetPHYAddrSet \ + ROM_EthernetPHYAddrSet +#else +#define MAP_EthernetPHYAddrSet \ + EthernetPHYAddrSet +#endif +#ifdef ROM_EthernetPHYPowerOff +#define MAP_EthernetPHYPowerOff \ + ROM_EthernetPHYPowerOff +#else +#define MAP_EthernetPHYPowerOff \ + EthernetPHYPowerOff +#endif +#ifdef ROM_EthernetPHYPowerOn +#define MAP_EthernetPHYPowerOn \ + ROM_EthernetPHYPowerOn +#else +#define MAP_EthernetPHYPowerOn \ + EthernetPHYPowerOn +#endif + +//***************************************************************************** +// +// Macros for the Fan API. +// +//***************************************************************************** +#ifdef ROM_FanIntClear +#define MAP_FanIntClear \ + ROM_FanIntClear +#else +#define MAP_FanIntClear \ + FanIntClear +#endif +#ifdef ROM_FanChannelConfigAuto +#define MAP_FanChannelConfigAuto \ + ROM_FanChannelConfigAuto +#else +#define MAP_FanChannelConfigAuto \ + FanChannelConfigAuto +#endif +#ifdef ROM_FanChannelConfigManual +#define MAP_FanChannelConfigManual \ + ROM_FanChannelConfigManual +#else +#define MAP_FanChannelConfigManual \ + FanChannelConfigManual +#endif +#ifdef ROM_FanChannelDisable +#define MAP_FanChannelDisable \ + ROM_FanChannelDisable +#else +#define MAP_FanChannelDisable \ + FanChannelDisable +#endif +#ifdef ROM_FanChannelDutyGet +#define MAP_FanChannelDutyGet \ + ROM_FanChannelDutyGet +#else +#define MAP_FanChannelDutyGet \ + FanChannelDutyGet +#endif +#ifdef ROM_FanChannelDutySet +#define MAP_FanChannelDutySet \ + ROM_FanChannelDutySet +#else +#define MAP_FanChannelDutySet \ + FanChannelDutySet +#endif +#ifdef ROM_FanChannelEnable +#define MAP_FanChannelEnable \ + ROM_FanChannelEnable +#else +#define MAP_FanChannelEnable \ + FanChannelEnable +#endif +#ifdef ROM_FanChannelRPMGet +#define MAP_FanChannelRPMGet \ + ROM_FanChannelRPMGet +#else +#define MAP_FanChannelRPMGet \ + FanChannelRPMGet +#endif +#ifdef ROM_FanChannelRPMSet +#define MAP_FanChannelRPMSet \ + ROM_FanChannelRPMSet +#else +#define MAP_FanChannelRPMSet \ + FanChannelRPMSet +#endif +#ifdef ROM_FanChannelStatus +#define MAP_FanChannelStatus \ + ROM_FanChannelStatus +#else +#define MAP_FanChannelStatus \ + FanChannelStatus +#endif +#ifdef ROM_FanChannelsGet +#define MAP_FanChannelsGet \ + ROM_FanChannelsGet +#else +#define MAP_FanChannelsGet \ + FanChannelsGet +#endif +#ifdef ROM_FanIntDisable +#define MAP_FanIntDisable \ + ROM_FanIntDisable +#else +#define MAP_FanIntDisable \ + FanIntDisable +#endif +#ifdef ROM_FanIntEnable +#define MAP_FanIntEnable \ + ROM_FanIntEnable +#else +#define MAP_FanIntEnable \ + FanIntEnable +#endif +#ifdef ROM_FanIntStatus +#define MAP_FanIntStatus \ + ROM_FanIntStatus +#else +#define MAP_FanIntStatus \ + FanIntStatus +#endif + +//***************************************************************************** +// +// Macros for the Flash API. +// +//***************************************************************************** +#ifdef ROM_FlashProgram +#define MAP_FlashProgram \ + ROM_FlashProgram +#else +#define MAP_FlashProgram \ + FlashProgram +#endif +#ifdef ROM_FlashUsecGet +#define MAP_FlashUsecGet \ + ROM_FlashUsecGet +#else +#define MAP_FlashUsecGet \ + FlashUsecGet +#endif +#ifdef ROM_FlashUsecSet +#define MAP_FlashUsecSet \ + ROM_FlashUsecSet +#else +#define MAP_FlashUsecSet \ + FlashUsecSet +#endif +#ifdef ROM_FlashErase +#define MAP_FlashErase \ + ROM_FlashErase +#else +#define MAP_FlashErase \ + FlashErase +#endif +#ifdef ROM_FlashProtectGet +#define MAP_FlashProtectGet \ + ROM_FlashProtectGet +#else +#define MAP_FlashProtectGet \ + FlashProtectGet +#endif +#ifdef ROM_FlashProtectSet +#define MAP_FlashProtectSet \ + ROM_FlashProtectSet +#else +#define MAP_FlashProtectSet \ + FlashProtectSet +#endif +#ifdef ROM_FlashProtectSave +#define MAP_FlashProtectSave \ + ROM_FlashProtectSave +#else +#define MAP_FlashProtectSave \ + FlashProtectSave +#endif +#ifdef ROM_FlashUserGet +#define MAP_FlashUserGet \ + ROM_FlashUserGet +#else +#define MAP_FlashUserGet \ + FlashUserGet +#endif +#ifdef ROM_FlashUserSet +#define MAP_FlashUserSet \ + ROM_FlashUserSet +#else +#define MAP_FlashUserSet \ + FlashUserSet +#endif +#ifdef ROM_FlashUserSave +#define MAP_FlashUserSave \ + ROM_FlashUserSave +#else +#define MAP_FlashUserSave \ + FlashUserSave +#endif +#ifdef ROM_FlashIntEnable +#define MAP_FlashIntEnable \ + ROM_FlashIntEnable +#else +#define MAP_FlashIntEnable \ + FlashIntEnable +#endif +#ifdef ROM_FlashIntDisable +#define MAP_FlashIntDisable \ + ROM_FlashIntDisable +#else +#define MAP_FlashIntDisable \ + FlashIntDisable +#endif +#ifdef ROM_FlashIntStatus +#define MAP_FlashIntStatus \ + ROM_FlashIntStatus +#else +#define MAP_FlashIntStatus \ + FlashIntStatus +#endif +#ifdef ROM_FlashIntClear +#define MAP_FlashIntClear \ + ROM_FlashIntClear +#else +#define MAP_FlashIntClear \ + FlashIntClear +#endif + +//***************************************************************************** +// +// Macros for the FPU API. +// +//***************************************************************************** +#ifdef ROM_FPUEnable +#define MAP_FPUEnable \ + ROM_FPUEnable +#else +#define MAP_FPUEnable \ + FPUEnable +#endif +#ifdef ROM_FPUDisable +#define MAP_FPUDisable \ + ROM_FPUDisable +#else +#define MAP_FPUDisable \ + FPUDisable +#endif +#ifdef ROM_FPUFlushToZeroModeSet +#define MAP_FPUFlushToZeroModeSet \ + ROM_FPUFlushToZeroModeSet +#else +#define MAP_FPUFlushToZeroModeSet \ + FPUFlushToZeroModeSet +#endif +#ifdef ROM_FPUHalfPrecisionModeSet +#define MAP_FPUHalfPrecisionModeSet \ + ROM_FPUHalfPrecisionModeSet +#else +#define MAP_FPUHalfPrecisionModeSet \ + FPUHalfPrecisionModeSet +#endif +#ifdef ROM_FPULazyStackingEnable +#define MAP_FPULazyStackingEnable \ + ROM_FPULazyStackingEnable +#else +#define MAP_FPULazyStackingEnable \ + FPULazyStackingEnable +#endif +#ifdef ROM_FPUNaNModeSet +#define MAP_FPUNaNModeSet \ + ROM_FPUNaNModeSet +#else +#define MAP_FPUNaNModeSet \ + FPUNaNModeSet +#endif +#ifdef ROM_FPURoundingModeSet +#define MAP_FPURoundingModeSet \ + ROM_FPURoundingModeSet +#else +#define MAP_FPURoundingModeSet \ + FPURoundingModeSet +#endif +#ifdef ROM_FPUStackingDisable +#define MAP_FPUStackingDisable \ + ROM_FPUStackingDisable +#else +#define MAP_FPUStackingDisable \ + FPUStackingDisable +#endif +#ifdef ROM_FPUStackingEnable +#define MAP_FPUStackingEnable \ + ROM_FPUStackingEnable +#else +#define MAP_FPUStackingEnable \ + FPUStackingEnable +#endif + +//***************************************************************************** +// +// Macros for the GPIO API. +// +//***************************************************************************** +#ifdef ROM_GPIOPinWrite +#define MAP_GPIOPinWrite \ + ROM_GPIOPinWrite +#else +#define MAP_GPIOPinWrite \ + GPIOPinWrite +#endif +#ifdef ROM_GPIODirModeSet +#define MAP_GPIODirModeSet \ + ROM_GPIODirModeSet +#else +#define MAP_GPIODirModeSet \ + GPIODirModeSet +#endif +#ifdef ROM_GPIODirModeGet +#define MAP_GPIODirModeGet \ + ROM_GPIODirModeGet +#else +#define MAP_GPIODirModeGet \ + GPIODirModeGet +#endif +#ifdef ROM_GPIOIntTypeSet +#define MAP_GPIOIntTypeSet \ + ROM_GPIOIntTypeSet +#else +#define MAP_GPIOIntTypeSet \ + GPIOIntTypeSet +#endif +#ifdef ROM_GPIOIntTypeGet +#define MAP_GPIOIntTypeGet \ + ROM_GPIOIntTypeGet +#else +#define MAP_GPIOIntTypeGet \ + GPIOIntTypeGet +#endif +#ifdef ROM_GPIOPadConfigSet +#define MAP_GPIOPadConfigSet \ + ROM_GPIOPadConfigSet +#else +#define MAP_GPIOPadConfigSet \ + GPIOPadConfigSet +#endif +#ifdef ROM_GPIOPadConfigGet +#define MAP_GPIOPadConfigGet \ + ROM_GPIOPadConfigGet +#else +#define MAP_GPIOPadConfigGet \ + GPIOPadConfigGet +#endif +#ifdef ROM_GPIOPinIntEnable +#define MAP_GPIOPinIntEnable \ + ROM_GPIOPinIntEnable +#else +#define MAP_GPIOPinIntEnable \ + GPIOPinIntEnable +#endif +#ifdef ROM_GPIOPinIntDisable +#define MAP_GPIOPinIntDisable \ + ROM_GPIOPinIntDisable +#else +#define MAP_GPIOPinIntDisable \ + GPIOPinIntDisable +#endif +#ifdef ROM_GPIOPinIntStatus +#define MAP_GPIOPinIntStatus \ + ROM_GPIOPinIntStatus +#else +#define MAP_GPIOPinIntStatus \ + GPIOPinIntStatus +#endif +#ifdef ROM_GPIOPinIntClear +#define MAP_GPIOPinIntClear \ + ROM_GPIOPinIntClear +#else +#define MAP_GPIOPinIntClear \ + GPIOPinIntClear +#endif +#ifdef ROM_GPIOPinRead +#define MAP_GPIOPinRead \ + ROM_GPIOPinRead +#else +#define MAP_GPIOPinRead \ + GPIOPinRead +#endif +#ifdef ROM_GPIOPinTypeCAN +#define MAP_GPIOPinTypeCAN \ + ROM_GPIOPinTypeCAN +#else +#define MAP_GPIOPinTypeCAN \ + GPIOPinTypeCAN +#endif +#ifdef ROM_GPIOPinTypeComparator +#define MAP_GPIOPinTypeComparator \ + ROM_GPIOPinTypeComparator +#else +#define MAP_GPIOPinTypeComparator \ + GPIOPinTypeComparator +#endif +#ifdef ROM_GPIOPinTypeGPIOInput +#define MAP_GPIOPinTypeGPIOInput \ + ROM_GPIOPinTypeGPIOInput +#else +#define MAP_GPIOPinTypeGPIOInput \ + GPIOPinTypeGPIOInput +#endif +#ifdef ROM_GPIOPinTypeGPIOOutput +#define MAP_GPIOPinTypeGPIOOutput \ + ROM_GPIOPinTypeGPIOOutput +#else +#define MAP_GPIOPinTypeGPIOOutput \ + GPIOPinTypeGPIOOutput +#endif +#ifdef ROM_GPIOPinTypeI2C +#define MAP_GPIOPinTypeI2C \ + ROM_GPIOPinTypeI2C +#else +#define MAP_GPIOPinTypeI2C \ + GPIOPinTypeI2C +#endif +#ifdef ROM_GPIOPinTypePWM +#define MAP_GPIOPinTypePWM \ + ROM_GPIOPinTypePWM +#else +#define MAP_GPIOPinTypePWM \ + GPIOPinTypePWM +#endif +#ifdef ROM_GPIOPinTypeQEI +#define MAP_GPIOPinTypeQEI \ + ROM_GPIOPinTypeQEI +#else +#define MAP_GPIOPinTypeQEI \ + GPIOPinTypeQEI +#endif +#ifdef ROM_GPIOPinTypeSSI +#define MAP_GPIOPinTypeSSI \ + ROM_GPIOPinTypeSSI +#else +#define MAP_GPIOPinTypeSSI \ + GPIOPinTypeSSI +#endif +#ifdef ROM_GPIOPinTypeTimer +#define MAP_GPIOPinTypeTimer \ + ROM_GPIOPinTypeTimer +#else +#define MAP_GPIOPinTypeTimer \ + GPIOPinTypeTimer +#endif +#ifdef ROM_GPIOPinTypeUART +#define MAP_GPIOPinTypeUART \ + ROM_GPIOPinTypeUART +#else +#define MAP_GPIOPinTypeUART \ + GPIOPinTypeUART +#endif +#ifdef ROM_GPIOPinTypeGPIOOutputOD +#define MAP_GPIOPinTypeGPIOOutputOD \ + ROM_GPIOPinTypeGPIOOutputOD +#else +#define MAP_GPIOPinTypeGPIOOutputOD \ + GPIOPinTypeGPIOOutputOD +#endif +#ifdef ROM_GPIOPinTypeADC +#define MAP_GPIOPinTypeADC \ + ROM_GPIOPinTypeADC +#else +#define MAP_GPIOPinTypeADC \ + GPIOPinTypeADC +#endif +#ifdef ROM_GPIOPinTypeUSBDigital +#define MAP_GPIOPinTypeUSBDigital \ + ROM_GPIOPinTypeUSBDigital +#else +#define MAP_GPIOPinTypeUSBDigital \ + GPIOPinTypeUSBDigital +#endif +#ifdef ROM_GPIOPinTypeI2S +#define MAP_GPIOPinTypeI2S \ + ROM_GPIOPinTypeI2S +#else +#define MAP_GPIOPinTypeI2S \ + GPIOPinTypeI2S +#endif +#ifdef ROM_GPIOPinConfigure +#define MAP_GPIOPinConfigure \ + ROM_GPIOPinConfigure +#else +#define MAP_GPIOPinConfigure \ + GPIOPinConfigure +#endif +#ifdef ROM_GPIOPinTypeEthernetLED +#define MAP_GPIOPinTypeEthernetLED \ + ROM_GPIOPinTypeEthernetLED +#else +#define MAP_GPIOPinTypeEthernetLED \ + GPIOPinTypeEthernetLED +#endif +#ifdef ROM_GPIOPinTypeUSBAnalog +#define MAP_GPIOPinTypeUSBAnalog \ + ROM_GPIOPinTypeUSBAnalog +#else +#define MAP_GPIOPinTypeUSBAnalog \ + GPIOPinTypeUSBAnalog +#endif +#ifdef ROM_GPIOPinTypeEPI +#define MAP_GPIOPinTypeEPI \ + ROM_GPIOPinTypeEPI +#else +#define MAP_GPIOPinTypeEPI \ + GPIOPinTypeEPI +#endif +#ifdef ROM_GPIOPinTypeEthernetMII +#define MAP_GPIOPinTypeEthernetMII \ + ROM_GPIOPinTypeEthernetMII +#else +#define MAP_GPIOPinTypeEthernetMII \ + GPIOPinTypeEthernetMII +#endif +#ifdef ROM_GPIODMATriggerEnable +#define MAP_GPIODMATriggerEnable \ + ROM_GPIODMATriggerEnable +#else +#define MAP_GPIODMATriggerEnable \ + GPIODMATriggerEnable +#endif +#ifdef ROM_GPIODMATriggerDisable +#define MAP_GPIODMATriggerDisable \ + ROM_GPIODMATriggerDisable +#else +#define MAP_GPIODMATriggerDisable \ + GPIODMATriggerDisable +#endif +#ifdef ROM_GPIOADCTriggerEnable +#define MAP_GPIOADCTriggerEnable \ + ROM_GPIOADCTriggerEnable +#else +#define MAP_GPIOADCTriggerEnable \ + GPIOADCTriggerEnable +#endif +#ifdef ROM_GPIOADCTriggerDisable +#define MAP_GPIOADCTriggerDisable \ + ROM_GPIOADCTriggerDisable +#else +#define MAP_GPIOADCTriggerDisable \ + GPIOADCTriggerDisable +#endif +#ifdef ROM_GPIOPinTypeFan +#define MAP_GPIOPinTypeFan \ + ROM_GPIOPinTypeFan +#else +#define MAP_GPIOPinTypeFan \ + GPIOPinTypeFan +#endif +#ifdef ROM_GPIOPinTypeLPC +#define MAP_GPIOPinTypeLPC \ + ROM_GPIOPinTypeLPC +#else +#define MAP_GPIOPinTypeLPC \ + GPIOPinTypeLPC +#endif +#ifdef ROM_GPIOPinTypePECIRx +#define MAP_GPIOPinTypePECIRx \ + ROM_GPIOPinTypePECIRx +#else +#define MAP_GPIOPinTypePECIRx \ + GPIOPinTypePECIRx +#endif +#ifdef ROM_GPIOPinTypePECITx +#define MAP_GPIOPinTypePECITx \ + ROM_GPIOPinTypePECITx +#else +#define MAP_GPIOPinTypePECITx \ + GPIOPinTypePECITx +#endif +#ifdef ROM_GPIOPinTypeI2CSCL +#define MAP_GPIOPinTypeI2CSCL \ + ROM_GPIOPinTypeI2CSCL +#else +#define MAP_GPIOPinTypeI2CSCL \ + GPIOPinTypeI2CSCL +#endif + +//***************************************************************************** +// +// Macros for the Hibernate API. +// +//***************************************************************************** +#ifdef ROM_HibernateIntClear +#define MAP_HibernateIntClear \ + ROM_HibernateIntClear +#else +#define MAP_HibernateIntClear \ + HibernateIntClear +#endif +#ifdef ROM_HibernateEnableExpClk +#define MAP_HibernateEnableExpClk \ + ROM_HibernateEnableExpClk +#else +#define MAP_HibernateEnableExpClk \ + HibernateEnableExpClk +#endif +#ifdef ROM_HibernateDisable +#define MAP_HibernateDisable \ + ROM_HibernateDisable +#else +#define MAP_HibernateDisable \ + HibernateDisable +#endif +#ifdef ROM_HibernateClockSelect +#define MAP_HibernateClockSelect \ + ROM_HibernateClockSelect +#else +#define MAP_HibernateClockSelect \ + HibernateClockSelect +#endif +#ifdef ROM_HibernateRTCEnable +#define MAP_HibernateRTCEnable \ + ROM_HibernateRTCEnable +#else +#define MAP_HibernateRTCEnable \ + HibernateRTCEnable +#endif +#ifdef ROM_HibernateRTCDisable +#define MAP_HibernateRTCDisable \ + ROM_HibernateRTCDisable +#else +#define MAP_HibernateRTCDisable \ + HibernateRTCDisable +#endif +#ifdef ROM_HibernateWakeSet +#define MAP_HibernateWakeSet \ + ROM_HibernateWakeSet +#else +#define MAP_HibernateWakeSet \ + HibernateWakeSet +#endif +#ifdef ROM_HibernateWakeGet +#define MAP_HibernateWakeGet \ + ROM_HibernateWakeGet +#else +#define MAP_HibernateWakeGet \ + HibernateWakeGet +#endif +#ifdef ROM_HibernateLowBatSet +#define MAP_HibernateLowBatSet \ + ROM_HibernateLowBatSet +#else +#define MAP_HibernateLowBatSet \ + HibernateLowBatSet +#endif +#ifdef ROM_HibernateLowBatGet +#define MAP_HibernateLowBatGet \ + ROM_HibernateLowBatGet +#else +#define MAP_HibernateLowBatGet \ + HibernateLowBatGet +#endif +#ifdef ROM_HibernateRTCSet +#define MAP_HibernateRTCSet \ + ROM_HibernateRTCSet +#else +#define MAP_HibernateRTCSet \ + HibernateRTCSet +#endif +#ifdef ROM_HibernateRTCGet +#define MAP_HibernateRTCGet \ + ROM_HibernateRTCGet +#else +#define MAP_HibernateRTCGet \ + HibernateRTCGet +#endif +#ifdef ROM_HibernateRTCMatch0Set +#define MAP_HibernateRTCMatch0Set \ + ROM_HibernateRTCMatch0Set +#else +#define MAP_HibernateRTCMatch0Set \ + HibernateRTCMatch0Set +#endif +#ifdef ROM_HibernateRTCMatch0Get +#define MAP_HibernateRTCMatch0Get \ + ROM_HibernateRTCMatch0Get +#else +#define MAP_HibernateRTCMatch0Get \ + HibernateRTCMatch0Get +#endif +#ifdef ROM_HibernateRTCMatch1Set +#define MAP_HibernateRTCMatch1Set \ + ROM_HibernateRTCMatch1Set +#else +#define MAP_HibernateRTCMatch1Set \ + HibernateRTCMatch1Set +#endif +#ifdef ROM_HibernateRTCMatch1Get +#define MAP_HibernateRTCMatch1Get \ + ROM_HibernateRTCMatch1Get +#else +#define MAP_HibernateRTCMatch1Get \ + HibernateRTCMatch1Get +#endif +#ifdef ROM_HibernateRTCTrimSet +#define MAP_HibernateRTCTrimSet \ + ROM_HibernateRTCTrimSet +#else +#define MAP_HibernateRTCTrimSet \ + HibernateRTCTrimSet +#endif +#ifdef ROM_HibernateRTCTrimGet +#define MAP_HibernateRTCTrimGet \ + ROM_HibernateRTCTrimGet +#else +#define MAP_HibernateRTCTrimGet \ + HibernateRTCTrimGet +#endif +#ifdef ROM_HibernateDataSet +#define MAP_HibernateDataSet \ + ROM_HibernateDataSet +#else +#define MAP_HibernateDataSet \ + HibernateDataSet +#endif +#ifdef ROM_HibernateDataGet +#define MAP_HibernateDataGet \ + ROM_HibernateDataGet +#else +#define MAP_HibernateDataGet \ + HibernateDataGet +#endif +#ifdef ROM_HibernateRequest +#define MAP_HibernateRequest \ + ROM_HibernateRequest +#else +#define MAP_HibernateRequest \ + HibernateRequest +#endif +#ifdef ROM_HibernateIntEnable +#define MAP_HibernateIntEnable \ + ROM_HibernateIntEnable +#else +#define MAP_HibernateIntEnable \ + HibernateIntEnable +#endif +#ifdef ROM_HibernateIntDisable +#define MAP_HibernateIntDisable \ + ROM_HibernateIntDisable +#else +#define MAP_HibernateIntDisable \ + HibernateIntDisable +#endif +#ifdef ROM_HibernateIntStatus +#define MAP_HibernateIntStatus \ + ROM_HibernateIntStatus +#else +#define MAP_HibernateIntStatus \ + HibernateIntStatus +#endif +#ifdef ROM_HibernateIsActive +#define MAP_HibernateIsActive \ + ROM_HibernateIsActive +#else +#define MAP_HibernateIsActive \ + HibernateIsActive +#endif +#ifdef ROM_HibernateRTCSSMatch0Set +#define MAP_HibernateRTCSSMatch0Set \ + ROM_HibernateRTCSSMatch0Set +#else +#define MAP_HibernateRTCSSMatch0Set \ + HibernateRTCSSMatch0Set +#endif +#ifdef ROM_HibernateRTCSSMatch0Get +#define MAP_HibernateRTCSSMatch0Get \ + ROM_HibernateRTCSSMatch0Get +#else +#define MAP_HibernateRTCSSMatch0Get \ + HibernateRTCSSMatch0Get +#endif +#ifdef ROM_HibernateRTCSSGet +#define MAP_HibernateRTCSSGet \ + ROM_HibernateRTCSSGet +#else +#define MAP_HibernateRTCSSGet \ + HibernateRTCSSGet +#endif +#ifdef ROM_HibernateClockConfig +#define MAP_HibernateClockConfig \ + ROM_HibernateClockConfig +#else +#define MAP_HibernateClockConfig \ + HibernateClockConfig +#endif +#ifdef ROM_HibernateBatCheckStart +#define MAP_HibernateBatCheckStart \ + ROM_HibernateBatCheckStart +#else +#define MAP_HibernateBatCheckStart \ + HibernateBatCheckStart +#endif +#ifdef ROM_HibernateBatCheckDone +#define MAP_HibernateBatCheckDone \ + ROM_HibernateBatCheckDone +#else +#define MAP_HibernateBatCheckDone \ + HibernateBatCheckDone +#endif + +//***************************************************************************** +// +// Macros for the I2C API. +// +//***************************************************************************** +#ifdef ROM_I2CMasterDataPut +#define MAP_I2CMasterDataPut \ + ROM_I2CMasterDataPut +#else +#define MAP_I2CMasterDataPut \ + I2CMasterDataPut +#endif +#ifdef ROM_I2CMasterInitExpClk +#define MAP_I2CMasterInitExpClk \ + ROM_I2CMasterInitExpClk +#else +#define MAP_I2CMasterInitExpClk \ + I2CMasterInitExpClk +#endif +#ifdef ROM_I2CSlaveInit +#define MAP_I2CSlaveInit \ + ROM_I2CSlaveInit +#else +#define MAP_I2CSlaveInit \ + I2CSlaveInit +#endif +#ifdef ROM_I2CMasterEnable +#define MAP_I2CMasterEnable \ + ROM_I2CMasterEnable +#else +#define MAP_I2CMasterEnable \ + I2CMasterEnable +#endif +#ifdef ROM_I2CSlaveEnable +#define MAP_I2CSlaveEnable \ + ROM_I2CSlaveEnable +#else +#define MAP_I2CSlaveEnable \ + I2CSlaveEnable +#endif +#ifdef ROM_I2CMasterDisable +#define MAP_I2CMasterDisable \ + ROM_I2CMasterDisable +#else +#define MAP_I2CMasterDisable \ + I2CMasterDisable +#endif +#ifdef ROM_I2CSlaveDisable +#define MAP_I2CSlaveDisable \ + ROM_I2CSlaveDisable +#else +#define MAP_I2CSlaveDisable \ + I2CSlaveDisable +#endif +#ifdef ROM_I2CMasterIntEnable +#define MAP_I2CMasterIntEnable \ + ROM_I2CMasterIntEnable +#else +#define MAP_I2CMasterIntEnable \ + I2CMasterIntEnable +#endif +#ifdef ROM_I2CSlaveIntEnable +#define MAP_I2CSlaveIntEnable \ + ROM_I2CSlaveIntEnable +#else +#define MAP_I2CSlaveIntEnable \ + I2CSlaveIntEnable +#endif +#ifdef ROM_I2CMasterIntDisable +#define MAP_I2CMasterIntDisable \ + ROM_I2CMasterIntDisable +#else +#define MAP_I2CMasterIntDisable \ + I2CMasterIntDisable +#endif +#ifdef ROM_I2CSlaveIntDisable +#define MAP_I2CSlaveIntDisable \ + ROM_I2CSlaveIntDisable +#else +#define MAP_I2CSlaveIntDisable \ + I2CSlaveIntDisable +#endif +#ifdef ROM_I2CMasterIntStatus +#define MAP_I2CMasterIntStatus \ + ROM_I2CMasterIntStatus +#else +#define MAP_I2CMasterIntStatus \ + I2CMasterIntStatus +#endif +#ifdef ROM_I2CSlaveIntStatus +#define MAP_I2CSlaveIntStatus \ + ROM_I2CSlaveIntStatus +#else +#define MAP_I2CSlaveIntStatus \ + I2CSlaveIntStatus +#endif +#ifdef ROM_I2CMasterIntClear +#define MAP_I2CMasterIntClear \ + ROM_I2CMasterIntClear +#else +#define MAP_I2CMasterIntClear \ + I2CMasterIntClear +#endif +#ifdef ROM_I2CSlaveIntClear +#define MAP_I2CSlaveIntClear \ + ROM_I2CSlaveIntClear +#else +#define MAP_I2CSlaveIntClear \ + I2CSlaveIntClear +#endif +#ifdef ROM_I2CMasterSlaveAddrSet +#define MAP_I2CMasterSlaveAddrSet \ + ROM_I2CMasterSlaveAddrSet +#else +#define MAP_I2CMasterSlaveAddrSet \ + I2CMasterSlaveAddrSet +#endif +#ifdef ROM_I2CMasterBusy +#define MAP_I2CMasterBusy \ + ROM_I2CMasterBusy +#else +#define MAP_I2CMasterBusy \ + I2CMasterBusy +#endif +#ifdef ROM_I2CMasterBusBusy +#define MAP_I2CMasterBusBusy \ + ROM_I2CMasterBusBusy +#else +#define MAP_I2CMasterBusBusy \ + I2CMasterBusBusy +#endif +#ifdef ROM_I2CMasterControl +#define MAP_I2CMasterControl \ + ROM_I2CMasterControl +#else +#define MAP_I2CMasterControl \ + I2CMasterControl +#endif +#ifdef ROM_I2CMasterErr +#define MAP_I2CMasterErr \ + ROM_I2CMasterErr +#else +#define MAP_I2CMasterErr \ + I2CMasterErr +#endif +#ifdef ROM_I2CMasterDataGet +#define MAP_I2CMasterDataGet \ + ROM_I2CMasterDataGet +#else +#define MAP_I2CMasterDataGet \ + I2CMasterDataGet +#endif +#ifdef ROM_I2CSlaveStatus +#define MAP_I2CSlaveStatus \ + ROM_I2CSlaveStatus +#else +#define MAP_I2CSlaveStatus \ + I2CSlaveStatus +#endif +#ifdef ROM_I2CSlaveDataPut +#define MAP_I2CSlaveDataPut \ + ROM_I2CSlaveDataPut +#else +#define MAP_I2CSlaveDataPut \ + I2CSlaveDataPut +#endif +#ifdef ROM_I2CSlaveDataGet +#define MAP_I2CSlaveDataGet \ + ROM_I2CSlaveDataGet +#else +#define MAP_I2CSlaveDataGet \ + I2CSlaveDataGet +#endif +#ifdef ROM_I2CSlaveIntEnableEx +#define MAP_I2CSlaveIntEnableEx \ + ROM_I2CSlaveIntEnableEx +#else +#define MAP_I2CSlaveIntEnableEx \ + I2CSlaveIntEnableEx +#endif +#ifdef ROM_I2CSlaveIntDisableEx +#define MAP_I2CSlaveIntDisableEx \ + ROM_I2CSlaveIntDisableEx +#else +#define MAP_I2CSlaveIntDisableEx \ + I2CSlaveIntDisableEx +#endif +#ifdef ROM_I2CSlaveIntStatusEx +#define MAP_I2CSlaveIntStatusEx \ + ROM_I2CSlaveIntStatusEx +#else +#define MAP_I2CSlaveIntStatusEx \ + I2CSlaveIntStatusEx +#endif +#ifdef ROM_I2CSlaveIntClearEx +#define MAP_I2CSlaveIntClearEx \ + ROM_I2CSlaveIntClearEx +#else +#define MAP_I2CSlaveIntClearEx \ + I2CSlaveIntClearEx +#endif +#ifdef ROM_I2CMasterIntEnableEx +#define MAP_I2CMasterIntEnableEx \ + ROM_I2CMasterIntEnableEx +#else +#define MAP_I2CMasterIntEnableEx \ + I2CMasterIntEnableEx +#endif +#ifdef ROM_I2CMasterIntDisableEx +#define MAP_I2CMasterIntDisableEx \ + ROM_I2CMasterIntDisableEx +#else +#define MAP_I2CMasterIntDisableEx \ + I2CMasterIntDisableEx +#endif +#ifdef ROM_I2CMasterIntStatusEx +#define MAP_I2CMasterIntStatusEx \ + ROM_I2CMasterIntStatusEx +#else +#define MAP_I2CMasterIntStatusEx \ + I2CMasterIntStatusEx +#endif +#ifdef ROM_I2CMasterIntClearEx +#define MAP_I2CMasterIntClearEx \ + ROM_I2CMasterIntClearEx +#else +#define MAP_I2CMasterIntClearEx \ + I2CMasterIntClearEx +#endif +#ifdef ROM_I2CMasterTimeoutSet +#define MAP_I2CMasterTimeoutSet \ + ROM_I2CMasterTimeoutSet +#else +#define MAP_I2CMasterTimeoutSet \ + I2CMasterTimeoutSet +#endif +#ifdef ROM_I2CSlaveACKOverride +#define MAP_I2CSlaveACKOverride \ + ROM_I2CSlaveACKOverride +#else +#define MAP_I2CSlaveACKOverride \ + I2CSlaveACKOverride +#endif +#ifdef ROM_I2CSlaveACKValueSet +#define MAP_I2CSlaveACKValueSet \ + ROM_I2CSlaveACKValueSet +#else +#define MAP_I2CSlaveACKValueSet \ + I2CSlaveACKValueSet +#endif +#ifdef ROM_I2CSlaveAddressSet +#define MAP_I2CSlaveAddressSet \ + ROM_I2CSlaveAddressSet +#else +#define MAP_I2CSlaveAddressSet \ + I2CSlaveAddressSet +#endif +#ifdef ROM_I2CMasterLineStateGet +#define MAP_I2CMasterLineStateGet \ + ROM_I2CMasterLineStateGet +#else +#define MAP_I2CMasterLineStateGet \ + I2CMasterLineStateGet +#endif + +//***************************************************************************** +// +// Macros for the I2S API. +// +//***************************************************************************** +#ifdef ROM_I2SIntStatus +#define MAP_I2SIntStatus \ + ROM_I2SIntStatus +#else +#define MAP_I2SIntStatus \ + I2SIntStatus +#endif +#ifdef ROM_I2STxEnable +#define MAP_I2STxEnable \ + ROM_I2STxEnable +#else +#define MAP_I2STxEnable \ + I2STxEnable +#endif +#ifdef ROM_I2STxDisable +#define MAP_I2STxDisable \ + ROM_I2STxDisable +#else +#define MAP_I2STxDisable \ + I2STxDisable +#endif +#ifdef ROM_I2STxDataPut +#define MAP_I2STxDataPut \ + ROM_I2STxDataPut +#else +#define MAP_I2STxDataPut \ + I2STxDataPut +#endif +#ifdef ROM_I2STxDataPutNonBlocking +#define MAP_I2STxDataPutNonBlocking \ + ROM_I2STxDataPutNonBlocking +#else +#define MAP_I2STxDataPutNonBlocking \ + I2STxDataPutNonBlocking +#endif +#ifdef ROM_I2STxConfigSet +#define MAP_I2STxConfigSet \ + ROM_I2STxConfigSet +#else +#define MAP_I2STxConfigSet \ + I2STxConfigSet +#endif +#ifdef ROM_I2STxFIFOLimitSet +#define MAP_I2STxFIFOLimitSet \ + ROM_I2STxFIFOLimitSet +#else +#define MAP_I2STxFIFOLimitSet \ + I2STxFIFOLimitSet +#endif +#ifdef ROM_I2STxFIFOLimitGet +#define MAP_I2STxFIFOLimitGet \ + ROM_I2STxFIFOLimitGet +#else +#define MAP_I2STxFIFOLimitGet \ + I2STxFIFOLimitGet +#endif +#ifdef ROM_I2STxFIFOLevelGet +#define MAP_I2STxFIFOLevelGet \ + ROM_I2STxFIFOLevelGet +#else +#define MAP_I2STxFIFOLevelGet \ + I2STxFIFOLevelGet +#endif +#ifdef ROM_I2SRxEnable +#define MAP_I2SRxEnable \ + ROM_I2SRxEnable +#else +#define MAP_I2SRxEnable \ + I2SRxEnable +#endif +#ifdef ROM_I2SRxDisable +#define MAP_I2SRxDisable \ + ROM_I2SRxDisable +#else +#define MAP_I2SRxDisable \ + I2SRxDisable +#endif +#ifdef ROM_I2SRxDataGet +#define MAP_I2SRxDataGet \ + ROM_I2SRxDataGet +#else +#define MAP_I2SRxDataGet \ + I2SRxDataGet +#endif +#ifdef ROM_I2SRxDataGetNonBlocking +#define MAP_I2SRxDataGetNonBlocking \ + ROM_I2SRxDataGetNonBlocking +#else +#define MAP_I2SRxDataGetNonBlocking \ + I2SRxDataGetNonBlocking +#endif +#ifdef ROM_I2SRxConfigSet +#define MAP_I2SRxConfigSet \ + ROM_I2SRxConfigSet +#else +#define MAP_I2SRxConfigSet \ + I2SRxConfigSet +#endif +#ifdef ROM_I2SRxFIFOLimitSet +#define MAP_I2SRxFIFOLimitSet \ + ROM_I2SRxFIFOLimitSet +#else +#define MAP_I2SRxFIFOLimitSet \ + I2SRxFIFOLimitSet +#endif +#ifdef ROM_I2SRxFIFOLimitGet +#define MAP_I2SRxFIFOLimitGet \ + ROM_I2SRxFIFOLimitGet +#else +#define MAP_I2SRxFIFOLimitGet \ + I2SRxFIFOLimitGet +#endif +#ifdef ROM_I2SRxFIFOLevelGet +#define MAP_I2SRxFIFOLevelGet \ + ROM_I2SRxFIFOLevelGet +#else +#define MAP_I2SRxFIFOLevelGet \ + I2SRxFIFOLevelGet +#endif +#ifdef ROM_I2STxRxEnable +#define MAP_I2STxRxEnable \ + ROM_I2STxRxEnable +#else +#define MAP_I2STxRxEnable \ + I2STxRxEnable +#endif +#ifdef ROM_I2STxRxDisable +#define MAP_I2STxRxDisable \ + ROM_I2STxRxDisable +#else +#define MAP_I2STxRxDisable \ + I2STxRxDisable +#endif +#ifdef ROM_I2STxRxConfigSet +#define MAP_I2STxRxConfigSet \ + ROM_I2STxRxConfigSet +#else +#define MAP_I2STxRxConfigSet \ + I2STxRxConfigSet +#endif +#ifdef ROM_I2SMasterClockSelect +#define MAP_I2SMasterClockSelect \ + ROM_I2SMasterClockSelect +#else +#define MAP_I2SMasterClockSelect \ + I2SMasterClockSelect +#endif +#ifdef ROM_I2SIntEnable +#define MAP_I2SIntEnable \ + ROM_I2SIntEnable +#else +#define MAP_I2SIntEnable \ + I2SIntEnable +#endif +#ifdef ROM_I2SIntDisable +#define MAP_I2SIntDisable \ + ROM_I2SIntDisable +#else +#define MAP_I2SIntDisable \ + I2SIntDisable +#endif +#ifdef ROM_I2SIntClear +#define MAP_I2SIntClear \ + ROM_I2SIntClear +#else +#define MAP_I2SIntClear \ + I2SIntClear +#endif + +//***************************************************************************** +// +// Macros for the Interrupt API. +// +//***************************************************************************** +#ifdef ROM_IntEnable +#define MAP_IntEnable \ + ROM_IntEnable +#else +#define MAP_IntEnable \ + IntEnable +#endif +#ifdef ROM_IntMasterEnable +#define MAP_IntMasterEnable \ + ROM_IntMasterEnable +#else +#define MAP_IntMasterEnable \ + IntMasterEnable +#endif +#ifdef ROM_IntMasterDisable +#define MAP_IntMasterDisable \ + ROM_IntMasterDisable +#else +#define MAP_IntMasterDisable \ + IntMasterDisable +#endif +#ifdef ROM_IntDisable +#define MAP_IntDisable \ + ROM_IntDisable +#else +#define MAP_IntDisable \ + IntDisable +#endif +#ifdef ROM_IntPriorityGroupingSet +#define MAP_IntPriorityGroupingSet \ + ROM_IntPriorityGroupingSet +#else +#define MAP_IntPriorityGroupingSet \ + IntPriorityGroupingSet +#endif +#ifdef ROM_IntPriorityGroupingGet +#define MAP_IntPriorityGroupingGet \ + ROM_IntPriorityGroupingGet +#else +#define MAP_IntPriorityGroupingGet \ + IntPriorityGroupingGet +#endif +#ifdef ROM_IntPrioritySet +#define MAP_IntPrioritySet \ + ROM_IntPrioritySet +#else +#define MAP_IntPrioritySet \ + IntPrioritySet +#endif +#ifdef ROM_IntPriorityGet +#define MAP_IntPriorityGet \ + ROM_IntPriorityGet +#else +#define MAP_IntPriorityGet \ + IntPriorityGet +#endif +#ifdef ROM_IntPendSet +#define MAP_IntPendSet \ + ROM_IntPendSet +#else +#define MAP_IntPendSet \ + IntPendSet +#endif +#ifdef ROM_IntPendClear +#define MAP_IntPendClear \ + ROM_IntPendClear +#else +#define MAP_IntPendClear \ + IntPendClear +#endif +#ifdef ROM_IntPriorityMaskSet +#define MAP_IntPriorityMaskSet \ + ROM_IntPriorityMaskSet +#else +#define MAP_IntPriorityMaskSet \ + IntPriorityMaskSet +#endif +#ifdef ROM_IntPriorityMaskGet +#define MAP_IntPriorityMaskGet \ + ROM_IntPriorityMaskGet +#else +#define MAP_IntPriorityMaskGet \ + IntPriorityMaskGet +#endif + +//***************************************************************************** +// +// Macros for the LPC API. +// +//***************************************************************************** +#ifdef ROM_LPCIntClear +#define MAP_LPCIntClear \ + ROM_LPCIntClear +#else +#define MAP_LPCIntClear \ + LPCIntClear +#endif +#ifdef ROM_LPCByteRead +#define MAP_LPCByteRead \ + ROM_LPCByteRead +#else +#define MAP_LPCByteRead \ + LPCByteRead +#endif +#ifdef ROM_LPCByteWrite +#define MAP_LPCByteWrite \ + ROM_LPCByteWrite +#else +#define MAP_LPCByteWrite \ + LPCByteWrite +#endif +#ifdef ROM_LPCChannelConfigCOMxSet +#define MAP_LPCChannelConfigCOMxSet \ + ROM_LPCChannelConfigCOMxSet +#else +#define MAP_LPCChannelConfigCOMxSet \ + LPCChannelConfigCOMxSet +#endif +#ifdef ROM_LPCChannelConfigGet +#define MAP_LPCChannelConfigGet \ + ROM_LPCChannelConfigGet +#else +#define MAP_LPCChannelConfigGet \ + LPCChannelConfigGet +#endif +#ifdef ROM_LPCChannelConfigEPSet +#define MAP_LPCChannelConfigEPSet \ + ROM_LPCChannelConfigEPSet +#else +#define MAP_LPCChannelConfigEPSet \ + LPCChannelConfigEPSet +#endif +#ifdef ROM_LPCChannelConfigMBSet +#define MAP_LPCChannelConfigMBSet \ + ROM_LPCChannelConfigMBSet +#else +#define MAP_LPCChannelConfigMBSet \ + LPCChannelConfigMBSet +#endif +#ifdef ROM_LPCChannelDMAConfigGet +#define MAP_LPCChannelDMAConfigGet \ + ROM_LPCChannelDMAConfigGet +#else +#define MAP_LPCChannelDMAConfigGet \ + LPCChannelDMAConfigGet +#endif +#ifdef ROM_LPCChannelDMAConfigSet +#define MAP_LPCChannelDMAConfigSet \ + ROM_LPCChannelDMAConfigSet +#else +#define MAP_LPCChannelDMAConfigSet \ + LPCChannelDMAConfigSet +#endif +#ifdef ROM_LPCChannelDisable +#define MAP_LPCChannelDisable \ + ROM_LPCChannelDisable +#else +#define MAP_LPCChannelDisable \ + LPCChannelDisable +#endif +#ifdef ROM_LPCChannelEnable +#define MAP_LPCChannelEnable \ + ROM_LPCChannelEnable +#else +#define MAP_LPCChannelEnable \ + LPCChannelEnable +#endif +#ifdef ROM_LPCChannelStatusClear +#define MAP_LPCChannelStatusClear \ + ROM_LPCChannelStatusClear +#else +#define MAP_LPCChannelStatusClear \ + LPCChannelStatusClear +#endif +#ifdef ROM_LPCChannelStatusGet +#define MAP_LPCChannelStatusGet \ + ROM_LPCChannelStatusGet +#else +#define MAP_LPCChannelStatusGet \ + LPCChannelStatusGet +#endif +#ifdef ROM_LPCChannelStatusSet +#define MAP_LPCChannelStatusSet \ + ROM_LPCChannelStatusSet +#else +#define MAP_LPCChannelStatusSet \ + LPCChannelStatusSet +#endif +#ifdef ROM_LPCCOMxIntClear +#define MAP_LPCCOMxIntClear \ + ROM_LPCCOMxIntClear +#else +#define MAP_LPCCOMxIntClear \ + LPCCOMxIntClear +#endif +#ifdef ROM_LPCCOMxIntDisable +#define MAP_LPCCOMxIntDisable \ + ROM_LPCCOMxIntDisable +#else +#define MAP_LPCCOMxIntDisable \ + LPCCOMxIntDisable +#endif +#ifdef ROM_LPCCOMxIntEnable +#define MAP_LPCCOMxIntEnable \ + ROM_LPCCOMxIntEnable +#else +#define MAP_LPCCOMxIntEnable \ + LPCCOMxIntEnable +#endif +#ifdef ROM_LPCCOMxIntStatus +#define MAP_LPCCOMxIntStatus \ + ROM_LPCCOMxIntStatus +#else +#define MAP_LPCCOMxIntStatus \ + LPCCOMxIntStatus +#endif +#ifdef ROM_LPCConfigGet +#define MAP_LPCConfigGet \ + ROM_LPCConfigGet +#else +#define MAP_LPCConfigGet \ + LPCConfigGet +#endif +#ifdef ROM_LPCConfigSet +#define MAP_LPCConfigSet \ + ROM_LPCConfigSet +#else +#define MAP_LPCConfigSet \ + LPCConfigSet +#endif +#ifdef ROM_LPCHalfWordRead +#define MAP_LPCHalfWordRead \ + ROM_LPCHalfWordRead +#else +#define MAP_LPCHalfWordRead \ + LPCHalfWordRead +#endif +#ifdef ROM_LPCHalfWordWrite +#define MAP_LPCHalfWordWrite \ + ROM_LPCHalfWordWrite +#else +#define MAP_LPCHalfWordWrite \ + LPCHalfWordWrite +#endif +#ifdef ROM_LPCIRQClear +#define MAP_LPCIRQClear \ + ROM_LPCIRQClear +#else +#define MAP_LPCIRQClear \ + LPCIRQClear +#endif +#ifdef ROM_LPCIRQConfig +#define MAP_LPCIRQConfig \ + ROM_LPCIRQConfig +#else +#define MAP_LPCIRQConfig \ + LPCIRQConfig +#endif +#ifdef ROM_LPCIRQGet +#define MAP_LPCIRQGet \ + ROM_LPCIRQGet +#else +#define MAP_LPCIRQGet \ + LPCIRQGet +#endif +#ifdef ROM_LPCIRQSend +#define MAP_LPCIRQSend \ + ROM_LPCIRQSend +#else +#define MAP_LPCIRQSend \ + LPCIRQSend +#endif +#ifdef ROM_LPCIRQSet +#define MAP_LPCIRQSet \ + ROM_LPCIRQSet +#else +#define MAP_LPCIRQSet \ + LPCIRQSet +#endif +#ifdef ROM_LPCIntDisable +#define MAP_LPCIntDisable \ + ROM_LPCIntDisable +#else +#define MAP_LPCIntDisable \ + LPCIntDisable +#endif +#ifdef ROM_LPCIntEnable +#define MAP_LPCIntEnable \ + ROM_LPCIntEnable +#else +#define MAP_LPCIntEnable \ + LPCIntEnable +#endif +#ifdef ROM_LPCIntStatus +#define MAP_LPCIntStatus \ + ROM_LPCIntStatus +#else +#define MAP_LPCIntStatus \ + LPCIntStatus +#endif +#ifdef ROM_LPCSCIAssert +#define MAP_LPCSCIAssert \ + ROM_LPCSCIAssert +#else +#define MAP_LPCSCIAssert \ + LPCSCIAssert +#endif +#ifdef ROM_LPCStatusGet +#define MAP_LPCStatusGet \ + ROM_LPCStatusGet +#else +#define MAP_LPCStatusGet \ + LPCStatusGet +#endif +#ifdef ROM_LPCWordRead +#define MAP_LPCWordRead \ + ROM_LPCWordRead +#else +#define MAP_LPCWordRead \ + LPCWordRead +#endif +#ifdef ROM_LPCWordWrite +#define MAP_LPCWordWrite \ + ROM_LPCWordWrite +#else +#define MAP_LPCWordWrite \ + LPCWordWrite +#endif +#ifdef ROM_LPCChannelPoolAddressGet +#define MAP_LPCChannelPoolAddressGet \ + ROM_LPCChannelPoolAddressGet +#else +#define MAP_LPCChannelPoolAddressGet \ + LPCChannelPoolAddressGet +#endif +#ifdef ROM_LPCStatusBlockAddressGet +#define MAP_LPCStatusBlockAddressGet \ + ROM_LPCStatusBlockAddressGet +#else +#define MAP_LPCStatusBlockAddressGet \ + LPCStatusBlockAddressGet +#endif +#ifdef ROM_LPCStatusBlockAddressSet +#define MAP_LPCStatusBlockAddressSet \ + ROM_LPCStatusBlockAddressSet +#else +#define MAP_LPCStatusBlockAddressSet \ + LPCStatusBlockAddressSet +#endif + +//***************************************************************************** +// +// Macros for the MPU API. +// +//***************************************************************************** +#ifdef ROM_MPUEnable +#define MAP_MPUEnable \ + ROM_MPUEnable +#else +#define MAP_MPUEnable \ + MPUEnable +#endif +#ifdef ROM_MPUDisable +#define MAP_MPUDisable \ + ROM_MPUDisable +#else +#define MAP_MPUDisable \ + MPUDisable +#endif +#ifdef ROM_MPURegionCountGet +#define MAP_MPURegionCountGet \ + ROM_MPURegionCountGet +#else +#define MAP_MPURegionCountGet \ + MPURegionCountGet +#endif +#ifdef ROM_MPURegionEnable +#define MAP_MPURegionEnable \ + ROM_MPURegionEnable +#else +#define MAP_MPURegionEnable \ + MPURegionEnable +#endif +#ifdef ROM_MPURegionDisable +#define MAP_MPURegionDisable \ + ROM_MPURegionDisable +#else +#define MAP_MPURegionDisable \ + MPURegionDisable +#endif +#ifdef ROM_MPURegionSet +#define MAP_MPURegionSet \ + ROM_MPURegionSet +#else +#define MAP_MPURegionSet \ + MPURegionSet +#endif +#ifdef ROM_MPURegionGet +#define MAP_MPURegionGet \ + ROM_MPURegionGet +#else +#define MAP_MPURegionGet \ + MPURegionGet +#endif + +//***************************************************************************** +// +// Macros for the PECI API. +// +//***************************************************************************** +#ifdef ROM_PECIIntClear +#define MAP_PECIIntClear \ + ROM_PECIIntClear +#else +#define MAP_PECIIntClear \ + PECIIntClear +#endif +#ifdef ROM_PECIAdvCmdSend +#define MAP_PECIAdvCmdSend \ + ROM_PECIAdvCmdSend +#else +#define MAP_PECIAdvCmdSend \ + PECIAdvCmdSend +#endif +#ifdef ROM_PECIAdvCmdSendNonBlocking +#define MAP_PECIAdvCmdSendNonBlocking \ + ROM_PECIAdvCmdSendNonBlocking +#else +#define MAP_PECIAdvCmdSendNonBlocking \ + PECIAdvCmdSendNonBlocking +#endif +#ifdef ROM_PECIAdvCmdStatusGet +#define MAP_PECIAdvCmdStatusGet \ + ROM_PECIAdvCmdStatusGet +#else +#define MAP_PECIAdvCmdStatusGet \ + PECIAdvCmdStatusGet +#endif +#ifdef ROM_PECIConfigGet +#define MAP_PECIConfigGet \ + ROM_PECIConfigGet +#else +#define MAP_PECIConfigGet \ + PECIConfigGet +#endif +#ifdef ROM_PECIConfigSet +#define MAP_PECIConfigSet \ + ROM_PECIConfigSet +#else +#define MAP_PECIConfigSet \ + PECIConfigSet +#endif +#ifdef ROM_PECIDomainMaxReadClear +#define MAP_PECIDomainMaxReadClear \ + ROM_PECIDomainMaxReadClear +#else +#define MAP_PECIDomainMaxReadClear \ + PECIDomainMaxReadClear +#endif +#ifdef ROM_PECIDomainValueClear +#define MAP_PECIDomainValueClear \ + ROM_PECIDomainValueClear +#else +#define MAP_PECIDomainValueClear \ + PECIDomainValueClear +#endif +#ifdef ROM_PECIDomainConfigGet +#define MAP_PECIDomainConfigGet \ + ROM_PECIDomainConfigGet +#else +#define MAP_PECIDomainConfigGet \ + PECIDomainConfigGet +#endif +#ifdef ROM_PECIDomainConfigSet +#define MAP_PECIDomainConfigSet \ + ROM_PECIDomainConfigSet +#else +#define MAP_PECIDomainConfigSet \ + PECIDomainConfigSet +#endif +#ifdef ROM_PECIDomainDisable +#define MAP_PECIDomainDisable \ + ROM_PECIDomainDisable +#else +#define MAP_PECIDomainDisable \ + PECIDomainDisable +#endif +#ifdef ROM_PECIDomainEnable +#define MAP_PECIDomainEnable \ + ROM_PECIDomainEnable +#else +#define MAP_PECIDomainEnable \ + PECIDomainEnable +#endif +#ifdef ROM_PECIDomainMaxReadGet +#define MAP_PECIDomainMaxReadGet \ + ROM_PECIDomainMaxReadGet +#else +#define MAP_PECIDomainMaxReadGet \ + PECIDomainMaxReadGet +#endif +#ifdef ROM_PECIDomainValueGet +#define MAP_PECIDomainValueGet \ + ROM_PECIDomainValueGet +#else +#define MAP_PECIDomainValueGet \ + PECIDomainValueGet +#endif +#ifdef ROM_PECIIntDisable +#define MAP_PECIIntDisable \ + ROM_PECIIntDisable +#else +#define MAP_PECIIntDisable \ + PECIIntDisable +#endif +#ifdef ROM_PECIIntEnable +#define MAP_PECIIntEnable \ + ROM_PECIIntEnable +#else +#define MAP_PECIIntEnable \ + PECIIntEnable +#endif +#ifdef ROM_PECIIntStatus +#define MAP_PECIIntStatus \ + ROM_PECIIntStatus +#else +#define MAP_PECIIntStatus \ + PECIIntStatus +#endif +#ifdef ROM_PECIBypassEnable +#define MAP_PECIBypassEnable \ + ROM_PECIBypassEnable +#else +#define MAP_PECIBypassEnable \ + PECIBypassEnable +#endif +#ifdef ROM_PECIBypassDisable +#define MAP_PECIBypassDisable \ + ROM_PECIBypassDisable +#else +#define MAP_PECIBypassDisable \ + PECIBypassDisable +#endif + +//***************************************************************************** +// +// Macros for the PWM API. +// +//***************************************************************************** +#ifdef ROM_PWMPulseWidthSet +#define MAP_PWMPulseWidthSet \ + ROM_PWMPulseWidthSet +#else +#define MAP_PWMPulseWidthSet \ + PWMPulseWidthSet +#endif +#ifdef ROM_PWMGenConfigure +#define MAP_PWMGenConfigure \ + ROM_PWMGenConfigure +#else +#define MAP_PWMGenConfigure \ + PWMGenConfigure +#endif +#ifdef ROM_PWMGenPeriodSet +#define MAP_PWMGenPeriodSet \ + ROM_PWMGenPeriodSet +#else +#define MAP_PWMGenPeriodSet \ + PWMGenPeriodSet +#endif +#ifdef ROM_PWMGenPeriodGet +#define MAP_PWMGenPeriodGet \ + ROM_PWMGenPeriodGet +#else +#define MAP_PWMGenPeriodGet \ + PWMGenPeriodGet +#endif +#ifdef ROM_PWMGenEnable +#define MAP_PWMGenEnable \ + ROM_PWMGenEnable +#else +#define MAP_PWMGenEnable \ + PWMGenEnable +#endif +#ifdef ROM_PWMGenDisable +#define MAP_PWMGenDisable \ + ROM_PWMGenDisable +#else +#define MAP_PWMGenDisable \ + PWMGenDisable +#endif +#ifdef ROM_PWMPulseWidthGet +#define MAP_PWMPulseWidthGet \ + ROM_PWMPulseWidthGet +#else +#define MAP_PWMPulseWidthGet \ + PWMPulseWidthGet +#endif +#ifdef ROM_PWMDeadBandEnable +#define MAP_PWMDeadBandEnable \ + ROM_PWMDeadBandEnable +#else +#define MAP_PWMDeadBandEnable \ + PWMDeadBandEnable +#endif +#ifdef ROM_PWMDeadBandDisable +#define MAP_PWMDeadBandDisable \ + ROM_PWMDeadBandDisable +#else +#define MAP_PWMDeadBandDisable \ + PWMDeadBandDisable +#endif +#ifdef ROM_PWMSyncUpdate +#define MAP_PWMSyncUpdate \ + ROM_PWMSyncUpdate +#else +#define MAP_PWMSyncUpdate \ + PWMSyncUpdate +#endif +#ifdef ROM_PWMSyncTimeBase +#define MAP_PWMSyncTimeBase \ + ROM_PWMSyncTimeBase +#else +#define MAP_PWMSyncTimeBase \ + PWMSyncTimeBase +#endif +#ifdef ROM_PWMOutputState +#define MAP_PWMOutputState \ + ROM_PWMOutputState +#else +#define MAP_PWMOutputState \ + PWMOutputState +#endif +#ifdef ROM_PWMOutputInvert +#define MAP_PWMOutputInvert \ + ROM_PWMOutputInvert +#else +#define MAP_PWMOutputInvert \ + PWMOutputInvert +#endif +#ifdef ROM_PWMOutputFault +#define MAP_PWMOutputFault \ + ROM_PWMOutputFault +#else +#define MAP_PWMOutputFault \ + PWMOutputFault +#endif +#ifdef ROM_PWMGenIntTrigEnable +#define MAP_PWMGenIntTrigEnable \ + ROM_PWMGenIntTrigEnable +#else +#define MAP_PWMGenIntTrigEnable \ + PWMGenIntTrigEnable +#endif +#ifdef ROM_PWMGenIntTrigDisable +#define MAP_PWMGenIntTrigDisable \ + ROM_PWMGenIntTrigDisable +#else +#define MAP_PWMGenIntTrigDisable \ + PWMGenIntTrigDisable +#endif +#ifdef ROM_PWMGenIntStatus +#define MAP_PWMGenIntStatus \ + ROM_PWMGenIntStatus +#else +#define MAP_PWMGenIntStatus \ + PWMGenIntStatus +#endif +#ifdef ROM_PWMGenIntClear +#define MAP_PWMGenIntClear \ + ROM_PWMGenIntClear +#else +#define MAP_PWMGenIntClear \ + PWMGenIntClear +#endif +#ifdef ROM_PWMIntEnable +#define MAP_PWMIntEnable \ + ROM_PWMIntEnable +#else +#define MAP_PWMIntEnable \ + PWMIntEnable +#endif +#ifdef ROM_PWMIntDisable +#define MAP_PWMIntDisable \ + ROM_PWMIntDisable +#else +#define MAP_PWMIntDisable \ + PWMIntDisable +#endif +#ifdef ROM_PWMFaultIntClear +#define MAP_PWMFaultIntClear \ + ROM_PWMFaultIntClear +#else +#define MAP_PWMFaultIntClear \ + PWMFaultIntClear +#endif +#ifdef ROM_PWMIntStatus +#define MAP_PWMIntStatus \ + ROM_PWMIntStatus +#else +#define MAP_PWMIntStatus \ + PWMIntStatus +#endif +#ifdef ROM_PWMOutputFaultLevel +#define MAP_PWMOutputFaultLevel \ + ROM_PWMOutputFaultLevel +#else +#define MAP_PWMOutputFaultLevel \ + PWMOutputFaultLevel +#endif +#ifdef ROM_PWMFaultIntClearExt +#define MAP_PWMFaultIntClearExt \ + ROM_PWMFaultIntClearExt +#else +#define MAP_PWMFaultIntClearExt \ + PWMFaultIntClearExt +#endif +#ifdef ROM_PWMGenFaultConfigure +#define MAP_PWMGenFaultConfigure \ + ROM_PWMGenFaultConfigure +#else +#define MAP_PWMGenFaultConfigure \ + PWMGenFaultConfigure +#endif +#ifdef ROM_PWMGenFaultTriggerSet +#define MAP_PWMGenFaultTriggerSet \ + ROM_PWMGenFaultTriggerSet +#else +#define MAP_PWMGenFaultTriggerSet \ + PWMGenFaultTriggerSet +#endif +#ifdef ROM_PWMGenFaultTriggerGet +#define MAP_PWMGenFaultTriggerGet \ + ROM_PWMGenFaultTriggerGet +#else +#define MAP_PWMGenFaultTriggerGet \ + PWMGenFaultTriggerGet +#endif +#ifdef ROM_PWMGenFaultStatus +#define MAP_PWMGenFaultStatus \ + ROM_PWMGenFaultStatus +#else +#define MAP_PWMGenFaultStatus \ + PWMGenFaultStatus +#endif +#ifdef ROM_PWMGenFaultClear +#define MAP_PWMGenFaultClear \ + ROM_PWMGenFaultClear +#else +#define MAP_PWMGenFaultClear \ + PWMGenFaultClear +#endif + +//***************************************************************************** +// +// Macros for the QEI API. +// +//***************************************************************************** +#ifdef ROM_QEIPositionGet +#define MAP_QEIPositionGet \ + ROM_QEIPositionGet +#else +#define MAP_QEIPositionGet \ + QEIPositionGet +#endif +#ifdef ROM_QEIEnable +#define MAP_QEIEnable \ + ROM_QEIEnable +#else +#define MAP_QEIEnable \ + QEIEnable +#endif +#ifdef ROM_QEIDisable +#define MAP_QEIDisable \ + ROM_QEIDisable +#else +#define MAP_QEIDisable \ + QEIDisable +#endif +#ifdef ROM_QEIConfigure +#define MAP_QEIConfigure \ + ROM_QEIConfigure +#else +#define MAP_QEIConfigure \ + QEIConfigure +#endif +#ifdef ROM_QEIPositionSet +#define MAP_QEIPositionSet \ + ROM_QEIPositionSet +#else +#define MAP_QEIPositionSet \ + QEIPositionSet +#endif +#ifdef ROM_QEIDirectionGet +#define MAP_QEIDirectionGet \ + ROM_QEIDirectionGet +#else +#define MAP_QEIDirectionGet \ + QEIDirectionGet +#endif +#ifdef ROM_QEIErrorGet +#define MAP_QEIErrorGet \ + ROM_QEIErrorGet +#else +#define MAP_QEIErrorGet \ + QEIErrorGet +#endif +#ifdef ROM_QEIVelocityEnable +#define MAP_QEIVelocityEnable \ + ROM_QEIVelocityEnable +#else +#define MAP_QEIVelocityEnable \ + QEIVelocityEnable +#endif +#ifdef ROM_QEIVelocityDisable +#define MAP_QEIVelocityDisable \ + ROM_QEIVelocityDisable +#else +#define MAP_QEIVelocityDisable \ + QEIVelocityDisable +#endif +#ifdef ROM_QEIVelocityConfigure +#define MAP_QEIVelocityConfigure \ + ROM_QEIVelocityConfigure +#else +#define MAP_QEIVelocityConfigure \ + QEIVelocityConfigure +#endif +#ifdef ROM_QEIVelocityGet +#define MAP_QEIVelocityGet \ + ROM_QEIVelocityGet +#else +#define MAP_QEIVelocityGet \ + QEIVelocityGet +#endif +#ifdef ROM_QEIIntEnable +#define MAP_QEIIntEnable \ + ROM_QEIIntEnable +#else +#define MAP_QEIIntEnable \ + QEIIntEnable +#endif +#ifdef ROM_QEIIntDisable +#define MAP_QEIIntDisable \ + ROM_QEIIntDisable +#else +#define MAP_QEIIntDisable \ + QEIIntDisable +#endif +#ifdef ROM_QEIIntStatus +#define MAP_QEIIntStatus \ + ROM_QEIIntStatus +#else +#define MAP_QEIIntStatus \ + QEIIntStatus +#endif +#ifdef ROM_QEIIntClear +#define MAP_QEIIntClear \ + ROM_QEIIntClear +#else +#define MAP_QEIIntClear \ + QEIIntClear +#endif + +//***************************************************************************** +// +// Macros for the SMBus API. +// +//***************************************************************************** +#ifdef ROM_SMBusMasterIntProcess +#define MAP_SMBusMasterIntProcess \ + ROM_SMBusMasterIntProcess +#else +#define MAP_SMBusMasterIntProcess \ + SMBusMasterIntProcess +#endif +#ifdef ROM_SMBusARPDisable +#define MAP_SMBusARPDisable \ + ROM_SMBusARPDisable +#else +#define MAP_SMBusARPDisable \ + SMBusARPDisable +#endif +#ifdef ROM_SMBusARPEnable +#define MAP_SMBusARPEnable \ + ROM_SMBusARPEnable +#else +#define MAP_SMBusARPEnable \ + SMBusARPEnable +#endif +#ifdef ROM_SMBusARPUDIDPacketDecode +#define MAP_SMBusARPUDIDPacketDecode \ + ROM_SMBusARPUDIDPacketDecode +#else +#define MAP_SMBusARPUDIDPacketDecode \ + SMBusARPUDIDPacketDecode +#endif +#ifdef ROM_SMBusARPUDIDPacketEncode +#define MAP_SMBusARPUDIDPacketEncode \ + ROM_SMBusARPUDIDPacketEncode +#else +#define MAP_SMBusARPUDIDPacketEncode \ + SMBusARPUDIDPacketEncode +#endif +#ifdef ROM_SMBusMasterARPAssignAddress +#define MAP_SMBusMasterARPAssignAddress \ + ROM_SMBusMasterARPAssignAddress +#else +#define MAP_SMBusMasterARPAssignAddress \ + SMBusMasterARPAssignAddress +#endif +#ifdef ROM_SMBusMasterARPGetUDIDDir +#define MAP_SMBusMasterARPGetUDIDDir \ + ROM_SMBusMasterARPGetUDIDDir +#else +#define MAP_SMBusMasterARPGetUDIDDir \ + SMBusMasterARPGetUDIDDir +#endif +#ifdef ROM_SMBusMasterARPGetUDIDGen +#define MAP_SMBusMasterARPGetUDIDGen \ + ROM_SMBusMasterARPGetUDIDGen +#else +#define MAP_SMBusMasterARPGetUDIDGen \ + SMBusMasterARPGetUDIDGen +#endif +#ifdef ROM_SMBusMasterARPNotifyMaster +#define MAP_SMBusMasterARPNotifyMaster \ + ROM_SMBusMasterARPNotifyMaster +#else +#define MAP_SMBusMasterARPNotifyMaster \ + SMBusMasterARPNotifyMaster +#endif +#ifdef ROM_SMBusMasterARPPrepareToARP +#define MAP_SMBusMasterARPPrepareToARP \ + ROM_SMBusMasterARPPrepareToARP +#else +#define MAP_SMBusMasterARPPrepareToARP \ + SMBusMasterARPPrepareToARP +#endif +#ifdef ROM_SMBusMasterARPResetDeviceDir +#define MAP_SMBusMasterARPResetDeviceDir \ + ROM_SMBusMasterARPResetDeviceDir +#else +#define MAP_SMBusMasterARPResetDeviceDir \ + SMBusMasterARPResetDeviceDir +#endif +#ifdef ROM_SMBusMasterARPResetDeviceGen +#define MAP_SMBusMasterARPResetDeviceGen \ + ROM_SMBusMasterARPResetDeviceGen +#else +#define MAP_SMBusMasterARPResetDeviceGen \ + SMBusMasterARPResetDeviceGen +#endif +#ifdef ROM_SMBusMasterBlockProcessCall +#define MAP_SMBusMasterBlockProcessCall \ + ROM_SMBusMasterBlockProcessCall +#else +#define MAP_SMBusMasterBlockProcessCall \ + SMBusMasterBlockProcessCall +#endif +#ifdef ROM_SMBusMasterBlockRead +#define MAP_SMBusMasterBlockRead \ + ROM_SMBusMasterBlockRead +#else +#define MAP_SMBusMasterBlockRead \ + SMBusMasterBlockRead +#endif +#ifdef ROM_SMBusMasterBlockWrite +#define MAP_SMBusMasterBlockWrite \ + ROM_SMBusMasterBlockWrite +#else +#define MAP_SMBusMasterBlockWrite \ + SMBusMasterBlockWrite +#endif +#ifdef ROM_SMBusMasterByteReceive +#define MAP_SMBusMasterByteReceive \ + ROM_SMBusMasterByteReceive +#else +#define MAP_SMBusMasterByteReceive \ + SMBusMasterByteReceive +#endif +#ifdef ROM_SMBusMasterByteSend +#define MAP_SMBusMasterByteSend \ + ROM_SMBusMasterByteSend +#else +#define MAP_SMBusMasterByteSend \ + SMBusMasterByteSend +#endif +#ifdef ROM_SMBusMasterByteWordRead +#define MAP_SMBusMasterByteWordRead \ + ROM_SMBusMasterByteWordRead +#else +#define MAP_SMBusMasterByteWordRead \ + SMBusMasterByteWordRead +#endif +#ifdef ROM_SMBusMasterByteWordWrite +#define MAP_SMBusMasterByteWordWrite \ + ROM_SMBusMasterByteWordWrite +#else +#define MAP_SMBusMasterByteWordWrite \ + SMBusMasterByteWordWrite +#endif +#ifdef ROM_SMBusMasterHostNotify +#define MAP_SMBusMasterHostNotify \ + ROM_SMBusMasterHostNotify +#else +#define MAP_SMBusMasterHostNotify \ + SMBusMasterHostNotify +#endif +#ifdef ROM_SMBusMasterI2CRead +#define MAP_SMBusMasterI2CRead \ + ROM_SMBusMasterI2CRead +#else +#define MAP_SMBusMasterI2CRead \ + SMBusMasterI2CRead +#endif +#ifdef ROM_SMBusMasterI2CWrite +#define MAP_SMBusMasterI2CWrite \ + ROM_SMBusMasterI2CWrite +#else +#define MAP_SMBusMasterI2CWrite \ + SMBusMasterI2CWrite +#endif +#ifdef ROM_SMBusMasterI2CWriteRead +#define MAP_SMBusMasterI2CWriteRead \ + ROM_SMBusMasterI2CWriteRead +#else +#define MAP_SMBusMasterI2CWriteRead \ + SMBusMasterI2CWriteRead +#endif +#ifdef ROM_SMBusMasterInit +#define MAP_SMBusMasterInit \ + ROM_SMBusMasterInit +#else +#define MAP_SMBusMasterInit \ + SMBusMasterInit +#endif +#ifdef ROM_SMBusMasterIntEnable +#define MAP_SMBusMasterIntEnable \ + ROM_SMBusMasterIntEnable +#else +#define MAP_SMBusMasterIntEnable \ + SMBusMasterIntEnable +#endif +#ifdef ROM_SMBusMasterProcessCall +#define MAP_SMBusMasterProcessCall \ + ROM_SMBusMasterProcessCall +#else +#define MAP_SMBusMasterProcessCall \ + SMBusMasterProcessCall +#endif +#ifdef ROM_SMBusMasterQuickCommand +#define MAP_SMBusMasterQuickCommand \ + ROM_SMBusMasterQuickCommand +#else +#define MAP_SMBusMasterQuickCommand \ + SMBusMasterQuickCommand +#endif +#ifdef ROM_SMBusPECDisable +#define MAP_SMBusPECDisable \ + ROM_SMBusPECDisable +#else +#define MAP_SMBusPECDisable \ + SMBusPECDisable +#endif +#ifdef ROM_SMBusPECEnable +#define MAP_SMBusPECEnable \ + ROM_SMBusPECEnable +#else +#define MAP_SMBusPECEnable \ + SMBusPECEnable +#endif +#ifdef ROM_SMBusRxPacketSizeGet +#define MAP_SMBusRxPacketSizeGet \ + ROM_SMBusRxPacketSizeGet +#else +#define MAP_SMBusRxPacketSizeGet \ + SMBusRxPacketSizeGet +#endif +#ifdef ROM_SMBusSlaveACKSend +#define MAP_SMBusSlaveACKSend \ + ROM_SMBusSlaveACKSend +#else +#define MAP_SMBusSlaveACKSend \ + SMBusSlaveACKSend +#endif +#ifdef ROM_SMBusSlaveAddressSet +#define MAP_SMBusSlaveAddressSet \ + ROM_SMBusSlaveAddressSet +#else +#define MAP_SMBusSlaveAddressSet \ + SMBusSlaveAddressSet +#endif +#ifdef ROM_SMBusSlaveARPFlagARGet +#define MAP_SMBusSlaveARPFlagARGet \ + ROM_SMBusSlaveARPFlagARGet +#else +#define MAP_SMBusSlaveARPFlagARGet \ + SMBusSlaveARPFlagARGet +#endif +#ifdef ROM_SMBusSlaveARPFlagARSet +#define MAP_SMBusSlaveARPFlagARSet \ + ROM_SMBusSlaveARPFlagARSet +#else +#define MAP_SMBusSlaveARPFlagARSet \ + SMBusSlaveARPFlagARSet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVGet +#define MAP_SMBusSlaveARPFlagAVGet \ + ROM_SMBusSlaveARPFlagAVGet +#else +#define MAP_SMBusSlaveARPFlagAVGet \ + SMBusSlaveARPFlagAVGet +#endif +#ifdef ROM_SMBusSlaveARPFlagAVSet +#define MAP_SMBusSlaveARPFlagAVSet \ + ROM_SMBusSlaveARPFlagAVSet +#else +#define MAP_SMBusSlaveARPFlagAVSet \ + SMBusSlaveARPFlagAVSet +#endif +#ifdef ROM_SMBusSlaveBlockTransferDisable +#define MAP_SMBusSlaveBlockTransferDisable \ + ROM_SMBusSlaveBlockTransferDisable +#else +#define MAP_SMBusSlaveBlockTransferDisable \ + SMBusSlaveBlockTransferDisable +#endif +#ifdef ROM_SMBusSlaveBlockTransferEnable +#define MAP_SMBusSlaveBlockTransferEnable \ + ROM_SMBusSlaveBlockTransferEnable +#else +#define MAP_SMBusSlaveBlockTransferEnable \ + SMBusSlaveBlockTransferEnable +#endif +#ifdef ROM_SMBusSlaveCommandGet +#define MAP_SMBusSlaveCommandGet \ + ROM_SMBusSlaveCommandGet +#else +#define MAP_SMBusSlaveCommandGet \ + SMBusSlaveCommandGet +#endif +#ifdef ROM_SMBusSlaveI2CDisable +#define MAP_SMBusSlaveI2CDisable \ + ROM_SMBusSlaveI2CDisable +#else +#define MAP_SMBusSlaveI2CDisable \ + SMBusSlaveI2CDisable +#endif +#ifdef ROM_SMBusSlaveI2CEnable +#define MAP_SMBusSlaveI2CEnable \ + ROM_SMBusSlaveI2CEnable +#else +#define MAP_SMBusSlaveI2CEnable \ + SMBusSlaveI2CEnable +#endif +#ifdef ROM_SMBusSlaveInit +#define MAP_SMBusSlaveInit \ + ROM_SMBusSlaveInit +#else +#define MAP_SMBusSlaveInit \ + SMBusSlaveInit +#endif +#ifdef ROM_SMBusSlaveIntAddressGet +#define MAP_SMBusSlaveIntAddressGet \ + ROM_SMBusSlaveIntAddressGet +#else +#define MAP_SMBusSlaveIntAddressGet \ + SMBusSlaveIntAddressGet +#endif +#ifdef ROM_SMBusSlaveIntEnable +#define MAP_SMBusSlaveIntEnable \ + ROM_SMBusSlaveIntEnable +#else +#define MAP_SMBusSlaveIntEnable \ + SMBusSlaveIntEnable +#endif +#ifdef ROM_SMBusSlaveIntProcess +#define MAP_SMBusSlaveIntProcess \ + ROM_SMBusSlaveIntProcess +#else +#define MAP_SMBusSlaveIntProcess \ + SMBusSlaveIntProcess +#endif +#ifdef ROM_SMBusSlaveManualACKDisable +#define MAP_SMBusSlaveManualACKDisable \ + ROM_SMBusSlaveManualACKDisable +#else +#define MAP_SMBusSlaveManualACKDisable \ + SMBusSlaveManualACKDisable +#endif +#ifdef ROM_SMBusSlaveManualACKEnable +#define MAP_SMBusSlaveManualACKEnable \ + ROM_SMBusSlaveManualACKEnable +#else +#define MAP_SMBusSlaveManualACKEnable \ + SMBusSlaveManualACKEnable +#endif +#ifdef ROM_SMBusSlaveManualACKStatusGet +#define MAP_SMBusSlaveManualACKStatusGet \ + ROM_SMBusSlaveManualACKStatusGet +#else +#define MAP_SMBusSlaveManualACKStatusGet \ + SMBusSlaveManualACKStatusGet +#endif +#ifdef ROM_SMBusSlaveProcessCallDisable +#define MAP_SMBusSlaveProcessCallDisable \ + ROM_SMBusSlaveProcessCallDisable +#else +#define MAP_SMBusSlaveProcessCallDisable \ + SMBusSlaveProcessCallDisable +#endif +#ifdef ROM_SMBusSlaveProcessCallEnable +#define MAP_SMBusSlaveProcessCallEnable \ + ROM_SMBusSlaveProcessCallEnable +#else +#define MAP_SMBusSlaveProcessCallEnable \ + SMBusSlaveProcessCallEnable +#endif +#ifdef ROM_SMBusSlaveRxBufferSet +#define MAP_SMBusSlaveRxBufferSet \ + ROM_SMBusSlaveRxBufferSet +#else +#define MAP_SMBusSlaveRxBufferSet \ + SMBusSlaveRxBufferSet +#endif +#ifdef ROM_SMBusSlaveTransferInit +#define MAP_SMBusSlaveTransferInit \ + ROM_SMBusSlaveTransferInit +#else +#define MAP_SMBusSlaveTransferInit \ + SMBusSlaveTransferInit +#endif +#ifdef ROM_SMBusSlaveTxBufferSet +#define MAP_SMBusSlaveTxBufferSet \ + ROM_SMBusSlaveTxBufferSet +#else +#define MAP_SMBusSlaveTxBufferSet \ + SMBusSlaveTxBufferSet +#endif +#ifdef ROM_SMBusSlaveUDIDSet +#define MAP_SMBusSlaveUDIDSet \ + ROM_SMBusSlaveUDIDSet +#else +#define MAP_SMBusSlaveUDIDSet \ + SMBusSlaveUDIDSet +#endif +#ifdef ROM_SMBusStatusGet +#define MAP_SMBusStatusGet \ + ROM_SMBusStatusGet +#else +#define MAP_SMBusStatusGet \ + SMBusStatusGet +#endif +#ifdef ROM_SMBusSlaveDataSend +#define MAP_SMBusSlaveDataSend \ + ROM_SMBusSlaveDataSend +#else +#define MAP_SMBusSlaveDataSend \ + SMBusSlaveDataSend +#endif + +//***************************************************************************** +// +// Macros for the SSI API. +// +//***************************************************************************** +#ifdef ROM_SSIDataPut +#define MAP_SSIDataPut \ + ROM_SSIDataPut +#else +#define MAP_SSIDataPut \ + SSIDataPut +#endif +#ifdef ROM_SSIConfigSetExpClk +#define MAP_SSIConfigSetExpClk \ + ROM_SSIConfigSetExpClk +#else +#define MAP_SSIConfigSetExpClk \ + SSIConfigSetExpClk +#endif +#ifdef ROM_SSIEnable +#define MAP_SSIEnable \ + ROM_SSIEnable +#else +#define MAP_SSIEnable \ + SSIEnable +#endif +#ifdef ROM_SSIDisable +#define MAP_SSIDisable \ + ROM_SSIDisable +#else +#define MAP_SSIDisable \ + SSIDisable +#endif +#ifdef ROM_SSIIntEnable +#define MAP_SSIIntEnable \ + ROM_SSIIntEnable +#else +#define MAP_SSIIntEnable \ + SSIIntEnable +#endif +#ifdef ROM_SSIIntDisable +#define MAP_SSIIntDisable \ + ROM_SSIIntDisable +#else +#define MAP_SSIIntDisable \ + SSIIntDisable +#endif +#ifdef ROM_SSIIntStatus +#define MAP_SSIIntStatus \ + ROM_SSIIntStatus +#else +#define MAP_SSIIntStatus \ + SSIIntStatus +#endif +#ifdef ROM_SSIIntClear +#define MAP_SSIIntClear \ + ROM_SSIIntClear +#else +#define MAP_SSIIntClear \ + SSIIntClear +#endif +#ifdef ROM_SSIDataPutNonBlocking +#define MAP_SSIDataPutNonBlocking \ + ROM_SSIDataPutNonBlocking +#else +#define MAP_SSIDataPutNonBlocking \ + SSIDataPutNonBlocking +#endif +#ifdef ROM_SSIDataGet +#define MAP_SSIDataGet \ + ROM_SSIDataGet +#else +#define MAP_SSIDataGet \ + SSIDataGet +#endif +#ifdef ROM_SSIDataGetNonBlocking +#define MAP_SSIDataGetNonBlocking \ + ROM_SSIDataGetNonBlocking +#else +#define MAP_SSIDataGetNonBlocking \ + SSIDataGetNonBlocking +#endif +#ifdef ROM_SSIDMAEnable +#define MAP_SSIDMAEnable \ + ROM_SSIDMAEnable +#else +#define MAP_SSIDMAEnable \ + SSIDMAEnable +#endif +#ifdef ROM_SSIDMADisable +#define MAP_SSIDMADisable \ + ROM_SSIDMADisable +#else +#define MAP_SSIDMADisable \ + SSIDMADisable +#endif +#ifdef ROM_SSIBusy +#define MAP_SSIBusy \ + ROM_SSIBusy +#else +#define MAP_SSIBusy \ + SSIBusy +#endif +#ifdef ROM_SSIClockSourceGet +#define MAP_SSIClockSourceGet \ + ROM_SSIClockSourceGet +#else +#define MAP_SSIClockSourceGet \ + SSIClockSourceGet +#endif +#ifdef ROM_SSIClockSourceSet +#define MAP_SSIClockSourceSet \ + ROM_SSIClockSourceSet +#else +#define MAP_SSIClockSourceSet \ + SSIClockSourceSet +#endif + +//***************************************************************************** +// +// Macros for the SysCtl API. +// +//***************************************************************************** +#ifdef ROM_SysCtlSleep +#define MAP_SysCtlSleep \ + ROM_SysCtlSleep +#else +#define MAP_SysCtlSleep \ + SysCtlSleep +#endif +#ifdef ROM_SysCtlSRAMSizeGet +#define MAP_SysCtlSRAMSizeGet \ + ROM_SysCtlSRAMSizeGet +#else +#define MAP_SysCtlSRAMSizeGet \ + SysCtlSRAMSizeGet +#endif +#ifdef ROM_SysCtlFlashSizeGet +#define MAP_SysCtlFlashSizeGet \ + ROM_SysCtlFlashSizeGet +#else +#define MAP_SysCtlFlashSizeGet \ + SysCtlFlashSizeGet +#endif +#ifdef ROM_SysCtlPinPresent +#define MAP_SysCtlPinPresent \ + ROM_SysCtlPinPresent +#else +#define MAP_SysCtlPinPresent \ + SysCtlPinPresent +#endif +#ifdef ROM_SysCtlPeripheralPresent +#define MAP_SysCtlPeripheralPresent \ + ROM_SysCtlPeripheralPresent +#else +#define MAP_SysCtlPeripheralPresent \ + SysCtlPeripheralPresent +#endif +#ifdef ROM_SysCtlPeripheralReset +#define MAP_SysCtlPeripheralReset \ + ROM_SysCtlPeripheralReset +#else +#define MAP_SysCtlPeripheralReset \ + SysCtlPeripheralReset +#endif +#ifdef ROM_SysCtlPeripheralEnable +#define MAP_SysCtlPeripheralEnable \ + ROM_SysCtlPeripheralEnable +#else +#define MAP_SysCtlPeripheralEnable \ + SysCtlPeripheralEnable +#endif +#ifdef ROM_SysCtlPeripheralDisable +#define MAP_SysCtlPeripheralDisable \ + ROM_SysCtlPeripheralDisable +#else +#define MAP_SysCtlPeripheralDisable \ + SysCtlPeripheralDisable +#endif +#ifdef ROM_SysCtlPeripheralSleepEnable +#define MAP_SysCtlPeripheralSleepEnable \ + ROM_SysCtlPeripheralSleepEnable +#else +#define MAP_SysCtlPeripheralSleepEnable \ + SysCtlPeripheralSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralSleepDisable +#define MAP_SysCtlPeripheralSleepDisable \ + ROM_SysCtlPeripheralSleepDisable +#else +#define MAP_SysCtlPeripheralSleepDisable \ + SysCtlPeripheralSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepEnable +#define MAP_SysCtlPeripheralDeepSleepEnable \ + ROM_SysCtlPeripheralDeepSleepEnable +#else +#define MAP_SysCtlPeripheralDeepSleepEnable \ + SysCtlPeripheralDeepSleepEnable +#endif +#ifdef ROM_SysCtlPeripheralDeepSleepDisable +#define MAP_SysCtlPeripheralDeepSleepDisable \ + ROM_SysCtlPeripheralDeepSleepDisable +#else +#define MAP_SysCtlPeripheralDeepSleepDisable \ + SysCtlPeripheralDeepSleepDisable +#endif +#ifdef ROM_SysCtlPeripheralClockGating +#define MAP_SysCtlPeripheralClockGating \ + ROM_SysCtlPeripheralClockGating +#else +#define MAP_SysCtlPeripheralClockGating \ + SysCtlPeripheralClockGating +#endif +#ifdef ROM_SysCtlIntEnable +#define MAP_SysCtlIntEnable \ + ROM_SysCtlIntEnable +#else +#define MAP_SysCtlIntEnable \ + SysCtlIntEnable +#endif +#ifdef ROM_SysCtlIntDisable +#define MAP_SysCtlIntDisable \ + ROM_SysCtlIntDisable +#else +#define MAP_SysCtlIntDisable \ + SysCtlIntDisable +#endif +#ifdef ROM_SysCtlIntClear +#define MAP_SysCtlIntClear \ + ROM_SysCtlIntClear +#else +#define MAP_SysCtlIntClear \ + SysCtlIntClear +#endif +#ifdef ROM_SysCtlIntStatus +#define MAP_SysCtlIntStatus \ + ROM_SysCtlIntStatus +#else +#define MAP_SysCtlIntStatus \ + SysCtlIntStatus +#endif +#ifdef ROM_SysCtlLDOSet +#define MAP_SysCtlLDOSet \ + ROM_SysCtlLDOSet +#else +#define MAP_SysCtlLDOSet \ + SysCtlLDOSet +#endif +#ifdef ROM_SysCtlLDOGet +#define MAP_SysCtlLDOGet \ + ROM_SysCtlLDOGet +#else +#define MAP_SysCtlLDOGet \ + SysCtlLDOGet +#endif +#ifdef ROM_SysCtlReset +#define MAP_SysCtlReset \ + ROM_SysCtlReset +#else +#define MAP_SysCtlReset \ + SysCtlReset +#endif +#ifdef ROM_SysCtlDeepSleep +#define MAP_SysCtlDeepSleep \ + ROM_SysCtlDeepSleep +#else +#define MAP_SysCtlDeepSleep \ + SysCtlDeepSleep +#endif +#ifdef ROM_SysCtlResetCauseGet +#define MAP_SysCtlResetCauseGet \ + ROM_SysCtlResetCauseGet +#else +#define MAP_SysCtlResetCauseGet \ + SysCtlResetCauseGet +#endif +#ifdef ROM_SysCtlResetCauseClear +#define MAP_SysCtlResetCauseClear \ + ROM_SysCtlResetCauseClear +#else +#define MAP_SysCtlResetCauseClear \ + SysCtlResetCauseClear +#endif +#ifdef ROM_SysCtlClockSet +#define MAP_SysCtlClockSet \ + ROM_SysCtlClockSet +#else +#define MAP_SysCtlClockSet \ + SysCtlClockSet +#endif +#ifdef ROM_SysCtlClockGet +#define MAP_SysCtlClockGet \ + ROM_SysCtlClockGet +#else +#define MAP_SysCtlClockGet \ + SysCtlClockGet +#endif +#ifdef ROM_SysCtlPWMClockSet +#define MAP_SysCtlPWMClockSet \ + ROM_SysCtlPWMClockSet +#else +#define MAP_SysCtlPWMClockSet \ + SysCtlPWMClockSet +#endif +#ifdef ROM_SysCtlPWMClockGet +#define MAP_SysCtlPWMClockGet \ + ROM_SysCtlPWMClockGet +#else +#define MAP_SysCtlPWMClockGet \ + SysCtlPWMClockGet +#endif +#ifdef ROM_SysCtlADCSpeedSet +#define MAP_SysCtlADCSpeedSet \ + ROM_SysCtlADCSpeedSet +#else +#define MAP_SysCtlADCSpeedSet \ + SysCtlADCSpeedSet +#endif +#ifdef ROM_SysCtlADCSpeedGet +#define MAP_SysCtlADCSpeedGet \ + ROM_SysCtlADCSpeedGet +#else +#define MAP_SysCtlADCSpeedGet \ + SysCtlADCSpeedGet +#endif +#ifdef ROM_SysCtlGPIOAHBEnable +#define MAP_SysCtlGPIOAHBEnable \ + ROM_SysCtlGPIOAHBEnable +#else +#define MAP_SysCtlGPIOAHBEnable \ + SysCtlGPIOAHBEnable +#endif +#ifdef ROM_SysCtlGPIOAHBDisable +#define MAP_SysCtlGPIOAHBDisable \ + ROM_SysCtlGPIOAHBDisable +#else +#define MAP_SysCtlGPIOAHBDisable \ + SysCtlGPIOAHBDisable +#endif +#ifdef ROM_SysCtlUSBPLLEnable +#define MAP_SysCtlUSBPLLEnable \ + ROM_SysCtlUSBPLLEnable +#else +#define MAP_SysCtlUSBPLLEnable \ + SysCtlUSBPLLEnable +#endif +#ifdef ROM_SysCtlUSBPLLDisable +#define MAP_SysCtlUSBPLLDisable \ + ROM_SysCtlUSBPLLDisable +#else +#define MAP_SysCtlUSBPLLDisable \ + SysCtlUSBPLLDisable +#endif +#ifdef ROM_SysCtlI2SMClkSet +#define MAP_SysCtlI2SMClkSet \ + ROM_SysCtlI2SMClkSet +#else +#define MAP_SysCtlI2SMClkSet \ + SysCtlI2SMClkSet +#endif +#ifdef ROM_SysCtlDelay +#define MAP_SysCtlDelay \ + ROM_SysCtlDelay +#else +#define MAP_SysCtlDelay \ + SysCtlDelay +#endif +#ifdef ROM_SysCtlPeripheralReady +#define MAP_SysCtlPeripheralReady \ + ROM_SysCtlPeripheralReady +#else +#define MAP_SysCtlPeripheralReady \ + SysCtlPeripheralReady +#endif +#ifdef ROM_SysCtlPeripheralPowerOn +#define MAP_SysCtlPeripheralPowerOn \ + ROM_SysCtlPeripheralPowerOn +#else +#define MAP_SysCtlPeripheralPowerOn \ + SysCtlPeripheralPowerOn +#endif +#ifdef ROM_SysCtlPeripheralPowerOff +#define MAP_SysCtlPeripheralPowerOff \ + ROM_SysCtlPeripheralPowerOff +#else +#define MAP_SysCtlPeripheralPowerOff \ + SysCtlPeripheralPowerOff +#endif +#ifdef ROM_SysCtlMOSCConfigSet +#define MAP_SysCtlMOSCConfigSet \ + ROM_SysCtlMOSCConfigSet +#else +#define MAP_SysCtlMOSCConfigSet \ + SysCtlMOSCConfigSet +#endif +#ifdef ROM_SysCtlPIOSCCalibrate +#define MAP_SysCtlPIOSCCalibrate \ + ROM_SysCtlPIOSCCalibrate +#else +#define MAP_SysCtlPIOSCCalibrate \ + SysCtlPIOSCCalibrate +#endif +#ifdef ROM_SysCtlDeepSleepClockSet +#define MAP_SysCtlDeepSleepClockSet \ + ROM_SysCtlDeepSleepClockSet +#else +#define MAP_SysCtlDeepSleepClockSet \ + SysCtlDeepSleepClockSet +#endif + +//***************************************************************************** +// +// Macros for the SysExc API. +// +//***************************************************************************** +#ifdef ROM_SysExcIntStatus +#define MAP_SysExcIntStatus \ + ROM_SysExcIntStatus +#else +#define MAP_SysExcIntStatus \ + SysExcIntStatus +#endif +#ifdef ROM_SysExcIntClear +#define MAP_SysExcIntClear \ + ROM_SysExcIntClear +#else +#define MAP_SysExcIntClear \ + SysExcIntClear +#endif +#ifdef ROM_SysExcIntDisable +#define MAP_SysExcIntDisable \ + ROM_SysExcIntDisable +#else +#define MAP_SysExcIntDisable \ + SysExcIntDisable +#endif +#ifdef ROM_SysExcIntEnable +#define MAP_SysExcIntEnable \ + ROM_SysExcIntEnable +#else +#define MAP_SysExcIntEnable \ + SysExcIntEnable +#endif + +//***************************************************************************** +// +// Macros for the SysTick API. +// +//***************************************************************************** +#ifdef ROM_SysTickValueGet +#define MAP_SysTickValueGet \ + ROM_SysTickValueGet +#else +#define MAP_SysTickValueGet \ + SysTickValueGet +#endif +#ifdef ROM_SysTickEnable +#define MAP_SysTickEnable \ + ROM_SysTickEnable +#else +#define MAP_SysTickEnable \ + SysTickEnable +#endif +#ifdef ROM_SysTickDisable +#define MAP_SysTickDisable \ + ROM_SysTickDisable +#else +#define MAP_SysTickDisable \ + SysTickDisable +#endif +#ifdef ROM_SysTickIntEnable +#define MAP_SysTickIntEnable \ + ROM_SysTickIntEnable +#else +#define MAP_SysTickIntEnable \ + SysTickIntEnable +#endif +#ifdef ROM_SysTickIntDisable +#define MAP_SysTickIntDisable \ + ROM_SysTickIntDisable +#else +#define MAP_SysTickIntDisable \ + SysTickIntDisable +#endif +#ifdef ROM_SysTickPeriodSet +#define MAP_SysTickPeriodSet \ + ROM_SysTickPeriodSet +#else +#define MAP_SysTickPeriodSet \ + SysTickPeriodSet +#endif +#ifdef ROM_SysTickPeriodGet +#define MAP_SysTickPeriodGet \ + ROM_SysTickPeriodGet +#else +#define MAP_SysTickPeriodGet \ + SysTickPeriodGet +#endif + +//***************************************************************************** +// +// Macros for the Timer API. +// +//***************************************************************************** +#ifdef ROM_TimerIntClear +#define MAP_TimerIntClear \ + ROM_TimerIntClear +#else +#define MAP_TimerIntClear \ + TimerIntClear +#endif +#ifdef ROM_TimerEnable +#define MAP_TimerEnable \ + ROM_TimerEnable +#else +#define MAP_TimerEnable \ + TimerEnable +#endif +#ifdef ROM_TimerDisable +#define MAP_TimerDisable \ + ROM_TimerDisable +#else +#define MAP_TimerDisable \ + TimerDisable +#endif +#ifdef ROM_TimerConfigure +#define MAP_TimerConfigure \ + ROM_TimerConfigure +#else +#define MAP_TimerConfigure \ + TimerConfigure +#endif +#ifdef ROM_TimerControlLevel +#define MAP_TimerControlLevel \ + ROM_TimerControlLevel +#else +#define MAP_TimerControlLevel \ + TimerControlLevel +#endif +#ifdef ROM_TimerControlTrigger +#define MAP_TimerControlTrigger \ + ROM_TimerControlTrigger +#else +#define MAP_TimerControlTrigger \ + TimerControlTrigger +#endif +#ifdef ROM_TimerControlEvent +#define MAP_TimerControlEvent \ + ROM_TimerControlEvent +#else +#define MAP_TimerControlEvent \ + TimerControlEvent +#endif +#ifdef ROM_TimerControlStall +#define MAP_TimerControlStall \ + ROM_TimerControlStall +#else +#define MAP_TimerControlStall \ + TimerControlStall +#endif +#ifdef ROM_TimerRTCEnable +#define MAP_TimerRTCEnable \ + ROM_TimerRTCEnable +#else +#define MAP_TimerRTCEnable \ + TimerRTCEnable +#endif +#ifdef ROM_TimerRTCDisable +#define MAP_TimerRTCDisable \ + ROM_TimerRTCDisable +#else +#define MAP_TimerRTCDisable \ + TimerRTCDisable +#endif +#ifdef ROM_TimerPrescaleSet +#define MAP_TimerPrescaleSet \ + ROM_TimerPrescaleSet +#else +#define MAP_TimerPrescaleSet \ + TimerPrescaleSet +#endif +#ifdef ROM_TimerPrescaleGet +#define MAP_TimerPrescaleGet \ + ROM_TimerPrescaleGet +#else +#define MAP_TimerPrescaleGet \ + TimerPrescaleGet +#endif +#ifdef ROM_TimerPrescaleMatchSet +#define MAP_TimerPrescaleMatchSet \ + ROM_TimerPrescaleMatchSet +#else +#define MAP_TimerPrescaleMatchSet \ + TimerPrescaleMatchSet +#endif +#ifdef ROM_TimerPrescaleMatchGet +#define MAP_TimerPrescaleMatchGet \ + ROM_TimerPrescaleMatchGet +#else +#define MAP_TimerPrescaleMatchGet \ + TimerPrescaleMatchGet +#endif +#ifdef ROM_TimerLoadSet +#define MAP_TimerLoadSet \ + ROM_TimerLoadSet +#else +#define MAP_TimerLoadSet \ + TimerLoadSet +#endif +#ifdef ROM_TimerLoadGet +#define MAP_TimerLoadGet \ + ROM_TimerLoadGet +#else +#define MAP_TimerLoadGet \ + TimerLoadGet +#endif +#ifdef ROM_TimerValueGet +#define MAP_TimerValueGet \ + ROM_TimerValueGet +#else +#define MAP_TimerValueGet \ + TimerValueGet +#endif +#ifdef ROM_TimerMatchSet +#define MAP_TimerMatchSet \ + ROM_TimerMatchSet +#else +#define MAP_TimerMatchSet \ + TimerMatchSet +#endif +#ifdef ROM_TimerMatchGet +#define MAP_TimerMatchGet \ + ROM_TimerMatchGet +#else +#define MAP_TimerMatchGet \ + TimerMatchGet +#endif +#ifdef ROM_TimerIntEnable +#define MAP_TimerIntEnable \ + ROM_TimerIntEnable +#else +#define MAP_TimerIntEnable \ + TimerIntEnable +#endif +#ifdef ROM_TimerIntDisable +#define MAP_TimerIntDisable \ + ROM_TimerIntDisable +#else +#define MAP_TimerIntDisable \ + TimerIntDisable +#endif +#ifdef ROM_TimerIntStatus +#define MAP_TimerIntStatus \ + ROM_TimerIntStatus +#else +#define MAP_TimerIntStatus \ + TimerIntStatus +#endif +#ifdef ROM_TimerControlWaitOnTrigger +#define MAP_TimerControlWaitOnTrigger \ + ROM_TimerControlWaitOnTrigger +#else +#define MAP_TimerControlWaitOnTrigger \ + TimerControlWaitOnTrigger +#endif +#ifdef ROM_TimerLoadSet64 +#define MAP_TimerLoadSet64 \ + ROM_TimerLoadSet64 +#else +#define MAP_TimerLoadSet64 \ + TimerLoadSet64 +#endif +#ifdef ROM_TimerLoadGet64 +#define MAP_TimerLoadGet64 \ + ROM_TimerLoadGet64 +#else +#define MAP_TimerLoadGet64 \ + TimerLoadGet64 +#endif +#ifdef ROM_TimerValueGet64 +#define MAP_TimerValueGet64 \ + ROM_TimerValueGet64 +#else +#define MAP_TimerValueGet64 \ + TimerValueGet64 +#endif +#ifdef ROM_TimerMatchSet64 +#define MAP_TimerMatchSet64 \ + ROM_TimerMatchSet64 +#else +#define MAP_TimerMatchSet64 \ + TimerMatchSet64 +#endif +#ifdef ROM_TimerMatchGet64 +#define MAP_TimerMatchGet64 \ + ROM_TimerMatchGet64 +#else +#define MAP_TimerMatchGet64 \ + TimerMatchGet64 +#endif + +//***************************************************************************** +// +// Macros for the UART API. +// +//***************************************************************************** +#ifdef ROM_UARTCharPut +#define MAP_UARTCharPut \ + ROM_UARTCharPut +#else +#define MAP_UARTCharPut \ + UARTCharPut +#endif +#ifdef ROM_UARTParityModeSet +#define MAP_UARTParityModeSet \ + ROM_UARTParityModeSet +#else +#define MAP_UARTParityModeSet \ + UARTParityModeSet +#endif +#ifdef ROM_UARTParityModeGet +#define MAP_UARTParityModeGet \ + ROM_UARTParityModeGet +#else +#define MAP_UARTParityModeGet \ + UARTParityModeGet +#endif +#ifdef ROM_UARTFIFOLevelSet +#define MAP_UARTFIFOLevelSet \ + ROM_UARTFIFOLevelSet +#else +#define MAP_UARTFIFOLevelSet \ + UARTFIFOLevelSet +#endif +#ifdef ROM_UARTFIFOLevelGet +#define MAP_UARTFIFOLevelGet \ + ROM_UARTFIFOLevelGet +#else +#define MAP_UARTFIFOLevelGet \ + UARTFIFOLevelGet +#endif +#ifdef ROM_UARTConfigSetExpClk +#define MAP_UARTConfigSetExpClk \ + ROM_UARTConfigSetExpClk +#else +#define MAP_UARTConfigSetExpClk \ + UARTConfigSetExpClk +#endif +#ifdef ROM_UARTConfigGetExpClk +#define MAP_UARTConfigGetExpClk \ + ROM_UARTConfigGetExpClk +#else +#define MAP_UARTConfigGetExpClk \ + UARTConfigGetExpClk +#endif +#ifdef ROM_UARTEnable +#define MAP_UARTEnable \ + ROM_UARTEnable +#else +#define MAP_UARTEnable \ + UARTEnable +#endif +#ifdef ROM_UARTDisable +#define MAP_UARTDisable \ + ROM_UARTDisable +#else +#define MAP_UARTDisable \ + UARTDisable +#endif +#ifdef ROM_UARTEnableSIR +#define MAP_UARTEnableSIR \ + ROM_UARTEnableSIR +#else +#define MAP_UARTEnableSIR \ + UARTEnableSIR +#endif +#ifdef ROM_UARTDisableSIR +#define MAP_UARTDisableSIR \ + ROM_UARTDisableSIR +#else +#define MAP_UARTDisableSIR \ + UARTDisableSIR +#endif +#ifdef ROM_UARTCharsAvail +#define MAP_UARTCharsAvail \ + ROM_UARTCharsAvail +#else +#define MAP_UARTCharsAvail \ + UARTCharsAvail +#endif +#ifdef ROM_UARTSpaceAvail +#define MAP_UARTSpaceAvail \ + ROM_UARTSpaceAvail +#else +#define MAP_UARTSpaceAvail \ + UARTSpaceAvail +#endif +#ifdef ROM_UARTCharGetNonBlocking +#define MAP_UARTCharGetNonBlocking \ + ROM_UARTCharGetNonBlocking +#else +#define MAP_UARTCharGetNonBlocking \ + UARTCharGetNonBlocking +#endif +#ifdef ROM_UARTCharGet +#define MAP_UARTCharGet \ + ROM_UARTCharGet +#else +#define MAP_UARTCharGet \ + UARTCharGet +#endif +#ifdef ROM_UARTCharPutNonBlocking +#define MAP_UARTCharPutNonBlocking \ + ROM_UARTCharPutNonBlocking +#else +#define MAP_UARTCharPutNonBlocking \ + UARTCharPutNonBlocking +#endif +#ifdef ROM_UARTBreakCtl +#define MAP_UARTBreakCtl \ + ROM_UARTBreakCtl +#else +#define MAP_UARTBreakCtl \ + UARTBreakCtl +#endif +#ifdef ROM_UARTIntEnable +#define MAP_UARTIntEnable \ + ROM_UARTIntEnable +#else +#define MAP_UARTIntEnable \ + UARTIntEnable +#endif +#ifdef ROM_UARTIntDisable +#define MAP_UARTIntDisable \ + ROM_UARTIntDisable +#else +#define MAP_UARTIntDisable \ + UARTIntDisable +#endif +#ifdef ROM_UARTIntStatus +#define MAP_UARTIntStatus \ + ROM_UARTIntStatus +#else +#define MAP_UARTIntStatus \ + UARTIntStatus +#endif +#ifdef ROM_UARTIntClear +#define MAP_UARTIntClear \ + ROM_UARTIntClear +#else +#define MAP_UARTIntClear \ + UARTIntClear +#endif +#ifdef ROM_UARTDMAEnable +#define MAP_UARTDMAEnable \ + ROM_UARTDMAEnable +#else +#define MAP_UARTDMAEnable \ + UARTDMAEnable +#endif +#ifdef ROM_UARTDMADisable +#define MAP_UARTDMADisable \ + ROM_UARTDMADisable +#else +#define MAP_UARTDMADisable \ + UARTDMADisable +#endif +#ifdef ROM_UARTFIFOEnable +#define MAP_UARTFIFOEnable \ + ROM_UARTFIFOEnable +#else +#define MAP_UARTFIFOEnable \ + UARTFIFOEnable +#endif +#ifdef ROM_UARTFIFODisable +#define MAP_UARTFIFODisable \ + ROM_UARTFIFODisable +#else +#define MAP_UARTFIFODisable \ + UARTFIFODisable +#endif +#ifdef ROM_UARTBusy +#define MAP_UARTBusy \ + ROM_UARTBusy +#else +#define MAP_UARTBusy \ + UARTBusy +#endif +#ifdef ROM_UARTTxIntModeSet +#define MAP_UARTTxIntModeSet \ + ROM_UARTTxIntModeSet +#else +#define MAP_UARTTxIntModeSet \ + UARTTxIntModeSet +#endif +#ifdef ROM_UARTTxIntModeGet +#define MAP_UARTTxIntModeGet \ + ROM_UARTTxIntModeGet +#else +#define MAP_UARTTxIntModeGet \ + UARTTxIntModeGet +#endif +#ifdef ROM_UARTRxErrorGet +#define MAP_UARTRxErrorGet \ + ROM_UARTRxErrorGet +#else +#define MAP_UARTRxErrorGet \ + UARTRxErrorGet +#endif +#ifdef ROM_UARTRxErrorClear +#define MAP_UARTRxErrorClear \ + ROM_UARTRxErrorClear +#else +#define MAP_UARTRxErrorClear \ + UARTRxErrorClear +#endif +#ifdef ROM_UARTClockSourceSet +#define MAP_UARTClockSourceSet \ + ROM_UARTClockSourceSet +#else +#define MAP_UARTClockSourceSet \ + UARTClockSourceSet +#endif +#ifdef ROM_UARTClockSourceGet +#define MAP_UARTClockSourceGet \ + ROM_UARTClockSourceGet +#else +#define MAP_UARTClockSourceGet \ + UARTClockSourceGet +#endif +#ifdef ROM_UART9BitEnable +#define MAP_UART9BitEnable \ + ROM_UART9BitEnable +#else +#define MAP_UART9BitEnable \ + UART9BitEnable +#endif +#ifdef ROM_UART9BitDisable +#define MAP_UART9BitDisable \ + ROM_UART9BitDisable +#else +#define MAP_UART9BitDisable \ + UART9BitDisable +#endif +#ifdef ROM_UART9BitAddrSet +#define MAP_UART9BitAddrSet \ + ROM_UART9BitAddrSet +#else +#define MAP_UART9BitAddrSet \ + UART9BitAddrSet +#endif +#ifdef ROM_UART9BitAddrSend +#define MAP_UART9BitAddrSend \ + ROM_UART9BitAddrSend +#else +#define MAP_UART9BitAddrSend \ + UART9BitAddrSend +#endif + +//***************************************************************************** +// +// Macros for the uDMA API. +// +//***************************************************************************** +#ifdef ROM_uDMAChannelTransferSet +#define MAP_uDMAChannelTransferSet \ + ROM_uDMAChannelTransferSet +#else +#define MAP_uDMAChannelTransferSet \ + uDMAChannelTransferSet +#endif +#ifdef ROM_uDMAEnable +#define MAP_uDMAEnable \ + ROM_uDMAEnable +#else +#define MAP_uDMAEnable \ + uDMAEnable +#endif +#ifdef ROM_uDMADisable +#define MAP_uDMADisable \ + ROM_uDMADisable +#else +#define MAP_uDMADisable \ + uDMADisable +#endif +#ifdef ROM_uDMAErrorStatusGet +#define MAP_uDMAErrorStatusGet \ + ROM_uDMAErrorStatusGet +#else +#define MAP_uDMAErrorStatusGet \ + uDMAErrorStatusGet +#endif +#ifdef ROM_uDMAErrorStatusClear +#define MAP_uDMAErrorStatusClear \ + ROM_uDMAErrorStatusClear +#else +#define MAP_uDMAErrorStatusClear \ + uDMAErrorStatusClear +#endif +#ifdef ROM_uDMAChannelEnable +#define MAP_uDMAChannelEnable \ + ROM_uDMAChannelEnable +#else +#define MAP_uDMAChannelEnable \ + uDMAChannelEnable +#endif +#ifdef ROM_uDMAChannelDisable +#define MAP_uDMAChannelDisable \ + ROM_uDMAChannelDisable +#else +#define MAP_uDMAChannelDisable \ + uDMAChannelDisable +#endif +#ifdef ROM_uDMAChannelIsEnabled +#define MAP_uDMAChannelIsEnabled \ + ROM_uDMAChannelIsEnabled +#else +#define MAP_uDMAChannelIsEnabled \ + uDMAChannelIsEnabled +#endif +#ifdef ROM_uDMAControlBaseSet +#define MAP_uDMAControlBaseSet \ + ROM_uDMAControlBaseSet +#else +#define MAP_uDMAControlBaseSet \ + uDMAControlBaseSet +#endif +#ifdef ROM_uDMAControlBaseGet +#define MAP_uDMAControlBaseGet \ + ROM_uDMAControlBaseGet +#else +#define MAP_uDMAControlBaseGet \ + uDMAControlBaseGet +#endif +#ifdef ROM_uDMAChannelRequest +#define MAP_uDMAChannelRequest \ + ROM_uDMAChannelRequest +#else +#define MAP_uDMAChannelRequest \ + uDMAChannelRequest +#endif +#ifdef ROM_uDMAChannelAttributeEnable +#define MAP_uDMAChannelAttributeEnable \ + ROM_uDMAChannelAttributeEnable +#else +#define MAP_uDMAChannelAttributeEnable \ + uDMAChannelAttributeEnable +#endif +#ifdef ROM_uDMAChannelAttributeDisable +#define MAP_uDMAChannelAttributeDisable \ + ROM_uDMAChannelAttributeDisable +#else +#define MAP_uDMAChannelAttributeDisable \ + uDMAChannelAttributeDisable +#endif +#ifdef ROM_uDMAChannelAttributeGet +#define MAP_uDMAChannelAttributeGet \ + ROM_uDMAChannelAttributeGet +#else +#define MAP_uDMAChannelAttributeGet \ + uDMAChannelAttributeGet +#endif +#ifdef ROM_uDMAChannelControlSet +#define MAP_uDMAChannelControlSet \ + ROM_uDMAChannelControlSet +#else +#define MAP_uDMAChannelControlSet \ + uDMAChannelControlSet +#endif +#ifdef ROM_uDMAChannelSizeGet +#define MAP_uDMAChannelSizeGet \ + ROM_uDMAChannelSizeGet +#else +#define MAP_uDMAChannelSizeGet \ + uDMAChannelSizeGet +#endif +#ifdef ROM_uDMAChannelModeGet +#define MAP_uDMAChannelModeGet \ + ROM_uDMAChannelModeGet +#else +#define MAP_uDMAChannelModeGet \ + uDMAChannelModeGet +#endif +#ifdef ROM_uDMAChannelSelectSecondary +#define MAP_uDMAChannelSelectSecondary \ + ROM_uDMAChannelSelectSecondary +#else +#define MAP_uDMAChannelSelectSecondary \ + uDMAChannelSelectSecondary +#endif +#ifdef ROM_uDMAChannelSelectDefault +#define MAP_uDMAChannelSelectDefault \ + ROM_uDMAChannelSelectDefault +#else +#define MAP_uDMAChannelSelectDefault \ + uDMAChannelSelectDefault +#endif +#ifdef ROM_uDMAIntStatus +#define MAP_uDMAIntStatus \ + ROM_uDMAIntStatus +#else +#define MAP_uDMAIntStatus \ + uDMAIntStatus +#endif +#ifdef ROM_uDMAIntClear +#define MAP_uDMAIntClear \ + ROM_uDMAIntClear +#else +#define MAP_uDMAIntClear \ + uDMAIntClear +#endif +#ifdef ROM_uDMAControlAlternateBaseGet +#define MAP_uDMAControlAlternateBaseGet \ + ROM_uDMAControlAlternateBaseGet +#else +#define MAP_uDMAControlAlternateBaseGet \ + uDMAControlAlternateBaseGet +#endif +#ifdef ROM_uDMAChannelScatterGatherSet +#define MAP_uDMAChannelScatterGatherSet \ + ROM_uDMAChannelScatterGatherSet +#else +#define MAP_uDMAChannelScatterGatherSet \ + uDMAChannelScatterGatherSet +#endif +#ifdef ROM_uDMAChannelAssign +#define MAP_uDMAChannelAssign \ + ROM_uDMAChannelAssign +#else +#define MAP_uDMAChannelAssign \ + uDMAChannelAssign +#endif + +//***************************************************************************** +// +// Macros for the USB API. +// +//***************************************************************************** +#ifdef ROM_USBIntStatus +#define MAP_USBIntStatus \ + ROM_USBIntStatus +#else +#define MAP_USBIntStatus \ + USBIntStatus +#endif +#ifdef ROM_USBDevAddrGet +#define MAP_USBDevAddrGet \ + ROM_USBDevAddrGet +#else +#define MAP_USBDevAddrGet \ + USBDevAddrGet +#endif +#ifdef ROM_USBDevAddrSet +#define MAP_USBDevAddrSet \ + ROM_USBDevAddrSet +#else +#define MAP_USBDevAddrSet \ + USBDevAddrSet +#endif +#ifdef ROM_USBDevConnect +#define MAP_USBDevConnect \ + ROM_USBDevConnect +#else +#define MAP_USBDevConnect \ + USBDevConnect +#endif +#ifdef ROM_USBDevDisconnect +#define MAP_USBDevDisconnect \ + ROM_USBDevDisconnect +#else +#define MAP_USBDevDisconnect \ + USBDevDisconnect +#endif +#ifdef ROM_USBDevEndpointConfigSet +#define MAP_USBDevEndpointConfigSet \ + ROM_USBDevEndpointConfigSet +#else +#define MAP_USBDevEndpointConfigSet \ + USBDevEndpointConfigSet +#endif +#ifdef ROM_USBDevEndpointDataAck +#define MAP_USBDevEndpointDataAck \ + ROM_USBDevEndpointDataAck +#else +#define MAP_USBDevEndpointDataAck \ + USBDevEndpointDataAck +#endif +#ifdef ROM_USBDevEndpointStall +#define MAP_USBDevEndpointStall \ + ROM_USBDevEndpointStall +#else +#define MAP_USBDevEndpointStall \ + USBDevEndpointStall +#endif +#ifdef ROM_USBDevEndpointStallClear +#define MAP_USBDevEndpointStallClear \ + ROM_USBDevEndpointStallClear +#else +#define MAP_USBDevEndpointStallClear \ + USBDevEndpointStallClear +#endif +#ifdef ROM_USBDevEndpointStatusClear +#define MAP_USBDevEndpointStatusClear \ + ROM_USBDevEndpointStatusClear +#else +#define MAP_USBDevEndpointStatusClear \ + USBDevEndpointStatusClear +#endif +#ifdef ROM_USBEndpointDataGet +#define MAP_USBEndpointDataGet \ + ROM_USBEndpointDataGet +#else +#define MAP_USBEndpointDataGet \ + USBEndpointDataGet +#endif +#ifdef ROM_USBEndpointDataPut +#define MAP_USBEndpointDataPut \ + ROM_USBEndpointDataPut +#else +#define MAP_USBEndpointDataPut \ + USBEndpointDataPut +#endif +#ifdef ROM_USBEndpointDataSend +#define MAP_USBEndpointDataSend \ + ROM_USBEndpointDataSend +#else +#define MAP_USBEndpointDataSend \ + USBEndpointDataSend +#endif +#ifdef ROM_USBEndpointDataToggleClear +#define MAP_USBEndpointDataToggleClear \ + ROM_USBEndpointDataToggleClear +#else +#define MAP_USBEndpointDataToggleClear \ + USBEndpointDataToggleClear +#endif +#ifdef ROM_USBEndpointStatus +#define MAP_USBEndpointStatus \ + ROM_USBEndpointStatus +#else +#define MAP_USBEndpointStatus \ + USBEndpointStatus +#endif +#ifdef ROM_USBFIFOAddrGet +#define MAP_USBFIFOAddrGet \ + ROM_USBFIFOAddrGet +#else +#define MAP_USBFIFOAddrGet \ + USBFIFOAddrGet +#endif +#ifdef ROM_USBFIFOConfigGet +#define MAP_USBFIFOConfigGet \ + ROM_USBFIFOConfigGet +#else +#define MAP_USBFIFOConfigGet \ + USBFIFOConfigGet +#endif +#ifdef ROM_USBFIFOConfigSet +#define MAP_USBFIFOConfigSet \ + ROM_USBFIFOConfigSet +#else +#define MAP_USBFIFOConfigSet \ + USBFIFOConfigSet +#endif +#ifdef ROM_USBFIFOFlush +#define MAP_USBFIFOFlush \ + ROM_USBFIFOFlush +#else +#define MAP_USBFIFOFlush \ + USBFIFOFlush +#endif +#ifdef ROM_USBFrameNumberGet +#define MAP_USBFrameNumberGet \ + ROM_USBFrameNumberGet +#else +#define MAP_USBFrameNumberGet \ + USBFrameNumberGet +#endif +#ifdef ROM_USBHostAddrGet +#define MAP_USBHostAddrGet \ + ROM_USBHostAddrGet +#else +#define MAP_USBHostAddrGet \ + USBHostAddrGet +#endif +#ifdef ROM_USBHostAddrSet +#define MAP_USBHostAddrSet \ + ROM_USBHostAddrSet +#else +#define MAP_USBHostAddrSet \ + USBHostAddrSet +#endif +#ifdef ROM_USBHostEndpointConfig +#define MAP_USBHostEndpointConfig \ + ROM_USBHostEndpointConfig +#else +#define MAP_USBHostEndpointConfig \ + USBHostEndpointConfig +#endif +#ifdef ROM_USBHostEndpointDataAck +#define MAP_USBHostEndpointDataAck \ + ROM_USBHostEndpointDataAck +#else +#define MAP_USBHostEndpointDataAck \ + USBHostEndpointDataAck +#endif +#ifdef ROM_USBHostEndpointDataToggle +#define MAP_USBHostEndpointDataToggle \ + ROM_USBHostEndpointDataToggle +#else +#define MAP_USBHostEndpointDataToggle \ + USBHostEndpointDataToggle +#endif +#ifdef ROM_USBHostEndpointStatusClear +#define MAP_USBHostEndpointStatusClear \ + ROM_USBHostEndpointStatusClear +#else +#define MAP_USBHostEndpointStatusClear \ + USBHostEndpointStatusClear +#endif +#ifdef ROM_USBHostHubAddrGet +#define MAP_USBHostHubAddrGet \ + ROM_USBHostHubAddrGet +#else +#define MAP_USBHostHubAddrGet \ + USBHostHubAddrGet +#endif +#ifdef ROM_USBHostHubAddrSet +#define MAP_USBHostHubAddrSet \ + ROM_USBHostHubAddrSet +#else +#define MAP_USBHostHubAddrSet \ + USBHostHubAddrSet +#endif +#ifdef ROM_USBHostPwrDisable +#define MAP_USBHostPwrDisable \ + ROM_USBHostPwrDisable +#else +#define MAP_USBHostPwrDisable \ + USBHostPwrDisable +#endif +#ifdef ROM_USBHostPwrEnable +#define MAP_USBHostPwrEnable \ + ROM_USBHostPwrEnable +#else +#define MAP_USBHostPwrEnable \ + USBHostPwrEnable +#endif +#ifdef ROM_USBHostPwrConfig +#define MAP_USBHostPwrConfig \ + ROM_USBHostPwrConfig +#else +#define MAP_USBHostPwrConfig \ + USBHostPwrConfig +#endif +#ifdef ROM_USBHostPwrFaultDisable +#define MAP_USBHostPwrFaultDisable \ + ROM_USBHostPwrFaultDisable +#else +#define MAP_USBHostPwrFaultDisable \ + USBHostPwrFaultDisable +#endif +#ifdef ROM_USBHostPwrFaultEnable +#define MAP_USBHostPwrFaultEnable \ + ROM_USBHostPwrFaultEnable +#else +#define MAP_USBHostPwrFaultEnable \ + USBHostPwrFaultEnable +#endif +#ifdef ROM_USBHostRequestIN +#define MAP_USBHostRequestIN \ + ROM_USBHostRequestIN +#else +#define MAP_USBHostRequestIN \ + USBHostRequestIN +#endif +#ifdef ROM_USBHostRequestStatus +#define MAP_USBHostRequestStatus \ + ROM_USBHostRequestStatus +#else +#define MAP_USBHostRequestStatus \ + USBHostRequestStatus +#endif +#ifdef ROM_USBHostReset +#define MAP_USBHostReset \ + ROM_USBHostReset +#else +#define MAP_USBHostReset \ + USBHostReset +#endif +#ifdef ROM_USBHostResume +#define MAP_USBHostResume \ + ROM_USBHostResume +#else +#define MAP_USBHostResume \ + USBHostResume +#endif +#ifdef ROM_USBHostSpeedGet +#define MAP_USBHostSpeedGet \ + ROM_USBHostSpeedGet +#else +#define MAP_USBHostSpeedGet \ + USBHostSpeedGet +#endif +#ifdef ROM_USBHostSuspend +#define MAP_USBHostSuspend \ + ROM_USBHostSuspend +#else +#define MAP_USBHostSuspend \ + USBHostSuspend +#endif +#ifdef ROM_USBIntDisable +#define MAP_USBIntDisable \ + ROM_USBIntDisable +#else +#define MAP_USBIntDisable \ + USBIntDisable +#endif +#ifdef ROM_USBIntEnable +#define MAP_USBIntEnable \ + ROM_USBIntEnable +#else +#define MAP_USBIntEnable \ + USBIntEnable +#endif +#ifdef ROM_USBDevEndpointConfigGet +#define MAP_USBDevEndpointConfigGet \ + ROM_USBDevEndpointConfigGet +#else +#define MAP_USBDevEndpointConfigGet \ + USBDevEndpointConfigGet +#endif +#ifdef ROM_USBEndpointDMAEnable +#define MAP_USBEndpointDMAEnable \ + ROM_USBEndpointDMAEnable +#else +#define MAP_USBEndpointDMAEnable \ + USBEndpointDMAEnable +#endif +#ifdef ROM_USBEndpointDMADisable +#define MAP_USBEndpointDMADisable \ + ROM_USBEndpointDMADisable +#else +#define MAP_USBEndpointDMADisable \ + USBEndpointDMADisable +#endif +#ifdef ROM_USBEndpointDataAvail +#define MAP_USBEndpointDataAvail \ + ROM_USBEndpointDataAvail +#else +#define MAP_USBEndpointDataAvail \ + USBEndpointDataAvail +#endif +#ifdef ROM_USBOTGHostRequest +#define MAP_USBOTGHostRequest \ + ROM_USBOTGHostRequest +#else +#define MAP_USBOTGHostRequest \ + USBOTGHostRequest +#endif +#ifdef ROM_USBModeGet +#define MAP_USBModeGet \ + ROM_USBModeGet +#else +#define MAP_USBModeGet \ + USBModeGet +#endif +#ifdef ROM_USBEndpointDMAChannel +#define MAP_USBEndpointDMAChannel \ + ROM_USBEndpointDMAChannel +#else +#define MAP_USBEndpointDMAChannel \ + USBEndpointDMAChannel +#endif +#ifdef ROM_USBIntDisableControl +#define MAP_USBIntDisableControl \ + ROM_USBIntDisableControl +#else +#define MAP_USBIntDisableControl \ + USBIntDisableControl +#endif +#ifdef ROM_USBIntEnableControl +#define MAP_USBIntEnableControl \ + ROM_USBIntEnableControl +#else +#define MAP_USBIntEnableControl \ + USBIntEnableControl +#endif +#ifdef ROM_USBIntStatusControl +#define MAP_USBIntStatusControl \ + ROM_USBIntStatusControl +#else +#define MAP_USBIntStatusControl \ + USBIntStatusControl +#endif +#ifdef ROM_USBIntStatus +#define MAP_USBIntStatus \ + ROM_USBIntStatus +#else +#define MAP_USBIntStatus \ + USBIntStatus +#endif +#ifdef ROM_USBIntDisableEndpoint +#define MAP_USBIntDisableEndpoint \ + ROM_USBIntDisableEndpoint +#else +#define MAP_USBIntDisableEndpoint \ + USBIntDisableEndpoint +#endif +#ifdef ROM_USBIntEnableEndpoint +#define MAP_USBIntEnableEndpoint \ + ROM_USBIntEnableEndpoint +#else +#define MAP_USBIntEnableEndpoint \ + USBIntEnableEndpoint +#endif +#ifdef ROM_USBIntStatusEndpoint +#define MAP_USBIntStatusEndpoint \ + ROM_USBIntStatusEndpoint +#else +#define MAP_USBIntStatusEndpoint \ + USBIntStatusEndpoint +#endif +#ifdef ROM_USBHostMode +#define MAP_USBHostMode \ + ROM_USBHostMode +#else +#define MAP_USBHostMode \ + USBHostMode +#endif +#ifdef ROM_USBDevMode +#define MAP_USBDevMode \ + ROM_USBDevMode +#else +#define MAP_USBDevMode \ + USBDevMode +#endif +#ifdef ROM_USBPHYPowerOff +#define MAP_USBPHYPowerOff \ + ROM_USBPHYPowerOff +#else +#define MAP_USBPHYPowerOff \ + USBPHYPowerOff +#endif +#ifdef ROM_USBPHYPowerOn +#define MAP_USBPHYPowerOn \ + ROM_USBPHYPowerOn +#else +#define MAP_USBPHYPowerOn \ + USBPHYPowerOn +#endif +#ifdef ROM_USBOTGMode +#define MAP_USBOTGMode \ + ROM_USBOTGMode +#else +#define MAP_USBOTGMode \ + USBOTGMode +#endif + +//***************************************************************************** +// +// Macros for the Watchdog API. +// +//***************************************************************************** +#ifdef ROM_WatchdogIntClear +#define MAP_WatchdogIntClear \ + ROM_WatchdogIntClear +#else +#define MAP_WatchdogIntClear \ + WatchdogIntClear +#endif +#ifdef ROM_WatchdogRunning +#define MAP_WatchdogRunning \ + ROM_WatchdogRunning +#else +#define MAP_WatchdogRunning \ + WatchdogRunning +#endif +#ifdef ROM_WatchdogEnable +#define MAP_WatchdogEnable \ + ROM_WatchdogEnable +#else +#define MAP_WatchdogEnable \ + WatchdogEnable +#endif +#ifdef ROM_WatchdogResetEnable +#define MAP_WatchdogResetEnable \ + ROM_WatchdogResetEnable +#else +#define MAP_WatchdogResetEnable \ + WatchdogResetEnable +#endif +#ifdef ROM_WatchdogResetDisable +#define MAP_WatchdogResetDisable \ + ROM_WatchdogResetDisable +#else +#define MAP_WatchdogResetDisable \ + WatchdogResetDisable +#endif +#ifdef ROM_WatchdogLock +#define MAP_WatchdogLock \ + ROM_WatchdogLock +#else +#define MAP_WatchdogLock \ + WatchdogLock +#endif +#ifdef ROM_WatchdogUnlock +#define MAP_WatchdogUnlock \ + ROM_WatchdogUnlock +#else +#define MAP_WatchdogUnlock \ + WatchdogUnlock +#endif +#ifdef ROM_WatchdogLockState +#define MAP_WatchdogLockState \ + ROM_WatchdogLockState +#else +#define MAP_WatchdogLockState \ + WatchdogLockState +#endif +#ifdef ROM_WatchdogReloadSet +#define MAP_WatchdogReloadSet \ + ROM_WatchdogReloadSet +#else +#define MAP_WatchdogReloadSet \ + WatchdogReloadSet +#endif +#ifdef ROM_WatchdogReloadGet +#define MAP_WatchdogReloadGet \ + ROM_WatchdogReloadGet +#else +#define MAP_WatchdogReloadGet \ + WatchdogReloadGet +#endif +#ifdef ROM_WatchdogValueGet +#define MAP_WatchdogValueGet \ + ROM_WatchdogValueGet +#else +#define MAP_WatchdogValueGet \ + WatchdogValueGet +#endif +#ifdef ROM_WatchdogIntEnable +#define MAP_WatchdogIntEnable \ + ROM_WatchdogIntEnable +#else +#define MAP_WatchdogIntEnable \ + WatchdogIntEnable +#endif +#ifdef ROM_WatchdogIntStatus +#define MAP_WatchdogIntStatus \ + ROM_WatchdogIntStatus +#else +#define MAP_WatchdogIntStatus \ + WatchdogIntStatus +#endif +#ifdef ROM_WatchdogStallEnable +#define MAP_WatchdogStallEnable \ + ROM_WatchdogStallEnable +#else +#define MAP_WatchdogStallEnable \ + WatchdogStallEnable +#endif +#ifdef ROM_WatchdogStallDisable +#define MAP_WatchdogStallDisable \ + ROM_WatchdogStallDisable +#else +#define MAP_WatchdogStallDisable \ + WatchdogStallDisable +#endif +#ifdef ROM_WatchdogIntTypeSet +#define MAP_WatchdogIntTypeSet \ + ROM_WatchdogIntTypeSet +#else +#define MAP_WatchdogIntTypeSet \ + WatchdogIntTypeSet +#endif + +//***************************************************************************** +// +// Macros for the Software API. +// +//***************************************************************************** +#ifdef ROM_Crc16Array +#define MAP_Crc16Array \ + ROM_Crc16Array +#else +#define MAP_Crc16Array \ + Crc16Array +#endif +#ifdef ROM_Crc16Array3 +#define MAP_Crc16Array3 \ + ROM_Crc16Array3 +#else +#define MAP_Crc16Array3 \ + Crc16Array3 +#endif +#ifdef ROM_Crc16 +#define MAP_Crc16 \ + ROM_Crc16 +#else +#define MAP_Crc16 \ + Crc16 +#endif +#ifdef ROM_Crc8CCITT +#define MAP_Crc8CCITT \ + ROM_Crc8CCITT +#else +#define MAP_Crc8CCITT \ + Crc8CCITT +#endif + +#endif // __ROM_MAP_H__ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rtos_bindings.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rtos_bindings.h new file mode 100644 index 00000000000..9c3df5da882 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/rtos_bindings.h @@ -0,0 +1,107 @@ +//***************************************************************************** +// +// rtos_bindings.h - Macros ulIntIDended to aid porting of StellarisWare modules +// for use with an RTOS. +// +// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** +#ifndef RTOS_BINDINGS_H_ +#define RTOS_BINDINGS_H_ + +#ifdef USE_RTOS +//***************************************************************************** +// +// If an RTOS is in use, implement a header file called "stellaris_rtos.h" +// which contains RTOS-specific versions of each of the macros defined below +// and make sure it appears on the include path set when you build your +// project. +// +// Note that there is no default implementation of this header file included +// in StellarisWare - it is your responsibility to create it specifically for +// your RTOS. +// +//***************************************************************************** +#include "stellaris_rtos.h" + +#else +//***************************************************************************** +// +// When no RTOS is in use, the follow macros compile to either nothing or a +// minimal implementation that works in a bare-metal environment. +// +// Each of these macros must be redefined in stellaris_rtos.h if you are using +// StellarisWare under an RTOS. +// +//***************************************************************************** + +//***************************************************************************** +// +// A simple macro used to yield within polling loops. In the default, non-RTOS +// implementation, this compiles to nothing. +// +//***************************************************************************** +#define OS_YIELD() + +//***************************************************************************** +// +// A simple macro around the SysCtlDelay function. The parameter is the number +// of 3 cycle loops to wait before returning (as for SysCtlDelay). In an RTOS +// implementation, this could be replaced with an OS delay call with +// appropriate parameter scaling. +// +//***************************************************************************** +#define OS_DELAY(ul3Cycles) MAP_SysCtlDelay(ul3Cycles) + +//***************************************************************************** +// +// Wrappers around low level interrupt control functions. For information +// on each of these functions, please see the appropriate API documentation +// for the DriverLib Interrupt driver. +// +// The macros defined here represent interrupt-control functions that may be +// called from within StellarisWare code. It is expected that application +// code will use RTOS-specific functions to control interrupt priority, to +// pend interrupts and to perform runtime vector manipulation. As a result, +// no macros are defined to wrap any of these functions from interrupt.c. +// +//***************************************************************************** +#define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable() +#define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable() +#define OS_INT_DISABLE(ulIntID) MAP_IntDisable(ulIntID) +#define OS_INT_ENABLE(ulIntID) MAP_IntEnable(ulIntID) + +#endif // USE_RTOS + +#endif // RTOS_BINDINGS_H_ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.c new file mode 100644 index 00000000000..00fbd65ad40 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.c @@ -0,0 +1,841 @@ +//########################################################################### +// +// FILE: sysctl.c +// +// TITLE: Stellaris style wrapper driver for F2837x system control. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** + +#include "F28x_Project.h" +#include +#include +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/sysctl.h" + +//***************************************************************************** +// +//! \internal +//! Checks a peripheral identifier. +//! +//! \param ui32Peripheral is the peripheral identifier. +//! +//! This function determines if a peripheral identifier is valid. +//! +//! \return Returns \b true if the peripheral identifier is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +_SysCtlPeripheralValid(uint32_t ui32Peripheral) +{ + return((ui32Peripheral == SYSCTL_PERIPH_CLA1) || + (ui32Peripheral == SYSCTL_PERIPH_DMA) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER0) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER1) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER2) || + (ui32Peripheral == SYSCTL_PERIPH_HRPWM) || + (ui32Peripheral == SYSCTL_PERIPH_TBCLKSYNC) || + (ui32Peripheral == SYSCTL_PERIPH_GTBCLKSYNC) || + (ui32Peripheral == SYSCTL_PERIPH_EMIF1) || + (ui32Peripheral == SYSCTL_PERIPH_EMIF2) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM1) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM2) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM3) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM4) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM5) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM6) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM7) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM8) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM9) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM10) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM11) || + (ui32Peripheral == SYSCTL_PERIPH_EPWM12) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP1) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP2) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP3) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP4) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP5) || + (ui32Peripheral == SYSCTL_PERIPH_ECAP6) || + (ui32Peripheral == SYSCTL_PERIPH_EQEP1) || + (ui32Peripheral == SYSCTL_PERIPH_EQEP2) || + (ui32Peripheral == SYSCTL_PERIPH_EQEP3) || + (ui32Peripheral == SYSCTL_PERIPH_SD1) || + (ui32Peripheral == SYSCTL_PERIPH_SD2) || + (ui32Peripheral == SYSCTL_PERIPH_SCI1) || + (ui32Peripheral == SYSCTL_PERIPH_SCI2) || + (ui32Peripheral == SYSCTL_PERIPH_SCI3) || + (ui32Peripheral == SYSCTL_PERIPH_SCI4) || + (ui32Peripheral == SYSCTL_PERIPH_SPI1) || + (ui32Peripheral == SYSCTL_PERIPH_SPI2) || + (ui32Peripheral == SYSCTL_PERIPH_SPI3) || + (ui32Peripheral == SYSCTL_PERIPH_I2C1) || + (ui32Peripheral == SYSCTL_PERIPH_I2C2) || + (ui32Peripheral == SYSCTL_PERIPH_CAN1) || + (ui32Peripheral == SYSCTL_PERIPH_CAN2) || + (ui32Peripheral == SYSCTL_PERIPH_MCBSP1) || + (ui32Peripheral == SYSCTL_PERIPH_MCBSP2) || + (ui32Peripheral == SYSCTL_PERIPH_UPP1) || + (ui32Peripheral == SYSCTL_PERIPH_ADC1) || + (ui32Peripheral == SYSCTL_PERIPH_ADC2) || + (ui32Peripheral == SYSCTL_PERIPH_ADC3) || + (ui32Peripheral == SYSCTL_PERIPH_ADC4) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS1) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS2) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS3) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS4) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS5) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS6) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS7) || + (ui32Peripheral == SYSCTL_PERIPH_CMPSS8) || + (ui32Peripheral == SYSCTL_PERIPH_BUFFDAC1) || + (ui32Peripheral == SYSCTL_PERIPH_BUFFDAC2) || + (ui32Peripheral == SYSCTL_PERIPH_BUFFDAC3)); +} +#endif + + + +//***************************************************************************** +// +//! Determines if a peripheral is present. +//! +//! \param ui32Peripheral is the peripheral in question. +//! +//! This function determines if a particular peripheral is present in the +//! device. Each member of the family has a different peripheral +//! set; this function determines which peripherals are present on this device. +//! +//! \return Returns \b true if the specified peripheral is present and \b false +//! if it is not. +// +//***************************************************************************** +bool +SysCtlPeripheralPresent(uint32_t ui32Peripheral) +{ + + uint16_t regIndex; + uint16_t bitIndex; + + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + + regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M; + bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S; + + if(HWREG(&(DevCfgRegs.DC0.all) + (2 * regIndex)) & (1 << bitIndex)){ + return true; + }else{ + return false; + } + + +} + +//***************************************************************************** +// +//! Determines if a peripheral is ready. +//! +//! \param ui32Peripheral is the peripheral in question. +//! +//! This function determines if a particular peripheral is ready to be +//! accessed. The peripheral may be in a non-ready state if it is not enabled, +//! is being held in reset, or is in the process of becoming ready after being +//! enabled or taken out of reset. +//! +//! \note The ability to check for a peripheral being ready varies based on the +//! part in use. Please consult the data sheet for the part you are +//! using to determine if this feature is available. +//! +//! \return Returns \b true if the specified peripheral is ready and \b false +//! if it is not. +// +//***************************************************************************** +bool +SysCtlPeripheralReady(uint32_t ui32Peripheral) +{ + + uint16_t regIndex; + uint16_t bitIndex; + + // + // Check the arguments. + // + ASSERT(_SysCtlPeripheralValid(ui32Peripheral)); + + + regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M; + bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S; + + // Is the peripheral there? + if(HWREG((uint32_t)&(DevCfgRegs.DC0.all) + (2 * regIndex)) & ((uint32_t)1 << bitIndex)){ + // Is the peripheral enabled? + if(HWREG((uint32_t)&(CpuSysRegs.PCLKCR0.all) + (2 * regIndex)) & ((uint32_t)1 << bitIndex)){ + // Is the peripheral in reset? + if((HWREG((uint32_t)&(DevCfgRegs.SOFTPRES0.all) + (2 * regIndex)) & ((uint32_t)1 << bitIndex)) == 0){ + // No? Ok cool + return true; + } + } + }else{ + return false; + } + + return false; +} +//***************************************************************************** +// +//! Resets a peripheral +//! +//! \param ui32Peripheral is the peripheral to reset. +//! +//! The f2837x devices do not have a means of resetting peripherals via +//! via software. This is a dummy function that does nothing. +//! +//! +//! \return None. +// +//***************************************************************************** +void SysCtlPeripheralReset(uint32_t ui32Peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M; + bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S; + + EALLOW; + + HWREG((uint32_t)&(DevCfgRegs.SOFTPRES0.all) + (2 * regIndex)) |= ((uint32_t)1 << bitIndex); + asm(" nop"); + asm(" nop"); + asm(" nop"); + asm(" nop"); + HWREG((uint32_t)&(DevCfgRegs.SOFTPRES0.all) + (2 * regIndex)) &= ~((uint32_t)1 << bitIndex); + EDIS; +} + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param ui32Peripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_UART_A, \b SYSCTL_PERIPH_UART_B, \b SYSCTL_PERIPH_UART_C, +//! \b SYSCTL_PERIPH_UART_D, \b SYSCTL_PERIPH_SPI_A, \b SYSCTL_PERIPH_SPI_B, +//! \b SYSCTL_PERIPH_SPI_C, \b SYSCTL_PERIPH_MCBSP_A, \b SYSCTL_PERIPH_MCBSP_B, +//! \b SYSCTL_PERIPH_DMA, \b SYSCTL_PERIPH_USB_A +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralEnable(uint32_t ui32Peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + volatile uint32_t test1, test2, test3, test4; + + regIndex = (ui32Peripheral & SYSCTL_PERIPH_REG_M); + bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S; + + EALLOW; + HWREG((uint32_t)&(CpuSysRegs.PCLKCR0.all) + (2 * regIndex)) |= ((uint32_t)1 << bitIndex); + + EDIS; +} + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param ui32Peripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! The \e ui32Peripheral parameter must be only one of the following values: +//! \b SYSCTL_PERIPH_UART_A, \b SYSCTL_PERIPH_UART_B, \b SYSCTL_PERIPH_UART_C, +//! \b SYSCTL_PERIPH_UART_D, \b SYSCTL_PERIPH_SPI_A, \b SYSCTL_PERIPH_SPI_B, +//! \b SYSCTL_PERIPH_SPI_C, \b SYSCTL_PERIPH_MCBSP_A, \b SYSCTL_PERIPH_MCBSP_B, +//! \b SYSCTL_PERIPH_DMA, \b SYSCTL_PERIPH_USB_A +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlPeripheralDisable(uint32_t ui32Peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + regIndex = ui32Peripheral & SYSCTL_PERIPH_REG_M; + bitIndex = (ui32Peripheral & SYSCTL_PERIPH_BIT_M) >> SYSCTL_PERIPH_BIT_S; + + EALLOW; + + HWREG((uint32_t)&(CpuSysRegs.PCLKCR0.all) + (2 * regIndex)) &= ~((uint32_t)1 << bitIndex); + + EDIS; +} + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function performs a software reset of the entire device. The +//! processor and all peripherals are reset and all device registers are +//! returned to their default values (with the exception of the reset cause +//! register, which maintains its current value but has the software reset +//! bit set as well). +//! +//! \return This function does not return. +// +//***************************************************************************** +void +SysCtlReset(void) +{ + // + // Write an incorrect check value to the watchdog control register + // This will cause a device reset + // + EALLOW; + // Enable the watchdog + HWREG(&(WdRegs.WDCR.all)) = 0x0028; + // Write a bad check value + HWREG(&(WdRegs.WDCR.all)) = 0xFFFF; + EDIS; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while(1) + { + } +} + + +//***************************************************************************** +// +//! Provides a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! This function provides a means of generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! The loop takes 5 cycles/loop + 9. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + __asm(" .def _SysCtlDelay\n" + " .sect \".TI.ramfunc\"\n" + " .global _SysCtlDelay\n" + "_SysCtlDelay:\n" + " SUB ACC,#1\n" + " BF _SysCtlDelay,GEQ\n" + " LRETR\n"); + #else + __asm(" .def _SysCtlDelay\n" + " .sect \"ramfuncs\"\n" + " .global _SysCtlDelay\n" + "_SysCtlDelay:\n" + " SUB ACC,#1\n" + " BF _SysCtlDelay,GEQ\n" + " LRETR\n"); + #endif +#endif + +//***************************************************************************** +// +//! Gets the processor clock rate. +//! +//! This function determines the clock rate of the processor clock. +//! +//! \note Because of the many different clocking options available, this +//! function cannot determine the clock speed of the processor. This function +//! should be modified to return the actual clock speed of the processor in +//! your specific application. +//! +//! \return The processor clock rate. +// +//***************************************************************************** +uint32_t +SysCtlClockGet(uint32_t u32ClockIn) +{ + + if((ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 0) || + (ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL == 2)){ + //10MHz Internal Clock + u32ClockIn = 10000000; + } + + //If the pll is enabled calculate its effect on the clock +// if((HWREG(SYSCTL_SYSPLLCTL) & +// (SYSCTL_SYSPLLCTL_SPLLEN | SYSCTL_SYSPLLCTL_SPLLCLKEN)) == 3) + if(ClkCfgRegs.SYSPLLCTL1.bit.PLLEN && ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN) + { + //Calculate integer multiplier and fixed divide by 2 +// ulClockIn = ulClockIn * +// (HWREG(SYSCTL_SYSPLLMULT) & SYSCTL_SYSPLLMULT_SPLLIMULT_M); + u32ClockIn = u32ClockIn * ClkCfgRegs.SYSPLLMULT.bit.IMULT; + + + //Calculate fractional multiplier +// switch((HWREG(SYSCTL_SYSPLLMULT) & SYSCTL_SYSPLLMULT_SPLLFMULT_M) >> +// SYSCTL_SYSPLLMULT_SPLLFMULT_S) + switch(ClkCfgRegs.SYSPLLMULT.bit.FMULT) + { + default: + case 0: + break; + + case 1: + u32ClockIn += u32ClockIn / 4; + break; + + case 2: + u32ClockIn += u32ClockIn / 2; + break; + + case 3: + u32ClockIn += (u32ClockIn * 3) / 4; + break; + } + } + + if(ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV != 0){ + u32ClockIn /= (2 * ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV); + } + + return u32ClockIn; + +} + +//***************************************************************************** +// +//! Gets the low speed peripheral clock rate. +//! +//! This function determines the clock rate of the low speed peripherals. +//! +//! \note Because of the many different clocking options available, this +//! function cannot determine the clock speed of the processor. This function +//! should be modified to return the actual clock speed of the processor in +//! your specific application. +//! +//! \return The low speed peripheral clock rate. +// +//***************************************************************************** +uint32_t +SysCtlLowSpeedClockGet(uint32_t u32ClockIn) +{ + + // Get the main system clock + u32ClockIn = SysCtlClockGet(u32ClockIn); + + // Apply the divider to the main clock + if(ClkCfgRegs.LOSPCP.bit.LSPCLKDIV != 0){ + u32ClockIn /= (2 * ClkCfgRegs.LOSPCP.bit.LSPCLKDIV); + } + + return u32ClockIn; + +} + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ui32Config is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The oscillator to be +//! used, SYSPLL fractional and integer multiplier, and the system clock +//! divider are all configured with this function. +//! +//! The \e ui32Config parameter is the logical OR of four values: +//! Clock divider, Integer multiplier, Fractional multiplier, and oscillator +//! source. +//! +//! The system clock divider is chosen with using the following macro: +//! \b SYSCTL_SYSDIV(x) - "x" is an integer of value 1 or any even value +//! up to 126 +//! +//! The System PLL fractional multiplier is chosen with one of the following +//! values: +//! \b SYSCTL_FMULT_0, \b SYSCTL_FMULT_1_4, \b SYSCTL_FMULT_1_2, +//! \b SYSCTL_FMULT_3_4 +//! +//! The System PLL integer multiplier is chosen with using the following macro: +//! \b SYSCTL_IMULT(x) - "x" is an integer from 0 to 127 +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, \b SYSCTL_OSCSRC_OSC1 +//! +//! \note The external oscillator must be enabled in order to use an external +//! clock source. Note that attempts to disable the oscillator used to clock +//! the device is prevented by the hardware. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlClockSet(uint32_t ui32Config) +{ + uint32_t clock_source = (ui32Config & SYSCTL_OSCSRC_M) >> SYSCTL_OSCSRC_S; + uint32_t imult = (ui32Config & SYSCTL_IMULT_M); + uint32_t fmult = (ui32Config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S; + uint32_t divsel = (ui32Config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S; + + if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && + (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && + (fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) && + (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) + { + //everything is set as required, so just return + return; + } + + if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) + { + //Configure Oscillator + EALLOW; + switch (clock_source) + { + case ((uint32_t)SYSCTL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S): + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + break; + + case ((uint32_t)SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S): + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; // Clk Src = XTAL + break; + + case ((uint32_t)SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S): + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + break; + } + EDIS; + } + + EALLOW; + // first modify the PLL multipliers + if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || + fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT) + { + // Bypass PLL and set dividers to /1 + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; + + // Program PLL multipliers + uint32_t temp_syspllmult = ClkCfgRegs.SYSPLLMULT.all; + ClkCfgRegs.SYSPLLMULT.all = ((temp_syspllmult & ~(0x37FU)) | + ((fmult << 8U) | imult)); + + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1; // Enable SYSPLL + + // Wait for the SYSPLL lock + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) + { + // Uncomment to service the watchdog + //WdRegs.WDKEY.bit.WDKEY = 0x0055; + //WdRegs.WDKEY.bit.WDKEY = 0x00AA; + } + + // Write a multiplier again to ensure proper PLL initialization + // This will force the PLL to lock a second time + ClkCfgRegs.SYSPLLMULT.bit.IMULT = imult; // Setting integer multiplier + + // Wait for the SYSPLL re-lock + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) + { + // Uncomment to service the watchdog + //WdRegs.WDKEY.bit.WDKEY = 0x0055; + //WdRegs.WDKEY.bit.WDKEY = 0x00AA; + } + } + + // Set divider to produce slower output frequency to limit current increase + if(divsel != (126/2)) + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; + } + else + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + } + + // Enable PLLSYSCLK is fed from system PLL clock + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // Small 100 cycle delay + asm(" RPT #100 || NOP"); + + // Set the divider to user value + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ui32Config is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \e ui32Config parameter is the logical OR of several different values, +//! many of which are grouped into sets where only one can be chosen. +//! +//! The system clock divider is chosen with one of the following values: +//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ... +//! \b SYSCTL_SYSDIV_64. +//! +//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or +//! \b SYSCTL_USE_OSC. +//! +//! The external crystal frequency is chosen with one of the following values: +//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, +//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, +//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, +//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, +//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ, +//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ, +//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz. +//! Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in +//! operation. +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4, +//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only +//! available on devices with the hibernate module, and then only when the +//! hibernate module has been enabled. +//! +//! The internal and main oscillators are disabled with the +//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. +//! The external oscillator must be enabled in order to use an external clock +//! source. Note that attempts to disable the oscillator used to clock the +//! device is prevented by the hardware. +//! +//! To clock the system from an external source (such as an external crystal +//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the +//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | +//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use +//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate +//! crystal with one of the \b SYSCTL_XTAL_xxx values. +//! +//! \note If selecting the PLL as the system clock source (that is, via +//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to +//! determine when the PLL has locked. If an interrupt handler for the +//! system control interrupt is in place, and it responds to and clears the +//! PLL lock interrupt, this function delays until its timeout has occurred +//! instead of completing as soon as PLL lock is achieved. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlAuxClockSet(uint32_t ui32Config) +{ + uint16_t ui16TempDivsel; + + //Bypass PLL + //Ensure the PLL is out of our clock tree + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; + EDIS; + + __asm( " RPT #255 || NOP"); + + //Configure Oscillator + EALLOW; + switch (ui32Config & SYSCTL_OSCSRC_M) + { + default: + case SYSCTL_OSCSRC_OSC2: + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + break; + + case SYSCTL_OSCSRC_XTAL: + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL + break; + + case SYSCTL_OSCSRC_OSC1: + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = INTOSC1 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + break; + + } + EDIS; + + __asm( " RPT #255 || NOP"); + + //Configure PLL if enabled + if(ui32Config & SYSCTL_PLL_ENABLE) + { + EALLOW; + //modify dividers to maximum to reduce the inrush current + //set the integer fractional multipliers in one single write + ClkCfgRegs.AUXPLLMULT.all = ((ui32Config & SYSCTL_IMULT_M) >> SYSCTL_IMULT_S) | + (((ui32Config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S) << 8); + EDIS; + + __asm( " RPT #255 || NOP"); + + //Wait for the SYSPLL lock + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) + { + // Uncomment to service the watchdog + // ServiceDog(); + } + } + + //Configure Dividers + //increase the freq. of operation in steps to avoid any VDD fluctuations + ui16TempDivsel = 3; + while(ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV != ((ui32Config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S)) + { + EALLOW; + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = ui16TempDivsel; + EDIS; + ui16TempDivsel -= 1; + if(ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV != ((ui32Config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S)) + { + SysCtlDelay(15); + } + } + + //Enable PLLSYSCLK is fed from system PLL clock + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + EDIS; +} + +//***************************************************************************** +// +//! Powers up the USB PLL. +//! +//! This function will enable the USB controller's PLL. +//! +//! \note Because every application is different, the user will likely have to +//! modify this function to ensure the PLL multiplier is set correctly to +//! achieve the 60 MHz required by the USB controller. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlUSBPLLEnable(void) +{ +// // Turn on INTOSC2 +// ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; +// //Select INTOSC2 as USB PLL Clk In +// ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; +// // Set Aux PLL divider +// ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = 1; +// // Set Aux PLL multiplier +// ClkCfgRegs.AUXPLLMULT.bit.IMULT = 12; +// // Set Aux PLL fractional multiplier to 0.0 +// ClkCfgRegs.AUXPLLMULT.bit.FMULT = 0; +// //Enable AUXPLL +// ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1; +// +// //Wait for the AUXPLL lock +// while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) +// { +// // Uncomment to service the watchdog +// // ServiceDog(); +// } +// // AUXPLLCLK is fed from the AUXPLL +// ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + +} + +//***************************************************************************** +// +//! Powers down the USB PLL. +//! +//! This function will disable the USB controller's PLL. The USB registers +//! are still accessible, but the physical layer will no longer function. +//! +//! \return None. +// +//***************************************************************************** +void +SysCtlUSBPLLDisable(void) +{ + //Disable the PLL +// ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.h new file mode 100644 index 00000000000..db3c9552dea --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/sysctl.h @@ -0,0 +1,283 @@ +//########################################################################### +// +// FILE: sysctl.h +// +// TITLE: Stellaris style wrapper driver for F2837x system control. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** +#include "inc/hw_types.h" +//***************************************************************************** +// +//! Defined system clock oscillator source speed. Adjust this to reflect your +//! actual clock speed. +// +//***************************************************************************** +#if defined(_LAUNCHXL_F28379D) || defined(_LAUNCHXL_F28377S) +#define SYSTEM_CLOCK_SPEED 10000000 +#else +#define SYSTEM_CLOCK_SPEED 20000000 +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_M 0x00001F80 +#define SYSCTL_SYSDIV_S 0x00000007 +// Only 1 or even values up to 126 are allowed +#define SYSCTL_SYSDIV(x) ((((x == 1) ? 0 : (x / 2)) << SYSCTL_SYSDIV_S) & SYSCTL_SYSDIV_M) + +#define SYSCTL_IMULT_M 0x0000007F +#define SYSCTL_IMULT_S 0x00000000 +#define SYSCTL_IMULT(x) (((x) << SYSCTL_IMULT_S) & SYSCTL_IMULT_M) + +#define SYSCTL_FMULT_M 0x00006000 +#define SYSCTL_FMULT_S 0x0000000D +#define SYSCTL_FMULT_0 0x00000000 +#define SYSCTL_FMULT_1_4 0x00002000 +#define SYSCTL_FMULT_1_2 0x00004000 +#define SYSCTL_FMULT_3_4 0x00006000 + +#define SYSCTL_OSCSRC_M 0x00030000 +#define SYSCTL_OSCSRC_S 0x00000010 +#define SYSCTL_OSCSRC_OSC2 0x00000000 +#define SYSCTL_OSCSRC_XTAL 0x00010000 +#define SYSCTL_OSCSRC_OSC1 0x00020000 + +#define SYSCTL_LSDIV_M 0x00700000 +#define SYSCTL_LSDIV_S 0x00000014 +// Only 1 or even values up to 14 are allowed +#define SYSCTL_LSDIV(x) (((x == 1) ? 0 : (x / 2)) << SYSCTL_LSDIV_S) & SYSCTL_LSDIV_M) + +#define SYSCTL_PLL_ENABLE 0x80000000 +#define SYSCTL_PLL_DISABLE 0x00000000 + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_REG_M 0x0000001F +#define SYSCTL_PERIPH_REG_S 0x00000000 + +#define SYSCTL_PERIPH_BIT_M 0x003F0000 +#define SYSCTL_PERIPH_BIT_S 0x00000010 + +//PCLKCR0 +#define SYSCTL_PERIPH_CLA1 0x00000000 +#define SYSCTL_PERIPH_DMA 0x00020000 +#define SYSCTL_PERIPH_TIMER0 0x00030000 +#define SYSCTL_PERIPH_TIMER1 0x00040000 +#define SYSCTL_PERIPH_TIMER2 0x00050000 +#define SYSCTL_PERIPH_HRPWM 0x00100000 +#define SYSCTL_PERIPH_TBCLKSYNC 0x00120000 +#define SYSCTL_PERIPH_GTBCLKSYNC 0x00130000 + +//PCLKCR1 +#define SYSCTL_PERIPH_EMIF1 0x00000001 +#define SYSCTL_PERIPH_EMIF2 0x00010001 + +//PCLKCR2 +#define SYSCTL_PERIPH_EPWM1 0x00000002 +#define SYSCTL_PERIPH_EPWM2 0x00010002 +#define SYSCTL_PERIPH_EPWM3 0x00020002 +#define SYSCTL_PERIPH_EPWM4 0x00030002 +#define SYSCTL_PERIPH_EPWM5 0x00040002 +#define SYSCTL_PERIPH_EPWM6 0x00050002 +#define SYSCTL_PERIPH_EPWM7 0x00060002 +#define SYSCTL_PERIPH_EPWM8 0x00070002 +#define SYSCTL_PERIPH_EPWM9 0x00080002 +#define SYSCTL_PERIPH_EPWM10 0x00090002 +#define SYSCTL_PERIPH_EPWM11 0x000A0002 +#define SYSCTL_PERIPH_EPWM12 0x000B0002 + +//PCLKCR3 +#define SYSCTL_PERIPH_ECAP1 0x00000003 +#define SYSCTL_PERIPH_ECAP2 0x00010003 +#define SYSCTL_PERIPH_ECAP3 0x00020003 +#define SYSCTL_PERIPH_ECAP4 0x00030003 +#define SYSCTL_PERIPH_ECAP5 0x00040003 +#define SYSCTL_PERIPH_ECAP6 0x00050003 + +//PCLKCR4 +#define SYSCTL_PERIPH_EQEP1 0x00000004 +#define SYSCTL_PERIPH_EQEP2 0x00010004 +#define SYSCTL_PERIPH_EQEP3 0x00020004 + +//PCLKCR5 +//Reserved + +//PCLKCR6 +#define SYSCTL_PERIPH_SD1 0x00000006 +#define SYSCTL_PERIPH_SD2 0x00010006 + +//PCLKCR7 +#define SYSCTL_PERIPH_SCI1 0x00000007 +#define SYSCTL_PERIPH_SCI2 0x00010007 +#define SYSCTL_PERIPH_SCI3 0x00020007 +#define SYSCTL_PERIPH_SCI4 0x00030007 + +//PCLKCR8 +#define SYSCTL_PERIPH_SPI1 0x00000008 +#define SYSCTL_PERIPH_SPI2 0x00010008 +#define SYSCTL_PERIPH_SPI3 0x00020008 + +//PCLKCR9 +#define SYSCTL_PERIPH_I2C1 0x00000009 +#define SYSCTL_PERIPH_I2C2 0x00010009 + +//PCLKCR10 +#define SYSCTL_PERIPH_CAN1 0x0000000A +#define SYSCTL_PERIPH_CAN2 0x0001000A + +//PCLKCR11 +#define SYSCTL_PERIPH_MCBSP1 0x0000000B +#define SYSCTL_PERIPH_MCBSP2 0x0001000B +#define SYSCTL_PERIPH_USB0 0x0010000B + +//PCLKCR12 +#define SYSCTL_PERIPH_UPP1 0x0000000C + +//PCLKCR13 +#define SYSCTL_PERIPH_ADC1 0x0000000D +#define SYSCTL_PERIPH_ADC2 0x0001000D +#define SYSCTL_PERIPH_ADC3 0x0002000D +#define SYSCTL_PERIPH_ADC4 0x0003000D + +//PCLKCR14 +#define SYSCTL_PERIPH_CMPSS1 0x0000000E +#define SYSCTL_PERIPH_CMPSS2 0x0001000E +#define SYSCTL_PERIPH_CMPSS3 0x0002000E +#define SYSCTL_PERIPH_CMPSS4 0x0003000E +#define SYSCTL_PERIPH_CMPSS5 0x0004000E +#define SYSCTL_PERIPH_CMPSS6 0x0005000E +#define SYSCTL_PERIPH_CMPSS7 0x0006000E +#define SYSCTL_PERIPH_CMPSS8 0x0007000E + +//PCLKCR15 +//Reserved + +//PCLKCR16 +#define SYSCTL_PERIPH_BUFFDAC1 0x00000010 +#define SYSCTL_PERIPH_BUFFDAC2 0x00010010 +#define SYSCTL_PERIPH_BUFFDAC3 0x00020010 + + +//old +//#define SYSCTL_PERIPH_UART_A 0x1 // SCI A +//#define SYSCTL_PERIPH_UART_B 0x2 // SCI B +//#define SYSCTL_PERIPH_UART_C 0x3 // SCI C +//#define SYSCTL_PERIPH_UART_D 0x4 // SCI D +// +//#define SYSCTL_PERIPH_SPI_A 0x5 // SPI A +//#define SYSCTL_PERIPH_SPI_B 0x6 // SPI B +//#define SYSCTL_PERIPH_SPI_C 0x7 // SPI C +// +//#define SYSCTL_PERIPH_MCBSP_A 0x8 // McBSP A +//#define SYSCTL_PERIPH_MCBSP_B 0x9 // McBSP B +// +//#define SYSCTL_PERIPH_DMA 0xA // DMA +// +//#define SYSCTL_PERIPH_USB0 0xB // USBA + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +extern uint32_t SysCtlSRAMSizeGet(void); +extern uint32_t SysCtlFlashSizeGet(void); +extern void SysCtlPeripheralReset(uint32_t ui32Peripheral); +extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral); +extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral); +extern void SysCtlDelay(uint32_t ulCount); +extern uint32_t SysCtlClockGet(uint32_t u32ClockIn); +extern void SysCtlClockSet(uint32_t ui32Config); +extern void SysCtlAuxClockSet(uint32_t ui32Config); +extern uint32_t SysCtlLowSpeedClockGet(uint32_t u32ClockIn); +extern void SysCtlUSBPLLEnable(void); +extern void SysCtlUSBPLLDisable(void); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//**************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.c new file mode 100644 index 00000000000..971715de786 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.c @@ -0,0 +1,305 @@ +//########################################################################### +// +// FILE: systick.c +// +// TITLE: Stellaris style wrapper driver for C28x CPU Timer 0. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#include "F28x_Project.h" +#include "inc/hw_ints.h" +#include "inc/hw_types.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/systick.h" + + +//***************************************************************************** +// +//! Initializes the Timer0 Module to act as a system tick +//! +//! \return None. +// +//***************************************************************************** +void +SysTickInit(void) +{ + // CPU Timer 0 + // Initialize timer period to maximum: + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + // Make sure timer is stopped: + CpuTimer0Regs.TCR.bit.TSS = 1; + // Reload all counter register with period value: + CpuTimer0Regs.TCR.bit.TRB = 1; +} + +//***************************************************************************** +// +//! Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \note Calling this function will cause the SysTick counter to (re)commence +//! counting from its current value. The counter is not automatically reloaded +//! with the period as specified in a previous call to SysTickPeriodSet(). If +//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be +//! written to force this. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the supplied period on the next +//! clock. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickEnable(void) +{ + // + // Enable SysTick. + // + CpuTimer0Regs.TCR.bit.TRB = 1; + CpuTimer0Regs.TCR.bit.TSS = 0; +} + +//***************************************************************************** +// +//! Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickDisable(void) +{ + // + // Disable SysTick. + // + StopCpuTimer0(); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the SysTick interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! This sets the handler to be called when a SysTick interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_TINT0, pfnHandler); + + // + // Enable the SysTick interrupt. + // + IntEnable(INT_TINT0); +} + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the SysTick interrupt. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntUnregister(void) +{ + // + // Disable the SysTick interrupt. + // + IntDisable(INT_TINT0); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_TINT0); +} + +//***************************************************************************** +// +//! Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \note The SysTick interrupt handler does not need to clear the SysTick +//! interrupt source as this is done automatically by NVIC when the interrupt +//! handler is called. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntEnable(void) +{ + // + // Enable the SysTick interrupt. + // + CpuTimer0Regs.TCR.bit.TIE = 1; + IntEnable(INT_TINT0); +} + +//***************************************************************************** +// +//! Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickIntDisable(void) +{ + // + // Disable the SysTick interrupt. + // + CpuTimer0Regs.TCR.bit.TIE = 0; + IntDisable(INT_TINT0); +} + +//***************************************************************************** +// +//! Sets the period of the SysTick counter. +//! +//! \param ui32Period is the number of clock ticks in each period of the SysTick +//! counter; must be between 1 and 16,777,216, inclusive. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \note Calling this function does not cause the SysTick counter to reload +//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT +//! register must be written. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the \e ui32Period supplied here on +//! the next clock after the SysTick is enabled. +//! +//! \return None. +// +//***************************************************************************** +void +SysTickPeriodSet(uint32_t ui32Period) +{ + // + // Check the arguments. + // + ASSERT((ui32Period > 0) && (ui32Period <= 16777216)); + + // + // Set the period of the SysTick counter. + // + CpuTimer0Regs.PRD.all = ui32Period; +} + +//***************************************************************************** +// +//! Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +uint32_t +SysTickPeriodGet(void) +{ + // + // Return the period of the SysTick counter. + // + return(CpuTimer0Regs.PRD.all); +} + +//***************************************************************************** +// +//! Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the period - 1 and zero, inclusive. +//! +//! \return Returns the current value of the SysTick counter. +// +//***************************************************************************** +uint32_t +SysTickValueGet(void) +{ + // + // Return the current value of the SysTick counter. + // + return(CpuTimer0Regs.TIM.all); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.h new file mode 100644 index 00000000000..e4b6e7bf6ff --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/systick.h @@ -0,0 +1,84 @@ +//########################################################################### +// +// FILE: systick.h +// +// TITLE: Stellaris style wrapper driver for C28x CPU Timer 0. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + extern void SysTickInit(void); + extern void SysTickEnable(void); + extern void SysTickDisable(void); + extern void SysTickIntRegister(void (*pfnHandler)(void)); + extern void SysTickIntUnregister(void); + extern void SysTickIntEnable(void); + extern void SysTickIntDisable(void); + extern void SysTickPeriodSet(uint32_t ui32Period); + extern uint32_t SysTickPeriodGet(void); + extern uint32_t SysTickValueGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.c b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.c new file mode 100644 index 00000000000..29b2454261e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.c @@ -0,0 +1,1352 @@ +//########################################################################### +// +// FILE: uart.c +// +// TITLE: Stellaris style wrapper driver for C28x SCI peripheral. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_uart.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/uart.h" + + +//***************************************************************************** +// +//! \internal +//! Checks a UART base address. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function determines if a UART port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static bool +UARTBaseValid(uint32_t ui32Base) +{ + return((ui32Base == UARTA_BASE) || (ui32Base == UARTB_BASE) || + (ui32Base == UARTC_BASE) || (ui32Base == UARTD_BASE)); +} +#endif + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Parity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e ui32Parity parameter must be one of \b UART_CONFIG_PAR_NONE, +//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, +//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the +//! parity bit; it is always either one or zero based on the mode. +//! +//! \return None. +// +//***************************************************************************** +void +UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || + (ui32Parity == UART_CONFIG_PAR_EVEN) || + (ui32Parity == UART_CONFIG_PAR_ODD) || + (ui32Parity == UART_CONFIG_PAR_ONE) || + (ui32Parity == UART_CONFIG_PAR_ZERO)); + + // + // Set the parity mode. + // + HWREGB(ui32Base + UART_O_CCR) = ((HWREGB(ui32Base + UART_O_CCR) & + ~(UART_CONFIG_PAR_MASK)) | ui32Parity); +} + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \return Returns the current parity settings, specified as one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. +// +//***************************************************************************** +uint32_t +UARTParityModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return the current parity setting. + // + return(HWREGB(ui32Base + UART_O_CCR) & + (UART_CONFIG_PAR_MASK)); +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one of +//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8, +//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of +//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, +//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOIntLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || + (ui32TxLevel == UART_FIFO_TX2_8) || + (ui32TxLevel == UART_FIFO_TX4_8) || + (ui32TxLevel == UART_FIFO_TX6_8)); + ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || + (ui32RxLevel == UART_FIFO_RX2_8) || + (ui32RxLevel == UART_FIFO_RX4_8) || + (ui32RxLevel == UART_FIFO_RX6_8)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(ui32Base + UART_O_FFTX) = (HWREGH(ui32Base + UART_O_FFTX)& (~UART_FFTX_TXFFIL_M)) | ui32TxLevel ; + HWREGH(ui32Base + UART_O_FFRX) = (HWREGH(ui32Base + UART_O_FFRX)& (~UART_FFRX_RXFFIL_M)) | ui32RxLevel ; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, +//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, +//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOIntLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Extract the transmit and receive FIFO levels. + // + *pui32TxLevel = HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_TXFFIL_M; + *pui32RxLevel = HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFIL_M; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, +//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. +//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, +//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Extract the transmit and receive FIFO levels. + // + *pui32TxLevel = (HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_TXFFST_M) >> UART_FFTX_TXFFST_S; + *pui32RxLevel = (HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S; +} + +//***************************************************************************** +// +//! Sets the configuration of a UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param ui32Baud is the desired baud rate. +//! \param ui32Config is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the UART for operation in the specified data +//! format. The baud rate is provided in the \e ui32Baud parameter and the data +//! format in the \e ui32Config parameter. +//! +//! The \e ui32Config parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, +//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 +//! select from eight to five data bits per byte (respectively). +//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, +//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO +//! select the parity mode (no parity bit, even parity bit, odd parity bit, +//! parity bit always one, and parity bit always zero, respectively). +//! +//! The peripheral clock will be the same as the processor clock. This will be +//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtlClockGet()). +//! +//! This function replaces the original UARTConfigSet() API and performs the +//! same actions. A macro is provided in uart.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +//Changed for C28x +void +UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config) +{ + uint32_t ui32Div; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); +// ASSERT(ui32UARTClk >= (ui32Baud * UART_CLK_DIVIDER)); + + // + // Stop the UART. + // + UARTDisable(ui32Base); + + // + // Is the required baud rate greater than the maximum rate supported? + // + if((ui32Baud * 16) > ui32UARTClk) + { + // + // Baud Rate Not supported with current clock + // + return; + } + + // + // Compute the baud rate divider. + // + ui32Div = ((ui32UARTClk / (ui32Baud * 8)) - 1); + + // + // Set the baud rate. + // + HWREGB(ui32Base + UART_O_HBAUD) = (ui32Div & 0xFF00) >> 8; + HWREGB(ui32Base + UART_O_LBAUD) = ui32Div & 0x00FF; + + // + // Set parity, data length, and number of stop bits. + // + HWREGB(ui32Base + UART_O_CCR) = ((HWREGB(ui32Base + UART_O_CCR) & + ~(UART_CONFIG_PAR_MASK | UART_CONFIG_STOP_MASK | UART_CONFIG_WLEN_MASK)) + | ui32Config); + + + // + // Start the UART. + // + UARTEnable(ui32Base); +} + +//***************************************************************************** +// +//! Gets the current configuration of a UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param pui32Baud is a pointer to storage for the baud rate. +//! \param pui32Config is a pointer to storage for the data format. +//! +//! The baud rate and data format for the UART is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an ``official'' baud rate. The data format returned in +//! \e pui32Config is enumerated the same as the \e ui32Config parameter of +//! UARTConfigSetExpClk(). +//! +//! The peripheral clock will be the same as the processor clock. This will be +//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtlClockGet()). +//! +//! This function replaces the original UARTConfigGet() API and performs the +//! same actions. A macro is provided in uart.h to map the original +//! API to this API. +//! +//! \return None. +// +//***************************************************************************** +void +UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config) +{ + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Compute the baud rate. + // + *pui32Baud = ui32UARTClk / ((1 + (HWREGB(ui32Base + UART_O_HBAUD) << 8 ) | HWREGB(ui32Base + UART_O_LBAUD)) * 8); + + // + // Get the parity, data length, and number of stop bits. + // + *pui32Config = HWREGB(ui32Base + UART_O_CCR) & + (UART_CONFIG_PAR_MASK | UART_CONFIG_STOP_MASK | UART_CONFIG_WLEN_MASK); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive +//! FIFOs. +//! +//! \return None. +// +//***************************************************************************** +void +UARTEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Enable RX, TX, and the UART. + // + HWREGB(ui32Base + UART_O_CTL1) |= (UART_CTL1_TXENA | UART_CTL1_RXENA | UART_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +void +UARTDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait for end of TX. + // + while(!(HWREGH(ui32Base + UART_O_CTL2) & UART_CTL2_TXEMPTY)) + { + } + + // + // Disable the FIFO. + // + HWREGH(ui32Base + UART_O_FFTX) &= ~(UART_FFTX_SCIFFENA); + + // + // Disable the UART. + // + HWREGB(ui32Base + UART_O_CTL1) &= ~(UART_CTL1_TXENA | UART_CTL1_RXENA); +} + +//***************************************************************************** +// +//! Enables Loop Back Test Mode. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Sets the SCICCR.LOOPBKENA to enable +//! +//! \return None. +// +//***************************************************************************** +void UARTsetLoopBack(uint32_t ui32Base, bool enable) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + if(enable) + { + // + // Enable LoopBack. + // + + HWREGB(ui32Base + UART_O_CCR) |= UART_CCR_LOOPBKENA; + } + else + { + // + // Disable LoopBack. + // + HWREGB(ui32Base + UART_O_CCR) &= ~UART_CCR_LOOPBKENA; + } +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFOEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Enable the FIFO. + // + HWREGH(ui32Base + UART_O_FFTX) |= UART_FFTX_SCIFFENA; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This functions disables the transmit and receive FIFOs in the UART. +//! +//! \return None. +// +//***************************************************************************** +void +UARTFIFODisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Disable the FIFO. + // + HWREGH(ui32Base + UART_O_FFTX) &= ~UART_FFTX_SCIFFENA; +} + +//***************************************************************************** +// +//! Sets the operating mode for the UART transmit interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Mode is the operating mode for the transmit interrupt. It may be +//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle +//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO +//! level. +//! +//! This function allows the mode of the UART transmit interrupt to be set. By +//! default, the transmit interrupt is asserted when the FIFO level falls past +//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this +//! function is called with \e ui32Mode set to \b UART_TXINT_MODE_EOT, the +//! transmit interrupt will only be asserted once the transmitter is completely +//! idle - the transmit FIFO is empty and all bits, including any stop bits, +//! have cleared the transmitter. +//! +//! \return None. +// +//***************************************************************************** +void +UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32Mode == UART_TXINT_MODE_EOT) || + (ui32Mode == UART_TXINT_MODE_FIFO_M)); + + // + // Set or clear the EOT bit of the UART control register as appropriate. + // + HWREGH(ui32Base + UART_O_FFTX) = ((HWREG(ui32Base + UART_O_FFTX) & ~(UART_TXINT_MODE_FIFO_M)) | ui32Mode); +} + +//***************************************************************************** +// +//! Returns the current operating mode for the UART transmit interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns the current operating mode for the UART transmit +//! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the +//! transmit interrupt is currently set to be asserted once the transmitter is +//! completely idle - the transmit FIFO is empty and all bits, including any +//! stop bits, have cleared the transmitter. The return value will be \b +//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the +//! level of the transmit FIFO. +//! +//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT. +// +//***************************************************************************** +uint32_t +UARTTxIntModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return the current transmit interrupt mode. + // + return(HWREGH(ui32Base + UART_O_FFTX) & UART_TXINT_MODE_FIFO_M); +} + +//***************************************************************************** +// +//! Determines if there are any characters in the receive FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \return Returns \b true if there is data in the receive FIFO or \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +bool +UARTCharsAvail(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return the availability of characters. + // + if(HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_SCIFFENA) + { + return(((HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S) ? true : false); + + } + else + { + return((HWREGB(ui32Base + UART_O_RXST) & UART_RXST_RXRDY) ? true : false); + } +} + +//***************************************************************************** +// +//! Determines if there is any space in the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \return Returns \b true if there is space available in the transmit FIFO +//! or \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +bool +UARTSpaceAvail(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return the availability of space. + // + return((HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY) ? true : false); + +} + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. +//! +//! This function replaces the original UARTCharNonBlockingGet() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 is returned if there are no characters present in the +//! receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +int32_t +UARTCharGetNonBlocking(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // See if there are any characters in the receive FIFO. + // + if(HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_SCIFFENA) + { + if((HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S) + { + // + // Read and return the next character. + // + return(HWREGH(ui32Base + UART_O_RXBUF) & UART_RXBUF_SAR_M); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } + } + else + { + if((HWREGB(ui32Base + UART_O_RXST) & UART_RXST_RXRDY)) + { + // + // Read and return the next character. + // + return(HWREGH(ui32Base + UART_O_RXBUF) & UART_RXBUF_SAR_M); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } + } +} + +//***************************************************************************** +// +//! Waits for a character from the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function waits until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. +// +//***************************************************************************** +int32_t +UARTCharGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait until a char is available. + // + + if(HWREGH(ui32Base + UART_O_FFTX) & UART_FFTX_SCIFFENA) + { + while(!((HWREGH(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFST_M) >> UART_FFRX_RXFFST_S)) + { + } + } + else + { + while(!(HWREGH(ui32Base + UART_O_RXST) & UART_RXST_RXRDY)) + { + + } + } + // + // Now get the char. + // + return(HWREGH(ui32Base + UART_O_RXBUF) & UART_RXBUF_SAR_M); +} + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Writes the character \e ucData to the transmit FIFO for the specified port. +//! This function does not block, so if there is no space available, then a +//! \b false is returned, and the application must retry the function later. +//! +//! This function replaces the original UARTCharNonBlockingPut() API and +//! performs the same actions. A macro is provided in uart.h to map +//! the original API to this API. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO or \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +bool +UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // See if there is space in the transmit FIFO. + // + if(HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY) + { + // + // Write this character to the transmit FIFO. + // + HWREGB(ui32Base + UART_O_TXBUF) = ucData; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Sends the character \e ucData to the transmit FIFO for the specified port. +//! If there is no space available in the transmit FIFO, this function waits +//! until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +void +UARTCharPut(uint32_t ui32Base, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Wait until space is available. + // + while(!(HWREGH(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY)) + { + } + + // + // Send the char. + // + HWREGB(ui32Base + UART_O_TXBUF) = ucData; +} + +//***************************************************************************** +// +//! Determines whether the UART transmitter is busy or not. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \b false is returned, the transmit FIFO is +//! empty and all bits of the last transmitted character, including all stop +//! bits, have left the hardware shift register. +//! +//! \return Returns \b true if the UART is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +bool +UARTBusy(uint32_t ui32Base) +{ + // + // Check the argument. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Determine if the UART is busy. + // + return((HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXEMPTY) ? false : true); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART RX interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; specific UART +//! interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTRXIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the UART port. + // + ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCIRXINTA : INT_SCIRXINTB ); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART TX interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; specific UART +//! interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTTXIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the UART port. + // + ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCITXINTA : INT_SCITXINTB ); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART RX interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! will clear the handler to be called when a UART interrupt occurs. This +//! will also mask off the interrupt in the interrupt controller so that the +//! interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTRXIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the UART port. + // + ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCIRXINTA : INT_SCIRXINTB ); + + // + // Disable the interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART TX interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! will clear the handler to be called when a UART interrupt occurs. This +//! will also mask off the interrupt in the interrupt controller so that the +//! interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +UARTTXIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Determine the interrupt number based on the UART port. + // + ui32Int = ((ui32Base == UARTA_BASE) ? INT_SCITXINTA : INT_SCITXINTB ); + + // + // Disable the interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Enables individual UART interrupt sources. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ui32IntFlags parameter is the logical OR of any of the following: +//! +//! - \b UART_INT_OE - Overrun Error interrupt +//! - \b UART_INT_BE - Break Error interrupt +//! - \b UART_INT_PE - Parity Error interrupt +//! - \b UART_INT_FE - Framing Error interrupt +//! - \b UART_INT_RT - Receive Timeout interrupt +//! - \b UART_INT_TX - Transmit interrupt +//! - \b UART_INT_RX - Receive interrupt +//! - \b UART_INT_DSR - DSR interrupt +//! - \b UART_INT_DCD - DCD interrupt +//! - \b UART_INT_CTS - CTS interrupt +//! - \b UART_INT_RI - RI interrupt +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Enable the specified interrupts. + // + if(ui32IntFlags & UART_INT_RXERR) + HWREGB(ui32Base + UART_O_CTL1) |= UART_CTL1_RXERRINTENA; + + if(ui32IntFlags & UART_INT_RXRDY_BRKDT) + HWREGB(ui32Base + UART_O_CTL2) |= UART_CTL2_RXBKINTENA; + + if(ui32IntFlags & UART_INT_TXRDY) + HWREGB(ui32Base + UART_O_CTL2) |= UART_CTL2_TXINTENA; + + if(ui32IntFlags & UART_INT_TXFF) + HWREGB(ui32Base + UART_O_FFTX) |= UART_FFTX_TXFFIENA; + + if(ui32IntFlags & UART_INT_RXFF) + HWREGB(ui32Base + UART_O_FFRX) |= UART_FFRX_RXFFIENA; + + +} + +//***************************************************************************** +// +//! Disables individual UART interrupt sources. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e ui32IntFlags parameter has the same definition as the \e ui32IntFlags +//! parameter to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Disable the specified interrupts. + // + if(ui32IntFlags & UART_INT_RXERR) + HWREGB(ui32Base + UART_O_CTL1) &= ~UART_CTL1_RXERRINTENA; + + if(ui32IntFlags & UART_INT_RXRDY_BRKDT) + HWREGB(ui32Base + UART_O_CTL2) &= ~UART_CTL2_RXBKINTENA; + + if(ui32IntFlags & UART_INT_TXRDY) + HWREGB(ui32Base + UART_O_CTL2) &= ~UART_CTL2_TXINTENA; + + if(ui32IntFlags & UART_INT_TXFF) + HWREGB(ui32Base + UART_O_FFTX) &= ~UART_FFTX_TXFFIENA; + + if(ui32IntFlags & UART_INT_RXFF) + HWREGB(ui32Base + UART_O_FFRX) &= ~UART_FFRX_RXFFIENA; +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified UART. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in UARTIntEnable(). +// +//***************************************************************************** +uint32_t +UARTIntStatus(uint32_t ui32Base, bool bMasked) +{ + + uint32_t temp = 0; + + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + + + if(HWREGB(ui32Base + UART_O_CTL2) & UART_CTL2_TXRDY) + temp |= UART_INT_TXRDY; + + if(HWREGB(ui32Base + UART_O_RXST) & UART_RXST_RXERROR) + temp |= UART_INT_RXERR; + + if(HWREGB(ui32Base + UART_O_RXST) & (UART_RXST_RXRDY | UART_RXST_BRKDT)) + temp |= UART_INT_RXRDY_BRKDT; + + if(HWREGB(ui32Base + UART_O_FFTX) & UART_FFTX_TXFFINT) + temp |= UART_INT_TXFF; + + if(HWREGB(ui32Base + UART_O_FFRX) & UART_FFRX_RXFFINT) + temp |= UART_INT_RXFF; + + return temp; +} + +//***************************************************************************** +// +//! Clears UART interrupt sources. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e ui32IntFlags parameter has the same definition as the \e ui32IntFlags +//! parameter to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +void +UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Clear the requested interrupt sources. + // + if(ui32IntFlags & (UART_INT_RXERR | UART_INT_RXRDY_BRKDT)) + { + HWREGB(ui32Base + UART_O_CTL1) &= ~UART_CTL1_SWRESET; + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + HWREGB(ui32Base + UART_O_CTL1) |= UART_CTL1_SWRESET; + } + + if(ui32IntFlags & UART_INT_TXFF) + HWREGB(ui32Base + UART_O_FFTX) |= UART_FFTX_TXFFINTCLR; + + if(ui32IntFlags & UART_INT_RXFF) + HWREGB(ui32Base + UART_O_FFRX) |= UART_FFRX_RXFFINTCLR; + +} + +//***************************************************************************** +// +//! Gets current receiver errors. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \return Returns a logical OR combination of the receiver error flags, +//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK +//! and \b UART_RXERROR_OVERRUN. +// +//***************************************************************************** +uint32_t +UARTRxErrorGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // Return the current value of the receive status register. + // + return(HWREGH(ui32Base + UART_O_RXST)); +} + +//***************************************************************************** +// +//! Clears all reported receiver errors. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function is used to clear all receiver error conditions reported via +//! UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +UARTRxErrorClear(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(UARTBaseValid(ui32Base)); + + // + // To clear all errors a sw reset of the module is required + // + HWREGB(ui32Base + UART_O_CTL1) &= ~UART_CTL1_SWRESET; + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + HWREGB(ui32Base + UART_O_CTL1) |= UART_CTL1_SWRESET; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.h b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.h new file mode 100644 index 00000000000..ed13d30ec2f --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/driverlib/uart.h @@ -0,0 +1,214 @@ +//########################################################################### +// +// FILE: uart.h +// +// TITLE: Stellaris style wrapper driver for C28x SCI peripheral. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ui32IntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_RXERR 0x01 +#define UART_INT_RXRDY_BRKDT 0x02 +#define UART_INT_TXRDY 0x04 +#define UART_INT_TXFF 0x08 +#define UART_INT_RXFF 0x10 + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter +// and returned by UARTConfigGetExpClk in the pui32Config parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ui32Parity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000007 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000007 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000006 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000005 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000004 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000080 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000080 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000060 // Parity Mask +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000060 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000020 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000020 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000060 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter and +// returned by UARTFIFOLevelGet in the pui32TxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX2_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX4_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX6_8 0x00000004 // Transmit interrupt Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter and +// returned by UARTFIFOLevelGet in the pui32RxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000001 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX2_8 0x00000002 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX4_8 0x00000003 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX6_8 0x00000004 // Receive interrupt at Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000020 +#define UART_RXERROR_PARITY 0x00000004 +#define UART_RXERROR_FRAMING 0x00000010 + +//***************************************************************************** +// +// Values that can be passed to UARTHandshakeOutputsSet() or returned from +// UARTHandshakeOutputGet(). +// +//***************************************************************************** +#define UART_OUTPUT_RTS 0x00000800 +#define UART_OUTPUT_DTR 0x00000400 + +//***************************************************************************** +// +// Values that can be returned from UARTHandshakeInputsGet(). +// +//***************************************************************************** +#define UART_INPUT_RI 0x00000100 +#define UART_INPUT_DCD 0x00000004 +#define UART_INPUT_DSR 0x00000002 +#define UART_INPUT_CTS 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTTxIntModeSet() or returned from +// UARTTxIntModeGet(). +// +//***************************************************************************** +#define UART_TXINT_MODE_FIFO_M 0x0000001F +#define UART_TXINT_MODE_EOT 0x00000000 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity); +extern uint32_t UARTParityModeGet(uint32_t ui32Base); +extern void UARTFIFOIntLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel); +extern void UARTFIFOIntLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel); +extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel); +extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config); +extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config); +extern void UARTEnable(uint32_t ui32Base); +extern void UARTDisable(uint32_t ui32Base); +extern void UARTsetLoopBack(uint32_t ui32Base, bool enable); +extern void UARTFIFOEnable(uint32_t ui32Base); +extern void UARTFIFODisable(uint32_t ui32Base); +extern bool UARTCharsAvail(uint32_t ui32Base); +extern bool UARTSpaceAvail(uint32_t ui32Base); +extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); +extern int32_t UARTCharGet(uint32_t ui32Base); +extern bool UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData); +extern void UARTCharPut(uint32_t ui32Base, unsigned char ucData); +extern bool UARTBusy(uint32_t ui32Base); +extern void UARTRXIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern void UARTTXIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern void UARTRXIntUnregister(uint32_t ui32Base); +extern void UARTTXIntUnregister(uint32_t ui32Base); +extern void UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t UARTIntStatus(uint32_t ui32Base, bool bMasked); +extern void UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t UARTRxErrorGet(uint32_t ui32Base); +extern void UARTRxErrorClear(uint32_t ui32Base); +extern void UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode); +extern uint32_t UARTTxIntModeGet(uint32_t ui32Base); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_adc.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_adc.h new file mode 100644 index 00000000000..b3a09713c69 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_adc.h @@ -0,0 +1,1227 @@ +//########################################################################### +// +// FILE: hw_adc.h +// +// TITLE: Definitions for the C28x ADC registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets +// +//***************************************************************************** +#define ADC_O_CTL1 0x0 // ADC Control 1 Register +#define ADC_O_CTL2 0x1 // ADC Control 2 Register +#define ADC_O_BURSTCTL 0x2 // ADC Burst Control Register +#define ADC_O_INTFLG 0x3 // ADC Interrupt Flag Register +#define ADC_O_INTFLGCLR 0x4 // ADC Interrupt Flag Clear + // Register +#define ADC_O_INTOVF 0x5 // ADC Interrupt Overflow Register +#define ADC_O_INTOVFCLR 0x6 // ADC Interrupt Overflow Clear + // Register +#define ADC_O_INTSEL1N2 0x7 // ADC Interrupt 1 and 2 Selection + // Register +#define ADC_O_INTSEL3N4 0x8 // ADC Interrupt 3 and 4 Selection + // Register +#define ADC_O_SOCPRICTL 0x9 // ADC SOC Priority Control + // Register +#define ADC_O_INTSOCSEL1 0xA // ADC Interrupt SOC Selection 1 + // Register +#define ADC_O_INTSOCSEL2 0xB // ADC Interrupt SOC Selection 2 + // Register +#define ADC_O_SOCFLG1 0xC // ADC SOC Flag 1 Register +#define ADC_O_SOCFRC1 0xD // ADC SOC Force 1 Register +#define ADC_O_SOCOVF1 0xE // ADC SOC Overflow 1 Register +#define ADC_O_SOCOVFCLR1 0xF // ADC SOC Overflow Clear 1 + // Register +#define ADC_O_SOC0CTL 0x10 // ADC SOC0 Control Register +#define ADC_O_SOC1CTL 0x12 // ADC SOC1 Control Register +#define ADC_O_SOC2CTL 0x14 // ADC SOC2 Control Register +#define ADC_O_SOC3CTL 0x16 // ADC SOC3 Control Register +#define ADC_O_SOC4CTL 0x18 // ADC SOC4 Control Register +#define ADC_O_SOC5CTL 0x1A // ADC SOC5 Control Register +#define ADC_O_SOC6CTL 0x1C // ADC SOC6 Control Register +#define ADC_O_SOC7CTL 0x1E // ADC SOC7 Control Register +#define ADC_O_SOC8CTL 0x20 // ADC SOC8 Control Register +#define ADC_O_SOC9CTL 0x22 // ADC SOC9 Control Register +#define ADC_O_SOC10CTL 0x24 // ADC SOC10 Control Register +#define ADC_O_SOC11CTL 0x26 // ADC SOC11 Control Register +#define ADC_O_SOC12CTL 0x28 // ADC SOC12 Control Register +#define ADC_O_SOC13CTL 0x2A // ADC SOC13 Control Register +#define ADC_O_SOC14CTL 0x2C // ADC SOC14 Control Register +#define ADC_O_SOC15CTL 0x2E // ADC SOC15 Control Register +#define ADC_O_EVTSTAT 0x30 // ADC Event Status Register +#define ADC_O_EVTCLR 0x32 // ADC Event Clear Register +#define ADC_O_EVTSEL 0x34 // ADC Event Selection Register +#define ADC_O_EVTINTSEL 0x36 // ADC Event Interrupt Selection + // Register +#define ADC_O_COUNTER 0x39 // ADC Counter Register +#define ADC_O_REV 0x3A // ADC Revision Register +#define ADC_O_OFFTRIM 0x3B // ADC Offset Trim Register +#define ADC_O_PPB1CONFIG 0x40 // ADC PPB1 Config Register +#define ADC_O_PPB1STAMP 0x41 // ADC PPB1 Sample Delay Time + // Stamp Register +#define ADC_O_PPB1OFFCAL 0x42 // ADC PPB1 Offset Calibration + // Register +#define ADC_O_PPB1OFFREF 0x43 // ADC PPB1 Offset Reference + // Register +#define ADC_O_PPB1TRIPHI 0x44 // ADC PPB1 Trip High Register +#define ADC_O_PPB1TRIPLO 0x46 // ADC PPB1 Trip Low/Trigger Time + // Stamp Register +#define ADC_O_PPB2CONFIG 0x48 // ADC PPB2 Config Register +#define ADC_O_PPB2STAMP 0x49 // ADC PPB2 Sample Delay Time + // Stamp Register +#define ADC_O_PPB2OFFCAL 0x4A // ADC PPB2 Offset Calibration + // Register +#define ADC_O_PPB2OFFREF 0x4B // ADC PPB2 Offset Reference + // Register +#define ADC_O_PPB2TRIPHI 0x4C // ADC PPB2 Trip High Register +#define ADC_O_PPB2TRIPLO 0x4E // ADC PPB2 Trip Low/Trigger Time + // Stamp Register +#define ADC_O_PPB3CONFIG 0x50 // ADC PPB3 Config Register +#define ADC_O_PPB3STAMP 0x51 // ADC PPB3 Sample Delay Time + // Stamp Register +#define ADC_O_PPB3OFFCAL 0x52 // ADC PPB3 Offset Calibration + // Register +#define ADC_O_PPB3OFFREF 0x53 // ADC PPB3 Offset Reference + // Register +#define ADC_O_PPB3TRIPHI 0x54 // ADC PPB3 Trip High Register +#define ADC_O_PPB3TRIPLO 0x56 // ADC PPB3 Trip Low/Trigger Time + // Stamp Register +#define ADC_O_PPB4CONFIG 0x58 // ADC PPB4 Config Register +#define ADC_O_PPB4STAMP 0x59 // ADC PPB4 Sample Delay Time + // Stamp Register +#define ADC_O_PPB4OFFCAL 0x5A // ADC PPB4 Offset Calibration + // Register +#define ADC_O_PPB4OFFREF 0x5B // ADC PPB4 Offset Reference + // Register +#define ADC_O_PPB4TRIPHI 0x5C // ADC PPB4 Trip High Register +#define ADC_O_PPB4TRIPLO 0x5E // ADC PPB4 Trip Low/Trigger Time + // Stamp Register +#define ADC_O_RESULT0 0x0 // ADC Result 0 Register +#define ADC_O_RESULT1 0x1 // ADC Result 1 Register +#define ADC_O_RESULT2 0x2 // ADC Result 2 Register +#define ADC_O_RESULT3 0x3 // ADC Result 3 Register +#define ADC_O_RESULT4 0x4 // ADC Result 4 Register +#define ADC_O_RESULT5 0x5 // ADC Result 5 Register +#define ADC_O_RESULT6 0x6 // ADC Result 6 Register +#define ADC_O_RESULT7 0x7 // ADC Result 7 Register +#define ADC_O_RESULT8 0x8 // ADC Result 8 Register +#define ADC_O_RESULT9 0x9 // ADC Result 9 Register +#define ADC_O_RESULT10 0xA // ADC Result 10 Register +#define ADC_O_RESULT11 0xB // ADC Result 11 Register +#define ADC_O_RESULT12 0xC // ADC Result 12 Register +#define ADC_O_RESULT13 0xD // ADC Result 13 Register +#define ADC_O_RESULT14 0xE // ADC Result 14 Register +#define ADC_O_RESULT15 0xF // ADC Result 15 Register +#define ADC_O_PPB1RESULT 0x10 // ADC Post Processing Block 1 + // Result Register +#define ADC_O_PPB2RESULT 0x12 // ADC Post Processing Block 2 + // Result Register +#define ADC_O_PPB3RESULT 0x14 // ADC Post Processing Block 3 + // Result Register +#define ADC_O_PPB4RESULT 0x16 // ADC Post Processing Block 4 + // Result Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCCTL1 register +// +//***************************************************************************** +#define ADC_CTL1_INTPULSEPOS 0x4 // ADC Interrupt Pulse Position +#define ADC_CTL1_ADCPWDNZ 0x80 // ADC Power Down +#define ADC_CTL1_ADCBSYCHN_S 8 +#define ADC_CTL1_ADCBSYCHN_M 0xF00 // ADC Busy Channel +#define ADC_CTL1_ADCBSY 0x2000 // ADC Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCCTL2 register +// +//***************************************************************************** +#define ADC_CTL2_PRESCALE_S 0 +#define ADC_CTL2_PRESCALE_M 0xF // ADC Clock Prescaler +#define ADC_CTL2_RESOLUTION 0x40 // SOC Conversion Resolution +#define ADC_CTL2_SIGNALMODE 0x80 // SOC Signaling Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCBURSTCTL register +// +//***************************************************************************** +#define ADC_BURSTCTL_BURSTTRIGSEL_S 0 +#define ADC_BURSTCTL_BURSTTRIGSEL_M 0x3F // SOC Burst Trigger Source Select +#define ADC_BURSTCTL_BURSTSIZE_S 8 +#define ADC_BURSTCTL_BURSTSIZE_M 0xF00 // SOC Burst Size Select +#define ADC_BURSTCTL_BURSTEN 0x8000 // SOC Burst Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTFLG register +// +//***************************************************************************** +#define ADC_INTFLG_ADCINT1 0x1 // ADC Interrupt 1 Flag +#define ADC_INTFLG_ADCINT2 0x2 // ADC Interrupt 2 Flag +#define ADC_INTFLG_ADCINT3 0x4 // ADC Interrupt 3 Flag +#define ADC_INTFLG_ADCINT4 0x8 // ADC Interrupt 4 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTFLGCLR register +// +//***************************************************************************** +#define ADC_INTFLGCLR_ADCINT1 0x1 // ADC Interrupt 1 Flag Clear +#define ADC_INTFLGCLR_ADCINT2 0x2 // ADC Interrupt 2 Flag Clear +#define ADC_INTFLGCLR_ADCINT3 0x4 // ADC Interrupt 3 Flag Clear +#define ADC_INTFLGCLR_ADCINT4 0x8 // ADC Interrupt 4 Flag Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTOVF register +// +//***************************************************************************** +#define ADC_INTOVF_ADCINT1 0x1 // ADC Interrupt 1 Overflow Flags +#define ADC_INTOVF_ADCINT2 0x2 // ADC Interrupt 2 Overflow Flags +#define ADC_INTOVF_ADCINT3 0x4 // ADC Interrupt 3 Overflow Flags +#define ADC_INTOVF_ADCINT4 0x8 // ADC Interrupt 4 Overflow Flags + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTOVFCLR register +// +//***************************************************************************** +#define ADC_INTOVFCLR_ADCINT1 0x1 // ADC Interrupt 1 Overflow Clear + // Bits +#define ADC_INTOVFCLR_ADCINT2 0x2 // ADC Interrupt 2 Overflow Clear + // Bits +#define ADC_INTOVFCLR_ADCINT3 0x4 // ADC Interrupt 3 Overflow Clear + // Bits +#define ADC_INTOVFCLR_ADCINT4 0x8 // ADC Interrupt 4 Overflow Clear + // Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTSEL1N2 register +// +//***************************************************************************** +#define ADC_INTSEL1N2_INT1SEL_S 0 +#define ADC_INTSEL1N2_INT1SEL_M 0xF // ADCINT1 EOC Source Select +#define ADC_INTSEL1N2_INT1E 0x20 // ADCINT1 Interrupt Enable +#define ADC_INTSEL1N2_INT1CONT 0x40 // ADCINT1 Continuous Mode Enable +#define ADC_INTSEL1N2_INT2SEL_S 8 +#define ADC_INTSEL1N2_INT2SEL_M 0xF00 // ADCINT2 EOC Source Select +#define ADC_INTSEL1N2_INT2E 0x2000 // ADCINT2 Interrupt Enable +#define ADC_INTSEL1N2_INT2CONT 0x4000 // ADCINT2 Continuous Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTSEL3N4 register +// +//***************************************************************************** +#define ADC_INTSEL3N4_INT3SEL_S 0 +#define ADC_INTSEL3N4_INT3SEL_M 0xF // ADCINT3 EOC Source Select +#define ADC_INTSEL3N4_INT3E 0x20 // ADCINT3 Interrupt Enable +#define ADC_INTSEL3N4_INT3CONT 0x40 // ADCINT3 Continuous Mode Enable +#define ADC_INTSEL3N4_INT4SEL_S 8 +#define ADC_INTSEL3N4_INT4SEL_M 0xF00 // ADCINT4 EOC Source Select +#define ADC_INTSEL3N4_INT4E 0x2000 // ADCINT4 Interrupt Enable +#define ADC_INTSEL3N4_INT4CONT 0x4000 // ADCINT4 Continuous Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOCPRICTL register +// +//***************************************************************************** +#define ADC_SOCPRICTL_SOCPRIORITY_S 0 +#define ADC_SOCPRICTL_SOCPRIORITY_M 0x1F // SOC Priority +#define ADC_SOCPRICTL_RRPOINTER_S 5 +#define ADC_SOCPRICTL_RRPOINTER_M 0x3E0 // Round Robin Pointer + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTSOCSEL1 register +// +//***************************************************************************** +#define ADC_INTSOCSEL1_SOC0_S 0 +#define ADC_INTSOCSEL1_SOC0_M 0x3 // SOC0 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC1_S 2 +#define ADC_INTSOCSEL1_SOC1_M 0xC // SOC1 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC2_S 4 +#define ADC_INTSOCSEL1_SOC2_M 0x30 // SOC2 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC3_S 6 +#define ADC_INTSOCSEL1_SOC3_M 0xC0 // SOC3 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC4_S 8 +#define ADC_INTSOCSEL1_SOC4_M 0x300 // SOC4 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC5_S 10 +#define ADC_INTSOCSEL1_SOC5_M 0xC00 // SOC5 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC6_S 12 +#define ADC_INTSOCSEL1_SOC6_M 0x3000 // SOC6 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL1_SOC7_S 14 +#define ADC_INTSOCSEL1_SOC7_M 0xC000 // SOC7 ADC Interrupt Trigger + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCINTSOCSEL2 register +// +//***************************************************************************** +#define ADC_INTSOCSEL2_SOC8_S 0 +#define ADC_INTSOCSEL2_SOC8_M 0x3 // SOC8 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC9_S 2 +#define ADC_INTSOCSEL2_SOC9_M 0xC // SOC9 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC10_S 4 +#define ADC_INTSOCSEL2_SOC10_M 0x30 // SOC10 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC11_S 6 +#define ADC_INTSOCSEL2_SOC11_M 0xC0 // SOC11 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC12_S 8 +#define ADC_INTSOCSEL2_SOC12_M 0x300 // SOC12 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC13_S 10 +#define ADC_INTSOCSEL2_SOC13_M 0xC00 // SOC13 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC14_S 12 +#define ADC_INTSOCSEL2_SOC14_M 0x3000 // SOC14 ADC Interrupt Trigger + // Select +#define ADC_INTSOCSEL2_SOC15_S 14 +#define ADC_INTSOCSEL2_SOC15_M 0xC000 // SOC15 ADC Interrupt Trigger + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOCFLG1 register +// +//***************************************************************************** +#define ADC_SOCFLG1_SOC0 0x1 // SOC0 Start of Conversion Flag +#define ADC_SOCFLG1_SOC1 0x2 // SOC1 Start of Conversion Flag +#define ADC_SOCFLG1_SOC2 0x4 // SOC2 Start of Conversion Flag +#define ADC_SOCFLG1_SOC3 0x8 // SOC3 Start of Conversion Flag +#define ADC_SOCFLG1_SOC4 0x10 // SOC4 Start of Conversion Flag +#define ADC_SOCFLG1_SOC5 0x20 // SOC5 Start of Conversion Flag +#define ADC_SOCFLG1_SOC6 0x40 // SOC6 Start of Conversion Flag +#define ADC_SOCFLG1_SOC7 0x80 // SOC7 Start of Conversion Flag +#define ADC_SOCFLG1_SOC8 0x100 // SOC8 Start of Conversion Flag +#define ADC_SOCFLG1_SOC9 0x200 // SOC9 Start of Conversion Flag +#define ADC_SOCFLG1_SOC10 0x400 // SOC10 Start of Conversion Flag +#define ADC_SOCFLG1_SOC11 0x800 // SOC11 Start of Conversion Flag +#define ADC_SOCFLG1_SOC12 0x1000 // SOC12 Start of Conversion Flag +#define ADC_SOCFLG1_SOC13 0x2000 // SOC13 Start of Conversion Flag +#define ADC_SOCFLG1_SOC14 0x4000 // SOC14 Start of Conversion Flag +#define ADC_SOCFLG1_SOC15 0x8000 // SOC15 Start of Conversion Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOCFRC1 register +// +//***************************************************************************** +#define ADC_SOCFRC1_SOC0 0x1 // SOC0 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC1 0x2 // SOC1 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC2 0x4 // SOC2 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC3 0x8 // SOC3 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC4 0x10 // SOC4 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC5 0x20 // SOC5 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC6 0x40 // SOC6 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC7 0x80 // SOC7 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC8 0x100 // SOC8 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC9 0x200 // SOC9 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC10 0x400 // SOC10 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC11 0x800 // SOC11 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC12 0x1000 // SOC12 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC13 0x2000 // SOC13 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC14 0x4000 // SOC14 Force Start of Conversion + // Bit +#define ADC_SOCFRC1_SOC15 0x8000 // SOC15 Force Start of Conversion + // Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOCOVF1 register +// +//***************************************************************************** +#define ADC_SOCOVF1_SOC0 0x1 // SOC0 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC1 0x2 // SOC1 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC2 0x4 // SOC2 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC3 0x8 // SOC3 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC4 0x10 // SOC4 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC5 0x20 // SOC5 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC6 0x40 // SOC6 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC7 0x80 // SOC7 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC8 0x100 // SOC8 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC9 0x200 // SOC9 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC10 0x400 // SOC10 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC11 0x800 // SOC11 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC12 0x1000 // SOC12 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC13 0x2000 // SOC13 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC14 0x4000 // SOC14 Start of Conversion + // Overflow Flag +#define ADC_SOCOVF1_SOC15 0x8000 // SOC15 Start of Conversion + // Overflow Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOCOVFCLR1 register +// +//***************************************************************************** +#define ADC_SOCOVFCLR1_SOC0 0x1 // SOC0 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC1 0x2 // SOC1 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC2 0x4 // SOC2 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC3 0x8 // SOC3 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC4 0x10 // SOC4 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC5 0x20 // SOC5 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC6 0x40 // SOC6 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC7 0x80 // SOC7 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC8 0x100 // SOC8 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC9 0x200 // SOC9 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC10 0x400 // SOC10 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC11 0x800 // SOC11 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC12 0x1000 // SOC12 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC13 0x2000 // SOC13 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC14 0x4000 // SOC14 Clear Start of Conversion + // Overflow Bit +#define ADC_SOCOVFCLR1_SOC15 0x8000 // SOC15 Clear Start of Conversion + // Overflow Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC0CTL register +// +//***************************************************************************** +#define ADC_SOC0CTL_ACQPS_S 0 +#define ADC_SOC0CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC0CTL_CHSEL_S 15 +#define ADC_SOC0CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC0CTL_TRIGSEL_S 20 +#define ADC_SOC0CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC1CTL register +// +//***************************************************************************** +#define ADC_SOC1CTL_ACQPS_S 0 +#define ADC_SOC1CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC1CTL_CHSEL_S 15 +#define ADC_SOC1CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC1CTL_TRIGSEL_S 20 +#define ADC_SOC1CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC2CTL register +// +//***************************************************************************** +#define ADC_SOC2CTL_ACQPS_S 0 +#define ADC_SOC2CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC2CTL_CHSEL_S 15 +#define ADC_SOC2CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC2CTL_TRIGSEL_S 20 +#define ADC_SOC2CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC3CTL register +// +//***************************************************************************** +#define ADC_SOC3CTL_ACQPS_S 0 +#define ADC_SOC3CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC3CTL_CHSEL_S 15 +#define ADC_SOC3CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC3CTL_TRIGSEL_S 20 +#define ADC_SOC3CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC4CTL register +// +//***************************************************************************** +#define ADC_SOC4CTL_ACQPS_S 0 +#define ADC_SOC4CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC4CTL_CHSEL_S 15 +#define ADC_SOC4CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC4CTL_TRIGSEL_S 20 +#define ADC_SOC4CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC5CTL register +// +//***************************************************************************** +#define ADC_SOC5CTL_ACQPS_S 0 +#define ADC_SOC5CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC5CTL_CHSEL_S 15 +#define ADC_SOC5CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC5CTL_TRIGSEL_S 20 +#define ADC_SOC5CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC6CTL register +// +//***************************************************************************** +#define ADC_SOC6CTL_ACQPS_S 0 +#define ADC_SOC6CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC6CTL_CHSEL_S 15 +#define ADC_SOC6CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC6CTL_TRIGSEL_S 20 +#define ADC_SOC6CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC7CTL register +// +//***************************************************************************** +#define ADC_SOC7CTL_ACQPS_S 0 +#define ADC_SOC7CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC7CTL_CHSEL_S 15 +#define ADC_SOC7CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC7CTL_TRIGSEL_S 20 +#define ADC_SOC7CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC8CTL register +// +//***************************************************************************** +#define ADC_SOC8CTL_ACQPS_S 0 +#define ADC_SOC8CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC8CTL_CHSEL_S 15 +#define ADC_SOC8CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC8CTL_TRIGSEL_S 20 +#define ADC_SOC8CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC9CTL register +// +//***************************************************************************** +#define ADC_SOC9CTL_ACQPS_S 0 +#define ADC_SOC9CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC9CTL_CHSEL_S 15 +#define ADC_SOC9CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC9CTL_TRIGSEL_S 20 +#define ADC_SOC9CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC10CTL register +// +//***************************************************************************** +#define ADC_SOC10CTL_ACQPS_S 0 +#define ADC_SOC10CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC10CTL_CHSEL_S 15 +#define ADC_SOC10CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC10CTL_TRIGSEL_S 20 +#define ADC_SOC10CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC11CTL register +// +//***************************************************************************** +#define ADC_SOC11CTL_ACQPS_S 0 +#define ADC_SOC11CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC11CTL_CHSEL_S 15 +#define ADC_SOC11CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC11CTL_TRIGSEL_S 20 +#define ADC_SOC11CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC12CTL register +// +//***************************************************************************** +#define ADC_SOC12CTL_ACQPS_S 0 +#define ADC_SOC12CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC12CTL_CHSEL_S 15 +#define ADC_SOC12CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC12CTL_TRIGSEL_S 20 +#define ADC_SOC12CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC13CTL register +// +//***************************************************************************** +#define ADC_SOC13CTL_ACQPS_S 0 +#define ADC_SOC13CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC13CTL_CHSEL_S 15 +#define ADC_SOC13CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC13CTL_TRIGSEL_S 20 +#define ADC_SOC13CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC14CTL register +// +//***************************************************************************** +#define ADC_SOC14CTL_ACQPS_S 0 +#define ADC_SOC14CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC14CTL_CHSEL_S 15 +#define ADC_SOC14CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC14CTL_TRIGSEL_S 20 +#define ADC_SOC14CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCSOC15CTL register +// +//***************************************************************************** +#define ADC_SOC15CTL_ACQPS_S 0 +#define ADC_SOC15CTL_ACQPS_M 0x1FF // SOC Acquisition Prescale +#define ADC_SOC15CTL_CHSEL_S 15 +#define ADC_SOC15CTL_CHSEL_M 0x78000 // SOC Channel Select +#define ADC_SOC15CTL_TRIGSEL_S 20 +#define ADC_SOC15CTL_TRIGSEL_M 0x1F00000 // SOC Trigger Source Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCEVTSTAT register +// +//***************************************************************************** +#define ADC_EVTSTAT_PPB1TRIPHI 0x1 // Post Processing Block 1 Trip + // High Flag +#define ADC_EVTSTAT_PPB1TRIPLO 0x2 // Post Processing Block 1 Trip + // Low Flag +#define ADC_EVTSTAT_PPB1ZERO 0x4 // Post Processing Block 1 Zero + // Crossing Flag +#define ADC_EVTSTAT_PPB2TRIPHI 0x10 // Post Processing Block 2 Trip + // High Flag +#define ADC_EVTSTAT_PPB2TRIPLO 0x20 // Post Processing Block 2 Trip + // Low Flag +#define ADC_EVTSTAT_PPB2ZERO 0x40 // Post Processing Block 2 Zero + // Crossing Flag +#define ADC_EVTSTAT_PPB3TRIPHI 0x100 // Post Processing Block 3 Trip + // High Flag +#define ADC_EVTSTAT_PPB3TRIPLO 0x200 // Post Processing Block 3 Trip + // Low Flag +#define ADC_EVTSTAT_PPB3ZERO 0x400 // Post Processing Block 3 Zero + // Crossing Flag +#define ADC_EVTSTAT_PPB4TRIPHI 0x1000 // Post Processing Block 4 Trip + // High Flag +#define ADC_EVTSTAT_PPB4TRIPLO 0x2000 // Post Processing Block 4 Trip + // Low Flag +#define ADC_EVTSTAT_PPB4ZERO 0x4000 // Post Processing Block 4 Zero + // Crossing Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCEVTCLR register +// +//***************************************************************************** +#define ADC_EVTCLR_PPB1TRIPHI 0x1 // Post Processing Block 1 Trip + // High Clear +#define ADC_EVTCLR_PPB1TRIPLO 0x2 // Post Processing Block 1 Trip + // Low Clear +#define ADC_EVTCLR_PPB1ZERO 0x4 // Post Processing Block 1 Zero + // Crossing Clear +#define ADC_EVTCLR_PPB2TRIPHI 0x10 // Post Processing Block 2 Trip + // High Clear +#define ADC_EVTCLR_PPB2TRIPLO 0x20 // Post Processing Block 2 Trip + // Low Clear +#define ADC_EVTCLR_PPB2ZERO 0x40 // Post Processing Block 2 Zero + // Crossing Clear +#define ADC_EVTCLR_PPB3TRIPHI 0x100 // Post Processing Block 3 Trip + // High Clear +#define ADC_EVTCLR_PPB3TRIPLO 0x200 // Post Processing Block 3 Trip + // Low Clear +#define ADC_EVTCLR_PPB3ZERO 0x400 // Post Processing Block 3 Zero + // Crossing Clear +#define ADC_EVTCLR_PPB4TRIPHI 0x1000 // Post Processing Block 4 Trip + // High Clear +#define ADC_EVTCLR_PPB4TRIPLO 0x2000 // Post Processing Block 4 Trip + // Low Clear +#define ADC_EVTCLR_PPB4ZERO 0x4000 // Post Processing Block 4 Zero + // Crossing Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCEVTSEL register +// +//***************************************************************************** +#define ADC_EVTSEL_PPB1TRIPHI 0x1 // Post Processing Block 1 Trip + // High Event Enable +#define ADC_EVTSEL_PPB1TRIPLO 0x2 // Post Processing Block 1 Trip + // Low Event Enable +#define ADC_EVTSEL_PPB1ZERO 0x4 // Post Processing Block 1 Zero + // Crossing Event Enable +#define ADC_EVTSEL_PPB2TRIPHI 0x10 // Post Processing Block 2 Trip + // High Event Enable +#define ADC_EVTSEL_PPB2TRIPLO 0x20 // Post Processing Block 2 Trip + // Low Event Enable +#define ADC_EVTSEL_PPB2ZERO 0x40 // Post Processing Block 2 Zero + // Crossing Event Enable +#define ADC_EVTSEL_PPB3TRIPHI 0x100 // Post Processing Block 3 Trip + // High Event Enable +#define ADC_EVTSEL_PPB3TRIPLO 0x200 // Post Processing Block 3 Trip + // Low Event Enable +#define ADC_EVTSEL_PPB3ZERO 0x400 // Post Processing Block 3 Zero + // Crossing Event Enable +#define ADC_EVTSEL_PPB4TRIPHI 0x1000 // Post Processing Block 4 Trip + // High Event Enable +#define ADC_EVTSEL_PPB4TRIPLO 0x2000 // Post Processing Block 4 Trip + // Low Event Enable +#define ADC_EVTSEL_PPB4ZERO 0x4000 // Post Processing Block 4 Zero + // Crossing Event Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCEVTINTSEL register +// +//***************************************************************************** +#define ADC_EVTINTSEL_PPB1TRIPHI 0x1 // Post Processing Block 1 Trip + // High Interrupt Enable +#define ADC_EVTINTSEL_PPB1TRIPLO 0x2 // Post Processing Block 1 Trip + // Low Interrupt Enable +#define ADC_EVTINTSEL_PPB1ZERO 0x4 // Post Processing Block 1 Zero + // Crossing Interrupt Enable +#define ADC_EVTINTSEL_PPB2TRIPHI 0x10 // Post Processing Block 2 Trip + // High Interrupt Enable +#define ADC_EVTINTSEL_PPB2TRIPLO 0x20 // Post Processing Block 2 Trip + // Low Interrupt Enable +#define ADC_EVTINTSEL_PPB2ZERO 0x40 // Post Processing Block 2 Zero + // Crossing Interrupt Enable +#define ADC_EVTINTSEL_PPB3TRIPHI 0x100 // Post Processing Block 3 Trip + // High Interrupt Enable +#define ADC_EVTINTSEL_PPB3TRIPLO 0x200 // Post Processing Block 3 Trip + // Low Interrupt Enable +#define ADC_EVTINTSEL_PPB3ZERO 0x400 // Post Processing Block 3 Zero + // Crossing Interrupt Enable +#define ADC_EVTINTSEL_PPB4TRIPHI 0x1000 // Post Processing Block 4 Trip + // High Interrupt Enable +#define ADC_EVTINTSEL_PPB4TRIPLO 0x2000 // Post Processing Block 4 Trip + // Low Interrupt Enable +#define ADC_EVTINTSEL_PPB4ZERO 0x4000 // Post Processing Block 4 Zero + // Crossing Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCCOUNTER register +// +//***************************************************************************** +#define ADC_COUNTER_FREECOUNT_S 0 +#define ADC_COUNTER_FREECOUNT_M 0xFFF // ADC Free Running Counter Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCREV register +// +//***************************************************************************** +#define ADC_REV_TYPE_S 0 +#define ADC_REV_TYPE_M 0xFF // ADC Type +#define ADC_REV_REV_S 8 +#define ADC_REV_REV_M 0xFF00 // ADC Revision + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCOFFTRIM register +// +//***************************************************************************** +#define ADC_OFFTRIM_OFFTRIM_S 0 +#define ADC_OFFTRIM_OFFTRIM_M 0xFF // ADC Offset Trim + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1CONFIG register +// +//***************************************************************************** +#define ADC_PPB1CONFIG_CONFIG_S 0 +#define ADC_PPB1CONFIG_CONFIG_M 0xF // ADC Post Processing Block + // Configuration +#define ADC_PPB1CONFIG_TWOSCOMPEN 0x10 // ADC Post Processing Block Two's + // Complement Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1STAMP register +// +//***************************************************************************** +#define ADC_PPB1STAMP_DLYSTAMP_S 0 +#define ADC_PPB1STAMP_DLYSTAMP_M 0xFFF // ADC Post Processing Block Delay + // Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1OFFCAL register +// +//***************************************************************************** +#define ADC_PPB1OFFCAL_OFFCAL_S 0 +#define ADC_PPB1OFFCAL_OFFCAL_M 0x3FF // ADC Post Processing Block + // Offset Correction + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1OFFREF register +// +//***************************************************************************** +#define ADC_PPB1OFFREF_OFFREF_S 0 +#define ADC_PPB1OFFREF_OFFREF_M 0xFFFF // ADC Post Processing Block + // Offset Reference + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1TRIPHI register +// +//***************************************************************************** +#define ADC_PPB1TRIPHI_LIMITHI_S 0 +#define ADC_PPB1TRIPHI_LIMITHI_M 0xFFFF // ADC Post Processing Block Trip + // High Limit +#define ADC_PPB1TRIPHI_HSIGN 0x10000 // High Limit Sign Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1TRIPLO register +// +//***************************************************************************** +#define ADC_PPB1TRIPLO_LIMITLO_S 0 +#define ADC_PPB1TRIPLO_LIMITLO_M 0xFFFF // ADC Post Processing Block Trip + // Low Limit +#define ADC_PPB1TRIPLO_LSIGN 0x10000 // Low Limit Sign Bit +#define ADC_PPB1TRIPLO_REQSTAMP_S 20 +#define ADC_PPB1TRIPLO_REQSTAMP_M 0xFFF00000 // ADC Post Processing Block + // Request Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2CONFIG register +// +//***************************************************************************** +#define ADC_PPB2CONFIG_CONFIG_S 0 +#define ADC_PPB2CONFIG_CONFIG_M 0xF // ADC Post Processing Block + // Configuration +#define ADC_PPB2CONFIG_TWOSCOMPEN 0x10 // ADC Post Processing Block Two's + // Complement Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2STAMP register +// +//***************************************************************************** +#define ADC_PPB2STAMP_DLYSTAMP_S 0 +#define ADC_PPB2STAMP_DLYSTAMP_M 0xFFF // ADC Post Processing Block Delay + // Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2OFFCAL register +// +//***************************************************************************** +#define ADC_PPB2OFFCAL_OFFCAL_S 0 +#define ADC_PPB2OFFCAL_OFFCAL_M 0x3FF // ADC Post Processing Block + // Offset Correction + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2OFFREF register +// +//***************************************************************************** +#define ADC_PPB2OFFREF_OFFREF_S 0 +#define ADC_PPB2OFFREF_OFFREF_M 0xFFFF // ADC Post Processing Block + // Offset Reference + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2TRIPHI register +// +//***************************************************************************** +#define ADC_PPB2TRIPHI_LIMITHI_S 0 +#define ADC_PPB2TRIPHI_LIMITHI_M 0xFFFF // ADC Post Processing Block Trip + // High Limit +#define ADC_PPB2TRIPHI_HSIGN 0x10000 // High Limit Sign Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2TRIPLO register +// +//***************************************************************************** +#define ADC_PPB2TRIPLO_LIMITLO_S 0 +#define ADC_PPB2TRIPLO_LIMITLO_M 0xFFFF // ADC Post Processing Block Trip + // Low Limit +#define ADC_PPB2TRIPLO_LSIGN 0x10000 // Low Limit Sign Bit +#define ADC_PPB2TRIPLO_REQSTAMP_S 20 +#define ADC_PPB2TRIPLO_REQSTAMP_M 0xFFF00000 // ADC Post Processing Block + // Request Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3CONFIG register +// +//***************************************************************************** +#define ADC_PPB3CONFIG_CONFIG_S 0 +#define ADC_PPB3CONFIG_CONFIG_M 0xF // ADC Post Processing Block + // Configuration +#define ADC_PPB3CONFIG_TWOSCOMPEN 0x10 // ADC Post Processing Block Two's + // Complement Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3STAMP register +// +//***************************************************************************** +#define ADC_PPB3STAMP_DLYSTAMP_S 0 +#define ADC_PPB3STAMP_DLYSTAMP_M 0xFFF // ADC Post Processing Block Delay + // Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3OFFCAL register +// +//***************************************************************************** +#define ADC_PPB3OFFCAL_OFFCAL_S 0 +#define ADC_PPB3OFFCAL_OFFCAL_M 0x3FF // ADC Post Processing Block + // Offset Correction + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3OFFREF register +// +//***************************************************************************** +#define ADC_PPB3OFFREF_OFFREF_S 0 +#define ADC_PPB3OFFREF_OFFREF_M 0xFFFF // ADC Post Processing Block + // Offset Reference + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3TRIPHI register +// +//***************************************************************************** +#define ADC_PPB3TRIPHI_LIMITHI_S 0 +#define ADC_PPB3TRIPHI_LIMITHI_M 0xFFFF // ADC Post Processing Block Trip + // High Limit +#define ADC_PPB3TRIPHI_HSIGN 0x10000 // High Limit Sign Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3TRIPLO register +// +//***************************************************************************** +#define ADC_PPB3TRIPLO_LIMITLO_S 0 +#define ADC_PPB3TRIPLO_LIMITLO_M 0xFFFF // ADC Post Processing Block Trip + // Low Limit +#define ADC_PPB3TRIPLO_LSIGN 0x10000 // Low Limit Sign Bit +#define ADC_PPB3TRIPLO_REQSTAMP_S 20 +#define ADC_PPB3TRIPLO_REQSTAMP_M 0xFFF00000 // ADC Post Processing Block + // Request Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4CONFIG register +// +//***************************************************************************** +#define ADC_PPB4CONFIG_CONFIG_S 0 +#define ADC_PPB4CONFIG_CONFIG_M 0xF // ADC Post Processing Block + // Configuration +#define ADC_PPB4CONFIG_TWOSCOMPEN 0x10 // ADC Post Processing Block Two's + // Complement Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4STAMP register +// +//***************************************************************************** +#define ADC_PPB4STAMP_DLYSTAMP_S 0 +#define ADC_PPB4STAMP_DLYSTAMP_M 0xFFF // ADC Post Processing Block Delay + // Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4OFFCAL register +// +//***************************************************************************** +#define ADC_PPB4OFFCAL_OFFCAL_S 0 +#define ADC_PPB4OFFCAL_OFFCAL_M 0x3FF // ADC Post Processing Block + // Offset Correction + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4OFFREF register +// +//***************************************************************************** +#define ADC_PPB4OFFREF_OFFREF_S 0 +#define ADC_PPB4OFFREF_OFFREF_M 0xFFFF // ADC Post Processing Block + // Offset Reference + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4TRIPHI register +// +//***************************************************************************** +#define ADC_PPB4TRIPHI_LIMITHI_S 0 +#define ADC_PPB4TRIPHI_LIMITHI_M 0xFFFF // ADC Post Processing Block Trip + // High Limit +#define ADC_PPB4TRIPHI_HSIGN 0x10000 // High Limit Sign Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4TRIPLO register +// +//***************************************************************************** +#define ADC_PPB4TRIPLO_LIMITLO_S 0 +#define ADC_PPB4TRIPLO_LIMITLO_M 0xFFFF // ADC Post Processing Block Trip + // Low Limit +#define ADC_PPB4TRIPLO_LSIGN 0x10000 // Low Limit Sign Bit +#define ADC_PPB4TRIPLO_REQSTAMP_S 20 +#define ADC_PPB4TRIPLO_REQSTAMP_M 0xFFF00000 // ADC Post Processing Block + // Request Time Stamp + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT0 register +// +//***************************************************************************** +#define ADC_RESULT0_RESULT_S 0 +#define ADC_RESULT0_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT1 register +// +//***************************************************************************** +#define ADC_RESULT1_RESULT_S 0 +#define ADC_RESULT1_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT2 register +// +//***************************************************************************** +#define ADC_RESULT2_RESULT_S 0 +#define ADC_RESULT2_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT3 register +// +//***************************************************************************** +#define ADC_RESULT3_RESULT_S 0 +#define ADC_RESULT3_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT4 register +// +//***************************************************************************** +#define ADC_RESULT4_RESULT_S 0 +#define ADC_RESULT4_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT5 register +// +//***************************************************************************** +#define ADC_RESULT5_RESULT_S 0 +#define ADC_RESULT5_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT6 register +// +//***************************************************************************** +#define ADC_RESULT6_RESULT_S 0 +#define ADC_RESULT6_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT7 register +// +//***************************************************************************** +#define ADC_RESULT7_RESULT_S 0 +#define ADC_RESULT7_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT8 register +// +//***************************************************************************** +#define ADC_RESULT8_RESULT_S 0 +#define ADC_RESULT8_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT9 register +// +//***************************************************************************** +#define ADC_RESULT9_RESULT_S 0 +#define ADC_RESULT9_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT10 register +// +//***************************************************************************** +#define ADC_RESULT10_RESULT_S 0 +#define ADC_RESULT10_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT11 register +// +//***************************************************************************** +#define ADC_RESULT11_RESULT_S 0 +#define ADC_RESULT11_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT12 register +// +//***************************************************************************** +#define ADC_RESULT12_RESULT_S 0 +#define ADC_RESULT12_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT13 register +// +//***************************************************************************** +#define ADC_RESULT13_RESULT_S 0 +#define ADC_RESULT13_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT14 register +// +//***************************************************************************** +#define ADC_RESULT14_RESULT_S 0 +#define ADC_RESULT14_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCRESULT15 register +// +//***************************************************************************** +#define ADC_RESULT15_RESULT_S 0 +#define ADC_RESULT15_RESULT_M 0xFFFF // ADC Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB1RESULT register +// +//***************************************************************************** +#define ADC_PPB1RESULT_PPBRESULT_S 0 +#define ADC_PPB1RESULT_PPBRESULT_M 0xFFFF // ADC Post Processing Block + // Result +#define ADC_PPB1RESULT_SIGN_S 16 +#define ADC_PPB1RESULT_SIGN_M 0xFFFF0000 // Sign Extended Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB2RESULT register +// +//***************************************************************************** +#define ADC_PPB2RESULT_PPBRESULT_S 0 +#define ADC_PPB2RESULT_PPBRESULT_M 0xFFFF // ADC Post Processing Block + // Result +#define ADC_PPB2RESULT_SIGN_S 16 +#define ADC_PPB2RESULT_SIGN_M 0xFFFF0000 // Sign Extended Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB3RESULT register +// +//***************************************************************************** +#define ADC_PPB3RESULT_PPBRESULT_S 0 +#define ADC_PPB3RESULT_PPBRESULT_M 0xFFFF // ADC Post Processing Block + // Result +#define ADC_PPB3RESULT_SIGN_S 16 +#define ADC_PPB3RESULT_SIGN_M 0xFFFF0000 // Sign Extended Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADCPPB4RESULT register +// +//***************************************************************************** +#define ADC_PPB4RESULT_PPBRESULT_S 0 +#define ADC_PPB4RESULT_PPBRESULT_M 0xFFFF // ADC Post Processing Block + // Result +#define ADC_PPB4RESULT_SIGN_S 16 +#define ADC_PPB4RESULT_SIGN_M 0xFFFF0000 // Sign Extended Bits +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_can.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_can.h new file mode 100644 index 00000000000..f421a0caf86 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_can.h @@ -0,0 +1,612 @@ +//########################################################################### +// +// FILE: hw_can.h +// +// TITLE: Definitions for the C28x CAN registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_CAN_H__ +#define __HW_CAN_H__ + +//***************************************************************************** +// +// The following are defines for the CAN register offsets +// +//***************************************************************************** +#define CAN_O_CTL 0x0 // CAN Control Register +#define CAN_O_ES 0x4 // Error and Status Register +#define CAN_O_ERRC 0x8 // Error Counter Register +#define CAN_O_BTR 0xC // Bit Timing Register +#define CAN_O_INT 0x10 // Interrupt Register +#define CAN_O_TEST 0x14 // Test Register +#define CAN_O_PERR 0x1C // CAN Parity Error Code Register +#define CAN_O_REL 0x20 // CAN Core Release Register +#define CAN_O_RAM_INIT 0x40 // CAN RAM Initialization Register +#define CAN_O_GLB_INT_EN 0x50 // CAN Global Interrupt Enable + // Register +#define CAN_O_GLB_INT_FLG 0x54 // CAN Global Interrupt Flag + // Register +#define CAN_O_GLB_INT_CLR 0x58 // CAN Global Interrupt Clear + // Register +#define CAN_O_ABOTR 0x80 // Auto-Bus-On Time Register +#define CAN_O_TXRQ_X 0x84 // CAN Transmission Request X + // Register +#define CAN_O_TXRQ_21 0x88 // CAN Transmission Request 2_1 + // Register +#define CAN_O_NDAT_X 0x98 // CAN New Data X Register +#define CAN_O_NDAT_21 0x9C // CAN New Data 2_1 Register +#define CAN_O_IPEN_X 0xAC // CAN Interrupt Pending X + // Register +#define CAN_O_IPEN_21 0xB0 // CAN Interrupt Pending 2_1 + // Register +#define CAN_O_MVAL_X 0xC0 // CAN Message Valid X Register +#define CAN_O_MVAL_21 0xC4 // CAN Message Valid 2_1 Register +#define CAN_O_IP_MUX21 0xD8 // CAN Interrupt Multiplexer 2_1 + // Register +#define CAN_O_IF1CMD 0x100 // IF1 Command Register +#define CAN_O_IF1MSK 0x104 // IF1 Mask Register +#define CAN_O_IF1ARB 0x108 // IF1 Arbitration Register +#define CAN_O_IF1MCTL 0x10C // IF1 Message Control Register +#define CAN_O_IF1DATA 0x110 // IF1 Data A Register +#define CAN_O_IF1DATB 0x114 // IF1 Data B Register +#define CAN_O_IF2CMD 0x120 // IF2 Command Register +#define CAN_O_IF2MSK 0x124 // IF2 Mask Register +#define CAN_O_IF2ARB 0x128 // IF2 Arbitration Register +#define CAN_O_IF2MCTL 0x12C // IF2 Message Control Register +#define CAN_O_IF2DATA 0x130 // IF2 Data A Register +#define CAN_O_IF2DATB 0x134 // IF2 Data B Register +#define CAN_O_IF3OBS 0x140 // IF3 Observation Register +#define CAN_O_IF3MSK 0x144 // IF3 Mask Register +#define CAN_O_IF3ARB 0x148 // IF3 Arbitration Register +#define CAN_O_IF3MCTL 0x14C // IF3 Message Control Register +#define CAN_O_IF3DATA 0x150 // IF3 Data A Register +#define CAN_O_IF3DATB 0x154 // IF3 Data B Register +#define CAN_O_IF3UPD 0x160 // IF3 Update Enable Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_CTL register +// +//***************************************************************************** +#define CAN_CTL_INIT 0x1 // Initialization +#define CAN_CTL_IE0 0x2 // Interrupt line 0 Enable + // Disabled +#define CAN_CTL_SIE 0x4 // Status Change Interrupt Enable + // Disabled +#define CAN_CTL_EIE 0x8 // Error Interrupt Enable Disabled +#define CAN_CTL_DAR 0x20 // Disable Automatic + // Retransmission +#define CAN_CTL_CCE 0x40 // Configuration Change Enable +#define CAN_CTL_TEST 0x80 // Test Mode Enable +#define CAN_CTL_IDS 0x100 // Interruption Debug Support + // Enable +#define CAN_CTL_ABO 0x200 // Auto-Bus-On Enable +#define CAN_CTL_PMD_S 10 +#define CAN_CTL_PMD_M 0x3C00 // Parity on/off +#define CAN_CTL_SWR 0x8000 // SW Reset Enable +#define CAN_CTL_INITDBG 0x10000 // Debug Mode Status +#define CAN_CTL_IE1 0x20000 // Interrupt line 1 Enable + // Disabled +#define CAN_CTL_PDR 0x1000000 // Power Down Request Mode +#define CAN_CTL_WUBA 0x2000000 // Wake Up on Bus Activity + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_ES register +// +//***************************************************************************** +#define CAN_ES_LEC_S 0 +#define CAN_ES_LEC_M 0x7 // Last Error Code +#define CAN_ES_TXOK 0x8 // Transmission status +#define CAN_ES_RXOK 0x10 // Reception status +#define CAN_ES_EPASS 0x20 // Error Passive State +#define CAN_ES_EWARN 0x40 // Warning State +#define CAN_ES_BOFF 0x80 // Bus-Off State +#define CAN_ES_PER 0x100 // Parity Error Detected +#define CAN_ES_WAKEUPPND 0x200 // Wake Up Pending +#define CAN_ES_PDA 0x400 // Power down mode acknowledge + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_ERRC register +// +//***************************************************************************** +#define CAN_ERRC_TEC_S 0 +#define CAN_ERRC_TEC_M 0xFF // Transmit Error Counter +#define CAN_ERRC_REC_S 8 +#define CAN_ERRC_REC_M 0x7F00 // Receive Error Counter +#define CAN_ERRC_RP 0x8000 // Receive Error Passive + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_BTR register +// +//***************************************************************************** +#define CAN_BTR_BRP_S 0 +#define CAN_BTR_BRP_M 0x3F // Baud Rate Prescaler +#define CAN_BTR_SJW_S 6 +#define CAN_BTR_SJW_M 0xC0 // Synchronization Jump Width +#define CAN_BTR_TSEG1_S 8 +#define CAN_BTR_TSEG1_M 0xF00 // Time segment +#define CAN_BTR_TSEG2_S 12 +#define CAN_BTR_TSEG2_M 0x7000 // Time segment +#define CAN_BTR_BRPE_S 16 +#define CAN_BTR_BRPE_M 0xF0000 // Baud Rate Prescaler Extension + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_INT register +// +//***************************************************************************** +#define CAN_INT_INT0ID_S 0 +#define CAN_INT_INT0ID_M 0xFFFF // Interrupt Identifier +#define CAN_INT_INT1ID_S 16 +#define CAN_INT_INT1ID_M 0xFF0000 // Interrupt 1 Identifier + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TEST register +// +//***************************************************************************** +#define CAN_TEST_SILENT 0x8 // Silent Mode +#define CAN_TEST_LBACK 0x10 // Loopback Mode +#define CAN_TEST_TX_S 5 +#define CAN_TEST_TX_M 0x60 // CANTX Pin Control +#define CAN_TEST_RX 0x80 // CANRX Pin Status +#define CAN_TEST_EXL 0x100 // External Loopback Mode +#define CAN_TEST_RDA 0x200 // RAM Direct Access Enable: + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_PERR register +// +//***************************************************************************** +#define CAN_PERR_MSG_NUM_S 0 +#define CAN_PERR_MSG_NUM_M 0xFF // Message Number +#define CAN_PERR_WORD_NUM_S 8 +#define CAN_PERR_WORD_NUM_M 0x700 // Word Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_REL register +// +//***************************************************************************** +#define CAN_REL_DAY_S 0 +#define CAN_REL_DAY_M 0xFF // Day +#define CAN_REL_MON_S 8 +#define CAN_REL_MON_M 0xFF00 // Month +#define CAN_REL_YEAR_S 16 +#define CAN_REL_YEAR_M 0xF0000 // Year +#define CAN_REL_SUBSTEP_S 20 +#define CAN_REL_SUBSTEP_M 0xF00000 // Substep +#define CAN_REL_STEP_S 24 +#define CAN_REL_STEP_M 0xF000000 // Step +#define CAN_REL_REL_S 28 +#define CAN_REL_REL_M 0xF0000000 // Release + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_RAM_INIT register +// +//***************************************************************************** +#define CAN_RAM_INIT_KEY0 0x1 // KEY0 +#define CAN_RAM_INIT_KEY1 0x2 // KEY1 +#define CAN_RAM_INIT_KEY2 0x4 // KEY2 +#define CAN_RAM_INIT_KEY3 0x8 // KEY3 +#define CAN_RAM_INIT_CAN_RAM_INIT 0x10 // Initialize CAN Mailbox RAM +#define CAN_RAM_INIT_RAM_INIT_DONE 0x20 // CAN RAM initialization complete + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_GLB_INT_EN register +// +//***************************************************************************** +#define CAN_GLB_INT_CANINT0 0x1 // Global Interrupt Enable for CAN INT0 +#define CAN_GLB_INT_CANINT1 0x2 // Global Interrupt Enable for CAN INT1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_GLB_INT_FLG register +// +//***************************************************************************** +#define CAN_GLB_INT_FLG_NAME 0x1 // Global Interrupt Flag for CAN + // INT0 +#define CAN_GLB_INT_FLG_INT1_FLG 0x2 // Global Interrupt Flag for CAN + // INT1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_GLB_INT_CLR register +// +//***************************************************************************** +#define CAN_GLB_INT_CLR_INT0_FLG_CLR 0x1 // Global Interrupt flag clear for + // CAN INT0 +#define CAN_GLB_INT_CLR_INT1_FLG_CLR 0x2 // Global Interrupt flag clear + // for CAN INT1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_ABOTR register +// +//***************************************************************************** +#define CAN_ABOTR_ABO_TIME_S 0 +#define CAN_ABOTR_ABO_TIME_M 0xFFFFFFFF // Auto-Bus-On Timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TXRQ_X register +// +//***************************************************************************** +#define CAN_TXRQ_X_TXRQSTREG1_S 0 +#define CAN_TXRQ_X_TXRQSTREG1_M 0x3 // Transmit Request Register 1 +#define CAN_TXRQ_X_TXRQSTREG2_S 2 +#define CAN_TXRQ_X_TXRQSTREG2_M 0xC // Transmit Request Register 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_TXRQ_21 register +// +//***************************************************************************** +#define CAN_TXRQ_21_TXRQST_S 0 +#define CAN_TXRQ_21_TXRQST_M 0xFFFFFFFF // Transmission Request Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_NDAT_X register +// +//***************************************************************************** +#define CAN_NDAT_X_NEWDATREG1_S 0 +#define CAN_NDAT_X_NEWDATREG1_M 0x3 // New Data Register 1 +#define CAN_NDAT_X_NEWDATREG2_S 2 +#define CAN_NDAT_X_NEWDATREG2_M 0xC // New Data Register 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_NDAT_21 register +// +//***************************************************************************** +#define CAN_NDAT_21_NEWDAT_S 0 +#define CAN_NDAT_21_NEWDAT_M 0xFFFFFFFF // New Data Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IPEN_X register +// +//***************************************************************************** +#define CAN_IPEN_X_INTPNDREG1_S 0 +#define CAN_IPEN_X_INTPNDREG1_M 0x3 // Interrupt Pending Register 1 +#define CAN_IPEN_X_INTPNDREG2_S 2 +#define CAN_IPEN_X_INTPNDREG2_M 0xC // Interrupt Pending Register 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IPEN_21 register +// +//***************************************************************************** +#define CAN_IPEN_21_INTPND_S 0 +#define CAN_IPEN_21_INTPND_M 0xFFFFFFFF // Interrupt Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_MVAL_X register +// +//***************************************************************************** +#define CAN_MVAL_X_MSGVALREG1_S 0 +#define CAN_MVAL_X_MSGVALREG1_M 0x3 // Message Valid Register 1 +#define CAN_MVAL_X_MSGVALREG2_S 2 +#define CAN_MVAL_X_MSGVALREG2_M 0xC // Message Valid Register 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_MVAL_21 register +// +//***************************************************************************** +#define CAN_MVAL_21_MSGVALREG_S 0 +#define CAN_MVAL_21_MSGVALREG_M 0xFFFFFFFF // Message Valid Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IP_MUX21 register +// +//***************************************************************************** +#define CAN_IP_MUX21_INTMUX_S 0 +#define CAN_IP_MUX21_INTMUX_M 0xFFFFFFFF // Interrupt Mux + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1CMD register +// +//***************************************************************************** +#define CAN_IF1CMD_MSG_NUM_S 0 +#define CAN_IF1CMD_MSG_NUM_M 0xFF // Message Number +#define CAN_IF1CMD_BUSY 0x8000 // Busy Flag +#define CAN_IF1CMD_DATA_B 0x10000 // Access Data Bytes 4-7 +#define CAN_IF1CMD_DATA_A 0x20000 // Access Data Bytes 0-3 +#define CAN_IF1CMD_TXRQST 0x40000 // Access Transmission Request Bit +#define CAN_IF1CMD_CLRINTPND 0x80000 // Clear Interrupt Pending Bit +#define CAN_IF1CMD_CONTROL 0x100000 // Access Control Bits +#define CAN_IF1CMD_ARB 0x200000 // Access Arbitration Bits +#define CAN_IF1CMD_MASK 0x400000 // Access Mask Bits +#define CAN_IF1CMD_DIR 0x800000 // Write/Read Direction + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1MSK register +// +//***************************************************************************** +#define CAN_IF1MSK_MSK_S 0 +#define CAN_IF1MSK_MSK_M 0x1FFFFFFF // Identifier Mask +#define CAN_IF1MSK_MDIR 0x40000000 // Mask Message Direction +#define CAN_IF1MSK_MXTD 0x80000000 // Mask Extended Identifier + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1ARB register +// +//***************************************************************************** +#define CAN_IF1ARB_ID_S 0 +#define CAN_IF1ARB_ID_M 0x1FFFFFFF // ` +#define CAN_IF1ARB_DIR 0x20000000 // Message Direction +#define CAN_IF1ARB_XTD 0x40000000 // Extended Identifier +#define CAN_IF1ARB_MSGVAL 0x80000000 // Message Valid + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1MCTL register +// +//***************************************************************************** +#define CAN_IF1MCTL_DLC_S 0 +#define CAN_IF1MCTL_DLC_M 0xF // Data length code +#define CAN_IF1MCTL_EOB 0x80 // End of Block +#define CAN_IF1MCTL_TXRQST 0x100 // Transmit Request +#define CAN_IF1MCTL_RMTEN 0x200 // Remote Enable +#define CAN_IF1MCTL_RXIE 0x400 // Receive Interrupt Enable +#define CAN_IF1MCTL_TXIE 0x800 // Transmit Interrupt Enable +#define CAN_IF1MCTL_UMASK 0x1000 // Use Acceptance Mask +#define CAN_IF1MCTL_INTPND 0x2000 // Interrupt Pending +#define CAN_IF1MCTL_MSGLST 0x4000 // Message Lost +#define CAN_IF1MCTL_NEWDAT 0x8000 // New Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1DATA register +// +//***************************************************************************** +#define CAN_IF1DATA_DATA_0_S 0 +#define CAN_IF1DATA_DATA_0_M 0xFF // Data Byte 0 +#define CAN_IF1DATA_DATA_1_S 8 +#define CAN_IF1DATA_DATA_1_M 0xFF00 // Data Byte 1 +#define CAN_IF1DATA_DATA_2_S 16 +#define CAN_IF1DATA_DATA_2_M 0xFF0000 // Data Byte 2 +#define CAN_IF1DATA_DATA_3_S 24 +#define CAN_IF1DATA_DATA_3_M 0xFF000000 // Data Byte 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF1DATB register +// +//***************************************************************************** +#define CAN_IF1DATB_DATA_4_S 0 +#define CAN_IF1DATB_DATA_4_M 0xFF // Data Byte 4 +#define CAN_IF1DATB_DATA_5_S 8 +#define CAN_IF1DATB_DATA_5_M 0xFF00 // Data Byte 5 +#define CAN_IF1DATB_DATA_6_S 16 +#define CAN_IF1DATB_DATA_6_M 0xFF0000 // Data Byte 6 +#define CAN_IF1DATB_DATA_7_S 24 +#define CAN_IF1DATB_DATA_7_M 0xFF000000 // Data Byte 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2CMD register +// +//***************************************************************************** +#define CAN_IF2CMD_MSG_NUM_S 0 +#define CAN_IF2CMD_MSG_NUM_M 0xFF // Message Number +#define CAN_IF2CMD_BUSY 0x8000 // Busy Flag +#define CAN_IF2CMD_DATA_B 0x10000 // Access Data Bytes 4-7 +#define CAN_IF2CMD_DATA_A 0x20000 // Access Data Bytes 0-3 +#define CAN_IF2CMD_TXRQST 0x40000 // Access Transmission Request Bit +#define CAN_IF2CMD_CLRINTPND 0x80000 // Clear Interrupt Pending Bit +#define CAN_IF2CMD_CONTROL 0x100000 // Access Control Bits +#define CAN_IF2CMD_ARB 0x200000 // Access Arbitration Bits +#define CAN_IF2CMD_MASK 0x400000 // Access Mask Bits +#define CAN_IF2CMD_DIR 0x800000 // Write/Read Direction + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2MSK register +// +//***************************************************************************** +#define CAN_IF2MSK_MSK_S 0 +#define CAN_IF2MSK_MSK_M 0x1FFFFFFF // Identifier Mask +#define CAN_IF2MSK_MDIR 0x40000000 // Mask Message Direction +#define CAN_IF2MSK_MXTD 0x80000000 // Mask Extended Identifier + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2ARB register +// +//***************************************************************************** +#define CAN_IF2ARB_ID_S 0 +#define CAN_IF2ARB_ID_M 0x1FFFFFFF // Message Identifier +#define CAN_IF2ARB_DIR 0x20000000 // Message Direction +#define CAN_IF2ARB_XTD 0x40000000 // Extended Identifier +#define CAN_IF2ARB_MSGVAL 0x80000000 // Message Valid + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2MCTL register +// +//***************************************************************************** +#define CAN_IF2MCTL_DLC_S 0 +#define CAN_IF2MCTL_DLC_M 0xF // Data length code +#define CAN_IF2MCTL_EOB 0x80 // End of Block +#define CAN_IF2MCTL_TXRQST 0x100 // Transmit Request +#define CAN_IF2MCTL_RMTEN 0x200 // Remote Enable +#define CAN_IF2MCTL_RXIE 0x400 // Receive Interrupt Enable +#define CAN_IF2MCTL_TXIE 0x800 // Transmit Interrupt Enable +#define CAN_IF2MCTL_UMASK 0x1000 // Use Acceptance Mask +#define CAN_IF2MCTL_INTPND 0x2000 // Interrupt Pending +#define CAN_IF2MCTL_MSGLST 0x4000 // Message Lost +#define CAN_IF2MCTL_NEWDAT 0x8000 // New Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2DATA register +// +//***************************************************************************** +#define CAN_IF2DATA_DATA_0_S 0 +#define CAN_IF2DATA_DATA_0_M 0xFF // Data Byte 0 +#define CAN_IF2DATA_DATA_1_S 8 +#define CAN_IF2DATA_DATA_1_M 0xFF00 // Data Byte 1 +#define CAN_IF2DATA_DATA_2_S 16 +#define CAN_IF2DATA_DATA_2_M 0xFF0000 // Data Byte 2 +#define CAN_IF2DATA_DATA_3_S 24 +#define CAN_IF2DATA_DATA_3_M 0xFF000000 // Data Byte 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF2DATB register +// +//***************************************************************************** +#define CAN_IF2DATB_DATA_4_S 0 +#define CAN_IF2DATB_DATA_4_M 0xFF // Data Byte 4 +#define CAN_IF2DATB_DATA_5_S 8 +#define CAN_IF2DATB_DATA_5_M 0xFF00 // Data Byte 5 +#define CAN_IF2DATB_DATA_6_S 16 +#define CAN_IF2DATB_DATA_6_M 0xFF0000 // Data Byte 6 +#define CAN_IF2DATB_DATA_7_S 24 +#define CAN_IF2DATB_DATA_7_M 0xFF000000 // Data Byte 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3OBS register +// +//***************************************************************************** +#define CAN_IF3OBS_MASK 0x1 // Mask data read observation +#define CAN_IF3OBS_ARB 0x2 // Arbitration data read + // observation +#define CAN_IF3OBS_CTRL 0x4 // Ctrl read observation +#define CAN_IF3OBS_DATA_A 0x8 // Data A read observation +#define CAN_IF3OBS_DATA_B 0x10 // Data B read observation +#define CAN_IF3OBS_IF3SM 0x100 // IF3 Status of Mask data read + // access +#define CAN_IF3OBS_IF3SA 0x200 // IF3 Status of Arbitration data + // read access +#define CAN_IF3OBS_IF3SC 0x400 // IF3 Status of Control bits read + // access +#define CAN_IF3OBS_IF3SDA 0x800 // IF3 Status of Data A read + // access +#define CAN_IF3OBS_IF3SDB 0x1000 // IF3 Status of Data B read + // access +#define CAN_IF3OBS_IF3UPD 0x8000 // IF3 Update Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3MSK register +// +//***************************************************************************** +#define CAN_IF3MSK_MSK_S 0 +#define CAN_IF3MSK_MSK_M 0x1FFFFFFF // Mask +#define CAN_IF3MSK_MDIR 0x40000000 // Mask Message Direction +#define CAN_IF3MSK_MXTD 0x80000000 // Mask Extended Identifier + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3ARB register +// +//***************************************************************************** +#define CAN_IF3ARB_ID_S 0 +#define CAN_IF3ARB_ID_M 0x1FFFFFFF // Message Identifier +#define CAN_IF3ARB_DIR 0x20000000 // Message Direction +#define CAN_IF3ARB_XTD 0x40000000 // Extended Identifier +#define CAN_IF3ARB_MSGVAL 0x80000000 // Message Valid + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3MCTL register +// +//***************************************************************************** +#define CAN_IF3MCTL_DLC_S 0 +#define CAN_IF3MCTL_DLC_M 0xF // Data length code +#define CAN_IF3MCTL_EOB 0x80 // End of Block +#define CAN_IF3MCTL_TXRQST 0x100 // Transmit Request +#define CAN_IF3MCTL_RMTEN 0x200 // Remote Enable +#define CAN_IF3MCTL_RXIE 0x400 // Receive Interrupt Enable +#define CAN_IF3MCTL_TXIE 0x800 // Transmit Interrupt Enable +#define CAN_IF3MCTL_UMASK 0x1000 // Use Acceptance Mask +#define CAN_IF3MCTL_INTPND 0x2000 // Interrupt Pending +#define CAN_IF3MCTL_MSGLST 0x4000 // Message Lost +#define CAN_IF3MCTL_NEWDAT 0x8000 // New Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3DATA register +// +//***************************************************************************** +#define CAN_IF3DATA_DATA_0_S 0 +#define CAN_IF3DATA_DATA_0_M 0xFF // Data Byte 0 +#define CAN_IF3DATA_DATA_1_S 8 +#define CAN_IF3DATA_DATA_1_M 0xFF00 // Data Byte 1 +#define CAN_IF3DATA_DATA_2_S 16 +#define CAN_IF3DATA_DATA_2_M 0xFF0000 // Data Byte 2 +#define CAN_IF3DATA_DATA_3_S 24 +#define CAN_IF3DATA_DATA_3_M 0xFF000000 // Data Byte 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3DATB register +// +//***************************************************************************** +#define CAN_IF3DATB_DATA_4_S 0 +#define CAN_IF3DATB_DATA_4_M 0xFF // Data Byte 4 +#define CAN_IF3DATB_DATA_5_S 8 +#define CAN_IF3DATB_DATA_5_M 0xFF00 // Data Byte 5 +#define CAN_IF3DATB_DATA_6_S 16 +#define CAN_IF3DATB_DATA_6_M 0xFF0000 // Data Byte 6 +#define CAN_IF3DATB_DATA_7_S 24 +#define CAN_IF3DATB_DATA_7_M 0xFF000000 // Data Byte 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_IF3UPD register +// +//***************************************************************************** +#define CAN_IF3UPD_IF3UPDEN_S 0 +#define CAN_IF3UPD_IF3UPDEN_M 0xFFFFFFFF // IF3 Update Enabled +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cmpss.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cmpss.h new file mode 100644 index 00000000000..c87a8840e84 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cmpss.h @@ -0,0 +1,295 @@ +//########################################################################### +// +// FILE: hw_cmpss.h +// +// TITLE: Definitions for the C28x CMPSS registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_CMPSS_H__ +#define __HW_CMPSS_H__ + +//***************************************************************************** +// +// The following are defines for the CMPSS register offsets +// +//***************************************************************************** +#define CMPSS_O_COMPCTL 0x0 // CMPSS Comparator Control + // Register +#define CMPSS_O_COMPHYSCTL 0x1 // CMPSS Comparator Hysteresis + // Control Register +#define CMPSS_O_COMPSTS 0x2 // CMPSS Comparator Status + // Register +#define CMPSS_O_COMPSTSCLR 0x3 // CMPSS Comparator Status Clear + // Register +#define CMPSS_O_COMPDACCTL 0x4 // CMPSS DAC Control Register +#define CMPSS_O_DACHVALS 0x6 // CMPSS High DAC Value Shadow + // Register +#define CMPSS_O_DACHVALA 0x7 // CMPSS High DAC Value Active + // Register +#define CMPSS_O_RAMPMAXREFA 0x8 // CMPSS Ramp Max Reference Active + // Register +#define CMPSS_O_RAMPMAXREFS 0xA // CMPSS Ramp Max Reference Shadow + // Register +#define CMPSS_O_RAMPDECVALA 0xC // CMPSS Ramp Decrement Value + // Active Register +#define CMPSS_O_RAMPDECVALS 0xE // CMPSS Ramp Decrement Value + // Shadow Register +#define CMPSS_O_RAMPSTS 0x10 // CMPSS Ramp Status Register +#define CMPSS_O_DACLVALS 0x12 // CMPSS Low DAC Value Shadow + // Register +#define CMPSS_O_DACLVALA 0x13 // CMPSS Low DAC Value Active + // Register +#define CMPSS_O_RAMPDLYA 0x14 // CMPSS Ramp Delay Active + // Register +#define CMPSS_O_RAMPDLYS 0x15 // CMPSS Ramp Delay Shadow + // Register +#define CMPSS_O_CTRIPLFILCTL 0x16 // CTRIPL Filter Control Register +#define CMPSS_O_CTRIPLFILCLKCTL 0x17 // CTRIPL Filter Clock Control + // Register +#define CMPSS_O_CTRIPHFILCTL 0x18 // CTRIPH Filter Control Register +#define CMPSS_O_CTRIPHFILCLKCTL 0x19 // CTRIPH Filter Clock Control + // Register +#define CMPSS_O_COMPLOCK 0x1A // CMPSS Lock Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPCTL register +// +//***************************************************************************** +#define CMPSS_COMPCTL_COMPHSOURCE 0x1 // High Comparator Source Select +#define CMPSS_COMPCTL_COMPHINV 0x2 // High Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPHSEL_S 2 +#define CMPSS_COMPCTL_CTRIPHSEL_M 0xC // High Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4 +#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30 // High Comparator Trip Output + // Select +#define CMPSS_COMPCTL_ASYNCHEN 0x40 // High Comparator Asynchronous + // Path Enable +#define CMPSS_COMPCTL_COMPLSOURCE 0x100 // Low Comparator Source Select +#define CMPSS_COMPCTL_COMPLINV 0x200 // Low Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPLSEL_S 10 +#define CMPSS_COMPCTL_CTRIPLSEL_M 0xC00 // Low Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12 +#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000 // Low Comparator Trip Output + // Select +#define CMPSS_COMPCTL_ASYNCLEN 0x4000 // Low Comparator Asynchronous + // Path Enable +#define CMPSS_COMPCTL_COMPDACE 0x8000 // Comparator/DAC Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPHYSCTL register +// +//***************************************************************************** +#define CMPSS_COMPHYSCTL_COMPHYS_S 0 +#define CMPSS_COMPHYSCTL_COMPHYS_M 0x7 // Comparator Hysteresis Trim + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPSTS register +// +//***************************************************************************** +#define CMPSS_COMPSTS_COMPHSTS 0x1 // High Comparator Status +#define CMPSS_COMPSTS_COMPHLATCH 0x2 // High Comparator Latched Status +#define CMPSS_COMPSTS_COMPLSTS 0x100 // Low Comparator Status +#define CMPSS_COMPSTS_COMPLLATCH 0x200 // Low Comparator Latched Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPSTSCLR register +// +//***************************************************************************** +#define CMPSS_COMPSTSCLR_HLATCHCLR 0x2 // High Comparator Latched Status + // Clear +#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4 // High Comparator PWMSYNC Clear + // Enable +#define CMPSS_COMPSTSCLR_LLATCHCLR 0x200 // Low Comparator Latched Status + // Clear +#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400 // Low Comparator PWMSYNC Clear + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPDACCTL register +// +//***************************************************************************** +#define CMPSS_COMPDACCTL_DACSOURCE 0x1 // DAC Source Control +#define CMPSS_COMPDACCTL_RAMPSOURCE_S 1 +#define CMPSS_COMPDACCTL_RAMPSOURCE_M 0x1E // Ramp Generator Source Control +#define CMPSS_COMPDACCTL_SELREF 0x20 // DAC Reference Select +#define CMPSS_COMPDACCTL_RAMPLOADSEL 0x40 // Ramp Load Select +#define CMPSS_COMPDACCTL_SWLOADSEL 0x80 // Software Load Select +#define CMPSS_COMPDACCTL_FREESOFT_S 14 +#define CMPSS_COMPDACCTL_FREESOFT_M 0xC000 // Free/Soft Emulation Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the DACHVALS register +// +//***************************************************************************** +#define CMPSS_DACHVALS_DACVAL_S 0 +#define CMPSS_DACHVALS_DACVAL_M 0xFFF // DAC Value Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the DACHVALA register +// +//***************************************************************************** +#define CMPSS_DACHVALA_DACVAL_S 0 +#define CMPSS_DACHVALA_DACVAL_M 0xFFF // DAC Value Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPMAXREFA register +// +//***************************************************************************** +#define CMPSS_RAMPMAXREFA_RAMPMAXREF_S 0 +#define CMPSS_RAMPMAXREFA_RAMPMAXREF_M 0xFFFF // Ramp Maximum Reference Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPMAXREFS register +// +//***************************************************************************** +#define CMPSS_RAMPMAXREFS_RAMPMAXREF_S 0 +#define CMPSS_RAMPMAXREFS_RAMPMAXREF_M 0xFFFF // Ramp Maximum Reference Shadow + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPDECVALA register +// +//***************************************************************************** +#define CMPSS_RAMPDECVALA_RAMPDECVAL_S 0 +#define CMPSS_RAMPDECVALA_RAMPDECVAL_M 0xFFFF // Ramp Decrement Value Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPDECVALS register +// +//***************************************************************************** +#define CMPSS_RAMPDECVALS_RAMPDECVAL_S 0 +#define CMPSS_RAMPDECVALS_RAMPDECVAL_M 0xFFFF // Ramp Decrement Value Shadow + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPSTS register +// +//***************************************************************************** +#define CMPSS_RAMPSTS_RAMPVALUE_S 0 +#define CMPSS_RAMPSTS_RAMPVALUE_M 0xFFFF // Ramp Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the DACLVALS register +// +//***************************************************************************** +#define CMPSS_DACLVALS_DACVAL_S 0 +#define CMPSS_DACLVALS_DACVAL_M 0xFFF // DAC Value Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the DACLVALA register +// +//***************************************************************************** +#define CMPSS_DACLVALA_DACVAL_S 0 +#define CMPSS_DACLVALA_DACVAL_M 0xFFF // DAC Value Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPDLYA register +// +//***************************************************************************** +#define CMPSS_RAMPDLYA_DELAY_S 0 +#define CMPSS_RAMPDLYA_DELAY_M 0x1FFF // Ramp Delay Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the RAMPDLYS register +// +//***************************************************************************** +#define CMPSS_RAMPDLYS_DELAY_S 0 +#define CMPSS_RAMPDLYS_DELAY_M 0x1FFF // Ramp Delay Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the CTRIPLFILCTL register +// +//***************************************************************************** +#define CMPSS_CTRIPLFILCTL_SAMPWIN_S 4 +#define CMPSS_CTRIPLFILCTL_SAMPWIN_M 0x1F0 // Sample Window +#define CMPSS_CTRIPLFILCTL_THRESH_S 9 +#define CMPSS_CTRIPLFILCTL_THRESH_M 0x3E00 // Majority Voting Threshold +#define CMPSS_CTRIPLFILCTL_FILINIT 0x8000 // Filter Initialization Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the CTRIPLFILCLKCTL register +// +//***************************************************************************** +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S 0 +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M 0x3FF // Sample Clock Prescale + +//***************************************************************************** +// +// The following are defines for the bit fields in the CTRIPHFILCTL register +// +//***************************************************************************** +#define CMPSS_CTRIPHFILCTL_SAMPWIN_S 4 +#define CMPSS_CTRIPHFILCTL_SAMPWIN_M 0x1F0 // Sample Window +#define CMPSS_CTRIPHFILCTL_THRESH_S 9 +#define CMPSS_CTRIPHFILCTL_THRESH_M 0x3E00 // Majority Voting Threshold +#define CMPSS_CTRIPHFILCTL_FILINIT 0x8000 // Filter Initialization Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the CTRIPHFILCLKCTL register +// +//***************************************************************************** +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S 0 +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M 0x3FF // Sample Clock Prescale + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMPLOCK register +// +//***************************************************************************** +#define CMPSS_COMPLOCK_COMPCTL 0x1 // COMPCTL Lock +#define CMPSS_COMPLOCK_COMPHYSCTL 0x2 // COMPHYSCTL Lock +#define CMPSS_COMPLOCK_DACCTL 0x4 // DACCTL Lock +#define CMPSS_COMPLOCK_CTRIP 0x8 // CTRIP Lock +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cputimer.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cputimer.h new file mode 100644 index 00000000000..c29d0dbcb25 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_cputimer.h @@ -0,0 +1,125 @@ +//########################################################################### +// +// FILE: hw_cputimer.h +// +// TITLE: Definitions for the C28x CPUTIMER registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_CPUTIMER_H__ +#define __HW_CPUTIMER_H__ + +//***************************************************************************** +// +// The following are defines for the CPUTIMER register offsets +// +//***************************************************************************** +#define CPUTIMER_O_TIM 0x0 // CPU-Timer, Counter Register +#define CPUTIMER_O_TIMH 0x1 // CPU-Timer, Counter Register + // High +#define CPUTIMER_O_PRD 0x2 // CPU-Timer, Period Register +#define CPUTIMER_O_PRDH 0x3 // CPU-Timer, Period Register High +#define CPUTIMER_O_TCR 0x4 // CPU-Timer, Control Register +#define CPUTIMER_O_TPR 0x6 // CPU-Timer, Prescale Register +#define CPUTIMER_O_TPRH 0x7 // CPU-Timer, Prescale Register + // High + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIM register +// +//***************************************************************************** +#define CPUTIMER_TIM_TIM_S 0 +#define CPUTIMER_TIM_TIM_M 0xFFFF // CPU-Timer Counter Registers + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMH register +// +//***************************************************************************** +#define CPUTIMER_TIMH_TIMH_S 0 +#define CPUTIMER_TIMH_TIMH_M 0xFFFF // CPU-Timer Counter Registers + // High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PRD register +// +//***************************************************************************** +#define CPUTIMER_PRD_PRD_S 0 +#define CPUTIMER_PRD_PRD_M 0xFFFF // CPU-Timer Period Registers + +//***************************************************************************** +// +// The following are defines for the bit fields in the PRDH register +// +//***************************************************************************** +#define CPUTIMER_PRDH_PRDH_S 0 +#define CPUTIMER_PRDH_PRDH_M 0xFFFF // CPU-Timer Period Registers High + +//***************************************************************************** +// +// The following are defines for the bit fields in the TCR register +// +//***************************************************************************** +#define CPUTIMER_TCR_TSS 0x10 // CPU-Timer stop status bit. +#define CPUTIMER_TCR_TRB 0x20 // Timer reload +#define CPUTIMER_TCR_FREE_SOFT_S 10 +#define CPUTIMER_TCR_FREE_SOFT_M 0xC00 // Emulation modes +#define CPUTIMER_TCR_TIE 0x4000 // CPU-Timer Interrupt Enable. +#define CPUTIMER_TCR_TIF 0x8000 // CPU-Timer Interrupt Flag. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TPR register +// +//***************************************************************************** +#define CPUTIMER_TPR_TDDR_S 0 +#define CPUTIMER_TPR_TDDR_M 0xFF // CPU-Timer Divide-Down. +#define CPUTIMER_TPR_PSC_S 8 +#define CPUTIMER_TPR_PSC_M 0xFF00 // CPU-Timer Prescale Counter. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TPRH register +// +//***************************************************************************** +#define CPUTIMER_TPRH_TDDRH_S 0 +#define CPUTIMER_TPRH_TDDRH_M 0xFF // CPU-Timer Divide-Down. +#define CPUTIMER_TPRH_PSCH_S 8 +#define CPUTIMER_TPRH_PSCH_M 0xFF00 // CPU-Timer Prescale Counter. +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ecap.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ecap.h new file mode 100644 index 00000000000..ed45234ce19 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ecap.h @@ -0,0 +1,220 @@ +//########################################################################### +// +// FILE: hw_ecap.h +// +// TITLE: Definitions for the C28x ECAP registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_ECAP_H__ +#define __HW_ECAP_H__ + +//***************************************************************************** +// +// The following are defines for the ECAP register offsets +// +//***************************************************************************** +#define ECAP_O_TSCTR 0x0 // Time-Stamp Counter +#define ECAP_O_CTRPHS 0x2 // Counter Phase Offset Value + // Register +#define ECAP_O_CAP1 0x4 // Capture 1 Register +#define ECAP_O_CAP2 0x6 // Capture 2 Register +#define ECAP_O_CAP3 0x8 // Capture 3Register +#define ECAP_O_CAP4 0xA // Capture 4 Register +#define ECAP_O_ECCTL1 0x14 // Capture Control Register 1 +#define ECAP_O_ECCTL2 0x15 // Capture Control Register 2 +#define ECAP_O_ECEINT 0x16 // Capture Interrupt Enable + // Register +#define ECAP_O_ECFLG 0x17 // Capture Interrupt Flag Register +#define ECAP_O_ECCLR 0x18 // Capture Interrupt Flag Register +#define ECAP_O_ECFRC 0x19 // Capture Interrupt Force + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the TSCTR register +// +//***************************************************************************** +#define ECAP_TSCTR_TSCTR_S 0 +#define ECAP_TSCTR_TSCTR_M 0xFFFFFFFF // Time Stamp Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the CTRPHS register +// +//***************************************************************************** +#define ECAP_CTRPHS_CTRPHS_S 0 +#define ECAP_CTRPHS_CTRPHS_M 0xFFFFFFFF // Counter phase + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAP1 register +// +//***************************************************************************** +#define ECAP_CAP1_CAP1_S 0 +#define ECAP_CAP1_CAP1_M 0xFFFFFFFF // Capture 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAP2 register +// +//***************************************************************************** +#define ECAP_CAP2_CAP2_S 0 +#define ECAP_CAP2_CAP2_M 0xFFFFFFFF // Capture 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAP3 register +// +//***************************************************************************** +#define ECAP_CAP3_CAP3_S 0 +#define ECAP_CAP3_CAP3_M 0xFFFFFFFF // Capture 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAP4 register +// +//***************************************************************************** +#define ECAP_CAP4_CAP4_S 0 +#define ECAP_CAP4_CAP4_M 0xFFFFFFFF // Capture 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECCTL1 register +// +//***************************************************************************** +#define ECAP_ECCTL1_CAP1POL 0x1 // Capture Event 1 Polarity select +#define ECAP_ECCTL1_CTRRST1 0x2 // Counter Reset on Capture Event + // 1 +#define ECAP_ECCTL1_CAP2POL 0x4 // Capture Event 2 Polarity select +#define ECAP_ECCTL1_CTRRST2 0x8 // Counter Reset on Capture Event + // 2 +#define ECAP_ECCTL1_CAP3POL 0x10 // Capture Event 3 Polarity select +#define ECAP_ECCTL1_CTRRST3 0x20 // Counter Reset on Capture Event + // 3 +#define ECAP_ECCTL1_CAP4POL 0x40 // Capture Event 4 Polarity select +#define ECAP_ECCTL1_CTRRST4 0x80 // Counter Reset on Capture Event + // 4 +#define ECAP_ECCTL1_CAPLDEN 0x100 // Enable Loading CAP1-4 regs on a + // Cap Event +#define ECAP_ECCTL1_PRESCALE_S 9 +#define ECAP_ECCTL1_PRESCALE_M 0x3E00 // Event Filter prescale select +#define ECAP_ECCTL1_FREE_SOFT_S 14 +#define ECAP_ECCTL1_FREE_SOFT_M 0xC000 // Emulation mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECCTL2 register +// +//***************************************************************************** +#define ECAP_ECCTL2_CONT_ONESHT 0x1 // Continuous or one-shot +#define ECAP_ECCTL2_STOP_WRAP_S 1 +#define ECAP_ECCTL2_STOP_WRAP_M 0x6 // Stop value for one-shot, Wrap + // for continuous +#define ECAP_ECCTL2_RE_ARM 0x8 // One-shot re-arm +#define ECAP_ECCTL2_TSCTRSTOP 0x10 // TSCNT counter stop +#define ECAP_ECCTL2_SYNCI_EN 0x20 // Counter sync-in select +#define ECAP_ECCTL2_SYNCO_SEL_S 6 +#define ECAP_ECCTL2_SYNCO_SEL_M 0xC0 // Sync-out mode +#define ECAP_ECCTL2_SWSYNC 0x100 // SW forced counter sync +#define ECAP_ECCTL2_CAP_APWM 0x200 // CAP/APWM operating mode select +#define ECAP_ECCTL2_APWMPOL 0x400 // APWM output polarity select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECEINT register +// +//***************************************************************************** +#define ECAP_ECEINT_CEVT1 0x2 // Capture Event 1 Interrupt + // Enable +#define ECAP_ECEINT_CEVT2 0x4 // Capture Event 2 Interrupt + // Enable +#define ECAP_ECEINT_CEVT3 0x8 // Capture Event 3 Interrupt + // Enable +#define ECAP_ECEINT_CEVT4 0x10 // Capture Event 4 Interrupt + // Enable +#define ECAP_ECEINT_CTROVF 0x20 // Counter Overflow Interrupt + // Enable +#define ECAP_ECEINT_CTR_PRD 0x40 // Period Equal Interrupt Enable +#define ECAP_ECEINT_CTR_CMP 0x80 // Compare Equal Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECFLG register +// +//***************************************************************************** +#define ECAP_ECFLG_INT 0x1 // Global Flag +#define ECAP_ECFLG_CEVT1 0x2 // Capture Event 1 Interrupt Flag +#define ECAP_ECFLG_CEVT2 0x4 // Capture Event 2 Interrupt Flag +#define ECAP_ECFLG_CEVT3 0x8 // Capture Event 3 Interrupt Flag +#define ECAP_ECFLG_CEVT4 0x10 // Capture Event 4 Interrupt Flag +#define ECAP_ECFLG_CTROVF 0x20 // Counter Overflow Interrupt Flag +#define ECAP_ECFLG_CTR_PRD 0x40 // Period Equal Interrupt Flag +#define ECAP_ECFLG_CTR_CMP 0x80 // Compare Equal Interrupt Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECCLR register +// +//***************************************************************************** +#define ECAP_ECCLR_INT 0x1 // Global Flag +#define ECAP_ECCLR_CEVT1 0x2 // Capture Event 1 Interrupt Flag +#define ECAP_ECCLR_CEVT2 0x4 // Capture Event 2 Interrupt Flag +#define ECAP_ECCLR_CEVT3 0x8 // Capture Event 3 Interrupt Flag +#define ECAP_ECCLR_CEVT4 0x10 // Capture Event 4 Interrupt Flag +#define ECAP_ECCLR_CTROVF 0x20 // Counter Overflow Interrupt Flag +#define ECAP_ECCLR_CTR_PRD 0x40 // Period Equal Interrupt Flag +#define ECAP_ECCLR_CTR_CMP 0x80 // Compare Equal Interrupt Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ECFRC register +// +//***************************************************************************** +#define ECAP_ECFRC_CEVT1 0x2 // Capture Event 1 Interrupt + // Enable +#define ECAP_ECFRC_CEVT2 0x4 // Capture Event 2 Interrupt + // Enable +#define ECAP_ECFRC_CEVT3 0x8 // Capture Event 3 Interrupt + // Enable +#define ECAP_ECFRC_CEVT4 0x10 // Capture Event 4 Interrupt + // Enable +#define ECAP_ECFRC_CTROVF 0x20 // Counter Overflow Interrupt + // Enable +#define ECAP_ECFRC_CTR_PRD 0x40 // Period Equal Interrupt Enable +#define ECAP_ECFRC_CTR_CMP 0x80 // Compare Equal Interrupt Enable +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_emif.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_emif.h new file mode 100644 index 00000000000..f7532220915 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_emif.h @@ -0,0 +1,372 @@ +//########################################################################### +// +// FILE: hw_emif.h +// +// TITLE: Definitions for the C28x EMIF registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_EMIF_H__ +#define __HW_EMIF_H__ + +//***************************************************************************** +// +// The following are defines for the EMIF register offsets +// +//***************************************************************************** +#define EMIF_O_RCSR 0x0 // Revision Code and Status + // Register +#define EMIF_O_ASYNC_WCCR 0x2 // Async Wait Cycle Config + // Register +#define EMIF_O_SDRAM_CR 0x4 // SDRAM + // (pad_cs_o_n[0]/pad_cs_o_n[1]) + // Config Register +#define EMIF_O_SDRAM_RCR 0x6 // SDRAM Refresh Control Register +#define EMIF_O_ASYNC_CS2_CR 0x8 // Async 1 (pad_cs_o_n[2]) Config + // Register +#define EMIF_O_ASYNC_CS3_CR 0xA // Async 2 (pad_cs_o_n[3]) Config + // Register +#define EMIF_O_ASYNC_CS4_CR 0xC // Async 3 (pad_cs_o_n[4]) Config + // Register +#define EMIF_O_ASYNC_CS5_CR 0xE // Async 4 (pad_cs_o_n[5]) Config + // Register +#define EMIF_O_SDRAM_TR 0x10 // SDRAM Timing Register +#define EMIF_O_TOTAL_SDRAM_AR 0x18 // Total SDRAM Accesses Register +#define EMIF_O_TOTAL_SDRAM_ACTR 0x1A // Total SDRAM Activate Register +#define EMIF_O_SDR_EXT_TMNG 0x1E // SDRAM SR/PD Exit Timing + // Register +#define EMIF_O_INT_RAW 0x20 // Interrupt Raw Register +#define EMIF_O_INT_MSK 0x22 // Interrupt Masked Register +#define EMIF_O_INT_MSK_SET 0x24 // Interrupt Mask Set Register +#define EMIF_O_INT_MSK_CLR 0x26 // Interrupt Mask Clear Register +#define EMIF_O_IO_CTRL 0x28 // IO Control Register +#define EMIF_O_IO_STAT 0x2A // IO Status Register +#define EMIF_O_MODEL_REL_NUM 0x56 // Module Release Number Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the RCSR register +// +//***************************************************************************** +#define EMIF_RCSR_MINOR_REVISION_S 0 +#define EMIF_RCSR_MINOR_REVISION_M 0xFF // Minor Revision. +#define EMIF_RCSR_MAJOR_REVISION_S 8 +#define EMIF_RCSR_MAJOR_REVISION_M 0xFF00 // Major Revision. +#define EMIF_RCSR_MODULE_ID_S 16 +#define EMIF_RCSR_MODULE_ID_M 0x3FFF0000 // EMIF module ID. +#define EMIF_RCSR_FR 0x40000000 // EMIF is running in full rate or + // half rate. +#define EMIF_RCSR_BE 0x80000000 // EMIF endian mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ASYNC_WCCR register +// +//***************************************************************************** +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_S 0 +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M 0xFF // Maximum Extended Wait cycles. +#define EMIF_ASYNC_WCCR_CS2_WAIT_S 16 +#define EMIF_ASYNC_WCCR_CS2_WAIT_M 0x30000 // Maps the wait signal for chip + // select 2. +#define EMIF_ASYNC_WCCR_CS3_WAIT_S 18 +#define EMIF_ASYNC_WCCR_CS3_WAIT_M 0xC0000 // Maps the wait signal for chip + // select 3. +#define EMIF_ASYNC_WCCR_CS4_WAIT_S 20 +#define EMIF_ASYNC_WCCR_CS4_WAIT_M 0x300000 // Maps the wait signal for chip + // select 4. +#define EMIF_ASYNC_WCCR_CS5_WAIT_S 22 +#define EMIF_ASYNC_WCCR_CS5_WAIT_M 0xC00000 // Maps the wait signal for chip + // select 5. +#define EMIF_ASYNC_WCCR_WP0 0x10000000 // Wait Polarity for + // pad_wait_i[0]. +#define EMIF_ASYNC_WCCR_WP1 0x20000000 // Wait Polarity for + // pad_wait_i[1]. +#define EMIF_ASYNC_WCCR_WP2 0x40000000 // Wait Polarity for + // pad_wait_i[2]. +#define EMIF_ASYNC_WCCR_WP3 0x80000000 // Wait Polarity for + // pad_wait_i[3]. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SDRAM_CR register +// +//***************************************************************************** +#define EMIF_SDRAM_CR_PAGESIGE_S 0 +#define EMIF_SDRAM_CR_PAGESIGE_M 0x7 // Page Size. +#define EMIF_SDRAM_CR_EBANK 0x8 // External chip select setup. +#define EMIF_SDRAM_CR_IBANK_S 4 +#define EMIF_SDRAM_CR_IBANK_M 0x70 // Internal Bank setup of SDRAM + // devices. +#define EMIF_SDRAM_CR_BIT_11_9_LOCK 0x100 // Bits 11 to 9 are writable only + // if this bit is set. +#define EMIF_SDRAM_CR_CL_S 9 +#define EMIF_SDRAM_CR_CL_M 0xE00 // CAS Latency. +#define EMIF_SDRAM_CR_BIT_13_LOCK 0x1000 // Bits 13 is writable only if + // this bit is set. +#define EMIF_SDRAM_CR_NM 0x4000 // Narrow Mode. +#define EMIF_SDRAM_CR_BIT_25_17_LOCK 0x10000 // Bits 25 to 17 are writable only + // if this bit is set +#define EMIF_SDRAM_CR_IBANK_POS 0x80000 // Internal bank position. +#define EMIF_SDRAM_CR_ROWSIZE_S 20 +#define EMIF_SDRAM_CR_ROWSIZE_M 0x700000 // Row Size. +#define EMIF_SDRAM_CR_PASR_S 23 +#define EMIF_SDRAM_CR_PASR_M 0x3800000 // Partial Array Self Refresh. +#define EMIF_SDRAM_CR_PDWR 0x20000000 // Perform refreshes during Power + // Down. +#define EMIF_SDRAM_CR_PD 0x40000000 // Power Down. +#define EMIF_SDRAM_CR_SR 0x80000000 // Self Refresh. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SDRAM_RCR register +// +//***************************************************************************** +#define EMIF_SDRAM_RCR_REFRESH_RATE_S 0 +#define EMIF_SDRAM_RCR_REFRESH_RATE_M 0x1FFF // Refresh Rate. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ASYNC_CS2_CR register +// +//***************************************************************************** +#define EMIF_ASYNC_CS2_CR_ASIZE_S 0 +#define EMIF_ASYNC_CS2_CR_ASIZE_M 0x3 // Asynchronous Memory Size. +#define EMIF_ASYNC_CS2_CR_TA_S 2 +#define EMIF_ASYNC_CS2_CR_TA_M 0xC // Turn Around cycles. +#define EMIF_ASYNC_CS2_CR_R_HOLD_S 4 +#define EMIF_ASYNC_CS2_CR_R_HOLD_M 0x70 // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_R_STROBE_S 7 +#define EMIF_ASYNC_CS2_CR_R_STROBE_M 0x1F80 // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_R_SETUP_S 13 +#define EMIF_ASYNC_CS2_CR_R_SETUP_M 0x1E000 // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_W_HOLD_S 17 +#define EMIF_ASYNC_CS2_CR_W_HOLD_M 0xE0000 // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_W_STROBE_S 20 +#define EMIF_ASYNC_CS2_CR_W_STROBE_M 0x3F00000 // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_W_SETUP_S 26 +#define EMIF_ASYNC_CS2_CR_W_SETUP_M 0x3C000000 // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_EW 0x40000000 // Extend Wait mode. +#define EMIF_ASYNC_CS2_CR_SS 0x80000000 // Select Strobe mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ASYNC_CS3_CR register +// +//***************************************************************************** +#define EMIF_ASYNC_CS3_CR_ASIZE_S 0 +#define EMIF_ASYNC_CS3_CR_ASIZE_M 0x3 // Asynchronous Memory Size. +#define EMIF_ASYNC_CS3_CR_TA_S 2 +#define EMIF_ASYNC_CS3_CR_TA_M 0xC // Turn Around cycles. +#define EMIF_ASYNC_CS3_CR_R_HOLD_S 4 +#define EMIF_ASYNC_CS3_CR_R_HOLD_M 0x70 // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_R_STROBE_S 7 +#define EMIF_ASYNC_CS3_CR_R_STROBE_M 0x1F80 // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_R_SETUP_S 13 +#define EMIF_ASYNC_CS3_CR_R_SETUP_M 0x1E000 // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_W_HOLD_S 17 +#define EMIF_ASYNC_CS3_CR_W_HOLD_M 0xE0000 // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_W_STROBE_S 20 +#define EMIF_ASYNC_CS3_CR_W_STROBE_M 0x3F00000 // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_W_SETUP_S 26 +#define EMIF_ASYNC_CS3_CR_W_SETUP_M 0x3C000000 // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_EW 0x40000000 // Extend Wait mode. +#define EMIF_ASYNC_CS3_CR_SS 0x80000000 // Select Strobe mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ASYNC_CS4_CR register +// +//***************************************************************************** +#define EMIF_ASYNC_CS4_CR_ASIZE_S 0 +#define EMIF_ASYNC_CS4_CR_ASIZE_M 0x3 // Asynchronous Memory Size. +#define EMIF_ASYNC_CS4_CR_TA_S 2 +#define EMIF_ASYNC_CS4_CR_TA_M 0xC // Turn Around cycles. +#define EMIF_ASYNC_CS4_CR_R_HOLD_S 4 +#define EMIF_ASYNC_CS4_CR_R_HOLD_M 0x70 // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_R_STROBE_S 7 +#define EMIF_ASYNC_CS4_CR_R_STROBE_M 0x1F80 // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_R_SETUP_S 13 +#define EMIF_ASYNC_CS4_CR_R_SETUP_M 0x1E000 // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_W_HOLD_S 17 +#define EMIF_ASYNC_CS4_CR_W_HOLD_M 0xE0000 // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_W_STROBE_S 20 +#define EMIF_ASYNC_CS4_CR_W_STROBE_M 0x3F00000 // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_W_SETUP_S 26 +#define EMIF_ASYNC_CS4_CR_W_SETUP_M 0x3C000000 // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_EW 0x40000000 // Extend Wait mode. +#define EMIF_ASYNC_CS4_CR_SS 0x80000000 // Select Strobe mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the ASYNC_CS5_CR register +// +//***************************************************************************** +#define EMIF_ASYNC_CS5_CR_ASIZE_S 0 +#define EMIF_ASYNC_CS5_CR_ASIZE_M 0x3 // Asynchronous Memory Size. +#define EMIF_ASYNC_CS5_CR_TA_S 2 +#define EMIF_ASYNC_CS5_CR_TA_M 0xC // Turn Around cycles. +#define EMIF_ASYNC_CS5_CR_R_HOLD_S 4 +#define EMIF_ASYNC_CS5_CR_R_HOLD_M 0x70 // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS5_CR_R_STROBE_S 7 +#define EMIF_ASYNC_CS5_CR_R_STROBE_M 0x1F80 // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS5_CR_R_SETUP_S 13 +#define EMIF_ASYNC_CS5_CR_R_SETUP_M 0x1E000 // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS5_CR_W_HOLD_S 17 +#define EMIF_ASYNC_CS5_CR_W_HOLD_M 0xE0000 // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS5_CR_W_STROBE_S 20 +#define EMIF_ASYNC_CS5_CR_W_STROBE_M 0x3F00000 // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS5_CR_W_SETUP_S 26 +#define EMIF_ASYNC_CS5_CR_W_SETUP_M 0x3C000000 // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS5_CR_EW 0x40000000 // Extend Wait mode. +#define EMIF_ASYNC_CS5_CR_SS 0x80000000 // Select Strobe mode. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SDRAM_TR register +// +//***************************************************************************** +#define EMIF_SDRAM_TR_T_RRD_S 4 +#define EMIF_SDRAM_TR_T_RRD_M 0x70 // Activate to Activate timing for + // different bank. +#define EMIF_SDRAM_TR_T_RC_S 8 +#define EMIF_SDRAM_TR_T_RC_M 0xF00 // Activate to Activate timing . +#define EMIF_SDRAM_TR_T_RAS_S 12 +#define EMIF_SDRAM_TR_T_RAS_M 0xF000 // Activate to Precharge timing. +#define EMIF_SDRAM_TR_T_WR_S 16 +#define EMIF_SDRAM_TR_T_WR_M 0x70000 // Last Write to Precharge timing. +#define EMIF_SDRAM_TR_T_RCD_S 20 +#define EMIF_SDRAM_TR_T_RCD_M 0x700000 // Activate to Read/Write timing. +#define EMIF_SDRAM_TR_T_RP_S 24 +#define EMIF_SDRAM_TR_T_RP_M 0x7000000 // Precharge to Activate/Refresh + // timing. +#define EMIF_SDRAM_TR_T_RFC_S 27 +#define EMIF_SDRAM_TR_T_RFC_M 0xF8000000 // Refresh/Load Mode to + // Refresh/Activate timing + +//***************************************************************************** +// +// The following are defines for the bit fields in the TOTAL_SDRAM_AR register +// +//***************************************************************************** +#define EMIF_TOTAL_SDRAM_AR_TOTAL_SDRAM_AR_S 0 +#define EMIF_TOTAL_SDRAM_AR_TOTAL_SDRAM_AR_M 0xFFFFFFFF // Total number of VBUSP accesses + // to SDRAM. + +//***************************************************************************** +// +// The following are defines for the bit fields in the TOTAL_SDRAM_ACTR register +// +//***************************************************************************** +#define EMIF_TOTAL_SDRAM_ACTR_TOTAL_SDRAM_ACTR_S 0 +#define EMIF_TOTAL_SDRAM_ACTR_TOTAL_SDRAM_ACTR_M 0xFFFFFFFF // Number of SDRAM accesses which + // required an activate command. + +//***************************************************************************** +// +// The following are defines for the bit fields in the SDR_EXT_TMNG register +// +//***************************************************************************** +#define EMIF_SDR_EXT_TMNG_T_XS_S 0 +#define EMIF_SDR_EXT_TMNG_T_XS_M 0x1F // Self Refresh exit to new + // command timing. + +//***************************************************************************** +// +// The following are defines for the bit fields in the INT_RAW register +// +//***************************************************************************** +#define EMIF_INT_RAW_AT 0x1 // Asynchronous Timeout. +#define EMIF_INT_RAW_LT 0x2 // Line Trap. +#define EMIF_INT_RAW_WR_S 2 +#define EMIF_INT_RAW_WR_M 0x3C // Wait Rise. + +//***************************************************************************** +// +// The following are defines for the bit fields in the INT_MSK register +// +//***************************************************************************** +#define EMIF_INT_MSK_AT_MASKED 0x1 // Asynchronous Timeout. +#define EMIF_INT_MSK_LT_MASKED 0x2 // Line Trap. +#define EMIF_INT_MSK_WR_MASKED_S 2 +#define EMIF_INT_MSK_WR_MASKED_M 0x3C // Wait Rise. + +//***************************************************************************** +// +// The following are defines for the bit fields in the INT_MSK_SET register +// +//***************************************************************************** +#define EMIF_INT_MSK_SET_AT_MASK_SET 0x1 // Asynchronous Timeout. +#define EMIF_INT_MSK_SET_LT_MASK_SET 0x2 // Line Trap. +#define EMIF_INT_MSK_SET_WR_MASK_SET_S 2 +#define EMIF_INT_MSK_SET_WR_MASK_SET_M 0x3C // Wait Rise. + +//***************************************************************************** +// +// The following are defines for the bit fields in the INT_MSK_CLR register +// +//***************************************************************************** +#define EMIF_INT_MSK_CLR_AT_MASK_CLR 0x1 // Asynchronous Timeout. +#define EMIF_INT_MSK_CLR_LT_MASK_CLR 0x2 // Line Trap. +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_S 2 +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_M 0x3C // Wait Rise. + +//***************************************************************************** +// +// The following are defines for the bit fields in the IO_CTRL register +// +//***************************************************************************** +#define EMIF_IO_CTRL_IO_CTRL_S 0 +#define EMIF_IO_CTRL_IO_CTRL_M 0xFFFF // VTP calibration control for the + // IOs + +//***************************************************************************** +// +// The following are defines for the bit fields in the IO_STAT register +// +//***************************************************************************** +#define EMIF_IO_STAT_IO_STAT_S 0 +#define EMIF_IO_STAT_IO_STAT_M 0xFFFF // VTP calibration status of the + // IOs + +//***************************************************************************** +// +// The following are defines for the bit fields in the MODEL_REL_NUM register +// +//***************************************************************************** +#define EMIF_MODEL_REL_NUM_RELEASE_NUM_S 0 +#define EMIF_MODEL_REL_NUM_RELEASE_NUM_M 0xFF // Release Number. +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_epwm.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_epwm.h new file mode 100644 index 00000000000..f72a5bc5f3b --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_epwm.h @@ -0,0 +1,1248 @@ +//########################################################################### +// +// FILE: hw_epwm.h +// +// TITLE: Definitions for the C28x EPWM registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_EPWM_H__ +#define __HW_EPWM_H__ + +//***************************************************************************** +// +// The following are defines for the EPWM register offsets +// +//***************************************************************************** +#define EPWM_O_TBCTL 0x0 // Time Base Control Register +#define EPWM_O_TBCTL2 0x1 // Time Base Control Register 2 +#define EPWM_O_TBCTR 0x4 // Time Base Counter Register +#define EPWM_O_TBSTS 0x5 // Time Base Status Register +#define EPWM_O_CMPCTL 0x8 // Counter Compare Control + // Register +#define EPWM_O_CMPCTL2 0x9 // Counter Compare Control + // Register 2 +#define EPWM_O_DBCTL 0xC // Dead-Band Generator Control + // Register +#define EPWM_O_DBCTL2 0xD // Dead-Band Generator Control + // Register 2 +#define EPWM_O_AQCTL 0x10 // Action Qualifier Control + // Register +#define EPWM_O_AQTSRCSEL 0x11 // Action Qualifier Trigger Event + // Source Select Register +#define EPWM_O_PCCTL 0x14 // PWM Chopper Control Register +#define EPWM_O_HRCNFG 0x20 // HRPWM Configuration Register +#define EPWM_O_HRPWR 0x21 // HRPWM Power Register +#define EPWM_O_HRMSTEP 0x26 // HRPWM MEP Step Register +#define EPWM_O_HRPCTL 0x2D // High Resolution Period Control + // Register +#define EPWM_O_GLDCTL 0x34 // Global PWM Load Control + // Register +#define EPWM_O_GLDCFG 0x35 // Global PWM Load Config Register +#define EPWM_O_XLINK 0x38 // EPWMx Link Register +#define EPWM_O_AQCTLA 0x40 // Action Qualifier Control + // Register For Output A +#define EPWM_O_AQCTLA2 0x41 // Additional Action Qualifier + // Control Register For Output A +#define EPWM_O_AQCTLB 0x42 // Action Qualifier Control + // Register For Output B +#define EPWM_O_AQCTLB2 0x43 // Additional Action Qualifier + // Control Register For Output B +#define EPWM_O_AQSFRC 0x47 // Action Qualifier Software Force + // Register +#define EPWM_O_AQCSFRC 0x49 // Action Qualifier Continuous S/W + // Force Register +#define EPWM_O_DBREDHR 0x50 // Dead-Band Generator Rising Edge + // Delay High Resolution Mirror + // Register +#define EPWM_O_DBRED 0x51 // Dead-Band Generator Rising Edge + // Delay High Resolution Mirror + // Register +#define EPWM_O_DBFEDHR 0x52 // Dead-Band Generator Falling + // Edge Delay High Resolution + // Register +#define EPWM_O_DBFED 0x53 // Dead-Band Generator Falling + // Edge Delay Count Register +#define EPWM_O_TBPHS 0x60 // Time Base Phase High +#define EPWM_O_TBPRDHR 0x62 // Time Base Period High + // Resolution Register +#define EPWM_O_TBPRD 0x63 // Time Base Period Register +#define EPWM_O_CMPA 0x6A // Counter Compare A Register +#define EPWM_O_CMPB 0x6C // Compare B Register +#define EPWM_O_CMPC 0x6F // Counter Compare C Register +#define EPWM_O_CMPD 0x71 // Counter Compare D Register +#define EPWM_O_GLDCTL2 0x74 // Global PWM Load Control + // Register 2 +#define EPWM_O_TZSEL 0x80 // Trip Zone Select Register +#define EPWM_O_TZDCSEL 0x82 // Trip Zone Digital Comparator + // Select Register +#define EPWM_O_TZCTL 0x84 // Trip Zone Control Register +#define EPWM_O_TZCTL2 0x85 // Additional Trip Zone Control + // Register +#define EPWM_O_TZCTLDCA 0x86 // Trip Zone Control Register + // Digital Compare A +#define EPWM_O_TZCTLDCB 0x87 // Trip Zone Control Register + // Digital Compare B +#define EPWM_O_TZEINT 0x8D // Trip Zone Enable Interrupt + // Register +#define EPWM_O_TZFLG 0x93 // Trip Zone Flag Register +#define EPWM_O_TZCBCFLG 0x94 // Trip Zone CBC Flag Register +#define EPWM_O_TZOSTFLG 0x95 // Trip Zone OST Flag Register +#define EPWM_O_TZCLR 0x97 // Trip Zone Clear Register +#define EPWM_O_TZCBCCLR 0x98 // Trip Zone CBC Clear Register +#define EPWM_O_TZOSTCLR 0x99 // Trip Zone OST Clear Register +#define EPWM_O_TZFRC 0x9B // Trip Zone Force Register +#define EPWM_O_ETSEL 0xA4 // Event Trigger Selection + // Register +#define EPWM_O_ETPS 0xA6 // Event Trigger Pre-Scale + // Register +#define EPWM_O_ETFLG 0xA8 // Event Trigger Flag Register +#define EPWM_O_ETCLR 0xAA // Event Trigger Clear Register +#define EPWM_O_ETFRC 0xAC // Event Trigger Force Register +#define EPWM_O_ETINTPS 0xAE // Event-Trigger Interrupt + // Pre-Scale Register +#define EPWM_O_ETSOCPS 0xB0 // Event-Trigger SOC Pre-Scale + // Register +#define EPWM_O_ETCNTINITCTL 0xB2 // Event-Trigger Counter + // Initialization Control + // Register +#define EPWM_O_ETCNTINIT 0xB4 // Event-Trigger Counter + // Initialization Register +#define EPWM_O_DCTRIPSEL 0xC0 // Digital Compare Trip Select + // Register +#define EPWM_O_DCACTL 0xC3 // Digital Compare A Control + // Register +#define EPWM_O_DCBCTL 0xC4 // Digital Compare B Control + // Register +#define EPWM_O_DCFCTL 0xC7 // Digital Compare Filter Control + // Register +#define EPWM_O_DCCAPCTL 0xC8 // Digital Compare Capture Control + // Register +#define EPWM_O_DCFOFFSET 0xC9 // Digital Compare Filter Offset + // Register +#define EPWM_O_DCFOFFSETCNT 0xCA // Digital Compare Filter Offset + // Counter Register +#define EPWM_O_DCFWINDOW 0xCB // Digital Compare Filter Window + // Register +#define EPWM_O_DCFWINDOWCNT 0xCC // Digital Compare Filter Window + // Counter Register +#define EPWM_O_DCCAP 0xCF // Digital Compare Counter Capture + // Register +#define EPWM_O_DCAHTRIPSEL 0xD2 // Digital Compare AH Trip Select +#define EPWM_O_DCALTRIPSEL 0xD3 // Digital Compare AL Trip Select +#define EPWM_O_DCBHTRIPSEL 0xD4 // Digital Compare BH Trip Select +#define EPWM_O_DCBLTRIPSEL 0xD5 // Digital Compare BL Trip Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBCTL register +// +//***************************************************************************** +#define EPWM_TBCTL_CTRMODE_S 0 +#define EPWM_TBCTL_CTRMODE_M 0x3 // Counter Mode +#define EPWM_TBCTL_PHSEN 0x4 // Phase Load Enable +#define EPWM_TBCTL_PRDLD 0x8 // Active Period Load +#define EPWM_TBCTL_SYNCOSEL_S 4 +#define EPWM_TBCTL_SYNCOSEL_M 0x30 // Sync Output Select +#define EPWM_TBCTL_SWFSYNC 0x40 // Software Force Sync Pulse +#define EPWM_TBCTL_HSPCLKDIV_S 7 +#define EPWM_TBCTL_HSPCLKDIV_M 0x380 // High Speed TBCLK Pre-scaler +#define EPWM_TBCTL_CLKDIV_S 10 +#define EPWM_TBCTL_CLKDIV_M 0x1C00 // Time Base Clock Pre-scaler +#define EPWM_TBCTL_PHSDIR 0x2000 // Phase Direction Bit +#define EPWM_TBCTL_FREE_SOFT_S 14 +#define EPWM_TBCTL_FREE_SOFT_M 0xC000 // Emulation Mode Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBCTL2 register +// +//***************************************************************************** +#define EPWM_TBCTL2_SELFCLRTRREM 0x20 // Self clear Translator reminder +#define EPWM_TBCTL2_OSHTSYNCMODE 0x40 // One shot sync mode +#define EPWM_TBCTL2_OSHTSYNC 0x80 // One shot sync +#define EPWM_TBCTL2_SYNCOSELX_S 12 +#define EPWM_TBCTL2_SYNCOSELX_M 0x3000 // Syncout selection +#define EPWM_TBCTL2_PRDLDSYNC_S 14 +#define EPWM_TBCTL2_PRDLDSYNC_M 0xC000 // PRD Shadow to Active Load on + // SYNC Event + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBCTR register +// +//***************************************************************************** +#define EPWM_TBCTR_TBCTR_S 0 +#define EPWM_TBCTR_TBCTR_M 0xFFFF // Counter Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBSTS register +// +//***************************************************************************** +#define EPWM_TBSTS_CTRDIR 0x1 // Counter Direction Status +#define EPWM_TBSTS_SYNCI 0x2 // External Input Sync Status +#define EPWM_TBSTS_CTRMAX 0x4 // Counter Max Latched Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPCTL register +// +//***************************************************************************** +#define EPWM_CMPCTL_LOADAMODE_S 0 +#define EPWM_CMPCTL_LOADAMODE_M 0x3 // Active Compare A Load +#define EPWM_CMPCTL_LOADBMODE_S 2 +#define EPWM_CMPCTL_LOADBMODE_M 0xC // Active Compare B Load +#define EPWM_CMPCTL_SHDWAMODE 0x10 // Compare A Register Block + // Operating Mode +#define EPWM_CMPCTL_SHDWBMODE 0x40 // Compare B Register Block + // Operating Mode +#define EPWM_CMPCTL_SHDWAFULL 0x100 // Compare A Shadow Register Full + // Status +#define EPWM_CMPCTL_SHDWBFULL 0x200 // Compare B Shadow Register Full + // Status +#define EPWM_CMPCTL_LOADASYNC_S 10 +#define EPWM_CMPCTL_LOADASYNC_M 0xC00 // Active Compare A Load on SYNC +#define EPWM_CMPCTL_LOADBSYNC_S 12 +#define EPWM_CMPCTL_LOADBSYNC_M 0x3000 // Active Compare B Load on SYNC + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPCTL2 register +// +//***************************************************************************** +#define EPWM_CMPCTL2_LOADCMODE_S 0 +#define EPWM_CMPCTL2_LOADCMODE_M 0x3 // Active Compare C Load +#define EPWM_CMPCTL2_LOADDMODE_S 2 +#define EPWM_CMPCTL2_LOADDMODE_M 0xC // Active Compare D load +#define EPWM_CMPCTL2_SHDWCMODE 0x10 // Compare C Block Operating Mode +#define EPWM_CMPCTL2_SHDWDMODE 0x40 // Compare D Block Operating Mode +#define EPWM_CMPCTL2_LOADCSYNC_S 10 +#define EPWM_CMPCTL2_LOADCSYNC_M 0xC00 // Active Compare C Load on SYNC +#define EPWM_CMPCTL2_LOADDSYNC_S 12 +#define EPWM_CMPCTL2_LOADDSYNC_M 0x3000 // Active Compare D Load on SYNC + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBCTL register +// +//***************************************************************************** +#define EPWM_DBCTL_OUT_MODE_S 0 +#define EPWM_DBCTL_OUT_MODE_M 0x3 // Dead Band Output Mode Control +#define EPWM_DBCTL_POLSEL_S 2 +#define EPWM_DBCTL_POLSEL_M 0xC // Polarity Select Control +#define EPWM_DBCTL_IN_MODE_S 4 +#define EPWM_DBCTL_IN_MODE_M 0x30 // Dead Band Input Select Mode + // Control +#define EPWM_DBCTL_LOADREDMODE_S 6 +#define EPWM_DBCTL_LOADREDMODE_M 0xC0 // Active DBRED Load Mode +#define EPWM_DBCTL_LOADFEDMODE_S 8 +#define EPWM_DBCTL_LOADFEDMODE_M 0x300 // Active DBFED Load Mode +#define EPWM_DBCTL_SHDWDBREDMODE 0x400 // DBRED Block Operating Mode +#define EPWM_DBCTL_SHDWDBFEDMODE 0x800 // DBFED Block Operating Mode +#define EPWM_DBCTL_OUTSWAP_S 12 +#define EPWM_DBCTL_OUTSWAP_M 0x3000 // Dead Band Output Swap Control +#define EPWM_DBCTL_DEDB_MODE 0x4000 // Dead Band Dual-Edge B Mode + // Control +#define EPWM_DBCTL_HALFCYCLE 0x8000 // Half Cycle Clocking Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBCTL2 register +// +//***************************************************************************** +#define EPWM_DBCTL2_LOADDBCTLMODE_S 0 +#define EPWM_DBCTL2_LOADDBCTLMODE_M 0x3 // DBCTL Load from Shadow Mode + // Select +#define EPWM_DBCTL2_SHDWDBCTLMODE 0x4 // DBCTL Load mode Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCTL register +// +//***************************************************************************** +#define EPWM_AQCTL_LDAQAMODE_S 0 +#define EPWM_AQCTL_LDAQAMODE_M 0x3 // Action Qualifier A Load Select +#define EPWM_AQCTL_LDAQBMODE_S 2 +#define EPWM_AQCTL_LDAQBMODE_M 0xC // Action Qualifier B Load Select +#define EPWM_AQCTL_SHDWAQAMODE 0x10 // Action Qualifer A Operating + // Mode +#define EPWM_AQCTL_SHDWAQBMODE 0x40 // Action Qualifier B Operating + // Mode +#define EPWM_AQCTL_LDAQASYNC_S 8 +#define EPWM_AQCTL_LDAQASYNC_M 0x300 // AQCTLA Register Load on SYNC +#define EPWM_AQCTL_LDAQBSYNC_S 10 +#define EPWM_AQCTL_LDAQBSYNC_M 0xC00 // AQCTLB Register Load on SYNC + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQTSRCSEL register +// +//***************************************************************************** +#define EPWM_AQTSRCSEL_T1SEL_S 0 +#define EPWM_AQTSRCSEL_T1SEL_M 0xF // T1 Event Source Select Bits +#define EPWM_AQTSRCSEL_T2SEL_S 4 +#define EPWM_AQTSRCSEL_T2SEL_M 0xF0 // T2 Event Source Select Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the PCCTL register +// +//***************************************************************************** +#define EPWM_PCCTL_CHPEN 0x1 // PWM chopping enable +#define EPWM_PCCTL_OSHTWTH_S 1 +#define EPWM_PCCTL_OSHTWTH_M 0x1E // One-shot pulse width +#define EPWM_PCCTL_CHPFREQ_S 5 +#define EPWM_PCCTL_CHPFREQ_M 0xE0 // Chopping clock frequency +#define EPWM_PCCTL_CHPDUTY_S 8 +#define EPWM_PCCTL_CHPDUTY_M 0x700 // Chopping clock Duty cycle + +//***************************************************************************** +// +// The following are defines for the bit fields in the HRCNFG register +// +//***************************************************************************** +#define EPWM_HRCNFG_EDGMODE_S 0 +#define EPWM_HRCNFG_EDGMODE_M 0x3 // ePWMxA Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODE 0x4 // ePWMxA Control Mode Select Bits +#define EPWM_HRCNFG_HRLOAD_S 3 +#define EPWM_HRCNFG_HRLOAD_M 0x18 // ePWMxA Shadow Mode Select Bits +#define EPWM_HRCNFG_SELOUTB 0x20 // EPWMB Output Selection Bit +#define EPWM_HRCNFG_AUTOCONV 0x40 // Autoconversion Bit +#define EPWM_HRCNFG_SWAPAB 0x80 // Swap EPWMA and EPWMB Outputs + // Bit +#define EPWM_HRCNFG_EDGMODEB_S 8 +#define EPWM_HRCNFG_EDGMODEB_M 0x300 // ePWMxB Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODEB 0x400 // ePWMxB Control Mode Select Bits +#define EPWM_HRCNFG_HRLOADB_S 11 +#define EPWM_HRCNFG_HRLOADB_M 0x1800 // ePWMxB Shadow Mode Select Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the HRPWR register +// +//***************************************************************************** +#define EPWM_HRPWR_CALPWRON 0x8000 // Calibration Power On + +//***************************************************************************** +// +// The following are defines for the bit fields in the HRMSTEP register +// +//***************************************************************************** +#define EPWM_HRMSTEP_HRMSTEP_S 0 +#define EPWM_HRMSTEP_HRMSTEP_M 0xFF // High Resolution Micro Step + // Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the HRPCTL register +// +//***************************************************************************** +#define EPWM_HRPCTL_HRPE 0x1 // High Resolution Period Enable +#define EPWM_HRPCTL_TBPHSHRLOADE 0x4 // TBPHSHR Load Enable +#define EPWM_HRPCTL_PWMSYNCSELX_S 4 +#define EPWM_HRPCTL_PWMSYNCSELX_M 0x70 // PWMSYNCX Source Select Bit: + +//***************************************************************************** +// +// The following are defines for the bit fields in the GLDCTL register +// +//***************************************************************************** +#define EPWM_GLDCTL_GLD 0x1 // Global Shadow to Active load + // event control +#define EPWM_GLDCTL_GLDMODE_S 1 +#define EPWM_GLDCTL_GLDMODE_M 0x1E // Shadow to Active Global Load + // Pulse Selection +#define EPWM_GLDCTL_OSHTMODE 0x20 // One Shot Load mode control bit +#define EPWM_GLDCTL_GLDPRD_S 7 +#define EPWM_GLDCTL_GLDPRD_M 0x380 // Global Reload Strobe Period + // Select Register +#define EPWM_GLDCTL_GLDCNT_S 10 +#define EPWM_GLDCTL_GLDCNT_M 0x1C00 // Global Reload Strobe Counter + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the GLDCFG register +// +//***************************************************************************** +#define EPWM_GLDCFG_TBPRD_TBPRDHR 0x1 // Global load event configuration + // for TBPRD:TBPRDHR +#define EPWM_GLDCFG_CMPA_CMPAHR 0x2 // Global load event configuration + // for CMPA:CMPAHR +#define EPWM_GLDCFG_CMPB_CMPBHR 0x4 // Global load event configuration + // for CMPB:CMPBHR +#define EPWM_GLDCFG_CMPC 0x8 // Global load event configuration + // for CMPC +#define EPWM_GLDCFG_CMPD 0x10 // Global load event configuration + // for CMPD +#define EPWM_GLDCFG_DBRED_DBREDHR 0x20 // Global load event configuration + // for DBRED:DBREDHR +#define EPWM_GLDCFG_DBFED_DBFEDHR 0x40 // Global load event configuration + // for DBFED:DBFEDHR +#define EPWM_GLDCFG_DBCTL 0x80 // Global load event configuration + // for DBCTL +#define EPWM_GLDCFG_AQCTLA_AQCTLA2 0x100 // Global load event configuration + // for AQCTLA/A2 +#define EPWM_GLDCFG_AQCTLB_AQCTLB2 0x200 // Global load event configuration + // for AQCTLB/B2 +#define EPWM_GLDCFG_AQCSFRC 0x400 // Global load event configuration + // for AQCSFRC + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPWMXLINK register +// +//***************************************************************************** +#define EPWM_XLINK_TBPRDLINK_S 0 +#define EPWM_XLINK_TBPRDLINK_M 0xF // TBPRD:TBPRDHR Link +#define EPWM_XLINK_CMPALINK_S 4 +#define EPWM_XLINK_CMPALINK_M 0xF0 // CMPA:CMPAHR Link +#define EPWM_XLINK_CMPBLINK_S 8 +#define EPWM_XLINK_CMPBLINK_M 0xF00 // CMPB:CMPBHR Link +#define EPWM_XLINK_CMPCLINK_S 12 +#define EPWM_XLINK_CMPCLINK_M 0xF000 // CMPC Link +#define EPWM_XLINK_CMPDLINK_S 16 +#define EPWM_XLINK_CMPDLINK_M 0xF0000 // CMPD Link +#define EPWM_XLINK_GLDCTL2LINK_S 28 +#define EPWM_XLINK_GLDCTL2LINK_M 0xF0000000 // GLDCTL2 Link + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCTLA register +// +//***************************************************************************** +#define EPWM_AQCTLA_ZRO_S 0 +#define EPWM_AQCTLA_ZRO_M 0x3 // Action Counter = Zero +#define EPWM_AQCTLA_PRD_S 2 +#define EPWM_AQCTLA_PRD_M 0xC // Action Counter = Period +#define EPWM_AQCTLA_CAU_S 4 +#define EPWM_AQCTLA_CAU_M 0x30 // Action Counter = Compare A Up +#define EPWM_AQCTLA_CAD_S 6 +#define EPWM_AQCTLA_CAD_M 0xC0 // Action Counter = Compare A Down +#define EPWM_AQCTLA_CBU_S 8 +#define EPWM_AQCTLA_CBU_M 0x300 // Action Counter = Compare B Up +#define EPWM_AQCTLA_CBD_S 10 +#define EPWM_AQCTLA_CBD_M 0xC00 // Action Counter = Compare B Down + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCTLA2 register +// +//***************************************************************************** +#define EPWM_AQCTLA2_T1U_S 0 +#define EPWM_AQCTLA2_T1U_M 0x3 // Action when event occurs on T1 + // in UP-Count +#define EPWM_AQCTLA2_T1D_S 2 +#define EPWM_AQCTLA2_T1D_M 0xC // Action when event occurs on T1 + // in DOWN-Count +#define EPWM_AQCTLA2_T2U_S 4 +#define EPWM_AQCTLA2_T2U_M 0x30 // Action when event occurs on T2 + // in UP-Count +#define EPWM_AQCTLA2_T2D_S 6 +#define EPWM_AQCTLA2_T2D_M 0xC0 // Action when event occurs on T2 + // in DOWN-Count + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCTLB register +// +//***************************************************************************** +#define EPWM_AQCTLB_ZRO_S 0 +#define EPWM_AQCTLB_ZRO_M 0x3 // Action Counter = Zero +#define EPWM_AQCTLB_PRD_S 2 +#define EPWM_AQCTLB_PRD_M 0xC // Action Counter = Period +#define EPWM_AQCTLB_CAU_S 4 +#define EPWM_AQCTLB_CAU_M 0x30 // Action Counter = Compare A Up +#define EPWM_AQCTLB_CAD_S 6 +#define EPWM_AQCTLB_CAD_M 0xC0 // Action Counter = Compare A Down +#define EPWM_AQCTLB_CBU_S 8 +#define EPWM_AQCTLB_CBU_M 0x300 // Action Counter = Compare B Up +#define EPWM_AQCTLB_CBD_S 10 +#define EPWM_AQCTLB_CBD_M 0xC00 // Action Counter = Compare B Down + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCTLB2 register +// +//***************************************************************************** +#define EPWM_AQCTLB2_T1U_S 0 +#define EPWM_AQCTLB2_T1U_M 0x3 // Action when event occurs on T1 + // in UP-Count +#define EPWM_AQCTLB2_T1D_S 2 +#define EPWM_AQCTLB2_T1D_M 0xC // Action when event occurs on T1 + // in DOWN-Count +#define EPWM_AQCTLB2_T2U_S 4 +#define EPWM_AQCTLB2_T2U_M 0x30 // Action when event occurs on T2 + // in UP-Count +#define EPWM_AQCTLB2_T2D_S 6 +#define EPWM_AQCTLB2_T2D_M 0xC0 // Action when event occurs on T2 + // in DOWN-Count + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQSFRC register +// +//***************************************************************************** +#define EPWM_AQSFRC_ACTSFA_S 0 +#define EPWM_AQSFRC_ACTSFA_M 0x3 // Action when One-time SW Force A + // Invoked +#define EPWM_AQSFRC_OTSFA 0x4 // One-time SW Force A Output +#define EPWM_AQSFRC_ACTSFB_S 3 +#define EPWM_AQSFRC_ACTSFB_M 0x18 // Action when One-time SW Force B + // Invoked +#define EPWM_AQSFRC_OTSFB 0x20 // One-time SW Force A Output +#define EPWM_AQSFRC_RLDCSF_S 6 +#define EPWM_AQSFRC_RLDCSF_M 0xC0 // Reload from Shadow Options + +//***************************************************************************** +// +// The following are defines for the bit fields in the AQCSFRC register +// +//***************************************************************************** +#define EPWM_AQCSFRC_CSFA_S 0 +#define EPWM_AQCSFRC_CSFA_M 0x3 // Continuous Software Force on + // output A +#define EPWM_AQCSFRC_CSFB_S 2 +#define EPWM_AQCSFRC_CSFB_M 0xC // Continuous Software Force on + // output B + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBREDHR register +// +//***************************************************************************** +#define EPWM_DBREDHR_DBREDHR_S 9 +#define EPWM_DBREDHR_DBREDHR_M 0xFE00 // DBREDHR High Resolution Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBRED register +// +//***************************************************************************** +#define EPWM_DBRED_DBRED_S 0 +#define EPWM_DBRED_DBRED_M 0xFFFF // Rising edge delay value + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBFEDHR register +// +//***************************************************************************** +#define EPWM_DBFEDHR_DBFEDHR_S 9 +#define EPWM_DBFEDHR_DBFEDHR_M 0xFE00 // DBFEDHR High Resolution Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the DBFED register +// +//***************************************************************************** +#define EPWM_DBFED_DBFED_S 0 +#define EPWM_DBFED_DBFED_M 0xFFFF // Falling edge delay value + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBPHS register +// +//***************************************************************************** +#define EPWM_TBPHS_TBPHSHR_S 0 +#define EPWM_TBPHS_TBPHSHR_M 0xFFFF // Extension Register for HRPWM + // Phase (8-bits) +#define EPWM_TBPHS_TBPHS_S 16 +#define EPWM_TBPHS_TBPHS_M 0xFFFF0000 // Phase Offset Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBPRDHR register +// +//***************************************************************************** +#define EPWM_TBPRDHR_TBPRDHR_S 0 +#define EPWM_TBPRDHR_TBPRDHR_M 0xFFFF // High res Time base period + // register + +//***************************************************************************** +// +// The following are defines for the bit fields in the TBPRD register +// +//***************************************************************************** +#define EPWM_TBPRD_TBPRD_S 0 +#define EPWM_TBPRD_TBPRD_M 0xFFFF // Time base period register + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPA register +// +//***************************************************************************** +#define EPWM_CMPA_CMPAHR_S 0 +#define EPWM_CMPA_CMPAHR_M 0xFFFF // Compare A HRPWM Extension + // Register +#define EPWM_CMPA_CMPA_S 16 +#define EPWM_CMPA_CMPA_M 0xFFFF0000 // Compare A Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPB register +// +//***************************************************************************** +#define EPWM_CMPB_CMPB_S 16 +#define EPWM_CMPB_CMPB_M 0xFFFF0000 // Compare B Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPC register +// +//***************************************************************************** +#define EPWM_CMPC_CMPC_S 0 +#define EPWM_CMPC_CMPC_M 0xFFFF // Compare C Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the CMPD register +// +//***************************************************************************** +#define EPWM_CMPD_CMPD_S 0 +#define EPWM_CMPD_CMPD_M 0xFFFF // Compare D Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the GLDCTL2 register +// +//***************************************************************************** +#define EPWM_GLDCTL2_OSHTLD 0x1 // Enable reload event in one shot + // mode +#define EPWM_GLDCTL2_GFRCLD 0x2 // Force reload event in one shot + // mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZSEL register +// +//***************************************************************************** +#define EPWM_TZSEL_CBC1 0x1 // TZ1 CBC select +#define EPWM_TZSEL_CBC2 0x2 // TZ2 CBC select +#define EPWM_TZSEL_CBC3 0x4 // TZ3 CBC select +#define EPWM_TZSEL_CBC4 0x8 // TZ4 CBC select +#define EPWM_TZSEL_CBC5 0x10 // TZ5 CBC select +#define EPWM_TZSEL_CBC6 0x20 // TZ6 CBC select +#define EPWM_TZSEL_DCAEVT2 0x40 // DCAEVT2 CBC select +#define EPWM_TZSEL_DCBEVT2 0x80 // DCBEVT2 CBC select +#define EPWM_TZSEL_OSHT1 0x100 // One-shot TZ1 select +#define EPWM_TZSEL_OSHT2 0x200 // One-shot TZ2 select +#define EPWM_TZSEL_OSHT3 0x400 // One-shot TZ3 select +#define EPWM_TZSEL_OSHT4 0x800 // One-shot TZ4 select +#define EPWM_TZSEL_OSHT5 0x1000 // One-shot TZ5 select +#define EPWM_TZSEL_OSHT6 0x2000 // One-shot TZ6 select +#define EPWM_TZSEL_DCAEVT1 0x4000 // One-shot DCAEVT1 select +#define EPWM_TZSEL_DCBEVT1 0x8000 // One-shot DCBEVT1 select + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZDCSEL register +// +//***************************************************************************** +#define EPWM_TZDCSEL_DCAEVT1_S 0 +#define EPWM_TZDCSEL_DCAEVT1_M 0x7 // Digital Compare Output A Event + // 1 +#define EPWM_TZDCSEL_DCAEVT2_S 3 +#define EPWM_TZDCSEL_DCAEVT2_M 0x38 // Digital Compare Output A Event + // 2 +#define EPWM_TZDCSEL_DCBEVT1_S 6 +#define EPWM_TZDCSEL_DCBEVT1_M 0x1C0 // Digital Compare Output B Event + // 1 +#define EPWM_TZDCSEL_DCBEVT2_S 9 +#define EPWM_TZDCSEL_DCBEVT2_M 0xE00 // Digital Compare Output B Event + // 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCTL register +// +//***************************************************************************** +#define EPWM_TZCTL_TZA_S 0 +#define EPWM_TZCTL_TZA_M 0x3 // TZ1 to TZ6 Trip Action On + // EPWMxA +#define EPWM_TZCTL_TZB_S 2 +#define EPWM_TZCTL_TZB_M 0xC // TZ1 to TZ6 Trip Action On + // EPWMxB +#define EPWM_TZCTL_DCAEVT1_S 4 +#define EPWM_TZCTL_DCAEVT1_M 0x30 // EPWMxA action on DCAEVT1 +#define EPWM_TZCTL_DCAEVT2_S 6 +#define EPWM_TZCTL_DCAEVT2_M 0xC0 // EPWMxA action on DCAEVT2 +#define EPWM_TZCTL_DCBEVT1_S 8 +#define EPWM_TZCTL_DCBEVT1_M 0x300 // EPWMxB action on DCBEVT1 +#define EPWM_TZCTL_DCBEVT2_S 10 +#define EPWM_TZCTL_DCBEVT2_M 0xC00 // EPWMxB action on DCBEVT2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCTL2 register +// +//***************************************************************************** +#define EPWM_TZCTL2_TZAU_S 0 +#define EPWM_TZCTL2_TZAU_M 0x7 // Trip Action On EPWMxA while + // Count direction is UP +#define EPWM_TZCTL2_TZAD_S 3 +#define EPWM_TZCTL2_TZAD_M 0x38 // Trip Action On EPWMxA while + // Count direction is DOWN +#define EPWM_TZCTL2_TZBU_S 6 +#define EPWM_TZCTL2_TZBU_M 0x1C0 // Trip Action On EPWMxB while + // Count direction is UP +#define EPWM_TZCTL2_TZBD_S 9 +#define EPWM_TZCTL2_TZBD_M 0xE00 // Trip Action On EPWMxB while + // Count direction is DOWN +#define EPWM_TZCTL2_ETZE 0x8000 // TZCTL2 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCTLDCA register +// +//***************************************************************************** +#define EPWM_TZCTLDCA_DCAEVT1U_S 0 +#define EPWM_TZCTLDCA_DCAEVT1U_M 0x7 // DCAEVT1 Action On EPWMxA while + // Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT1D_S 3 +#define EPWM_TZCTLDCA_DCAEVT1D_M 0x38 // DCAEVT1 Action On EPWMxA while + // Count direction is DOWN +#define EPWM_TZCTLDCA_DCAEVT2U_S 6 +#define EPWM_TZCTLDCA_DCAEVT2U_M 0x1C0 // DCAEVT2 Action On EPWMxA while + // Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT2D_S 9 +#define EPWM_TZCTLDCA_DCAEVT2D_M 0xE00 // DCAEVT2 Action On EPWMxA while + // Count direction is DOWN + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCTLDCB register +// +//***************************************************************************** +#define EPWM_TZCTLDCB_DCBEVT1U_S 0 +#define EPWM_TZCTLDCB_DCBEVT1U_M 0x7 // DCBEVT1 Action On EPWMxA while + // Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT1D_S 3 +#define EPWM_TZCTLDCB_DCBEVT1D_M 0x38 // DCBEVT1 Action On EPWMxA while + // Count direction is DOWN +#define EPWM_TZCTLDCB_DCBEVT2U_S 6 +#define EPWM_TZCTLDCB_DCBEVT2U_M 0x1C0 // DCBEVT2 Action On EPWMxA while + // Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT2D_S 9 +#define EPWM_TZCTLDCB_DCBEVT2D_M 0xE00 // DCBEVT2 Action On EPWMxA while + // Count direction is DOWN + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZEINT register +// +//***************************************************************************** +#define EPWM_TZEINT_CBC 0x2 // Trip Zones Cycle By Cycle Int + // Enable +#define EPWM_TZEINT_OST 0x4 // Trip Zones One Shot Int Enable +#define EPWM_TZEINT_DCAEVT1 0x8 // Digital Compare A Event 1 Int + // Enable +#define EPWM_TZEINT_DCAEVT2 0x10 // Digital Compare A Event 2 Int + // Enable +#define EPWM_TZEINT_DCBEVT1 0x20 // Digital Compare B Event 1 Int + // Enable +#define EPWM_TZEINT_DCBEVT2 0x40 // Digital Compare B Event 2 Int + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZFLG register +// +//***************************************************************************** +#define EPWM_TZFLG_INT 0x1 // Global Int Status Flag +#define EPWM_TZFLG_CBC 0x2 // Trip Zones Cycle By Cycle Flag +#define EPWM_TZFLG_OST 0x4 // Trip Zones One Shot Flag +#define EPWM_TZFLG_DCAEVT1 0x8 // Digital Compare A Event 1 Flag +#define EPWM_TZFLG_DCAEVT2 0x10 // Digital Compare A Event 2 Flag +#define EPWM_TZFLG_DCBEVT1 0x20 // Digital Compare B Event 1 Flag +#define EPWM_TZFLG_DCBEVT2 0x40 // Digital Compare B Event 2 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCBCFLG register +// +//***************************************************************************** +#define EPWM_TZCBCFLG_CBC1 0x1 // Latched Status Flag for CBC1 + // Trip Latch +#define EPWM_TZCBCFLG_CBC2 0x2 // Latched Status Flag for CBC2 + // Trip Latch +#define EPWM_TZCBCFLG_CBC3 0x4 // Latched Status Flag for CBC3 + // Trip Latch +#define EPWM_TZCBCFLG_CBC4 0x8 // Latched Status Flag for CBC4 + // Trip Latch +#define EPWM_TZCBCFLG_CBC5 0x10 // Latched Status Flag for CBC5 + // Trip Latch +#define EPWM_TZCBCFLG_CBC6 0x20 // Latched Status Flag for CBC6 + // Trip Latch +#define EPWM_TZCBCFLG_DCAEVT2 0x40 // Latched Status Flag for Digital + // Compare Output A Event 2 +#define EPWM_TZCBCFLG_DCBEVT2 0x80 // Latched Status Flag for Digital + // Compare Output B Event 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZOSTFLG register +// +//***************************************************************************** +#define EPWM_TZOSTFLG_OST1 0x1 // Latched Status Flag for OST1 + // Trip Latch +#define EPWM_TZOSTFLG_OST2 0x2 // Latched Status Flag for OST2 + // Trip Latch +#define EPWM_TZOSTFLG_OST3 0x4 // Latched Status Flag for OST3 + // Trip Latch +#define EPWM_TZOSTFLG_OST4 0x8 // Latched Status Flag for OST4 + // Trip Latch +#define EPWM_TZOSTFLG_OST5 0x10 // Latched Status Flag for OST5 + // Trip Latch +#define EPWM_TZOSTFLG_OST6 0x20 // Latched Status Flag for OST6 + // Trip Latch +#define EPWM_TZOSTFLG_DCAEVT2 0x40 // Latched Status Flag for Digital + // Compare Output A Event 1 +#define EPWM_TZOSTFLG_DCBEVT2 0x80 // Latched Status Flag for Digital + // Compare Output B Event 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCLR register +// +//***************************************************************************** +#define EPWM_TZCLR_INT 0x1 // Global Interrupt Clear Flag +#define EPWM_TZCLR_CBC 0x2 // Cycle-By-Cycle Flag Clear +#define EPWM_TZCLR_OST 0x4 // One-Shot Flag Clear +#define EPWM_TZCLR_DCAEVT1 0x8 // DCAVET1 Flag Clear +#define EPWM_TZCLR_DCAEVT2 0x10 // DCAEVT2 Flag Clear +#define EPWM_TZCLR_DCBEVT1 0x20 // DCBEVT1 Flag Clear +#define EPWM_TZCLR_DCBEVT2 0x40 // DCBEVT2 Flag Clear +#define EPWM_TZCLR_CBCPULSE_S 14 +#define EPWM_TZCLR_CBCPULSE_M 0xC000 // Clear Pulse for CBC Trip Latch + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZCBCCLR register +// +//***************************************************************************** +#define EPWM_TZCBCCLR_CBC1 0x1 // Clear Flag for Cycle-By-Cycle + // (CBC1) Trip Latch +#define EPWM_TZCBCCLR_CBC2 0x2 // Clear Flag for Cycle-By-Cycle + // (CBC2) Trip Latch +#define EPWM_TZCBCCLR_CBC3 0x4 // Clear Flag for Cycle-By-Cycle + // (CBC3) Trip Latch +#define EPWM_TZCBCCLR_CBC4 0x8 // Clear Flag for Cycle-By-Cycle + // (CBC4) Trip Latch +#define EPWM_TZCBCCLR_CBC5 0x10 // Clear Flag for Cycle-By-Cycle + // (CBC5) Trip Latch +#define EPWM_TZCBCCLR_CBC6 0x20 // Clear Flag for Cycle-By-Cycle + // (CBC6) Trip Latch +#define EPWM_TZCBCCLR_DCAEVT2 0x40 // Clear Flag forDCAEVT2 selected + // for CBC +#define EPWM_TZCBCCLR_DCBEVT2 0x80 // Clear Flag for DCBEVT2 selected + // for CBC + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZOSTCLR register +// +//***************************************************************************** +#define EPWM_TZOSTCLR_OST1 0x1 // Clear Flag for Oneshot (OST1) + // Trip Latch +#define EPWM_TZOSTCLR_OST2 0x2 // Clear Flag for Oneshot (OST2) + // Trip Latch +#define EPWM_TZOSTCLR_OST3 0x4 // Clear Flag for Oneshot (OST3) + // Trip Latch +#define EPWM_TZOSTCLR_OST4 0x8 // Clear Flag for Oneshot (OST4) + // Trip Latch +#define EPWM_TZOSTCLR_OST5 0x10 // Clear Flag for Oneshot (OST5) + // Trip Latch +#define EPWM_TZOSTCLR_OST6 0x20 // Clear Flag for Oneshot (OST6) + // Trip Latch +#define EPWM_TZOSTCLR_DCAEVT2 0x40 // Clear Flag for DCAEVT1 selected + // for OST +#define EPWM_TZOSTCLR_DCBEVT2 0x80 // Clear Flag for DCBEVT1 selected + // for OST + +//***************************************************************************** +// +// The following are defines for the bit fields in the TZFRC register +// +//***************************************************************************** +#define EPWM_TZFRC_CBC 0x2 // Force Trip Zones Cycle By Cycle + // Event +#define EPWM_TZFRC_OST 0x4 // Force Trip Zones One Shot Event +#define EPWM_TZFRC_DCAEVT1 0x8 // Force Digital Compare A Event 1 +#define EPWM_TZFRC_DCAEVT2 0x10 // Force Digital Compare A Event 2 +#define EPWM_TZFRC_DCBEVT1 0x20 // Force Digital Compare B Event 1 +#define EPWM_TZFRC_DCBEVT2 0x40 // Force Digital Compare B Event 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETSEL register +// +//***************************************************************************** +#define EPWM_ETSEL_INTSEL_S 0 +#define EPWM_ETSEL_INTSEL_M 0x7 // EPWMxINTn Select +#define EPWM_ETSEL_INTEN 0x8 // EPWMxINTn Enable +#define EPWM_ETSEL_SOCASELCMP 0x10 // EPWMxSOCA Compare Select +#define EPWM_ETSEL_SOCBSELCMP 0x20 // EPWMxSOCB Compare Select +#define EPWM_ETSEL_INTSELCMP 0x40 // EPWMxINT Compare Select +#define EPWM_ETSEL_SOCASEL_S 8 +#define EPWM_ETSEL_SOCASEL_M 0x700 // Start of Conversion A Select +#define EPWM_ETSEL_SOCAEN 0x800 // Start of Conversion A Enable +#define EPWM_ETSEL_SOCBSEL_S 12 +#define EPWM_ETSEL_SOCBSEL_M 0x7000 // Start of Conversion B Select +#define EPWM_ETSEL_SOCBEN 0x8000 // Start of Conversion B Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETPS register +// +//***************************************************************************** +#define EPWM_ETPS_INTPRD_S 0 +#define EPWM_ETPS_INTPRD_M 0x3 // EPWMxINTn Period Select +#define EPWM_ETPS_INTCNT_S 2 +#define EPWM_ETPS_INTCNT_M 0xC // EPWMxINTn Counter Register +#define EPWM_ETPS_INTPSSEL 0x10 // EPWMxINTn Pre-Scale Selection + // Bits +#define EPWM_ETPS_SOCPSSEL 0x20 // EPWMxSOC A/B Pre-Scale + // Selection Bits +#define EPWM_ETPS_SOCAPRD_S 8 +#define EPWM_ETPS_SOCAPRD_M 0x300 // EPWMxSOCA Period Select +#define EPWM_ETPS_SOCACNT_S 10 +#define EPWM_ETPS_SOCACNT_M 0xC00 // EPWMxSOCA Counter Register +#define EPWM_ETPS_SOCBPRD_S 12 +#define EPWM_ETPS_SOCBPRD_M 0x3000 // EPWMxSOCB Period Select +#define EPWM_ETPS_SOCBCNT_S 14 +#define EPWM_ETPS_SOCBCNT_M 0xC000 // EPWMxSOCB Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETFLG register +// +//***************************************************************************** +#define EPWM_ETFLG_INT 0x1 // EPWMxINTn Flag +#define EPWM_ETFLG_SOCA 0x4 // EPWMxSOCA Flag +#define EPWM_ETFLG_SOCB 0x8 // EPWMxSOCB Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETCLR register +// +//***************************************************************************** +#define EPWM_ETCLR_INT 0x1 // EPWMxINTn Clear +#define EPWM_ETCLR_SOCA 0x4 // EPWMxSOCA Clear +#define EPWM_ETCLR_SOCB 0x8 // EPWMxSOCB Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETFRC register +// +//***************************************************************************** +#define EPWM_ETFRC_INT 0x1 // EPWMxINTn Force +#define EPWM_ETFRC_SOCA 0x4 // EPWMxSOCA Force +#define EPWM_ETFRC_SOCB 0x8 // EPWMxSOCB Force + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETINTPS register +// +//***************************************************************************** +#define EPWM_ETINTPS_INTPRD2_S 0 +#define EPWM_ETINTPS_INTPRD2_M 0xF // EPWMxINTn Period Select +#define EPWM_ETINTPS_INTCNT2_S 4 +#define EPWM_ETINTPS_INTCNT2_M 0xF0 // EPWMxINTn Counter Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETSOCPS register +// +//***************************************************************************** +#define EPWM_ETSOCPS_SOCAPRD2_S 0 +#define EPWM_ETSOCPS_SOCAPRD2_M 0xF // EPWMxSOCA Period Select +#define EPWM_ETSOCPS_SOCACNT2_S 4 +#define EPWM_ETSOCPS_SOCACNT2_M 0xF0 // EPWMxSOCA Counter Register +#define EPWM_ETSOCPS_SOCBPRD2_S 8 +#define EPWM_ETSOCPS_SOCBPRD2_M 0xF00 // EPWMxSOCB Period Select +#define EPWM_ETSOCPS_SOCBCNT2_S 12 +#define EPWM_ETSOCPS_SOCBCNT2_M 0xF000 // EPWMxSOCB Counter Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETCNTINITCTL register +// +//***************************************************************************** +#define EPWM_ETCNTINITCTL_INTINITFRC 0x400 // EPWMxINT Counter Initialization + // Force +#define EPWM_ETCNTINITCTL_SOCAINITFRC 0x800 // EPWMxSOCA Counter + // Initialization Force +#define EPWM_ETCNTINITCTL_SOCBINITFRC 0x1000 // EPWMxSOCB Counter + // Initialization Force +#define EPWM_ETCNTINITCTL_INTINITEN 0x2000 // EPWMxINT Counter Initialization + // Enable +#define EPWM_ETCNTINITCTL_SOCAINITEN 0x4000 // EPWMxSOCA Counter + // Initialization Enable +#define EPWM_ETCNTINITCTL_SOCBINITEN 0x8000 // EPWMxSOCB Counter + // Initialization Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ETCNTINIT register +// +//***************************************************************************** +#define EPWM_ETCNTINIT_INTINIT_S 0 +#define EPWM_ETCNTINIT_INTINIT_M 0xF // EPWMxINT Counter Initialization + // Bits +#define EPWM_ETCNTINIT_SOCAINIT_S 4 +#define EPWM_ETCNTINIT_SOCAINIT_M 0xF0 // EPWMxSOCA Counter + // Initialization Bits +#define EPWM_ETCNTINIT_SOCBINIT_S 8 +#define EPWM_ETCNTINIT_SOCBINIT_M 0xF00 // EPWMxSOCB Counter + // Initialization Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCTRIPSEL register +// +//***************************************************************************** +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_S 0 +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_M 0xF // Digital Compare A High COMP + // Input Select +#define EPWM_DCTRIPSEL_DCALCOMPSEL_S 4 +#define EPWM_DCTRIPSEL_DCALCOMPSEL_M 0xF0 // Digital Compare A Low COMP + // Input Select +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_S 8 +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_M 0xF00 // Digital Compare B High COMP + // Input Select +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_S 12 +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_M 0xF000 // Digital Compare B Low COMP + // Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCACTL register +// +//***************************************************************************** +#define EPWM_DCACTL_EVT1SRCSEL 0x1 // DCAEVT1 Source Signal +#define EPWM_DCACTL_EVT1FRCSYNCSEL 0x2 // DCAEVT1 Force Sync Signal +#define EPWM_DCACTL_EVT1SOCE 0x4 // DCAEVT1 SOC Enable +#define EPWM_DCACTL_EVT1SYNCE 0x8 // DCAEVT1 SYNC Enable +#define EPWM_DCACTL_EVT2SRCSEL 0x100 // DCAEVT2 Source Signal +#define EPWM_DCACTL_EVT2FRCSYNCSEL 0x200 // DCAEVT2 Force Sync Signal + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCBCTL register +// +//***************************************************************************** +#define EPWM_DCBCTL_EVT1SRCSEL 0x1 // DCBEVT1 Source Signal +#define EPWM_DCBCTL_EVT1FRCSYNCSEL 0x2 // DCBEVT1 Force Sync Signal +#define EPWM_DCBCTL_EVT1SOCE 0x4 // DCBEVT1 SOC Enable +#define EPWM_DCBCTL_EVT1SYNCE 0x8 // DCBEVT1 SYNC Enable +#define EPWM_DCBCTL_EVT2SRCSEL 0x100 // DCBEVT2 Source Signal +#define EPWM_DCBCTL_EVT2FRCSYNCSEL 0x200 // DCBEVT2 Force Sync Signal + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCFCTL register +// +//***************************************************************************** +#define EPWM_DCFCTL_SRCSEL_S 0 +#define EPWM_DCFCTL_SRCSEL_M 0x3 // Filter Block Signal Source + // Select +#define EPWM_DCFCTL_BLANKE 0x4 // Blanking Enable/Disable +#define EPWM_DCFCTL_BLANKINV 0x8 // Blanking Window Inversion +#define EPWM_DCFCTL_PULSESEL_S 4 +#define EPWM_DCFCTL_PULSESEL_M 0x30 // Pulse Select for Blanking & + // Capture Alignment + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCCAPCTL register +// +//***************************************************************************** +#define EPWM_DCCAPCTL_CAPE 0x1 // Counter Capture Enable +#define EPWM_DCCAPCTL_SHDWMODE 0x2 // Counter Capture Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCFOFFSET register +// +//***************************************************************************** +#define EPWM_DCFOFFSET_DCFOFFSET_S 0 +#define EPWM_DCFOFFSET_DCFOFFSET_M 0xFFFF // Blanking Offset + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCFOFFSETCNT register +// +//***************************************************************************** +#define EPWM_DCFOFFSETCNT_DCFOFFSETCNT_S 0 +#define EPWM_DCFOFFSETCNT_DCFOFFSETCNT_M 0xFFFF // Blanking Offset Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCFWINDOW register +// +//***************************************************************************** +#define EPWM_DCFWINDOW_DCFWINDOW_S 0 +#define EPWM_DCFWINDOW_DCFWINDOW_M 0xFFFF // Digital Compare Filter Window + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCFWINDOWCNT register +// +//***************************************************************************** +#define EPWM_DCFWINDOWCNT_DCFWINDOWCNT_S 0 +#define EPWM_DCFWINDOWCNT_DCFWINDOWCNT_M 0xFFFF // Digital Compare Filter Window + // Counter Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCCAP register +// +//***************************************************************************** +#define EPWM_DCCAP_DCCAP_S 0 +#define EPWM_DCCAP_DCCAP_M 0xFFFF // Time Base Counter Capture + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCAHTRIPSEL register +// +//***************************************************************************** +#define EPWM_DCAHTRIPSEL_TRIPINPUT1 0x1 // Trip Input 1 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT2 0x2 // Trip Input 2 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT3 0x4 // Trip Input 3 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT4 0x8 // Trip Input 4 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT5 0x10 // Trip Input 5 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT6 0x20 // Trip Input 6 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT7 0x40 // Trip Input 7 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT8 0x80 // Trip Input 8 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT9 0x100 // Trip Input 9 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT10 0x200 // Trip Input 10 Select to DCAH + // Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT11 0x400 // Trip Input 11 Select to DCAH + // Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT12 0x800 // Trip Input 12 Select to DCAH + // Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT13 0x1000 // Trip Input 13 Select to DCAH + // Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT14 0x2000 // Trip Input 14 Select to DCAH + // Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT15 0x4000 // Trip Input 15 Select to DCAH + // Mux + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCALTRIPSEL register +// +//***************************************************************************** +#define EPWM_DCALTRIPSEL_TRIPINPUT1 0x1 // Trip Input 1 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT2 0x2 // Trip Input 2 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT3 0x4 // Trip Input 3 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT4 0x8 // Trip Input 4 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT5 0x10 // Trip Input 5 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT6 0x20 // Trip Input 6 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT7 0x40 // Trip Input 7 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT8 0x80 // Trip Input 8 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT9 0x100 // Trip Input 9 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT10 0x200 // Trip Input 10 Select to DCAL + // Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT11 0x400 // Trip Input 11 Select to DCAL + // Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT12 0x800 // Trip Input 12 Select to DCAL + // Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT13 0x1000 // Trip Input 13 Select to DCAL + // Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT14 0x2000 // Trip Input 14 Select to DCAL + // Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT15 0x4000 // Trip Input 15 Select to DCAL + // Mux + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCBHTRIPSEL register +// +//***************************************************************************** +#define EPWM_DCBHTRIPSEL_TRIPINPUT1 0x1 // Trip Input 1 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT2 0x2 // Trip Input 2 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT3 0x4 // Trip Input 3 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT4 0x8 // Trip Input 4 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT5 0x10 // Trip Input 5 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT6 0x20 // Trip Input 6 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT7 0x40 // Trip Input 7 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT8 0x80 // Trip Input 8 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT9 0x100 // Trip Input 9 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT10 0x200 // Trip Input 10 Select to DCBH + // Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT11 0x400 // Trip Input 11 Select to DCBH + // Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT12 0x800 // Trip Input 12 Select to DCBH + // Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT13 0x1000 // Trip Input 13 Select to DCBH + // Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT14 0x2000 // Trip Input 14 Select to DCBH + // Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT15 0x4000 // Trip Input 15 Select to DCBH + // Mux + +//***************************************************************************** +// +// The following are defines for the bit fields in the DCBLTRIPSEL register +// +//***************************************************************************** +#define EPWM_DCBLTRIPSEL_TRIPINPUT1 0x1 // Trip Input 1 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT2 0x2 // Trip Input 2 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT3 0x4 // Trip Input 3 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT4 0x8 // Trip Input 4 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT5 0x10 // Trip Input 5 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT6 0x20 // Trip Input 6 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT7 0x40 // Trip Input 7 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT8 0x80 // Trip Input 8 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT9 0x100 // Trip Input 9 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT10 0x200 // Trip Input 10 Select to DCBL + // Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT11 0x400 // Trip Input 11 Select to DCBL + // Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT12 0x800 // Trip Input 12 Select to DCBL + // Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT13 0x1000 // Trip Input 13 Select to DCBL + // Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT14 0x2000 // Trip Input 14 Select to DCBL + // Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT15 0x4000 // Trip Input 15 Select to DCBL + // Mux +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_eqep.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_eqep.h new file mode 100644 index 00000000000..6d5f37b5ebd --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_eqep.h @@ -0,0 +1,391 @@ +//########################################################################### +// +// FILE: hw_eqep.h +// +// TITLE: Definitions for the C28x EQEP registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_EQEP_H__ +#define __HW_EQEP_H__ + +//***************************************************************************** +// +// The following are defines for the EQEP register offsets +// +//***************************************************************************** +#define EQEP_O_QPOSCNT 0x0 // Position Counter +#define EQEP_O_QPOSINIT 0x2 // Position Counter Init +#define EQEP_O_QPOSMAX 0x4 // Maximum Position Count +#define EQEP_O_QPOSCMP 0x6 // Position Compare +#define EQEP_O_QPOSILAT 0x8 // Index Position Latch +#define EQEP_O_QPOSSLAT 0xA // Strobe Position Latch +#define EQEP_O_QPOSLAT 0xC // Position Latch +#define EQEP_O_QUTMR 0xE // QEP Unit Timer +#define EQEP_O_QUPRD 0x10 // QEP Unit Period +#define EQEP_O_QWDTMR 0x12 // QEP Watchdog Timer +#define EQEP_O_QWDPRD 0x13 // QEP Watchdog Period +#define EQEP_O_QDECCTL 0x14 // Quadrature Decoder Control +#define EQEP_O_QEPCTL 0x15 // QEP Control +#define EQEP_O_QCAPCTL 0x16 // Qaudrature Capture Control +#define EQEP_O_QPOSCTL 0x17 // Position Compare Control +#define EQEP_O_QEINT 0x18 // QEP Interrupt Control +#define EQEP_O_QFLG 0x19 // QEP Interrupt Flag +#define EQEP_O_QCLR 0x1A // QEP Interrupt Clear +#define EQEP_O_QFRC 0x1B // QEP Interrupt Force +#define EQEP_O_QEPSTS 0x1C // QEP Status +#define EQEP_O_QCTMR 0x1D // QEP Capture Timer +#define EQEP_O_QCPRD 0x1E // QEP Capture Period +#define EQEP_O_QCTMRLAT 0x1F // QEP Capture Latch +#define EQEP_O_QCPRDLAT 0x20 // QEP Capture Period Latch + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSCNT register +// +//***************************************************************************** +#define EQEP_QPOSCNT_QPOSCNT_S 0 +#define EQEP_QPOSCNT_QPOSCNT_M 0xFFFFFFFF // Position Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSINIT register +// +//***************************************************************************** +#define EQEP_QPOSINIT_QPOSINIT_S 0 +#define EQEP_QPOSINIT_QPOSINIT_M 0xFFFFFFFF // Position Counter Init + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSMAX register +// +//***************************************************************************** +#define EQEP_QPOSMAX_QPOSMAX_S 0 +#define EQEP_QPOSMAX_QPOSMAX_M 0xFFFFFFFF // Maximum Position Count + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSCMP register +// +//***************************************************************************** +#define EQEP_QPOSCMP_QPOSCMP_S 0 +#define EQEP_QPOSCMP_QPOSCMP_M 0xFFFFFFFF // Position Compare + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSILAT register +// +//***************************************************************************** +#define EQEP_QPOSILAT_QPOSILAT_S 0 +#define EQEP_QPOSILAT_QPOSILAT_M 0xFFFFFFFF // Index Position Latch + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSSLAT register +// +//***************************************************************************** +#define EQEP_QPOSSLAT_QPOSSLAT_S 0 +#define EQEP_QPOSSLAT_QPOSSLAT_M 0xFFFFFFFF // Strobe Position Latch + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSLAT register +// +//***************************************************************************** +#define EQEP_QPOSLAT_QPOSLAT_S 0 +#define EQEP_QPOSLAT_QPOSLAT_M 0xFFFFFFFF // Position Latch + +//***************************************************************************** +// +// The following are defines for the bit fields in the QUTMR register +// +//***************************************************************************** +#define EQEP_QUTMR_QUTMR_S 0 +#define EQEP_QUTMR_QUTMR_M 0xFFFFFFFF // QEP Unit Timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the QUPRD register +// +//***************************************************************************** +#define EQEP_QUPRD_QUPRD_S 0 +#define EQEP_QUPRD_QUPRD_M 0xFFFFFFFF // QEP Unit Period + +//***************************************************************************** +// +// The following are defines for the bit fields in the QWDTMR register +// +//***************************************************************************** +#define EQEP_QWDTMR_QWDTMR_S 0 +#define EQEP_QWDTMR_QWDTMR_M 0xFFFF // QEP Watchdog Timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the QWDPRD register +// +//***************************************************************************** +#define EQEP_QWDPRD_QWDPRD_S 0 +#define EQEP_QWDPRD_QWDPRD_M 0xFFFF // QEP Watchdog Period + +//***************************************************************************** +// +// The following are defines for the bit fields in the QDECCTL register +// +//***************************************************************************** +#define EQEP_QDECCTL_QSP 0x20 // QEPS input polarity +#define EQEP_QDECCTL_QIP 0x40 // QEPI input polarity +#define EQEP_QDECCTL_QBP 0x80 // QEPB input polarity +#define EQEP_QDECCTL_QAP 0x100 // QEPA input polarity +#define EQEP_QDECCTL_IGATE 0x200 // Index pulse gating option +#define EQEP_QDECCTL_SWAP 0x400 // CLK/DIR Signal Source for + // Position Counter +#define EQEP_QDECCTL_XCR 0x800 // External Clock Rate +#define EQEP_QDECCTL_SPSEL 0x1000 // Sync output pin selection +#define EQEP_QDECCTL_SOEN 0x2000 // Sync output-enable +#define EQEP_QDECCTL_QSRC_S 14 +#define EQEP_QDECCTL_QSRC_M 0xC000 // Position-counter source + // selection + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEPCTL register +// +//***************************************************************************** +#define EQEP_QEPCTL_WDE 0x1 // QEP watchdog enable +#define EQEP_QEPCTL_UTE 0x2 // QEP unit timer enable +#define EQEP_QEPCTL_QCLM 0x4 // QEP capture latch mode +#define EQEP_QEPCTL_QPEN 0x8 // Quadrature postotion counter + // enable +#define EQEP_QEPCTL_IEL_S 4 +#define EQEP_QEPCTL_IEL_M 0x30 // Index event latch +#define EQEP_QEPCTL_SEL 0x40 // Strobe event latch +#define EQEP_QEPCTL_SWI 0x80 // Software init position counter +#define EQEP_QEPCTL_IEI_S 8 +#define EQEP_QEPCTL_IEI_M 0x300 // Index event init of position + // count +#define EQEP_QEPCTL_SEI_S 10 +#define EQEP_QEPCTL_SEI_M 0xC00 // Strobe event init +#define EQEP_QEPCTL_PCRM_S 12 +#define EQEP_QEPCTL_PCRM_M 0x3000 // Postion counter reset +#define EQEP_QEPCTL_FREE_SOFT_S 14 +#define EQEP_QEPCTL_FREE_SOFT_M 0xC000 // Emulation mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCAPCTL register +// +//***************************************************************************** +#define EQEP_QCAPCTL_UPPS_S 0 +#define EQEP_QCAPCTL_UPPS_M 0xF // Unit position event prescaler +#define EQEP_QCAPCTL_CCPS_S 4 +#define EQEP_QCAPCTL_CCPS_M 0x70 // eQEP capture timer clock + // prescaler +#define EQEP_QCAPCTL_CEN 0x8000 // Enable eQEP capture + +//***************************************************************************** +// +// The following are defines for the bit fields in the QPOSCTL register +// +//***************************************************************************** +#define EQEP_QPOSCTL_PCSPW_S 0 +#define EQEP_QPOSCTL_PCSPW_M 0xFFF // Position compare sync pulse + // width +#define EQEP_QPOSCTL_PCE 0x1000 // Position compare enable/disable +#define EQEP_QPOSCTL_PCPOL 0x2000 // Polarity of sync output +#define EQEP_QPOSCTL_PCLOAD 0x4000 // Position compare of shadow load +#define EQEP_QPOSCTL_PCSHDW 0x8000 // Position compare of shadow + // enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEINT register +// +//***************************************************************************** +#define EQEP_QEINT_PCE 0x2 // Position counter error + // interrupt enable +#define EQEP_QEINT_QPE 0x4 // Quadrature phase error + // interrupt enable +#define EQEP_QEINT_QDC 0x8 // Quadrature direction change + // interrupt enable +#define EQEP_QEINT_WTO 0x10 // Watchdog time out interrupt + // enable +#define EQEP_QEINT_PCU 0x20 // Position counter underflow + // interrupt enable +#define EQEP_QEINT_PCO 0x40 // Position counter overflow + // interrupt enable +#define EQEP_QEINT_PCR 0x80 // Position-compare ready + // interrupt enable +#define EQEP_QEINT_PCM 0x100 // Position-compare match + // interrupt enable +#define EQEP_QEINT_SEL 0x200 // Strobe event latch interrupt + // enable +#define EQEP_QEINT_IEL 0x400 // Index event latch interrupt + // enable +#define EQEP_QEINT_UTO 0x800 // Unit time out interrupt enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QFLG register +// +//***************************************************************************** +#define EQEP_QFLG_INT 0x1 // Global interrupt status flag +#define EQEP_QFLG_PCE 0x2 // Position counter error + // interrupt flag +#define EQEP_QFLG_PHE 0x4 // Quadrature phase error + // interrupt flag +#define EQEP_QFLG_QDC 0x8 // Quadrature direction change + // interrupt flag +#define EQEP_QFLG_WTO 0x10 // Watchdog timeout interrupt flag +#define EQEP_QFLG_PCU 0x20 // Position counter underflow + // interrupt flag +#define EQEP_QFLG_PCO 0x40 // Position counter overflow + // interrupt flag +#define EQEP_QFLG_PCR 0x80 // Position-compare ready + // interrupt flag +#define EQEP_QFLG_PCM 0x100 // eQEP compare match event + // interrupt flag +#define EQEP_QFLG_SEL 0x200 // Strobe event latch interrupt + // flag +#define EQEP_QFLG_IEL 0x400 // Index event latch interrupt + // flag +#define EQEP_QFLG_UTO 0x800 // Unit time out interrupt flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCLR register +// +//***************************************************************************** +#define EQEP_QCLR_INT 0x1 // Global interrupt clear flag +#define EQEP_QCLR_PCE 0x2 // Clear position counter error + // interrupt flag +#define EQEP_QCLR_PHE 0x4 // Clear quadrature phase error + // interrupt flag +#define EQEP_QCLR_QDC 0x8 // Clear quadrature direction + // change interrupt flag +#define EQEP_QCLR_WTO 0x10 // Clear watchdog timeout + // interrupt flag +#define EQEP_QCLR_PCU 0x20 // Clear position counter + // underflow interrupt flag +#define EQEP_QCLR_PCO 0x40 // Clear position counter overflow + // interrupt flag +#define EQEP_QCLR_PCR 0x80 // Clear position-compare ready + // interrupt flag +#define EQEP_QCLR_PCM 0x100 // Clear eQEP compare match event + // interrupt flag +#define EQEP_QCLR_SEL 0x200 // Clear strobe event latch + // interrupt flag +#define EQEP_QCLR_IEL 0x400 // Clear index event latch + // interrupt flag +#define EQEP_QCLR_UTO 0x800 // Clear unit time out interrupt + // flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the QFRC register +// +//***************************************************************************** +#define EQEP_QFRC_PCE 0x2 // Force position counter error + // interrupt +#define EQEP_QFRC_PHE 0x4 // Force quadrature phase error + // interrupt +#define EQEP_QFRC_QDC 0x8 // Force quadrature direction + // change interrupt +#define EQEP_QFRC_WTO 0x10 // Force watchdog time out + // interrupt +#define EQEP_QFRC_PCU 0x20 // Force position counter + // underflow interrupt +#define EQEP_QFRC_PCO 0x40 // Force position counter overflow + // interrupt +#define EQEP_QFRC_PCR 0x80 // Force position-compare ready + // interrupt +#define EQEP_QFRC_PCM 0x100 // Force position-compare match + // interrupt +#define EQEP_QFRC_SEL 0x200 // Force strobe event latch + // interrupt +#define EQEP_QFRC_IEL 0x400 // Force index event latch + // interrupt +#define EQEP_QFRC_UTO 0x800 // Force unit time out interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEPSTS register +// +//***************************************************************************** +#define EQEP_QEPSTS_PCEF 0x1 // Position counter error flag. +#define EQEP_QEPSTS_FIMF 0x2 // First index marker flag +#define EQEP_QEPSTS_CDEF 0x4 // Capture direction error flag +#define EQEP_QEPSTS_COEF 0x8 // Capture overflow error flag +#define EQEP_QEPSTS_QDLF 0x10 // eQEP direction latch flag +#define EQEP_QEPSTS_QDF 0x20 // Quadrature direction flag +#define EQEP_QEPSTS_FIDF 0x40 // The first index marker +#define EQEP_QEPSTS_UPEVNT 0x80 // Unit position event flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCTMR register +// +//***************************************************************************** +#define EQEP_QCTMR_QCTMR_S 0 +#define EQEP_QCTMR_QCTMR_M 0xFFFF // This register provides time + // base for edge capture unit. + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCPRD register +// +//***************************************************************************** +#define EQEP_QCPRD_QCPRD_S 0 +#define EQEP_QCPRD_QCPRD_M 0xFFFF // Period count value between + // eQEP position events + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCTMRLAT register +// +//***************************************************************************** +#define EQEP_QCTMRLAT_QCTMRLAT_S 0 +#define EQEP_QCTMRLAT_QCTMRLAT_M 0xFFFF // The eQEP capture timer latch + // value + +//***************************************************************************** +// +// The following are defines for the bit fields in the QCPRDLAT register +// +//***************************************************************************** +#define EQEP_QCPRDLAT_QCPRDLAT_S 0 +#define EQEP_QCPRDLAT_QCPRDLAT_M 0xFFFF // eQEP capture period latch value +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_gpio.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_gpio.h new file mode 100644 index 00000000000..63c4f62a1eb --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_gpio.h @@ -0,0 +1,5662 @@ +//########################################################################### +// +// FILE: hw_gpio.h +// +// TITLE: Definitions for the C28x GPIO registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO register offsets +// +//***************************************************************************** +#define GPIO_O_GPACTRL 0x0 // GPIO A Qualification Sampling + // Period Control (GPIO0 to 31) +#define GPIO_O_GPAQSEL1 0x2 // GPIO A Qualifier Select 1 + // Register (GPIO0 to 15) +#define GPIO_O_GPAQSEL2 0x4 // GPIO A Qualifier Select 2 + // Register (GPIO16 to 31) +#define GPIO_O_GPAMUX1 0x6 // GPIO A Mux 1 Register (GPIO0 to + // 15) +#define GPIO_O_GPAMUX2 0x8 // GPIO A Mux 2 Register (GPIO16 + // to 31) +#define GPIO_O_GPADIR 0xA // GPIO A Direction Register + // (GPIO0 to 31) +#define GPIO_O_GPAPUD 0xC // GPIO A Pull Up Disable Register + // (GPIO0 to 31) +#define GPIO_O_GPAINV 0x10 // GPIO A Input Polarity Invert + // Registers (GPIO0 to 31) +#define GPIO_O_GPAODR 0x12 // GPIO A Open Drain Output + // Register (GPIO0 to GPIO31) +#define GPIO_O_GPAGMUX1 0x20 // GPIO A Peripheral Group Mux + // (GPIO0 to 15) +#define GPIO_O_GPAGMUX2 0x22 // GPIO A Peripheral Group Mux + // (GPIO16 to 31) +#define GPIO_O_GPACSEL1 0x28 // GPIO A Core Select Register + // (GPIO0 to 7) +#define GPIO_O_GPACSEL2 0x2A // GPIO A Core Select Register + // (GPIO8 to 15) +#define GPIO_O_GPACSEL3 0x2C // GPIO A Core Select Register + // (GPIO16 to 23) +#define GPIO_O_GPACSEL4 0x2E // GPIO A Core Select Register + // (GPIO24 to 31) +#define GPIO_O_GPALOCK 0x3C // GPIO A Lock Configuration + // Register (GPIO0 to 31) +#define GPIO_O_GPACR 0x3E // GPIO A Lock Commit Register + // (GPIO0 to 31) +#define GPIO_O_GPBCTRL 0x40 // GPIO B Qualification Sampling + // Period Control (GPIO32 to 63) +#define GPIO_O_GPBQSEL1 0x42 // GPIO B Qualifier Select 1 + // Register (GPIO32 to 47) +#define GPIO_O_GPBQSEL2 0x44 // GPIO B Qualifier Select 2 + // Register (GPIO48 to 63) +#define GPIO_O_GPBMUX1 0x46 // GPIO B Mux 1 Register (GPIO32 + // to 47) +#define GPIO_O_GPBMUX2 0x48 // GPIO B Mux 2 Register (GPIO48 + // to 63) +#define GPIO_O_GPBDIR 0x4A // GPIO B Direction Register + // (GPIO32 to 63) +#define GPIO_O_GPBPUD 0x4C // GPIO B Pull Up Disable Register + // (GPIO32 to 63) +#define GPIO_O_GPBINV 0x50 // GPIO B Input Polarity Invert + // Registers (GPIO32 to 63) +#define GPIO_O_GPBODR 0x52 // GPIO B Open Drain Output + // Register (GPIO32 to GPIO63) +#define GPIO_O_GPBAMSEL 0x54 // GPIO B Analog Mode Select + // register (GPIO32 to GPIO63) +#define GPIO_O_GPBGMUX1 0x60 // GPIO B Peripheral Group Mux + // (GPIO32 to 47) +#define GPIO_O_GPBGMUX2 0x62 // GPIO B Peripheral Group Mux + // (GPIO48 to 63) +#define GPIO_O_GPBCSEL1 0x68 // GPIO B Core Select Register + // (GPIO32 to 39) +#define GPIO_O_GPBCSEL2 0x6A // GPIO B Core Select Register + // (GPIO40 to 47) +#define GPIO_O_GPBCSEL3 0x6C // GPIO B Core Select Register + // (GPIO48 to 55) +#define GPIO_O_GPBCSEL4 0x6E // GPIO B Core Select Register + // (GPIO56 to 63) +#define GPIO_O_GPBLOCK 0x7C // GPIO B Lock Configuration + // Register (GPIO32 to 63) +#define GPIO_O_GPBCR 0x7E // GPIO B Lock Commit Register + // (GPIO32 to 63) +#define GPIO_O_GPCCTRL 0x80 // GPIO C Qualification Sampling + // Period Control (GPIO64 to 95) +#define GPIO_O_GPCQSEL1 0x82 // GPIO C Qualifier Select 1 + // Register (GPIO64 to 79) +#define GPIO_O_GPCQSEL2 0x84 // GPIO C Qualifier Select 2 + // Register (GPIO80 to 95) +#define GPIO_O_GPCMUX1 0x86 // GPIO C Mux 1 Register (GPIO64 + // to 79) +#define GPIO_O_GPCMUX2 0x88 // GPIO C Mux 2 Register (GPIO80 + // to 95) +#define GPIO_O_GPCDIR 0x8A // GPIO C Direction Register + // (GPIO64 to 95) +#define GPIO_O_GPCPUD 0x8C // GPIO C Pull Up Disable Register + // (GPIO64 to 95) +#define GPIO_O_GPCINV 0x90 // GPIO C Input Polarity Invert + // Registers (GPIO64 to 95) +#define GPIO_O_GPCODR 0x92 // GPIO C Open Drain Output + // Register (GPIO64 to GPIO95) +#define GPIO_O_GPCGMUX1 0xA0 // GPIO C Peripheral Group Mux + // (GPIO64 to 79) +#define GPIO_O_GPCGMUX2 0xA2 // GPIO C Peripheral Group Mux + // (GPIO80 to 95) +#define GPIO_O_GPCCSEL1 0xA8 // GPIO C Core Select Register + // (GPIO64 to 71) +#define GPIO_O_GPCCSEL2 0xAA // GPIO C Core Select Register + // (GPIO72 to 79) +#define GPIO_O_GPCCSEL3 0xAC // GPIO C Core Select Register + // (GPIO80 to 87) +#define GPIO_O_GPCCSEL4 0xAE // GPIO C Core Select Register + // (GPIO88 to 95) +#define GPIO_O_GPCLOCK 0xBC // GPIO C Lock Configuration + // Register (GPIO64 to 95) +#define GPIO_O_GPCCR 0xBE // GPIO C Lock Commit Register + // (GPIO64 to 95) +#define GPIO_O_GPDCTRL 0xC0 // GPIO D Qualification Sampling + // Period Control (GPIO96 to 127) +#define GPIO_O_GPDQSEL1 0xC2 // GPIO D Qualifier Select 1 + // Register (GPIO96 to 111) +#define GPIO_O_GPDQSEL2 0xC4 // GPIO D Qualifier Select 2 + // Register (GPIO112 to 127) +#define GPIO_O_GPDMUX1 0xC6 // GPIO D Mux 1 Register (GPIO96 + // to 111) +#define GPIO_O_GPDMUX2 0xC8 // GPIO D Mux 2 Register (GPIO112 + // to 127) +#define GPIO_O_GPDDIR 0xCA // GPIO D Direction Register + // (GPIO96 to 127) +#define GPIO_O_GPDPUD 0xCC // GPIO D Pull Up Disable Register + // (GPIO96 to 127) +#define GPIO_O_GPDINV 0xD0 // GPIO D Input Polarity Invert + // Registers (GPIO96 to 127) +#define GPIO_O_GPDODR 0xD2 // GPIO D Open Drain Output + // Register (GPIO96 to GPIO127) +#define GPIO_O_GPDGMUX1 0xE0 // GPIO D Peripheral Group Mux + // (GPIO96 to 111) +#define GPIO_O_GPDGMUX2 0xE2 // GPIO D Peripheral Group Mux + // (GPIO112 to 127) +#define GPIO_O_GPDCSEL1 0xE8 // GPIO D Core Select Register + // (GPIO96 to 103) +#define GPIO_O_GPDCSEL2 0xEA // GPIO D Core Select Register + // (GPIO104 to 111) +#define GPIO_O_GPDCSEL3 0xEC // GPIO D Core Select Register + // (GPIO112 to 119) +#define GPIO_O_GPDCSEL4 0xEE // GPIO D Core Select Register + // (GPIO120 to 127) +#define GPIO_O_GPDLOCK 0xFC // GPIO D Lock Configuration + // Register (GPIO96 to 127) +#define GPIO_O_GPDCR 0xFE // GPIO D Lock Commit Register + // (GPIO96 to 127) +#define GPIO_O_GPECTRL 0x100 // GPIO E Qualification Sampling + // Period Control (GPIO128 to + // 159) +#define GPIO_O_GPEQSEL1 0x102 // GPIO E Qualifier Select 1 + // Register (GPIO128 to 143) +#define GPIO_O_GPEQSEL2 0x104 // GPIO E Qualifier Select 2 + // Register (GPIO144 to 159) +#define GPIO_O_GPEMUX1 0x106 // GPIO E Mux 1 Register (GPIO128 + // to 143) +#define GPIO_O_GPEMUX2 0x108 // GPIO E Mux 2 Register (GPIO144 + // to 159) +#define GPIO_O_GPEDIR 0x10A // GPIO E Direction Register + // (GPIO128 to 159) +#define GPIO_O_GPEPUD 0x10C // GPIO E Pull Up Disable Register + // (GPIO128 to 159) +#define GPIO_O_GPEINV 0x110 // GPIO E Input Polarity Invert + // Registers (GPIO128 to 159) +#define GPIO_O_GPEODR 0x112 // GPIO E Open Drain Output + // Register (GPIO128 to GPIO159) +#define GPIO_O_GPEGMUX1 0x120 // GPIO E Peripheral Group Mux + // (GPIO128 to 143) +#define GPIO_O_GPEGMUX2 0x122 // GPIO E Peripheral Group Mux + // (GPIO144 to 159) +#define GPIO_O_GPECSEL1 0x128 // GPIO E Core Select Register + // (GPIO128 to 135) +#define GPIO_O_GPECSEL2 0x12A // GPIO E Core Select Register + // (GPIO136 to 143) +#define GPIO_O_GPECSEL3 0x12C // GPIO E Core Select Register + // (GPIO144 to 151) +#define GPIO_O_GPECSEL4 0x12E // GPIO E Core Select Register + // (GPIO152 to 159) +#define GPIO_O_GPELOCK 0x13C // GPIO E Lock Configuration + // Register (GPIO128 to 159) +#define GPIO_O_GPECR 0x13E // GPIO E Lock Commit Register + // (GPIO128 to 159) +#define GPIO_O_GPFCTRL 0x140 // GPIO F Qualification Sampling + // Period Control (GPIO160 to + // 168) +#define GPIO_O_GPFQSEL1 0x142 // GPIO F Qualifier Select 1 + // Register (GPIO160 to 168) +#define GPIO_O_GPFMUX1 0x146 // GPIO F Mux 1 Register (GPIO160 + // to 168) +#define GPIO_O_GPFDIR 0x14A // GPIO F Direction Register + // (GPIO160 to 168) +#define GPIO_O_GPFPUD 0x14C // GPIO F Pull Up Disable Register + // (GPIO160 to 168) +#define GPIO_O_GPFINV 0x150 // GPIO F Input Polarity Invert + // Registers (GPIO160 to 168) +#define GPIO_O_GPFODR 0x152 // GPIO F Open Drain Output + // Register (GPIO160 to GPIO168) +#define GPIO_O_GPFGMUX1 0x160 // GPIO F Peripheral Group Mux + // (GPIO160 to 168) +#define GPIO_O_GPFCSEL1 0x168 // GPIO F Core Select Register + // (GPIO160 to 167) +#define GPIO_O_GPFCSEL2 0x16A // GPIO F Core Select Register + // (GPIO168) +#define GPIO_O_GPFLOCK 0x17C // GPIO F Lock Configuration + // Register (GPIO160 to 168) +#define GPIO_O_GPFCR 0x17E // GPIO F Lock Commit Register + // (GPIO160 to 168) +#define GPIO_O_GPADAT 0x0 // GPIO A Data Register (GPIO0 to + // 31) +#define GPIO_O_GPASET 0x2 // GPIO A Data Set Register (GPIO0 + // to 31) +#define GPIO_O_GPACLEAR 0x4 // GPIO A Data Clear Register + // (GPIO0 to 31) +#define GPIO_O_GPATOGGLE 0x6 // GPIO A Data Toggle Register + // (GPIO0 to 31) +#define GPIO_O_GPBDAT 0x8 // GPIO B Data Register (GPIO32 to + // 63) +#define GPIO_O_GPBSET 0xA // GPIO B Data Set Register + // (GPIO32 to 63) +#define GPIO_O_GPBCLEAR 0xC // GPIO B Data Clear Register + // (GPIO32 to 63) +#define GPIO_O_GPBTOGGLE 0xE // GPIO B Data Toggle Register + // (GPIO32 to 63) +#define GPIO_O_GPCDAT 0x10 // GPIO C Data Register (GPIO64 to + // 95) +#define GPIO_O_GPCSET 0x12 // GPIO C Data Set Register + // (GPIO64 to 95) +#define GPIO_O_GPCCLEAR 0x14 // GPIO C Data Clear Register + // (GPIO64 to 95) +#define GPIO_O_GPCTOGGLE 0x16 // GPIO C Data Toggle Register + // (GPIO64 to 95) +#define GPIO_O_GPDDAT 0x18 // GPIO D Data Register (GPIO96 to + // 127) +#define GPIO_O_GPDSET 0x1A // GPIO D Data Set Register + // (GPIO96 to 127) +#define GPIO_O_GPDCLEAR 0x1C // GPIO D Data Clear Register + // (GPIO96 to 127) +#define GPIO_O_GPDTOGGLE 0x1E // GPIO D Data Toggle Register + // (GPIO96 to 127) +#define GPIO_O_GPEDAT 0x20 // GPIO E Data Register (GPIO128 + // to 159) +#define GPIO_O_GPESET 0x22 // GPIO E Data Set Register + // (GPIO128 to 159) +#define GPIO_O_GPECLEAR 0x24 // GPIO E Data Clear Register + // (GPIO128 to 159) +#define GPIO_O_GPETOGGLE 0x26 // GPIO E Data Toggle Register + // (GPIO128 to 159) +#define GPIO_O_GPFDAT 0x28 // GPIO F Data Register (GPIO160 + // to 168) +#define GPIO_O_GPFSET 0x2A // GPIO F Data Set Register + // (GPIO160 to 168) +#define GPIO_O_GPFCLEAR 0x2C // GPIO F Data Clear Register + // (GPIO160 to 168) +#define GPIO_O_GPFTOGGLE 0x2E // GPIO F Data Toggle Register + // (GPIO160 to 168) + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACTRL register +// +//***************************************************************************** +#define GPIO_GPACTRL_QUALPRD0_S 0 +#define GPIO_GPACTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO0 to GPIO7 +#define GPIO_GPACTRL_QUALPRD1_S 8 +#define GPIO_GPACTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO8 to GPIO15 +#define GPIO_GPACTRL_QUALPRD2_S 16 +#define GPIO_GPACTRL_QUALPRD2_M 0xFF0000 // Qualification sampling period + // for GPIO16 to GPIO23 +#define GPIO_GPACTRL_QUALPRD3_S 24 +#define GPIO_GPACTRL_QUALPRD3_M 0xFF000000 // Qualification sampling period + // for GPIO24 to GPIO31 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAQSEL1 register +// +//***************************************************************************** +#define GPIO_GPAQSEL1_GPIO0_S 0 +#define GPIO_GPAQSEL1_GPIO0_M 0x3 // Select input qualification type + // for GPIO0 +#define GPIO_GPAQSEL1_GPIO1_S 2 +#define GPIO_GPAQSEL1_GPIO1_M 0xC // Select input qualification type + // for GPIO1 +#define GPIO_GPAQSEL1_GPIO2_S 4 +#define GPIO_GPAQSEL1_GPIO2_M 0x30 // Select input qualification type + // for GPIO2 +#define GPIO_GPAQSEL1_GPIO3_S 6 +#define GPIO_GPAQSEL1_GPIO3_M 0xC0 // Select input qualification type + // for GPIO3 +#define GPIO_GPAQSEL1_GPIO4_S 8 +#define GPIO_GPAQSEL1_GPIO4_M 0x300 // Select input qualification type + // for GPIO4 +#define GPIO_GPAQSEL1_GPIO5_S 10 +#define GPIO_GPAQSEL1_GPIO5_M 0xC00 // Select input qualification type + // for GPIO5 +#define GPIO_GPAQSEL1_GPIO6_S 12 +#define GPIO_GPAQSEL1_GPIO6_M 0x3000 // Select input qualification type + // for GPIO6 +#define GPIO_GPAQSEL1_GPIO7_S 14 +#define GPIO_GPAQSEL1_GPIO7_M 0xC000 // Select input qualification type + // for GPIO7 +#define GPIO_GPAQSEL1_GPIO8_S 16 +#define GPIO_GPAQSEL1_GPIO8_M 0x30000 // Select input qualification type + // for GPIO8 +#define GPIO_GPAQSEL1_GPIO9_S 18 +#define GPIO_GPAQSEL1_GPIO9_M 0xC0000 // Select input qualification type + // for GPIO9 +#define GPIO_GPAQSEL1_GPIO10_S 20 +#define GPIO_GPAQSEL1_GPIO10_M 0x300000 // Select input qualification type + // for GPIO10 +#define GPIO_GPAQSEL1_GPIO11_S 22 +#define GPIO_GPAQSEL1_GPIO11_M 0xC00000 // Select input qualification type + // for GPIO11 +#define GPIO_GPAQSEL1_GPIO12_S 24 +#define GPIO_GPAQSEL1_GPIO12_M 0x3000000 // Select input qualification type + // for GPIO12 +#define GPIO_GPAQSEL1_GPIO13_S 26 +#define GPIO_GPAQSEL1_GPIO13_M 0xC000000 // Select input qualification type + // for GPIO13 +#define GPIO_GPAQSEL1_GPIO14_S 28 +#define GPIO_GPAQSEL1_GPIO14_M 0x30000000 // Select input qualification type + // for GPIO14 +#define GPIO_GPAQSEL1_GPIO15_S 30 +#define GPIO_GPAQSEL1_GPIO15_M 0xC0000000 // Select input qualification type + // for GPIO15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAQSEL2 register +// +//***************************************************************************** +#define GPIO_GPAQSEL2_GPIO16_S 0 +#define GPIO_GPAQSEL2_GPIO16_M 0x3 // Select input qualification type + // for GPIO16 +#define GPIO_GPAQSEL2_GPIO17_S 2 +#define GPIO_GPAQSEL2_GPIO17_M 0xC // Select input qualification type + // for GPIO17 +#define GPIO_GPAQSEL2_GPIO18_S 4 +#define GPIO_GPAQSEL2_GPIO18_M 0x30 // Select input qualification type + // for GPIO18 +#define GPIO_GPAQSEL2_GPIO19_S 6 +#define GPIO_GPAQSEL2_GPIO19_M 0xC0 // Select input qualification type + // for GPIO19 +#define GPIO_GPAQSEL2_GPIO20_S 8 +#define GPIO_GPAQSEL2_GPIO20_M 0x300 // Select input qualification type + // for GPIO20 +#define GPIO_GPAQSEL2_GPIO21_S 10 +#define GPIO_GPAQSEL2_GPIO21_M 0xC00 // Select input qualification type + // for GPIO21 +#define GPIO_GPAQSEL2_GPIO22_S 12 +#define GPIO_GPAQSEL2_GPIO22_M 0x3000 // Select input qualification type + // for GPIO22 +#define GPIO_GPAQSEL2_GPIO23_S 14 +#define GPIO_GPAQSEL2_GPIO23_M 0xC000 // Select input qualification type + // for GPIO23 +#define GPIO_GPAQSEL2_GPIO24_S 16 +#define GPIO_GPAQSEL2_GPIO24_M 0x30000 // Select input qualification type + // for GPIO24 +#define GPIO_GPAQSEL2_GPIO25_S 18 +#define GPIO_GPAQSEL2_GPIO25_M 0xC0000 // Select input qualification type + // for GPIO25 +#define GPIO_GPAQSEL2_GPIO26_S 20 +#define GPIO_GPAQSEL2_GPIO26_M 0x300000 // Select input qualification type + // for GPIO26 +#define GPIO_GPAQSEL2_GPIO27_S 22 +#define GPIO_GPAQSEL2_GPIO27_M 0xC00000 // Select input qualification type + // for GPIO27 +#define GPIO_GPAQSEL2_GPIO28_S 24 +#define GPIO_GPAQSEL2_GPIO28_M 0x3000000 // Select input qualification type + // for GPIO28 +#define GPIO_GPAQSEL2_GPIO29_S 26 +#define GPIO_GPAQSEL2_GPIO29_M 0xC000000 // Select input qualification type + // for GPIO29 +#define GPIO_GPAQSEL2_GPIO30_S 28 +#define GPIO_GPAQSEL2_GPIO30_M 0x30000000 // Select input qualification type + // for GPIO30 +#define GPIO_GPAQSEL2_GPIO31_S 30 +#define GPIO_GPAQSEL2_GPIO31_M 0xC0000000 // Select input qualification type + // for GPIO31 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAMUX1 register +// +//***************************************************************************** +#define GPIO_GPAMUX1_GPIO0_S 0 +#define GPIO_GPAMUX1_GPIO0_M 0x3 // Defines pin-muxing selection + // for GPIO0 +#define GPIO_GPAMUX1_GPIO1_S 2 +#define GPIO_GPAMUX1_GPIO1_M 0xC // Defines pin-muxing selection + // for GPIO1 +#define GPIO_GPAMUX1_GPIO2_S 4 +#define GPIO_GPAMUX1_GPIO2_M 0x30 // Defines pin-muxing selection + // for GPIO2 +#define GPIO_GPAMUX1_GPIO3_S 6 +#define GPIO_GPAMUX1_GPIO3_M 0xC0 // Defines pin-muxing selection + // for GPIO3 +#define GPIO_GPAMUX1_GPIO4_S 8 +#define GPIO_GPAMUX1_GPIO4_M 0x300 // Defines pin-muxing selection + // for GPIO4 +#define GPIO_GPAMUX1_GPIO5_S 10 +#define GPIO_GPAMUX1_GPIO5_M 0xC00 // Defines pin-muxing selection + // for GPIO5 +#define GPIO_GPAMUX1_GPIO6_S 12 +#define GPIO_GPAMUX1_GPIO6_M 0x3000 // Defines pin-muxing selection + // for GPIO6 +#define GPIO_GPAMUX1_GPIO7_S 14 +#define GPIO_GPAMUX1_GPIO7_M 0xC000 // Defines pin-muxing selection + // for GPIO7 +#define GPIO_GPAMUX1_GPIO8_S 16 +#define GPIO_GPAMUX1_GPIO8_M 0x30000 // Defines pin-muxing selection + // for GPIO8 +#define GPIO_GPAMUX1_GPIO9_S 18 +#define GPIO_GPAMUX1_GPIO9_M 0xC0000 // Defines pin-muxing selection + // for GPIO9 +#define GPIO_GPAMUX1_GPIO10_S 20 +#define GPIO_GPAMUX1_GPIO10_M 0x300000 // Defines pin-muxing selection + // for GPIO10 +#define GPIO_GPAMUX1_GPIO11_S 22 +#define GPIO_GPAMUX1_GPIO11_M 0xC00000 // Defines pin-muxing selection + // for GPIO11 +#define GPIO_GPAMUX1_GPIO12_S 24 +#define GPIO_GPAMUX1_GPIO12_M 0x3000000 // Defines pin-muxing selection + // for GPIO12 +#define GPIO_GPAMUX1_GPIO13_S 26 +#define GPIO_GPAMUX1_GPIO13_M 0xC000000 // Defines pin-muxing selection + // for GPIO13 +#define GPIO_GPAMUX1_GPIO14_S 28 +#define GPIO_GPAMUX1_GPIO14_M 0x30000000 // Defines pin-muxing selection + // for GPIO14 +#define GPIO_GPAMUX1_GPIO15_S 30 +#define GPIO_GPAMUX1_GPIO15_M 0xC0000000 // Defines pin-muxing selection + // for GPIO15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAMUX2 register +// +//***************************************************************************** +#define GPIO_GPAMUX2_GPIO16_S 0 +#define GPIO_GPAMUX2_GPIO16_M 0x3 // Defines pin-muxing selection + // for GPIO16 +#define GPIO_GPAMUX2_GPIO17_S 2 +#define GPIO_GPAMUX2_GPIO17_M 0xC // Defines pin-muxing selection + // for GPIO17 +#define GPIO_GPAMUX2_GPIO18_S 4 +#define GPIO_GPAMUX2_GPIO18_M 0x30 // Defines pin-muxing selection + // for GPIO18 +#define GPIO_GPAMUX2_GPIO19_S 6 +#define GPIO_GPAMUX2_GPIO19_M 0xC0 // Defines pin-muxing selection + // for GPIO19 +#define GPIO_GPAMUX2_GPIO20_S 8 +#define GPIO_GPAMUX2_GPIO20_M 0x300 // Defines pin-muxing selection + // for GPIO20 +#define GPIO_GPAMUX2_GPIO21_S 10 +#define GPIO_GPAMUX2_GPIO21_M 0xC00 // Defines pin-muxing selection + // for GPIO21 +#define GPIO_GPAMUX2_GPIO22_S 12 +#define GPIO_GPAMUX2_GPIO22_M 0x3000 // Defines pin-muxing selection + // for GPIO22 +#define GPIO_GPAMUX2_GPIO23_S 14 +#define GPIO_GPAMUX2_GPIO23_M 0xC000 // Defines pin-muxing selection + // for GPIO23 +#define GPIO_GPAMUX2_GPIO24_S 16 +#define GPIO_GPAMUX2_GPIO24_M 0x30000 // Defines pin-muxing selection + // for GPIO24 +#define GPIO_GPAMUX2_GPIO25_S 18 +#define GPIO_GPAMUX2_GPIO25_M 0xC0000 // Defines pin-muxing selection + // for GPIO25 +#define GPIO_GPAMUX2_GPIO26_S 20 +#define GPIO_GPAMUX2_GPIO26_M 0x300000 // Defines pin-muxing selection + // for GPIO26 +#define GPIO_GPAMUX2_GPIO27_S 22 +#define GPIO_GPAMUX2_GPIO27_M 0xC00000 // Defines pin-muxing selection + // for GPIO27 +#define GPIO_GPAMUX2_GPIO28_S 24 +#define GPIO_GPAMUX2_GPIO28_M 0x3000000 // Defines pin-muxing selection + // for GPIO28 +#define GPIO_GPAMUX2_GPIO29_S 26 +#define GPIO_GPAMUX2_GPIO29_M 0xC000000 // Defines pin-muxing selection + // for GPIO29 +#define GPIO_GPAMUX2_GPIO30_S 28 +#define GPIO_GPAMUX2_GPIO30_M 0x30000000 // Defines pin-muxing selection + // for GPIO30 +#define GPIO_GPAMUX2_GPIO31_S 30 +#define GPIO_GPAMUX2_GPIO31_M 0xC0000000 // Defines pin-muxing selection + // for GPIO31 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPADIR register +// +//***************************************************************************** +#define GPIO_GPADIR_GPIO0 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO1 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO2 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO3 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO4 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO5 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO6 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO7 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO8 0x100 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO9 0x200 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO10 0x400 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO11 0x800 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO12 0x1000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO13 0x2000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO14 0x4000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO15 0x8000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO16 0x10000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO17 0x20000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO18 0x40000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO19 0x80000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO20 0x100000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO21 0x200000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO22 0x400000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO23 0x800000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO24 0x1000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO25 0x2000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO26 0x4000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO27 0x8000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO28 0x10000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO29 0x20000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO30 0x40000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPADIR_GPIO31 0x80000000 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAPUD register +// +//***************************************************************************** +#define GPIO_GPAPUD_GPIO0 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO1 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO2 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO3 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO4 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO5 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO6 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO7 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO8 0x100 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO9 0x200 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO10 0x400 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO11 0x800 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO12 0x1000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO13 0x2000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO14 0x4000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO15 0x8000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO16 0x10000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO17 0x20000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO18 0x40000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO19 0x80000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO20 0x100000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO21 0x200000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO22 0x400000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO23 0x800000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO24 0x1000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO25 0x2000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO26 0x4000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO27 0x8000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO28 0x10000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO29 0x20000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO30 0x40000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPAPUD_GPIO31 0x80000000 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAINV register +// +//***************************************************************************** +#define GPIO_GPAINV_GPIO0 0x1 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO1 0x2 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO2 0x4 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO3 0x8 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO4 0x10 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO5 0x20 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO6 0x40 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO7 0x80 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO8 0x100 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO9 0x200 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO10 0x400 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO11 0x800 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO12 0x1000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO13 0x2000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO14 0x4000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO15 0x8000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO16 0x10000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO17 0x20000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO18 0x40000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO19 0x80000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO20 0x100000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO21 0x200000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO22 0x400000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO23 0x800000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO24 0x1000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO25 0x2000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO26 0x4000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO27 0x8000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO28 0x10000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO29 0x20000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO30 0x40000000 // Input inversion control for + // this pin +#define GPIO_GPAINV_GPIO31 0x80000000 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAODR register +// +//***************************************************************************** +#define GPIO_GPAODR_GPIO0 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO1 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO2 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO3 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO4 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO5 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO6 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO7 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO8 0x100 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO9 0x200 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO10 0x400 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO11 0x800 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO12 0x1000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO13 0x2000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO14 0x4000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO15 0x8000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO16 0x10000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO17 0x20000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO18 0x40000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO19 0x80000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO20 0x100000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO21 0x200000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO22 0x400000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO23 0x800000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO24 0x1000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO25 0x2000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO26 0x4000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO27 0x8000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO28 0x10000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO29 0x20000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO30 0x40000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPAODR_GPIO31 0x80000000 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAGMUX1 register +// +//***************************************************************************** +#define GPIO_GPAGMUX1_GPIO0_S 0 +#define GPIO_GPAGMUX1_GPIO0_M 0x3 // Defines pin-muxing selection + // for GPIO0 +#define GPIO_GPAGMUX1_GPIO1_S 2 +#define GPIO_GPAGMUX1_GPIO1_M 0xC // Defines pin-muxing selection + // for GPIO1 +#define GPIO_GPAGMUX1_GPIO2_S 4 +#define GPIO_GPAGMUX1_GPIO2_M 0x30 // Defines pin-muxing selection + // for GPIO2 +#define GPIO_GPAGMUX1_GPIO3_S 6 +#define GPIO_GPAGMUX1_GPIO3_M 0xC0 // Defines pin-muxing selection + // for GPIO3 +#define GPIO_GPAGMUX1_GPIO4_S 8 +#define GPIO_GPAGMUX1_GPIO4_M 0x300 // Defines pin-muxing selection + // for GPIO4 +#define GPIO_GPAGMUX1_GPIO5_S 10 +#define GPIO_GPAGMUX1_GPIO5_M 0xC00 // Defines pin-muxing selection + // for GPIO5 +#define GPIO_GPAGMUX1_GPIO6_S 12 +#define GPIO_GPAGMUX1_GPIO6_M 0x3000 // Defines pin-muxing selection + // for GPIO6 +#define GPIO_GPAGMUX1_GPIO7_S 14 +#define GPIO_GPAGMUX1_GPIO7_M 0xC000 // Defines pin-muxing selection + // for GPIO7 +#define GPIO_GPAGMUX1_GPIO8_S 16 +#define GPIO_GPAGMUX1_GPIO8_M 0x30000 // Defines pin-muxing selection + // for GPIO8 +#define GPIO_GPAGMUX1_GPIO9_S 18 +#define GPIO_GPAGMUX1_GPIO9_M 0xC0000 // Defines pin-muxing selection + // for GPIO9 +#define GPIO_GPAGMUX1_GPIO10_S 20 +#define GPIO_GPAGMUX1_GPIO10_M 0x300000 // Defines pin-muxing selection + // for GPIO10 +#define GPIO_GPAGMUX1_GPIO11_S 22 +#define GPIO_GPAGMUX1_GPIO11_M 0xC00000 // Defines pin-muxing selection + // for GPIO11 +#define GPIO_GPAGMUX1_GPIO12_S 24 +#define GPIO_GPAGMUX1_GPIO12_M 0x3000000 // Defines pin-muxing selection + // for GPIO12 +#define GPIO_GPAGMUX1_GPIO13_S 26 +#define GPIO_GPAGMUX1_GPIO13_M 0xC000000 // Defines pin-muxing selection + // for GPIO13 +#define GPIO_GPAGMUX1_GPIO14_S 28 +#define GPIO_GPAGMUX1_GPIO14_M 0x30000000 // Defines pin-muxing selection + // for GPIO14 +#define GPIO_GPAGMUX1_GPIO15_S 30 +#define GPIO_GPAGMUX1_GPIO15_M 0xC0000000 // Defines pin-muxing selection + // for GPIO15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPAGMUX2 register +// +//***************************************************************************** +#define GPIO_GPAGMUX2_GPIO16_S 0 +#define GPIO_GPAGMUX2_GPIO16_M 0x3 // Defines pin-muxing selection + // for GPIO16 +#define GPIO_GPAGMUX2_GPIO17_S 2 +#define GPIO_GPAGMUX2_GPIO17_M 0xC // Defines pin-muxing selection + // for GPIO17 +#define GPIO_GPAGMUX2_GPIO18_S 4 +#define GPIO_GPAGMUX2_GPIO18_M 0x30 // Defines pin-muxing selection + // for GPIO18 +#define GPIO_GPAGMUX2_GPIO19_S 6 +#define GPIO_GPAGMUX2_GPIO19_M 0xC0 // Defines pin-muxing selection + // for GPIO19 +#define GPIO_GPAGMUX2_GPIO20_S 8 +#define GPIO_GPAGMUX2_GPIO20_M 0x300 // Defines pin-muxing selection + // for GPIO20 +#define GPIO_GPAGMUX2_GPIO21_S 10 +#define GPIO_GPAGMUX2_GPIO21_M 0xC00 // Defines pin-muxing selection + // for GPIO21 +#define GPIO_GPAGMUX2_GPIO22_S 12 +#define GPIO_GPAGMUX2_GPIO22_M 0x3000 // Defines pin-muxing selection + // for GPIO22 +#define GPIO_GPAGMUX2_GPIO23_S 14 +#define GPIO_GPAGMUX2_GPIO23_M 0xC000 // Defines pin-muxing selection + // for GPIO23 +#define GPIO_GPAGMUX2_GPIO24_S 16 +#define GPIO_GPAGMUX2_GPIO24_M 0x30000 // Defines pin-muxing selection + // for GPIO24 +#define GPIO_GPAGMUX2_GPIO25_S 18 +#define GPIO_GPAGMUX2_GPIO25_M 0xC0000 // Defines pin-muxing selection + // for GPIO25 +#define GPIO_GPAGMUX2_GPIO26_S 20 +#define GPIO_GPAGMUX2_GPIO26_M 0x300000 // Defines pin-muxing selection + // for GPIO26 +#define GPIO_GPAGMUX2_GPIO27_S 22 +#define GPIO_GPAGMUX2_GPIO27_M 0xC00000 // Defines pin-muxing selection + // for GPIO27 +#define GPIO_GPAGMUX2_GPIO28_S 24 +#define GPIO_GPAGMUX2_GPIO28_M 0x3000000 // Defines pin-muxing selection + // for GPIO28 +#define GPIO_GPAGMUX2_GPIO29_S 26 +#define GPIO_GPAGMUX2_GPIO29_M 0xC000000 // Defines pin-muxing selection + // for GPIO29 +#define GPIO_GPAGMUX2_GPIO30_S 28 +#define GPIO_GPAGMUX2_GPIO30_M 0x30000000 // Defines pin-muxing selection + // for GPIO30 +#define GPIO_GPAGMUX2_GPIO31_S 30 +#define GPIO_GPAGMUX2_GPIO31_M 0xC0000000 // Defines pin-muxing selection + // for GPIO31 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACSEL1 register +// +//***************************************************************************** +#define GPIO_GPACSEL1_GPIO0_S 0 +#define GPIO_GPACSEL1_GPIO0_M 0xF // GPIO0 Master CPU Select +#define GPIO_GPACSEL1_GPIO1_S 4 +#define GPIO_GPACSEL1_GPIO1_M 0xF0 // GPIO1 Master CPU Select +#define GPIO_GPACSEL1_GPIO2_S 8 +#define GPIO_GPACSEL1_GPIO2_M 0xF00 // GPIO2 Master CPU Select +#define GPIO_GPACSEL1_GPIO3_S 12 +#define GPIO_GPACSEL1_GPIO3_M 0xF000 // GPIO3 Master CPU Select +#define GPIO_GPACSEL1_GPIO4_S 16 +#define GPIO_GPACSEL1_GPIO4_M 0xF0000 // GPIO4 Master CPU Select +#define GPIO_GPACSEL1_GPIO5_S 20 +#define GPIO_GPACSEL1_GPIO5_M 0xF00000 // GPIO5 Master CPU Select +#define GPIO_GPACSEL1_GPIO6_S 24 +#define GPIO_GPACSEL1_GPIO6_M 0xF000000 // GPIO6 Master CPU Select +#define GPIO_GPACSEL1_GPIO7_S 28 +#define GPIO_GPACSEL1_GPIO7_M 0xF0000000 // GPIO7 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACSEL2 register +// +//***************************************************************************** +#define GPIO_GPACSEL2_GPIO8_S 0 +#define GPIO_GPACSEL2_GPIO8_M 0xF // GPIO8 Master CPU Select +#define GPIO_GPACSEL2_GPIO9_S 4 +#define GPIO_GPACSEL2_GPIO9_M 0xF0 // GPIO9 Master CPU Select +#define GPIO_GPACSEL2_GPIO10_S 8 +#define GPIO_GPACSEL2_GPIO10_M 0xF00 // GPIO10 Master CPU Select +#define GPIO_GPACSEL2_GPIO11_S 12 +#define GPIO_GPACSEL2_GPIO11_M 0xF000 // GPIO11 Master CPU Select +#define GPIO_GPACSEL2_GPIO12_S 16 +#define GPIO_GPACSEL2_GPIO12_M 0xF0000 // GPIO12 Master CPU Select +#define GPIO_GPACSEL2_GPIO13_S 20 +#define GPIO_GPACSEL2_GPIO13_M 0xF00000 // GPIO13 Master CPU Select +#define GPIO_GPACSEL2_GPIO14_S 24 +#define GPIO_GPACSEL2_GPIO14_M 0xF000000 // GPIO14 Master CPU Select +#define GPIO_GPACSEL2_GPIO15_S 28 +#define GPIO_GPACSEL2_GPIO15_M 0xF0000000 // GPIO15 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACSEL3 register +// +//***************************************************************************** +#define GPIO_GPACSEL3_GPIO16_S 0 +#define GPIO_GPACSEL3_GPIO16_M 0xF // GPIO16 Master CPU Select +#define GPIO_GPACSEL3_GPIO17_S 4 +#define GPIO_GPACSEL3_GPIO17_M 0xF0 // GPIO17 Master CPU Select +#define GPIO_GPACSEL3_GPIO18_S 8 +#define GPIO_GPACSEL3_GPIO18_M 0xF00 // GPIO18 Master CPU Select +#define GPIO_GPACSEL3_GPIO19_S 12 +#define GPIO_GPACSEL3_GPIO19_M 0xF000 // GPIO19 Master CPU Select +#define GPIO_GPACSEL3_GPIO20_S 16 +#define GPIO_GPACSEL3_GPIO20_M 0xF0000 // GPIO20 Master CPU Select +#define GPIO_GPACSEL3_GPIO21_S 20 +#define GPIO_GPACSEL3_GPIO21_M 0xF00000 // GPIO21 Master CPU Select +#define GPIO_GPACSEL3_GPIO22_S 24 +#define GPIO_GPACSEL3_GPIO22_M 0xF000000 // GPIO22 Master CPU Select +#define GPIO_GPACSEL3_GPIO23_S 28 +#define GPIO_GPACSEL3_GPIO23_M 0xF0000000 // GPIO23 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACSEL4 register +// +//***************************************************************************** +#define GPIO_GPACSEL4_GPIO24_S 0 +#define GPIO_GPACSEL4_GPIO24_M 0xF // GPIO24 Master CPU Select +#define GPIO_GPACSEL4_GPIO25_S 4 +#define GPIO_GPACSEL4_GPIO25_M 0xF0 // GPIO25 Master CPU Select +#define GPIO_GPACSEL4_GPIO26_S 8 +#define GPIO_GPACSEL4_GPIO26_M 0xF00 // GPIO26 Master CPU Select +#define GPIO_GPACSEL4_GPIO27_S 12 +#define GPIO_GPACSEL4_GPIO27_M 0xF000 // GPIO27 Master CPU Select +#define GPIO_GPACSEL4_GPIO28_S 16 +#define GPIO_GPACSEL4_GPIO28_M 0xF0000 // GPIO28 Master CPU Select +#define GPIO_GPACSEL4_GPIO29_S 20 +#define GPIO_GPACSEL4_GPIO29_M 0xF00000 // GPIO29 Master CPU Select +#define GPIO_GPACSEL4_GPIO30_S 24 +#define GPIO_GPACSEL4_GPIO30_M 0xF000000 // GPIO30 Master CPU Select +#define GPIO_GPACSEL4_GPIO31_S 28 +#define GPIO_GPACSEL4_GPIO31_M 0xF0000000 // GPIO31 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPALOCK register +// +//***************************************************************************** +#define GPIO_GPALOCK_GPIO0 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO1 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO2 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO3 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO4 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO5 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO6 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO7 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO8 0x100 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO9 0x200 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO10 0x400 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO11 0x800 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO12 0x1000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO13 0x2000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO14 0x4000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO15 0x8000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO16 0x10000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO17 0x20000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO18 0x40000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO19 0x80000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO20 0x100000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO21 0x200000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO22 0x400000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO23 0x800000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO24 0x1000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO25 0x2000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO26 0x4000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO27 0x8000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO28 0x10000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO29 0x20000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO30 0x40000000 // Configuration Lock bit for this + // pin +#define GPIO_GPALOCK_GPIO31 0x80000000 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACR register +// +//***************************************************************************** +#define GPIO_GPACR_GPIO0 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO1 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO2 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO3 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO4 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO5 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO6 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO7 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO8 0x100 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO9 0x200 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO10 0x400 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO11 0x800 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO12 0x1000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO13 0x2000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO14 0x4000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO15 0x8000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO16 0x10000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO17 0x20000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO18 0x40000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO19 0x80000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO20 0x100000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO21 0x200000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO22 0x400000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO23 0x800000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO24 0x1000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO25 0x2000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO26 0x4000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO27 0x8000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO28 0x10000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO29 0x20000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO30 0x40000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPACR_GPIO31 0x80000000 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCTRL register +// +//***************************************************************************** +#define GPIO_GPBCTRL_QUALPRD0_S 0 +#define GPIO_GPBCTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO32 to GPIO39 +#define GPIO_GPBCTRL_QUALPRD1_S 8 +#define GPIO_GPBCTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO40 to GPIO47 +#define GPIO_GPBCTRL_QUALPRD2_S 16 +#define GPIO_GPBCTRL_QUALPRD2_M 0xFF0000 // Qualification sampling period + // for GPIO48 to GPIO55 +#define GPIO_GPBCTRL_QUALPRD3_S 24 +#define GPIO_GPBCTRL_QUALPRD3_M 0xFF000000 // Qualification sampling period + // for GPIO56 to GPIO63 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBQSEL1 register +// +//***************************************************************************** +#define GPIO_GPBQSEL1_GPIO32_S 0 +#define GPIO_GPBQSEL1_GPIO32_M 0x3 // Select input qualification type + // for GPIO32 +#define GPIO_GPBQSEL1_GPIO33_S 2 +#define GPIO_GPBQSEL1_GPIO33_M 0xC // Select input qualification type + // for GPIO33 +#define GPIO_GPBQSEL1_GPIO34_S 4 +#define GPIO_GPBQSEL1_GPIO34_M 0x30 // Select input qualification type + // for GPIO34 +#define GPIO_GPBQSEL1_GPIO35_S 6 +#define GPIO_GPBQSEL1_GPIO35_M 0xC0 // Select input qualification type + // for GPIO35 +#define GPIO_GPBQSEL1_GPIO36_S 8 +#define GPIO_GPBQSEL1_GPIO36_M 0x300 // Select input qualification type + // for GPIO36 +#define GPIO_GPBQSEL1_GPIO37_S 10 +#define GPIO_GPBQSEL1_GPIO37_M 0xC00 // Select input qualification type + // for GPIO37 +#define GPIO_GPBQSEL1_GPIO38_S 12 +#define GPIO_GPBQSEL1_GPIO38_M 0x3000 // Select input qualification type + // for GPIO38 +#define GPIO_GPBQSEL1_GPIO39_S 14 +#define GPIO_GPBQSEL1_GPIO39_M 0xC000 // Select input qualification type + // for GPIO39 +#define GPIO_GPBQSEL1_GPIO40_S 16 +#define GPIO_GPBQSEL1_GPIO40_M 0x30000 // Select input qualification type + // for GPIO40 +#define GPIO_GPBQSEL1_GPIO41_S 18 +#define GPIO_GPBQSEL1_GPIO41_M 0xC0000 // Select input qualification type + // for GPIO41 +#define GPIO_GPBQSEL1_GPIO42_S 20 +#define GPIO_GPBQSEL1_GPIO42_M 0x300000 // Select input qualification type + // for GPIO42 +#define GPIO_GPBQSEL1_GPIO43_S 22 +#define GPIO_GPBQSEL1_GPIO43_M 0xC00000 // Select input qualification type + // for GPIO43 +#define GPIO_GPBQSEL1_GPIO44_S 24 +#define GPIO_GPBQSEL1_GPIO44_M 0x3000000 // Select input qualification type + // for GPIO44 +#define GPIO_GPBQSEL1_GPIO45_S 26 +#define GPIO_GPBQSEL1_GPIO45_M 0xC000000 // Select input qualification type + // for GPIO45 +#define GPIO_GPBQSEL1_GPIO46_S 28 +#define GPIO_GPBQSEL1_GPIO46_M 0x30000000 // Select input qualification type + // for GPIO46 +#define GPIO_GPBQSEL1_GPIO47_S 30 +#define GPIO_GPBQSEL1_GPIO47_M 0xC0000000 // Select input qualification type + // for GPIO47 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBQSEL2 register +// +//***************************************************************************** +#define GPIO_GPBQSEL2_GPIO48_S 0 +#define GPIO_GPBQSEL2_GPIO48_M 0x3 // Select input qualification type + // for GPIO48 +#define GPIO_GPBQSEL2_GPIO49_S 2 +#define GPIO_GPBQSEL2_GPIO49_M 0xC // Select input qualification type + // for GPIO49 +#define GPIO_GPBQSEL2_GPIO50_S 4 +#define GPIO_GPBQSEL2_GPIO50_M 0x30 // Select input qualification type + // for GPIO50 +#define GPIO_GPBQSEL2_GPIO51_S 6 +#define GPIO_GPBQSEL2_GPIO51_M 0xC0 // Select input qualification type + // for GPIO51 +#define GPIO_GPBQSEL2_GPIO52_S 8 +#define GPIO_GPBQSEL2_GPIO52_M 0x300 // Select input qualification type + // for GPIO52 +#define GPIO_GPBQSEL2_GPIO53_S 10 +#define GPIO_GPBQSEL2_GPIO53_M 0xC00 // Select input qualification type + // for GPIO53 +#define GPIO_GPBQSEL2_GPIO54_S 12 +#define GPIO_GPBQSEL2_GPIO54_M 0x3000 // Select input qualification type + // for GPIO54 +#define GPIO_GPBQSEL2_GPIO55_S 14 +#define GPIO_GPBQSEL2_GPIO55_M 0xC000 // Select input qualification type + // for GPIO55 +#define GPIO_GPBQSEL2_GPIO56_S 16 +#define GPIO_GPBQSEL2_GPIO56_M 0x30000 // Select input qualification type + // for GPIO56 +#define GPIO_GPBQSEL2_GPIO57_S 18 +#define GPIO_GPBQSEL2_GPIO57_M 0xC0000 // Select input qualification type + // for GPIO57 +#define GPIO_GPBQSEL2_GPIO58_S 20 +#define GPIO_GPBQSEL2_GPIO58_M 0x300000 // Select input qualification type + // for GPIO58 +#define GPIO_GPBQSEL2_GPIO59_S 22 +#define GPIO_GPBQSEL2_GPIO59_M 0xC00000 // Select input qualification type + // for GPIO59 +#define GPIO_GPBQSEL2_GPIO60_S 24 +#define GPIO_GPBQSEL2_GPIO60_M 0x3000000 // Select input qualification type + // for GPIO60 +#define GPIO_GPBQSEL2_GPIO61_S 26 +#define GPIO_GPBQSEL2_GPIO61_M 0xC000000 // Select input qualification type + // for GPIO61 +#define GPIO_GPBQSEL2_GPIO62_S 28 +#define GPIO_GPBQSEL2_GPIO62_M 0x30000000 // Select input qualification type + // for GPIO62 +#define GPIO_GPBQSEL2_GPIO63_S 30 +#define GPIO_GPBQSEL2_GPIO63_M 0xC0000000 // Select input qualification type + // for GPIO63 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBMUX1 register +// +//***************************************************************************** +#define GPIO_GPBMUX1_GPIO32_S 0 +#define GPIO_GPBMUX1_GPIO32_M 0x3 // Defines pin-muxing selection + // for GPIO32 +#define GPIO_GPBMUX1_GPIO33_S 2 +#define GPIO_GPBMUX1_GPIO33_M 0xC // Defines pin-muxing selection + // for GPIO33 +#define GPIO_GPBMUX1_GPIO34_S 4 +#define GPIO_GPBMUX1_GPIO34_M 0x30 // Defines pin-muxing selection + // for GPIO34 +#define GPIO_GPBMUX1_GPIO35_S 6 +#define GPIO_GPBMUX1_GPIO35_M 0xC0 // Defines pin-muxing selection + // for GPIO35 +#define GPIO_GPBMUX1_GPIO36_S 8 +#define GPIO_GPBMUX1_GPIO36_M 0x300 // Defines pin-muxing selection + // for GPIO36 +#define GPIO_GPBMUX1_GPIO37_S 10 +#define GPIO_GPBMUX1_GPIO37_M 0xC00 // Defines pin-muxing selection + // for GPIO37 +#define GPIO_GPBMUX1_GPIO38_S 12 +#define GPIO_GPBMUX1_GPIO38_M 0x3000 // Defines pin-muxing selection + // for GPIO38 +#define GPIO_GPBMUX1_GPIO39_S 14 +#define GPIO_GPBMUX1_GPIO39_M 0xC000 // Defines pin-muxing selection + // for GPIO39 +#define GPIO_GPBMUX1_GPIO40_S 16 +#define GPIO_GPBMUX1_GPIO40_M 0x30000 // Defines pin-muxing selection + // for GPIO40 +#define GPIO_GPBMUX1_GPIO41_S 18 +#define GPIO_GPBMUX1_GPIO41_M 0xC0000 // Defines pin-muxing selection + // for GPIO41 +#define GPIO_GPBMUX1_GPIO42_S 20 +#define GPIO_GPBMUX1_GPIO42_M 0x300000 // Defines pin-muxing selection + // for GPIO42 +#define GPIO_GPBMUX1_GPIO43_S 22 +#define GPIO_GPBMUX1_GPIO43_M 0xC00000 // Defines pin-muxing selection + // for GPIO43 +#define GPIO_GPBMUX1_GPIO44_S 24 +#define GPIO_GPBMUX1_GPIO44_M 0x3000000 // Defines pin-muxing selection + // for GPIO44 +#define GPIO_GPBMUX1_GPIO45_S 26 +#define GPIO_GPBMUX1_GPIO45_M 0xC000000 // Defines pin-muxing selection + // for GPIO45 +#define GPIO_GPBMUX1_GPIO46_S 28 +#define GPIO_GPBMUX1_GPIO46_M 0x30000000 // Defines pin-muxing selection + // for GPIO46 +#define GPIO_GPBMUX1_GPIO47_S 30 +#define GPIO_GPBMUX1_GPIO47_M 0xC0000000 // Defines pin-muxing selection + // for GPIO47 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBMUX2 register +// +//***************************************************************************** +#define GPIO_GPBMUX2_GPIO48_S 0 +#define GPIO_GPBMUX2_GPIO48_M 0x3 // Defines pin-muxing selection + // for GPIO48 +#define GPIO_GPBMUX2_GPIO49_S 2 +#define GPIO_GPBMUX2_GPIO49_M 0xC // Defines pin-muxing selection + // for GPIO49 +#define GPIO_GPBMUX2_GPIO50_S 4 +#define GPIO_GPBMUX2_GPIO50_M 0x30 // Defines pin-muxing selection + // for GPIO50 +#define GPIO_GPBMUX2_GPIO51_S 6 +#define GPIO_GPBMUX2_GPIO51_M 0xC0 // Defines pin-muxing selection + // for GPIO51 +#define GPIO_GPBMUX2_GPIO52_S 8 +#define GPIO_GPBMUX2_GPIO52_M 0x300 // Defines pin-muxing selection + // for GPIO52 +#define GPIO_GPBMUX2_GPIO53_S 10 +#define GPIO_GPBMUX2_GPIO53_M 0xC00 // Defines pin-muxing selection + // for GPIO53 +#define GPIO_GPBMUX2_GPIO54_S 12 +#define GPIO_GPBMUX2_GPIO54_M 0x3000 // Defines pin-muxing selection + // for GPIO54 +#define GPIO_GPBMUX2_GPIO55_S 14 +#define GPIO_GPBMUX2_GPIO55_M 0xC000 // Defines pin-muxing selection + // for GPIO55 +#define GPIO_GPBMUX2_GPIO56_S 16 +#define GPIO_GPBMUX2_GPIO56_M 0x30000 // Defines pin-muxing selection + // for GPIO56 +#define GPIO_GPBMUX2_GPIO57_S 18 +#define GPIO_GPBMUX2_GPIO57_M 0xC0000 // Defines pin-muxing selection + // for GPIO57 +#define GPIO_GPBMUX2_GPIO58_S 20 +#define GPIO_GPBMUX2_GPIO58_M 0x300000 // Defines pin-muxing selection + // for GPIO58 +#define GPIO_GPBMUX2_GPIO59_S 22 +#define GPIO_GPBMUX2_GPIO59_M 0xC00000 // Defines pin-muxing selection + // for GPIO59 +#define GPIO_GPBMUX2_GPIO60_S 24 +#define GPIO_GPBMUX2_GPIO60_M 0x3000000 // Defines pin-muxing selection + // for GPIO60 +#define GPIO_GPBMUX2_GPIO61_S 26 +#define GPIO_GPBMUX2_GPIO61_M 0xC000000 // Defines pin-muxing selection + // for GPIO61 +#define GPIO_GPBMUX2_GPIO62_S 28 +#define GPIO_GPBMUX2_GPIO62_M 0x30000000 // Defines pin-muxing selection + // for GPIO62 +#define GPIO_GPBMUX2_GPIO63_S 30 +#define GPIO_GPBMUX2_GPIO63_M 0xC0000000 // Defines pin-muxing selection + // for GPIO63 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBDIR register +// +//***************************************************************************** +#define GPIO_GPBDIR_GPIO32 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO33 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO34 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO35 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO36 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO37 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO38 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO39 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO40 0x100 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO41 0x200 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO42 0x400 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO43 0x800 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO44 0x1000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO45 0x2000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO46 0x4000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO47 0x8000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO48 0x10000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO49 0x20000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO50 0x40000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO51 0x80000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO52 0x100000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO53 0x200000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO54 0x400000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO55 0x800000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO56 0x1000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO57 0x2000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO58 0x4000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO59 0x8000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO60 0x10000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO61 0x20000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO62 0x40000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPBDIR_GPIO63 0x80000000 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBPUD register +// +//***************************************************************************** +#define GPIO_GPBPUD_GPIO32 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO33 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO34 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO35 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO36 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO37 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO38 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO39 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO40 0x100 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO41 0x200 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO42 0x400 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO43 0x800 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO44 0x1000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO45 0x2000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO46 0x4000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO47 0x8000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO48 0x10000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO49 0x20000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO50 0x40000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO51 0x80000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO52 0x100000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO53 0x200000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO54 0x400000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO55 0x800000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO56 0x1000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO57 0x2000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO58 0x4000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO59 0x8000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO60 0x10000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO61 0x20000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO62 0x40000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPBPUD_GPIO63 0x80000000 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBINV register +// +//***************************************************************************** +#define GPIO_GPBINV_GPIO32 0x1 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO33 0x2 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO34 0x4 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO35 0x8 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO36 0x10 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO37 0x20 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO38 0x40 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO39 0x80 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO40 0x100 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO41 0x200 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO42 0x400 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO43 0x800 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO44 0x1000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO45 0x2000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO46 0x4000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO47 0x8000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO48 0x10000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO49 0x20000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO50 0x40000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO51 0x80000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO52 0x100000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO53 0x200000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO54 0x400000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO55 0x800000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO56 0x1000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO57 0x2000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO58 0x4000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO59 0x8000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO60 0x10000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO61 0x20000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO62 0x40000000 // Input inversion control for + // this pin +#define GPIO_GPBINV_GPIO63 0x80000000 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBODR register +// +//***************************************************************************** +#define GPIO_GPBODR_GPIO32 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO33 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO34 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO35 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO36 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO37 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO38 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO39 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO40 0x100 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO41 0x200 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO42 0x400 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO43 0x800 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO44 0x1000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO45 0x2000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO46 0x4000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO47 0x8000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO48 0x10000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO49 0x20000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO50 0x40000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO51 0x80000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO52 0x100000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO53 0x200000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO54 0x400000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO55 0x800000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO56 0x1000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO57 0x2000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO58 0x4000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO59 0x8000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO60 0x10000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO61 0x20000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO62 0x40000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPBODR_GPIO63 0x80000000 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBAMSEL register +// +//***************************************************************************** +#define GPIO_GPBAMSEL_GPIO42 0x400 // Analog Mode select for this pin +#define GPIO_GPBAMSEL_GPIO43 0x800 // Analog Mode select for this pin +#define GPIO_GPBAMSEL_GPIO46 0x4000 // Analog Mode select for this pin +#define GPIO_GPBAMSEL_GPIO47 0x8000 // Analog Mode select for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBGMUX1 register +// +//***************************************************************************** +#define GPIO_GPBGMUX1_GPIO32_S 0 +#define GPIO_GPBGMUX1_GPIO32_M 0x3 // Defines pin-muxing selection + // for GPIO32 +#define GPIO_GPBGMUX1_GPIO33_S 2 +#define GPIO_GPBGMUX1_GPIO33_M 0xC // Defines pin-muxing selection + // for GPIO33 +#define GPIO_GPBGMUX1_GPIO34_S 4 +#define GPIO_GPBGMUX1_GPIO34_M 0x30 // Defines pin-muxing selection + // for GPIO34 +#define GPIO_GPBGMUX1_GPIO35_S 6 +#define GPIO_GPBGMUX1_GPIO35_M 0xC0 // Defines pin-muxing selection + // for GPIO35 +#define GPIO_GPBGMUX1_GPIO36_S 8 +#define GPIO_GPBGMUX1_GPIO36_M 0x300 // Defines pin-muxing selection + // for GPIO36 +#define GPIO_GPBGMUX1_GPIO37_S 10 +#define GPIO_GPBGMUX1_GPIO37_M 0xC00 // Defines pin-muxing selection + // for GPIO37 +#define GPIO_GPBGMUX1_GPIO38_S 12 +#define GPIO_GPBGMUX1_GPIO38_M 0x3000 // Defines pin-muxing selection + // for GPIO38 +#define GPIO_GPBGMUX1_GPIO39_S 14 +#define GPIO_GPBGMUX1_GPIO39_M 0xC000 // Defines pin-muxing selection + // for GPIO39 +#define GPIO_GPBGMUX1_GPIO40_S 16 +#define GPIO_GPBGMUX1_GPIO40_M 0x30000 // Defines pin-muxing selection + // for GPIO40 +#define GPIO_GPBGMUX1_GPIO41_S 18 +#define GPIO_GPBGMUX1_GPIO41_M 0xC0000 // Defines pin-muxing selection + // for GPIO41 +#define GPIO_GPBGMUX1_GPIO42_S 20 +#define GPIO_GPBGMUX1_GPIO42_M 0x300000 // Defines pin-muxing selection + // for GPIO42 +#define GPIO_GPBGMUX1_GPIO43_S 22 +#define GPIO_GPBGMUX1_GPIO43_M 0xC00000 // Defines pin-muxing selection + // for GPIO43 +#define GPIO_GPBGMUX1_GPIO44_S 24 +#define GPIO_GPBGMUX1_GPIO44_M 0x3000000 // Defines pin-muxing selection + // for GPIO44 +#define GPIO_GPBGMUX1_GPIO45_S 26 +#define GPIO_GPBGMUX1_GPIO45_M 0xC000000 // Defines pin-muxing selection + // for GPIO45 +#define GPIO_GPBGMUX1_GPIO46_S 28 +#define GPIO_GPBGMUX1_GPIO46_M 0x30000000 // Defines pin-muxing selection + // for GPIO46 +#define GPIO_GPBGMUX1_GPIO47_S 30 +#define GPIO_GPBGMUX1_GPIO47_M 0xC0000000 // Defines pin-muxing selection + // for GPIO47 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBGMUX2 register +// +//***************************************************************************** +#define GPIO_GPBGMUX2_GPIO48_S 0 +#define GPIO_GPBGMUX2_GPIO48_M 0x3 // Defines pin-muxing selection + // for GPIO48 +#define GPIO_GPBGMUX2_GPIO49_S 2 +#define GPIO_GPBGMUX2_GPIO49_M 0xC // Defines pin-muxing selection + // for GPIO49 +#define GPIO_GPBGMUX2_GPIO50_S 4 +#define GPIO_GPBGMUX2_GPIO50_M 0x30 // Defines pin-muxing selection + // for GPIO50 +#define GPIO_GPBGMUX2_GPIO51_S 6 +#define GPIO_GPBGMUX2_GPIO51_M 0xC0 // Defines pin-muxing selection + // for GPIO51 +#define GPIO_GPBGMUX2_GPIO52_S 8 +#define GPIO_GPBGMUX2_GPIO52_M 0x300 // Defines pin-muxing selection + // for GPIO52 +#define GPIO_GPBGMUX2_GPIO53_S 10 +#define GPIO_GPBGMUX2_GPIO53_M 0xC00 // Defines pin-muxing selection + // for GPIO53 +#define GPIO_GPBGMUX2_GPIO54_S 12 +#define GPIO_GPBGMUX2_GPIO54_M 0x3000 // Defines pin-muxing selection + // for GPIO54 +#define GPIO_GPBGMUX2_GPIO55_S 14 +#define GPIO_GPBGMUX2_GPIO55_M 0xC000 // Defines pin-muxing selection + // for GPIO55 +#define GPIO_GPBGMUX2_GPIO56_S 16 +#define GPIO_GPBGMUX2_GPIO56_M 0x30000 // Defines pin-muxing selection + // for GPIO56 +#define GPIO_GPBGMUX2_GPIO57_S 18 +#define GPIO_GPBGMUX2_GPIO57_M 0xC0000 // Defines pin-muxing selection + // for GPIO57 +#define GPIO_GPBGMUX2_GPIO58_S 20 +#define GPIO_GPBGMUX2_GPIO58_M 0x300000 // Defines pin-muxing selection + // for GPIO58 +#define GPIO_GPBGMUX2_GPIO59_S 22 +#define GPIO_GPBGMUX2_GPIO59_M 0xC00000 // Defines pin-muxing selection + // for GPIO59 +#define GPIO_GPBGMUX2_GPIO60_S 24 +#define GPIO_GPBGMUX2_GPIO60_M 0x3000000 // Defines pin-muxing selection + // for GPIO60 +#define GPIO_GPBGMUX2_GPIO61_S 26 +#define GPIO_GPBGMUX2_GPIO61_M 0xC000000 // Defines pin-muxing selection + // for GPIO61 +#define GPIO_GPBGMUX2_GPIO62_S 28 +#define GPIO_GPBGMUX2_GPIO62_M 0x30000000 // Defines pin-muxing selection + // for GPIO62 +#define GPIO_GPBGMUX2_GPIO63_S 30 +#define GPIO_GPBGMUX2_GPIO63_M 0xC0000000 // Defines pin-muxing selection + // for GPIO63 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCSEL1 register +// +//***************************************************************************** +#define GPIO_GPBCSEL1_GPIO32_S 0 +#define GPIO_GPBCSEL1_GPIO32_M 0xF // GPIO32 Master CPU Select +#define GPIO_GPBCSEL1_GPIO33_S 4 +#define GPIO_GPBCSEL1_GPIO33_M 0xF0 // GPIO33 Master CPU Select +#define GPIO_GPBCSEL1_GPIO34_S 8 +#define GPIO_GPBCSEL1_GPIO34_M 0xF00 // GPIO34 Master CPU Select +#define GPIO_GPBCSEL1_GPIO35_S 12 +#define GPIO_GPBCSEL1_GPIO35_M 0xF000 // GPIO35 Master CPU Select +#define GPIO_GPBCSEL1_GPIO36_S 16 +#define GPIO_GPBCSEL1_GPIO36_M 0xF0000 // GPIO36 Master CPU Select +#define GPIO_GPBCSEL1_GPIO37_S 20 +#define GPIO_GPBCSEL1_GPIO37_M 0xF00000 // GPIO37 Master CPU Select +#define GPIO_GPBCSEL1_GPIO38_S 24 +#define GPIO_GPBCSEL1_GPIO38_M 0xF000000 // GPIO38 Master CPU Select +#define GPIO_GPBCSEL1_GPIO39_S 28 +#define GPIO_GPBCSEL1_GPIO39_M 0xF0000000 // GPIO39 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCSEL2 register +// +//***************************************************************************** +#define GPIO_GPBCSEL2_GPIO40_S 0 +#define GPIO_GPBCSEL2_GPIO40_M 0xF // GPIO40 Master CPU Select +#define GPIO_GPBCSEL2_GPIO41_S 4 +#define GPIO_GPBCSEL2_GPIO41_M 0xF0 // GPIO41 Master CPU Select +#define GPIO_GPBCSEL2_GPIO42_S 8 +#define GPIO_GPBCSEL2_GPIO42_M 0xF00 // GPIO42 Master CPU Select +#define GPIO_GPBCSEL2_GPIO43_S 12 +#define GPIO_GPBCSEL2_GPIO43_M 0xF000 // GPIO43 Master CPU Select +#define GPIO_GPBCSEL2_GPIO44_S 16 +#define GPIO_GPBCSEL2_GPIO44_M 0xF0000 // GPIO44 Master CPU Select +#define GPIO_GPBCSEL2_GPIO45_S 20 +#define GPIO_GPBCSEL2_GPIO45_M 0xF00000 // GPIO45 Master CPU Select +#define GPIO_GPBCSEL2_GPIO46_S 24 +#define GPIO_GPBCSEL2_GPIO46_M 0xF000000 // GPIO46 Master CPU Select +#define GPIO_GPBCSEL2_GPIO47_S 28 +#define GPIO_GPBCSEL2_GPIO47_M 0xF0000000 // GPIO47 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCSEL3 register +// +//***************************************************************************** +#define GPIO_GPBCSEL3_GPIO48_S 0 +#define GPIO_GPBCSEL3_GPIO48_M 0xF // GPIO48 Master CPU Select +#define GPIO_GPBCSEL3_GPIO49_S 4 +#define GPIO_GPBCSEL3_GPIO49_M 0xF0 // GPIO49 Master CPU Select +#define GPIO_GPBCSEL3_GPIO50_S 8 +#define GPIO_GPBCSEL3_GPIO50_M 0xF00 // GPIO50 Master CPU Select +#define GPIO_GPBCSEL3_GPIO51_S 12 +#define GPIO_GPBCSEL3_GPIO51_M 0xF000 // GPIO51 Master CPU Select +#define GPIO_GPBCSEL3_GPIO52_S 16 +#define GPIO_GPBCSEL3_GPIO52_M 0xF0000 // GPIO52 Master CPU Select +#define GPIO_GPBCSEL3_GPIO53_S 20 +#define GPIO_GPBCSEL3_GPIO53_M 0xF00000 // GPIO53 Master CPU Select +#define GPIO_GPBCSEL3_GPIO54_S 24 +#define GPIO_GPBCSEL3_GPIO54_M 0xF000000 // GPIO54 Master CPU Select +#define GPIO_GPBCSEL3_GPIO55_S 28 +#define GPIO_GPBCSEL3_GPIO55_M 0xF0000000 // GPIO55 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCSEL4 register +// +//***************************************************************************** +#define GPIO_GPBCSEL4_GPIO56_S 0 +#define GPIO_GPBCSEL4_GPIO56_M 0xF // GPIO56 Master CPU Select +#define GPIO_GPBCSEL4_GPIO57_S 4 +#define GPIO_GPBCSEL4_GPIO57_M 0xF0 // GPIO57 Master CPU Select +#define GPIO_GPBCSEL4_GPIO58_S 8 +#define GPIO_GPBCSEL4_GPIO58_M 0xF00 // GPIO58 Master CPU Select +#define GPIO_GPBCSEL4_GPIO59_S 12 +#define GPIO_GPBCSEL4_GPIO59_M 0xF000 // GPIO59 Master CPU Select +#define GPIO_GPBCSEL4_GPIO60_S 16 +#define GPIO_GPBCSEL4_GPIO60_M 0xF0000 // GPIO60 Master CPU Select +#define GPIO_GPBCSEL4_GPIO61_S 20 +#define GPIO_GPBCSEL4_GPIO61_M 0xF00000 // GPIO61 Master CPU Select +#define GPIO_GPBCSEL4_GPIO62_S 24 +#define GPIO_GPBCSEL4_GPIO62_M 0xF000000 // GPIO62 Master CPU Select +#define GPIO_GPBCSEL4_GPIO63_S 28 +#define GPIO_GPBCSEL4_GPIO63_M 0xF0000000 // GPIO63 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBLOCK register +// +//***************************************************************************** +#define GPIO_GPBLOCK_GPIO32 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO33 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO34 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO35 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO36 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO37 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO38 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO39 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO40 0x100 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO41 0x200 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO42 0x400 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO43 0x800 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO44 0x1000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO45 0x2000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO46 0x4000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO47 0x8000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO48 0x10000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO49 0x20000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO50 0x40000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO51 0x80000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO52 0x100000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO53 0x200000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO54 0x400000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO55 0x800000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO56 0x1000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO57 0x2000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO58 0x4000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO59 0x8000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO60 0x10000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO61 0x20000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO62 0x40000000 // Configuration Lock bit for this + // pin +#define GPIO_GPBLOCK_GPIO63 0x80000000 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCR register +// +//***************************************************************************** +#define GPIO_GPBCR_GPIO32 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO33 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO34 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO35 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO36 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO37 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO38 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO39 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO40 0x100 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO41 0x200 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO42 0x400 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO43 0x800 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO44 0x1000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO45 0x2000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO46 0x4000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO47 0x8000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO48 0x10000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO49 0x20000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO50 0x40000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO51 0x80000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO52 0x100000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO53 0x200000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO54 0x400000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO55 0x800000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO56 0x1000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO57 0x2000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO58 0x4000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO59 0x8000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO60 0x10000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO61 0x20000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO62 0x40000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPBCR_GPIO63 0x80000000 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCTRL register +// +//***************************************************************************** +#define GPIO_GPCCTRL_QUALPRD0_S 0 +#define GPIO_GPCCTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO64 to GPIO71 +#define GPIO_GPCCTRL_QUALPRD1_S 8 +#define GPIO_GPCCTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO72 to GPIO79 +#define GPIO_GPCCTRL_QUALPRD2_S 16 +#define GPIO_GPCCTRL_QUALPRD2_M 0xFF0000 // Qualification sampling period + // for GPIO80 to GPIO87 +#define GPIO_GPCCTRL_QUALPRD3_S 24 +#define GPIO_GPCCTRL_QUALPRD3_M 0xFF000000 // Qualification sampling period + // for GPIO88 to GPIO95 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCQSEL1 register +// +//***************************************************************************** +#define GPIO_GPCQSEL1_GPIO64_S 0 +#define GPIO_GPCQSEL1_GPIO64_M 0x3 // Select input qualification type + // for GPIO64 +#define GPIO_GPCQSEL1_GPIO65_S 2 +#define GPIO_GPCQSEL1_GPIO65_M 0xC // Select input qualification type + // for GPIO65 +#define GPIO_GPCQSEL1_GPIO66_S 4 +#define GPIO_GPCQSEL1_GPIO66_M 0x30 // Select input qualification type + // for GPIO66 +#define GPIO_GPCQSEL1_GPIO67_S 6 +#define GPIO_GPCQSEL1_GPIO67_M 0xC0 // Select input qualification type + // for GPIO67 +#define GPIO_GPCQSEL1_GPIO68_S 8 +#define GPIO_GPCQSEL1_GPIO68_M 0x300 // Select input qualification type + // for GPIO68 +#define GPIO_GPCQSEL1_GPIO69_S 10 +#define GPIO_GPCQSEL1_GPIO69_M 0xC00 // Select input qualification type + // for GPIO69 +#define GPIO_GPCQSEL1_GPIO70_S 12 +#define GPIO_GPCQSEL1_GPIO70_M 0x3000 // Select input qualification type + // for GPIO70 +#define GPIO_GPCQSEL1_GPIO71_S 14 +#define GPIO_GPCQSEL1_GPIO71_M 0xC000 // Select input qualification type + // for GPIO71 +#define GPIO_GPCQSEL1_GPIO72_S 16 +#define GPIO_GPCQSEL1_GPIO72_M 0x30000 // Select input qualification type + // for GPIO72 +#define GPIO_GPCQSEL1_GPIO73_S 18 +#define GPIO_GPCQSEL1_GPIO73_M 0xC0000 // Select input qualification type + // for GPIO73 +#define GPIO_GPCQSEL1_GPIO74_S 20 +#define GPIO_GPCQSEL1_GPIO74_M 0x300000 // Select input qualification type + // for GPIO74 +#define GPIO_GPCQSEL1_GPIO75_S 22 +#define GPIO_GPCQSEL1_GPIO75_M 0xC00000 // Select input qualification type + // for GPIO75 +#define GPIO_GPCQSEL1_GPIO76_S 24 +#define GPIO_GPCQSEL1_GPIO76_M 0x3000000 // Select input qualification type + // for GPIO76 +#define GPIO_GPCQSEL1_GPIO77_S 26 +#define GPIO_GPCQSEL1_GPIO77_M 0xC000000 // Select input qualification type + // for GPIO77 +#define GPIO_GPCQSEL1_GPIO78_S 28 +#define GPIO_GPCQSEL1_GPIO78_M 0x30000000 // Select input qualification type + // for GPIO78 +#define GPIO_GPCQSEL1_GPIO79_S 30 +#define GPIO_GPCQSEL1_GPIO79_M 0xC0000000 // Select input qualification type + // for GPIO79 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCQSEL2 register +// +//***************************************************************************** +#define GPIO_GPCQSEL2_GPIO80_S 0 +#define GPIO_GPCQSEL2_GPIO80_M 0x3 // Select input qualification type + // for GPIO80 +#define GPIO_GPCQSEL2_GPIO81_S 2 +#define GPIO_GPCQSEL2_GPIO81_M 0xC // Select input qualification type + // for GPIO81 +#define GPIO_GPCQSEL2_GPIO82_S 4 +#define GPIO_GPCQSEL2_GPIO82_M 0x30 // Select input qualification type + // for GPIO82 +#define GPIO_GPCQSEL2_GPIO83_S 6 +#define GPIO_GPCQSEL2_GPIO83_M 0xC0 // Select input qualification type + // for GPIO83 +#define GPIO_GPCQSEL2_GPIO84_S 8 +#define GPIO_GPCQSEL2_GPIO84_M 0x300 // Select input qualification type + // for GPIO84 +#define GPIO_GPCQSEL2_GPIO85_S 10 +#define GPIO_GPCQSEL2_GPIO85_M 0xC00 // Select input qualification type + // for GPIO85 +#define GPIO_GPCQSEL2_GPIO86_S 12 +#define GPIO_GPCQSEL2_GPIO86_M 0x3000 // Select input qualification type + // for GPIO86 +#define GPIO_GPCQSEL2_GPIO87_S 14 +#define GPIO_GPCQSEL2_GPIO87_M 0xC000 // Select input qualification type + // for GPIO87 +#define GPIO_GPCQSEL2_GPIO88_S 16 +#define GPIO_GPCQSEL2_GPIO88_M 0x30000 // Select input qualification type + // for GPIO88 +#define GPIO_GPCQSEL2_GPIO89_S 18 +#define GPIO_GPCQSEL2_GPIO89_M 0xC0000 // Select input qualification type + // for GPIO89 +#define GPIO_GPCQSEL2_GPIO90_S 20 +#define GPIO_GPCQSEL2_GPIO90_M 0x300000 // Select input qualification type + // for GPIO90 +#define GPIO_GPCQSEL2_GPIO91_S 22 +#define GPIO_GPCQSEL2_GPIO91_M 0xC00000 // Select input qualification type + // for GPIO91 +#define GPIO_GPCQSEL2_GPIO92_S 24 +#define GPIO_GPCQSEL2_GPIO92_M 0x3000000 // Select input qualification type + // for GPIO92 +#define GPIO_GPCQSEL2_GPIO93_S 26 +#define GPIO_GPCQSEL2_GPIO93_M 0xC000000 // Select input qualification type + // for GPIO93 +#define GPIO_GPCQSEL2_GPIO94_S 28 +#define GPIO_GPCQSEL2_GPIO94_M 0x30000000 // Select input qualification type + // for GPIO94 +#define GPIO_GPCQSEL2_GPIO95_S 30 +#define GPIO_GPCQSEL2_GPIO95_M 0xC0000000 // Select input qualification type + // for GPIO95 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCMUX1 register +// +//***************************************************************************** +#define GPIO_GPCMUX1_GPIO64_S 0 +#define GPIO_GPCMUX1_GPIO64_M 0x3 // Defines pin-muxing selection + // for GPIO64 +#define GPIO_GPCMUX1_GPIO65_S 2 +#define GPIO_GPCMUX1_GPIO65_M 0xC // Defines pin-muxing selection + // for GPIO65 +#define GPIO_GPCMUX1_GPIO66_S 4 +#define GPIO_GPCMUX1_GPIO66_M 0x30 // Defines pin-muxing selection + // for GPIO66 +#define GPIO_GPCMUX1_GPIO67_S 6 +#define GPIO_GPCMUX1_GPIO67_M 0xC0 // Defines pin-muxing selection + // for GPIO67 +#define GPIO_GPCMUX1_GPIO68_S 8 +#define GPIO_GPCMUX1_GPIO68_M 0x300 // Defines pin-muxing selection + // for GPIO68 +#define GPIO_GPCMUX1_GPIO69_S 10 +#define GPIO_GPCMUX1_GPIO69_M 0xC00 // Defines pin-muxing selection + // for GPIO69 +#define GPIO_GPCMUX1_GPIO70_S 12 +#define GPIO_GPCMUX1_GPIO70_M 0x3000 // Defines pin-muxing selection + // for GPIO70 +#define GPIO_GPCMUX1_GPIO71_S 14 +#define GPIO_GPCMUX1_GPIO71_M 0xC000 // Defines pin-muxing selection + // for GPIO71 +#define GPIO_GPCMUX1_GPIO72_S 16 +#define GPIO_GPCMUX1_GPIO72_M 0x30000 // Defines pin-muxing selection + // for GPIO72 +#define GPIO_GPCMUX1_GPIO73_S 18 +#define GPIO_GPCMUX1_GPIO73_M 0xC0000 // Defines pin-muxing selection + // for GPIO73 +#define GPIO_GPCMUX1_GPIO74_S 20 +#define GPIO_GPCMUX1_GPIO74_M 0x300000 // Defines pin-muxing selection + // for GPIO74 +#define GPIO_GPCMUX1_GPIO75_S 22 +#define GPIO_GPCMUX1_GPIO75_M 0xC00000 // Defines pin-muxing selection + // for GPIO75 +#define GPIO_GPCMUX1_GPIO76_S 24 +#define GPIO_GPCMUX1_GPIO76_M 0x3000000 // Defines pin-muxing selection + // for GPIO76 +#define GPIO_GPCMUX1_GPIO77_S 26 +#define GPIO_GPCMUX1_GPIO77_M 0xC000000 // Defines pin-muxing selection + // for GPIO77 +#define GPIO_GPCMUX1_GPIO78_S 28 +#define GPIO_GPCMUX1_GPIO78_M 0x30000000 // Defines pin-muxing selection + // for GPIO78 +#define GPIO_GPCMUX1_GPIO79_S 30 +#define GPIO_GPCMUX1_GPIO79_M 0xC0000000 // Defines pin-muxing selection + // for GPIO79 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCMUX2 register +// +//***************************************************************************** +#define GPIO_GPCMUX2_GPIO80_S 0 +#define GPIO_GPCMUX2_GPIO80_M 0x3 // Defines pin-muxing selection + // for GPIO80 +#define GPIO_GPCMUX2_GPIO81_S 2 +#define GPIO_GPCMUX2_GPIO81_M 0xC // Defines pin-muxing selection + // for GPIO81 +#define GPIO_GPCMUX2_GPIO82_S 4 +#define GPIO_GPCMUX2_GPIO82_M 0x30 // Defines pin-muxing selection + // for GPIO82 +#define GPIO_GPCMUX2_GPIO83_S 6 +#define GPIO_GPCMUX2_GPIO83_M 0xC0 // Defines pin-muxing selection + // for GPIO83 +#define GPIO_GPCMUX2_GPIO84_S 8 +#define GPIO_GPCMUX2_GPIO84_M 0x300 // Defines pin-muxing selection + // for GPIO84 +#define GPIO_GPCMUX2_GPIO85_S 10 +#define GPIO_GPCMUX2_GPIO85_M 0xC00 // Defines pin-muxing selection + // for GPIO85 +#define GPIO_GPCMUX2_GPIO86_S 12 +#define GPIO_GPCMUX2_GPIO86_M 0x3000 // Defines pin-muxing selection + // for GPIO86 +#define GPIO_GPCMUX2_GPIO87_S 14 +#define GPIO_GPCMUX2_GPIO87_M 0xC000 // Defines pin-muxing selection + // for GPIO87 +#define GPIO_GPCMUX2_GPIO88_S 16 +#define GPIO_GPCMUX2_GPIO88_M 0x30000 // Defines pin-muxing selection + // for GPIO88 +#define GPIO_GPCMUX2_GPIO89_S 18 +#define GPIO_GPCMUX2_GPIO89_M 0xC0000 // Defines pin-muxing selection + // for GPIO89 +#define GPIO_GPCMUX2_GPIO90_S 20 +#define GPIO_GPCMUX2_GPIO90_M 0x300000 // Defines pin-muxing selection + // for GPIO90 +#define GPIO_GPCMUX2_GPIO91_S 22 +#define GPIO_GPCMUX2_GPIO91_M 0xC00000 // Defines pin-muxing selection + // for GPIO91 +#define GPIO_GPCMUX2_GPIO92_S 24 +#define GPIO_GPCMUX2_GPIO92_M 0x3000000 // Defines pin-muxing selection + // for GPIO92 +#define GPIO_GPCMUX2_GPIO93_S 26 +#define GPIO_GPCMUX2_GPIO93_M 0xC000000 // Defines pin-muxing selection + // for GPIO93 +#define GPIO_GPCMUX2_GPIO94_S 28 +#define GPIO_GPCMUX2_GPIO94_M 0x30000000 // Defines pin-muxing selection + // for GPIO94 +#define GPIO_GPCMUX2_GPIO95_S 30 +#define GPIO_GPCMUX2_GPIO95_M 0xC0000000 // Defines pin-muxing selection + // for GPIO95 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCDIR register +// +//***************************************************************************** +#define GPIO_GPCDIR_GPIO64 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO65 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO66 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO67 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO68 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO69 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO70 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO71 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO72 0x100 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO73 0x200 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO74 0x400 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO75 0x800 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO76 0x1000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO77 0x2000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO78 0x4000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO79 0x8000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO80 0x10000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO81 0x20000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO82 0x40000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO83 0x80000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO84 0x100000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO85 0x200000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO86 0x400000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO87 0x800000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO88 0x1000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO89 0x2000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO90 0x4000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO91 0x8000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO92 0x10000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO93 0x20000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO94 0x40000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPCDIR_GPIO95 0x80000000 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCPUD register +// +//***************************************************************************** +#define GPIO_GPCPUD_GPIO64 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO65 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO66 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO67 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO68 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO69 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO70 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO71 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO72 0x100 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO73 0x200 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO74 0x400 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO75 0x800 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO76 0x1000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO77 0x2000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO78 0x4000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO79 0x8000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO80 0x10000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO81 0x20000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO82 0x40000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO83 0x80000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO84 0x100000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO85 0x200000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO86 0x400000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO87 0x800000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO88 0x1000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO89 0x2000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO90 0x4000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO91 0x8000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO92 0x10000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO93 0x20000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO94 0x40000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPCPUD_GPIO95 0x80000000 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCINV register +// +//***************************************************************************** +#define GPIO_GPCINV_GPIO64 0x1 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO65 0x2 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO66 0x4 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO67 0x8 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO68 0x10 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO69 0x20 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO70 0x40 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO71 0x80 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO72 0x100 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO73 0x200 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO74 0x400 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO75 0x800 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO76 0x1000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO77 0x2000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO78 0x4000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO79 0x8000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO80 0x10000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO81 0x20000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO82 0x40000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO83 0x80000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO84 0x100000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO85 0x200000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO86 0x400000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO87 0x800000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO88 0x1000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO89 0x2000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO90 0x4000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO91 0x8000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO92 0x10000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO93 0x20000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO94 0x40000000 // Input inversion control for + // this pin +#define GPIO_GPCINV_GPIO95 0x80000000 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCODR register +// +//***************************************************************************** +#define GPIO_GPCODR_GPIO64 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO65 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO66 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO67 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO68 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO69 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO70 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO71 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO72 0x100 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO73 0x200 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO74 0x400 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO75 0x800 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO76 0x1000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO77 0x2000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO78 0x4000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO79 0x8000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO80 0x10000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO81 0x20000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO82 0x40000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO83 0x80000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO84 0x100000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO85 0x200000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO86 0x400000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO87 0x800000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO88 0x1000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO89 0x2000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO90 0x4000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO91 0x8000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO92 0x10000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO93 0x20000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO94 0x40000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPCODR_GPIO95 0x80000000 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCGMUX1 register +// +//***************************************************************************** +#define GPIO_GPCGMUX1_GPIO64_S 0 +#define GPIO_GPCGMUX1_GPIO64_M 0x3 // Defines pin-muxing selection + // for GPIO64 +#define GPIO_GPCGMUX1_GPIO65_S 2 +#define GPIO_GPCGMUX1_GPIO65_M 0xC // Defines pin-muxing selection + // for GPIO65 +#define GPIO_GPCGMUX1_GPIO66_S 4 +#define GPIO_GPCGMUX1_GPIO66_M 0x30 // Defines pin-muxing selection + // for GPIO66 +#define GPIO_GPCGMUX1_GPIO67_S 6 +#define GPIO_GPCGMUX1_GPIO67_M 0xC0 // Defines pin-muxing selection + // for GPIO67 +#define GPIO_GPCGMUX1_GPIO68_S 8 +#define GPIO_GPCGMUX1_GPIO68_M 0x300 // Defines pin-muxing selection + // for GPIO68 +#define GPIO_GPCGMUX1_GPIO69_S 10 +#define GPIO_GPCGMUX1_GPIO69_M 0xC00 // Defines pin-muxing selection + // for GPIO69 +#define GPIO_GPCGMUX1_GPIO70_S 12 +#define GPIO_GPCGMUX1_GPIO70_M 0x3000 // Defines pin-muxing selection + // for GPIO70 +#define GPIO_GPCGMUX1_GPIO71_S 14 +#define GPIO_GPCGMUX1_GPIO71_M 0xC000 // Defines pin-muxing selection + // for GPIO71 +#define GPIO_GPCGMUX1_GPIO72_S 16 +#define GPIO_GPCGMUX1_GPIO72_M 0x30000 // Defines pin-muxing selection + // for GPIO72 +#define GPIO_GPCGMUX1_GPIO73_S 18 +#define GPIO_GPCGMUX1_GPIO73_M 0xC0000 // Defines pin-muxing selection + // for GPIO73 +#define GPIO_GPCGMUX1_GPIO74_S 20 +#define GPIO_GPCGMUX1_GPIO74_M 0x300000 // Defines pin-muxing selection + // for GPIO74 +#define GPIO_GPCGMUX1_GPIO75_S 22 +#define GPIO_GPCGMUX1_GPIO75_M 0xC00000 // Defines pin-muxing selection + // for GPIO75 +#define GPIO_GPCGMUX1_GPIO76_S 24 +#define GPIO_GPCGMUX1_GPIO76_M 0x3000000 // Defines pin-muxing selection + // for GPIO76 +#define GPIO_GPCGMUX1_GPIO77_S 26 +#define GPIO_GPCGMUX1_GPIO77_M 0xC000000 // Defines pin-muxing selection + // for GPIO77 +#define GPIO_GPCGMUX1_GPIO78_S 28 +#define GPIO_GPCGMUX1_GPIO78_M 0x30000000 // Defines pin-muxing selection + // for GPIO78 +#define GPIO_GPCGMUX1_GPIO79_S 30 +#define GPIO_GPCGMUX1_GPIO79_M 0xC0000000 // Defines pin-muxing selection + // for GPIO79 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCGMUX2 register +// +//***************************************************************************** +#define GPIO_GPCGMUX2_GPIO80_S 0 +#define GPIO_GPCGMUX2_GPIO80_M 0x3 // Defines pin-muxing selection + // for GPIO80 +#define GPIO_GPCGMUX2_GPIO81_S 2 +#define GPIO_GPCGMUX2_GPIO81_M 0xC // Defines pin-muxing selection + // for GPIO81 +#define GPIO_GPCGMUX2_GPIO82_S 4 +#define GPIO_GPCGMUX2_GPIO82_M 0x30 // Defines pin-muxing selection + // for GPIO82 +#define GPIO_GPCGMUX2_GPIO83_S 6 +#define GPIO_GPCGMUX2_GPIO83_M 0xC0 // Defines pin-muxing selection + // for GPIO83 +#define GPIO_GPCGMUX2_GPIO84_S 8 +#define GPIO_GPCGMUX2_GPIO84_M 0x300 // Defines pin-muxing selection + // for GPIO84 +#define GPIO_GPCGMUX2_GPIO85_S 10 +#define GPIO_GPCGMUX2_GPIO85_M 0xC00 // Defines pin-muxing selection + // for GPIO85 +#define GPIO_GPCGMUX2_GPIO86_S 12 +#define GPIO_GPCGMUX2_GPIO86_M 0x3000 // Defines pin-muxing selection + // for GPIO86 +#define GPIO_GPCGMUX2_GPIO87_S 14 +#define GPIO_GPCGMUX2_GPIO87_M 0xC000 // Defines pin-muxing selection + // for GPIO87 +#define GPIO_GPCGMUX2_GPIO88_S 16 +#define GPIO_GPCGMUX2_GPIO88_M 0x30000 // Defines pin-muxing selection + // for GPIO88 +#define GPIO_GPCGMUX2_GPIO89_S 18 +#define GPIO_GPCGMUX2_GPIO89_M 0xC0000 // Defines pin-muxing selection + // for GPIO89 +#define GPIO_GPCGMUX2_GPIO90_S 20 +#define GPIO_GPCGMUX2_GPIO90_M 0x300000 // Defines pin-muxing selection + // for GPIO90 +#define GPIO_GPCGMUX2_GPIO91_S 22 +#define GPIO_GPCGMUX2_GPIO91_M 0xC00000 // Defines pin-muxing selection + // for GPIO91 +#define GPIO_GPCGMUX2_GPIO92_S 24 +#define GPIO_GPCGMUX2_GPIO92_M 0x3000000 // Defines pin-muxing selection + // for GPIO92 +#define GPIO_GPCGMUX2_GPIO93_S 26 +#define GPIO_GPCGMUX2_GPIO93_M 0xC000000 // Defines pin-muxing selection + // for GPIO93 +#define GPIO_GPCGMUX2_GPIO94_S 28 +#define GPIO_GPCGMUX2_GPIO94_M 0x30000000 // Defines pin-muxing selection + // for GPIO94 +#define GPIO_GPCGMUX2_GPIO95_S 30 +#define GPIO_GPCGMUX2_GPIO95_M 0xC0000000 // Defines pin-muxing selection + // for GPIO95 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCSEL1 register +// +//***************************************************************************** +#define GPIO_GPCCSEL1_GPIO64_S 0 +#define GPIO_GPCCSEL1_GPIO64_M 0xF // GPIO64 Master CPU Select +#define GPIO_GPCCSEL1_GPIO65_S 4 +#define GPIO_GPCCSEL1_GPIO65_M 0xF0 // GPIO65 Master CPU Select +#define GPIO_GPCCSEL1_GPIO66_S 8 +#define GPIO_GPCCSEL1_GPIO66_M 0xF00 // GPIO66 Master CPU Select +#define GPIO_GPCCSEL1_GPIO67_S 12 +#define GPIO_GPCCSEL1_GPIO67_M 0xF000 // GPIO67 Master CPU Select +#define GPIO_GPCCSEL1_GPIO68_S 16 +#define GPIO_GPCCSEL1_GPIO68_M 0xF0000 // GPIO68 Master CPU Select +#define GPIO_GPCCSEL1_GPIO69_S 20 +#define GPIO_GPCCSEL1_GPIO69_M 0xF00000 // GPIO69 Master CPU Select +#define GPIO_GPCCSEL1_GPIO70_S 24 +#define GPIO_GPCCSEL1_GPIO70_M 0xF000000 // GPIO70 Master CPU Select +#define GPIO_GPCCSEL1_GPIO71_S 28 +#define GPIO_GPCCSEL1_GPIO71_M 0xF0000000 // GPIO71 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCSEL2 register +// +//***************************************************************************** +#define GPIO_GPCCSEL2_GPIO72_S 0 +#define GPIO_GPCCSEL2_GPIO72_M 0xF // GPIO72 Master CPU Select +#define GPIO_GPCCSEL2_GPIO73_S 4 +#define GPIO_GPCCSEL2_GPIO73_M 0xF0 // GPIO73 Master CPU Select +#define GPIO_GPCCSEL2_GPIO74_S 8 +#define GPIO_GPCCSEL2_GPIO74_M 0xF00 // GPIO74 Master CPU Select +#define GPIO_GPCCSEL2_GPIO75_S 12 +#define GPIO_GPCCSEL2_GPIO75_M 0xF000 // GPIO75 Master CPU Select +#define GPIO_GPCCSEL2_GPIO76_S 16 +#define GPIO_GPCCSEL2_GPIO76_M 0xF0000 // GPIO76 Master CPU Select +#define GPIO_GPCCSEL2_GPIO77_S 20 +#define GPIO_GPCCSEL2_GPIO77_M 0xF00000 // GPIO77 Master CPU Select +#define GPIO_GPCCSEL2_GPIO78_S 24 +#define GPIO_GPCCSEL2_GPIO78_M 0xF000000 // GPIO78 Master CPU Select +#define GPIO_GPCCSEL2_GPIO79_S 28 +#define GPIO_GPCCSEL2_GPIO79_M 0xF0000000 // GPIO79 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCSEL3 register +// +//***************************************************************************** +#define GPIO_GPCCSEL3_GPIO80_S 0 +#define GPIO_GPCCSEL3_GPIO80_M 0xF // GPIO80 Master CPU Select +#define GPIO_GPCCSEL3_GPIO81_S 4 +#define GPIO_GPCCSEL3_GPIO81_M 0xF0 // GPIO81 Master CPU Select +#define GPIO_GPCCSEL3_GPIO82_S 8 +#define GPIO_GPCCSEL3_GPIO82_M 0xF00 // GPIO82 Master CPU Select +#define GPIO_GPCCSEL3_GPIO83_S 12 +#define GPIO_GPCCSEL3_GPIO83_M 0xF000 // GPIO83 Master CPU Select +#define GPIO_GPCCSEL3_GPIO84_S 16 +#define GPIO_GPCCSEL3_GPIO84_M 0xF0000 // GPIO84 Master CPU Select +#define GPIO_GPCCSEL3_GPIO85_S 20 +#define GPIO_GPCCSEL3_GPIO85_M 0xF00000 // GPIO85 Master CPU Select +#define GPIO_GPCCSEL3_GPIO86_S 24 +#define GPIO_GPCCSEL3_GPIO86_M 0xF000000 // GPIO86 Master CPU Select +#define GPIO_GPCCSEL3_GPIO87_S 28 +#define GPIO_GPCCSEL3_GPIO87_M 0xF0000000 // GPIO87 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCSEL4 register +// +//***************************************************************************** +#define GPIO_GPCCSEL4_GPIO88_S 0 +#define GPIO_GPCCSEL4_GPIO88_M 0xF // GPIO88 Master CPU Select +#define GPIO_GPCCSEL4_GPIO89_S 4 +#define GPIO_GPCCSEL4_GPIO89_M 0xF0 // GPIO89 Master CPU Select +#define GPIO_GPCCSEL4_GPIO90_S 8 +#define GPIO_GPCCSEL4_GPIO90_M 0xF00 // GPIO90 Master CPU Select +#define GPIO_GPCCSEL4_GPIO91_S 12 +#define GPIO_GPCCSEL4_GPIO91_M 0xF000 // GPIO91 Master CPU Select +#define GPIO_GPCCSEL4_GPIO92_S 16 +#define GPIO_GPCCSEL4_GPIO92_M 0xF0000 // GPIO92 Master CPU Select +#define GPIO_GPCCSEL4_GPIO93_S 20 +#define GPIO_GPCCSEL4_GPIO93_M 0xF00000 // GPIO93 Master CPU Select +#define GPIO_GPCCSEL4_GPIO94_S 24 +#define GPIO_GPCCSEL4_GPIO94_M 0xF000000 // GPIO94 Master CPU Select +#define GPIO_GPCCSEL4_GPIO95_S 28 +#define GPIO_GPCCSEL4_GPIO95_M 0xF0000000 // GPIO95 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCLOCK register +// +//***************************************************************************** +#define GPIO_GPCLOCK_GPIO64 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO65 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO66 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO67 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO68 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO69 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO70 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO71 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO72 0x100 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO73 0x200 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO74 0x400 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO75 0x800 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO76 0x1000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO77 0x2000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO78 0x4000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO79 0x8000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO80 0x10000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO81 0x20000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO82 0x40000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO83 0x80000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO84 0x100000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO85 0x200000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO86 0x400000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO87 0x800000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO88 0x1000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO89 0x2000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO90 0x4000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO91 0x8000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO92 0x10000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO93 0x20000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO94 0x40000000 // Configuration Lock bit for this + // pin +#define GPIO_GPCLOCK_GPIO95 0x80000000 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCR register +// +//***************************************************************************** +#define GPIO_GPCCR_GPIO64 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO65 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO66 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO67 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO68 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO69 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO70 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO71 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO72 0x100 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO73 0x200 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO74 0x400 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO75 0x800 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO76 0x1000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO77 0x2000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO78 0x4000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO79 0x8000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO80 0x10000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO81 0x20000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO82 0x40000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO83 0x80000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO84 0x100000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO85 0x200000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO86 0x400000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO87 0x800000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO88 0x1000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO89 0x2000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO90 0x4000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO91 0x8000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO92 0x10000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO93 0x20000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO94 0x40000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPCCR_GPIO95 0x80000000 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCTRL register +// +//***************************************************************************** +#define GPIO_GPDCTRL_QUALPRD0_S 0 +#define GPIO_GPDCTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO96 to GPIO103 +#define GPIO_GPDCTRL_QUALPRD1_S 8 +#define GPIO_GPDCTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO104 to GPIO111 +#define GPIO_GPDCTRL_QUALPRD2_S 16 +#define GPIO_GPDCTRL_QUALPRD2_M 0xFF0000 // Qualification sampling period + // for GPIO112 to GPIO119 +#define GPIO_GPDCTRL_QUALPRD3_S 24 +#define GPIO_GPDCTRL_QUALPRD3_M 0xFF000000 // Qualification sampling period + // for GPIO120 to GPIO127 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDQSEL1 register +// +//***************************************************************************** +#define GPIO_GPDQSEL1_GPIO96_S 0 +#define GPIO_GPDQSEL1_GPIO96_M 0x3 // Select input qualification type + // for GPIO96 +#define GPIO_GPDQSEL1_GPIO97_S 2 +#define GPIO_GPDQSEL1_GPIO97_M 0xC // Select input qualification type + // for GPIO97 +#define GPIO_GPDQSEL1_GPIO98_S 4 +#define GPIO_GPDQSEL1_GPIO98_M 0x30 // Select input qualification type + // for GPIO98 +#define GPIO_GPDQSEL1_GPIO99_S 6 +#define GPIO_GPDQSEL1_GPIO99_M 0xC0 // Select input qualification type + // for GPIO99 +#define GPIO_GPDQSEL1_GPIO100_S 8 +#define GPIO_GPDQSEL1_GPIO100_M 0x300 // Select input qualification type + // for GPIO100 +#define GPIO_GPDQSEL1_GPIO101_S 10 +#define GPIO_GPDQSEL1_GPIO101_M 0xC00 // Select input qualification type + // for GPIO101 +#define GPIO_GPDQSEL1_GPIO102_S 12 +#define GPIO_GPDQSEL1_GPIO102_M 0x3000 // Select input qualification type + // for GPIO102 +#define GPIO_GPDQSEL1_GPIO103_S 14 +#define GPIO_GPDQSEL1_GPIO103_M 0xC000 // Select input qualification type + // for GPIO103 +#define GPIO_GPDQSEL1_GPIO104_S 16 +#define GPIO_GPDQSEL1_GPIO104_M 0x30000 // Select input qualification type + // for GPIO104 +#define GPIO_GPDQSEL1_GPIO105_S 18 +#define GPIO_GPDQSEL1_GPIO105_M 0xC0000 // Select input qualification type + // for GPIO105 +#define GPIO_GPDQSEL1_GPIO106_S 20 +#define GPIO_GPDQSEL1_GPIO106_M 0x300000 // Select input qualification type + // for GPIO106 +#define GPIO_GPDQSEL1_GPIO107_S 22 +#define GPIO_GPDQSEL1_GPIO107_M 0xC00000 // Select input qualification type + // for GPIO107 +#define GPIO_GPDQSEL1_GPIO108_S 24 +#define GPIO_GPDQSEL1_GPIO108_M 0x3000000 // Select input qualification type + // for GPIO108 +#define GPIO_GPDQSEL1_GPIO109_S 26 +#define GPIO_GPDQSEL1_GPIO109_M 0xC000000 // Select input qualification type + // for GPIO109 +#define GPIO_GPDQSEL1_GPIO110_S 28 +#define GPIO_GPDQSEL1_GPIO110_M 0x30000000 // Select input qualification type + // for GPIO110 +#define GPIO_GPDQSEL1_GPIO111_S 30 +#define GPIO_GPDQSEL1_GPIO111_M 0xC0000000 // Select input qualification type + // for GPIO111 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDQSEL2 register +// +//***************************************************************************** +#define GPIO_GPDQSEL2_GPIO112_S 0 +#define GPIO_GPDQSEL2_GPIO112_M 0x3 // Select input qualification type + // for GPIO112 +#define GPIO_GPDQSEL2_GPIO113_S 2 +#define GPIO_GPDQSEL2_GPIO113_M 0xC // Select input qualification type + // for GPIO113 +#define GPIO_GPDQSEL2_GPIO114_S 4 +#define GPIO_GPDQSEL2_GPIO114_M 0x30 // Select input qualification type + // for GPIO114 +#define GPIO_GPDQSEL2_GPIO115_S 6 +#define GPIO_GPDQSEL2_GPIO115_M 0xC0 // Select input qualification type + // for GPIO115 +#define GPIO_GPDQSEL2_GPIO116_S 8 +#define GPIO_GPDQSEL2_GPIO116_M 0x300 // Select input qualification type + // for GPIO116 +#define GPIO_GPDQSEL2_GPIO117_S 10 +#define GPIO_GPDQSEL2_GPIO117_M 0xC00 // Select input qualification type + // for GPIO117 +#define GPIO_GPDQSEL2_GPIO118_S 12 +#define GPIO_GPDQSEL2_GPIO118_M 0x3000 // Select input qualification type + // for GPIO118 +#define GPIO_GPDQSEL2_GPIO119_S 14 +#define GPIO_GPDQSEL2_GPIO119_M 0xC000 // Select input qualification type + // for GPIO119 +#define GPIO_GPDQSEL2_GPIO120_S 16 +#define GPIO_GPDQSEL2_GPIO120_M 0x30000 // Select input qualification type + // for GPIO120 +#define GPIO_GPDQSEL2_GPIO121_S 18 +#define GPIO_GPDQSEL2_GPIO121_M 0xC0000 // Select input qualification type + // for GPIO121 +#define GPIO_GPDQSEL2_GPIO122_S 20 +#define GPIO_GPDQSEL2_GPIO122_M 0x300000 // Select input qualification type + // for GPIO122 +#define GPIO_GPDQSEL2_GPIO123_S 22 +#define GPIO_GPDQSEL2_GPIO123_M 0xC00000 // Select input qualification type + // for GPIO123 +#define GPIO_GPDQSEL2_GPIO124_S 24 +#define GPIO_GPDQSEL2_GPIO124_M 0x3000000 // Select input qualification type + // for GPIO124 +#define GPIO_GPDQSEL2_GPIO125_S 26 +#define GPIO_GPDQSEL2_GPIO125_M 0xC000000 // Select input qualification type + // for GPIO125 +#define GPIO_GPDQSEL2_GPIO126_S 28 +#define GPIO_GPDQSEL2_GPIO126_M 0x30000000 // Select input qualification type + // for GPIO126 +#define GPIO_GPDQSEL2_GPIO127_S 30 +#define GPIO_GPDQSEL2_GPIO127_M 0xC0000000 // Select input qualification type + // for GPIO127 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDMUX1 register +// +//***************************************************************************** +#define GPIO_GPDMUX1_GPIO96_S 0 +#define GPIO_GPDMUX1_GPIO96_M 0x3 // Defines pin-muxing selection + // for GPIO96 +#define GPIO_GPDMUX1_GPIO97_S 2 +#define GPIO_GPDMUX1_GPIO97_M 0xC // Defines pin-muxing selection + // for GPIO97 +#define GPIO_GPDMUX1_GPIO98_S 4 +#define GPIO_GPDMUX1_GPIO98_M 0x30 // Defines pin-muxing selection + // for GPIO98 +#define GPIO_GPDMUX1_GPIO99_S 6 +#define GPIO_GPDMUX1_GPIO99_M 0xC0 // Defines pin-muxing selection + // for GPIO99 +#define GPIO_GPDMUX1_GPIO100_S 8 +#define GPIO_GPDMUX1_GPIO100_M 0x300 // Defines pin-muxing selection + // for GPIO100 +#define GPIO_GPDMUX1_GPIO101_S 10 +#define GPIO_GPDMUX1_GPIO101_M 0xC00 // Defines pin-muxing selection + // for GPIO101 +#define GPIO_GPDMUX1_GPIO102_S 12 +#define GPIO_GPDMUX1_GPIO102_M 0x3000 // Defines pin-muxing selection + // for GPIO102 +#define GPIO_GPDMUX1_GPIO103_S 14 +#define GPIO_GPDMUX1_GPIO103_M 0xC000 // Defines pin-muxing selection + // for GPIO103 +#define GPIO_GPDMUX1_GPIO104_S 16 +#define GPIO_GPDMUX1_GPIO104_M 0x30000 // Defines pin-muxing selection + // for GPIO104 +#define GPIO_GPDMUX1_GPIO105_S 18 +#define GPIO_GPDMUX1_GPIO105_M 0xC0000 // Defines pin-muxing selection + // for GPIO105 +#define GPIO_GPDMUX1_GPIO106_S 20 +#define GPIO_GPDMUX1_GPIO106_M 0x300000 // Defines pin-muxing selection + // for GPIO106 +#define GPIO_GPDMUX1_GPIO107_S 22 +#define GPIO_GPDMUX1_GPIO107_M 0xC00000 // Defines pin-muxing selection + // for GPIO107 +#define GPIO_GPDMUX1_GPIO108_S 24 +#define GPIO_GPDMUX1_GPIO108_M 0x3000000 // Defines pin-muxing selection + // for GPIO108 +#define GPIO_GPDMUX1_GPIO109_S 26 +#define GPIO_GPDMUX1_GPIO109_M 0xC000000 // Defines pin-muxing selection + // for GPIO109 +#define GPIO_GPDMUX1_GPIO110_S 28 +#define GPIO_GPDMUX1_GPIO110_M 0x30000000 // Defines pin-muxing selection + // for GPIO110 +#define GPIO_GPDMUX1_GPIO111_S 30 +#define GPIO_GPDMUX1_GPIO111_M 0xC0000000 // Defines pin-muxing selection + // for GPIO111 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDMUX2 register +// +//***************************************************************************** +#define GPIO_GPDMUX2_GPIO112_S 0 +#define GPIO_GPDMUX2_GPIO112_M 0x3 // Defines pin-muxing selection + // for GPIO112 +#define GPIO_GPDMUX2_GPIO113_S 2 +#define GPIO_GPDMUX2_GPIO113_M 0xC // Defines pin-muxing selection + // for GPIO113 +#define GPIO_GPDMUX2_GPIO114_S 4 +#define GPIO_GPDMUX2_GPIO114_M 0x30 // Defines pin-muxing selection + // for GPIO114 +#define GPIO_GPDMUX2_GPIO115_S 6 +#define GPIO_GPDMUX2_GPIO115_M 0xC0 // Defines pin-muxing selection + // for GPIO115 +#define GPIO_GPDMUX2_GPIO116_S 8 +#define GPIO_GPDMUX2_GPIO116_M 0x300 // Defines pin-muxing selection + // for GPIO116 +#define GPIO_GPDMUX2_GPIO117_S 10 +#define GPIO_GPDMUX2_GPIO117_M 0xC00 // Defines pin-muxing selection + // for GPIO117 +#define GPIO_GPDMUX2_GPIO118_S 12 +#define GPIO_GPDMUX2_GPIO118_M 0x3000 // Defines pin-muxing selection + // for GPIO118 +#define GPIO_GPDMUX2_GPIO119_S 14 +#define GPIO_GPDMUX2_GPIO119_M 0xC000 // Defines pin-muxing selection + // for GPIO119 +#define GPIO_GPDMUX2_GPIO120_S 16 +#define GPIO_GPDMUX2_GPIO120_M 0x30000 // Defines pin-muxing selection + // for GPIO120 +#define GPIO_GPDMUX2_GPIO121_S 18 +#define GPIO_GPDMUX2_GPIO121_M 0xC0000 // Defines pin-muxing selection + // for GPIO121 +#define GPIO_GPDMUX2_GPIO122_S 20 +#define GPIO_GPDMUX2_GPIO122_M 0x300000 // Defines pin-muxing selection + // for GPIO122 +#define GPIO_GPDMUX2_GPIO123_S 22 +#define GPIO_GPDMUX2_GPIO123_M 0xC00000 // Defines pin-muxing selection + // for GPIO123 +#define GPIO_GPDMUX2_GPIO124_S 24 +#define GPIO_GPDMUX2_GPIO124_M 0x3000000 // Defines pin-muxing selection + // for GPIO124 +#define GPIO_GPDMUX2_GPIO125_S 26 +#define GPIO_GPDMUX2_GPIO125_M 0xC000000 // Defines pin-muxing selection + // for GPIO125 +#define GPIO_GPDMUX2_GPIO126_S 28 +#define GPIO_GPDMUX2_GPIO126_M 0x30000000 // Defines pin-muxing selection + // for GPIO126 +#define GPIO_GPDMUX2_GPIO127_S 30 +#define GPIO_GPDMUX2_GPIO127_M 0xC0000000 // Defines pin-muxing selection + // for GPIO127 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDDIR register +// +//***************************************************************************** +#define GPIO_GPDDIR_GPIO96 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO97 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO98 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO99 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO100 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO101 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO102 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO103 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO104 0x100 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO105 0x200 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO106 0x400 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO107 0x800 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO108 0x1000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO109 0x2000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO110 0x4000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO111 0x8000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO112 0x10000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO113 0x20000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO114 0x40000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO115 0x80000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO116 0x100000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO117 0x200000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO118 0x400000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO119 0x800000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO120 0x1000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO121 0x2000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO122 0x4000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO123 0x8000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO124 0x10000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO125 0x20000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO126 0x40000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPDDIR_GPIO127 0x80000000 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDPUD register +// +//***************************************************************************** +#define GPIO_GPDPUD_GPIO96 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO97 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO98 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO99 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO100 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO101 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO102 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO103 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO104 0x100 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO105 0x200 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO106 0x400 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO107 0x800 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO108 0x1000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO109 0x2000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO110 0x4000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO111 0x8000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO112 0x10000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO113 0x20000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO114 0x40000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO115 0x80000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO116 0x100000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO117 0x200000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO118 0x400000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO119 0x800000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO120 0x1000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO121 0x2000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO122 0x4000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO123 0x8000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO124 0x10000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO125 0x20000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO126 0x40000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPDPUD_GPIO127 0x80000000 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDINV register +// +//***************************************************************************** +#define GPIO_GPDINV_GPIO96 0x1 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO97 0x2 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO98 0x4 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO99 0x8 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO100 0x10 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO101 0x20 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO102 0x40 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO103 0x80 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO104 0x100 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO105 0x200 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO106 0x400 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO107 0x800 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO108 0x1000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO109 0x2000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO110 0x4000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO111 0x8000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO112 0x10000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO113 0x20000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO114 0x40000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO115 0x80000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO116 0x100000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO117 0x200000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO118 0x400000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO119 0x800000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO120 0x1000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO121 0x2000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO122 0x4000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO123 0x8000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO124 0x10000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO125 0x20000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO126 0x40000000 // Input inversion control for + // this pin +#define GPIO_GPDINV_GPIO127 0x80000000 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDODR register +// +//***************************************************************************** +#define GPIO_GPDODR_GPIO96 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO97 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO98 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO99 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO100 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO101 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO102 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO103 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO104 0x100 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO105 0x200 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO106 0x400 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO107 0x800 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO108 0x1000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO109 0x2000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO110 0x4000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO111 0x8000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO112 0x10000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO113 0x20000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO114 0x40000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO115 0x80000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO116 0x100000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO117 0x200000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO118 0x400000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO119 0x800000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO120 0x1000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO121 0x2000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO122 0x4000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO123 0x8000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO124 0x10000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO125 0x20000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO126 0x40000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPDODR_GPIO127 0x80000000 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDGMUX1 register +// +//***************************************************************************** +#define GPIO_GPDGMUX1_GPIO96_S 0 +#define GPIO_GPDGMUX1_GPIO96_M 0x3 // Defines pin-muxing selection + // for GPIO96 +#define GPIO_GPDGMUX1_GPIO97_S 2 +#define GPIO_GPDGMUX1_GPIO97_M 0xC // Defines pin-muxing selection + // for GPIO97 +#define GPIO_GPDGMUX1_GPIO98_S 4 +#define GPIO_GPDGMUX1_GPIO98_M 0x30 // Defines pin-muxing selection + // for GPIO98 +#define GPIO_GPDGMUX1_GPIO99_S 6 +#define GPIO_GPDGMUX1_GPIO99_M 0xC0 // Defines pin-muxing selection + // for GPIO99 +#define GPIO_GPDGMUX1_GPIO100_S 8 +#define GPIO_GPDGMUX1_GPIO100_M 0x300 // Defines pin-muxing selection + // for GPIO100 +#define GPIO_GPDGMUX1_GPIO101_S 10 +#define GPIO_GPDGMUX1_GPIO101_M 0xC00 // Defines pin-muxing selection + // for GPIO101 +#define GPIO_GPDGMUX1_GPIO102_S 12 +#define GPIO_GPDGMUX1_GPIO102_M 0x3000 // Defines pin-muxing selection + // for GPIO102 +#define GPIO_GPDGMUX1_GPIO103_S 14 +#define GPIO_GPDGMUX1_GPIO103_M 0xC000 // Defines pin-muxing selection + // for GPIO103 +#define GPIO_GPDGMUX1_GPIO104_S 16 +#define GPIO_GPDGMUX1_GPIO104_M 0x30000 // Defines pin-muxing selection + // for GPIO104 +#define GPIO_GPDGMUX1_GPIO105_S 18 +#define GPIO_GPDGMUX1_GPIO105_M 0xC0000 // Defines pin-muxing selection + // for GPIO105 +#define GPIO_GPDGMUX1_GPIO106_S 20 +#define GPIO_GPDGMUX1_GPIO106_M 0x300000 // Defines pin-muxing selection + // for GPIO106 +#define GPIO_GPDGMUX1_GPIO107_S 22 +#define GPIO_GPDGMUX1_GPIO107_M 0xC00000 // Defines pin-muxing selection + // for GPIO107 +#define GPIO_GPDGMUX1_GPIO108_S 24 +#define GPIO_GPDGMUX1_GPIO108_M 0x3000000 // Defines pin-muxing selection + // for GPIO108 +#define GPIO_GPDGMUX1_GPIO109_S 26 +#define GPIO_GPDGMUX1_GPIO109_M 0xC000000 // Defines pin-muxing selection + // for GPIO109 +#define GPIO_GPDGMUX1_GPIO110_S 28 +#define GPIO_GPDGMUX1_GPIO110_M 0x30000000 // Defines pin-muxing selection + // for GPIO110 +#define GPIO_GPDGMUX1_GPIO111_S 30 +#define GPIO_GPDGMUX1_GPIO111_M 0xC0000000 // Defines pin-muxing selection + // for GPIO111 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDGMUX2 register +// +//***************************************************************************** +#define GPIO_GPDGMUX2_GPIO112_S 0 +#define GPIO_GPDGMUX2_GPIO112_M 0x3 // Defines pin-muxing selection + // for GPIO112 +#define GPIO_GPDGMUX2_GPIO113_S 2 +#define GPIO_GPDGMUX2_GPIO113_M 0xC // Defines pin-muxing selection + // for GPIO113 +#define GPIO_GPDGMUX2_GPIO114_S 4 +#define GPIO_GPDGMUX2_GPIO114_M 0x30 // Defines pin-muxing selection + // for GPIO114 +#define GPIO_GPDGMUX2_GPIO115_S 6 +#define GPIO_GPDGMUX2_GPIO115_M 0xC0 // Defines pin-muxing selection + // for GPIO115 +#define GPIO_GPDGMUX2_GPIO116_S 8 +#define GPIO_GPDGMUX2_GPIO116_M 0x300 // Defines pin-muxing selection + // for GPIO116 +#define GPIO_GPDGMUX2_GPIO117_S 10 +#define GPIO_GPDGMUX2_GPIO117_M 0xC00 // Defines pin-muxing selection + // for GPIO117 +#define GPIO_GPDGMUX2_GPIO118_S 12 +#define GPIO_GPDGMUX2_GPIO118_M 0x3000 // Defines pin-muxing selection + // for GPIO118 +#define GPIO_GPDGMUX2_GPIO119_S 14 +#define GPIO_GPDGMUX2_GPIO119_M 0xC000 // Defines pin-muxing selection + // for GPIO119 +#define GPIO_GPDGMUX2_GPIO120_S 16 +#define GPIO_GPDGMUX2_GPIO120_M 0x30000 // Defines pin-muxing selection + // for GPIO120 +#define GPIO_GPDGMUX2_GPIO121_S 18 +#define GPIO_GPDGMUX2_GPIO121_M 0xC0000 // Defines pin-muxing selection + // for GPIO121 +#define GPIO_GPDGMUX2_GPIO122_S 20 +#define GPIO_GPDGMUX2_GPIO122_M 0x300000 // Defines pin-muxing selection + // for GPIO122 +#define GPIO_GPDGMUX2_GPIO123_S 22 +#define GPIO_GPDGMUX2_GPIO123_M 0xC00000 // Defines pin-muxing selection + // for GPIO123 +#define GPIO_GPDGMUX2_GPIO124_S 24 +#define GPIO_GPDGMUX2_GPIO124_M 0x3000000 // Defines pin-muxing selection + // for GPIO124 +#define GPIO_GPDGMUX2_GPIO125_S 26 +#define GPIO_GPDGMUX2_GPIO125_M 0xC000000 // Defines pin-muxing selection + // for GPIO125 +#define GPIO_GPDGMUX2_GPIO126_S 28 +#define GPIO_GPDGMUX2_GPIO126_M 0x30000000 // Defines pin-muxing selection + // for GPIO126 +#define GPIO_GPDGMUX2_GPIO127_S 30 +#define GPIO_GPDGMUX2_GPIO127_M 0xC0000000 // Defines pin-muxing selection + // for GPIO127 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCSEL1 register +// +//***************************************************************************** +#define GPIO_GPDCSEL1_GPIO96_S 0 +#define GPIO_GPDCSEL1_GPIO96_M 0xF // GPIO96 Master CPU Select +#define GPIO_GPDCSEL1_GPIO97_S 4 +#define GPIO_GPDCSEL1_GPIO97_M 0xF0 // GPIO97 Master CPU Select +#define GPIO_GPDCSEL1_GPIO98_S 8 +#define GPIO_GPDCSEL1_GPIO98_M 0xF00 // GPIO98 Master CPU Select +#define GPIO_GPDCSEL1_GPIO99_S 12 +#define GPIO_GPDCSEL1_GPIO99_M 0xF000 // GPIO99 Master CPU Select +#define GPIO_GPDCSEL1_GPIO100_S 16 +#define GPIO_GPDCSEL1_GPIO100_M 0xF0000 // GPIO100 Master CPU Select +#define GPIO_GPDCSEL1_GPIO101_S 20 +#define GPIO_GPDCSEL1_GPIO101_M 0xF00000 // GPIO101 Master CPU Select +#define GPIO_GPDCSEL1_GPIO102_S 24 +#define GPIO_GPDCSEL1_GPIO102_M 0xF000000 // GPIO102 Master CPU Select +#define GPIO_GPDCSEL1_GPIO103_S 28 +#define GPIO_GPDCSEL1_GPIO103_M 0xF0000000 // GPIO103 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCSEL2 register +// +//***************************************************************************** +#define GPIO_GPDCSEL2_GPIO104_S 0 +#define GPIO_GPDCSEL2_GPIO104_M 0xF // GPIO104 Master CPU Select +#define GPIO_GPDCSEL2_GPIO105_S 4 +#define GPIO_GPDCSEL2_GPIO105_M 0xF0 // GPIO105 Master CPU Select +#define GPIO_GPDCSEL2_GPIO106_S 8 +#define GPIO_GPDCSEL2_GPIO106_M 0xF00 // GPIO106 Master CPU Select +#define GPIO_GPDCSEL2_GPIO107_S 12 +#define GPIO_GPDCSEL2_GPIO107_M 0xF000 // GPIO107 Master CPU Select +#define GPIO_GPDCSEL2_GPIO108_S 16 +#define GPIO_GPDCSEL2_GPIO108_M 0xF0000 // GPIO108 Master CPU Select +#define GPIO_GPDCSEL2_GPIO109_S 20 +#define GPIO_GPDCSEL2_GPIO109_M 0xF00000 // GPIO109 Master CPU Select +#define GPIO_GPDCSEL2_GPIO110_S 24 +#define GPIO_GPDCSEL2_GPIO110_M 0xF000000 // GPIO110 Master CPU Select +#define GPIO_GPDCSEL2_GPIO111_S 28 +#define GPIO_GPDCSEL2_GPIO111_M 0xF0000000 // GPIO111 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCSEL3 register +// +//***************************************************************************** +#define GPIO_GPDCSEL3_GPIO112_S 0 +#define GPIO_GPDCSEL3_GPIO112_M 0xF // GPIO112 Master CPU Select +#define GPIO_GPDCSEL3_GPIO113_S 4 +#define GPIO_GPDCSEL3_GPIO113_M 0xF0 // GPIO113 Master CPU Select +#define GPIO_GPDCSEL3_GPIO114_S 8 +#define GPIO_GPDCSEL3_GPIO114_M 0xF00 // GPIO114 Master CPU Select +#define GPIO_GPDCSEL3_GPIO115_S 12 +#define GPIO_GPDCSEL3_GPIO115_M 0xF000 // GPIO115 Master CPU Select +#define GPIO_GPDCSEL3_GPIO116_S 16 +#define GPIO_GPDCSEL3_GPIO116_M 0xF0000 // GPIO116 Master CPU Select +#define GPIO_GPDCSEL3_GPIO117_S 20 +#define GPIO_GPDCSEL3_GPIO117_M 0xF00000 // GPIO117 Master CPU Select +#define GPIO_GPDCSEL3_GPIO118_S 24 +#define GPIO_GPDCSEL3_GPIO118_M 0xF000000 // GPIO118 Master CPU Select +#define GPIO_GPDCSEL3_GPIO119_S 28 +#define GPIO_GPDCSEL3_GPIO119_M 0xF0000000 // GPIO119 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCSEL4 register +// +//***************************************************************************** +#define GPIO_GPDCSEL4_GPIO120_S 0 +#define GPIO_GPDCSEL4_GPIO120_M 0xF // GPIO120 Master CPU Select +#define GPIO_GPDCSEL4_GPIO121_S 4 +#define GPIO_GPDCSEL4_GPIO121_M 0xF0 // GPIO121 Master CPU Select +#define GPIO_GPDCSEL4_GPIO122_S 8 +#define GPIO_GPDCSEL4_GPIO122_M 0xF00 // GPIO122 Master CPU Select +#define GPIO_GPDCSEL4_GPIO123_S 12 +#define GPIO_GPDCSEL4_GPIO123_M 0xF000 // GPIO123 Master CPU Select +#define GPIO_GPDCSEL4_GPIO124_S 16 +#define GPIO_GPDCSEL4_GPIO124_M 0xF0000 // GPIO124 Master CPU Select +#define GPIO_GPDCSEL4_GPIO125_S 20 +#define GPIO_GPDCSEL4_GPIO125_M 0xF00000 // GPIO125 Master CPU Select +#define GPIO_GPDCSEL4_GPIO126_S 24 +#define GPIO_GPDCSEL4_GPIO126_M 0xF000000 // GPIO126 Master CPU Select +#define GPIO_GPDCSEL4_GPIO127_S 28 +#define GPIO_GPDCSEL4_GPIO127_M 0xF0000000 // GPIO127 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDLOCK register +// +//***************************************************************************** +#define GPIO_GPDLOCK_GPIO96 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO97 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO98 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO99 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO100 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO101 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO102 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO103 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO104 0x100 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO105 0x200 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO106 0x400 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO107 0x800 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO108 0x1000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO109 0x2000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO110 0x4000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO111 0x8000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO112 0x10000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO113 0x20000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO114 0x40000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO115 0x80000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO116 0x100000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO117 0x200000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO118 0x400000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO119 0x800000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO120 0x1000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO121 0x2000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO122 0x4000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO123 0x8000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO124 0x10000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO125 0x20000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO126 0x40000000 // Configuration Lock bit for this + // pin +#define GPIO_GPDLOCK_GPIO127 0x80000000 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCR register +// +//***************************************************************************** +#define GPIO_GPDCR_GPIO96 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO97 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO98 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO99 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO100 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO101 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO102 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO103 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO104 0x100 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO105 0x200 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO106 0x400 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO107 0x800 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO108 0x1000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO109 0x2000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO110 0x4000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO111 0x8000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO112 0x10000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO113 0x20000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO114 0x40000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO115 0x80000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO116 0x100000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO117 0x200000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO118 0x400000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO119 0x800000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO120 0x1000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO121 0x2000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO122 0x4000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO123 0x8000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO124 0x10000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO125 0x20000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO126 0x40000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPDCR_GPIO127 0x80000000 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECTRL register +// +//***************************************************************************** +#define GPIO_GPECTRL_QUALPRD0_S 0 +#define GPIO_GPECTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO128 to GPIO135 +#define GPIO_GPECTRL_QUALPRD1_S 8 +#define GPIO_GPECTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO136 to GPIO143 +#define GPIO_GPECTRL_QUALPRD2_S 16 +#define GPIO_GPECTRL_QUALPRD2_M 0xFF0000 // Qualification sampling period + // for GPIO144 to GPIO151 +#define GPIO_GPECTRL_QUALPRD3_S 24 +#define GPIO_GPECTRL_QUALPRD3_M 0xFF000000 // Qualification sampling period + // for GPIO152 to GPIO159 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEQSEL1 register +// +//***************************************************************************** +#define GPIO_GPEQSEL1_GPIO128_S 0 +#define GPIO_GPEQSEL1_GPIO128_M 0x3 // Select input qualification type + // for GPIO128 +#define GPIO_GPEQSEL1_GPIO129_S 2 +#define GPIO_GPEQSEL1_GPIO129_M 0xC // Select input qualification type + // for GPIO129 +#define GPIO_GPEQSEL1_GPIO130_S 4 +#define GPIO_GPEQSEL1_GPIO130_M 0x30 // Select input qualification type + // for GPIO130 +#define GPIO_GPEQSEL1_GPIO131_S 6 +#define GPIO_GPEQSEL1_GPIO131_M 0xC0 // Select input qualification type + // for GPIO131 +#define GPIO_GPEQSEL1_GPIO132_S 8 +#define GPIO_GPEQSEL1_GPIO132_M 0x300 // Select input qualification type + // for GPIO132 +#define GPIO_GPEQSEL1_GPIO133_S 10 +#define GPIO_GPEQSEL1_GPIO133_M 0xC00 // Select input qualification type + // for GPIO133 +#define GPIO_GPEQSEL1_GPIO134_S 12 +#define GPIO_GPEQSEL1_GPIO134_M 0x3000 // Select input qualification type + // for GPIO134 +#define GPIO_GPEQSEL1_GPIO135_S 14 +#define GPIO_GPEQSEL1_GPIO135_M 0xC000 // Select input qualification type + // for GPIO135 +#define GPIO_GPEQSEL1_GPIO136_S 16 +#define GPIO_GPEQSEL1_GPIO136_M 0x30000 // Select input qualification type + // for GPIO136 +#define GPIO_GPEQSEL1_GPIO137_S 18 +#define GPIO_GPEQSEL1_GPIO137_M 0xC0000 // Select input qualification type + // for GPIO137 +#define GPIO_GPEQSEL1_GPIO138_S 20 +#define GPIO_GPEQSEL1_GPIO138_M 0x300000 // Select input qualification type + // for GPIO138 +#define GPIO_GPEQSEL1_GPIO139_S 22 +#define GPIO_GPEQSEL1_GPIO139_M 0xC00000 // Select input qualification type + // for GPIO139 +#define GPIO_GPEQSEL1_GPIO140_S 24 +#define GPIO_GPEQSEL1_GPIO140_M 0x3000000 // Select input qualification type + // for GPIO140 +#define GPIO_GPEQSEL1_GPIO141_S 26 +#define GPIO_GPEQSEL1_GPIO141_M 0xC000000 // Select input qualification type + // for GPIO141 +#define GPIO_GPEQSEL1_GPIO142_S 28 +#define GPIO_GPEQSEL1_GPIO142_M 0x30000000 // Select input qualification type + // for GPIO142 +#define GPIO_GPEQSEL1_GPIO143_S 30 +#define GPIO_GPEQSEL1_GPIO143_M 0xC0000000 // Select input qualification type + // for GPIO143 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEQSEL2 register +// +//***************************************************************************** +#define GPIO_GPEQSEL2_GPIO144_S 0 +#define GPIO_GPEQSEL2_GPIO144_M 0x3 // Select input qualification type + // for GPIO144 +#define GPIO_GPEQSEL2_GPIO145_S 2 +#define GPIO_GPEQSEL2_GPIO145_M 0xC // Select input qualification type + // for GPIO145 +#define GPIO_GPEQSEL2_GPIO146_S 4 +#define GPIO_GPEQSEL2_GPIO146_M 0x30 // Select input qualification type + // for GPIO146 +#define GPIO_GPEQSEL2_GPIO147_S 6 +#define GPIO_GPEQSEL2_GPIO147_M 0xC0 // Select input qualification type + // for GPIO147 +#define GPIO_GPEQSEL2_GPIO148_S 8 +#define GPIO_GPEQSEL2_GPIO148_M 0x300 // Select input qualification type + // for GPIO148 +#define GPIO_GPEQSEL2_GPIO149_S 10 +#define GPIO_GPEQSEL2_GPIO149_M 0xC00 // Select input qualification type + // for GPIO149 +#define GPIO_GPEQSEL2_GPIO150_S 12 +#define GPIO_GPEQSEL2_GPIO150_M 0x3000 // Select input qualification type + // for GPIO150 +#define GPIO_GPEQSEL2_GPIO151_S 14 +#define GPIO_GPEQSEL2_GPIO151_M 0xC000 // Select input qualification type + // for GPIO151 +#define GPIO_GPEQSEL2_GPIO152_S 16 +#define GPIO_GPEQSEL2_GPIO152_M 0x30000 // Select input qualification type + // for GPIO152 +#define GPIO_GPEQSEL2_GPIO153_S 18 +#define GPIO_GPEQSEL2_GPIO153_M 0xC0000 // Select input qualification type + // for GPIO153 +#define GPIO_GPEQSEL2_GPIO154_S 20 +#define GPIO_GPEQSEL2_GPIO154_M 0x300000 // Select input qualification type + // for GPIO154 +#define GPIO_GPEQSEL2_GPIO155_S 22 +#define GPIO_GPEQSEL2_GPIO155_M 0xC00000 // Select input qualification type + // for GPIO155 +#define GPIO_GPEQSEL2_GPIO156_S 24 +#define GPIO_GPEQSEL2_GPIO156_M 0x3000000 // Select input qualification type + // for GPIO156 +#define GPIO_GPEQSEL2_GPIO157_S 26 +#define GPIO_GPEQSEL2_GPIO157_M 0xC000000 // Select input qualification type + // for GPIO157 +#define GPIO_GPEQSEL2_GPIO158_S 28 +#define GPIO_GPEQSEL2_GPIO158_M 0x30000000 // Select input qualification type + // for GPIO158 +#define GPIO_GPEQSEL2_GPIO159_S 30 +#define GPIO_GPEQSEL2_GPIO159_M 0xC0000000 // Select input qualification type + // for GPIO159 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEMUX1 register +// +//***************************************************************************** +#define GPIO_GPEMUX1_GPIO128_S 0 +#define GPIO_GPEMUX1_GPIO128_M 0x3 // Defines pin-muxing selection + // for GPIO128 +#define GPIO_GPEMUX1_GPIO129_S 2 +#define GPIO_GPEMUX1_GPIO129_M 0xC // Defines pin-muxing selection + // for GPIO129 +#define GPIO_GPEMUX1_GPIO130_S 4 +#define GPIO_GPEMUX1_GPIO130_M 0x30 // Defines pin-muxing selection + // for GPIO130 +#define GPIO_GPEMUX1_GPIO131_S 6 +#define GPIO_GPEMUX1_GPIO131_M 0xC0 // Defines pin-muxing selection + // for GPIO131 +#define GPIO_GPEMUX1_GPIO132_S 8 +#define GPIO_GPEMUX1_GPIO132_M 0x300 // Defines pin-muxing selection + // for GPIO132 +#define GPIO_GPEMUX1_GPIO133_S 10 +#define GPIO_GPEMUX1_GPIO133_M 0xC00 // Defines pin-muxing selection + // for GPIO133 +#define GPIO_GPEMUX1_GPIO134_S 12 +#define GPIO_GPEMUX1_GPIO134_M 0x3000 // Defines pin-muxing selection + // for GPIO134 +#define GPIO_GPEMUX1_GPIO135_S 14 +#define GPIO_GPEMUX1_GPIO135_M 0xC000 // Defines pin-muxing selection + // for GPIO135 +#define GPIO_GPEMUX1_GPIO136_S 16 +#define GPIO_GPEMUX1_GPIO136_M 0x30000 // Defines pin-muxing selection + // for GPIO136 +#define GPIO_GPEMUX1_GPIO137_S 18 +#define GPIO_GPEMUX1_GPIO137_M 0xC0000 // Defines pin-muxing selection + // for GPIO137 +#define GPIO_GPEMUX1_GPIO138_S 20 +#define GPIO_GPEMUX1_GPIO138_M 0x300000 // Defines pin-muxing selection + // for GPIO138 +#define GPIO_GPEMUX1_GPIO139_S 22 +#define GPIO_GPEMUX1_GPIO139_M 0xC00000 // Defines pin-muxing selection + // for GPIO139 +#define GPIO_GPEMUX1_GPIO140_S 24 +#define GPIO_GPEMUX1_GPIO140_M 0x3000000 // Defines pin-muxing selection + // for GPIO140 +#define GPIO_GPEMUX1_GPIO141_S 26 +#define GPIO_GPEMUX1_GPIO141_M 0xC000000 // Defines pin-muxing selection + // for GPIO141 +#define GPIO_GPEMUX1_GPIO142_S 28 +#define GPIO_GPEMUX1_GPIO142_M 0x30000000 // Defines pin-muxing selection + // for GPIO142 +#define GPIO_GPEMUX1_GPIO143_S 30 +#define GPIO_GPEMUX1_GPIO143_M 0xC0000000 // Defines pin-muxing selection + // for GPIO143 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEMUX2 register +// +//***************************************************************************** +#define GPIO_GPEMUX2_GPIO144_S 0 +#define GPIO_GPEMUX2_GPIO144_M 0x3 // Defines pin-muxing selection + // for GPIO144 +#define GPIO_GPEMUX2_GPIO145_S 2 +#define GPIO_GPEMUX2_GPIO145_M 0xC // Defines pin-muxing selection + // for GPIO145 +#define GPIO_GPEMUX2_GPIO146_S 4 +#define GPIO_GPEMUX2_GPIO146_M 0x30 // Defines pin-muxing selection + // for GPIO146 +#define GPIO_GPEMUX2_GPIO147_S 6 +#define GPIO_GPEMUX2_GPIO147_M 0xC0 // Defines pin-muxing selection + // for GPIO147 +#define GPIO_GPEMUX2_GPIO148_S 8 +#define GPIO_GPEMUX2_GPIO148_M 0x300 // Defines pin-muxing selection + // for GPIO148 +#define GPIO_GPEMUX2_GPIO149_S 10 +#define GPIO_GPEMUX2_GPIO149_M 0xC00 // Defines pin-muxing selection + // for GPIO149 +#define GPIO_GPEMUX2_GPIO150_S 12 +#define GPIO_GPEMUX2_GPIO150_M 0x3000 // Defines pin-muxing selection + // for GPIO150 +#define GPIO_GPEMUX2_GPIO151_S 14 +#define GPIO_GPEMUX2_GPIO151_M 0xC000 // Defines pin-muxing selection + // for GPIO151 +#define GPIO_GPEMUX2_GPIO152_S 16 +#define GPIO_GPEMUX2_GPIO152_M 0x30000 // Defines pin-muxing selection + // for GPIO152 +#define GPIO_GPEMUX2_GPIO153_S 18 +#define GPIO_GPEMUX2_GPIO153_M 0xC0000 // Defines pin-muxing selection + // for GPIO153 +#define GPIO_GPEMUX2_GPIO154_S 20 +#define GPIO_GPEMUX2_GPIO154_M 0x300000 // Defines pin-muxing selection + // for GPIO154 +#define GPIO_GPEMUX2_GPIO155_S 22 +#define GPIO_GPEMUX2_GPIO155_M 0xC00000 // Defines pin-muxing selection + // for GPIO155 +#define GPIO_GPEMUX2_GPIO156_S 24 +#define GPIO_GPEMUX2_GPIO156_M 0x3000000 // Defines pin-muxing selection + // for GPIO156 +#define GPIO_GPEMUX2_GPIO157_S 26 +#define GPIO_GPEMUX2_GPIO157_M 0xC000000 // Defines pin-muxing selection + // for GPIO157 +#define GPIO_GPEMUX2_GPIO158_S 28 +#define GPIO_GPEMUX2_GPIO158_M 0x30000000 // Defines pin-muxing selection + // for GPIO158 +#define GPIO_GPEMUX2_GPIO159_S 30 +#define GPIO_GPEMUX2_GPIO159_M 0xC0000000 // Defines pin-muxing selection + // for GPIO159 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEDIR register +// +//***************************************************************************** +#define GPIO_GPEDIR_GPIO128 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO129 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO130 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO131 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO132 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO133 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO134 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO135 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO136 0x100 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO137 0x200 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO138 0x400 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO139 0x800 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO140 0x1000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO141 0x2000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO142 0x4000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO143 0x8000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO144 0x10000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO145 0x20000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO146 0x40000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO147 0x80000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO148 0x100000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO149 0x200000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO150 0x400000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO151 0x800000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO152 0x1000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO153 0x2000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO154 0x4000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO155 0x8000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO156 0x10000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO157 0x20000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO158 0x40000000 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPEDIR_GPIO159 0x80000000 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEPUD register +// +//***************************************************************************** +#define GPIO_GPEPUD_GPIO128 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO129 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO130 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO131 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO132 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO133 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO134 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO135 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO136 0x100 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO137 0x200 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO138 0x400 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO139 0x800 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO140 0x1000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO141 0x2000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO142 0x4000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO143 0x8000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO144 0x10000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO145 0x20000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO146 0x40000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO147 0x80000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO148 0x100000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO149 0x200000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO150 0x400000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO151 0x800000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO152 0x1000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO153 0x2000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO154 0x4000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO155 0x8000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO156 0x10000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO157 0x20000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO158 0x40000000 // Pull-Up Disable control for + // this pin +#define GPIO_GPEPUD_GPIO159 0x80000000 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEINV register +// +//***************************************************************************** +#define GPIO_GPEINV_GPIO128 0x1 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO129 0x2 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO130 0x4 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO131 0x8 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO132 0x10 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO133 0x20 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO134 0x40 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO135 0x80 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO136 0x100 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO137 0x200 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO138 0x400 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO139 0x800 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO140 0x1000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO141 0x2000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO142 0x4000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO143 0x8000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO144 0x10000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO145 0x20000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO146 0x40000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO147 0x80000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO148 0x100000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO149 0x200000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO150 0x400000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO151 0x800000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO152 0x1000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO153 0x2000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO154 0x4000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO155 0x8000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO156 0x10000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO157 0x20000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO158 0x40000000 // Input inversion control for + // this pin +#define GPIO_GPEINV_GPIO159 0x80000000 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEODR register +// +//***************************************************************************** +#define GPIO_GPEODR_GPIO128 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO129 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO130 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO131 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO132 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO133 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO134 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO135 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO136 0x100 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO137 0x200 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO138 0x400 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO139 0x800 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO140 0x1000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO141 0x2000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO142 0x4000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO143 0x8000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO144 0x10000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO145 0x20000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO146 0x40000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO147 0x80000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO148 0x100000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO149 0x200000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO150 0x400000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO151 0x800000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO152 0x1000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO153 0x2000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO154 0x4000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO155 0x8000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO156 0x10000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO157 0x20000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO158 0x40000000 // Outpout Open-Drain control for + // this pin +#define GPIO_GPEODR_GPIO159 0x80000000 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEGMUX1 register +// +//***************************************************************************** +#define GPIO_GPEGMUX1_GPIO128_S 0 +#define GPIO_GPEGMUX1_GPIO128_M 0x3 // Defines pin-muxing selection + // for GPIO128 +#define GPIO_GPEGMUX1_GPIO129_S 2 +#define GPIO_GPEGMUX1_GPIO129_M 0xC // Defines pin-muxing selection + // for GPIO129 +#define GPIO_GPEGMUX1_GPIO130_S 4 +#define GPIO_GPEGMUX1_GPIO130_M 0x30 // Defines pin-muxing selection + // for GPIO130 +#define GPIO_GPEGMUX1_GPIO131_S 6 +#define GPIO_GPEGMUX1_GPIO131_M 0xC0 // Defines pin-muxing selection + // for GPIO131 +#define GPIO_GPEGMUX1_GPIO132_S 8 +#define GPIO_GPEGMUX1_GPIO132_M 0x300 // Defines pin-muxing selection + // for GPIO132 +#define GPIO_GPEGMUX1_GPIO133_S 10 +#define GPIO_GPEGMUX1_GPIO133_M 0xC00 // Defines pin-muxing selection + // for GPIO133 +#define GPIO_GPEGMUX1_GPIO134_S 12 +#define GPIO_GPEGMUX1_GPIO134_M 0x3000 // Defines pin-muxing selection + // for GPIO134 +#define GPIO_GPEGMUX1_GPIO135_S 14 +#define GPIO_GPEGMUX1_GPIO135_M 0xC000 // Defines pin-muxing selection + // for GPIO135 +#define GPIO_GPEGMUX1_GPIO136_S 16 +#define GPIO_GPEGMUX1_GPIO136_M 0x30000 // Defines pin-muxing selection + // for GPIO136 +#define GPIO_GPEGMUX1_GPIO137_S 18 +#define GPIO_GPEGMUX1_GPIO137_M 0xC0000 // Defines pin-muxing selection + // for GPIO137 +#define GPIO_GPEGMUX1_GPIO138_S 20 +#define GPIO_GPEGMUX1_GPIO138_M 0x300000 // Defines pin-muxing selection + // for GPIO138 +#define GPIO_GPEGMUX1_GPIO139_S 22 +#define GPIO_GPEGMUX1_GPIO139_M 0xC00000 // Defines pin-muxing selection + // for GPIO139 +#define GPIO_GPEGMUX1_GPIO140_S 24 +#define GPIO_GPEGMUX1_GPIO140_M 0x3000000 // Defines pin-muxing selection + // for GPIO140 +#define GPIO_GPEGMUX1_GPIO141_S 26 +#define GPIO_GPEGMUX1_GPIO141_M 0xC000000 // Defines pin-muxing selection + // for GPIO141 +#define GPIO_GPEGMUX1_GPIO142_S 28 +#define GPIO_GPEGMUX1_GPIO142_M 0x30000000 // Defines pin-muxing selection + // for GPIO142 +#define GPIO_GPEGMUX1_GPIO143_S 30 +#define GPIO_GPEGMUX1_GPIO143_M 0xC0000000 // Defines pin-muxing selection + // for GPIO143 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEGMUX2 register +// +//***************************************************************************** +#define GPIO_GPEGMUX2_GPIO144_S 0 +#define GPIO_GPEGMUX2_GPIO144_M 0x3 // Defines pin-muxing selection + // for GPIO144 +#define GPIO_GPEGMUX2_GPIO145_S 2 +#define GPIO_GPEGMUX2_GPIO145_M 0xC // Defines pin-muxing selection + // for GPIO145 +#define GPIO_GPEGMUX2_GPIO146_S 4 +#define GPIO_GPEGMUX2_GPIO146_M 0x30 // Defines pin-muxing selection + // for GPIO146 +#define GPIO_GPEGMUX2_GPIO147_S 6 +#define GPIO_GPEGMUX2_GPIO147_M 0xC0 // Defines pin-muxing selection + // for GPIO147 +#define GPIO_GPEGMUX2_GPIO148_S 8 +#define GPIO_GPEGMUX2_GPIO148_M 0x300 // Defines pin-muxing selection + // for GPIO148 +#define GPIO_GPEGMUX2_GPIO149_S 10 +#define GPIO_GPEGMUX2_GPIO149_M 0xC00 // Defines pin-muxing selection + // for GPIO149 +#define GPIO_GPEGMUX2_GPIO150_S 12 +#define GPIO_GPEGMUX2_GPIO150_M 0x3000 // Defines pin-muxing selection + // for GPIO150 +#define GPIO_GPEGMUX2_GPIO151_S 14 +#define GPIO_GPEGMUX2_GPIO151_M 0xC000 // Defines pin-muxing selection + // for GPIO151 +#define GPIO_GPEGMUX2_GPIO152_S 16 +#define GPIO_GPEGMUX2_GPIO152_M 0x30000 // Defines pin-muxing selection + // for GPIO152 +#define GPIO_GPEGMUX2_GPIO153_S 18 +#define GPIO_GPEGMUX2_GPIO153_M 0xC0000 // Defines pin-muxing selection + // for GPIO153 +#define GPIO_GPEGMUX2_GPIO154_S 20 +#define GPIO_GPEGMUX2_GPIO154_M 0x300000 // Defines pin-muxing selection + // for GPIO154 +#define GPIO_GPEGMUX2_GPIO155_S 22 +#define GPIO_GPEGMUX2_GPIO155_M 0xC00000 // Defines pin-muxing selection + // for GPIO155 +#define GPIO_GPEGMUX2_GPIO156_S 24 +#define GPIO_GPEGMUX2_GPIO156_M 0x3000000 // Defines pin-muxing selection + // for GPIO156 +#define GPIO_GPEGMUX2_GPIO157_S 26 +#define GPIO_GPEGMUX2_GPIO157_M 0xC000000 // Defines pin-muxing selection + // for GPIO157 +#define GPIO_GPEGMUX2_GPIO158_S 28 +#define GPIO_GPEGMUX2_GPIO158_M 0x30000000 // Defines pin-muxing selection + // for GPIO158 +#define GPIO_GPEGMUX2_GPIO159_S 30 +#define GPIO_GPEGMUX2_GPIO159_M 0xC0000000 // Defines pin-muxing selection + // for GPIO159 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECSEL1 register +// +//***************************************************************************** +#define GPIO_GPECSEL1_GPIO128_S 0 +#define GPIO_GPECSEL1_GPIO128_M 0xF // GPIO128 Master CPU Select +#define GPIO_GPECSEL1_GPIO129_S 4 +#define GPIO_GPECSEL1_GPIO129_M 0xF0 // GPIO129 Master CPU Select +#define GPIO_GPECSEL1_GPIO130_S 8 +#define GPIO_GPECSEL1_GPIO130_M 0xF00 // GPIO130 Master CPU Select +#define GPIO_GPECSEL1_GPIO131_S 12 +#define GPIO_GPECSEL1_GPIO131_M 0xF000 // GPIO131 Master CPU Select +#define GPIO_GPECSEL1_GPIO132_S 16 +#define GPIO_GPECSEL1_GPIO132_M 0xF0000 // GPIO132 Master CPU Select +#define GPIO_GPECSEL1_GPIO133_S 20 +#define GPIO_GPECSEL1_GPIO133_M 0xF00000 // GPIO133 Master CPU Select +#define GPIO_GPECSEL1_GPIO134_S 24 +#define GPIO_GPECSEL1_GPIO134_M 0xF000000 // GPIO134 Master CPU Select +#define GPIO_GPECSEL1_GPIO135_S 28 +#define GPIO_GPECSEL1_GPIO135_M 0xF0000000 // GPIO135 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECSEL2 register +// +//***************************************************************************** +#define GPIO_GPECSEL2_GPIO136_S 0 +#define GPIO_GPECSEL2_GPIO136_M 0xF // GPIO136 Master CPU Select +#define GPIO_GPECSEL2_GPIO137_S 4 +#define GPIO_GPECSEL2_GPIO137_M 0xF0 // GPIO137 Master CPU Select +#define GPIO_GPECSEL2_GPIO138_S 8 +#define GPIO_GPECSEL2_GPIO138_M 0xF00 // GPIO138 Master CPU Select +#define GPIO_GPECSEL2_GPIO139_S 12 +#define GPIO_GPECSEL2_GPIO139_M 0xF000 // GPIO139 Master CPU Select +#define GPIO_GPECSEL2_GPIO140_S 16 +#define GPIO_GPECSEL2_GPIO140_M 0xF0000 // GPIO140 Master CPU Select +#define GPIO_GPECSEL2_GPIO141_S 20 +#define GPIO_GPECSEL2_GPIO141_M 0xF00000 // GPIO141 Master CPU Select +#define GPIO_GPECSEL2_GPIO142_S 24 +#define GPIO_GPECSEL2_GPIO142_M 0xF000000 // GPIO142 Master CPU Select +#define GPIO_GPECSEL2_GPIO143_S 28 +#define GPIO_GPECSEL2_GPIO143_M 0xF0000000 // GPIO143 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECSEL3 register +// +//***************************************************************************** +#define GPIO_GPECSEL3_GPIO144_S 0 +#define GPIO_GPECSEL3_GPIO144_M 0xF // GPIO144 Master CPU Select +#define GPIO_GPECSEL3_GPIO145_S 4 +#define GPIO_GPECSEL3_GPIO145_M 0xF0 // GPIO145 Master CPU Select +#define GPIO_GPECSEL3_GPIO146_S 8 +#define GPIO_GPECSEL3_GPIO146_M 0xF00 // GPIO146 Master CPU Select +#define GPIO_GPECSEL3_GPIO147_S 12 +#define GPIO_GPECSEL3_GPIO147_M 0xF000 // GPIO147 Master CPU Select +#define GPIO_GPECSEL3_GPIO148_S 16 +#define GPIO_GPECSEL3_GPIO148_M 0xF0000 // GPIO148 Master CPU Select +#define GPIO_GPECSEL3_GPIO149_S 20 +#define GPIO_GPECSEL3_GPIO149_M 0xF00000 // GPIO149 Master CPU Select +#define GPIO_GPECSEL3_GPIO150_S 24 +#define GPIO_GPECSEL3_GPIO150_M 0xF000000 // GPIO150 Master CPU Select +#define GPIO_GPECSEL3_GPIO151_S 28 +#define GPIO_GPECSEL3_GPIO151_M 0xF0000000 // GPIO151 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECSEL4 register +// +//***************************************************************************** +#define GPIO_GPECSEL4_GPIO152_S 0 +#define GPIO_GPECSEL4_GPIO152_M 0xF // GPIO152 Master CPU Select +#define GPIO_GPECSEL4_GPIO153_S 4 +#define GPIO_GPECSEL4_GPIO153_M 0xF0 // GPIO153 Master CPU Select +#define GPIO_GPECSEL4_GPIO154_S 8 +#define GPIO_GPECSEL4_GPIO154_M 0xF00 // GPIO154 Master CPU Select +#define GPIO_GPECSEL4_GPIO155_S 12 +#define GPIO_GPECSEL4_GPIO155_M 0xF000 // GPIO155 Master CPU Select +#define GPIO_GPECSEL4_GPIO156_S 16 +#define GPIO_GPECSEL4_GPIO156_M 0xF0000 // GPIO156 Master CPU Select +#define GPIO_GPECSEL4_GPIO157_S 20 +#define GPIO_GPECSEL4_GPIO157_M 0xF00000 // GPIO157 Master CPU Select +#define GPIO_GPECSEL4_GPIO158_S 24 +#define GPIO_GPECSEL4_GPIO158_M 0xF000000 // GPIO158 Master CPU Select +#define GPIO_GPECSEL4_GPIO159_S 28 +#define GPIO_GPECSEL4_GPIO159_M 0xF0000000 // GPIO159 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPELOCK register +// +//***************************************************************************** +#define GPIO_GPELOCK_GPIO128 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO129 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO130 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO131 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO132 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO133 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO134 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO135 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO136 0x100 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO137 0x200 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO138 0x400 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO139 0x800 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO140 0x1000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO141 0x2000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO142 0x4000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO143 0x8000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO144 0x10000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO145 0x20000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO146 0x40000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO147 0x80000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO148 0x100000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO149 0x200000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO150 0x400000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO151 0x800000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO152 0x1000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO153 0x2000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO154 0x4000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO155 0x8000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO156 0x10000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO157 0x20000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO158 0x40000000 // Configuration Lock bit for this + // pin +#define GPIO_GPELOCK_GPIO159 0x80000000 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECR register +// +//***************************************************************************** +#define GPIO_GPECR_GPIO128 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO129 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO130 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO131 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO132 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO133 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO134 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO135 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO136 0x100 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO137 0x200 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO138 0x400 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO139 0x800 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO140 0x1000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO141 0x2000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO142 0x4000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO143 0x8000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO144 0x10000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO145 0x20000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO146 0x40000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO147 0x80000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO148 0x100000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO149 0x200000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO150 0x400000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO151 0x800000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO152 0x1000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO153 0x2000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO154 0x4000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO155 0x8000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO156 0x10000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO157 0x20000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO158 0x40000000 // Configuration lock commit bit + // for this pin +#define GPIO_GPECR_GPIO159 0x80000000 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFCTRL register +// +//***************************************************************************** +#define GPIO_GPFCTRL_QUALPRD0_S 0 +#define GPIO_GPFCTRL_QUALPRD0_M 0xFF // Qualification sampling period + // for GPIO160 to GPIO167 +#define GPIO_GPFCTRL_QUALPRD1_S 8 +#define GPIO_GPFCTRL_QUALPRD1_M 0xFF00 // Qualification sampling period + // for GPIO168 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFQSEL1 register +// +//***************************************************************************** +#define GPIO_GPFQSEL1_GPIO160_S 0 +#define GPIO_GPFQSEL1_GPIO160_M 0x3 // Select input qualification type + // for GPIO160 +#define GPIO_GPFQSEL1_GPIO161_S 2 +#define GPIO_GPFQSEL1_GPIO161_M 0xC // Select input qualification type + // for GPIO161 +#define GPIO_GPFQSEL1_GPIO162_S 4 +#define GPIO_GPFQSEL1_GPIO162_M 0x30 // Select input qualification type + // for GPIO162 +#define GPIO_GPFQSEL1_GPIO163_S 6 +#define GPIO_GPFQSEL1_GPIO163_M 0xC0 // Select input qualification type + // for GPIO163 +#define GPIO_GPFQSEL1_GPIO164_S 8 +#define GPIO_GPFQSEL1_GPIO164_M 0x300 // Select input qualification type + // for GPIO164 +#define GPIO_GPFQSEL1_GPIO165_S 10 +#define GPIO_GPFQSEL1_GPIO165_M 0xC00 // Select input qualification type + // for GPIO165 +#define GPIO_GPFQSEL1_GPIO166_S 12 +#define GPIO_GPFQSEL1_GPIO166_M 0x3000 // Select input qualification type + // for GPIO166 +#define GPIO_GPFQSEL1_GPIO167_S 14 +#define GPIO_GPFQSEL1_GPIO167_M 0xC000 // Select input qualification type + // for GPIO167 +#define GPIO_GPFQSEL1_GPIO168_S 16 +#define GPIO_GPFQSEL1_GPIO168_M 0x30000 // Select input qualification type + // for GPIO168 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFMUX1 register +// +//***************************************************************************** +#define GPIO_GPFMUX1_GPIO160_S 0 +#define GPIO_GPFMUX1_GPIO160_M 0x3 // Defines pin-muxing selection + // for GPIO160 +#define GPIO_GPFMUX1_GPIO161_S 2 +#define GPIO_GPFMUX1_GPIO161_M 0xC // Defines pin-muxing selection + // for GPIO161 +#define GPIO_GPFMUX1_GPIO162_S 4 +#define GPIO_GPFMUX1_GPIO162_M 0x30 // Defines pin-muxing selection + // for GPIO162 +#define GPIO_GPFMUX1_GPIO163_S 6 +#define GPIO_GPFMUX1_GPIO163_M 0xC0 // Defines pin-muxing selection + // for GPIO163 +#define GPIO_GPFMUX1_GPIO164_S 8 +#define GPIO_GPFMUX1_GPIO164_M 0x300 // Defines pin-muxing selection + // for GPIO164 +#define GPIO_GPFMUX1_GPIO165_S 10 +#define GPIO_GPFMUX1_GPIO165_M 0xC00 // Defines pin-muxing selection + // for GPIO165 +#define GPIO_GPFMUX1_GPIO166_S 12 +#define GPIO_GPFMUX1_GPIO166_M 0x3000 // Defines pin-muxing selection + // for GPIO166 +#define GPIO_GPFMUX1_GPIO167_S 14 +#define GPIO_GPFMUX1_GPIO167_M 0xC000 // Defines pin-muxing selection + // for GPIO167 +#define GPIO_GPFMUX1_GPIO168_S 16 +#define GPIO_GPFMUX1_GPIO168_M 0x30000 // Defines pin-muxing selection + // for GPIO168 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFDIR register +// +//***************************************************************************** +#define GPIO_GPFDIR_GPIO160 0x1 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO161 0x2 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO162 0x4 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO163 0x8 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO164 0x10 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO165 0x20 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO166 0x40 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO167 0x80 // Defines direction for this pin + // in GPIO mode +#define GPIO_GPFDIR_GPIO168 0x100 // Defines direction for this pin + // in GPIO mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFPUD register +// +//***************************************************************************** +#define GPIO_GPFPUD_GPIO160 0x1 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO161 0x2 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO162 0x4 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO163 0x8 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO164 0x10 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO165 0x20 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO166 0x40 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO167 0x80 // Pull-Up Disable control for + // this pin +#define GPIO_GPFPUD_GPIO168 0x100 // Pull-Up Disable control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFINV register +// +//***************************************************************************** +#define GPIO_GPFINV_GPIO160 0x1 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO161 0x2 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO162 0x4 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO163 0x8 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO164 0x10 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO165 0x20 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO166 0x40 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO167 0x80 // Input inversion control for + // this pin +#define GPIO_GPFINV_GPIO168 0x100 // Input inversion control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFODR register +// +//***************************************************************************** +#define GPIO_GPFODR_GPIO160 0x1 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO161 0x2 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO162 0x4 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO163 0x8 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO164 0x10 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO165 0x20 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO166 0x40 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO167 0x80 // Outpout Open-Drain control for + // this pin +#define GPIO_GPFODR_GPIO168 0x100 // Outpout Open-Drain control for + // this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFGMUX1 register +// +//***************************************************************************** +#define GPIO_GPFGMUX1_GPIO160_S 0 +#define GPIO_GPFGMUX1_GPIO160_M 0x3 // Defines pin-muxing selection + // for GPIO160 +#define GPIO_GPFGMUX1_GPIO161_S 2 +#define GPIO_GPFGMUX1_GPIO161_M 0xC // Defines pin-muxing selection + // for GPIO161 +#define GPIO_GPFGMUX1_GPIO162_S 4 +#define GPIO_GPFGMUX1_GPIO162_M 0x30 // Defines pin-muxing selection + // for GPIO162 +#define GPIO_GPFGMUX1_GPIO163_S 6 +#define GPIO_GPFGMUX1_GPIO163_M 0xC0 // Defines pin-muxing selection + // for GPIO163 +#define GPIO_GPFGMUX1_GPIO164_S 8 +#define GPIO_GPFGMUX1_GPIO164_M 0x300 // Defines pin-muxing selection + // for GPIO164 +#define GPIO_GPFGMUX1_GPIO165_S 10 +#define GPIO_GPFGMUX1_GPIO165_M 0xC00 // Defines pin-muxing selection + // for GPIO165 +#define GPIO_GPFGMUX1_GPIO166_S 12 +#define GPIO_GPFGMUX1_GPIO166_M 0x3000 // Defines pin-muxing selection + // for GPIO166 +#define GPIO_GPFGMUX1_GPIO167_S 14 +#define GPIO_GPFGMUX1_GPIO167_M 0xC000 // Defines pin-muxing selection + // for GPIO167 +#define GPIO_GPFGMUX1_GPIO168_S 16 +#define GPIO_GPFGMUX1_GPIO168_M 0x30000 // Defines pin-muxing selection + // for GPIO168 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFCSEL1 register +// +//***************************************************************************** +#define GPIO_GPFCSEL1_GPIO160_S 0 +#define GPIO_GPFCSEL1_GPIO160_M 0xF // GPIO160 Master CPU Select +#define GPIO_GPFCSEL1_GPIO161_S 4 +#define GPIO_GPFCSEL1_GPIO161_M 0xF0 // GPIO161 Master CPU Select +#define GPIO_GPFCSEL1_GPIO162_S 8 +#define GPIO_GPFCSEL1_GPIO162_M 0xF00 // GPIO162 Master CPU Select +#define GPIO_GPFCSEL1_GPIO163_S 12 +#define GPIO_GPFCSEL1_GPIO163_M 0xF000 // GPIO163 Master CPU Select +#define GPIO_GPFCSEL1_GPIO164_S 16 +#define GPIO_GPFCSEL1_GPIO164_M 0xF0000 // GPIO164 Master CPU Select +#define GPIO_GPFCSEL1_GPIO165_S 20 +#define GPIO_GPFCSEL1_GPIO165_M 0xF00000 // GPIO165 Master CPU Select +#define GPIO_GPFCSEL1_GPIO166_S 24 +#define GPIO_GPFCSEL1_GPIO166_M 0xF000000 // GPIO166 Master CPU Select +#define GPIO_GPFCSEL1_GPIO167_S 28 +#define GPIO_GPFCSEL1_GPIO167_M 0xF0000000 // GPIO167 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFCSEL2 register +// +//***************************************************************************** +#define GPIO_GPFCSEL2_GPIO168_S 0 +#define GPIO_GPFCSEL2_GPIO168_M 0xF // GPIO168 Master CPU Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFLOCK register +// +//***************************************************************************** +#define GPIO_GPFLOCK_GPIO160 0x1 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO161 0x2 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO162 0x4 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO163 0x8 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO164 0x10 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO165 0x20 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO166 0x40 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO167 0x80 // Configuration Lock bit for this + // pin +#define GPIO_GPFLOCK_GPIO168 0x100 // Configuration Lock bit for this + // pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFCR register +// +//***************************************************************************** +#define GPIO_GPFCR_GPIO160 0x1 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO161 0x2 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO162 0x4 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO163 0x8 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO164 0x10 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO165 0x20 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO166 0x40 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO167 0x80 // Configuration lock commit bit + // for this pin +#define GPIO_GPFCR_GPIO168 0x100 // Configuration lock commit bit + // for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPADAT register +// +//***************************************************************************** +#define GPIO_GPADAT_GPIO0 0x1 // Data Register for this pin +#define GPIO_GPADAT_GPIO1 0x2 // Data Register for this pin +#define GPIO_GPADAT_GPIO2 0x4 // Data Register for this pin +#define GPIO_GPADAT_GPIO3 0x8 // Data Register for this pin +#define GPIO_GPADAT_GPIO4 0x10 // Data Register for this pin +#define GPIO_GPADAT_GPIO5 0x20 // Data Register for this pin +#define GPIO_GPADAT_GPIO6 0x40 // Data Register for this pin +#define GPIO_GPADAT_GPIO7 0x80 // Data Register for this pin +#define GPIO_GPADAT_GPIO8 0x100 // Data Register for this pin +#define GPIO_GPADAT_GPIO9 0x200 // Data Register for this pin +#define GPIO_GPADAT_GPIO10 0x400 // Data Register for this pin +#define GPIO_GPADAT_GPIO11 0x800 // Data Register for this pin +#define GPIO_GPADAT_GPIO12 0x1000 // Data Register for this pin +#define GPIO_GPADAT_GPIO13 0x2000 // Data Register for this pin +#define GPIO_GPADAT_GPIO14 0x4000 // Data Register for this pin +#define GPIO_GPADAT_GPIO15 0x8000 // Data Register for this pin +#define GPIO_GPADAT_GPIO16 0x10000 // Data Register for this pin +#define GPIO_GPADAT_GPIO17 0x20000 // Data Register for this pin +#define GPIO_GPADAT_GPIO18 0x40000 // Data Register for this pin +#define GPIO_GPADAT_GPIO19 0x80000 // Data Register for this pin +#define GPIO_GPADAT_GPIO20 0x100000 // Data Register for this pin +#define GPIO_GPADAT_GPIO21 0x200000 // Data Register for this pin +#define GPIO_GPADAT_GPIO22 0x400000 // Data Register for this pin +#define GPIO_GPADAT_GPIO23 0x800000 // Data Register for this pin +#define GPIO_GPADAT_GPIO24 0x1000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO25 0x2000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO26 0x4000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO27 0x8000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO28 0x10000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO29 0x20000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO30 0x40000000 // Data Register for this pin +#define GPIO_GPADAT_GPIO31 0x80000000 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPASET register +// +//***************************************************************************** +#define GPIO_GPASET_GPIO0 0x1 // Output Set bit for this pin +#define GPIO_GPASET_GPIO1 0x2 // Output Set bit for this pin +#define GPIO_GPASET_GPIO2 0x4 // Output Set bit for this pin +#define GPIO_GPASET_GPIO3 0x8 // Output Set bit for this pin +#define GPIO_GPASET_GPIO4 0x10 // Output Set bit for this pin +#define GPIO_GPASET_GPIO5 0x20 // Output Set bit for this pin +#define GPIO_GPASET_GPIO6 0x40 // Output Set bit for this pin +#define GPIO_GPASET_GPIO7 0x80 // Output Set bit for this pin +#define GPIO_GPASET_GPIO8 0x100 // Output Set bit for this pin +#define GPIO_GPASET_GPIO9 0x200 // Output Set bit for this pin +#define GPIO_GPASET_GPIO10 0x400 // Output Set bit for this pin +#define GPIO_GPASET_GPIO11 0x800 // Output Set bit for this pin +#define GPIO_GPASET_GPIO12 0x1000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO13 0x2000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO14 0x4000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO15 0x8000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO16 0x10000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO17 0x20000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO18 0x40000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO19 0x80000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO20 0x100000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO21 0x200000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO22 0x400000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO23 0x800000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO24 0x1000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO25 0x2000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO26 0x4000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO27 0x8000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO28 0x10000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO29 0x20000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO30 0x40000000 // Output Set bit for this pin +#define GPIO_GPASET_GPIO31 0x80000000 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPACLEAR register +// +//***************************************************************************** +#define GPIO_GPACLEAR_GPIO0 0x1 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO1 0x2 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO2 0x4 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO3 0x8 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO4 0x10 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO5 0x20 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO6 0x40 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO7 0x80 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO8 0x100 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO9 0x200 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO10 0x400 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO11 0x800 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO12 0x1000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO13 0x2000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO14 0x4000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO15 0x8000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO16 0x10000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO17 0x20000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO18 0x40000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO19 0x80000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO20 0x100000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO21 0x200000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO22 0x400000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO23 0x800000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO24 0x1000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO25 0x2000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO26 0x4000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO27 0x8000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO28 0x10000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO29 0x20000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO30 0x40000000 // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO31 0x80000000 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPATOGGLE register +// +//***************************************************************************** +#define GPIO_GPATOGGLE_GPIO0 0x1 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO1 0x2 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO2 0x4 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO3 0x8 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO4 0x10 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO5 0x20 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO6 0x40 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO7 0x80 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO8 0x100 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO9 0x200 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO10 0x400 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO11 0x800 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO12 0x1000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO13 0x2000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO14 0x4000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO15 0x8000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO16 0x10000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO17 0x20000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO18 0x40000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO19 0x80000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO20 0x100000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO21 0x200000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO22 0x400000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO23 0x800000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO24 0x1000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO25 0x2000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO26 0x4000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO27 0x8000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO28 0x10000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO29 0x20000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO30 0x40000000 // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO31 0x80000000 // Output Toggle bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBDAT register +// +//***************************************************************************** +#define GPIO_GPBDAT_GPIO32 0x1 // Data Register for this pin +#define GPIO_GPBDAT_GPIO33 0x2 // Data Register for this pin +#define GPIO_GPBDAT_GPIO34 0x4 // Data Register for this pin +#define GPIO_GPBDAT_GPIO35 0x8 // Data Register for this pin +#define GPIO_GPBDAT_GPIO36 0x10 // Data Register for this pin +#define GPIO_GPBDAT_GPIO37 0x20 // Data Register for this pin +#define GPIO_GPBDAT_GPIO38 0x40 // Data Register for this pin +#define GPIO_GPBDAT_GPIO39 0x80 // Data Register for this pin +#define GPIO_GPBDAT_GPIO40 0x100 // Data Register for this pin +#define GPIO_GPBDAT_GPIO41 0x200 // Data Register for this pin +#define GPIO_GPBDAT_GPIO42 0x400 // Data Register for this pin +#define GPIO_GPBDAT_GPIO43 0x800 // Data Register for this pin +#define GPIO_GPBDAT_GPIO44 0x1000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO45 0x2000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO46 0x4000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO47 0x8000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO48 0x10000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO49 0x20000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO50 0x40000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO51 0x80000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO52 0x100000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO53 0x200000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO54 0x400000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO55 0x800000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO56 0x1000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO57 0x2000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO58 0x4000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO59 0x8000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO60 0x10000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO61 0x20000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO62 0x40000000 // Data Register for this pin +#define GPIO_GPBDAT_GPIO63 0x80000000 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBSET register +// +//***************************************************************************** +#define GPIO_GPBSET_GPIO32 0x1 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO33 0x2 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO34 0x4 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO35 0x8 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO36 0x10 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO37 0x20 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO38 0x40 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO39 0x80 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO40 0x100 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO41 0x200 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO42 0x400 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO43 0x800 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO44 0x1000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO45 0x2000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO46 0x4000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO47 0x8000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO48 0x10000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO49 0x20000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO50 0x40000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO51 0x80000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO52 0x100000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO53 0x200000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO54 0x400000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO55 0x800000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO56 0x1000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO57 0x2000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO58 0x4000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO59 0x8000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO60 0x10000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO61 0x20000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO62 0x40000000 // Output Set bit for this pin +#define GPIO_GPBSET_GPIO63 0x80000000 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBCLEAR register +// +//***************************************************************************** +#define GPIO_GPBCLEAR_GPIO32 0x1 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO33 0x2 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO34 0x4 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO35 0x8 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO36 0x10 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO37 0x20 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO38 0x40 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO39 0x80 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO40 0x100 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO41 0x200 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO42 0x400 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO43 0x800 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO44 0x1000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO45 0x2000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO46 0x4000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO47 0x8000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO48 0x10000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO49 0x20000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO50 0x40000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO51 0x80000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO52 0x100000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO53 0x200000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO54 0x400000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO55 0x800000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO56 0x1000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO57 0x2000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO58 0x4000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO59 0x8000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO60 0x10000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO61 0x20000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO62 0x40000000 // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO63 0x80000000 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPBTOGGLE register +// +//***************************************************************************** +#define GPIO_GPBTOGGLE_GPIO32 0x1 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO33 0x2 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO34 0x4 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO35 0x8 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO36 0x10 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO37 0x20 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO38 0x40 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO39 0x80 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO40 0x100 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO41 0x200 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO42 0x400 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO43 0x800 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO44 0x1000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO45 0x2000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO46 0x4000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO47 0x8000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO48 0x10000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO49 0x20000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO50 0x40000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO51 0x80000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO52 0x100000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO53 0x200000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO54 0x400000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO55 0x800000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO56 0x1000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO57 0x2000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO58 0x4000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO59 0x8000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO60 0x10000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO61 0x20000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO62 0x40000000 // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO63 0x80000000 // Output Toggle bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCDAT register +// +//***************************************************************************** +#define GPIO_GPCDAT_GPIO64 0x1 // Data Register for this pin +#define GPIO_GPCDAT_GPIO65 0x2 // Data Register for this pin +#define GPIO_GPCDAT_GPIO66 0x4 // Data Register for this pin +#define GPIO_GPCDAT_GPIO67 0x8 // Data Register for this pin +#define GPIO_GPCDAT_GPIO68 0x10 // Data Register for this pin +#define GPIO_GPCDAT_GPIO69 0x20 // Data Register for this pin +#define GPIO_GPCDAT_GPIO70 0x40 // Data Register for this pin +#define GPIO_GPCDAT_GPIO71 0x80 // Data Register for this pin +#define GPIO_GPCDAT_GPIO72 0x100 // Data Register for this pin +#define GPIO_GPCDAT_GPIO73 0x200 // Data Register for this pin +#define GPIO_GPCDAT_GPIO74 0x400 // Data Register for this pin +#define GPIO_GPCDAT_GPIO75 0x800 // Data Register for this pin +#define GPIO_GPCDAT_GPIO76 0x1000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO77 0x2000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO78 0x4000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO79 0x8000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO80 0x10000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO81 0x20000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO82 0x40000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO83 0x80000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO84 0x100000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO85 0x200000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO86 0x400000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO87 0x800000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO88 0x1000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO89 0x2000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO90 0x4000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO91 0x8000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO92 0x10000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO93 0x20000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO94 0x40000000 // Data Register for this pin +#define GPIO_GPCDAT_GPIO95 0x80000000 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCSET register +// +//***************************************************************************** +#define GPIO_GPCSET_GPIO64 0x1 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO65 0x2 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO66 0x4 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO67 0x8 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO68 0x10 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO69 0x20 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO70 0x40 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO71 0x80 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO72 0x100 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO73 0x200 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO74 0x400 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO75 0x800 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO76 0x1000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO77 0x2000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO78 0x4000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO79 0x8000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO80 0x10000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO81 0x20000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO82 0x40000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO83 0x80000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO84 0x100000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO85 0x200000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO86 0x400000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO87 0x800000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO88 0x1000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO89 0x2000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO90 0x4000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO91 0x8000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO92 0x10000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO93 0x20000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO94 0x40000000 // Output Set bit for this pin +#define GPIO_GPCSET_GPIO95 0x80000000 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCCLEAR register +// +//***************************************************************************** +#define GPIO_GPCCLEAR_GPIO64 0x1 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO65 0x2 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO66 0x4 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO67 0x8 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO68 0x10 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO69 0x20 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO70 0x40 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO71 0x80 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO72 0x100 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO73 0x200 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO74 0x400 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO75 0x800 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO76 0x1000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO77 0x2000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO78 0x4000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO79 0x8000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO80 0x10000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO81 0x20000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO82 0x40000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO83 0x80000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO84 0x100000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO85 0x200000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO86 0x400000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO87 0x800000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO88 0x1000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO89 0x2000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO90 0x4000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO91 0x8000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO92 0x10000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO93 0x20000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO94 0x40000000 // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO95 0x80000000 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPCTOGGLE register +// +//***************************************************************************** +#define GPIO_GPCTOGGLE_GPIO64 0x1 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO65 0x2 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO66 0x4 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO67 0x8 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO68 0x10 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO69 0x20 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO70 0x40 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO71 0x80 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO72 0x100 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO73 0x200 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO74 0x400 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO75 0x800 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO76 0x1000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO77 0x2000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO78 0x4000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO79 0x8000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO80 0x10000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO81 0x20000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO82 0x40000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO83 0x80000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO84 0x100000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO85 0x200000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO86 0x400000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO87 0x800000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO88 0x1000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO89 0x2000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO90 0x4000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO91 0x8000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO92 0x10000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO93 0x20000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO94 0x40000000 // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO95 0x80000000 // Output Toggle bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDDAT register +// +//***************************************************************************** +#define GPIO_GPDDAT_GPIO96 0x1 // Data Register for this pin +#define GPIO_GPDDAT_GPIO97 0x2 // Data Register for this pin +#define GPIO_GPDDAT_GPIO98 0x4 // Data Register for this pin +#define GPIO_GPDDAT_GPIO99 0x8 // Data Register for this pin +#define GPIO_GPDDAT_GPIO100 0x10 // Data Register for this pin +#define GPIO_GPDDAT_GPIO101 0x20 // Data Register for this pin +#define GPIO_GPDDAT_GPIO102 0x40 // Data Register for this pin +#define GPIO_GPDDAT_GPIO103 0x80 // Data Register for this pin +#define GPIO_GPDDAT_GPIO104 0x100 // Data Register for this pin +#define GPIO_GPDDAT_GPIO105 0x200 // Data Register for this pin +#define GPIO_GPDDAT_GPIO106 0x400 // Data Register for this pin +#define GPIO_GPDDAT_GPIO107 0x800 // Data Register for this pin +#define GPIO_GPDDAT_GPIO108 0x1000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO109 0x2000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO110 0x4000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO111 0x8000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO112 0x10000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO113 0x20000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO114 0x40000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO115 0x80000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO116 0x100000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO117 0x200000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO118 0x400000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO119 0x800000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO120 0x1000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO121 0x2000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO122 0x4000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO123 0x8000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO124 0x10000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO125 0x20000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO126 0x40000000 // Data Register for this pin +#define GPIO_GPDDAT_GPIO127 0x80000000 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDSET register +// +//***************************************************************************** +#define GPIO_GPDSET_GPIO96 0x1 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO97 0x2 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO98 0x4 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO99 0x8 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO100 0x10 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO101 0x20 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO102 0x40 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO103 0x80 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO104 0x100 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO105 0x200 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO106 0x400 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO107 0x800 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO108 0x1000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO109 0x2000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO110 0x4000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO111 0x8000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO112 0x10000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO113 0x20000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO114 0x40000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO115 0x80000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO116 0x100000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO117 0x200000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO118 0x400000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO119 0x800000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO120 0x1000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO121 0x2000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO122 0x4000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO123 0x8000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO124 0x10000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO125 0x20000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO126 0x40000000 // Output Set bit for this pin +#define GPIO_GPDSET_GPIO127 0x80000000 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDCLEAR register +// +//***************************************************************************** +#define GPIO_GPDCLEAR_GPIO96 0x1 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO97 0x2 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO98 0x4 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO99 0x8 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO100 0x10 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO101 0x20 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO102 0x40 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO103 0x80 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO104 0x100 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO105 0x200 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO106 0x400 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO107 0x800 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO108 0x1000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO109 0x2000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO110 0x4000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO111 0x8000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO112 0x10000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO113 0x20000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO114 0x40000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO115 0x80000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO116 0x100000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO117 0x200000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO118 0x400000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO119 0x800000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO120 0x1000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO121 0x2000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO122 0x4000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO123 0x8000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO124 0x10000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO125 0x20000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO126 0x40000000 // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO127 0x80000000 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPDTOGGLE register +// +//***************************************************************************** +#define GPIO_GPDTOGGLE_GPIO96 0x1 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO97 0x2 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO98 0x4 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO99 0x8 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO100 0x10 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO101 0x20 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO102 0x40 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO103 0x80 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO104 0x100 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO105 0x200 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO106 0x400 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO107 0x800 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO108 0x1000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO109 0x2000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO110 0x4000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO111 0x8000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO112 0x10000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO113 0x20000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO114 0x40000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO115 0x80000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO116 0x100000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO117 0x200000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO118 0x400000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO119 0x800000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO120 0x1000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO121 0x2000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO122 0x4000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO123 0x8000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO124 0x10000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO125 0x20000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO126 0x40000000 // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO127 0x80000000 // Output Toggle bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPEDAT register +// +//***************************************************************************** +#define GPIO_GPEDAT_GPIO128 0x1 // Data Register for this pin +#define GPIO_GPEDAT_GPIO129 0x2 // Data Register for this pin +#define GPIO_GPEDAT_GPIO130 0x4 // Data Register for this pin +#define GPIO_GPEDAT_GPIO131 0x8 // Data Register for this pin +#define GPIO_GPEDAT_GPIO132 0x10 // Data Register for this pin +#define GPIO_GPEDAT_GPIO133 0x20 // Data Register for this pin +#define GPIO_GPEDAT_GPIO134 0x40 // Data Register for this pin +#define GPIO_GPEDAT_GPIO135 0x80 // Data Register for this pin +#define GPIO_GPEDAT_GPIO136 0x100 // Data Register for this pin +#define GPIO_GPEDAT_GPIO137 0x200 // Data Register for this pin +#define GPIO_GPEDAT_GPIO138 0x400 // Data Register for this pin +#define GPIO_GPEDAT_GPIO139 0x800 // Data Register for this pin +#define GPIO_GPEDAT_GPIO140 0x1000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO141 0x2000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO142 0x4000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO143 0x8000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO144 0x10000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO145 0x20000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO146 0x40000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO147 0x80000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO148 0x100000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO149 0x200000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO150 0x400000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO151 0x800000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO152 0x1000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO153 0x2000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO154 0x4000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO155 0x8000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO156 0x10000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO157 0x20000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO158 0x40000000 // Data Register for this pin +#define GPIO_GPEDAT_GPIO159 0x80000000 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPESET register +// +//***************************************************************************** +#define GPIO_GPESET_GPIO128 0x1 // Output Set bit for this pin +#define GPIO_GPESET_GPIO129 0x2 // Output Set bit for this pin +#define GPIO_GPESET_GPIO130 0x4 // Output Set bit for this pin +#define GPIO_GPESET_GPIO131 0x8 // Output Set bit for this pin +#define GPIO_GPESET_GPIO132 0x10 // Output Set bit for this pin +#define GPIO_GPESET_GPIO133 0x20 // Output Set bit for this pin +#define GPIO_GPESET_GPIO134 0x40 // Output Set bit for this pin +#define GPIO_GPESET_GPIO135 0x80 // Output Set bit for this pin +#define GPIO_GPESET_GPIO136 0x100 // Output Set bit for this pin +#define GPIO_GPESET_GPIO137 0x200 // Output Set bit for this pin +#define GPIO_GPESET_GPIO138 0x400 // Output Set bit for this pin +#define GPIO_GPESET_GPIO139 0x800 // Output Set bit for this pin +#define GPIO_GPESET_GPIO140 0x1000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO141 0x2000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO142 0x4000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO143 0x8000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO144 0x10000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO145 0x20000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO146 0x40000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO147 0x80000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO148 0x100000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO149 0x200000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO150 0x400000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO151 0x800000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO152 0x1000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO153 0x2000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO154 0x4000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO155 0x8000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO156 0x10000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO157 0x20000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO158 0x40000000 // Output Set bit for this pin +#define GPIO_GPESET_GPIO159 0x80000000 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPECLEAR register +// +//***************************************************************************** +#define GPIO_GPECLEAR_GPIO128 0x1 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO129 0x2 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO130 0x4 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO131 0x8 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO132 0x10 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO133 0x20 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO134 0x40 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO135 0x80 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO136 0x100 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO137 0x200 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO138 0x400 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO139 0x800 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO140 0x1000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO141 0x2000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO142 0x4000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO143 0x8000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO144 0x10000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO145 0x20000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO146 0x40000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO147 0x80000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO148 0x100000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO149 0x200000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO150 0x400000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO151 0x800000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO152 0x1000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO153 0x2000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO154 0x4000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO155 0x8000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO156 0x10000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO157 0x20000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO158 0x40000000 // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO159 0x80000000 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPETOGGLE register +// +//***************************************************************************** +#define GPIO_GPETOGGLE_GPIO128 0x1 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO129 0x2 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO130 0x4 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO131 0x8 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO132 0x10 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO133 0x20 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO134 0x40 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO135 0x80 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO136 0x100 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO137 0x200 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO138 0x400 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO139 0x800 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO140 0x1000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO141 0x2000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO142 0x4000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO143 0x8000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO144 0x10000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO145 0x20000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO146 0x40000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO147 0x80000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO148 0x100000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO149 0x200000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO150 0x400000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO151 0x800000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO152 0x1000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO153 0x2000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO154 0x4000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO155 0x8000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO156 0x10000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO157 0x20000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO158 0x40000000 // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO159 0x80000000 // Output Toggle bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFDAT register +// +//***************************************************************************** +#define GPIO_GPFDAT_GPIO160 0x1 // Data Register for this pin +#define GPIO_GPFDAT_GPIO161 0x2 // Data Register for this pin +#define GPIO_GPFDAT_GPIO162 0x4 // Data Register for this pin +#define GPIO_GPFDAT_GPIO163 0x8 // Data Register for this pin +#define GPIO_GPFDAT_GPIO164 0x10 // Data Register for this pin +#define GPIO_GPFDAT_GPIO165 0x20 // Data Register for this pin +#define GPIO_GPFDAT_GPIO166 0x40 // Data Register for this pin +#define GPIO_GPFDAT_GPIO167 0x80 // Data Register for this pin +#define GPIO_GPFDAT_GPIO168 0x100 // Data Register for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFSET register +// +//***************************************************************************** +#define GPIO_GPFSET_GPIO160 0x1 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO161 0x2 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO162 0x4 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO163 0x8 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO164 0x10 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO165 0x20 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO166 0x40 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO167 0x80 // Output Set bit for this pin +#define GPIO_GPFSET_GPIO168 0x100 // Output Set bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFCLEAR register +// +//***************************************************************************** +#define GPIO_GPFCLEAR_GPIO160 0x1 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO161 0x2 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO162 0x4 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO163 0x8 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO164 0x10 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO165 0x20 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO166 0x40 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO167 0x80 // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO168 0x100 // Output Clear bit for this pin + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPFTOGGLE register +// +//***************************************************************************** +#define GPIO_GPFTOGGLE_GPIO160 0x1 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO161 0x2 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO162 0x4 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO163 0x8 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO164 0x10 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO165 0x20 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO166 0x40 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO167 0x80 // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO168 0x100 // Output Toggle bit for this pin +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_i2c.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_i2c.h new file mode 100644 index 00000000000..57a045c8f21 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_i2c.h @@ -0,0 +1,244 @@ +//########################################################################### +// +// FILE: hw_i2c.h +// +// TITLE: Definitions for the C28x I2C registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the I2C register offsets +// +//***************************************************************************** +#define I2C_O_OAR 0x0 // I2C Own address +#define I2C_O_IER 0x1 // I2C Interrupt Enable +#define I2C_O_STR 0x2 // I2C Status +#define I2C_O_CLKL 0x3 // I2C Clock low-time divider +#define I2C_O_CLKH 0x4 // I2C Clock high-time divider +#define I2C_O_CNT 0x5 // I2C Data count +#define I2C_O_DRR 0x6 // I2C Data receive +#define I2C_O_SAR 0x7 // I2C Slave address +#define I2C_O_DXR 0x8 // I2C Data Transmit +#define I2C_O_MDR 0x9 // I2C Mode +#define I2C_O_ISRC 0xA // I2C Interrupt Source +#define I2C_O_EMDR 0xB // I2C Extended Mode +#define I2C_O_PSC 0xC // I2C Prescaler +#define I2C_O_FFTX 0x20 // I2C FIFO Transmit +#define I2C_O_FFRX 0x21 // I2C FIFO Receive + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2COAR register +// +//***************************************************************************** +#define I2C_OAR_OAR_S 0 +#define I2C_OAR_OAR_M 0x3FF // I2C Own address + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CIER register +// +//***************************************************************************** +#define I2C_IER_ARBL 0x1 // Arbitration-lost interrupt + // enable +#define I2C_IER_NACK 0x2 // No-acknowledgment interrupt + // enable +#define I2C_IER_ARDY 0x4 // Register-access-ready interrupt + // enable +#define I2C_IER_RRDY 0x8 // Receive-data-ready interrupt + // enable +#define I2C_IER_XRDY 0x10 // Transmit-data-ready interrupt + // enable +#define I2C_IER_SCD 0x20 // Stop condition detected + // interrupt enable +#define I2C_IER_AAS 0x40 // Addressed as slave interrupt + // enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CSTR register +// +//***************************************************************************** +#define I2C_STR_ARBL 0x1 // Arbitration-lost interrupt flag + // bit +#define I2C_STR_NACK 0x2 // No-acknowledgment interrupt + // flag bit. +#define I2C_STR_ARDY 0x4 // Register-access-ready interrupt + // flag bit +#define I2C_STR_RRDY 0x8 // Receive-data-ready interrupt + // flag bit. +#define I2C_STR_XRDY 0x10 // Transmit-data-ready interrupt + // flag bit. +#define I2C_STR_SCD 0x20 // Stop condition detected bit. +#define I2C_STR_AD0 0x100 // Address 0 bits +#define I2C_STR_AAS 0x200 // Addressed-as-slave bit +#define I2C_STR_XSMT 0x400 // Transmit shift register empty + // bit. +#define I2C_STR_RSFULL 0x800 // Receive shift register full + // bit. +#define I2C_STR_BB 0x1000 // Bus busy bit. +#define I2C_STR_NACKSNT 0x2000 // NACK sent bit. +#define I2C_STR_SDIR 0x4000 // Slave direction bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CCLKL register +// +//***************************************************************************** +#define I2C_CLKL_I2CCLKL_S 0 +#define I2C_CLKL_I2CCLKL_M 0xFFFF // Clock low-time divide-down + // value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CCLKH register +// +//***************************************************************************** +#define I2C_CLKH_I2CCLKH_S 0 +#define I2C_CLKH_I2CCLKH_M 0xFFFF // Clock high-time divide-down + // value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CCNT register +// +//***************************************************************************** +#define I2C_CNT_I2CCNT_S 0 +#define I2C_CNT_I2CCNT_M 0xFFFF // Data count value. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CDRR register +// +//***************************************************************************** +#define I2C_DRR_DATA_S 0 +#define I2C_DRR_DATA_M 0xFF // Receive data + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CSAR register +// +//***************************************************************************** +#define I2C_SAR_SAR_S 0 +#define I2C_SAR_SAR_M 0x3FF // Slave Address + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CDXR register +// +//***************************************************************************** +#define I2C_DXR_DATA_S 0 +#define I2C_DXR_DATA_M 0xFF // Transmit data + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CMDR register +// +//***************************************************************************** +#define I2C_MDR_BC_S 0 +#define I2C_MDR_BC_M 0x7 // Bit count bits. +#define I2C_MDR_FDF 0x8 // Free Data Format +#define I2C_MDR_STB 0x10 // START Byte Mode +#define I2C_MDR_IRS 0x20 // I2C Module Reset +#define I2C_MDR_DLB 0x40 // Digital Loopback Mode +#define I2C_MDR_RM 0x80 // Repeat Mode +#define I2C_MDR_XA 0x100 // Expanded Address Mode +#define I2C_MDR_TRX 0x200 // Transmitter Mode +#define I2C_MDR_MST 0x400 // Master Mode +#define I2C_MDR_STP 0x800 // STOP Condition +#define I2C_MDR_STT 0x2000 // START condition bit +#define I2C_MDR_FREE 0x4000 // Debug Action +#define I2C_MDR_NACKMOD 0x8000 // NACK mode bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CISRC register +// +//***************************************************************************** +#define I2C_ISRC_INTCODE_S 0 +#define I2C_ISRC_INTCODE_M 0x7 // Interrupt code bits. + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CEMDR register +// +//***************************************************************************** +#define I2C_EMDR_BC 0x1 // Backwards compatibility mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CPSC register +// +//***************************************************************************** +#define I2C_PSC_IPSC_S 0 +#define I2C_PSC_IPSC_M 0xFF // I2C Prescaler Divide Down + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CFFTX register +// +//***************************************************************************** +#define I2C_FFTX_TXFFIL_S 0 +#define I2C_FFTX_TXFFIL_M 0x1F // Transmit FIFO Interrupt Level +#define I2C_FFTX_TXFFIENA 0x20 // Transmit FIFO Interrupt Enable +#define I2C_FFTX_TXFFINTCLR 0x40 // Transmit FIFO Interrupt Flag + // Clear +#define I2C_FFTX_TXFFINT 0x80 // Transmit FIFO Interrupt Flag +#define I2C_FFTX_TXFFST_S 8 +#define I2C_FFTX_TXFFST_M 0x1F00 // Transmit FIFO Status +#define I2C_FFTX_TXFFRST 0x2000 // Transmit FIFO Reset +#define I2C_FFTX_I2CFFEN 0x4000 // Transmit FIFO Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2CFFRX register +// +//***************************************************************************** +#define I2C_FFRX_RXFFIL_S 0 +#define I2C_FFRX_RXFFIL_M 0x1F // Receive FIFO Interrupt Level +#define I2C_FFRX_RXFFIENA 0x20 // Receive FIFO Interrupt Enable +#define I2C_FFRX_RXFFINTCLR 0x40 // Receive FIFO Interrupt Flag + // Clear +#define I2C_FFRX_RXFFINT 0x80 // Receive FIFO Interrupt Flag +#define I2C_FFRX_RXFFST_S 8 +#define I2C_FFRX_RXFFST_M 0x1F00 // Receive FIFO Status +#define I2C_FFRX_RXFFRST 0x2000 // Receive FIFO Reset +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ints.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ints.h new file mode 100644 index 00000000000..8f2ca7471fd --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_ints.h @@ -0,0 +1,299 @@ +//########################################################################### +// +// FILE: hw_ints.h +// +// TITLE: Definitions of interrupt numbers for use with interrupt.c. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// PIE Interrupt Numbers +// +// 0x00FF = PIE Table Row # +// 0xFF00 = PIE Table Column # +// 0xFFFF0000 = PIE Vector ID +// +//***************************************************************************** + +// Lower PIE Group 1 +#define INT_ADCA_CH1 0x200101 //ADC-A Interrupt 1 +#define INT_ADCB_CH1 0x210102 //ADC-B Interrupt 1 +#define INT_ADCC_CH1 0x220103 //ADC-C Interrupt 1 +#define INT_XINT1 0x230104 //External Interrupt 1 +#define INT_XINT2 0x240105 //External Interrupt 2 +#define INT_ADCD_CH1 0x250106 //ADC-D Interrupt 1 +#define INT_TINT0 0x260107 //Timer Interrupt 0 +#define INT_WAKEINT 0x270108 //Wakeup Interrupt + +// Lower PIE Group 2 +#define INT_PWM1TZ 0x280201 //PWM TZ Interrupt 1 +#define INT_PWM2TZ 0x290202 //PWM TZ Interrupt 2 +#define INT_PWM3TZ 0x2A0203 //PWM TZ Interrupt 3 +#define INT_PWM4TZ 0x2B0204 //PWM TZ Interrupt 4 +#define INT_PWM5TZ 0x2C0205 //PWM TZ Interrupt 5 +#define INT_PWM6TZ 0x2D0206 //PWM TZ Interrupt 6 +#define INT_PWM7TZ 0x2E0207 //PWM TZ Interrupt 7 +#define INT_PWM8TZ 0x2F0208 //PWM TZ Interrupt 8 + +// Lower PIE Group 3 +#define INT_PWM1INT 0x300301 //PWM Interrupt 1 +#define INT_PWM2INT 0x310302 //PWM Interrupt 2 +#define INT_PWM3INT 0x320303 //PWM Interrupt 3 +#define INT_PWM4INT 0x330304 //PWM Interrupt 4 +#define INT_PWM5INT 0x340305 //PWM Interrupt 5 +#define INT_PWM6INT 0x350306 //PWM Interrupt 6 +#define INT_PWM7INT 0x360307 //PWM Interrupt 7 +#define INT_PWM8INT 0x370308 //PWM Interrupt 8 + +// Lower PIE Group 4 +#define INT_CAP1INT 0x380401 //Capture Interrupt 1 +#define INT_CAP2INT 0x390402 //Capture Interrupt 2 +#define INT_CAP3INT 0x3A0403 //Capture Interrupt 3 +#define INT_CAP4INT 0x3B0404 //Capture Interrupt 4 +#define INT_CAP5INT 0x3C0405 //Capture Interrupt 5 +#define INT_CAP6INT 0x3D0406 //Capture Interrupt 6 +#define INT_CAP7INT 0x3E0407 //Capture Interrupt 7 +#define INT_CAP8INT 0x3F0408 //Capture Interrupt 8 + +// Lower PIE Group 5 +#define INT_EQEP1INT 0x400501 //Quadrature Interrupt 1 +#define INT_EQEP2INT 0x410502 //Quadrature Interrupt 2 +#define INT_EQEP3INT 0x420503 //Quadrature Interrupt 3 +#define INT_EQEP4INT 0x430504 //Quadrature Interrupt 4 +#define INT_CLB1INT 0x440505 //CLB Interrupt 1 +#define INT_CLB2INT 0x450506 //CLB Interrupt 2 +#define INT_CLB3INT 0x460507 //CLB Interrupt 3 +#define INT_CLB4INT 0x470508 //CLB Interrupt 4 + +// Lower PIE Group 6 +#define INT_SPIRXINTA 0x480601 //SPI-A Receive Interrupt +#define INT_SPITXINTA 0x490602 //SPI-A Transmit Interrupt +#define INT_SPIRXINTB 0x4A0603 //SPI-B Receive Interrupt +#define INT_SPITXINTB 0x4B0604 //SPI-B Transmit Interrupt +#define INT_MRINTA 0x4C0605 //McBSP-A Receive Interrupt +#define INT_MXINTA 0x4D0606 //McBSP-A Transmit Interrupt +#define INT_MRINTB 0x4E0607 //McBSP-B Receive Interrupt +#define INT_MXINTB 0x4F0608 //McBSP-B Transmit Interrupt + +// Lower PIE Group 7 +#define INT_DMA1INT 0x500701 //DMA Channel 1 Interrupt +#define INT_DMA2INT 0x510702 //DMA Channel 2 Interrupt +#define INT_DMA3INT 0x520703 //DMA Channel 3 Interrupt +#define INT_DMA4INT 0x530704 //DMA Channel 4 Interrupt +#define INT_DMA5INT 0x540705 //DMA Channel 5 Interrupt +#define INT_DMA6INT 0x550706 //DMA Channel 6 Interrupt + +// Lower PIE Group 8 +#define INT_I2CINT1A 0x580801 //I2C-A Basic Interrupts +#define INT_I2CINT2A 0x590802 //I2C-A FIFO Interrupts +#define INT_I2CINT1B 0x5A0803 //I2C-B Basic Interrupts +#define INT_I2CINT2B 0x5B0804 //I2C-B FIFO Interrupts +#define INT_SCICRX 0x5C0805 //SCI-C Receive Interrupt +#define INT_SCICTX 0x5D0806 //SCI-C Transmit Interrupt +#define INT_SCIDRX 0x5E0807 //SCI-D Receive Interrupt +#define INT_SCIDTX 0x5F0808 //SCI-D Transmit Interrupt + +// Lower PIE Group 9 +#define INT_SCIRXINTA 0x600901 //SCI-A RX Interrupt +#define INT_SCITXINTA 0x610902 //SCI-A TX Interrupt +#define INT_SCIRXINTB 0x620903 //SCI-B RX Interrupt +#define INT_SCITXINTB 0x630904 //SCI-B TX Interrupt +#define INT_CANA_0 0x640905 //CANA 0 Interrupt +#define INT_CANA_1 0x650906 //CANA 1 Interrupt +#define INT_CANB_0 0x660907 //CANB 0 Interrupt +#define INT_CANB_1 0x670908 //CANB 1 Interrupt + +// Lower PIE Group 10 +#define INT_ADCA_EVT 0x680A01 //ADCA_EVT Interrupt +#define INT_ADCA_CH2 0x690A02 //ADCA_CH2 Interrupt 2 +#define INT_ADCA_CH3 0x6A0A03 //ADCA_CH3 Interrupt 3 +#define INT_ADCA_CH4 0x6B0A04 //ADCA_CH4 Interrupt 4 +#define INT_ADCB_EVT 0x6C0A05 //ADCB_EVT Interrupt +#define INT_ADCB_CH2 0x6D0A06 //ADCB_CH2 Interrupt 2 +#define INT_ADCB_CH3 0x6E0A07 //ADCB_CH3 Interrupt 3 +#define INT_ADCB_CH4 0x6F0A08 //ADCB_CH4 Interrupt 4 + +// Lower PIE Group 11 +#define INT_CLA1INT1 0x700B01 //CLA_1 Interrupt 1 +#define INT_CLA1INT2 0x710B02 //CLA_1 Interrupt 2 +#define INT_CLA1INT3 0x720B03 //CLA_1 Interrupt 3 +#define INT_CLA1INT4 0x730B04 //CLA_1 Interrupt 4 +#define INT_CLA1INT5 0x740B05 //CLA_1 Interrupt 5 +#define INT_CLA1INT6 0x750B06 //CLA_1 Interrupt 6 +#define INT_CLA1INT7 0x760B07 //CLA_1 Interrupt 7 +#define INT_CLA1INT8 0x770B08 //CLA_1 Interrupt 8 + +// Lower PIE Group 12 +#define INT_XINT3 0x780C01 //External Interrupt 3 +#define INT_XINT4 0x790C02 //External Interrupt 4 +#define INT_XINT5 0x7A0C03 //External Interrupt 5 +#define INT_FMC 0x7C0C05 //FMC Interrupt +#define INT_VCU 0x7D0C06 //VCU Interrupt +#define INT_LVF 0x7E0C07 //Latched Overflow +#define INT_LUF 0x7F0C08 //Latched Underflow + +// Upper PIE Group 1 +#define INT_IPC0INT 0x84010D //IPC Interrupt 1 +#define INT_IPC1INT 0x85010E //IPC Interrupt 2 +#define INT_IPC2INT 0x86010F //IPC Interrupt 3 +#define INT_IPC3INT 0x870110 //IPC Interrupt 4 + +// Upper PIE Group 2 +#define INT_PWM9TZ 0x880209 //PWM TZ Interrupt 9 +#define INT_PWM10TZ 0x89020A //PWM TZ Interrupt 10 +#define INT_PWM11TZ 0x8A020B //PWM TZ Interrupt 11 +#define INT_PWM12TZ 0x8B020C //PWM TZ Interrupt 12 + +// Upper PIE Group 3 +#define INT_PWM9INT 0x900309 //PWM Interrupt 9 +#define INT_PWM10INT 0x91030A //PWN Interrupt 10 +#define INT_PWM11INT 0x92030B //PWM Interrupt 11 +#define INT_PWM12INT 0x93030C //PWM Interrupt 12 + +// Upper PIE Group 4 +#define INT_HRCAP1INT 0x980409 //High-Res Capture Interrupt 1 +#define INT_HRCAP2INT 0x99040A //High-Res Capture Interrupt 2 +#define INT_HRCAP3INT 0x9A040B //High-Res Capture Interrupt 3 +#define INT_HRCAP4INT 0x9B040C //High-Res Capture Interrupt 4 +#define INT_HRCAP5INT 0x9C040D //High-Res Capture Interrupt 1 +#define INT_HRCAP6INT 0x9D040E //High-Res Capture Interrupt 2 +#define INT_HRCAP7INT 0x9E040F //High-Res Capture Interrupt 3 +#define INT_HRCAP8INT 0x9F0410 //High-Res Capture Interrupt 4 + +// Upper PIE Group 5 +#define INT_SDFM1INT 0xA00509 //SDFM Interrupt 1 +#define INT_SDFM2INT 0xA1050A //SDFM Interrupt 2 +#define INT_SDFM3INT 0xA2050B //SDFM Interrupt 3 +#define INT_SDFM4INT 0xA3050C //SDFM Interrupt 4 +#define INT_SDFM5INT 0xA4050D //SDFM Interrupt 5 +#define INT_SDFM6INT 0xA5050E //SDFM Interrupt 6 +#define INT_SDFM7INT 0xA6050F //SDFM Interrupt 7 +#define INT_SDFM8INT 0xA70510 //SDFM Interrupt 8 + +// Upper PIE Group 6 +#define INT_SPIRXINTC 0xA80609 //SPI-A Receive Interrupt +#define INT_SPITXINTC 0xA9060A //SPI-A Transmit Interrupt +#define INT_SPIRXINTD 0xAA060B //SPI-B Receive Interrupt +#define INT_SPITXINTD 0xAB060C //SPI-B Transmit Interrupt + +// Upper PIE Group 8 +#define INT_UPPAINT 0xBE080F //UPP-A Interrupt +#define INT_UPPBINT 0xBF0810 //UPP-B Interrupt + +// Upper PIE Group 9 +#define INT_CANCINT1 0xC00909 //CANC 1 Interrupt +#define INT_CANCINT2 0xC1090A //CANC 2 Interrupt +#define INT_CANDINT1 0xC2090B //CAND 1 Interrupt +#define INT_CANDINT2 0xC3090C //CAND 2 Interrupt +#define INT_USBAINT 0xC6090F //USBA Interrupt +#define INT_USBBINT 0xC70910 //USBB Interrupt + +// Upper PIE Group 10 +#define INT_ADCC_EVT 0xC80A09 //ADCC_EVT Interrupt +#define INT_ADCC_CH2 0xC90A0A //ADCC_CH2 Interrupt 2 +#define INT_ADCC_CH3 0xCA0A0B //ADCC_CH3 Interrupt 3 +#define INT_ADCC_CH4 0xCB0A0C //ADCC_CH4 Interrupt 4 +#define INT_ADCD_EVT 0xCC0A0D //ADCD_EVT Interrupt +#define INT_ADCD_CH2 0xCD0A0E //ADCD_CH2 Interrupt 2 +#define INT_ADCD_CH3 0xCE0A0F //ADCD_CH3 Interrupt 3 +#define INT_ADCD_CH4 0xCF0A10 //ADCD_CH4 Interrupt 4 + +// Upper PIE Group 11 +#define INT_CLA2INT1 0xD00B09 //CLA_2 Interrupt 1 +#define INT_CLA2INT2 0xD10B0A //CLA_2 Interrupt 2 +#define INT_CLA2INT3 0xD20B0B //CLA_2 Interrupt 3 +#define INT_CLA2INT4 0xD30B0C //CLA_2 Interrupt 4 +#define INT_CLA2INT5 0xD40B0D //CLA_2 Interrupt 1 +#define INT_CLA2INT6 0xD50B0E //CLA_2 Interrupt 2 +#define INT_CLA2INT7 0xD60B0F //CLA_2 Interrupt 3 +#define INT_CLA2INT8 0xD70B10 //CLA_2 Interrupt 4 + +// Upper PIE Group 12 +#define INT_EMIF_ERR 0xD80C09 //EMIF Error Interrupt +#define INT_RAM_CORR_ERR 0xD90C0A //RAM Correctable Error Interrupt +#define INT_FLASH_CORR_ERR 0xDA0C0B //Flash correctable Error Interrupt +#define INT_RAM_ACC_VIO 0xDB0C0C //RAM Access Violation Interrupt +#define INT_SYS_PLL_SLIP 0xDC0C0D //System PLL Slip Interrupt +#define INT_AUX_PLL_SLIP 0xDD0C0E //Auxillary PLL Slip Interrupt +#define INT_CLA_OF 0xDE0C0F //CLA Overflow Interrupt +#define INT_CLA_UF 0xDF0C10 //CLA Underflow Interrupt + +//Workaround for Stellaris code +#define INT_USB0 INT_USBAINT // USB 0 Controller + +//Workaround for other interrupts +#define INT_RESET 0x000000 //Reset Interrupt +#define INT_INT1 0x010000 //Not Used +#define INT_INT2 0x020000 //Not Used +#define INT_INT3 0x030000 //Not Used +#define INT_INT4 0x040000 //Not Used +#define INT_INT5 0x050000 //Not Used +#define INT_INT6 0x060000 //Not Used +#define INT_INT7 0x070000 //Not Used +#define INT_INT8 0x080000 //Not Used +#define INT_INT9 0x090000 //Not Used +#define INT_INT10 0x0A0000 //Not Used +#define INT_INT11 0x0B0000 //Not Used +#define INT_INT12 0x0C0000 //Not Used +#define INT_TINT1 0x0D0D00 //Timer Interrupt 1 +#define INT_TINT2 0x0E0E00 //Timer Interrupt 2 +#define INT_DATALOG 0x0F0F00 //CPU Data Logging Interrupt +#define INT_RTOSINT 0x101000 //CPU Real Time OS Interrupt +#define INT_EMUINT 0x110000 //CPU Emulation Interrupt +#define INT_NMI 0x120000 //External Non-Maskable Interrupt +#define INT_ILLEGAL 0x130000 //Illegal Operation +#define INT_USER1 0x140000 //User-defined +#define INT_USER2 0x150000 //User-defined +#define INT_USER3 0x160000 //User-defined +#define INT_USER4 0x170000 //User-defined +#define INT_USER5 0x180000 //User-defined +#define INT_USER6 0x190000 //User-defined +#define INT_USER7 0x1A0000 //User-defined +#define INT_USER8 0x1B0000 //User-defined +#define INT_USER9 0x1C0000 //User-defined +#define INT_USER10 0x1D0000 //User-defined +#define INT_USER11 0x1E0000 //User-defined +#define INT_USER12 0x1F0000 //User-defined + + +#endif // __HW_INTS_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_memmap.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_memmap.h new file mode 100644 index 00000000000..94c774807aa --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_memmap.h @@ -0,0 +1,96 @@ +//########################################################################### +// +// FILE: hw_memmap.h +// +// TITLE: Macros defining the memory map of the C28x. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** + +#define USB0_BASE 0x00040000 // USB 0 Controller + +#define ADCA_RESULT_BASE 0x00000B00 // ADC-A Result +#define ADCB_RESULT_BASE 0x00000B20 // ADC-B Result +#define ADCC_RESULT_BASE 0x00000B40 // ADC-C Result +#define ADCD_RESULT_BASE 0x00000B60 // ADC-D Result + +#define ADCA_BASE 0x00007400 // ADC-A +#define ADCB_BASE 0x00007480 // ADC-B +#define ADCC_BASE 0x00007500 // ADC-C +#define ADCD_BASE 0x00007580 // ADC-D + +#define CMPSS1_BASE 0x00005C80 // CMPSS-1 +#define CMPSS2_BASE 0x00005CA0 // CMPSS-2 +#define CMPSS3_BASE 0x00005CC0 // CMPSS-3 +#define CMPSS4_BASE 0x00005CE0 // CMPSS-4 +#define CMPSS5_BASE 0x00005D00 // CMPSS-5 +#define CMPSS6_BASE 0x00005D20 // CMPSS-6 +#define CMPSS7_BASE 0x00005D40 // CMPSS-7 +#define CMPSS8_BASE 0x00005D60 // CMPSS-8 + +#define I2CA_BASE 0x00007300 // I2C-A +#define I2CB_BASE 0x00007340 // I2C-B + +#define UARTA_BASE 0x00007200 // SCI-A +#define UARTB_BASE 0x00007210 // SCI-B +#define UARTC_BASE 0x00007220 // SCI-C +#define UARTD_BASE 0x00007230 // SCI-D + +#define EQEP1_BASE 0x00005100 // Enhanced EQEP-1 +#define EQEP2_BASE 0x00005140 // Enhanced EQEP-2 +#define EQEP3_BASE 0x00005180 // Enhanced EQEP-3 + +#define SPIA_BASE 0x00006100 // SPI-A +#define SPIB_BASE 0x00006110 // SPI-B +#define SPIC_BASE 0x00006120 // SPI-C + +#define CANA_BASE 0x00048000 // CAN-A +#define CANB_BASE 0x0004A000 // CAN-B +#define CANA_MSG_RAM 0x00049000 +#define CANB_MSG_RAM 0x0004B000 + +#endif // __HW_MEMMAP_H__ + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_types.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_types.h new file mode 100644 index 00000000000..59edb8ce16c --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_types.h @@ -0,0 +1,88 @@ +//########################################################################### +// +// FILE: hw_types.h +// +// TITLE: Type definitions used in ALL driverlib functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define fake 8 bit types for USB related code. +// +//***************************************************************************** + +typedef uint16_t uint8_t; +typedef int16_t int8_t; + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + __byte((int *)(x),0) +//Emulated Bitbanded write +#define HWREGBITW(address, mask, value) \ + (*(volatile uint32_t *)(address)) = \ + ((*(volatile uint32_t *)(address)) & ~((uint32_t)1 << mask)) \ + | ((uint32_t)value << mask) +//Emulated Bitbanded read +#define HWREGBITR(address, mask) \ + (((*(volatile uint32_t *)(address)) & ((uint32_t)1 << mask)) >> mask) + +//Emulated Bitbanded write +#define HWREGBITHW(address, mask, value) \ + (*(volatile uint16_t *)(address)) = \ + ((*(volatile uint16_t *)(address)) & ~((uint16_t)1 << mask)) \ + | ((uint16_t)value << mask) +//Emulated Bitbanded read +#define HWREGBITHR(address, mask) \ + (((*(volatile uint16_t *)(address)) & ((uint16_t)1 << mask)) >> mask) + + + +#endif // __HW_TYPES_H__ + + diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_uart.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_uart.h new file mode 100644 index 00000000000..c788095febf --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_uart.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: hw_uart.h +// +// TITLE: Definitions for the C28x SCI registers. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the SCI register offsets +// +//***************************************************************************** +#define UART_O_CCR 0x0 // Communications control register +#define UART_O_CTL1 0x1 // Control register 1 +#define UART_O_HBAUD 0x2 // Baud rate (high) register +#define UART_O_LBAUD 0x3 // Baud rate (low) register +#define UART_O_CTL2 0x4 // Control register 2 +#define UART_O_RXST 0x5 // Receive status register +#define UART_O_RXEMU 0x6 // Receive emulation buffer + // register +#define UART_O_RXBUF 0x7 // Receive data buffer +#define UART_O_TXBUF 0x9 // Transmit data buffer +#define UART_O_FFTX 0xA // FIFO transmit register +#define UART_O_FFRX 0xB // FIFO receive register +#define UART_O_FFCT 0xC // FIFO control register +#define UART_O_PRI 0xF // FIFO Priority control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCICCR register +// +//***************************************************************************** +#define UART_CCR_SCICHAR_S 0 +#define UART_CCR_SCICHAR_M 0x7 // Character length control +#define UART_CCR_ADDRIDLE_MODE 0x8 // ADDR/IDLE Mode control +#define UART_CCR_LOOPBKENA 0x10 // Loop Back enable +#define UART_CCR_PARITYENA 0x20 // Parity enable +#define UART_CCR_PARITY 0x40 // Even or Odd Parity +#define UART_CCR_STOPBITS 0x80 // Number of Stop Bits + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCICTL1 register +// +//***************************************************************************** +#define UART_CTL1_RXENA 0x1 // SCI receiver enable +#define UART_CTL1_TXENA 0x2 // SCI transmitter enable +#define UART_CTL1_SLEEP 0x4 // SCI sleep +#define UART_CTL1_TXWAKE 0x8 // Transmitter wakeup method +#define UART_CTL1_SWRESET 0x20 // Software reset +#define UART_CTL1_RXERRINTENA 0x40 // Receive __interrupt enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIHBAUD register +// +//***************************************************************************** +#define UART_HBAUD_BAUD_S 0 +#define UART_HBAUD_BAUD_M 0xFFFF // SCI 16-bit baud selection + // Registers SCIHBAUD + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCILBAUD register +// +//***************************************************************************** +#define UART_LBAUD_BAUD_S 0 +#define UART_LBAUD_BAUD_M 0xFFFF // SCI 16-bit baud selection + // Registers SCILBAUD + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCICTL2 register +// +//***************************************************************************** +#define UART_CTL2_TXINTENA 0x1 // Transmit __interrupt enable +#define UART_CTL2_RXBKINTENA 0x2 // Receiver-buffer break enable +#define UART_CTL2_TXEMPTY 0x40 // Transmitter empty flag +#define UART_CTL2_TXRDY 0x80 // Transmitter ready flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIRXST register +// +//***************************************************************************** +#define UART_RXST_RXWAKE 0x2 // Receiver wakeup detect flag +#define UART_RXST_PE 0x4 // Parity error flag +#define UART_RXST_OE 0x8 // Overrun error flag +#define UART_RXST_FE 0x10 // Framing error flag +#define UART_RXST_BRKDT 0x20 // Break-detect flag +#define UART_RXST_RXRDY 0x40 // Receiver ready flag +#define UART_RXST_RXERROR 0x80 // Receiver error flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIRXEMU register +// +//***************************************************************************** +#define UART_RXEMU_ERXDT_S 0 +#define UART_RXEMU_ERXDT_M 0xFF // Receive emulation buffer data + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIRXBUF register +// +//***************************************************************************** +#define UART_RXBUF_SAR_S 0 +#define UART_RXBUF_SAR_M 0xFF // Receive Character bits +#define UART_RXBUF_SCIFFPE 0x4000 // Receiver error flag +#define UART_RXBUF_SCIFFFE 0x8000 // Receiver error flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCITXBUF register +// +//***************************************************************************** +#define UART_TXBUF_TXDT_S 0 +#define UART_TXBUF_TXDT_M 0xFF // Transmit data buffer + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIFFTX register +// +//***************************************************************************** +#define UART_FFTX_TXFFIL_S 0 +#define UART_FFTX_TXFFIL_M 0x1F // Interrupt level +#define UART_FFTX_TXFFIENA 0x20 // Interrupt enable +#define UART_FFTX_TXFFINTCLR 0x40 // Clear INT flag +#define UART_FFTX_TXFFINT 0x80 // INT flag +#define UART_FFTX_TXFFST_S 8 +#define UART_FFTX_TXFFST_M 0x1F00 // FIFO status +#define UART_FFTX_TXFIFORESET 0x2000 // FIFO reset +#define UART_FFTX_SCIFFENA 0x4000 // Enhancement enable +#define UART_FFTX_SCIRST 0x8000 // SCI reset rx/tx channels + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIFFRX register +// +//***************************************************************************** +#define UART_FFRX_RXFFIL_S 0 +#define UART_FFRX_RXFFIL_M 0x1F // Interrupt level +#define UART_FFRX_RXFFIENA 0x20 // Interrupt enable +#define UART_FFRX_RXFFINTCLR 0x40 // Clear INT flag +#define UART_FFRX_RXFFINT 0x80 // INT flag +#define UART_FFRX_RXFFST_S 8 +#define UART_FFRX_RXFFST_M 0x1F00 // FIFO status +#define UART_FFRX_RXFIFORESET 0x2000 // FIFO reset +#define UART_FFRX_RXFFOVRCLR 0x4000 // Clear overflow +#define UART_FFRX_RXFFOVF 0x8000 // FIFO overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIFFCT register +// +//***************************************************************************** +#define UART_FFCT_FFTXDLY_S 0 +#define UART_FFCT_FFTXDLY_M 0xFF // FIFO transmit delay +#define UART_FFCT_CDC 0x2000 // Auto baud mode enable +#define UART_FFCT_ABDCLR 0x4000 // Auto baud clear +#define UART_FFCT_ABD 0x8000 // Auto baud detect + +//***************************************************************************** +// +// The following are defines for the bit fields in the SCIPRI register +// +//***************************************************************************** +#define UART_PRI_FREESOFT_S 3 +#define UART_PRI_FREESOFT_M 0x18 // Emulation modes +#endif diff --git a/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_usb.h b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_usb.h new file mode 100644 index 00000000000..9602cb7a15a --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/inc/hw_usb.h @@ -0,0 +1,4611 @@ +//***************************************************************************** +// +// hw_usb.h - Macros for use in accessing the USB registers. +// +// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_USB_H__ +#define __HW_USB_H__ + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus register offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 +#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 +#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 +#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_FIFO8 0x00000040 // USB FIFO Endpoint 8 +#define USB_O_FIFO9 0x00000044 // USB FIFO Endpoint 9 +#define USB_O_FIFO10 0x00000048 // USB FIFO Endpoint 10 +#define USB_O_FIFO11 0x0000004C // USB FIFO Endpoint 11 +#define USB_O_FIFO12 0x00000050 // USB FIFO Endpoint 12 +#define USB_O_FIFO13 0x00000054 // USB FIFO Endpoint 13 +#define USB_O_FIFO14 0x00000058 // USB FIFO Endpoint 14 +#define USB_O_FIFO15 0x0000005C // USB FIFO Endpoint 15 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address + // Endpoint 4 +#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address + // Endpoint 4 +#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 +#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address + // Endpoint 4 +#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint + // 4 +#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 +#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address + // Endpoint 5 +#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address + // Endpoint 5 +#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 +#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address + // Endpoint 5 +#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint + // 5 +#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 +#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address + // Endpoint 6 +#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address + // Endpoint 6 +#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 +#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address + // Endpoint 6 +#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint + // 6 +#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 +#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address + // Endpoint 7 +#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address + // Endpoint 7 +#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 +#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address + // Endpoint 7 +#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint + // 7 +#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_TXFUNCADDR8 0x000000C0 // USB Transmit Functional Address + // Endpoint 8 +#define USB_O_TXHUBADDR8 0x000000C2 // USB Transmit Hub Address + // Endpoint 8 +#define USB_O_TXHUBPORT8 0x000000C3 // USB Transmit Hub Port Endpoint 8 +#define USB_O_RXFUNCADDR8 0x000000C4 // USB Receive Functional Address + // Endpoint 8 +#define USB_O_RXHUBADDR8 0x000000C6 // USB Receive Hub Address Endpoint + // 8 +#define USB_O_RXHUBPORT8 0x000000C7 // USB Receive Hub Port Endpoint 8 +#define USB_O_TXFUNCADDR9 0x000000C8 // USB Transmit Functional Address + // Endpoint 9 +#define USB_O_TXHUBADDR9 0x000000CA // USB Transmit Hub Address + // Endpoint 9 +#define USB_O_TXHUBPORT9 0x000000CB // USB Transmit Hub Port Endpoint 9 +#define USB_O_RXFUNCADDR9 0x000000CC // USB Receive Functional Address + // Endpoint 9 +#define USB_O_RXHUBADDR9 0x000000CE // USB Receive Hub Address Endpoint + // 9 +#define USB_O_RXHUBPORT9 0x000000CF // USB Receive Hub Port Endpoint 9 +#define USB_O_TXFUNCADDR10 0x000000D0 // USB Transmit Functional Address + // Endpoint 10 +#define USB_O_TXHUBADDR10 0x000000D2 // USB Transmit Hub Address + // Endpoint 10 +#define USB_O_TXHUBPORT10 0x000000D3 // USB Transmit Hub Port Endpoint + // 10 +#define USB_O_RXFUNCADDR10 0x000000D4 // USB Receive Functional Address + // Endpoint 10 +#define USB_O_RXHUBADDR10 0x000000D6 // USB Receive Hub Address Endpoint + // 10 +#define USB_O_RXHUBPORT10 0x000000D7 // USB Receive Hub Port Endpoint 10 +#define USB_O_TXFUNCADDR11 0x000000D8 // USB Transmit Functional Address + // Endpoint 11 +#define USB_O_TXHUBADDR11 0x000000DA // USB Transmit Hub Address + // Endpoint 11 +#define USB_O_TXHUBPORT11 0x000000DB // USB Transmit Hub Port Endpoint + // 11 +#define USB_O_RXFUNCADDR11 0x000000DC // USB Receive Functional Address + // Endpoint 11 +#define USB_O_RXHUBADDR11 0x000000DE // USB Receive Hub Address Endpoint + // 11 +#define USB_O_RXHUBPORT11 0x000000DF // USB Receive Hub Port Endpoint 11 +#define USB_O_TXFUNCADDR12 0x000000E0 // USB Transmit Functional Address + // Endpoint 12 +#define USB_O_TXHUBADDR12 0x000000E2 // USB Transmit Hub Address + // Endpoint 12 +#define USB_O_TXHUBPORT12 0x000000E3 // USB Transmit Hub Port Endpoint + // 12 +#define USB_O_RXFUNCADDR12 0x000000E4 // USB Receive Functional Address + // Endpoint 12 +#define USB_O_RXHUBADDR12 0x000000E6 // USB Receive Hub Address Endpoint + // 12 +#define USB_O_RXHUBPORT12 0x000000E7 // USB Receive Hub Port Endpoint 12 +#define USB_O_TXFUNCADDR13 0x000000E8 // USB Transmit Functional Address + // Endpoint 13 +#define USB_O_TXHUBADDR13 0x000000EA // USB Transmit Hub Address + // Endpoint 13 +#define USB_O_TXHUBPORT13 0x000000EB // USB Transmit Hub Port Endpoint + // 13 +#define USB_O_RXFUNCADDR13 0x000000EC // USB Receive Functional Address + // Endpoint 13 +#define USB_O_RXHUBADDR13 0x000000EE // USB Receive Hub Address Endpoint + // 13 +#define USB_O_RXHUBPORT13 0x000000EF // USB Receive Hub Port Endpoint 13 +#define USB_O_TXFUNCADDR14 0x000000F0 // USB Transmit Functional Address + // Endpoint 14 +#define USB_O_TXHUBADDR14 0x000000F2 // USB Transmit Hub Address + // Endpoint 14 +#define USB_O_TXHUBPORT14 0x000000F3 // USB Transmit Hub Port Endpoint + // 14 +#define USB_O_RXFUNCADDR14 0x000000F4 // USB Receive Functional Address + // Endpoint 14 +#define USB_O_RXHUBADDR14 0x000000F6 // USB Receive Hub Address Endpoint + // 14 +#define USB_O_RXHUBPORT14 0x000000F7 // USB Receive Hub Port Endpoint 14 +#define USB_O_TXFUNCADDR15 0x000000F8 // USB Transmit Functional Address + // Endpoint 15 +#define USB_O_TXHUBADDR15 0x000000FA // USB Transmit Hub Address + // Endpoint 15 +#define USB_O_TXHUBPORT15 0x000000FB // USB Transmit Hub Port Endpoint + // 15 +#define USB_O_RXFUNCADDR15 0x000000FC // USB Receive Functional Address + // Endpoint 15 +#define USB_O_RXHUBADDR15 0x000000FE // USB Receive Hub Address Endpoint + // 15 +#define USB_O_RXHUBPORT15 0x000000FF // USB Receive Hub Port Endpoint 15 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data + // Endpoint 4 +#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status + // Endpoint 4 Low +#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status + // Endpoint 4 High +#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data + // Endpoint 4 +#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status + // Endpoint 4 Low +#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status + // Endpoint 4 High +#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint + // 4 +#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type + // Endpoint 4 +#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval + // Endpoint 4 +#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type + // Endpoint 4 +#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling + // Interval Endpoint 4 +#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data + // Endpoint 5 +#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status + // Endpoint 5 Low +#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status + // Endpoint 5 High +#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data + // Endpoint 5 +#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status + // Endpoint 5 Low +#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status + // Endpoint 5 High +#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint + // 5 +#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type + // Endpoint 5 +#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval + // Endpoint 5 +#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type + // Endpoint 5 +#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling + // Interval Endpoint 5 +#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data + // Endpoint 6 +#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status + // Endpoint 6 Low +#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status + // Endpoint 6 High +#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data + // Endpoint 6 +#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status + // Endpoint 6 Low +#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status + // Endpoint 6 High +#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint + // 6 +#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type + // Endpoint 6 +#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval + // Endpoint 6 +#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type + // Endpoint 6 +#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling + // Interval Endpoint 6 +#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data + // Endpoint 7 +#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status + // Endpoint 7 Low +#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status + // Endpoint 7 High +#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data + // Endpoint 7 +#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status + // Endpoint 7 Low +#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status + // Endpoint 7 High +#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint + // 7 +#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type + // Endpoint 7 +#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval + // Endpoint 7 +#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type + // Endpoint 7 +#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling + // Interval Endpoint 7 +#define USB_O_TXMAXP8 0x00000180 // USB Maximum Transmit Data + // Endpoint 8 +#define USB_O_TXCSRL8 0x00000182 // USB Transmit Control and Status + // Endpoint 8 Low +#define USB_O_TXCSRH8 0x00000183 // USB Transmit Control and Status + // Endpoint 8 High +#define USB_O_RXMAXP8 0x00000184 // USB Maximum Receive Data + // Endpoint 8 +#define USB_O_RXCSRL8 0x00000186 // USB Receive Control and Status + // Endpoint 8 Low +#define USB_O_RXCSRH8 0x00000187 // USB Receive Control and Status + // Endpoint 8 High +#define USB_O_RXCOUNT8 0x00000188 // USB Receive Byte Count Endpoint + // 8 +#define USB_O_TXTYPE8 0x0000018A // USB Host Transmit Configure Type + // Endpoint 8 +#define USB_O_TXINTERVAL8 0x0000018B // USB Host Transmit Interval + // Endpoint 8 +#define USB_O_RXTYPE8 0x0000018C // USB Host Configure Receive Type + // Endpoint 8 +#define USB_O_RXINTERVAL8 0x0000018D // USB Host Receive Polling + // Interval Endpoint 8 +#define USB_O_TXMAXP9 0x00000190 // USB Maximum Transmit Data + // Endpoint 9 +#define USB_O_TXCSRL9 0x00000192 // USB Transmit Control and Status + // Endpoint 9 Low +#define USB_O_TXCSRH9 0x00000193 // USB Transmit Control and Status + // Endpoint 9 High +#define USB_O_RXMAXP9 0x00000194 // USB Maximum Receive Data + // Endpoint 9 +#define USB_O_RXCSRL9 0x00000196 // USB Receive Control and Status + // Endpoint 9 Low +#define USB_O_RXCSRH9 0x00000197 // USB Receive Control and Status + // Endpoint 9 High +#define USB_O_RXCOUNT9 0x00000198 // USB Receive Byte Count Endpoint + // 9 +#define USB_O_TXTYPE9 0x0000019A // USB Host Transmit Configure Type + // Endpoint 9 +#define USB_O_TXINTERVAL9 0x0000019B // USB Host Transmit Interval + // Endpoint 9 +#define USB_O_RXTYPE9 0x0000019C // USB Host Configure Receive Type + // Endpoint 9 +#define USB_O_RXINTERVAL9 0x0000019D // USB Host Receive Polling + // Interval Endpoint 9 +#define USB_O_TXMAXP10 0x000001A0 // USB Maximum Transmit Data + // Endpoint 10 +#define USB_O_TXCSRL10 0x000001A2 // USB Transmit Control and Status + // Endpoint 10 Low +#define USB_O_TXCSRH10 0x000001A3 // USB Transmit Control and Status + // Endpoint 10 High +#define USB_O_RXMAXP10 0x000001A4 // USB Maximum Receive Data + // Endpoint 10 +#define USB_O_RXCSRL10 0x000001A6 // USB Receive Control and Status + // Endpoint 10 Low +#define USB_O_RXCSRH10 0x000001A7 // USB Receive Control and Status + // Endpoint 10 High +#define USB_O_RXCOUNT10 0x000001A8 // USB Receive Byte Count Endpoint + // 10 +#define USB_O_TXTYPE10 0x000001AA // USB Host Transmit Configure Type + // Endpoint 10 +#define USB_O_TXINTERVAL10 0x000001AB // USB Host Transmit Interval + // Endpoint 10 +#define USB_O_RXTYPE10 0x000001AC // USB Host Configure Receive Type + // Endpoint 10 +#define USB_O_RXINTERVAL10 0x000001AD // USB Host Receive Polling + // Interval Endpoint 10 +#define USB_O_TXMAXP11 0x000001B0 // USB Maximum Transmit Data + // Endpoint 11 +#define USB_O_TXCSRL11 0x000001B2 // USB Transmit Control and Status + // Endpoint 11 Low +#define USB_O_TXCSRH11 0x000001B3 // USB Transmit Control and Status + // Endpoint 11 High +#define USB_O_RXMAXP11 0x000001B4 // USB Maximum Receive Data + // Endpoint 11 +#define USB_O_RXCSRL11 0x000001B6 // USB Receive Control and Status + // Endpoint 11 Low +#define USB_O_RXCSRH11 0x000001B7 // USB Receive Control and Status + // Endpoint 11 High +#define USB_O_RXCOUNT11 0x000001B8 // USB Receive Byte Count Endpoint + // 11 +#define USB_O_TXTYPE11 0x000001BA // USB Host Transmit Configure Type + // Endpoint 11 +#define USB_O_TXINTERVAL11 0x000001BB // USB Host Transmit Interval + // Endpoint 11 +#define USB_O_RXTYPE11 0x000001BC // USB Host Configure Receive Type + // Endpoint 11 +#define USB_O_RXINTERVAL11 0x000001BD // USB Host Receive Polling + // Interval Endpoint 11 +#define USB_O_TXMAXP12 0x000001C0 // USB Maximum Transmit Data + // Endpoint 12 +#define USB_O_TXCSRL12 0x000001C2 // USB Transmit Control and Status + // Endpoint 12 Low +#define USB_O_TXCSRH12 0x000001C3 // USB Transmit Control and Status + // Endpoint 12 High +#define USB_O_RXMAXP12 0x000001C4 // USB Maximum Receive Data + // Endpoint 12 +#define USB_O_RXCSRL12 0x000001C6 // USB Receive Control and Status + // Endpoint 12 Low +#define USB_O_RXCSRH12 0x000001C7 // USB Receive Control and Status + // Endpoint 12 High +#define USB_O_RXCOUNT12 0x000001C8 // USB Receive Byte Count Endpoint + // 12 +#define USB_O_TXTYPE12 0x000001CA // USB Host Transmit Configure Type + // Endpoint 12 +#define USB_O_TXINTERVAL12 0x000001CB // USB Host Transmit Interval + // Endpoint 12 +#define USB_O_RXTYPE12 0x000001CC // USB Host Configure Receive Type + // Endpoint 12 +#define USB_O_RXINTERVAL12 0x000001CD // USB Host Receive Polling + // Interval Endpoint 12 +#define USB_O_TXMAXP13 0x000001D0 // USB Maximum Transmit Data + // Endpoint 13 +#define USB_O_TXCSRL13 0x000001D2 // USB Transmit Control and Status + // Endpoint 13 Low +#define USB_O_TXCSRH13 0x000001D3 // USB Transmit Control and Status + // Endpoint 13 High +#define USB_O_RXMAXP13 0x000001D4 // USB Maximum Receive Data + // Endpoint 13 +#define USB_O_RXCSRL13 0x000001D6 // USB Receive Control and Status + // Endpoint 13 Low +#define USB_O_RXCSRH13 0x000001D7 // USB Receive Control and Status + // Endpoint 13 High +#define USB_O_RXCOUNT13 0x000001D8 // USB Receive Byte Count Endpoint + // 13 +#define USB_O_TXTYPE13 0x000001DA // USB Host Transmit Configure Type + // Endpoint 13 +#define USB_O_TXINTERVAL13 0x000001DB // USB Host Transmit Interval + // Endpoint 13 +#define USB_O_RXTYPE13 0x000001DC // USB Host Configure Receive Type + // Endpoint 13 +#define USB_O_RXINTERVAL13 0x000001DD // USB Host Receive Polling + // Interval Endpoint 13 +#define USB_O_TXMAXP14 0x000001E0 // USB Maximum Transmit Data + // Endpoint 14 +#define USB_O_TXCSRL14 0x000001E2 // USB Transmit Control and Status + // Endpoint 14 Low +#define USB_O_TXCSRH14 0x000001E3 // USB Transmit Control and Status + // Endpoint 14 High +#define USB_O_RXMAXP14 0x000001E4 // USB Maximum Receive Data + // Endpoint 14 +#define USB_O_RXCSRL14 0x000001E6 // USB Receive Control and Status + // Endpoint 14 Low +#define USB_O_RXCSRH14 0x000001E7 // USB Receive Control and Status + // Endpoint 14 High +#define USB_O_RXCOUNT14 0x000001E8 // USB Receive Byte Count Endpoint + // 14 +#define USB_O_TXTYPE14 0x000001EA // USB Host Transmit Configure Type + // Endpoint 14 +#define USB_O_TXINTERVAL14 0x000001EB // USB Host Transmit Interval + // Endpoint 14 +#define USB_O_RXTYPE14 0x000001EC // USB Host Configure Receive Type + // Endpoint 14 +#define USB_O_RXINTERVAL14 0x000001ED // USB Host Receive Polling + // Interval Endpoint 14 +#define USB_O_TXMAXP15 0x000001F0 // USB Maximum Transmit Data + // Endpoint 15 +#define USB_O_TXCSRL15 0x000001F2 // USB Transmit Control and Status + // Endpoint 15 Low +#define USB_O_TXCSRH15 0x000001F3 // USB Transmit Control and Status + // Endpoint 15 High +#define USB_O_RXMAXP15 0x000001F4 // USB Maximum Receive Data + // Endpoint 15 +#define USB_O_RXCSRL15 0x000001F6 // USB Receive Control and Status + // Endpoint 15 Low +#define USB_O_RXCSRH15 0x000001F7 // USB Receive Control and Status + // Endpoint 15 High +#define USB_O_RXCOUNT15 0x000001F8 // USB Receive Byte Count Endpoint + // 15 +#define USB_O_TXTYPE15 0x000001FA // USB Host Transmit Configure Type + // Endpoint 15 +#define USB_O_TXINTERVAL15 0x000001FB // USB Host Transmit Interval + // Endpoint 15 +#define USB_O_RXTYPE15 0x000001FC // USB Host Configure Receive Type + // Endpoint 15 +#define USB_O_RXINTERVAL15 0x000001FD // USB Host Receive Polling + // Interval Endpoint 15 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in + // Block Transfer Endpoint 4 +#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in + // Block Transfer Endpoint 5 +#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in + // Block Transfer Endpoint 6 +#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in + // Block Transfer Endpoint 7 +#define USB_O_RQPKTCOUNT8 0x00000320 // USB Request Packet Count in + // Block Transfer Endpoint 8 +#define USB_O_RQPKTCOUNT9 0x00000324 // USB Request Packet Count in + // Block Transfer Endpoint 9 +#define USB_O_RQPKTCOUNT10 0x00000328 // USB Request Packet Count in + // Block Transfer Endpoint 10 +#define USB_O_RQPKTCOUNT11 0x0000032C // USB Request Packet Count in + // Block Transfer Endpoint 11 +#define USB_O_RQPKTCOUNT12 0x00000330 // USB Request Packet Count in + // Block Transfer Endpoint 12 +#define USB_O_RQPKTCOUNT13 0x00000334 // USB Request Packet Count in + // Block Transfer Endpoint 13 +#define USB_O_RQPKTCOUNT14 0x00000338 // USB Request Packet Count in + // Block Transfer Endpoint 14 +#define USB_O_RQPKTCOUNT15 0x0000033C // USB Request Packet Count in + // Block Transfer Endpoint 15 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status +#define USB_O_VDC 0x00000430 // USB VBUS Droop Control +#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw + // Interrupt Status +#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt + // Mask +#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt + // Status and Clear +#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw + // Interrupt Status +#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt + // Mask +#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt + // Status and Clear +#define USB_O_DMASEL 0x00000450 // USB DMA Select +#define USB_O_PP 0x00000FC0 // USB Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt +#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt +#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt +#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt +#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt +#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt +#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt +#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt +#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt +#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt +#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt +#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt +#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt +#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt +#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable +#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable +#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable +#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable +#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable +#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable +#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable +#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable +#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable +#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable +#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable +#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable +#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable +#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable +#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST +#define USB_IS_DISCON 0x00000020 // Session Disconnect +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt +#define USB_IE_SESREQ 0x00000040 // Enable Session Request +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO8 register. +// +//***************************************************************************** +#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO8_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO9 register. +// +//***************************************************************************** +#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO9_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO10 register. +// +//***************************************************************************** +#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO10_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO11 register. +// +//***************************************************************************** +#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO11_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO12 register. +// +//***************************************************************************** +#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO12_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO13 register. +// +//***************************************************************************** +#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO13_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO14 register. +// +//***************************************************************************** +#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO14_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO15 register. +// +//***************************************************************************** +#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO15_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP8 register. +// +//***************************************************************************** +#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL8 register. +// +//***************************************************************************** +#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL8_STALL 0x00000010 // Send STALL +#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL8_ERROR 0x00000004 // Error +#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH8 register. +// +//***************************************************************************** +#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH8_MODE 0x00000020 // Mode +#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH8_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP8 register. +// +//***************************************************************************** +#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL8 register. +// +//***************************************************************************** +#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL8_STALL 0x00000020 // Send STALL +#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL8_OVER 0x00000004 // Overrun +#define USB_RXCSRL8_ERROR 0x00000004 // Error +#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH8 register. +// +//***************************************************************************** +#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH8_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT8 register. +// +//***************************************************************************** +#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE8 register. +// +//***************************************************************************** +#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL8_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL8_NAKLMT_S \ + 0 +#define USB_TXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE8 register. +// +//***************************************************************************** +#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL8_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL8_NAKLMT_S \ + 0 +#define USB_RXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP9 register. +// +//***************************************************************************** +#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL9 register. +// +//***************************************************************************** +#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL9_STALL 0x00000010 // Send STALL +#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL9_ERROR 0x00000004 // Error +#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH9 register. +// +//***************************************************************************** +#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH9_MODE 0x00000020 // Mode +#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH9_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP9 register. +// +//***************************************************************************** +#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL9 register. +// +//***************************************************************************** +#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL9_STALL 0x00000020 // Send STALL +#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL9_ERROR 0x00000004 // Error +#define USB_RXCSRL9_OVER 0x00000004 // Overrun +#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH9 register. +// +//***************************************************************************** +#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH9_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT9 register. +// +//***************************************************************************** +#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE9 register. +// +//***************************************************************************** +#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL9_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL9_TXPOLL_S \ + 0 +#define USB_TXINTERVAL9_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE9 register. +// +//***************************************************************************** +#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL9_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL9_NAKLMT_S \ + 0 +#define USB_RXINTERVAL9_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP10 register. +// +//***************************************************************************** +#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL10 register. +// +//***************************************************************************** +#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL10_STALL 0x00000010 // Send STALL +#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL10_ERROR 0x00000004 // Error +#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH10 register. +// +//***************************************************************************** +#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH10_MODE 0x00000020 // Mode +#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH10_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP10 register. +// +//***************************************************************************** +#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL10 register. +// +//***************************************************************************** +#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL10_STALL 0x00000020 // Send STALL +#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL10_OVER 0x00000004 // Overrun +#define USB_RXCSRL10_ERROR 0x00000004 // Error +#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH10 register. +// +//***************************************************************************** +#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH10_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT10_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE10 register. +// +//***************************************************************************** +#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL10_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL10_TXPOLL_S \ + 0 +#define USB_TXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE10 register. +// +//***************************************************************************** +#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL10_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL10_TXPOLL_S \ + 0 +#define USB_RXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP11 register. +// +//***************************************************************************** +#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL11 register. +// +//***************************************************************************** +#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL11_STALL 0x00000010 // Send STALL +#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL11_ERROR 0x00000004 // Error +#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH11 register. +// +//***************************************************************************** +#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH11_MODE 0x00000020 // Mode +#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH11_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP11 register. +// +//***************************************************************************** +#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL11 register. +// +//***************************************************************************** +#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL11_STALL 0x00000020 // Send STALL +#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL11_OVER 0x00000004 // Overrun +#define USB_RXCSRL11_ERROR 0x00000004 // Error +#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH11 register. +// +//***************************************************************************** +#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH11_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT11_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE11 register. +// +//***************************************************************************** +#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL11_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL11_NAKLMT_S \ + 0 +#define USB_TXINTERVAL11_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE11 register. +// +//***************************************************************************** +#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL11_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL11_TXPOLL_S \ + 0 +#define USB_RXINTERVAL11_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP12 register. +// +//***************************************************************************** +#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL12 register. +// +//***************************************************************************** +#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL12_STALL 0x00000010 // Send STALL +#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL12_ERROR 0x00000004 // Error +#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH12 register. +// +//***************************************************************************** +#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH12_MODE 0x00000020 // Mode +#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH12_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP12 register. +// +//***************************************************************************** +#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL12 register. +// +//***************************************************************************** +#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL12_STALL 0x00000020 // Send STALL +#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL12_ERROR 0x00000004 // Error +#define USB_RXCSRL12_OVER 0x00000004 // Overrun +#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH12 register. +// +//***************************************************************************** +#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH12_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT12_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE12 register. +// +//***************************************************************************** +#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL12_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL12_TXPOLL_S \ + 0 +#define USB_TXINTERVAL12_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE12 register. +// +//***************************************************************************** +#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL12_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL12_NAKLMT_S \ + 0 +#define USB_RXINTERVAL12_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP13 register. +// +//***************************************************************************** +#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL13 register. +// +//***************************************************************************** +#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL13_STALL 0x00000010 // Send STALL +#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL13_ERROR 0x00000004 // Error +#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH13 register. +// +//***************************************************************************** +#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH13_MODE 0x00000020 // Mode +#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH13_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP13 register. +// +//***************************************************************************** +#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL13 register. +// +//***************************************************************************** +#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL13_STALL 0x00000020 // Send STALL +#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL13_OVER 0x00000004 // Overrun +#define USB_RXCSRL13_ERROR 0x00000004 // Error +#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH13 register. +// +//***************************************************************************** +#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH13_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT13_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE13 register. +// +//***************************************************************************** +#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL13_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL13_TXPOLL_S \ + 0 +#define USB_TXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE13 register. +// +//***************************************************************************** +#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL13_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL13_TXPOLL_S \ + 0 +#define USB_RXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP14 register. +// +//***************************************************************************** +#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL14 register. +// +//***************************************************************************** +#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL14_STALL 0x00000010 // Send STALL +#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL14_ERROR 0x00000004 // Error +#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH14 register. +// +//***************************************************************************** +#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH14_MODE 0x00000020 // Mode +#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH14_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP14 register. +// +//***************************************************************************** +#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL14 register. +// +//***************************************************************************** +#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL14_STALL 0x00000020 // Send STALL +#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL14_OVER 0x00000004 // Overrun +#define USB_RXCSRL14_ERROR 0x00000004 // Error +#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH14 register. +// +//***************************************************************************** +#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH14_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT14_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE14 register. +// +//***************************************************************************** +#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL14_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL14_TXPOLL_S \ + 0 +#define USB_TXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE14 register. +// +//***************************************************************************** +#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL14_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL14_TXPOLL_S \ + 0 +#define USB_RXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP15 register. +// +//***************************************************************************** +#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL15 register. +// +//***************************************************************************** +#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL15_STALL 0x00000010 // Send STALL +#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL15_ERROR 0x00000004 // Error +#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH15 register. +// +//***************************************************************************** +#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH15_MODE 0x00000020 // Mode +#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH15_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP15 register. +// +//***************************************************************************** +#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL15 register. +// +//***************************************************************************** +#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL15_STALL 0x00000020 // Send STALL +#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL15_ERROR 0x00000004 // Error +#define USB_RXCSRL15_OVER 0x00000004 // Overrun +#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH15 register. +// +//***************************************************************************** +#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH15_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT15_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE15 register. +// +//***************************************************************************** +#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL15_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL15_NAKLMT_S \ + 0 +#define USB_TXINTERVAL15_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE15 register. +// +//***************************************************************************** +#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL15_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL15_TXPOLL_S \ + 0 +#define USB_RXINTERVAL15_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT10_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT10_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT11_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT11_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT12_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT12_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT13_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT13_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT14_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT14_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT15_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT15_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_TXFIFOADD register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_RXFIFOADD register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0 + +#endif + +#endif // __HW_USB_H__ diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.c b/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.c new file mode 100644 index 00000000000..a58927013e4 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.c @@ -0,0 +1,214 @@ +//########################################################################### +// +// FILE: cmdline.c +// +// TITLE: Functions to help with processing command lines. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup cmdline_api +//! @{ +// +//***************************************************************************** + +// +// Included Files +// +#include +#include +#include +#include "utils/cmdline.h" + +// +// Defines the maximum number of arguments that can be parsed. +// +#ifndef CMDLINE_MAX_ARGS +#define CMDLINE_MAX_ARGS 8 +#endif + +// +// An array to hold the pointers to the command line arguments. +// +static char *g_ppcArgv[CMDLINE_MAX_ARGS + 1]; + +//***************************************************************************** +// +//! Process a command line string into arguments and execute the command. +//! +//! \param pcCmdLine points to a string that contains a command line that was +//! obtained by an application by some means. +//! +//! This function will take the supplied command line string and break it up +//! into individual arguments. The first argument is treated as a command and +//! is searched for in the command table. If the command is found, then the +//! command function is called and all of the command line arguments are passed +//! in the normal argc, argv form. +//! +//! The command table is contained in an array named g_psCmdTable +//! containing tCmdLineEntry structures which must be provided by the +//! application. The array must be terminated with an entry whose \b pcCmd +//! field contains a NULL pointer. +//! +//! \return Returns \b CMDLINE_BAD_CMD if the command is not found, +//! \b CMDLINE_TOO_MANY_ARGS if there are more arguments than can be parsed. +//! Otherwise it returns the code that was returned by the command function. +// +//***************************************************************************** +int +CmdLineProcess(char *pcCmdLine) +{ + char *pcChar; + uint_fast8_t ui8Argc; + bool bFindArg = true; + tCmdLineEntry *psCmdEntry; + + // + // Initialize the argument counter, and point to the beginning of the + // command line string. + // + ui8Argc = 0; + pcChar = pcCmdLine; + + // + // Advance through the command line until a zero character is found. + // + while(*pcChar) + { + // + // If there is a space, then replace it with a zero, and set the flag + // to search for the next argument. + // + if(*pcChar == ' ') + { + *pcChar = 0; + bFindArg = true; + } + + // + // Otherwise it is not a space, so it must be a character that is part + // of an argument. + // + else + { + // + // If bFindArg is set, then that means we are looking for the start + // of the next argument. + // + if(bFindArg) + { + // + // As long as the maximum number of arguments has not been + // reached, then save the pointer to the start of this new arg + // in the argv array, and increment the count of args, argc. + // + if(ui8Argc < CMDLINE_MAX_ARGS) + { + g_ppcArgv[ui8Argc] = pcChar; + ui8Argc++; + bFindArg = false; + } + + // + // The maximum number of arguments has been reached so return + // the error. + // + else + { + return(CMDLINE_TOO_MANY_ARGS); + } + } + } + + // + // Advance to the next character in the command line. + // + pcChar++; + } + + // + // If one or more arguments was found, then process the command. + // + if(ui8Argc) + { + // + // Start at the beginning of the command table, to look for a matching + // command. + // + psCmdEntry = &g_psCmdTable[0]; + + // + // Search through the command table until a null command string is + // found, which marks the end of the table. + // + while(psCmdEntry->pcCmd) + { + // + // If this command entry command string matches argv[0], then call + // the function for this command, passing the command line + // arguments. + // + if(!strcmp(g_ppcArgv[0], psCmdEntry->pcCmd)) + { + return(psCmdEntry->pfnCmd(ui8Argc, g_ppcArgv)); + } + + // + // Not found, so advance to the next entry. + // + psCmdEntry++; + } + } + + // + // Fall through to here means that no matching command was found, so return + // an error. + // + return(CMDLINE_BAD_CMD); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.h b/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.h new file mode 100644 index 00000000000..47c3fa1b23b --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/cmdline.h @@ -0,0 +1,143 @@ +//########################################################################### +// +// FILE: cmdline.h +// +// TITLE: Prototypes for command line processing functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __CMDLINE_H__ +#define __CMDLINE_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup cmdline_api +//! @{ +// +//***************************************************************************** + +// +//! Defines the value that is returned if the command is not found. +// +#define CMDLINE_BAD_CMD (-1) + +// +//! Defines the value that is returned if there are too many arguments. +// +#define CMDLINE_TOO_MANY_ARGS (-2) + +// +//! Defines the value that is returned if there are too few arguments. +// +#define CMDLINE_TOO_FEW_ARGS (-3) + +// +//! Defines the value that is returned if an argument is invalid. +// +#define CMDLINE_INVALID_ARG (-4) + +// +// Command line function callback type. +// +typedef int (*pfnCmdLine)(int argc, char *argv[]); + +// +//! Structure for an entry in the command list table. +// +typedef struct +{ + // + //! A pointer to a string containing the name of the command. + // + const char *pcCmd; + + // + //! A function pointer to the implementation of the command. + // + pfnCmdLine pfnCmd; + + // + //! A pointer to a string of brief help text for the command. + // + const char *pcHelp; +} +tCmdLineEntry; + +// +//! This is the command table that must be provided by the application. The +//! last element of the array must be a structure whose pcCmd field contains +//! a NULL pointer. +// +extern tCmdLineEntry g_psCmdTable[]; + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +// +// Function Prototypes +// +extern int CmdLineProcess(char *pcCmdLine); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CMDLINE_H__ + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.c b/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.c new file mode 100644 index 00000000000..07354f184df --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.c @@ -0,0 +1,1773 @@ +//########################################################################### +// +// FILE: uartstdio.c +// +// TITLE: Utility driver to provide simple UART console functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_uart.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/rom.h" +#include "driverlib/rom_map.h" +#include "driverlib/sysctl.h" +#include "driverlib/uart.h" +#include "utils/uartstdio.h" + +//***************************************************************************** +// +//! \addtogroup uartstdio_api +//! @{ +// +//***************************************************************************** + +// +// If buffered mode is defined, set aside RX and TX buffers and read/write +// pointers to control them. +// +#ifdef UART_BUFFERED + +// +// This global controls whether or not we are echoing characters back to the +// transmitter. By default, echo is enabled but if using this module as a +// convenient method of implementing a buffered serial interface over which +// you will be running an application protocol, you are likely to want to +// disable echo by calling UARTEchoSet(false). +// +static bool g_bDisableEcho; + +// +// Output ring buffer. Buffer is full if g_ui32UARTTxReadIndex is one ahead of +// g_ui32UARTTxWriteIndex. Buffer is empty if the two indices are the same. +// +static unsigned char g_pcUARTTxBuffer[UART_TX_BUFFER_SIZE]; +static volatile uint32_t g_ui32UARTTxWriteIndex = 0; +static volatile uint32_t g_ui32UARTTxReadIndex = 0; + +// +// Input ring buffer. Buffer is full if g_ui32UARTTxReadIndex is one ahead of +// g_ui32UARTTxWriteIndex. Buffer is empty if the two indices are the same. +// +static unsigned char g_pcUARTRxBuffer[UART_RX_BUFFER_SIZE]; +static volatile uint32_t g_ui32UARTRxWriteIndex = 0; +static volatile uint32_t g_ui32UARTRxReadIndex = 0; + +// +// Macros to determine number of free and used bytes in the transmit buffer. +// +#define TX_BUFFER_USED (GetBufferCount(&g_ui32UARTTxReadIndex, \ + &g_ui32UARTTxWriteIndex, \ + UART_TX_BUFFER_SIZE)) +#define TX_BUFFER_FREE (UART_TX_BUFFER_SIZE - TX_BUFFER_USED) +#define TX_BUFFER_EMPTY (IsBufferEmpty(&g_ui32UARTTxReadIndex, \ + &g_ui32UARTTxWriteIndex)) +#define TX_BUFFER_FULL (IsBufferFull(&g_ui32UARTTxReadIndex, \ + &g_ui32UARTTxWriteIndex, \ + UART_TX_BUFFER_SIZE)) +#define ADVANCE_TX_BUFFER_INDEX(Index) \ + (Index) = ((Index) + 1) % UART_TX_BUFFER_SIZE + +// +// Macros to determine number of free and used bytes in the receive buffer. +// +#define RX_BUFFER_USED (GetBufferCount(&g_ui32UARTRxReadIndex, \ + &g_ui32UARTRxWriteIndex, \ + UART_RX_BUFFER_SIZE)) +#define RX_BUFFER_FREE (UART_RX_BUFFER_SIZE - RX_BUFFER_USED) +#define RX_BUFFER_EMPTY (IsBufferEmpty(&g_ui32UARTRxReadIndex, \ + &g_ui32UARTRxWriteIndex)) +#define RX_BUFFER_FULL (IsBufferFull(&g_ui32UARTRxReadIndex, \ + &g_ui32UARTRxWriteIndex, \ + UART_RX_BUFFER_SIZE)) +#define ADVANCE_RX_BUFFER_INDEX(Index) \ + (Index) = ((Index) + 1) % UART_RX_BUFFER_SIZE +#endif + +// +// The base address of the chosen UART. +// +static uint32_t g_ui32Base = 0; + +// +// A mapping from an integer between 0 and 15 to its ASCII character +// equivalent. +// +static const char * const g_pcHex = "0123456789abcdef"; + +// +// The list of possible base addresses for the console UART. +// +static const uint32_t g_ui32UARTBase[4] = +{ + UARTA_BASE, UARTB_BASE, UARTC_BASE, UARTD_BASE +}; + +#ifdef UART_BUFFERED +// +// The list of possible interrupts for the console UART. +// +static const uint32_t g_ui32UARTInt[3] = +{ + INT_UART0, INT_UART1, INT_UART2 +}; + +// +// The port number in use. +// +static uint32_t g_ui32PortNum; +#endif + +// +// The list of UART peripherals. +// +static const uint32_t g_ui32UARTPeriph[3] = +{ + SYSCTL_PERIPH_SCI1, SYSCTL_PERIPH_SCI2, SYSCTL_PERIPH_SCI3 +}; + +//***************************************************************************** +// +//! Determines whether the ring buffer whose pointers and size are provided +//! is full or not. +//! +//! \param pui32Read points to the read index for the buffer. +//! \param pui32Write points to the write index for the buffer. +//! \param ui32Size is the size of the buffer in bytes. +//! +//! This function is used to determine whether or not a given ring buffer is +//! full. The structure of the code is specifically to ensure that we do not +//! see warnings from the compiler related to the order of volatile accesses +//! being undefined. +//! +//! \return Returns \b true if the buffer is full or \b false otherwise. +// +//***************************************************************************** +#ifdef UART_BUFFERED +static bool +IsBufferFull(volatile uint32_t *pui32Read, + volatile uint32_t *pui32Write, uint32_t ui32Size) +{ + uint32_t ui32Write; + uint32_t ui32Read; + + ui32Write = *pui32Write; + ui32Read = *pui32Read; + + return((((ui32Write + 1) % ui32Size) == ui32Read) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Determines whether the ring buffer whose pointers and size are provided +//! is empty or not. +//! +//! \param pui32Read points to the read index for the buffer. +//! \param pui32Write points to the write index for the buffer. +//! +//! This function is used to determine whether or not a given ring buffer is +//! empty. The structure of the code is specifically to ensure that we do not +//! see warnings from the compiler related to the order of volatile accesses +//! being undefined. +//! +//! \return Returns \b true if the buffer is empty or \b false otherwise. +// +//***************************************************************************** +#ifdef UART_BUFFERED +static bool +IsBufferEmpty(volatile uint32_t *pui32Read, + volatile uint32_t *pui32Write) +{ + uint32_t ui32Write; + uint32_t ui32Read; + + ui32Write = *pui32Write; + ui32Read = *pui32Read; + + return((ui32Write == ui32Read) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Determines the number of bytes of data contained in a ring buffer. +//! +//! \param pui32Read points to the read index for the buffer. +//! \param pui32Write points to the write index for the buffer. +//! \param ui32Size is the size of the buffer in bytes. +//! +//! This function is used to determine how many bytes of data a given ring +//! buffer currently contains. The structure of the code is specifically to +//! ensure that we do not see warnings from the compiler related to the order +//! of volatile accesses being undefined. +//! +//! \return Returns the number of bytes of data currently in the buffer. +// +//***************************************************************************** +#ifdef UART_BUFFERED +static uint32_t +GetBufferCount(volatile uint32_t *pui32Read, + volatile uint32_t *pui32Write, uint32_t ui32Size) +{ + uint32_t ui32Write; + uint32_t ui32Read; + + ui32Write = *pui32Write; + ui32Read = *pui32Read; + + return((ui32Write >= ui32Read) ? (ui32Write - ui32Read) : + (ui32Size - (ui32Read - ui32Write))); +} +#endif + +//***************************************************************************** +// +// Take as many bytes from the transmit buffer as we have space for and move +// them into the UART transmit FIFO. +// +//***************************************************************************** +#ifdef UART_BUFFERED +static void +UARTPrimeTransmit(uint32_t ui32Base) +{ + // + // Do we have any data to transmit? + // + if(!TX_BUFFER_EMPTY) + { + // + // Disable the UART interrupt. If we don't do this there is a race + // condition which can cause the read index to be corrupted. + // + MAP_IntDisable(g_ui32UARTInt[g_ui32PortNum]); + + // + // Yes - take some characters out of the transmit buffer and feed + // them to the UART transmit FIFO. + // + while(MAP_UARTSpaceAvail(ui32Base) && !TX_BUFFER_EMPTY) + { + MAP_UARTCharPutNonBlocking(ui32Base, + g_pcUARTTxBuffer[g_ui32UARTTxReadIndex]); + ADVANCE_TX_BUFFER_INDEX(g_ui32UARTTxReadIndex); + } + + // + // Reenable the UART interrupt. + // + MAP_IntEnable(g_ui32UARTInt[g_ui32PortNum]); + } +} +#endif + +//***************************************************************************** +// +//! Configures the UART console. +//! +//! \param ui32PortNum is the number of UART port to use for the serial console +//! (0-2) +//! \param ui32Baud is the bit rate that the UART is to be configured to use. +//! \param ui32SrcClock is the frequency of the source clock for the UART +//! module. +//! +//! This function will configure the specified serial port to be used as a +//! serial console. The serial parameters are set to the baud rate +//! specified by the \e ui32Baud parameter and use 8 bit, no parity, and 1 stop +//! bit. +//! +//! This function must be called prior to using any of the other UART console +//! functions: UARTprintf() or UARTgets(). This function assumes that the +//! caller has previously configured the relevant UART pins for operation as a +//! UART rather than as GPIOs. +//! +//! \return None. +// +//***************************************************************************** +void +UARTStdioConfig(uint32_t ui32PortNum, uint32_t ui32Baud, uint32_t ui32SrcClock) +{ + // + // Check the arguments. + // + ASSERT((ui32PortNum == 0) || (ui32PortNum == 1) || + (ui32PortNum == 2)); + +#ifdef UART_BUFFERED + // + // In buffered mode, we only allow a single instance to be opened. + // + ASSERT(g_ui32Base == 0); +#endif + + // + // Check to make sure the UART peripheral is present. + // + if(!MAP_SysCtlPeripheralPresent(g_ui32UARTPeriph[ui32PortNum])) + { + return; + } + + // + // Select the base address of the UART. + // + g_ui32Base = g_ui32UARTBase[ui32PortNum]; + + // + // Enable the UART peripheral for use. + // + MAP_SysCtlPeripheralEnable(g_ui32UARTPeriph[ui32PortNum]); + + // + // Configure the UART for 115200, n, 8, 1 + // + MAP_UARTConfigSetExpClk(g_ui32Base, ui32SrcClock, ui32Baud, + (UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | + UART_CONFIG_WLEN_8)); + +#ifdef UART_BUFFERED + // + // Set the UART to interrupt whenever the TX FIFO is almost empty or + // when any character is received. + // + MAP_UARTFIFOLevelSet(g_ui32Base, UART_FIFO_TX1_8, UART_FIFO_RX1_8); + + // + // Flush both the buffers. + // + UARTFlushRx(); + UARTFlushTx(true); + + // + // Remember which interrupt we are dealing with. + // + g_ui32PortNum = ui32PortNum; + + // + // We are configured for buffered output so enable the master interrupt + // for this UART and the receive interrupts. We don't actually enable the + // transmit interrupt in the UART itself until some data has been placed + // in the transmit buffer. + // + MAP_UARTIntDisable(g_ui32Base, 0xFFFFFFFF); + MAP_UARTIntEnable(g_ui32Base, UART_INT_RX | UART_INT_RT); + MAP_IntEnable(g_ui32UARTInt[ui32PortNum]); +#endif + + // + // Enable the UART operation. + // + MAP_UARTEnable(g_ui32Base); +} + +//***************************************************************************** +// +//! Writes a string of characters to the UART output. +//! +//! \param pcBuf points to a buffer containing the string to transmit. +//! \param ui32Len is the length of the string to transmit. +//! +//! This function will transmit the string to the UART output. The number of +//! characters transmitted is determined by the \e ui32Len parameter. This +//! function does no interpretation or translation of any characters. Since +//! the output is sent to a UART, any LF (/n) characters encountered will be +//! replaced with a CRLF pair. +//! +//! Besides using the \e ui32Len parameter to stop transmitting the string, if +//! a null character (0) is encountered, then no more characters will be +//! transmitted and the function will return. +//! +//! In non-buffered mode, this function is blocking and will not return until +//! all the characters have been written to the output FIFO. In buffered mode, +//! the characters are written to the UART transmit buffer and the call returns +//! immediately. If insufficient space remains in the transmit buffer, +//! additional characters are discarded. +//! +//! \return Returns the count of characters written. +// +//***************************************************************************** +int +UARTwrite(const char *pcBuf, uint32_t ui32Len) +{ +#ifdef UART_BUFFERED + unsigned int uIdx; + + // + // Check for valid arguments. + // + ASSERT(pcBuf != 0); + ASSERT(g_ui32Base != 0); + + // + // Send the characters + // + for(uIdx = 0; uIdx < ui32Len; uIdx++) + { + // + // If the character to the UART is \n, then add a \r before it so that + // \n is translated to \n\r in the output. + // + if(pcBuf[uIdx] == '\n') + { + if(!TX_BUFFER_FULL) + { + g_pcUARTTxBuffer[g_ui32UARTTxWriteIndex] = '\r'; + ADVANCE_TX_BUFFER_INDEX(g_ui32UARTTxWriteIndex); + } + else + { + // + // Buffer is full - discard remaining characters and return. + // + break; + } + } + + // + // Send the character to the UART output. + // + if(!TX_BUFFER_FULL) + { + g_pcUARTTxBuffer[g_ui32UARTTxWriteIndex] = pcBuf[uIdx]; + ADVANCE_TX_BUFFER_INDEX(g_ui32UARTTxWriteIndex); + } + else + { + // + // Buffer is full - discard remaining characters and return. + // + break; + } + } + + // + // If we have anything in the buffer, make sure that the UART is set + // up to transmit it. + // + if(!TX_BUFFER_EMPTY) + { + UARTPrimeTransmit(g_ui32Base); + MAP_UARTIntEnable(g_ui32Base, UART_INT_TX); + } + + // + // Return the number of characters written. + // + return(uIdx); +#else + unsigned int uIdx; + + // + // Check for valid UART base address, and valid arguments. + // + ASSERT(g_ui32Base != 0); + ASSERT(pcBuf != 0); + + // + // Send the characters + // + for(uIdx = 0; uIdx < ui32Len; uIdx++) + { + // + // If the character to the UART is \n, then add a \r before it so that + // \n is translated to \n\r in the output. + // + if(pcBuf[uIdx] == '\n') + { + MAP_UARTCharPut(g_ui32Base, '\r'); + } + + // + // Send the character to the UART output. + // + MAP_UARTCharPut(g_ui32Base, pcBuf[uIdx]); + } + + // + // Return the number of characters written. + // + return(uIdx); +#endif +} + +//***************************************************************************** +// +//! A simple UART based get string function, with some line processing. +//! +//! \param pcBuf points to a buffer for the incoming string from the UART. +//! \param ui32Len is the length of the buffer for storage of the string, +//! including the trailing 0. +//! +//! This function will receive a string from the UART input and store the +//! characters in the buffer pointed to by \e pcBuf. The characters will +//! continue to be stored until a termination character is received. The +//! termination characters are CR, LF, or ESC. A CRLF pair is treated as a +//! single termination character. The termination characters are not stored in +//! the string. The string will be terminated with a 0 and the function will +//! return. +//! +//! In both buffered and unbuffered modes, this function will block until +//! a termination character is received. If non-blocking operation is required +//! in buffered mode, a call to UARTPeek() may be made to determine whether +//! a termination character already exists in the receive buffer prior to +//! calling UARTgets(). +//! +//! Since the string will be null terminated, the user must ensure that the +//! buffer is sized to allow for the additional null character. +//! +//! \return Returns the count of characters that were stored, not including +//! the trailing 0. +// +//***************************************************************************** +int +UARTgets(char *pcBuf, uint32_t ui32Len) +{ +#ifdef UART_BUFFERED + uint32_t ui32Count = 0; + int8_t cChar; + + // + // Check the arguments. + // + ASSERT(pcBuf != 0); + ASSERT(ui32Len != 0); + ASSERT(g_ui32Base != 0); + + // + // Adjust the length back by 1 to leave space for the trailing + // null terminator. + // + ui32Len--; + + // + // Process characters until a newline is received. + // + while(1) + { + // + // Read the next character from the receive buffer. + // + if(!RX_BUFFER_EMPTY) + { + cChar = g_pcUARTRxBuffer[g_ui32UARTRxReadIndex]; + ADVANCE_RX_BUFFER_INDEX(g_ui32UARTRxReadIndex); + + // + // See if a newline or escape character was received. + // + if((cChar == '\r') || (cChar == '\n') || (cChar == 0x1b)) + { + // + // Stop processing the input and end the line. + // + break; + } + + // + // Process the received character as long as we are not at the end + // of the buffer. If the end of the buffer has been reached then + // all additional characters are ignored until a newline is + // received. + // + if(ui32Count < ui32Len) + { + // + // Store the character in the caller supplied buffer. + // + pcBuf[ui32Count] = cChar; + + // + // Increment the count of characters received. + // + ui32Count++; + } + } + } + + // + // Add a null termination to the string. + // + pcBuf[ui32Count] = 0; + + // + // Return the count of int8_ts in the buffer, not counting the trailing 0. + // + return(ui32Count); +#else + uint32_t ui32Count = 0; + int8_t cChar; + static int8_t bLastWasCR = 0; + + // + // Check the arguments. + // + ASSERT(pcBuf != 0); + ASSERT(ui32Len != 0); + ASSERT(g_ui32Base != 0); + + // + // Adjust the length back by 1 to leave space for the trailing + // null terminator. + // + ui32Len--; + + // + // Process characters until a newline is received. + // + while(1) + { + // + // Read the next character from the console. + // + cChar = MAP_UARTCharGet(g_ui32Base); + + // + // See if the backspace key was pressed. + // + if(cChar == '\b') + { + // + // If there are any characters already in the buffer, then delete + // the last. + // + if(ui32Count) + { + // + // Rub out the previous character. + // + UARTwrite("\b \b", 3); + + // + // Decrement the number of characters in the buffer. + // + ui32Count--; + } + + // + // Skip ahead to read the next character. + // + continue; + } + + // + // If this character is LF and last was CR, then just gobble up the + // character because the EOL processing was taken care of with the CR. + // + if((cChar == '\n') && bLastWasCR) + { + bLastWasCR = 0; + continue; + } + + // + // See if a newline or escape character was received. + // + if((cChar == '\r') || (cChar == '\n') || (cChar == 0x1b)) + { + // + // If the character is a CR, then it may be followed by a LF which + // should be paired with the CR. So remember that a CR was + // received. + // + if(cChar == '\r') + { + bLastWasCR = 1; + } + + // + // Stop processing the input and end the line. + // + break; + } + + // + // Process the received character as long as we are not at the end of + // the buffer. If the end of the buffer has been reached then all + // additional characters are ignored until a newline is received. + // + if(ui32Count < ui32Len) + { + // + // Store the character in the caller supplied buffer. + // + pcBuf[ui32Count] = cChar; + + // + // Increment the count of characters received. + // + ui32Count++; + + // + // Reflect the character back to the user. + // + MAP_UARTCharPut(g_ui32Base, cChar); + } + } + + // + // Add a null termination to the string. + // + pcBuf[ui32Count] = 0; + + // + // Send a CRLF pair to the terminal to end the line. + // + UARTwrite("\r\n", 2); + + // + // Return the count of int8_ts in the buffer, not counting the trailing 0. + // + return(ui32Count); +#endif +} + +//***************************************************************************** +// +//! Read a single character from the UART, blocking if necessary. +//! +//! This function will receive a single character from the UART and store it at +//! the supplied address. +//! +//! In both buffered and unbuffered modes, this function will block until a +//! character is received. If non-blocking operation is required in buffered +//! mode, a call to UARTRxAvail() may be made to determine whether any +//! characters are currently available for reading. +//! +//! \return Returns the character read. +// +//***************************************************************************** +unsigned char +UARTgetc(void) +{ +#ifdef UART_BUFFERED + unsigned char cChar; + + // + // Wait for a character to be received. + // + while(RX_BUFFER_EMPTY) + { + // + // Block waiting for a character to be received (if the buffer is + // currently empty). + // + } + + // + // Read a character from the buffer. + // + cChar = g_pcUARTRxBuffer[g_ui32UARTRxReadIndex]; + ADVANCE_RX_BUFFER_INDEX(g_ui32UARTRxReadIndex); + + // + // Return the character to the caller. + // + return(cChar); +#else + // + // Block until a character is received by the UART then return it to + // the caller. + // + return(MAP_UARTCharGet(g_ui32Base)); +#endif +} + +//***************************************************************************** +// +//! A simple UART based vprintf function supporting \%c, \%d, \%p, \%s, \%u, +//! \%x, and \%X. +//! +//! \param pcString is the format string. +//! \param vaArgP is a variable argument list pointer whose content will depend +//! upon the format string passed in \e pcString. +//! +//! This function is very similar to the C library vprintf() function. +//! All of its output will be sent to the UART. Only the following formatting +//! characters are supported: +//! +//! - \%c to print a character +//! - \%d or \%i to print a decimal value +//! - \%l to print a long decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%p to print a pointer as a hexadecimal value +//! - \%\% to print out a \% character +//! +//! For \%s, \%d, \%i, \%u, \%p, \%x, and \%X, an optional number may reside +//! between the \% and the format character, which specifies the minimum number +//! of characters to use for that value; if preceded by a 0 then the extra +//! characters will be filled with zeros instead of spaces. For example, +//! ``\%8d'' will use eight characters to print the decimal value with spaces +//! added to reach eight; ``\%08d'' will use eight characters as well but will +//! add zeroes instead of spaces. +//! +//! The type of the arguments in the variable arguments list must match the +//! requirements of the format string. For example, if an integer was passed +//! where a string was expected, an error of some kind will most likely occur. +//! +//! \return None. +// +//***************************************************************************** +void +UARTvprintf(const char *pcString, va_list vaArgP) +{ + uint32_t ui32Idx, ui32Value, ui32Pos, ui32Count, ui32Base, ui32Neg; + char *pcStr, pcBuf[16], cFill; + + // + // Check the arguments. + // + ASSERT(pcString != 0); + + // + // Loop while there are more characters in the string. + // + while(*pcString) + { + // + // Find the first non-% character, or the end of the string. + // + for(ui32Idx = 0; + (pcString[ui32Idx] != '%') && (pcString[ui32Idx] != '\0'); + ui32Idx++) + { + } + + // + // Write this portion of the string. + // + UARTwrite(pcString, ui32Idx); + + // + // Skip the portion of the string that was written. + // + pcString += ui32Idx; + + // + // See if the next character is a %. + // + if(*pcString == '%') + { + // + // Skip the %. + // + pcString++; + + // + // Set the digit count to zero, and the fill character to space + // (in other words, to the defaults). + // + ui32Count = 0; + cFill = ' '; + + // + // It may be necessary to get back here to process more characters. + // Goto's aren't pretty, but effective. I feel extremely dirty for + // using not one but two of the beasts. + // +again: + + // + // Determine how to handle the next character. + // + switch(*pcString++) + { + // + // Handle the digit characters. + // + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + // + // If this is a zero, and it is the first digit, then the + // fill character is a zero instead of a space. + // + if((pcString[-1] == '0') && (ui32Count == 0)) + { + cFill = '0'; + } + + // + // Update the digit count. + // + ui32Count *= 10; + ui32Count += pcString[-1] - '0'; + + // + // Get the next character. + // + goto again; + } + + // + // Handle the %c command. + // + case 'c': + { + // + // Get the value from the varargs. + // + ui32Value = va_arg(vaArgP, uint32_t); + + // + // Print out the character. + // + UARTwrite((char *)&ui32Value, 1); + + // + // This command has been handled. + // + break; + } + + // + // Handle the %d and %i commands. + // + case 'd': + case 'i': + { + // + // Get the value from the varargs. + // + ui32Value = va_arg(vaArgP, uint16_t); + + // + // Reset the buffer position. + // + ui32Pos = 0; + + // + // If the value is negative, make it positive and indicate + // that a minus sign is needed. + // + if((int32_t)ui32Value < 0) + { + // + // Make the value positive. + // + ui32Value = -(int32_t)ui32Value; + + // + // Indicate that the value is negative. + // + ui32Neg = 1; + } + else + { + // + // Indicate that the value is positive so that a minus + // sign isn't inserted. + // + ui32Neg = 0; + } + + // + // Set the base to 10. + // + ui32Base = 10; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %l command. + // + case 'l': + { + // + // Get the value from the varargs. + // + ui32Value = va_arg(vaArgP, uint32_t); + + // + // Reset the buffer position. + // + ui32Pos = 0; + + // + // If the value is negative, make it positive and indicate + // that a minus sign is needed. + // + if((int32_t)ui32Value < 0) + { + // + // Make the value positive. + // + ui32Value = -(int32_t)ui32Value; + + // + // Indicate that the value is negative. + // + ui32Neg = 1; + } + else + { + // + // Indicate that the value is positive so that a minus + // sign isn't inserted. + // + ui32Neg = 0; + } + + // + // Set the base to 10. + // + ui32Base = 10; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %s command. + // + case 's': + { + // + // Get the string pointer from the varargs. + // + pcStr = va_arg(vaArgP, char *); + + // + // Determine the length of the string. + // + for(ui32Idx = 0; pcStr[ui32Idx] != '\0'; ui32Idx++) + { + } + + // + // Write the string. + // + UARTwrite(pcStr, ui32Idx); + + // + // Write any required padding spaces + // + if(ui32Count > ui32Idx) + { + ui32Count -= ui32Idx; + while(ui32Count--) + { + UARTwrite(" ", 1); + } + } + + // + // This command has been handled. + // + break; + } + + // + // Handle the %u command. + // + case 'u': + { + // + // Get the value from the varargs. + // + ui32Value = va_arg(vaArgP, uint32_t); + + // + // Reset the buffer position. + // + ui32Pos = 0; + + // + // Set the base to 10. + // + ui32Base = 10; + + // + // Indicate that the value is positive so that a minus sign + // isn't inserted. + // + ui32Neg = 0; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %x and %X commands. Note that they are treated + // identically; in other words, %X will use lower case letters + // for a-f instead of the upper case letters it should use. We + // also alias %p to %x. + // + case 'x': + case 'X': + case 'p': + { + // + // Get the value from the varargs. + // + ui32Value = va_arg(vaArgP, uint32_t); + + // + // Reset the buffer position. + // + ui32Pos = 0; + + // + // Set the base to 16. + // + ui32Base = 16; + + // + // Indicate that the value is positive so that a minus sign + // isn't inserted. + // + ui32Neg = 0; + + // + // Determine the number of digits in the string version of + // the value. + // +convert: + for(ui32Idx = 1; + (((ui32Idx * ui32Base) <= ui32Value) && + (((ui32Idx * ui32Base) / ui32Base) == ui32Idx)); + ui32Idx *= ui32Base, ui32Count--) + { + } + + // + // If the value is negative, reduce the count of padding + // characters needed. + // + if(ui32Neg) + { + ui32Count--; + } + + // + // If the value is negative and the value is padded with + // zeros, then place the minus sign before the padding. + // + if(ui32Neg && (cFill == '0')) + { + // + // Place the minus sign in the output buffer. + // + pcBuf[ui32Pos++] = '-'; + + // + // The minus sign has been placed, so turn off the + // negative flag. + // + ui32Neg = 0; + } + + // + // Provide additional padding at the beginning of the + // string conversion if needed. + // + if((ui32Count > 1) && (ui32Count < 16)) + { + for(ui32Count--; ui32Count; ui32Count--) + { + pcBuf[ui32Pos++] = cFill; + } + } + + // + // If the value is negative, then place the minus sign + // before the number. + // + if(ui32Neg) + { + // + // Place the minus sign in the output buffer. + // + pcBuf[ui32Pos++] = '-'; + } + + // + // Convert the value into a string. + // + for(; ui32Idx; ui32Idx /= ui32Base) + { + pcBuf[ui32Pos++] = + g_pcHex[(ui32Value / ui32Idx) % ui32Base]; + } + + // + // Write the string. + // + UARTwrite(pcBuf, ui32Pos); + + // + // This command has been handled. + // + break; + } + + // + // Handle the %% command. + // + case '%': + { + // + // Simply write a single %. + // + UARTwrite(pcString - 1, 1); + + // + // This command has been handled. + // + break; + } + + // + // Handle all other commands. + // + default: + { + // + // Indicate an error. + // + UARTwrite("ERROR", 5); + + // + // This command has been handled. + // + break; + } + } + } + } +} + +//***************************************************************************** +// +//! A simple UART based printf function supporting \%c, \%d, \%p, \%s, \%u, +//! \%x, and \%X. +//! +//! \param pcString is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! format string. +//! +//! This function is very similar to the C library fprintf() function. +//! All of its output will be sent to the UART. Only the following formatting +//! characters are supported: +//! +//! - \%c to print a character +//! - \%d or \%i to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%p to print a pointer as a hexadecimal value +//! - \%\% to print out a \% character +//! +//! For \%s, \%d, \%i, \%u, \%p, \%x, and \%X, an optional number may reside +//! between the \% and the format character, which specifies the minimum number +//! of characters to use for that value; if preceded by a 0 then the extra +//! characters will be filled with zeros instead of spaces. For example, +//! ``\%8d'' will use eight characters to print the decimal value with spaces +//! added to reach eight; ``\%08d'' will use eight characters as well but will +//! add zeroes instead of spaces. +//! +//! The type of the arguments after \e pcString must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! \return None. +// +//***************************************************************************** +void +UARTprintf(const char *pcString, ...) +{ + va_list vaArgP; + + // + // Start the varargs processing. + // + va_start(vaArgP, pcString); + + UARTvprintf(pcString, vaArgP); + + // + // We're finished with the varargs now. + // + va_end(vaArgP); +} + +//***************************************************************************** +// +//! Returns the number of bytes available in the receive buffer. +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to determine the number +//! of bytes of data currently available in the receive buffer. +//! +//! \return Returns the number of available bytes. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +int +UARTRxBytesAvail(void) +{ + return(RX_BUFFER_USED); +} +#endif + +#if defined(UART_BUFFERED) || defined(DOXYGEN) +//***************************************************************************** +// +//! Returns the number of bytes free in the transmit buffer. +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to determine the amount +//! of space currently available in the transmit buffer. +//! +//! \return Returns the number of free bytes. +// +//***************************************************************************** +int +UARTTxBytesFree(void) +{ + return(TX_BUFFER_FREE); +} +#endif + +//***************************************************************************** +// +//! Looks ahead in the receive buffer for a particular character. +//! +//! \param ucChar is the character that is to be searched for. +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to look ahead in the +//! receive buffer for a particular character and report its position if found. +//! It is typically used to determine whether a complete line of user input is +//! available, in which case ucChar should be set to CR ('\\r') which is used +//! as the line end marker in the receive buffer. +//! +//! \return Returns -1 to indicate that the requested character does not exist +//! in the receive buffer. Returns a non-negative number if the character was +//! found in which case the value represents the position of the first instance +//! of \e ucChar relative to the receive buffer read pointer. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +int +UARTPeek(unsigned char ucChar) +{ + int iCount; + int iAvail; + uint32_t ui32ReadIndex; + + // + // How many characters are there in the receive buffer? + // + iAvail = (int)RX_BUFFER_USED; + ui32ReadIndex = g_ui32UARTRxReadIndex; + + // + // Check all the unread characters looking for the one passed. + // + for(iCount = 0; iCount < iAvail; iCount++) + { + if(g_pcUARTRxBuffer[ui32ReadIndex] == ucChar) + { + // + // We found it so return the index + // + return(iCount); + } + else + { + // + // This one didn't match so move on to the next character. + // + ADVANCE_RX_BUFFER_INDEX(ui32ReadIndex); + } + } + + // + // If we drop out of the loop, we didn't find the character in the receive + // buffer. + // + return(-1); +} +#endif + +//***************************************************************************** +// +//! Flushes the receive buffer. +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to discard any data +//! received from the UART but not yet read using UARTgets(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +void +UARTFlushRx(void) +{ + uint32_t ui32Int; + + // + // Temporarily turn off interrupts. + // + ui32Int = MAP_IntMasterDisable(); + + // + // Flush the receive buffer. + // + g_ui32UARTRxReadIndex = 0; + g_ui32UARTRxWriteIndex = 0; + + // + // If interrupts were enabled when we turned them off, turn them + // back on again. + // + if(!ui32Int) + { + MAP_IntMasterEnable(); + } +} +#endif + +//***************************************************************************** +// +//! Flushes the transmit buffer. +//! +//! \param bDiscard indicates whether any remaining data in the buffer should +//! be discarded (\b true) or transmitted (\b false). +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to flush the transmit +//! buffer, either discarding or transmitting any data received via calls to +//! UARTprintf() that is waiting to be transmitted. On return, the transmit +//! buffer will be empty. +//! +//! \return None. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +void +UARTFlushTx(bool bDiscard) +{ + uint32_t ui32Int; + + // + // Should the remaining data be discarded or transmitted? + // + if(bDiscard) + { + // + // The remaining data should be discarded, so temporarily turn off + // interrupts. + // + ui32Int = MAP_IntMasterDisable(); + + // + // Flush the transmit buffer. + // + g_ui32UARTTxReadIndex = 0; + g_ui32UARTTxWriteIndex = 0; + + // + // If interrupts were enabled when we turned them off, turn them + // back on again. + // + if(!ui32Int) + { + MAP_IntMasterEnable(); + } + } + else + { + // + // Wait for all remaining data to be transmitted before returning. + // + while(!TX_BUFFER_EMPTY) + { + } + } +} +#endif + +//***************************************************************************** +// +//! Enables or disables echoing of received characters to the transmitter. +//! +//! \param bEnable must be set to \b true to enable echo or \b false to +//! disable it. +//! +//! This function, available only when the module is built to operate in +//! buffered mode using \b UART_BUFFERED, may be used to control whether or not +//! received characters are automatically echoed back to the transmitter. By +//! default, echo is enabled and this is typically the desired behavior if +//! the module is being used to support a serial command line. In applications +//! where this module is being used to provide a convenient, buffered serial +//! interface over which application-specific binary protocols are being run, +//! however, echo may be undesirable and this function can be used to disable +//! it. +//! +//! \return None. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +void +UARTEchoSet(bool bEnable) +{ + g_bDisableEcho = !bEnable; +} +#endif + +//***************************************************************************** +// +//! Handles UART interrupts. +//! +//! This function handles interrupts from the UART. It will copy data from the +//! transmit buffer to the UART transmit FIFO if space is available, and it +//! will copy data from the UART receive FIFO to the receive buffer if data is +//! available. +//! +//! \return None. +// +//***************************************************************************** +#if defined(UART_BUFFERED) || defined(DOXYGEN) +void +UARTStdioIntHandler(void) +{ + uint32_t ui32Ints; + int8_t cChar; + int32_t i32Char; + static bool bLastWasCR = false; + + // + // Get and clear the current interrupt source(s) + // + ui32Ints = MAP_UARTIntStatus(g_ui32Base, true); + MAP_UARTIntClear(g_ui32Base, ui32Ints); + + // + // Are we being interrupted because the TX FIFO has space available? + // + if(ui32Ints & UART_INT_TX) + { + // + // Move as many bytes as we can into the transmit FIFO. + // + UARTPrimeTransmit(g_ui32Base); + + // + // If the output buffer is empty, turn off the transmit interrupt. + // + if(TX_BUFFER_EMPTY) + { + MAP_UARTIntDisable(g_ui32Base, UART_INT_TX); + } + } + + // + // Are we being interrupted due to a received character? + // + if(ui32Ints & (UART_INT_RX | UART_INT_RT)) + { + // + // Get all the available characters from the UART. + // + while(MAP_UARTCharsAvail(g_ui32Base)) + { + // + // Read a character + // + i32Char = MAP_UARTCharGetNonBlocking(g_ui32Base); + cChar = (unsigned char)(i32Char & 0xFF); + + // + // If echo is disabled, we skip the various text filtering + // operations that would typically be required when supporting a + // command line. + // + if(!g_bDisableEcho) + { + // + // Handle backspace by erasing the last character in the + // buffer. + // + if(cChar == '\b') + { + // + // If there are any characters already in the buffer, then + // delete the last. + // + if(!RX_BUFFER_EMPTY) + { + // + // Rub out the previous character on the users + // terminal. + // + UARTwrite("\b \b", 3); + + // + // Decrement the number of characters in the buffer. + // + if(g_ui32UARTRxWriteIndex == 0) + { + g_ui32UARTRxWriteIndex = UART_RX_BUFFER_SIZE - 1; + } + else + { + g_ui32UARTRxWriteIndex--; + } + } + + // + // Skip ahead to read the next character. + // + continue; + } + + // + // If this character is LF and last was CR, then just gobble up + // the character since we already echoed the previous CR and we + // don't want to store 2 characters in the buffer if we don't + // need to. + // + if((cChar == '\n') && bLastWasCR) + { + bLastWasCR = false; + continue; + } + + // + // See if a newline or escape character was received. + // + if((cChar == '\r') || (cChar == '\n') || (cChar == 0x1b)) + { + // + // If the character is a CR, then it may be followed by an + // LF which should be paired with the CR. So remember that + // a CR was received. + // + if(cChar == '\r') + { + bLastWasCR = 1; + } + + // + // Regardless of the line termination character received, + // put a CR in the receive buffer as a marker telling + // UARTgets() where the line ends. We also send an + // additional LF to ensure that the local terminal echo + // receives both CR and LF. + // + cChar = '\r'; + UARTwrite("\n", 1); + } + } + + // + // If there is space in the receive buffer, put the character + // there, otherwise throw it away. + // + if(!RX_BUFFER_FULL) + { + // + // Store the new character in the receive buffer + // + g_pcUARTRxBuffer[g_ui32UARTRxWriteIndex] = + (unsigned char)(i32Char & 0xFF); + ADVANCE_RX_BUFFER_INDEX(g_ui32UARTRxWriteIndex); + + // + // If echo is enabled, write the character to the transmit + // buffer so that the user gets some immediate feedback. + // + if(!g_bDisableEcho) + { + UARTwrite((const char *)&cChar, 1); + } + } + } + + // + // If we wrote anything to the transmit buffer, make sure it actually + // gets transmitted. + // + UARTPrimeTransmit(g_ui32Base); + MAP_UARTIntEnable(g_ui32Base, UART_INT_TX); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.h b/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.h new file mode 100644 index 00000000000..1176091bbb3 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/uartstdio.h @@ -0,0 +1,107 @@ +//########################################################################### +// +// FILE: uartstdio.h +// +// TITLE: Prototypes for the UART console functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __UARTSTDIO_H__ +#define __UARTSTDIO_H__ + +// +// Included Files +// +#include + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// If built for buffered operation, the following labels define the sizes of +// the transmit and receive buffers respectively. +// +#ifdef UART_BUFFERED +#ifndef UART_RX_BUFFER_SIZE +#define UART_RX_BUFFER_SIZE 128 +#endif +#ifndef UART_TX_BUFFER_SIZE +#define UART_TX_BUFFER_SIZE 1024 +#endif +#endif + +// +// Function Prototypes +// +extern void UARTStdioConfig(uint32_t ui32Port, uint32_t ui32Baud, + uint32_t ui32SrcClock); +extern int UARTgets(char *pcBuf, uint32_t ui32Len); +extern unsigned char UARTgetc(void); +extern void UARTprintf(const char *pcString, ...); +extern void UARTvprintf(const char *pcString, va_list vaArgP); +extern int UARTwrite(const char *pcBuf, uint32_t ui32Len); +#ifdef UART_BUFFERED +extern int UARTPeek(unsigned char ucChar); +extern void UARTFlushTx(bool bDiscard); +extern void UARTFlushRx(void); +extern int UARTRxBytesAvail(void); +extern int UARTTxBytesFree(void); +extern void UARTEchoSet(bool bEnable); +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UARTSTDIO_H__ + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.c b/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.c new file mode 100644 index 00000000000..05e0ce7be2d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.c @@ -0,0 +1,1853 @@ +//########################################################################### +// +// FILE: ustdlib.c +// +// TITLE: Simple standard library functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include +#include +#include "driverlib/debug.h" +#include "utils/ustdlib.h" + +//***************************************************************************** +// +//! \addtogroup ustdlib_api +//! @{ +// +//***************************************************************************** + +// +// Globals +// + +// +// A mapping from an integer between 0 and 15 to its ASCII character +// equivalent. +// +static const char * const g_pcHex = "0123456789abcdef"; + +// +// Functions +// + +//***************************************************************************** +// +//! Copies a certain number of characters from one string to another. +//! +//! \param s1 is a pointer to the destination buffer into which characters +//! are to be copied. +//! \param s2 is a pointer to the string from which characters are to be +//! copied. +//! \param n is the number of characters to copy to the destination buffer. +//! +//! This function copies at most \e n characters from the string pointed to +//! by \e s2 into the buffer pointed to by \e s1. If the end of \e s2 is found +//! before \e n characters have been copied, remaining characters in \e s1 +//! will be padded with zeroes until \e n characters have been written. Note +//! that the destination string will only be NULL terminated if the number of +//! characters to be copied is greater than the length of \e s2. +//! +//! \return Returns \e s1. +// +//***************************************************************************** +char * +ustrncpy(char * restrict s1, const char * restrict s2, size_t n) +{ + size_t count; + + // + // Check the arguments. + // + ASSERT(s1); + ASSERT(s2); + + // + // Start at the beginning of the source string. + // + count = 0; + + // + // Copy the source string until we run out of source characters or + // destination space. + // + while(n && s2[count]) + { + s1[count] = s2[count]; + count++; + n--; + } + + // + // Pad the destination if we are not yet done. + // + while(n) + { + s1[count++] = (char)0; + n--; + } + + // + // Pass the destination pointer back to the caller. + // + return(s1); +} + +//***************************************************************************** +// +//! A simple vsnprintf function supporting \%c, \%d, \%p, \%s, \%u, \%x, and +//! \%X. +//! +//! \param s points to the buffer where the converted string is stored. +//! \param n is the size of the buffer. +//! \param format is the format string. +//! \param arg is the list of optional arguments, which depend on the +//! contents of the format string. +//! +//! This function is very similar to the C library vsnprintf() +//! function. Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d or \%i to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%p to print a pointer as a hexadecimal value +//! - \%\% to print out a \% character +//! +//! For \%d, \%i, \%p, \%s, \%u, \%x, and \%X, an optional number may reside +//! between the \% and the format character, which specifies the minimum number +//! of characters to use for that value; if preceded by a 0 then the extra +//! characters will be filled with zeros instead of spaces. For example, +//! ``\%8d'' will use eight characters to print the decimal value with spaces +//! added to reach eight; ``\%08d'' will use eight characters as well but will +//! add zeroes instead of spaces. +//! +//! The type of the arguments after \e format must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The \e n parameter limits the number of characters that will be +//! stored in the buffer pointed to by \e s to prevent the possibility of +//! a buffer overflow. The buffer size should be large enough to hold the +//! expected converted output string, including the null termination character. +//! +//! The function will return the number of characters that would be converted +//! as if there were no limit on the buffer size. Therefore it is possible for +//! the function to return a count that is greater than the specified buffer +//! size. If this happens, it means that the output was truncated. +//! +//! \return Returns the number of characters that were to be stored, not +//! including the NULL termination character, regardless of space in the +//! buffer. +// +//***************************************************************************** +int +uvsnprintf(char * restrict s, size_t n, const char * restrict format, + va_list arg) +{ + unsigned long ulIdx, ulValue, ulCount, ulBase, ulNeg; + char *pcStr, cFill; + int iConvertCount = 0; + + // + // Check the arguments. + // + ASSERT(s); + ASSERT(n); + ASSERT(format); + + // + // Adjust buffer size limit to allow one space for null termination. + // + if(n) + { + n--; + } + + // + // Initialize the count of characters converted. + // + iConvertCount = 0; + + // + // Loop while there are more characters in the format string. + // + while(*format) + { + // + // Find the first non-% character, or the end of the string. + // + for(ulIdx = 0; (format[ulIdx] != '%') && (format[ulIdx] != '\0'); + ulIdx++) + { + } + + // + // Write this portion of the string to the output buffer. If there are + // more characters to write than there is space in the buffer, then + // only write as much as will fit in the buffer. + // + if(ulIdx > n) + { + ustrncpy(s, format, n); + s += n; + n = 0; + } + else + { + ustrncpy(s, format, ulIdx); + s += ulIdx; + n -= ulIdx; + } + + // + // Update the conversion count. This will be the number of characters + // that should have been written, even if there was not room in the + // buffer. + // + iConvertCount += ulIdx; + + // + // Skip the portion of the format string that was written. + // + format += ulIdx; + + // + // See if the next character is a %. + // + if(*format == '%') + { + // + // Skip the %. + // + format++; + + // + // Set the digit count to zero, and the fill character to space + // (that is, to the defaults). + // + ulCount = 0; + cFill = ' '; + + // + // It may be necessary to get back here to process more characters. + // Goto's aren't pretty, but effective. I feel extremely dirty for + // using not one but two of the beasts. + // +again: + + // + // Determine how to handle the next character. + // + switch(*format++) + { + // + // Handle the digit characters. + // + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + // + // If this is a zero, and it is the first digit, then the + // fill character is a zero instead of a space. + // + if((format[-1] == '0') && (ulCount == 0)) + { + cFill = '0'; + } + + // + // Update the digit count. + // + ulCount *= 10; + ulCount += format[-1] - '0'; + + // + // Get the next character. + // + goto again; + } + + // + // Handle the %c command. + // + case 'c': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(arg, unsigned long); + + // + // Copy the character to the output buffer, if there is + // room. Update the buffer size remaining. + // + if(n != 0) + { + *s++ = (char)ulValue; + n--; + } + + // + // Update the conversion count. + // + iConvertCount++; + + // + // This command has been handled. + // + break; + } + + // + // Handle the %d and %i commands. + // + case 'd': + case 'i': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(arg, unsigned long); + + // + // If the value is negative, make it positive and indicate + // that a minus sign is needed. + // + if((long)ulValue < 0) + { + // + // Make the value positive. + // + ulValue = -(long)ulValue; + + // + // Indicate that the value is negative. + // + ulNeg = 1; + } + else + { + // + // Indicate that the value is positive so that a + // negative sign isn't inserted. + // + ulNeg = 0; + } + + // + // Set the base to 10. + // + ulBase = 10; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %s command. + // + case 's': + { + // + // Get the string pointer from the varargs. + // + pcStr = va_arg(arg, char *); + + // + // Determine the length of the string. + // + for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++) + { + } + + // + // Update the convert count to include any padding that + // should be necessary (regardless of whether we have space + // to write it or not). + // + if(ulCount > ulIdx) + { + iConvertCount += (ulCount - ulIdx); + } + + // + // Copy the string to the output buffer. Only copy as much + // as will fit in the buffer. Update the output buffer + // pointer and the space remaining. + // + if(ulIdx > n) + { + ustrncpy(s, pcStr, n); + s += n; + n = 0; + } + else + { + ustrncpy(s, pcStr, ulIdx); + s += ulIdx; + n -= ulIdx; + + // + // Write any required padding spaces assuming there is + // still space in the buffer. + // + if(ulCount > ulIdx) + { + ulCount -= ulIdx; + if(ulCount > n) + { + ulCount = n; + } + n = -ulCount; + + while(ulCount--) + { + *s++ = ' '; + } + } + } + + // + // Update the conversion count. This will be the number of + // characters that should have been written, even if there + // was not room in the buffer. + // + iConvertCount += ulIdx; + + // + // This command has been handled. + // + break; + } + + // + // Handle the %u command. + // + case 'u': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(arg, unsigned long); + + // + // Set the base to 10. + // + ulBase = 10; + + // + // Indicate that the value is positive so that a minus sign + // isn't inserted. + // + ulNeg = 0; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %x and %X commands. Note that they are treated + // identically; that is, %X will use lower case letters for a-f + // instead of the upper case letters is should use. We also + // alias %p to %x. + // + case 'x': + case 'X': + case 'p': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(arg, unsigned long); + + // + // Set the base to 16. + // + ulBase = 16; + + // + // Indicate that the value is positive so that a minus sign + // isn't inserted. + // + ulNeg = 0; + + // + // Determine the number of digits in the string version of + // the value. + // +convert: + for(ulIdx = 1; + (((ulIdx * ulBase) <= ulValue) && + (((ulIdx * ulBase) / ulBase) == ulIdx)); + ulIdx *= ulBase, ulCount--) + { + } + + // + // If the value is negative, reduce the count of padding + // characters needed. + // + if(ulNeg) + { + ulCount--; + } + + // + // If the value is negative and the value is padded with + // zeros, then place the minus sign before the padding. + // + if(ulNeg && (n != 0) && (cFill == '0')) + { + // + // Place the minus sign in the output buffer. + // + *s++ = '-'; + n--; + + // + // Update the conversion count. + // + iConvertCount++; + + // + // The minus sign has been placed, so turn off the + // negative flag. + // + ulNeg = 0; + } + + // + // See if there are more characters in the specified field + // width than there are in the conversion of this value. + // + if((ulCount > 1) && (ulCount < 65536)) + { + // + // Loop through the required padding characters. + // + for(ulCount--; ulCount; ulCount--) + { + // + // Copy the character to the output buffer if there + // is room. + // + if(n != 0) + { + *s++ = cFill; + n--; + } + + // + // Update the conversion count. + // + iConvertCount++; + } + } + + // + // If the value is negative, then place the minus sign + // before the number. + // + if(ulNeg && (n != 0)) + { + // + // Place the minus sign in the output buffer. + // + *s++ = '-'; + n--; + + // + // Update the conversion count. + // + iConvertCount++; + } + + // + // Convert the value into a string. + // + for(; ulIdx; ulIdx /= ulBase) + { + // + // Copy the character to the output buffer if there is + // room. + // + if(n != 0) + { + *s++ = g_pcHex[(ulValue / ulIdx) % ulBase]; + n--; + } + + // + // Update the conversion count. + // + iConvertCount++; + } + + // + // This command has been handled. + // + break; + } + + // + // Handle the %% command. + // + case '%': + { + // + // Simply write a single %. + // + if(n != 0) + { + *s++ = format[-1]; + n--; + } + + // + // Update the conversion count. + // + iConvertCount++; + + // + // This command has been handled. + // + break; + } + + // + // Handle all other commands. + // + default: + { + // + // Indicate an error. + // + if(n >= 5) + { + ustrncpy(s, "ERROR", 5); + s += 5; + n -= 5; + } + else + { + ustrncpy(s, "ERROR", n); + s += n; + n = 0; + } + + // + // Update the conversion count. + // + iConvertCount += 5; + + // + // This command has been handled. + // + break; + } + } + } + } + + // + // Null terminate the string in the buffer. + // + *s = 0; + + // + // Return the number of characters in the full converted string. + // + return(iConvertCount); +} + +//***************************************************************************** +// +//! A simple sprintf function supporting \%c, \%d, \%p, \%s, \%u, \%x, and \%X. +//! +//! \param s is the buffer where the converted string is stored. +//! \param format is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! format string. +//! +//! This function is very similar to the C library sprintf() function. +//! Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d or \%i to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%p to print a pointer as a hexadecimal value +//! - \%\% to print out a \% character +//! +//! For \%d, \%i, \%p, \%s, \%u, \%x, and \%X, an optional number may reside +//! between the \% and the format character, which specifies the minimum number +//! of characters to use for that value; if preceded by a 0 then the extra +//! characters will be filled with zeros instead of spaces. For example, +//! ``\%8d'' will use eight characters to print the decimal value with spaces +//! added to reach eight; ``\%08d'' will use eight characters as well but will +//! add zeros instead of spaces. +//! +//! The type of the arguments after \e format must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The caller must ensure that the buffer \e s is large enough to hold the +//! entire converted string, including the null termination character. +//! +//! \return Returns the count of characters that were written to the output +//! buffer, not including the NULL termination character. +// +//***************************************************************************** +int +usprintf(char * restrict s, const char *format, ...) +{ + va_list arg; + int ret; + + // + // Start the varargs processing. + // + va_start(arg, format); + + // + // Call vsnprintf to perform the conversion. Use a large number for the + // buffer size. + // + ret = uvsnprintf(s, 0xffff, format, arg); + + // + // End the varargs processing. + // + va_end(arg); + + // + // Return the conversion count. + // + return(ret); +} + +//***************************************************************************** +// +//! A simple snprintf function supporting \%c, \%d, \%p, \%s, \%u, \%x, and +//! \%X. +//! +//! \param s is the buffer where the converted string is stored. +//! \param n is the size of the buffer. +//! \param format is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! format string. +//! +//! This function is very similar to the C library sprintf() function. +//! Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d or \%i to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%p to print a pointer as a hexadecimal value +//! - \%\% to print out a \% character +//! +//! For \%d, \%i, \%p, \%s, \%u, \%x, and \%X, an optional number may reside +//! between the \% and the format character, which specifies the minimum number +//! of characters to use for that value; if preceded by a 0 then the extra +//! characters will be filled with zeros instead of spaces. For example, +//! ``\%8d'' will use eight characters to print the decimal value with spaces +//! added to reach eight; ``\%08d'' will use eight characters as well but will +//! add zeros instead of spaces. +//! +//! The type of the arguments after \e format must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The function will copy at most \e n - 1 characters into the buffer +//! \e s. One space is reserved in the buffer for the null termination +//! character. +//! +//! The function will return the number of characters that would be converted +//! as if there were no limit on the buffer size. Therefore it is possible for +//! the function to return a count that is greater than the specified buffer +//! size. If this happens, it means that the output was truncated. +//! +//! \return Returns the number of characters that were to be stored, not +//! including the NULL termination character, regardless of space in the +//! buffer. +// +//***************************************************************************** +int +usnprintf(char * restrict s, size_t n, const char * restrict format, ...) +{ + va_list arg; + int ret; + + // + // Start the varargs processing. + // + va_start(arg, format); + + // + // Call vsnprintf to perform the conversion. + // + ret = uvsnprintf(s, n, format, arg); + + // + // End the varargs processing. + // + va_end(arg); + + // + // Return the conversion count. + // + return(ret); +} + + +// +// This array contains the number of days in a year at the beginning of each +// month of the year, in a non-leap year. +// +static const time_t g_psDaysToMonth[12] = +{ + 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 +}; + +//***************************************************************************** +// +//! Converts from seconds to calendar date and time. +//! +//! \param timer is the number of seconds. +//! \param tm is a pointer to the time structure that is filled in with the +//! broken down date and time. +//! +//! This function converts a number of seconds since midnight GMT on January 1, +//! 1970 (traditional Unix epoch) into the equivalent month, day, year, hours, +//! minutes, and seconds representation. +//! +//! \return None. +// +//***************************************************************************** +void +ulocaltime(time_t timer, struct tm *tm) +{ + time_t temp, months; + + // + // Extract the number of seconds, converting time to the number of minutes. + // + temp = timer / 60; + tm->tm_sec = timer - (temp * 60); + timer = temp; + + // + // Extract the number of minutes, converting time to the number of hours. + // + temp = timer / 60; + tm->tm_min = timer - (temp * 60); + timer = temp; + + // + // Extract the number of hours, converting time to the number of days. + // + temp = timer / 24; + tm->tm_hour = timer - (temp * 24); + timer = temp; + + // + // Compute the day of the week. + // + tm->tm_wday = (timer + 4) % 7; + + // + // Compute the number of leap years that have occurred since 1968, the + // first leap year before 1970. For the beginning of a leap year, cut the + // month loop below at March so that the leap day is classified as February + // 29 followed by March 1, instead of March 1 followed by another March 1. + // + timer += 366 + 365; + temp = timer / ((4 * 365) + 1); + if((timer - (temp * ((4 * 365) + 1))) > (31 + 28)) + { + temp++; + months = 12; + } + else + { + months = 2; + } + + // + // Extract the year. + // + tm->tm_year = ((timer - temp) / 365) + 68; + timer -= ((tm->tm_year - 68) * 365) + temp; + + // + // Extract the month. + // + for(temp = 0; temp < months; temp++) + { + if(g_psDaysToMonth[temp] > timer) + { + break; + } + } + tm->tm_mon = temp - 1; + + // + // Extract the day of the month. + // + tm->tm_mday = timer - g_psDaysToMonth[temp - 1] + 1; +} + +//***************************************************************************** +// +//! Compares two time structures and determines if one is greater than, +//! less than, or equal to the other. +//! +//! \param t1 is the first time structure to compare. +//! \param t2 is the second time structure to compare. +//! +//! This function compares two time structures and returns a signed number +//! to indicate the result of the comparison. If the time represented by +//! \e t1 is greater than the time represented by \e t2 then a positive +//! number is returned. Likewise if \e t1 is less than \e t2 then a +//! negative number is returned. If the two times are equal then the function +//! returns 0. +//! +//! \return Returns 0 if the two times are equal, +1 if \e t1 is greater +//! than \e t2, and -1 if \e t1 is less than \e t2. +// +//***************************************************************************** +static int +ucmptime(struct tm *t1, struct tm *t2) +{ + // + // Compare each field in descending significance to determine if + // greater than, less than, or equal. + // + if(t1->tm_year > t2->tm_year) + { + return(1); + } + else if(t1->tm_year < t2->tm_year) + { + return(-1); + } + else if(t1->tm_mon > t2->tm_mon) + { + return(1); + } + else if(t1->tm_mon < t2->tm_mon) + { + return(-1); + } + else if(t1->tm_mday > t2->tm_mday) + { + return(1); + } + else if(t1->tm_mday < t2->tm_mday) + { + return(-1); + } + else if(t1->tm_hour > t2->tm_hour) + { + return(1); + } + else if(t1->tm_hour < t2->tm_hour) + { + return(-1); + } + else if(t1->tm_min > t2->tm_min) + { + return(1); + } + else if(t1->tm_min < t2->tm_min) + { + return(-1); + } + else if(t1->tm_sec > t2->tm_sec) + { + return(1); + } + else if(t1->tm_sec < t2->tm_sec) + { + return(-1); + } + else + { + // + // Reaching this branch of the conditional means that all of the + // fields are equal, and thus the two times are equal. + // + return(0); + } +} + +//***************************************************************************** +// +//! Converts calendar date and time to seconds. +//! +//! \param timeptr is a pointer to the time structure that is filled in with +//! the broken down date and time. +//! +//! This function converts the date and time represented by the \e timeptr +//! structure pointer to the number of seconds since midnight GMT on January 1, +//! 1970 (traditional Unix epoch). +//! +//! \return Returns the calendar time and date as seconds. If the conversion +//! was not possible then the function returns (uint32_t)(-1). +// +//***************************************************************************** +time_t +umktime(struct tm *timeptr) +{ + struct tm sTimeGuess; + unsigned long ulTimeGuess = 0x80000000; + unsigned long ulAdjust = 0x40000000; + int iSign; + + // + // Seed the binary search with the first guess. + // + ulocaltime(ulTimeGuess, &sTimeGuess); + iSign = ucmptime(timeptr, &sTimeGuess); + + // + // While the time is not yet found, execute a binary search. + // + while(iSign && ulAdjust) + { + // + // Adjust the time guess up or down depending on the result of the + // last compare. + // + ulTimeGuess = ((iSign > 0) ? (ulTimeGuess + ulAdjust) : + (ulTimeGuess - ulAdjust)); + ulAdjust /= 2; + + // + // Compare the new time guess against the time pointed at by the + // function parameters. + // + ulocaltime(ulTimeGuess, &sTimeGuess); + iSign = ucmptime(timeptr, &sTimeGuess); + } + + // + // If the above loop was exited with iSign == 0, that means that the + // time in seconds was found, so return that value to the caller. + // + if(iSign == 0) + { + return(ulTimeGuess); + } + + // + // Otherwise the time could not be converted so return an error. + // + else + { + return((unsigned long)-1); + } +} + +//***************************************************************************** +// +//! Converts a string into its numeric equivalent. +//! +//! \param nptr is a pointer to the string containing the integer. +//! \param endptr is a pointer that will be set to the first character past +//! the integer in the string. +//! \param base is the radix to use for the conversion; can be zero to +//! auto-select the radix or between 2 and 16 to explicitly specify the radix. +//! +//! This function is very similar to the C library strtoul() function. +//! It scans a string for the first token (that is, non-white space) and +//! converts the value at that location in the string into an integer value. +//! +//! \return Returns the result of the conversion. +// +//***************************************************************************** +unsigned long +ustrtoul(const char * restrict nptr, const char ** restrict endptr, int base) +{ + unsigned long ulRet, ulDigit, ulNeg, ulValid; + const char *pcPtr; + + // + // Check the arguments. + // + ASSERT(nptr); + ASSERT((base == 0) || ((base > 1) && (base <= 16))); + + // + // Initially, the result is zero. + // + ulRet = 0; + ulNeg = 0; + ulValid = 0; + + // + // Skip past any leading white space. + // + pcPtr = nptr; + while((*pcPtr == ' ') || (*pcPtr == '\t')) + { + pcPtr++; + } + + // + // Take a leading + or - from the value. + // + if(*pcPtr == '-') + { + ulNeg = 1; + pcPtr++; + } + else if(*pcPtr == '+') + { + pcPtr++; + } + + // + // See if the radix was not specified, or is 16, and the value starts with + // "0x" or "0X" (to indicate a hex value). + // + if(((base == 0) || (base == 16)) && (*pcPtr == '0') && + ((pcPtr[1] == 'x') || (pcPtr[1] == 'X'))) + { + // + // Skip the leading "0x". + // + pcPtr += 2; + + // + // Set the radix to 16. + // + base = 16; + } + + // + // See if the radix was not specified. + // + if(base == 0) + { + // + // See if the value starts with "0". + // + if(*pcPtr == '0') + { + // + // Values that start with "0" are assumed to be radix 8. + // + base = 8; + } + else + { + // + // Otherwise, the values are assumed to be radix 10. + // + base = 10; + } + } + + // + // Loop while there are more valid digits to consume. + // + while(1) + { + // + // See if this character is a number. + // + if((*pcPtr >= '0') && (*pcPtr <= '9')) + { + // + // Convert the character to its integer equivalent. + // + ulDigit = *pcPtr++ - '0'; + } + + // + // Otherwise, see if this character is an upper case letter. + // + else if((*pcPtr >= 'A') && (*pcPtr <= 'Z')) + { + // + // Convert the character to its integer equivalent. + // + ulDigit = *pcPtr++ - 'A' + 10; + } + + // + // Otherwise, see if this character is a lower case letter. + // + else if((*pcPtr >= 'a') && (*pcPtr <= 'z')) + { + // + // Convert the character to its integer equivalent. + // + ulDigit = *pcPtr++ - 'a' + 10; + } + + // + // Otherwise, this is not a valid character. + // + else + { + // + // Stop converting this value. + // + break; + } + + // + // See if this digit is valid for the chosen radix. + // + if(ulDigit >= base) + { + // + // Since this was not a valid digit, move the pointer back to the + // character that therefore should not have been consumed. + // + pcPtr--; + + // + // Stop converting this value. + // + break; + } + + // + // Add this digit to the converted value. + // + ulRet *= base; + ulRet += ulDigit; + + // + // Since a digit has been added, this is now a valid result. + // + ulValid = 1; + } + + // + // Set the return string pointer to the first character not consumed. + // + if(endptr) + { + *endptr = ulValid ? pcPtr : nptr; + } + + // + // Return the converted value. + // + return(ulNeg ? (0 - ulRet) : ulRet); +} + +// +// An array of the value of ten raised to the power-of-two exponents. This is +// used for converting the decimal exponent into the floating-point value of +// 10^exp. +// +static const float g_pfExponents[] = +{ + 1.0e+01, + 1.0e+02, + 1.0e+04, + 1.0e+08, + 1.0e+16, + 1.0e+32, +}; + +//***************************************************************************** +// +//! Converts a string into its floating-point equivalent. +//! +//! \param nptr is a pointer to the string containing the floating-point +//! value. +//! \param endptr is a pointer that will be set to the first character past +//! the floating-point value in the string. +//! +//! This function is very similar to the C library strtof() function. +//! It scans a string for the first token (that is, non-white space) and +//! converts the value at that location in the string into a floating-point +//! value. +//! +//! \return Returns the result of the conversion. +// +//***************************************************************************** +float +ustrtof(const char *nptr, const char **endptr) +{ + unsigned long ulNeg, ulExp, ulExpNeg, ulValid, ulIdx; + float fRet, fDigit, fExp; + const char *pcPtr; + + // + // Check the arguments. + // + ASSERT(nptr); + + // + // Initially, the result is zero. + // + fRet = 0; + ulNeg = 0; + ulValid = 0; + + // + // Skip past any leading white space. + // + pcPtr = nptr; + while((*pcPtr == ' ') || (*pcPtr == '\t')) + { + pcPtr++; + } + + // + // Take a leading + or - from the value. + // + if(*pcPtr == '-') + { + ulNeg = 1; + pcPtr++; + } + else if(*pcPtr == '+') + { + pcPtr++; + } + + // + // Loop while there are valid digits to consume. + // + while((*pcPtr >= '0') && (*pcPtr <= '9')) + { + // + // Add this digit to the converted value. + // + fRet *= 10; + fRet += *pcPtr++ - '0'; + + // + // Since a digit has been added, this is now a valid result. + // + ulValid = 1; + } + + // + // See if the next character is a period and the character after that is a + // digit, indicating the start of the fractional portion of the value. + // + if((*pcPtr == '.') && (pcPtr[1] >= '0') && (pcPtr[1] <= '9')) + { + // + // Skip the period. + // + pcPtr++; + + // + // Loop while there are valid fractional digits to consume. + // + fDigit = 0.1; + while((*pcPtr >= '0') && (*pcPtr <= '9')) + { + // + // Add this digit to the converted value. + // + fRet += (*pcPtr++ - '0') * fDigit; + fDigit /= (float)10.0; + + // + // Since a digit has been added, this is now a valid result. + // + ulValid = 1; + } + } + + // + // See if the next character is an "e" and a valid number has been + // converted, indicating the start of the exponent. + // + if(((pcPtr[0] == 'e') || (pcPtr[0] == 'E')) && (ulValid == 1) && + (((pcPtr[1] >= '0') && (pcPtr[1] <= '9')) || + (((pcPtr[1] == '+') || (pcPtr[1] == '-')) && + (pcPtr[2] >= '0') && (pcPtr[2] <= '9')))) + { + // + // Skip the "e". + // + pcPtr++; + + // + // Take a leading + or - from the exponent. + // + ulExpNeg = 0; + if(*pcPtr == '-') + { + ulExpNeg = 1; + pcPtr++; + } + else if(*pcPtr == '+') + { + pcPtr++; + } + + // + // Loop while there are valid digits in the exponent. + // + ulExp = 0; + while((*pcPtr >= '0') && (*pcPtr <= '9')) + { + // + // Add this digit to the converted value. + // + ulExp *= 10; + ulExp += *pcPtr++ - '0'; + } + + // + // Raise ten to the power of the exponent. Do this via binary + // decomposition; for each binary bit set in the exponent, multiply the + // floating-point representation by ten raised to that binary value + // (extracted from the table above). + // + fExp = 1; + for(ulIdx = 0; ulIdx < 7; ulIdx++) + { + if(ulExp & (1 << ulIdx)) + { + fExp *= g_pfExponents[ulIdx]; + } + } + + // + // If the exponent is negative, then the exponent needs to be inverted. + // + if(ulExpNeg == 1) + { + fExp = 1 / fExp; + } + + // + // Multiply the result by the computed exponent value. + // + fRet *= fExp; + } + + // + // Set the return string pointer to the first character not consumed. + // + if(endptr) + { + *endptr = ulValid ? pcPtr : nptr; + } + + // + // Return the converted value. + // + return(ulNeg ? (0 - fRet) : fRet); +} + +//***************************************************************************** +// +//! Returns the length of a null-terminated string. +//! +//! \param s is a pointer to the string whose length is to be found. +//! +//! This function is very similar to the C library strlen() function. +//! It determines the length of the null-terminated string passed and returns +//! this to the caller. +//! +//! This implementation assumes that single byte character strings are passed +//! and will return incorrect values if passed some UTF-8 strings. +//! +//! \return Returns the length of the string pointed to by \e s. +// +//***************************************************************************** +size_t +ustrlen(const char *s) +{ + size_t len; + + // + // Check the arguments. + // + ASSERT(s); + + // + // Initialize the length. + // + len = 0; + + // + // Step through the string looking for a zero character (marking its end). + // + while(s[len]) + { + // + // Zero not found so move on to the next character. + // + len++; + } + + return(len); +} + +//***************************************************************************** +// +//! Finds a substring within a string. +//! +//! \param s1 is a pointer to the string that will be searched. +//! \param s2 is a pointer to the substring that is to be found within +//! \e s1. +//! +//! This function is very similar to the C library strstr() function. +//! It scans a string for the first instance of a given substring and returns +//! a pointer to that substring. If the substring cannot be found, a NULL +//! pointer is returned. +//! +//! \return Returns a pointer to the first occurrence of \e s2 within +//! \e s1 or NULL if no match is found. +// +//***************************************************************************** +char * +ustrstr(const char *s1, const char *s2) +{ + size_t n; + + // + // Get the length of the string to be found. + // + n = ustrlen(s2); + + // + // Loop while we have not reached the end of the string. + // + while(*s1) + { + // + // Check to see if the substring appears at this position. + // + if(ustrncmp(s2, s1, n) == 0) + { + // + // It does so return the pointer. + // + return((char *)s1); + } + + // + // Move to the next position in the string being searched. + // + s1++; + } + + // + // We reached the end of the string without finding the substring so + // return NULL. + // + return((char *)0); +} + +//***************************************************************************** +// +//! Compares two strings without regard to case. +//! +//! \param s1 points to the first string to be compared. +//! \param s2 points to the second string to be compared. +//! \param n is the maximum number of characters to compare. +//! +//! This function is very similar to the C library strncasecmp() +//! function. It compares at most \e n characters of two strings without +//! regard to case. The comparison ends if a terminating NULL character is +//! found in either string before \e n characters are compared. In this case, +//! the shorter string is deemed the lesser. +//! +//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less +//! than \e s2 and 1 if \e s1 is greater than \e s2. +// +//***************************************************************************** +int +ustrncasecmp(const char *s1, const char *s2, size_t n) +{ + char c1, c2; + + // + // Loop while there are more characters to compare. + // + while(n) + { + // + // If we reached a NULL in both strings, they must be equal so + // we end the comparison and return 0 + // + if(!*s1 && !*s2) + { + return(0); + } + + // + // Lower case the characters at the current position before we compare. + // + c1 = (((*s1 >= 'A') && (*s1 <= 'Z')) ? (*s1 + ('a' - 'A')) : *s1); + c2 = (((*s2 >= 'A') && (*s2 <= 'Z')) ? (*s2 + ('a' - 'A')) : *s2); + + // + // Compare the two characters and, if different, return the relevant + // return code. + // + if(c2 < c1) + { + return(1); + } + if(c1 < c2) + { + return(-1); + } + + // + // Move on to the next character. + // + s1++; + s2++; + n--; + } + + // + // If we fall out, the strings must be equal for at least the first n + // characters so return 0 to indicate this. + // + return(0); +} + +//***************************************************************************** +// +//! Compares two strings without regard to case. +//! +//! \param s1 points to the first string to be compared. +//! \param s2 points to the second string to be compared. +//! +//! This function is very similar to the C library strcasecmp() +//! function. It compares two strings without regard to case. The comparison +//! ends if a terminating NULL character is found in either string. In this +//! case, the int16_ter string is deemed the lesser. +//! +//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less +//! than \e s2 and 1 if \e s1 is greater than \e s2. +// +//***************************************************************************** +int +ustrcasecmp(const char *s1, const char *s2) +{ + // + // Just let ustrncasecmp() handle this. + // + return(ustrncasecmp(s1, s2, (size_t)-1)); +} + +//***************************************************************************** +// +//! Compares two strings. +//! +//! \param s1 points to the first string to be compared. +//! \param s2 points to the second string to be compared. +//! \param n is the maximum number of characters to compare. +//! +//! This function is very similar to the C library strncmp() function. +//! It compares at most \e n characters of two strings taking case into +//! account. The comparison ends if a terminating NULL character is found in +//! either string before \e n characters are compared. In this case, the +//! int16_ter string is deemed the lesser. +//! +//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less +//! than \e s2 and 1 if \e s1 is greater than \e s2. +// +//***************************************************************************** +int +ustrncmp(const char *s1, const char *s2, size_t n) +{ + // + // Loop while there are more characters. + // + while(n) + { + // + // If we reached a NULL in both strings, they must be equal so we end + // the comparison and return 0 + // + if(!*s1 && !*s2) + { + return(0); + } + + // + // Compare the two characters and, if different, return the relevant + // return code. + // + if(*s2 < *s1) + { + return(1); + } + if(*s1 < *s2) + { + return(-1); + } + + // + // Move on to the next character. + // + s1++; + s2++; + n--; + } + + // + // If we fall out, the strings must be equal for at least the first n + // characters so return 0 to indicate this. + // + return(0); +} + +//***************************************************************************** +// +//! Compares two strings. +//! +//! \param s1 points to the first string to be compared. +//! \param s2 points to the second string to be compared. +//! +//! This function is very similar to the C library strcmp() +//! function. It compares two strings, taking case into account. The +//! comparison ends if a terminating NULL character is found in either string. +//! In this case, the int16_ter string is deemed the lesser. +//! +//! \return Returns 0 if the two strings are equal, -1 if \e s1 is less +//! than \e s2 and 1 if \e s1 is greater than \e s2. +// +//***************************************************************************** +int +ustrcmp(const char *s1, const char *s2) +{ + // + // Pass this on to ustrncmp. + // + return(ustrncmp(s1, s2, (size_t)-1)); +} + +// +// Random Number Generator Seed Value +// +static unsigned int g_iRandomSeed = 1; + +//***************************************************************************** +// +//! Set the random number generator seed. +//! +//! \param seed is the new seed value to use for the random number +//! generator. +//! +//! This function is very similar to the C library srand() function. +//! It will set the seed value used in the urand() function. +//! +//! \return None +// +//***************************************************************************** +void +usrand(unsigned int seed) +{ + g_iRandomSeed = seed; +} + +//***************************************************************************** +// +//! Generate a new (pseudo) random number +//! +//! This function is very similar to the C library rand() function. +//! It will generate a pseudo-random number sequence based on the seed value. +//! +//! \return A pseudo-random number will be returned. +// +//***************************************************************************** +int +urand(void) +{ + // + // Generate a new pseudo-random number with a linear congruence random + // number generator. This new random number becomes the seed for the next + // random number. + // + g_iRandomSeed = (g_iRandomSeed * 1664525) + 1013904223; + + // + // Return the new random number. + // + return((int)g_iRandomSeed); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.h b/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.h new file mode 100644 index 00000000000..2cb92ed3a19 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/deprecated/utils/ustdlib.h @@ -0,0 +1,96 @@ +//########################################################################### +// +// FILE: ustdlib.h +// +// TITLE: Prototypes for simple standard library functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __USTDLIB_H__ +#define __USTDLIB_H__ + +// +// Included Files +// +#include +#include + +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Function Prototypes +// +extern void ulocaltime(time_t timer, struct tm *tm); +extern time_t umktime(struct tm *timeptr); +extern int urand(void); +extern int usnprintf(char * restrict s, size_t n, const char * restrict format, + ...); +extern int usprintf(char * restrict s, const char * restrict format, ...); +extern void usrand(unsigned int seed); +extern int ustrcasecmp(const char *s1, const char *s2); +extern int ustrcmp(const char *s1, const char *s2); +extern size_t ustrlen(const char *s); +extern int ustrncasecmp(const char *s1, const char *s2, size_t n); +extern int ustrncmp(const char *s1, const char *s2, size_t n); +extern char *ustrncpy(char * restrict s1, const char * restrict s2, size_t n); +extern char *ustrstr(const char *s1, const char *s2); +extern float ustrtof(const char * restrict nptr, + const char ** restrict endptr); +extern unsigned long int ustrtoul(const char * restrict nptr, + const char ** restrict endptr, int base); +extern int uvsnprintf(char * restrict s, size_t n, + const char * restrict format, va_list arg); + +// +// Mark the end of the C bindings section for C++ compilers. +// +#ifdef __cplusplus +} +#endif + +#endif // __USTDLIB_H__ + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Adc_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Adc_defines.h new file mode 100644 index 00000000000..78ff34a2376 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Adc_defines.h @@ -0,0 +1,87 @@ +//########################################################################### +// +// FILE: F2837xD_Adc_defines.h +// +// TITLE: #defines used in ADC examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_ADC_DEFINES_H +#define F2837xD_ADC_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +//definitions for specifying an ADC +// +#define ADC_ADCA 0 +#define ADC_ADCB 1 +#define ADC_ADCC 2 +#define ADC_ADCD 3 + +// +//definitions for selecting ADC resolution +// +#ifndef _DUAL_HEADERS +#define ADC_RESOLUTION_12BIT 0 +#define ADC_RESOLUTION_16BIT 1 +#else +#define ADC_BITRESOLUTION_12BIT 0 +#define ADC_BITRESOLUTION_16BIT 1 +#endif +// +//definitions for selecting ADC signal mode +//(single-ended mode is only a valid mode for 12-bit resolution) +// +#define ADC_SIGNALMODE_SINGLE 0 +#define ADC_SIGNALMODE_DIFFERENTIAL 1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_ADC_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Can_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Can_defines.h new file mode 100644 index 00000000000..a784ef475dc --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Can_defines.h @@ -0,0 +1,129 @@ +//############################################################################# +// +// FILE: F2837xD_Can_defines.h +// +// TITLE: Common defines used in CAN Test Cases +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef F2837xD_CAN_DEFINES_H +#define F2837xD_CAN_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// Reset Values +// +#define CAN_RESET_VALUE_ZERO 0x00000000 +#define CAN_CTL_RESET_VALUE 0x00001401 +#define CAN_ES_RESET_VALUE 0x00000007 +#define CAN_BTR_RESET_VALUE 0x00002301 +#define CAN_REL_RESET_VALUE 0xA3170504 +#define CAN_RAM_INIT_RESET_VALUE 0x00000005 +#define CAN_IF_CMD_RESET_VALUE 0x00000001 +#define CAN_IF_MASK_RESET_VALUE 0xFFFFFFFF + +// +// Register value when Peripheral Clock is Disabled +// +#define CAN_MODULE_CLK_DISABLE_VALUE 0x00000000 + +// +// Bit field definition of CAN_CTL register. +// +#define CAN_CTL_INIT 0x00000001 // Initialization +#define CAN_CTL_IE0 0x00000002 // Interrupt Enable 0 +#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable +#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable +#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission +#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable +#define CAN_CTL_TEST 0x00000080 // Test Mode Enable +#define CAN_CTL_IDS 0x00000100 // Interruption Debug Support Enable +#define CAN_CTL_ABO 0x00000200 // Auto-Bus On Enable +#define CAN_CTL_PMD_S 10 +#define CAN_CTL_PMD_M 0x00003C00 // Parity/SECDED Enable +#define CAN_CTL_SWR 0x00008000 // Software Reset Enable +#define CAN_CTL_INITDBG 0x00010000 // Debug Mode Status +#define CAN_CTL_IE1 0x00020000 // Interrupt Enable 1 +#define CAN_CTL_PDR 0x01000000 // Power Down Mode Request +#define CAN_CTL_WUBA 0x02000000 // Wake Up on Bus Activity + +// +// Bit field definition of CAN_IF1_CMD register. +// +#define CAN_IF1_CMD_MESSNUM_S 0 +#define CAN_IF1_CMD_MESSNUM_M 0x000000FF // Message Number +#define CAN_IF1_CMD_BUSY 0x00008000 // Busy Flag +#define CAN_IF1_CMD_DATAB 0x00010000 // Access Data B +#define CAN_IF1_CMD_DATAA 0x00020000 // Access Data A +#define CAN_IF1_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit +#define CAN_IF1_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit +#define CAN_IF1_CMD_CONTROL 0x00100000 // Access Control Bits +#define CAN_IF1_CMD_ARB 0x00200000 // Access Arbitration Bits +#define CAN_IF1_CMD_MASK 0x00400000 // Access Mask Bits +#define CAN_IF1_CMD_WR_RD 0x00800000 // Write and Read + +// +// Bit field definition of CAN_IF2_CMD register. +// +#define CAN_IF2_CMD_MESSNUM_S 0 +#define CAN_IF2_CMD_MESSNUM_M 0x000000FF // Message Number +#define CAN_IF2_CMD_BUSY 0x00008000 // Busy Flag +#define CAN_IF2_CMD_DATAB 0x00010000 // Access Data B +#define CAN_IF2_CMD_DATAA 0x00020000 // Access Data A +#define CAN_IF2_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit +#define CAN_IF2_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit +#define CAN_IF2_CMD_CONTROL 0x00100000 // Access Control Bits +#define CAN_IF2_CMD_ARB 0x00200000 // Access Arbitration Bits +#define CAN_IF2_CMD_MASK 0x00400000 // Access Mask Bits +#define CAN_IF2_CMD_WR_RD 0x00800000 // Write and Read + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_CAN_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_defines.h new file mode 100644 index 00000000000..2df82d79298 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_defines.h @@ -0,0 +1,201 @@ +//########################################################################### +// +// FILE: F2837xD_Cla_defines.h +// +// TITLE: #defines used in CLA examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_CLA_DEFINES_H +#define F2837xD_CLA_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// MCTL Register +// +#define CLA_FORCE_RESET 0x1 +#define CLA_IACK_ENABLE 0x1 +#define CLA_IACK_DISABLE 0x0 + +// +// MMEMCFG Register +// +#define CLA_CLA_SPACE 0x1 +#define CLA_CPU_SPACE 0x0 + +// +// MIER Interrupt Enable Register +// +#define CLA_INT_ENABLE 0x1 +#define CLA_INT_DISABLE 0x0 + +// +// Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register +// +#define CLA_TRIG_NOPERPH 0 +#define CLA_TRIG_ADCAINT1 1 +#define CLA_TRIG_ADCAINT2 2 +#define CLA_TRIG_ADCAINT3 3 +#define CLA_TRIG_ADCAINT4 4 +#define CLA_TRIG_ADCAEVT 5 +#define CLA_TRIG_ADCBINT1 6 +#define CLA_TRIG_ADCBINT2 7 +#define CLA_TRIG_ADCBINT3 8 +#define CLA_TRIG_ADCBINT4 9 +#define CLA_TRIG_ADCBEVT 10 +#define CLA_TRIG_ADCCINT1 11 +#define CLA_TRIG_ADCCINT2 12 +#define CLA_TRIG_ADCCINT3 13 +#define CLA_TRIG_ADCCINT4 14 +#define CLA_TRIG_ADCCEVT 15 +#define CLA_TRIG_ADCDINT1 16 +#define CLA_TRIG_ADCDINT2 17 +#define CLA_TRIG_ADCDINT3 18 +#define CLA_TRIG_ADCDINT4 19 +#define CLA_TRIG_ADCDEVT 20 + +#define CLA_TRIG_XINT1 29 +#define CLA_TRIG_XINT2 30 +#define CLA_TRIG_XINT3 31 +#define CLA_TRIG_XINT4 32 +#define CLA_TRIG_XINT5 33 + +#define CLA_TRIG_EPWM1INT 36 +#define CLA_TRIG_EPWM2INT 37 +#define CLA_TRIG_EPWM3INT 38 +#define CLA_TRIG_EPWM4INT 39 +#define CLA_TRIG_EPWM5INT 40 +#define CLA_TRIG_EPWM6INT 41 +#define CLA_TRIG_EPWM7INT 42 +#define CLA_TRIG_EPWM8INT 43 +#define CLA_TRIG_EPWM9INT 44 +#define CLA_TRIG_EPWM10INT 45 +#define CLA_TRIG_EPWM11INT 46 +#define CLA_TRIG_EPWM12INT 47 + +#define CLA_TRIG_TINT0 68 +#define CLA_TRIG_TINT1 69 +#define CLA_TRIG_TINT2 70 + +#define CLA_TRIG_MXEVTA 71 +#define CLA_TRIG_MREVTA 72 +#define CLA_TRIG_MXEVTB 73 +#define CLA_TRIG_MREVTB 74 + +#define CLA_TRIG_ECAP1INT 75 +#define CLA_TRIG_ECAP2INT 76 +#define CLA_TRIG_ECAP3INT 77 +#define CLA_TRIG_ECAP4INT 78 +#define CLA_TRIG_ECAP5INT 79 +#define CLA_TRIG_ECAP6INT 80 + +#define CLA_TRIG_EQEP1INT 83 +#define CLA_TRIG_EQEP2INT 84 +#define CLA_TRIG_EQEP3INT 85 + +#define CLA_TRIG_HRCAP1INT 87 +#define CLA_TRIG_HRCAP2INT 88 + +#define CLA_TRIG_SD1INT 95 +#define CLA_TRIG_SD2INT 96 + +#define CLA_TRIG_UPP1_INT 107 + +#define CLA_TRIG_SPITXINTA 109 +#define CLA_TRIG_SPIRXINTA 110 +#define CLA_TRIG_SPITXINTB 111 +#define CLA_TRIG_SPIRXINTB 112 +#define CLA_TRIG_SPITXINTC 113 +#define CLA_TRIG_SPIRXINTC 114 + +#define Cla1ForceTask1andWait()asm(" IACK #0x0001"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT1 == 1); + +#define Cla1ForceTask2andWait()asm(" IACK #0x0002"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT2 == 1); + +#define Cla1ForceTask3andWait()asm(" IACK #0x0004"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT3 == 1); + +#define Cla1ForceTask4andWait()asm(" IACK #0x0008"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT4 == 1); + +#define Cla1ForceTask5andWait()asm(" IACK #0x0010"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT5 == 1); + +#define Cla1ForceTask6andWait()asm(" IACK #0x0020"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT6 == 1); + +#define Cla1ForceTask7andWait()asm(" IACK #0x0040"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT7 == 1); + +#define Cla1ForceTask8andWait()asm(" IACK #0x0080"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT8 == 1); + +#define Cla1ForceTask1() asm(" IACK #0x0001") +#define Cla1ForceTask2() asm(" IACK #0x0002") +#define Cla1ForceTask3() asm(" IACK #0x0004") +#define Cla1ForceTask4() asm(" IACK #0x0008") +#define Cla1ForceTask5() asm(" IACK #0x0010") +#define Cla1ForceTask6() asm(" IACK #0x0020") +#define Cla1ForceTask7() asm(" IACK #0x0040") +#define Cla1ForceTask8() asm(" IACK #0x0080") + +#ifdef __cplusplus +} +#endif + +#endif // - end of F2837xD_CLA_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_typedefs.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_typedefs.h new file mode 100644 index 00000000000..5a4650cbaa7 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Cla_typedefs.h @@ -0,0 +1,128 @@ +//########################################################################### +// +// FILE: F2837xD_Cla_typedefs.h +// +// TITLE: Variable type definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_CLA_TYPEDEFS_H_ +#define F2837xD_CLA_TYPEDEFS_H_ + +// +// Macros to manipulate pre-processor to generate a header file name +// at compile time that is based on the test name and can be used as +// an argument to #include +// +#define XSTRINGIZE(s) STRINGIZE(s) +#define STRINGIZE(s) #s +#define XCONCAT(x,y) CONCAT(x,y) +#define CONCAT(x,y) x##y + +// +// Suppress warnings casting CLA pointers +// +#pragma diag_suppress 70,770,232 + +#ifdef __TMS320C28XX_CLA__ +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +// CLA does not support 64-bit types +// This definition is only to allow inclusion of the standard header files +// which do use 64-bit types +// + +#if (!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) +#define F28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef short int16; +typedef long int32; +typedef unsigned char Uint8; +typedef unsigned short Uint16; +typedef unsigned long Uint32; +typedef float float32; +typedef long double float64; +typedef struct { Uint32 low32; Uint32 high32; } Uint64; +typedef struct { int32 low32; int32 high32; } int64; +#else +#error F2837xD_Cla_Typedefs.h must be included before F2837xD_Device.h or any other header \ +file that redefines data types using the guard macros F28_DATA_TYPES or DSP28_DATA_TYPES +#endif //(!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) + +#ifndef _TI_STD_TYPES +#define _TI_STD_TYPES +// +//These types are also defined in DSP/BIOS 5.x's and the +//SYS/BIOS 6.x's files. We need to protect their +//definition with the #ifndef/#define guard to avoid the duplicate +//definition warning. +// +//SYS/BIOS requires that the file be included before +//any other .h files. +// +#endif + +struct MSTF_SHADOW_BITS { // bits description + Uint16 LVF:1; // 0 Latched Overflow Flag + Uint16 LUF:1; // 1 Latched Underflow Flag + Uint16 NF:1; // 2 Negative Float Flag + Uint16 ZF:1; // 3 Zero Float Flag + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 TF:1; // 6 Test Flag + Uint16 rsvd2:2; // 8:7 Reserved + Uint16 RNDF32:1; // 9 Rounding Mode + Uint16 rsvd3:1; // 10 Reserved + Uint16 MEALLOW:1; // 11 MEALLOW Status + Uint16 RPCL:4; // 15:12 Return PC: Low Portion + Uint16 RPCH:8; // 23:16 Return PC: High Portion + Uint16 rsvd4:8; // 31:24 Reserved +}; +extern __cregister volatile unsigned int MSTF; + +#endif //__TMS320C28XX_CLA__ + +#ifndef __TMS320C28XX__ +#define __cregister +#endif //__TMS320C28xx__ + +#endif //F2837xD_CLA_TYPEDEFS_H_ + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Dma_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Dma_defines.h new file mode 100644 index 00000000000..ef6a245b931 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Dma_defines.h @@ -0,0 +1,212 @@ +//########################################################################### +// +// FILE: F2837xD_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_DMA_DEFINES_H +#define F2837xD_DMA_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// PERINTSEL bits +// +#define DMA_ADCAINT1 1 +#define DMA_ADCAINT2 2 +#define DMA_ADCAINT3 3 +#define DMA_ADCAINT4 4 +#define DMA_ADCAEVT 5 +#define DMA_ADCBINT1 6 +#define DMA_ADCBINT2 7 +#define DMA_ADCBINT3 8 +#define DMA_ADCBINT4 9 +#define DMA_ADCBEVT 10 +#define DMA_ADCCINT1 11 +#define DMA_ADCCINT2 12 +#define DMA_ADCCINT3 13 +#define DMA_ADCCINT4 14 +#define DMA_ADCCEVT 15 +#define DMA_ADCDINT1 16 +#define DMA_ADCDINT2 17 +#define DMA_ADCDINT3 18 +#define DMA_ADCDINT4 19 +#define DMA_ADCDEVT 20 + +#define DMA_XINT1 29 +#define DMA_XINT2 30 +#define DMA_XINT3 31 +#define DMA_XINT4 32 +#define DMA_XINT5 33 + +#define DMA_EPWM1A 36 +#define DMA_EPWM1B 37 +#define DMA_EPWM2A 38 +#define DMA_EPWM2B 39 +#define DMA_EPWM3A 40 +#define DMA_EPWM3B 41 +#define DMA_EPWM4A 42 +#define DMA_EPWM4B 43 +#define DMA_EPWM5A 44 +#define DMA_EPWM5B 45 +#define DMA_EPWM6A 46 +#define DMA_EPWM6B 47 +#define DMA_EPWM7A 48 +#define DMA_EPWM7B 49 +#define DMA_EPWM8A 50 +#define DMA_EPWM8B 51 +#define DMA_EPWM9A 52 +#define DMA_EPWM9B 53 +#define DMA_EPWM10A 54 +#define DMA_EPWM10B 55 +#define DMA_EPWM11A 56 +#define DMA_EPWM11B 57 +#define DMA_EPWM12A 58 +#define DMA_EPWM12B 59 +#define DMA_EPWM13A 60 +#define DMA_EPWM13B 61 +#define DMA_EPWM14A 62 +#define DMA_EPWM14B 63 +#define DMA_EPWM15A 64 +#define DMA_EPWM15B 65 +#define DMA_EPWM16A 66 +#define DMA_EPWM16B 67 + +#define DMA_TINT0 68 +#define DMA_TINT1 69 +#define DMA_TINT2 70 + +#define DMA_MXEVTA 71 +#define DMA_MREVTA 72 +#define DMA_MXEVTB 73 +#define DMA_MREVTB 74 + +#define DMA_SD1FLT1 95 +#define DMA_SD1FLT2 96 +#define DMA_SD1FLT3 97 +#define DMA_SD1FLT4 98 + +#define DMA_SD2FLT1 99 +#define DMA_SD2FLT2 100 +#define DMA_SD2FLT3 101 +#define DMA_SD2FLT4 102 + +#define DMA_SPIATX 109 +#define DMA_SPIARX 110 +#define DMA_SPIBTX 111 +#define DMA_SPIBRX 112 +#define DMA_SPICTX 113 +#define DMA_SPICRX 114 + +#define DMA_USBRX1 131 +#define DMA_USBTX1 132 +#define DMA_USBRX2 133 +#define DMA_USBTX2 134 +#define DMA_USBRX3 135 +#define DMA_USBTX3 136 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif + +#endif // - end of F2837xD_DMA_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_EPwm_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_EPwm_defines.h new file mode 100644 index 00000000000..a45ae46f627 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_EPwm_defines.h @@ -0,0 +1,342 @@ +//########################################################################### +// +// FILE: F2837xD_EPwm_defines.h +// +// TITLE: #defines used in EPwm examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_EPWM_DEFINES_H +#define F2837xD_EPWM_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// TBCTL (Time-Base Control) +// + +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// + +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// + +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// + +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// + +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// + +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// + +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// TZDCSEL (Trip Zone Digital Compare) +// + +// +// DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits +// +#define TZ_EVT_DISABLE 0x0 +#define TZ_DCAH_LOW 0x1 +#define TZ_DCAH_HI 0x2 +#define TZ_DCAL_LOW 0x3 +#define TZ_DCAL_HI 0x4 +#define TZ_DCAL_HI_DCAH_LOW 0x5 + +#define TZ_DCBH_LOW 0x1 +#define TZ_DCBH_HI 0x2 +#define TZ_DCBL_LOW 0x3 +#define TZ_DCBL_HI 0x4 +#define TZ_DCBL_HI_DCBH_LOW 0x5 + +// +// ETSEL (Event Trigger Select) +// +#define ET_DCAEVT1SOC 0x0 +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTR_PRDZERO 0x3 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// + +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// + +// +// HRCNFG +// +#define HR_DISABLE 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 +#define HR_CTR_ZERO_PRD 0x2 + +#define HR_NORM_B 0x0 +#define HR_INVERT_B 0x1 + +// +// DC (Digital Compare) +// + +// +// DCTRIPSEL +// +#define DC_TZ1 0x0 +#define DC_TZ2 0x1 +#define DC_TZ3 0x2 +#define DC_TRIPIN1 0x0 +#define DC_TRIPIN2 0x1 +#define DC_TRIPIN3 0x2 +#define DC_TRIPIN4 0x3 +#define DC_TRIPIN5 0x4 +#define DC_TRIPIN6 0x5 +#define DC_TRIPIN7 0x6 +#define DC_TRIPIN8 0x7 +#define DC_TRIPIN9 0x8 +#define DC_TRIPIN10 0x9 +#define DC_TRIPIN11 0xA +#define DC_TRIPIN12 0xB +// Reserved 0xC +#define DC_TRIPIN14 0xD +#define DC_TRIPIN15 0xE +#define DC_COMBINATION 0xF + +// +// DCFCTL +// +#define DC_SRC_DCAEVT1 0x0 +#define DC_SRC_DCAEVT2 0x1 +#define DC_SRC_DCBEVT1 0x2 +#define DC_SRC_DCBEVT2 0x3 + +#define DC_PULSESEL_PRD 0x0 +#define DC_PULSESEL_ZERO 0x1 +#define DC_PULSESEL_ZERO_PRD 0x2 + +#define DC_BLANK_DISABLE 0x0 +#define DC_BLANK_ENABLE 0x1 + +#define DC_BLANK_NOTINV 0x0 +#define DC_BLANK_INV 0x1 + +// +//DCACTL/DCBCTL +// +#define DC_EVT1 0x0 +#define DC_EVT2 0x0 +#define DC_EVT_FLT 0x1 +#define DC_EVT_SYNC 0x0 +#define DC_EVT_ASYNC 0x1 +#define DC_SOC_DISABLE 0x0 +#define DC_SOC_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_EPWM_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Emif_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Emif_defines.h new file mode 100644 index 00000000000..cb11472b045 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Emif_defines.h @@ -0,0 +1,319 @@ +//########################################################################### +// +// FILE: F2837xD_Emif_defines.h +// +// TITLE: #defines used in EMIF examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_EMIF_DEFINES_H +#define F2837xD_EMIF_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +//cpu1 to cpu2 message for handshaking +// +#define CPU1_CPU2_MSG 0x3fd00 + +// +//cpu2_to_cpu1 message ram for handshaking +// +#define CPU2_CPU1_MSG 0x3fb00 + +#define MSEL_EMIF1_CPU1 0x93A5CE71 +#define MSEL_EMIF1_CPU2 0x93A5CE72 +#define MSEL_DEF_3 0x93A5CE73 +#define MSEL_DEF_0 0x93A5CE70 +#define MSEL_DEF_1 0x93A5CE71 +#define MSEL_DEF_2 0x93A5CE72 + +// +//soft reset bit register +// +#define EMIF_SOFT_PRES_REG 0x5D084 + +// +//Device capability/EMIF customization register +// +#define EMIF_DEV_DC_REG 0x5D014 + +// +// Values for ASYNC_CSx_CR Registers +// +#define EMIF_ASYNC_ASIZE_8 0x0 +#define EMIF_ASYNC_ASIZE_16 0x1 +#define EMIF_ASYNC_ASIZE_32 0x2 + +#define EMIF_ASYNC_TA_1 0x0 +#define EMIF_ASYNC_TA_2 0x4 +#define EMIF_ASYNC_TA_3 0x8 +#define EMIF_ASYNC_TA_4 0xC + +#define EMIF_ASYNC_RHOLD_1 0x00 +#define EMIF_ASYNC_RHOLD_2 0x10 +#define EMIF_ASYNC_RHOLD_3 0x20 +#define EMIF_ASYNC_RHOLD_4 0x30 +#define EMIF_ASYNC_RHOLD_5 0x40 +#define EMIF_ASYNC_RHOLD_6 0x50 +#define EMIF_ASYNC_RHOLD_7 0x60 +#define EMIF_ASYNC_RHOLD_8 0x70 + +#define EMIF_ASYNC_RSTROBE_1 0x0000 +#define EMIF_ASYNC_RSTROBE_2 0x0080 +#define EMIF_ASYNC_RSTROBE_3 0x0100 +#define EMIF_ASYNC_RSTROBE_4 0x0180 +#define EMIF_ASYNC_RSTROBE_5 0x0200 +#define EMIF_ASYNC_RSTROBE_6 0x0280 +#define EMIF_ASYNC_RSTROBE_7 0x0300 +#define EMIF_ASYNC_RSTROBE_8 0x0380 +#define EMIF_ASYNC_RSTROBE_9 0x0400 +#define EMIF_ASYNC_RSTROBE_10 0x0480 +#define EMIF_ASYNC_RSTROBE_11 0x0500 +#define EMIF_ASYNC_RSTROBE_12 0x0580 +#define EMIF_ASYNC_RSTROBE_13 0x0600 +#define EMIF_ASYNC_RSTROBE_14 0x0680 +#define EMIF_ASYNC_RSTROBE_15 0x0700 +#define EMIF_ASYNC_RSTROBE_16 0x0780 +#define EMIF_ASYNC_RSTROBE_17 0x0800 +#define EMIF_ASYNC_RSTROBE_18 0x0880 +#define EMIF_ASYNC_RSTROBE_19 0x0900 +#define EMIF_ASYNC_RSTROBE_20 0x0980 +#define EMIF_ASYNC_RSTROBE_21 0x0A00 +#define EMIF_ASYNC_RSTROBE_22 0x0A80 +#define EMIF_ASYNC_RSTROBE_23 0x0B00 +#define EMIF_ASYNC_RSTROBE_24 0x0B80 +#define EMIF_ASYNC_RSTROBE_25 0x0C00 +#define EMIF_ASYNC_RSTROBE_26 0x0C80 +#define EMIF_ASYNC_RSTROBE_27 0x0D00 +#define EMIF_ASYNC_RSTROBE_28 0x0D80 +#define EMIF_ASYNC_RSTROBE_29 0x0E00 +#define EMIF_ASYNC_RSTROBE_30 0x0E80 +#define EMIF_ASYNC_RSTROBE_31 0x0F00 +#define EMIF_ASYNC_RSTROBE_32 0x0F80 +#define EMIF_ASYNC_RSTROBE_33 0x1000 +#define EMIF_ASYNC_RSTROBE_34 0x1080 +#define EMIF_ASYNC_RSTROBE_35 0x1100 +#define EMIF_ASYNC_RSTROBE_36 0x1180 +#define EMIF_ASYNC_RSTROBE_37 0x1200 +#define EMIF_ASYNC_RSTROBE_38 0x1280 +#define EMIF_ASYNC_RSTROBE_39 0x1300 +#define EMIF_ASYNC_RSTROBE_40 0x1380 +#define EMIF_ASYNC_RSTROBE_41 0x1400 +#define EMIF_ASYNC_RSTROBE_42 0x1480 +#define EMIF_ASYNC_RSTROBE_43 0x1500 +#define EMIF_ASYNC_RSTROBE_44 0x1580 +#define EMIF_ASYNC_RSTROBE_45 0x1600 +#define EMIF_ASYNC_RSTROBE_46 0x1680 +#define EMIF_ASYNC_RSTROBE_47 0x1700 +#define EMIF_ASYNC_RSTROBE_48 0x1780 +#define EMIF_ASYNC_RSTROBE_49 0x1800 +#define EMIF_ASYNC_RSTROBE_50 0x1880 +#define EMIF_ASYNC_RSTROBE_51 0x1900 +#define EMIF_ASYNC_RSTROBE_52 0x1980 +#define EMIF_ASYNC_RSTROBE_53 0x1A00 +#define EMIF_ASYNC_RSTROBE_54 0x1A80 +#define EMIF_ASYNC_RSTROBE_55 0x1B00 +#define EMIF_ASYNC_RSTROBE_56 0x1B80 +#define EMIF_ASYNC_RSTROBE_57 0x1C00 +#define EMIF_ASYNC_RSTROBE_58 0x1C80 +#define EMIF_ASYNC_RSTROBE_59 0x1D00 +#define EMIF_ASYNC_RSTROBE_60 0x1D80 +#define EMIF_ASYNC_RSTROBE_61 0x1E00 +#define EMIF_ASYNC_RSTROBE_62 0x1E80 +#define EMIF_ASYNC_RSTROBE_63 0x1F00 +#define EMIF_ASYNC_RSTROBE_64 0x1F80 + +#define EMIF_ASYNC_RSETUP_1 0x0000 +#define EMIF_ASYNC_RSETUP_2 0x2000 +#define EMIF_ASYNC_RSETUP_3 0x4000 +#define EMIF_ASYNC_RSETUP_4 0x6000 +#define EMIF_ASYNC_RSETUP_5 0x8000 +#define EMIF_ASYNC_RSETUP_6 0xA000 +#define EMIF_ASYNC_RSETUP_7 0xC000 +#define EMIF_ASYNC_RSETUP_8 0xE000 +#define EMIF_ASYNC_RSETUP_9 0x10000 +#define EMIF_ASYNC_RSETUP_10 0x12000 +#define EMIF_ASYNC_RSETUP_11 0x14000 +#define EMIF_ASYNC_RSETUP_12 0x16000 +#define EMIF_ASYNC_RSETUP_13 0x18000 +#define EMIF_ASYNC_RSETUP_14 0x1A000 +#define EMIF_ASYNC_RSETUP_15 0x1C000 +#define EMIF_ASYNC_RSETUP_16 0x1E000 + +#define EMIF_ASYNC_WHOLD_1 0x00000 +#define EMIF_ASYNC_WHOLD_2 0x20000 +#define EMIF_ASYNC_WHOLD_3 0x40000 +#define EMIF_ASYNC_WHOLD_4 0x60000 +#define EMIF_ASYNC_WHOLD_5 0x80000 +#define EMIF_ASYNC_WHOLD_6 0xA0000 +#define EMIF_ASYNC_WHOLD_7 0xC0000 +#define EMIF_ASYNC_WHOLD_8 0xE0000 + +#define EMIF_ASYNC_WSTROBE_1 0x0000000 +#define EMIF_ASYNC_WSTROBE_2 0x0100000 +#define EMIF_ASYNC_WSTROBE_3 0x0200000 +#define EMIF_ASYNC_WSTROBE_4 0x0300000 +#define EMIF_ASYNC_WSTROBE_5 0x0400000 +#define EMIF_ASYNC_WSTROBE_6 0x0500000 +#define EMIF_ASYNC_WSTROBE_7 0x0600000 +#define EMIF_ASYNC_WSTROBE_8 0x0700000 +#define EMIF_ASYNC_WSTROBE_9 0x0800000 +#define EMIF_ASYNC_WSTROBE_10 0x0900000 +#define EMIF_ASYNC_WSTROBE_11 0x0A00000 +#define EMIF_ASYNC_WSTROBE_12 0x0B00000 +#define EMIF_ASYNC_WSTROBE_13 0x0C00000 +#define EMIF_ASYNC_WSTROBE_14 0x0D00000 +#define EMIF_ASYNC_WSTROBE_15 0x0E00000 +#define EMIF_ASYNC_WSTROBE_16 0x0F00000 +#define EMIF_ASYNC_WSTROBE_17 0x1000000 +#define EMIF_ASYNC_WSTROBE_18 0x1100000 +#define EMIF_ASYNC_WSTROBE_19 0x1200000 +#define EMIF_ASYNC_WSTROBE_20 0x1300000 +#define EMIF_ASYNC_WSTROBE_21 0x1400000 +#define EMIF_ASYNC_WSTROBE_22 0x1500000 +#define EMIF_ASYNC_WSTROBE_23 0x1600000 +#define EMIF_ASYNC_WSTROBE_24 0x1700000 +#define EMIF_ASYNC_WSTROBE_25 0x1800000 +#define EMIF_ASYNC_WSTROBE_26 0x1900000 +#define EMIF_ASYNC_WSTROBE_27 0x1A00000 +#define EMIF_ASYNC_WSTROBE_28 0x1B00000 +#define EMIF_ASYNC_WSTROBE_29 0x1C00000 +#define EMIF_ASYNC_WSTROBE_30 0x1D00000 +#define EMIF_ASYNC_WSTROBE_31 0x1E00000 +#define EMIF_ASYNC_WSTROBE_32 0x1F00000 +#define EMIF_ASYNC_WSTROBE_33 0x2000000 +#define EMIF_ASYNC_WSTROBE_34 0x2100000 +#define EMIF_ASYNC_WSTROBE_35 0x2200000 +#define EMIF_ASYNC_WSTROBE_36 0x2300000 +#define EMIF_ASYNC_WSTROBE_37 0x2400000 +#define EMIF_ASYNC_WSTROBE_38 0x2500000 +#define EMIF_ASYNC_WSTROBE_39 0x2600000 +#define EMIF_ASYNC_WSTROBE_40 0x2700000 +#define EMIF_ASYNC_WSTROBE_41 0x2800000 +#define EMIF_ASYNC_WSTROBE_42 0x2900000 +#define EMIF_ASYNC_WSTROBE_43 0x2A00000 +#define EMIF_ASYNC_WSTROBE_44 0x2B00000 +#define EMIF_ASYNC_WSTROBE_45 0x2C00000 +#define EMIF_ASYNC_WSTROBE_46 0x2D00000 +#define EMIF_ASYNC_WSTROBE_47 0x2E00000 +#define EMIF_ASYNC_WSTROBE_48 0x2F00000 +#define EMIF_ASYNC_WSTROBE_49 0x3000000 +#define EMIF_ASYNC_WSTROBE_50 0x3100000 +#define EMIF_ASYNC_WSTROBE_51 0x3200000 +#define EMIF_ASYNC_WSTROBE_52 0x3300000 +#define EMIF_ASYNC_WSTROBE_53 0x3400000 +#define EMIF_ASYNC_WSTROBE_54 0x3500000 +#define EMIF_ASYNC_WSTROBE_55 0x3600000 +#define EMIF_ASYNC_WSTROBE_56 0x3700000 +#define EMIF_ASYNC_WSTROBE_57 0x3800000 +#define EMIF_ASYNC_WSTROBE_58 0x3900000 +#define EMIF_ASYNC_WSTROBE_59 0x3A00000 +#define EMIF_ASYNC_WSTROBE_60 0x3B00000 +#define EMIF_ASYNC_WSTROBE_61 0x3C00000 +#define EMIF_ASYNC_WSTROBE_62 0x3D00000 +#define EMIF_ASYNC_WSTROBE_63 0x3E00000 +#define EMIF_ASYNC_WSTROBE_64 0x3F00000 + +#define EMIF_ASYNC_WSETUP_1 0x00000000 +#define EMIF_ASYNC_WSETUP_2 0x04000000 +#define EMIF_ASYNC_WSETUP_3 0x08000000 +#define EMIF_ASYNC_WSETUP_4 0x0C000000 +#define EMIF_ASYNC_WSETUP_5 0x10000000 +#define EMIF_ASYNC_WSETUP_6 0x14000000 +#define EMIF_ASYNC_WSETUP_7 0x18000000 +#define EMIF_ASYNC_WSETUP_8 0x1C000000 +#define EMIF_ASYNC_WSETUP_9 0x20000000 +#define EMIF_ASYNC_WSETUP_10 0x24000000 +#define EMIF_ASYNC_WSETUP_11 0x28000000 +#define EMIF_ASYNC_WSETUP_12 0x2C000000 +#define EMIF_ASYNC_WSETUP_13 0x30000000 +#define EMIF_ASYNC_WSETUP_14 0x34000000 +#define EMIF_ASYNC_WSETUP_15 0x38000000 +#define EMIF_ASYNC_WSETUP_16 0x3C000000 + +#define EMIF_ASYNC_EW_DISABLE 0x00000000 +#define EMIF_ASYNC_EW_ENABLE 0x40000000 + +#define EMIF_ASYNC_SS_DISABLE 0x00000000 +#define EMIF_ASYNC_SS_ENABLE 0x80000000 + +// +// Values for ASYNC_WCCR Register +// +#define EMIF_ASYNC_WCCR_WP_LOW 0x00000000 +#define EMIF_ASYNC_WCCR_WP_HIGH 0x01000000 + +// +// Read mask for the registers which has reserved bits. +// +#define ASYNC_WCCR_RDMASK 0xF0FF00FF +#define SDRAM_CR_RDMASK 0xE3FF7F7F +#define SDRAM_RCR_RDMASK 0x00071FFF +#define SDRAM_TR_RDMASK 0xFF77FF70 +#define SDR_EXT_TMNG_RDMASK 0x1F +#define INT_RAW_RDMASK 0x3F +#define INT_MASK_RDMASK 0x3F +#define IO_CTRL_RDMASK_RDMASK 0xFFFF +#define IO_STAT_RDMASK_RDMASK 0xF +#define NAND_FLASH_CTRL_RDMASK 0x3F3F +#define NAND_FLASH_STAT_RDMASK 0x30F0F +#define IODFT_TLECR_REG_RDMASK 0xFFFF +#define IODFT_TLGCR_REG_RDMASK 0x71FF +#define IODFT_TLAMR_REG_RDMASK 0x0FFFFFFF +#define IODFT_TLDCMR_REG_RDMASK 0x3fff3f07 +#define MODEL_REL_NUM_REG_RDMASK 0xFF +#define NAND_FLASH_4BIT_ECCLR_RDMASK 0x3F +#define NAND_FLASH_4BIT_ECCx_RDMASK 0x03ff03ff +#define NAND_FLASH_ERR_ADDRx_RDMASK 0x03ff03ff +#define NAND_FLASH_ERR_VALx_RDMASK 0x03ff03ff + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_EMIF_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Examples.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Examples.h new file mode 100644 index 00000000000..bd3a3994b02 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Examples.h @@ -0,0 +1,448 @@ +//########################################################################### +// +// FILE: F2837xD_Examples.h +// +// TITLE: F2837xD Device Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_EXAMPLES_H +#define F2837xD_EXAMPLES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// The following are values that can be passed to the +// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL integer multiplier +// +#define IMULT_0 0 +#define IMULT_1 1 +#define IMULT_2 2 +#define IMULT_3 3 +#define IMULT_4 4 +#define IMULT_5 5 +#define IMULT_6 6 +#define IMULT_7 7 +#define IMULT_8 8 +#define IMULT_9 9 +#define IMULT_10 10 +#define IMULT_11 11 +#define IMULT_12 12 +#define IMULT_13 13 +#define IMULT_14 14 +#define IMULT_15 15 +#define IMULT_16 16 +#define IMULT_17 17 +#define IMULT_18 18 +#define IMULT_19 19 +#define IMULT_20 20 +#define IMULT_21 21 +#define IMULT_22 22 +#define IMULT_23 23 +#define IMULT_24 24 +#define IMULT_25 25 +#define IMULT_26 26 +#define IMULT_27 27 +#define IMULT_28 28 +#define IMULT_29 29 +#define IMULT_30 30 +#define IMULT_31 31 +#define IMULT_32 32 +#define IMULT_33 33 +#define IMULT_34 34 +#define IMULT_35 35 +#define IMULT_36 36 +#define IMULT_37 37 +#define IMULT_38 38 +#define IMULT_39 39 +#define IMULT_40 40 +#define IMULT_41 41 +#define IMULT_42 42 +#define IMULT_43 43 +#define IMULT_44 44 +#define IMULT_45 45 +#define IMULT_46 46 +#define IMULT_47 47 +#define IMULT_48 48 +#define IMULT_49 49 +#define IMULT_50 50 +#define IMULT_51 51 +#define IMULT_52 52 +#define IMULT_53 53 +#define IMULT_54 54 +#define IMULT_55 55 +#define IMULT_56 56 +#define IMULT_57 57 +#define IMULT_58 58 +#define IMULT_59 59 +#define IMULT_60 60 +#define IMULT_61 61 +#define IMULT_62 62 +#define IMULT_63 63 +#define IMULT_64 64 +#define IMULT_65 65 +#define IMULT_66 66 +#define IMULT_67 67 +#define IMULT_68 68 +#define IMULT_69 69 +#define IMULT_70 70 +#define IMULT_71 71 +#define IMULT_72 72 +#define IMULT_73 73 +#define IMULT_74 74 +#define IMULT_75 75 +#define IMULT_76 76 +#define IMULT_77 77 +#define IMULT_78 78 +#define IMULT_79 79 +#define IMULT_80 80 +#define IMULT_81 81 +#define IMULT_82 82 +#define IMULT_83 83 +#define IMULT_84 84 +#define IMULT_85 85 +#define IMULT_86 86 +#define IMULT_87 87 +#define IMULT_88 88 +#define IMULT_89 89 +#define IMULT_90 90 +#define IMULT_91 91 +#define IMULT_92 92 +#define IMULT_93 93 +#define IMULT_94 94 +#define IMULT_95 95 +#define IMULT_96 96 +#define IMULT_97 97 +#define IMULT_98 98 +#define IMULT_99 99 +#define IMULT_100 100 +#define IMULT_101 101 +#define IMULT_102 102 +#define IMULT_103 103 +#define IMULT_104 104 +#define IMULT_105 105 +#define IMULT_106 106 +#define IMULT_107 107 +#define IMULT_108 108 +#define IMULT_109 109 +#define IMULT_110 110 +#define IMULT_111 111 +#define IMULT_112 112 +#define IMULT_113 113 +#define IMULT_114 114 +#define IMULT_115 115 +#define IMULT_116 116 +#define IMULT_117 117 +#define IMULT_118 118 +#define IMULT_119 119 +#define IMULT_120 120 +#define IMULT_121 121 +#define IMULT_122 122 +#define IMULT_123 123 +#define IMULT_124 124 +#define IMULT_125 125 +#define IMULT_126 126 +#define IMULT_127 127 + +// +// The following are values that can be passed to the +// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL fractional multiplier +// +#define FMULT_0 0 +#define FMULT_0pt25 1 +#define FMULT_0pt5 2 +#define FMULT_0pt75 3 + +// +// The following are values that can be passed to the +// InitSysPll() to select divsel for SYSPLL +// +#define PLLCLK_BY_1 0 +#define PLLCLK_BY_2 1 +#define PLLCLK_BY_4 2 +#define PLLCLK_BY_6 3 +#define PLLCLK_BY_8 4 +#define PLLCLK_BY_10 5 +#define PLLCLK_BY_12 6 +#define PLLCLK_BY_14 7 +#define PLLCLK_BY_16 8 +#define PLLCLK_BY_18 9 +#define PLLCLK_BY_20 10 +#define PLLCLK_BY_22 11 +#define PLLCLK_BY_24 12 +#define PLLCLK_BY_26 13 +#define PLLCLK_BY_28 14 +#define PLLCLK_BY_30 15 +#define PLLCLK_BY_32 16 +#define PLLCLK_BY_34 17 +#define PLLCLK_BY_36 18 +#define PLLCLK_BY_38 19 +#define PLLCLK_BY_40 20 +#define PLLCLK_BY_42 21 +#define PLLCLK_BY_44 22 +#define PLLCLK_BY_46 23 +#define PLLCLK_BY_48 24 +#define PLLCLK_BY_50 25 +#define PLLCLK_BY_52 26 +#define PLLCLK_BY_54 27 +#define PLLCLK_BY_56 28 +#define PLLCLK_BY_58 29 +#define PLLCLK_BY_60 30 +#define PLLCLK_BY_62 31 +#define PLLCLK_BY_64 32 +#define PLLCLK_BY_66 33 +#define PLLCLK_BY_68 34 +#define PLLCLK_BY_70 35 +#define PLLCLK_BY_72 36 +#define PLLCLK_BY_74 37 +#define PLLCLK_BY_76 38 +#define PLLCLK_BY_78 39 +#define PLLCLK_BY_80 40 +#define PLLCLK_BY_82 41 +#define PLLCLK_BY_84 42 +#define PLLCLK_BY_86 43 +#define PLLCLK_BY_88 44 +#define PLLCLK_BY_90 45 +#define PLLCLK_BY_92 46 +#define PLLCLK_BY_94 47 +#define PLLCLK_BY_96 48 +#define PLLCLK_BY_98 49 +#define PLLCLK_BY_100 50 +#define PLLCLK_BY_102 51 +#define PLLCLK_BY_104 52 +#define PLLCLK_BY_106 53 +#define PLLCLK_BY_108 54 +#define PLLCLK_BY_110 55 +#define PLLCLK_BY_112 56 +#define PLLCLK_BY_114 57 +#define PLLCLK_BY_116 58 +#define PLLCLK_BY_118 59 +#define PLLCLK_BY_120 60 +#define PLLCLK_BY_122 61 +#define PLLCLK_BY_124 62 +#define PLLCLK_BY_126 63 + +// +// The following are values that can be passed to the +// InitAuxPll() to select divsel for AUXPLL +// +#define AUXPLLRAWCLK_BY_1 0 +#define AUXPLLRAWCLK_BY_2 1 +#define AUXPLLRAWCLK_BY_4 2 +#define AUXPLLRAWCLK_BY_8 3 + +// +// The following are values that can be passed to the +// IntOsc2Sel() & XtalOscSel() to select system PLL (or) AUX PLL +// +#define SYSTEM_PLL (Uint16) 0 +#define AUX_PLL (Uint16) 1 + +// +// The following are values that can be passed to the +// InitSysPll() & InitAuxPll() to select clock source +// +#define INT_OSC2 0 +#define XTAL_OSC 1 +#define INT_OSC1 2 +#define AUXCLKIN 4 + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example: 200 MHz devices: +// CLKIN is a 10 MHz crystal or internal 10 MHz oscillator +// +// In step 1 the user specified the PLL multiplier = 40 for a +// 200 MHz CPU clock (SYSCLKOUT = 200 MHz). +// +// In this case, the CPU_RATE will be 5.000L +// Uncomment the line: #define CPU_RATE 5.000L +// + +#define CPU_RATE 5.00L // for a 200MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 5.263L // for a 190MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 5.556L // for a 180MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 5.882L // for a 170MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 6.250L // for a 160MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.692L // for a 130MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) + +// +// The following pointer to a function call calibrates the ADC reference, +// DAC offset, and internal oscillators +// +#define Device_cal (void (*)(void))0x070282 + +// +// The following pointers to functions calibrate the ADC linearity. Use this +// in the AdcSetMode(...) function only +// +#define CalAdcaINL (void (*)(void))0x0703B4 +#define CalAdcbINL (void (*)(void))0x0703B2 +#define CalAdccINL (void (*)(void))0x0703B0 +#define CalAdcdINL (void (*)(void))0x0703AE + +// +// The following pointer to a function call looks up the ADC offset trim for a +// given condition. Use this in the AdcSetMode(...) function only. +// +#define GetAdcOffsetTrimOTP (Uint16 (*)(Uint16 OTPoffset))0x0703AC + +// +// Includes +// +#include "F2837xD_GlobalPrototypes.h" // Prototypes for global functions + // within the .c files. +#include "F2837xD_cputimervars.h" +#include "F2837xD_Cla_defines.h" // Macros used for CLA examples. +#include "F2837xD_EPwm_defines.h" // Macros used for PWM examples. +#include "F2837xD_Adc_defines.h" // Macros used for ADC examples. +#include "F2837xD_Emif_defines.h" // Macros used for EMIF examples. +#include "F2837xD_Gpio_defines.h" // Macros used for GPIO support code +#include "F2837xD_I2c_defines.h" // Macros used for I2C examples. +#include "F2837xD_Ipc_defines.h" // Macros used for IPC support code. +#include "F2837xD_Pie_defines.h" // Macros used for PIE examples. +#include "F2837xD_Dma_defines.h" // Macros used for DMA examples. +#include "F2837xD_SysCtrl_defines.h" // Macros used for LPM support code +#include "F2837xD_Upp_defines.h" // Macros used for UPP examples. + +#define PARTNO_2837xPACKAGEHERE 0x00 + +#define CPU_FRQ_200MHZ 1 +#define CPU_FRQ_150MHZ 0 +#define CPU_FRQ_120MHZ 0 + +// +// Include files not used with F/BIOS +// +#ifndef F28_BIOS +#include "F2837xD_defaultisr.h" +#endif + +extern void F28x_usDelay(long LoopCount); + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) F28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) + +// +// Timer Operations: +// + +// +// Start Timer: +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// Start Timer: +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of F2837xD_EXAMPLES_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_GlobalPrototypes.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_GlobalPrototypes.h new file mode 100644 index 00000000000..1b63dc48eee --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_GlobalPrototypes.h @@ -0,0 +1,363 @@ +//########################################################################### +// +// FILE: F2837xD_GlobalPrototypes.h +// +// TITLE: Global prototypes for F2837xD Examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_GLOBALPROTOTYPES_H +#define F2837xD_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Function Prototypes (Shared) +// +extern void EnableInterrupts(void); +extern void InitAPwm1Gpio(void); +extern void InitCAN(void); +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(Uint16 pin); +extern void InitECap2Gpio(Uint16 pin); +extern void InitECap3Gpio(Uint16 pin); +extern void InitECap4Gpio(Uint16 pin); +extern void InitECap5Gpio(Uint16 pin); +extern void InitECap6Gpio(Uint16 pin); +extern void InitEQep1Gpio(void); +extern void InitEQep2Gpio(void); +extern void InitEQep3Gpio(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +extern void InitEPwm4Gpio(void); +extern void InitEPwm5Gpio(void); +extern void InitEPwm6Gpio(void); +extern void InitEPwm7Gpio(void); +extern void InitEPwm8Gpio(void); +extern void InitEPwm9Gpio(void); +extern void InitEPwm10Gpio(void); +extern void InitEPwm11Gpio(void); +extern void InitEPwm12Gpio(void); +extern void InitPeripheralClocks(void); +extern void DisablePeripheralClocks(void); +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, + Uint16 divsel); +extern void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, + Uint16 divsel); + +#define KickDog ServiceDog // For compatibility with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); + +extern Uint16 CsmUnlock(void); +extern void SysIntOsc1Sel (void); +extern void SysIntOsc2Sel (void); +extern void SysXtalOscSel (void); + +extern void AuxIntOsc2Sel (void); +extern void AuxXtalOscSel (void); +extern void AuxAuxClkSel (void); + +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); +extern void InitFlash_Bank0(void); +extern void InitFlash_Bank1(void); +extern void FlashOff(void); +extern void FlashOff_Bank0(void); +extern void FlashOff_Bank1(void); +extern void SeizeFlashPump(void); +extern void SeizeFlashPump_Bank0(void); +extern void SeizeFlashPump_Bank1(void); +extern void ReleaseFlashPump(void); + +// +//LPM functions in F2837xD_SysCtrl.c +// +void IDLE(); +void STANDBY(); +void HALT(); +void HIB(); + +// +//ADC functions +// +extern void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode); +extern void CalAdcINL(Uint16 adc); + +// +// DMA Functions +// +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +// +//GPIO Functions +// +extern void InitGpio(); +extern void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition); +extern void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags); +extern void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags); +extern void GPIO_SetupXINT1Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT2Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT3Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT4Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT5Gpio(Uint16 gpioNumber); +extern void GPIO_SelectIpcInt(Uint16 newFlag); +extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void); +extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void); +extern void GPIO_EnableUnbondedIOPullups(void); +Uint16 GPIO_ReadPin(Uint16 gpioNumber); +void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal); + +// +//IPC Functions +// +extern void InitIpc(); +extern Uint64 ReadIpcTimer(); +extern void SendIpcData(void *data, Uint16 word_length, Uint16 flag); +extern void RecvIpcData(void *recv_buf, Uint16 word_length); +extern void FillIpcSendData(Uint16 fill_data); +extern void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, + Uint16 flag); +extern void SendIpcFlag(Uint16 flag); +extern void AckIpcFlag(Uint16 flag); +extern void CancelIpcFlag(Uint16 flag); +extern void WaitForIpcFlag(Uint16 flag); +extern void WaitForIpcAck(Uint16 flag); +extern void IpcSync(Uint16 flag); + +// +// CAN Functions +// +extern void CanGpioPinMuxing(Uint32 ulBase, Uint16 canTxRxPin); +extern void CanAGpioConfig(Uint16 canaTxRxPin); +extern void CanBGpioConfig(Uint16 canbTxRxPin); +extern void CanModuleClkSelect(Uint32 ulBase, Uint16 ucSource); + +// +// I2C Functions +// +extern void I2cAGpioConfig(Uint16 I2caDataClkPin); +extern void I2cBGpioConfig(Uint16 I2cbDataClkPin); + +// +// McBSP functions +// McBSPA +// +extern void InitMcbspa(void); +extern void InitMcbspaInt(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +extern void InitMcbspaGpio(void); +extern void delay_loop(void); + +// +// McBSPB +// +extern void InitMcbspb(void); +extern void InitMcbspbInt(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +extern void InitMcbspbGpio(void); + +// +//Temp Sensor Functions +// +extern void InitTempSensor(float32 vrefhi_voltage); +extern int16 GetTemperatureC(int16 sensorSample); +extern int16 GetTemperatureK(int16 sensorSample); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in Flash to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsLoadSize; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsRunEnd; +extern Uint16 RamfuncsRunSize; + +// +// External Boot ROM variable definitions +// +extern Uint16 EmuBMode; +extern Uint16 EmuBootPins; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_GLOBALPROTOTYPES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Gpio_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Gpio_defines.h new file mode 100644 index 00000000000..ecbff656187 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Gpio_defines.h @@ -0,0 +1,116 @@ +//########################################################################### +// +// FILE: F2837xD_Gpio_defines.h +// +// TITLE: F2837xD GPIO support definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_GPIO_DEFINES_H +#define F2837xD_GPIO_DEFINES_H + +// +// Defines +// + +// +//CPU pin masters for GPIO_SelectPinMux() +// +#define GPIO_MUX_CPU1 0x0 +#define GPIO_MUX_CPU1CLA 0x1 +#define GPIO_MUX_CPU2 0x2 +#define GPIO_MUX_CPU2CLA 0x3 + +// +//Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3, +//QUAL6, and ASYNC) take up two bits and must be in the order specified. +// +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 +#define GPIO_PUSHPULL 0 +#define GPIO_PULLUP (1 << 0) +#define GPIO_INVERT (1 << 1) +#define GPIO_OPENDRAIN (1 << 2) +#define GPIO_SYNC (0x0 << 4) +#define GPIO_QUAL3 (0x1 << 4) +#define GPIO_QUAL6 (0x2 << 4) +#define GPIO_ASYNC (0x3 << 4) + +// +//Flags for GPIO_SetupLock(). +// +#define GPIO_UNLOCK 0 +#define GPIO_LOCK 1 + +// +//Commands for the CPU2->CPU1 GPIO configuration interrupt handler +// +#define GPIO_CMD_INIT 1L +#define GPIO_CMD_PINMUX 2L +#define GPIO_CMD_PINOPTS 3L +#define GPIO_CMD_WRITE32 4L +#define GPIO_CMD_WRITE16 5L +#define GPIO_CMD_READ32 6L +#define GPIO_CMD_READ16 7L + +// +//Helpful constants for array-based access to GPIO registers +// +#define GPY_CTRL_OFFSET (0x40/2) +#define GPY_DATA_OFFSET (0x8/2) + +#define GPYQSEL (0x2/2) +#define GPYMUX (0x6/2) +#define GPYDIR (0xA/2) +#define GPYPUD (0xC/2) +#define GPYINV (0x10/2) +#define GPYODR (0x12/2) +#define GPYGMUX (0x20/2) +#define GPYCSEL (0x28/2) +#define GPYLOCK (0x3C/2) +#define GPYCR (0x3E/2) + +#define GPYDAT (0x0/2) +#define GPYSET (0x2/2) +#define GPYCLEAR (0x4/2) +#define GPYTOGGLE (0x6/2) + +#endif // end of F2837xD_GPIO_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_I2c_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_I2c_defines.h new file mode 100644 index 00000000000..95ed970e7ff --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_I2c_defines.h @@ -0,0 +1,184 @@ +//########################################################################### +// +// FILE: F2837xD_I2c_defines.h +// +// TITLE: F2837xD I2C Common Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_I2C_DEFINES_H +#define F2837xD_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + + +// +// These are the Defines to select I2C pin muxing when calling the functions +// I2cAGpioConfig() & I2cBGpioConfig() in F2837xD_I2C.c +// +#define I2C_A_GPIO0_GPIO1 1 //switch case 1 +#define I2C_A_GPIO32_GPIO33 2 //switch case 2 +#define I2C_A_GPIO42_GPIO43 3 //switch case 3 +#define I2C_A_GPIO91_GPIO92 4 //switch case 4 +#define I2C_A_GPIO63104_GPIO105 5 //switch case 5 + +#define I2C_B_GPIO2_GPIO3 1 //switch case 1 +#define I2C_B_GPIO134_GPIO35 2 //switch case 2 +#define I2C_B_GPIO40_GPIO41 3 //switch case 3 +#define I2C_B_GPIO66_GPIO69 4 //switch case 4 + +// +// Globals +// + +// +// I2C Message Structure +// +struct I2CMSG { + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a + // restart as a master receiver with a + // stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put + // in MsgBuffer) + Uint16 MemoryHighAddr; // EEPROM address of data associated with + // msg (high byte) + Uint16 MemoryLowAddr; // EEPROM address of data associated with + // msg (low byte) + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that + // MAX_BUFFER_SIZE can be is 16 due + // to the FIFO's +}; + +#endif // end of F2837xD_I2C_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_defines.h new file mode 100644 index 00000000000..404caee0b14 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_defines.h @@ -0,0 +1,70 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_defines.h +// +// TITLE: F2837xD IPC support definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_IPC_DEFINES_H +#define F2837xD_IPC_DEFINES_H + +// +// Defines +// +#define C1TOC2_MSG_RAM ((void *)0x3FC00) +#define C2TOC1_MSG_RAM ((void *)0x3F800) + +#if defined(CPU1) + #define SEND_MSG_RAM C1TOC2_MSG_RAM + #define RECV_MSG_RAM C2TOC1_MSG_RAM +#elif defined(CPU2) + #define SEND_MSG_RAM C2TOC1_MSG_RAM + #define RECV_MSG_RAM C1TOC2_MSG_RAM +#endif +#define MSG_RAM_SIZE 0x400 + +// +//Used with SendIpcData() and SendIpcCommand() to avoid setting a flag +// +#define NO_IPC_FLAG 32 + +#endif // end of F2837xD_IPC_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_drivers.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_drivers.h new file mode 100644 index 00000000000..648ad6a83ac --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Ipc_drivers.h @@ -0,0 +1,511 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_drivers.h +// +// TITLE: Defines and Macros for the IPC Controller +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +//! \addtogroup ipc_driver_api +//! @{ +// + +#ifndef F2837xD_IPC_DRIVERS_H +#define F2837xD_IPC_DRIVERS_H + +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +#ifdef __cplusplus +extern "C" { +#endif + +// +// Included Files +// +#include "F2837xD_device.h" + +// +// Defines +// + +// +// The following are values that are used to define the maximum size of the +// global circular buffer variables g_asIPCCPU1toCPU2Buffers and +// g_asIPCCPU2toCPU1Buffers. They are also used in the IpcPut() and IpcGet() +// functions. IPC_BUFFER_SIZE and NUM_IPC_INTERRUPTS are user-configurable. +// +#define IPC_BUFFER_SIZE 4 // # of tIpcMessage messages in + // circular buffer + // (must be interval of 2) +#define NUM_IPC_INTERRUPTS 4 // # of IPC interrupts using circular + // buffer + // (must be same number on both CPUs +#define MAX_BUFFER_INDEX IPC_BUFFER_SIZE - 1 + +// +// The following are values that can be passed to IPCInitialize() +// as the usCPU1IpcInterrupt and usCPU2IpcInterrupt parameters +// +#define IPC_INT0 0x0001 +#define IPC_INT1 0x0002 +#define IPC_INT2 0x0003 +#define IPC_INT3 0x0004 + +// +// The following are values that are returned from all of the IPCCtoM command +// functions to determine whether the command was successfully sent or not. +// +#define STATUS_FAIL 0x0001 +#define STATUS_PASS 0x0000 + +// +// The following are values that can be passed to IPCReqMemAccess() as +// usMaster parameter to determine which processor to give master access to +// GSx blocks. +// +#define IPC_GSX_CPU1_MASTER 0x0001 +#define IPC_GSX_CPU2_MASTER 0x0000 + +// +// The following are values that can be passed to all IPC CPU1 to CPU2 or +// CPU2 to CPU1 command functions as bBlock parameter to determine whether to +// wait/block until a slot in PutBuffer is available if it is full, or to exit +// with a failure status. +// +#define ENABLE_BLOCKING 0x0001 +#define DISABLE_BLOCKING 0x0000 + +// +// The following are values that can be passed to IPCCtoMDataRead(), +// IPCCCtoMSetBits(),IPCCCtoMSetBits_Protected(), IPCCCtoMClearBits(), +// IPCCCtoMClearBits_Protected(), IPCCCtoMDataWrite(), +// IPCCtoMDataWrite_Protected() +// as usLength parameter to determine whether command applies to 16- or 32-bit +// data word. +// +#define IPC_LENGTH_16_BITS 0x00000001 +#define IPC_LENGTH_32_BITS 0x00000002 + +// +// The following are values that can be passed to IPCReqMemAccess() as +// ulMask parameter to configure GSxMSEL_REG register for master access to Sx +// RAM block. +// +#define GS0_ACCESS 0x00000001 // Master Access to GS0 +#define GS1_ACCESS 0x00000002 // Master Access to GS1 +#define GS2_ACCESS 0x00000004 // Master Access to GS2 +#define GS3_ACCESS 0x00000008 // Master Access to GS3 +#define GS4_ACCESS 0x00000010 // Master Access to GS4 +#define GS5_ACCESS 0x00000020 // Master Access to GS5 +#define GS6_ACCESS 0x00000040 // Master Access to GS6 +#define GS7_ACCESS 0x00000080 // Master Access to GS7 +#define GS8_ACCESS 0x00000100 // Master Access to GS8 +#define GS9_ACCESS 0x00000200 // Master Access to GS9 +#define GS10_ACCESS 0x00000400 // Master Access to GS10 +#define GS11_ACCESS 0x00000800 // Master Access to GS11 +#define GS12_ACCESS 0x00001000 // Master Access to GS12 +#define GS13_ACCESS 0x00002000 // Master Access to GS13 +#define GS14_ACCESS 0x00004000 // Master Access to GS14 +#define GS15_ACCESS 0x00008000 // Master Access to GS15 + +// +// The following are values that can be passed to IPCCtoMTaskBusy() as the +// ulFlags parameter. +// IPC_FLAG17 - IPC_FLAG32 can also be passed to IPCtoMDataRead() and +// IPCCtoMReadBlock() as the ulResponseFlag parameter. +// +#define NO_FLAG 0x00000000 // NO FLAG +#define IPC_FLAG0 0x00000001 // IPC FLAG 0 +#define IPC_FLAG1 0x00000002 // IPC FLAG 1 +#define IPC_FLAG2 0x00000004 // IPC FLAG 2 +#define IPC_FLAG3 0x00000008 // IPC FLAG 3 +#define IPC_FLAG4 0x00000010 // IPC FLAG 4 +#define IPC_FLAG5 0x00000020 // IPC FLAG 5 +#define IPC_FLAG6 0x00000040 // IPC FLAG 6 +#define IPC_FLAG7 0x00000080 // IPC FLAG 7 +#define IPC_FLAG8 0x00000100 // IPC FLAG 8 +#define IPC_FLAG9 0x00000200 // IPC FLAG 9 +#define IPC_FLAG10 0x00000400 // IPC FLAG 10 +#define IPC_FLAG11 0x00000800 // IPC FLAG 11 +#define IPC_FLAG12 0x00001000 // IPC FLAG 12 +#define IPC_FLAG13 0x00002000 // IPC FLAG 13 +#define IPC_FLAG14 0x00004000 // IPC FLAG 14 +#define IPC_FLAG15 0x00008000 // IPC FLAG 15 +#define IPC_FLAG16 0x00010000 // IPC FLAG 16 +#define IPC_FLAG17 0x00020000 // IPC FLAG 17 +#define IPC_FLAG18 0x00040000 // IPC FLAG 18 +#define IPC_FLAG19 0x00080000 // IPC FLAG 19 +#define IPC_FLAG20 0x00100000 // IPC FLAG 20 +#define IPC_FLAG21 0x00200000 // IPC FLAG 21 +#define IPC_FLAG22 0x00400000 // IPC FLAG 22 +#define IPC_FLAG23 0x00800000 // IPC FLAG 23 +#define IPC_FLAG24 0x01000000 // IPC FLAG 24 +#define IPC_FLAG25 0x02000000 // IPC FLAG 25 +#define IPC_FLAG26 0x04000000 // IPC FLAG 26 +#define IPC_FLAG27 0x08000000 // IPC FLAG 27 +#define IPC_FLAG28 0x10000000 // IPC FLAG 28 +#define IPC_FLAG29 0x20000000 // IPC FLAG 29 +#define IPC_FLAG30 0x40000000 // IPC FLAG 30 +#define IPC_FLAG31 0x80000000 // IPC FLAG 31 + +// +// The following are values that are used by all command functions and passed +// between processors in tIpcMessage.ulmessage or in the xTOyIPCCOM register +// to determine what command is requested by the sending processor. +// +#define IPC_SET_BITS_16 0x00000001 // Used for IPC-Lite +#define IPC_SET_BITS_32 0x00000002 // Used for IPC-Lite +#define IPC_CLEAR_BITS_16 0x00000003 // Used for IPC-Lite +#define IPC_CLEAR_BITS_32 0x00000004 // Used for IPC-Lite +#define IPC_DATA_WRITE_16 0x00000005 // Used for IPC-Lite +#define IPC_DATA_WRITE_32 0x00000006 // Used for IPC-Lite +#define IPC_DATA_READ_16 0x00000007 // Used for Boot ROM +#define IPC_DATA_READ_32 0x00000008 // Used for Boot ROM +#define IPC_DATA_READ 0x00000008 +#define IPC_SET_BITS_16_PROTECTED 0x00000009 // Used for IPC-Lite +#define IPC_SET_BITS_32_PROTECTED 0x0000000A // Used for IPC-Lite +#define IPC_CLEAR_BITS_16_PROTECTED 0x0000000B // Used for IPC-Lite +#define IPC_CLEAR_BITS_32_PROTECTED 0x0000000C // Used for IPC-Lite +#define IPC_DATA_WRITE_16_PROTECTED 0x0000000D // Used for IPC-Lite +#define IPC_DATA_WRITE_32_PROTECTED 0x0000000E // Used for IPC-Lite + +// +// 0x0000000F and 0x0000010 are reserved by boot ROM +// + +#define IPC_BRANCH 0x00000011 +#define IPC_FUNC_CALL 0x00000012 +#define IPC_MTOC_EXECUTE_BOOTMODE_CMD 0x00000013 + +#define IPC_SET_BITS 0x00010001 +#define IPC_CLEAR_BITS 0x00010002 +#define IPC_DATA_WRITE 0x00010003 +#define IPC_BLOCK_READ 0x00010004 +#define IPC_BLOCK_WRITE 0x00010005 +#define IPC_DATA_READ_PROTECTED 0x00010007 +#define IPC_SET_BITS_PROTECTED 0x00010008 +#define IPC_CLEAR_BITS_PROTECTED 0x00010009 +#define IPC_DATA_WRITE_PROTECTED 0x0001000A +#define IPC_BLOCK_WRITE_PROTECTED 0x0001000B + +// +// The following are values that can be passed into the +// IPCBootControlSystem() function in the ulBootMode parameter. +// +#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013 + +// +// Below are the values programmed into IPCBOOTMODE register +// +#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000A +#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000B + +// +// The following value is used by the +// IPCBootControlSystem() function to limit the allowed boot mode values. +// +#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000C + +// +// The following values report on the CPU02 boot ROM status at all times while +// the CPU02 is booting, and will reside in IPCBOOTSTS[11:0]. +// + +// +// CPU02 has not filled in a valid value yet +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000 + +// +// CPU02 has started to boot, but not completed +// the boot process yet +// +#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001 + +// +// CPU02 has completed the boot and is ready for +// CPU01 TO CPU02 IPC commands +// +#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002 + +// +// CPU02 ACKs the command in CPU01 TO CPU01 +// BOOTMODE register +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003 + +// +// CPU02 un-supported command in CPU01 TO CPU01 +// BOOTMODE register +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004 + +// +// CPU2 NAKs the current boot command in +// CPU01 TO CPU01 BOOTMODE register +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005 + +// +//! A structure that defines an IPC message. These fields are used by the +//! IPC drivers to determine handling of data passed between processors. +//! Although they have a defined naming scheme, they can also be used +//! generically +//! to pass 32-bit data words between processors. +// +typedef struct +{ + //! The command passed between processor systems. + uint32_t ulcommand; + + //! The receiving processor address the command is requesting action on. + uint32_t uladdress; + + //! A 32-bit variable, the usage of which is determined by ulcommand. + //! The most common usage is to pass length requirements + //! with the upper 16-bits storing a Response Flag for read commands. + uint32_t uldataw1; + + //! A 32-bit variable, the usage of which is determined by ulcommand. + //! For block transfers, this variable is generally the address in + //! shared memory used to pass data between processors. + uint32_t uldataw2; + +} tIpcMessage; + +// +//! A structure that defines an IPC control instance. These +//! fields are used by the IPC drivers, and normally it is not necessary for +//! user software to directly read or write fields in the table. +// +typedef struct +{ + //! The address of the PutBuffer IPC message (in MSGRAM) + tIpcMessage *psPutBuffer; + + //! The IPC INT flag to set when sending messages + //! for this IPC controller instance. + uint32_t ulPutFlag; + + //! The address of the PutBuffer Write index (in MSGRAM) + uint16_t *pusPutWriteIndex; + + //! The address of the PutBuffer Read index (in MSGRAM) + uint16_t *pusPutReadIndex; + + //! The address of the GetBuffer IPC message(in MSGRAM) + tIpcMessage *psGetBuffer; + + //! The address of the GetBuffer Write Index (in MSGRAM) + uint16_t *pusGetWriteIndex; + + //! The address of the GetBuffer Read Index (in MSGRAM) + uint16_t *pusGetReadIndex; + +} tIpcController; + +// +// A type definition for the IPC function call command. +// +typedef uint32_t (*tfIpcFuncCall)(uint32_t ulParam); + +// +// Prototypes for Circular Buffers +// +extern tIpcMessage g_asIPCCPU1toCPU2Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; +extern tIpcMessage g_asIPCCPU2toCPU1Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; + +// +// Function Prototypes +// +extern void IPCInitialize (volatile tIpcController *psController, + uint16_t usCPU2IpcInterrupt, + uint16_t usCPU1IpcInterrupt); +extern uint16_t IpcPut (volatile tIpcController *psController, + tIpcMessage *psMessage, + uint16_t bBlock); +extern uint16_t IpcGet (volatile tIpcController *psController, + tIpcMessage *psMessage, + uint16_t bBlock); +extern uint16_t IPCLtoRDataRead (volatile tIpcController *psController, + uint32_t ulAddress, void *pvData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRDataRead_Protected (volatile tIpcController *psController, + uint32_t ulAddress, void *pvData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRSetBits(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength,uint16_t bBlock); +extern uint16_t IPCLtoRSetBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint16_t bBlock); +extern uint16_t IPCLtoRClearBits(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength,uint16_t bBlock); +extern uint16_t IPCLtoRClearBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint16_t bBlock); +extern uint16_t IPCLtoRDataWrite(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRDataWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRBlockRead(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulShareAddress, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRBlockWrite(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulShareAddress, + uint16_t usLength, uint16_t usWordLength, + uint16_t bBlock); +extern uint16_t IPCLtoRBlockWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, + uint32_t ulShareAddress, + uint16_t usLength, + uint16_t usWordLength, + uint16_t bBlock); +extern uint16_t IPCLtoRFunctionCall(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulParam, + uint16_t bBlock); +extern uint16_t IPCLtoRSendMessage(volatile tIpcController *psController, + uint32_t ulCommand, uint32_t ulAddress, + uint32_t ulDataW1, uint32_t ulDataW2, + uint16_t bBlock); +#if defined (CPU2) +uint16_t +IPCReqMemAccess (volatile tIpcController *psController, uint32_t ulMask, + uint16_t usMaster, uint16_t bBlock); +#endif + +extern void IPCRtoLDataWrite(tIpcMessage *psMessage); +extern void IPCRtoLDataWrite_Protected(tIpcMessage *psMessage); +extern void IPCRtoLDataRead(volatile tIpcController *psController, + tIpcMessage *psMessage, uint16_t bBlock); +extern void IPCRtoLDataRead_Protected(volatile tIpcController *psController, + tIpcMessage *psMessage,uint16_t bBlock); +extern void IPCRtoLSetBits(tIpcMessage *psMessage); +extern void IPCRtoLSetBits_Protected(tIpcMessage *psMessage); +extern void IPCRtoLClearBits(tIpcMessage *psMessage); +extern void IPCRtoLClearBits_Protected(tIpcMessage *psMessage); +extern void IPCRtoLBlockRead(tIpcMessage *psMessage); +extern void IPCRtoLBlockWrite(tIpcMessage *psMessage); +extern void IPCRtoLBlockWrite_Protected(tIpcMessage *psMessage); +extern void IPCRtoLFunctionCall(tIpcMessage *psMessage); + +// +// IPC Lite Driver Prototype Definitions +// +extern uint16_t IPCLiteLtoRGetResult (void *pvData, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRDataRead(uint32_t ulFlag, uint32_t ulAddress, + uint16_t usLength, uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRSetBits(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRSetBits_Protected (uint32_t ulFlag, + uint32_t ulAddress, + uint32_t ulMask, + uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRClearBits(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRClearBits_Protected (uint32_t ulFlag, + uint32_t ulAddress, + uint32_t ulMask, + uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRDataWrite(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulData, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRDataWrite_Protected(uint32_t ulFlag, + uint32_t ulAddress, + uint32_t ulData, + uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRFunctionCall(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulParam, uint32_t ulStatusFlag); +extern uint16_t IPCLiteReqMemAccess (uint32_t ulFlag, uint32_t ulMask, + uint16_t ulMaster, uint32_t ulStatusFlag); +extern void IPCLiteRtoLDataRead(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLSetBits(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLSetBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLClearBits(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLClearBits_Protected (uint32_t ulFlag, + uint32_t ulStatusFlag); +extern void IPCLiteRtoLDataWrite(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLDataWrite_Protected(uint32_t ulFlag, + uint32_t ulStatusFlag); +extern void IPCLiteRtoLFunctionCall(uint32_t ulFlag, uint32_t ulStatusFlag); + +// +// IPC Utility Driver Prototype Definitions +// +extern void IPCRtoLFlagAcknowledge (uint32_t ulFlags); +extern Uint16 IPCRtoLFlagBusy (uint32_t ulFlags); +extern Uint16 IPCLtoRFlagBusy (uint32_t ulFlags); +extern void IPCLtoRFlagSet (uint32_t ulFlags); +extern void IPCLtoRFlagClear (uint32_t ulFlags); +extern uint32_t IPCGetBootStatus (void); +extern uint16_t IPCBootCPU2(uint32_t ulBootMode); +#ifdef __cplusplus +} +#endif /* extern "C" */ + +// +// Close the Doxygen group. +//! @} +// + +#endif // end of F2837xD_IPC_DRIVERS_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Pie_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Pie_defines.h new file mode 100644 index 00000000000..1905d88ca86 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Pie_defines.h @@ -0,0 +1,74 @@ +//########################################################################### +// +// FILE: F2837xD_Pie_defines.h +// +// TITLE: #defines used in PIE examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_PIE_DEFINES_H +#define F2837xD_PIE_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_PIE_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_SWPrioritizedIsrLevels.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_SWPrioritizedIsrLevels.h new file mode 100644 index 00000000000..6fd27009654 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_SWPrioritizedIsrLevels.h @@ -0,0 +1,20681 @@ +//########################################################################### +// +// FILE: F2837xD_SWPrioritizedIsrLevels.h +// +// TITLE: F28 Devices Software Prioritized Interrupt Service Routine +// Level definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SW_PRIORITZIED_ISR_H +#define F2837xD_SW_PRIORITZIED_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Interrupt Enable Register Allocation For F2837xD Devices: +// +// Interrupts can be enabled/disabled using the CPU interrupt enable register +// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12). +// +// +// Set "Global" Interrupt Priority Level (IER register): +// +// The user must set the appropriate priority level for each of the CPU +// interrupts. This is termed as the "global" priority. The priority level +// must be a number between 1 (highest) to 16 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used. +// +// Note: The priority levels below are used to calculate the IER register +// interrupt masks MINT1 to MINT16. +// +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 16 = lowest priority +// +#define INT1PL 2 // Group1 Interrupts (PIEIER1) +#define INT2PL 1 // Group2 Interrupts (PIEIER2) +#define INT3PL 4 // Group3 Interrupts (PIEIER3) +#define INT4PL 2 // Group4 Interrupts (PIEIER4) +#define INT5PL 2 // Group5 Interrupts (PIEIER5) +#define INT6PL 3 // Group6 Interrupts (PIEIER6) +#define INT7PL 5 // Group7 Interrupts (PIEIER6) +#define INT8PL 5 // Group8 Interrupts (PIEIER6) +#define INT9PL 3 // Group9 Interrupts (PIEIER9) +#define INT10PL 6 // Group10 Interrupts (PIEIER6) +#define INT11PL 6 // Group11 Interrupts (PIEIER6) +#define INT12PL 8 // Group12 Interrupts (PIEIER6) +#define INT13PL 4 // XINT13 +#define INT14PL 4 // INT14 (TINT2) +#define INT15PL 4 // DATALOG +#define INT16PL 4 // RTOSINT + +// +// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers): +// +// The user must set the appropriate priority level for each of the PIE +// interrupts. This is termed as the "group" priority. The priority level +// must be a number between 1 (highest) to 16 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used: +// +// Note: The priority levels below are used to calculate the following +// PIEIER register interrupt masks: +// MG1_1 to MG1_16 +// MG2_1 to MG2_16 +// MG3_1 to MG3_16 +// MG4_1 to MG4_16 +// MG5_1 to MG5_16 +// MG6_1 to MG6_16 +// MG7_1 to MG7_16 +// MG8_1 to MG8_16 +// MG9_1 to MG9_16 +// MG10_1 to MG10_16 +// MG11_1 to MG11_16 +// MG12_1 to MG12_16 +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 16 = lowest priority +// +#define G1_1PL 5 // ADCA1_INT +#define G1_2PL 3 // ADCB1_INT +#define G1_3PL 1 // ADCC1_INT +#define G1_4PL 4 // XINT1_INT +#define G1_5PL 4 // XINT2_INT +#define G1_6PL 1 // ADCD1_INT +#define G1_7PL 12 // TIMER0_INT +#define G1_8PL 5 // WAKE_INT +#define G1_9PL 0 // Reserved +#define G1_10PL 0 // Reserved +#define G1_11PL 0 // Reserved +#define G1_12PL 0 // Reserved +#define G1_13PL 8 // IPC1_INT +#define G1_14PL 13 // IPC2_INT +#define G1_15PL 15 // IPC3_INT +#define G1_16PL 9 // IPC4_INT + +#define G2_1PL 13 // EPWM1_TZ_INT +#define G2_2PL 1 // EPWM2_TZ_INT +#define G2_3PL 1 // EPWM3_TZ_INT +#define G2_4PL 9 // EPWM4_TZ_INT +#define G2_5PL 3 // EPWM5_TZ_INT +#define G2_6PL 13 // EPWM6_TZ_INT +#define G2_7PL 9 // EPWM7_TZ_INT +#define G2_8PL 13 // EPWM8_TZ_INT +#define G2_9PL 15 // EPWM9_TZ_INT +#define G2_10PL 11 // EPWM10_TZ_INT +#define G2_11PL 7 // EPWM11_TZ_INT +#define G2_12PL 10 // EPWM12_TZ_INT +#define G2_13PL 0 // Reserved +#define G2_14PL 0 // Reserved +#define G2_15PL 0 // Reserved +#define G2_16PL 0 // Reserved + +#define G3_1PL 5 // EPWM1_INT +#define G3_2PL 9 // EPWM2_INT +#define G3_3PL 5 // EPWM3_INT +#define G3_4PL 2 // EPWM4_INT +#define G3_5PL 12 // EPWM5_INT +#define G3_6PL 4 // EPWM6_INT +#define G3_7PL 2 // EPWM7_INT +#define G3_8PL 13 // EPWM8_INT +#define G3_9PL 4 // EPWM9_INT +#define G3_10PL 12 // EPWM10_INT +#define G3_11PL 4 // EPWM11_INT +#define G3_12PL 14 // EPWM12_INT +#define G3_13PL 0 // Reserved +#define G3_14PL 0 // Reserved +#define G3_15PL 0 // Reserved +#define G3_16PL 0 // Reserved + +#define G4_1PL 3 // ECAP1_INT +#define G4_2PL 3 // ECAP2_INT +#define G4_3PL 3 // ECAP3_INT +#define G4_4PL 6 // ECAP4_INT +#define G4_5PL 7 // ECAP5_INT +#define G4_6PL 7 // ECAP6_INT +#define G4_7PL 0 // Reserved +#define G4_8PL 0 // Reserved +#define G4_9PL 0 // Reserved +#define G4_10PL 0 // Reserved +#define G4_11PL 0 // Reserved +#define G4_12PL 0 // Reserved +#define G4_13PL 0 // Reserved +#define G4_14PL 0 // Reserved +#define G4_15PL 0 // Reserved +#define G4_16PL 0 // Reserved + +#define G5_1PL 6 // EQEP1_INT +#define G5_2PL 5 // EQEP2_INT +#define G5_3PL 5 // EQEP3_INT +#define G5_4PL 1 // Reserved +#define G5_5PL 9 // CLB1_INT +#define G5_6PL 10 // CLB2_INT +#define G5_7PL 15 // CLB3_INT +#define G5_8PL 13 // CLB4_INT +#define G5_9PL 12 // SD1_INT +#define G5_10PL 9 // SD2_INT +#define G5_11PL 0 // Reserved +#define G5_12PL 0 // Reserved +#define G5_13PL 0 // Reserved +#define G5_14PL 0 // Reserved +#define G5_15PL 0 // Reserved +#define G5_16PL 0 // Reserved + +#define G6_1PL 1 // SPIA_RX_INT +#define G6_2PL 7 // SPIA_TX_INT +#define G6_3PL 3 // SPIB_RX_INT +#define G6_4PL 3 // SPIB_TX_INT +#define G6_5PL 10 // MCBSPA_RX_INT +#define G6_6PL 7 // MCBSPA_TX_INT +#define G6_7PL 6 // MCBSPB_RX_INT +#define G6_8PL 13 // MCBSPB_TX_INT +#define G6_9PL 14 // SPIC_RX_INT +#define G6_10PL 3 // SPIC_TX_INT +#define G6_11PL 0 // Reserved +#define G6_12PL 0 // Reserved +#define G6_13PL 0 // Reserved +#define G6_14PL 0 // Reserved +#define G6_15PL 0 // Reserved +#define G6_16PL 0 // Reserved + +#define G7_1PL 1 // DMA_CH1_INT +#define G7_2PL 11 // DMA_CH2_INT +#define G7_3PL 14 // DMA_CH3_INT +#define G7_4PL 3 // DMA_CH4_INT +#define G7_5PL 13 // DMA_CH5_INT +#define G7_6PL 14 // DMA_CH6_INT +#define G7_7PL 0 // Reserved +#define G7_8PL 0 // Reserved +#define G7_9PL 0 // Reserved +#define G7_10PL 0 // Reserved +#define G7_11PL 0 // Reserved +#define G7_12PL 0 // Reserved +#define G7_13PL 0 // Reserved +#define G7_14PL 0 // Reserved +#define G7_15PL 0 // Reserved +#define G7_16PL 0 // Reserved + +#define G8_1PL 14 // I2CA_INT +#define G8_2PL 10 // I2CA_FIFO_INT +#define G8_3PL 11 // I2CB_INT +#define G8_4PL 9 // I2CB_FIFO_INT +#define G8_5PL 12 // SCIC_RX_INT +#define G8_6PL 2 // SCIC_TX_INT +#define G8_7PL 8 // SCID_RX_INT +#define G8_8PL 7 // SCID_TX_INT +#define G8_9PL 0 // Reserved +#define G8_10PL 0 // Reserved +#define G8_11PL 0 // Reserved +#define G8_12PL 0 // Reserved +#define G8_13PL 0 // Reserved +#define G8_14PL 0 // Reserved +#define G8_15PL 1 // UPPA_INT +#define G8_16PL 0 // Reserved + +#define G9_1PL 12 // SCIA_RX_INT +#define G9_2PL 14 // SCIA_TX_INT +#define G9_3PL 11 // SCIB_RX_INT +#define G9_4PL 6 // SCIB_TX_INT +#define G9_5PL 14 // CANA0_INT +#define G9_6PL 10 // CANA1_INT +#define G9_7PL 10 // CANB0_INT +#define G9_8PL 5 // CANB1_INT +#define G9_9PL 0 // Reserved +#define G9_10PL 0 // Reserved +#define G9_11PL 0 // Reserved +#define G9_12PL 0 // Reserved +#define G9_13PL 0 // Reserved +#define G9_14PL 0 // Reserved +#define G9_15PL 12 // USBA_INT +#define G9_16PL 0 // Reserved + +#define G10_1PL 14 // ADCA_EVT_INT +#define G10_2PL 3 // ADCA2_INT +#define G10_3PL 1 // ADCA3_INT +#define G10_4PL 12 // ADCA4_INT +#define G10_5PL 5 // ADCB_EVT_INT +#define G10_6PL 11 // ADCB2_INT +#define G10_7PL 12 // ADCB3_INT +#define G10_8PL 13 // ADCB4_INT +#define G10_9PL 7 // ADCC_EVT_INT +#define G10_10PL 8 // ADCC2_INT +#define G10_11PL 4 // ADCC3_INT +#define G10_12PL 9 // ADCC4_INT +#define G10_13PL 2 // ADCD_EVT_INT +#define G10_14PL 10 // ADCD2_INT +#define G10_15PL 11 // ADCD3_INT +#define G10_16PL 5 // ADCD4_INT + +#define G11_1PL 9 // CLA1_1_INT +#define G11_2PL 6 // CLA1_2_INT +#define G11_3PL 9 // CLA1_3_INT +#define G11_4PL 9 // CLA1_4_INT +#define G11_5PL 6 // CLA1_5_INT +#define G11_6PL 13 // CLA1_6_INT +#define G11_7PL 10 // CLA1_7_INT +#define G11_8PL 15 // CLA1_8_INT +#define G11_9PL 0 // Reserved +#define G11_10PL 0 // Reserved +#define G11_11PL 0 // Reserved +#define G11_12PL 0 // Reserved +#define G11_13PL 0 // Reserved +#define G11_14PL 0 // Reserved +#define G11_15PL 0 // Reserved +#define G11_16PL 0 // Reserved + +#define G12_1PL 3 // XINT3_INT +#define G12_2PL 6 // XINT4_INT +#define G12_3PL 10 // XINT5_INT +#define G12_4PL 5 // Reserved +#define G12_5PL 2 // FMC_INT +#define G12_6PL 11 // VCU_INT +#define G12_7PL 14 // FPU_OVERFLOW_ISR +#define G12_8PL 14 // FPU_UNDERFLOW_ISR +#define G12_9PL 6 // EMIF_ERROR_ISR +#define G12_10PL 5 // RAM_CORRECTABLE_ERROR_ISR +#define G12_11PL 4 // FLASH_CORRECTABLE_ERROR_ISR +#define G12_12PL 12 // RAM_ACCESS_VIOLATION_INT +#define G12_13PL 8 // SYS_PLL_SLIP_INT +#define G12_14PL 2 // AUX_PLL_SLIP_INT +#define G12_15PL 12 // CLA_UNDERFLOW_INT +#define G12_16PL 2 // CLA_OVERFLOW_INT + +// +// There should be no need to modify code below this line +// +// Automatically generate IER interrupt masks MINT1 to MINT16: +// +// Beginning of MINT1: +#if (INT1PL == 0) +#define MINT1_1PL ~(1 << 0) +#else +#define MINT1_1PL 0xFFFF +#endif + +#if (INT2PL >= INT1PL) || (INT2PL == 0) +#define MINT1_2PL ~(1 << 1) +#else +#define MINT1_2PL 0xFFFF +#endif + +#if (INT3PL >= INT1PL) || (INT3PL == 0) +#define MINT1_3PL ~(1 << 2) +#else +#define MINT1_3PL 0xFFFF +#endif + +#if (INT4PL >= INT1PL) || (INT4PL == 0) +#define MINT1_4PL ~(1 << 3) +#else +#define MINT1_4PL 0xFFFF +#endif + +#if (INT5PL >= INT1PL) || (INT5PL == 0) +#define MINT1_5PL ~(1 << 4) +#else +#define MINT1_5PL 0xFFFF +#endif + +#if (INT6PL >= INT1PL) || (INT6PL == 0) +#define MINT1_6PL ~(1 << 5) +#else +#define MINT1_6PL 0xFFFF +#endif + +#if (INT7PL >= INT1PL) || (INT7PL == 0) +#define MINT1_7PL ~(1 << 6) +#else +#define MINT1_7PL 0xFFFF +#endif + +#if (INT8PL >= INT1PL) || (INT8PL == 0) +#define MINT1_8PL ~(1 << 7) +#else +#define MINT1_8PL 0xFFFF +#endif + +#if (INT9PL >= INT1PL) || (INT9PL == 0) +#define MINT1_9PL ~(1 << 8) +#else +#define MINT1_9PL 0xFFFF +#endif + +#if (INT10PL >= INT1PL) || (INT10PL == 0) +#define MINT1_10PL ~(1 << 9) +#else +#define MINT1_10PL 0xFFFF +#endif + +#if (INT11PL >= INT1PL) || (INT11PL == 0) +#define MINT1_11PL ~(1 << 10) +#else +#define MINT1_11PL 0xFFFF +#endif + +#if (INT12PL >= INT1PL) || (INT12PL == 0) +#define MINT1_12PL ~(1 << 11) +#else +#define MINT1_12PL 0xFFFF +#endif + +#if (INT13PL >= INT1PL) || (INT13PL == 0) +#define MINT1_13PL ~(1 << 12) +#else +#define MINT1_13PL 0xFFFF +#endif + +#if (INT14PL >= INT1PL) || (INT14PL == 0) +#define MINT1_14PL ~(1 << 13) +#else +#define MINT1_14PL 0xFFFF +#endif + +#if (INT15PL >= INT1PL) || (INT15PL == 0) +#define MINT1_15PL ~(1 << 14) +#else +#define MINT1_15PL 0xFFFF +#endif + +#if (INT16PL >= INT1PL) || (INT16PL == 0) +#define MINT1_16PL ~(1 << 15) +#else +#define MINT1_16PL 0xFFFF +#endif + +#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \ + MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \ + MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \ + MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL) +// End Of MINT1. + +// Beginning of MINT2: +#if (INT1PL >= INT2PL) || (INT1PL == 0) +#define MINT2_1PL ~(1 << 0) +#else +#define MINT2_1PL 0xFFFF +#endif + +#if (INT2PL == 0) +#define MINT2_2PL ~(1 << 1) +#else +#define MINT2_2PL 0xFFFF +#endif + +#if (INT3PL >= INT2PL) || (INT3PL == 0) +#define MINT2_3PL ~(1 << 2) +#else +#define MINT2_3PL 0xFFFF +#endif + +#if (INT4PL >= INT2PL) || (INT4PL == 0) +#define MINT2_4PL ~(1 << 3) +#else +#define MINT2_4PL 0xFFFF +#endif + +#if (INT5PL >= INT2PL) || (INT5PL == 0) +#define MINT2_5PL ~(1 << 4) +#else +#define MINT2_5PL 0xFFFF +#endif + +#if (INT6PL >= INT2PL) || (INT6PL == 0) +#define MINT2_6PL ~(1 << 5) +#else +#define MINT2_6PL 0xFFFF +#endif + +#if (INT7PL >= INT2PL) || (INT7PL == 0) +#define MINT2_7PL ~(1 << 6) +#else +#define MINT2_7PL 0xFFFF +#endif + +#if (INT8PL >= INT2PL) || (INT8PL == 0) +#define MINT2_8PL ~(1 << 7) +#else +#define MINT2_8PL 0xFFFF +#endif + +#if (INT9PL >= INT2PL) || (INT9PL == 0) +#define MINT2_9PL ~(1 << 8) +#else +#define MINT2_9PL 0xFFFF +#endif + +#if (INT10PL >= INT2PL) || (INT10PL == 0) +#define MINT2_10PL ~(1 << 9) +#else +#define MINT2_10PL 0xFFFF +#endif + +#if (INT11PL >= INT2PL) || (INT11PL == 0) +#define MINT2_11PL ~(1 << 10) +#else +#define MINT2_11PL 0xFFFF +#endif + +#if (INT12PL >= INT2PL) || (INT12PL == 0) +#define MINT2_12PL ~(1 << 11) +#else +#define MINT2_12PL 0xFFFF +#endif + +#if (INT13PL >= INT2PL) || (INT13PL == 0) +#define MINT2_13PL ~(1 << 12) +#else +#define MINT2_13PL 0xFFFF +#endif + +#if (INT14PL >= INT2PL) || (INT14PL == 0) +#define MINT2_14PL ~(1 << 13) +#else +#define MINT2_14PL 0xFFFF +#endif + +#if (INT15PL >= INT2PL) || (INT15PL == 0) +#define MINT2_15PL ~(1 << 14) +#else +#define MINT2_15PL 0xFFFF +#endif + +#if (INT16PL >= INT2PL) || (INT16PL == 0) +#define MINT2_16PL ~(1 << 15) +#else +#define MINT2_16PL 0xFFFF +#endif + +#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \ + MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \ + MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \ + MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL) +// End Of MINT2. + +// Beginning of MINT3: +#if (INT1PL >= INT3PL) || (INT1PL == 0) +#define MINT3_1PL ~(1 << 0) +#else +#define MINT3_1PL 0xFFFF +#endif + +#if (INT2PL >= INT3PL) || (INT2PL == 0) +#define MINT3_2PL ~(1 << 1) +#else +#define MINT3_2PL 0xFFFF +#endif + +#if (INT3PL == 0) +#define MINT3_3PL ~(1 << 2) +#else +#define MINT3_3PL 0xFFFF +#endif + +#if (INT4PL >= INT3PL) || (INT4PL == 0) +#define MINT3_4PL ~(1 << 3) +#else +#define MINT3_4PL 0xFFFF +#endif + +#if (INT5PL >= INT3PL) || (INT5PL == 0) +#define MINT3_5PL ~(1 << 4) +#else +#define MINT3_5PL 0xFFFF +#endif + +#if (INT6PL >= INT3PL) || (INT6PL == 0) +#define MINT3_6PL ~(1 << 5) +#else +#define MINT3_6PL 0xFFFF +#endif + +#if (INT7PL >= INT3PL) || (INT7PL == 0) +#define MINT3_7PL ~(1 << 6) +#else +#define MINT3_7PL 0xFFFF +#endif + +#if (INT8PL >= INT3PL) || (INT8PL == 0) +#define MINT3_8PL ~(1 << 7) +#else +#define MINT3_8PL 0xFFFF +#endif + +#if (INT9PL >= INT3PL) || (INT9PL == 0) +#define MINT3_9PL ~(1 << 8) +#else +#define MINT3_9PL 0xFFFF +#endif + +#if (INT10PL >= INT3PL) || (INT10PL == 0) +#define MINT3_10PL ~(1 << 9) +#else +#define MINT3_10PL 0xFFFF +#endif + +#if (INT11PL >= INT3PL) || (INT11PL == 0) +#define MINT3_11PL ~(1 << 10) +#else +#define MINT3_11PL 0xFFFF +#endif + +#if (INT12PL >= INT3PL) || (INT12PL == 0) +#define MINT3_12PL ~(1 << 11) +#else +#define MINT3_12PL 0xFFFF +#endif + +#if (INT13PL >= INT3PL) || (INT13PL == 0) +#define MINT3_13PL ~(1 << 12) +#else +#define MINT3_13PL 0xFFFF +#endif + +#if (INT14PL >= INT3PL) || (INT14PL == 0) +#define MINT3_14PL ~(1 << 13) +#else +#define MINT3_14PL 0xFFFF +#endif + +#if (INT15PL >= INT3PL) || (INT15PL == 0) +#define MINT3_15PL ~(1 << 14) +#else +#define MINT3_15PL 0xFFFF +#endif + +#if (INT16PL >= INT3PL) || (INT16PL == 0) +#define MINT3_16PL ~(1 << 15) +#else +#define MINT3_16PL 0xFFFF +#endif + +#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \ + MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \ + MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \ + MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL) +// End Of MINT3. + +// Beginning of MINT4: +#if (INT1PL >= INT4PL) || (INT1PL == 0) +#define MINT4_1PL ~(1 << 0) +#else +#define MINT4_1PL 0xFFFF +#endif + +#if (INT2PL >= INT4PL) || (INT2PL == 0) +#define MINT4_2PL ~(1 << 1) +#else +#define MINT4_2PL 0xFFFF +#endif + +#if (INT3PL >= INT4PL) || (INT3PL == 0) +#define MINT4_3PL ~(1 << 2) +#else +#define MINT4_3PL 0xFFFF +#endif + +#if (INT4PL == 0) +#define MINT4_4PL ~(1 << 3) +#else +#define MINT4_4PL 0xFFFF +#endif + +#if (INT5PL >= INT4PL) || (INT5PL == 0) +#define MINT4_5PL ~(1 << 4) +#else +#define MINT4_5PL 0xFFFF +#endif + +#if (INT6PL >= INT4PL) || (INT6PL == 0) +#define MINT4_6PL ~(1 << 5) +#else +#define MINT4_6PL 0xFFFF +#endif + +#if (INT7PL >= INT4PL) || (INT7PL == 0) +#define MINT4_7PL ~(1 << 6) +#else +#define MINT4_7PL 0xFFFF +#endif + +#if (INT8PL >= INT4PL) || (INT8PL == 0) +#define MINT4_8PL ~(1 << 7) +#else +#define MINT4_8PL 0xFFFF +#endif + +#if (INT9PL >= INT4PL) || (INT9PL == 0) +#define MINT4_9PL ~(1 << 8) +#else +#define MINT4_9PL 0xFFFF +#endif + +#if (INT10PL >= INT4PL) || (INT10PL == 0) +#define MINT4_10PL ~(1 << 9) +#else +#define MINT4_10PL 0xFFFF +#endif + +#if (INT11PL >= INT4PL) || (INT11PL == 0) +#define MINT4_11PL ~(1 << 10) +#else +#define MINT4_11PL 0xFFFF +#endif + +#if (INT12PL >= INT4PL) || (INT12PL == 0) +#define MINT4_12PL ~(1 << 11) +#else +#define MINT4_12PL 0xFFFF +#endif + +#if (INT13PL >= INT4PL) || (INT13PL == 0) +#define MINT4_13PL ~(1 << 12) +#else +#define MINT4_13PL 0xFFFF +#endif + +#if (INT14PL >= INT4PL) || (INT14PL == 0) +#define MINT4_14PL ~(1 << 13) +#else +#define MINT4_14PL 0xFFFF +#endif + +#if (INT15PL >= INT4PL) || (INT15PL == 0) +#define MINT4_15PL ~(1 << 14) +#else +#define MINT4_15PL 0xFFFF +#endif + +#if (INT16PL >= INT4PL) || (INT16PL == 0) +#define MINT4_16PL ~(1 << 15) +#else +#define MINT4_16PL 0xFFFF +#endif + +#define MINT4 (MINT4_1PL & MINT4_2PL & MINT4_3PL & MINT4_4PL & \ + MINT4_5PL & MINT4_6PL & MINT4_7PL & MINT4_8PL & \ + MINT4_9PL & MINT4_10PL & MINT4_11PL & MINT4_12PL & \ + MINT4_13PL & MINT4_14PL & MINT4_15PL & MINT4_16PL) +// End Of MINT4. + +// Beginning of MINT5: +#if (INT1PL >= INT5PL) || (INT1PL == 0) +#define MINT5_1PL ~(1 << 0) +#else +#define MINT5_1PL 0xFFFF +#endif + +#if (INT2PL >= INT5PL) || (INT2PL == 0) +#define MINT5_2PL ~(1 << 1) +#else +#define MINT5_2PL 0xFFFF +#endif + +#if (INT3PL >= INT5PL) || (INT3PL == 0) +#define MINT5_3PL ~(1 << 2) +#else +#define MINT5_3PL 0xFFFF +#endif + +#if (INT4PL >= INT5PL) || (INT4PL == 0) +#define MINT5_4PL ~(1 << 3) +#else +#define MINT5_4PL 0xFFFF +#endif + +#if (INT5PL == 0) +#define MINT5_5PL ~(1 << 4) +#else +#define MINT5_5PL 0xFFFF +#endif + +#if (INT6PL >= INT5PL) || (INT6PL == 0) +#define MINT5_6PL ~(1 << 5) +#else +#define MINT5_6PL 0xFFFF +#endif + +#if (INT7PL >= INT5PL) || (INT7PL == 0) +#define MINT5_7PL ~(1 << 6) +#else +#define MINT5_7PL 0xFFFF +#endif + +#if (INT8PL >= INT5PL) || (INT8PL == 0) +#define MINT5_8PL ~(1 << 7) +#else +#define MINT5_8PL 0xFFFF +#endif + +#if (INT9PL >= INT5PL) || (INT9PL == 0) +#define MINT5_9PL ~(1 << 8) +#else +#define MINT5_9PL 0xFFFF +#endif + +#if (INT10PL >= INT5PL) || (INT10PL == 0) +#define MINT5_10PL ~(1 << 9) +#else +#define MINT5_10PL 0xFFFF +#endif + +#if (INT11PL >= INT5PL) || (INT11PL == 0) +#define MINT5_11PL ~(1 << 10) +#else +#define MINT5_11PL 0xFFFF +#endif + +#if (INT12PL >= INT5PL) || (INT12PL == 0) +#define MINT5_12PL ~(1 << 11) +#else +#define MINT5_12PL 0xFFFF +#endif + +#if (INT13PL >= INT5PL) || (INT13PL == 0) +#define MINT5_13PL ~(1 << 12) +#else +#define MINT5_13PL 0xFFFF +#endif + +#if (INT14PL >= INT5PL) || (INT14PL == 0) +#define MINT5_14PL ~(1 << 13) +#else +#define MINT5_14PL 0xFFFF +#endif + +#if (INT15PL >= INT5PL) || (INT15PL == 0) +#define MINT5_15PL ~(1 << 14) +#else +#define MINT5_15PL 0xFFFF +#endif + +#if (INT16PL >= INT5PL) || (INT16PL == 0) +#define MINT5_16PL ~(1 << 15) +#else +#define MINT5_16PL 0xFFFF +#endif + +#define MINT5 (MINT5_1PL & MINT5_2PL & MINT5_3PL & MINT5_4PL & \ + MINT5_5PL & MINT5_6PL & MINT5_7PL & MINT5_8PL & \ + MINT5_9PL & MINT5_10PL & MINT5_11PL & MINT5_12PL & \ + MINT5_13PL & MINT5_14PL & MINT5_15PL & MINT5_16PL) +// End Of MINT5. + +// Beginning of MINT6: +#if (INT1PL >= INT6PL) || (INT1PL == 0) +#define MINT6_1PL ~(1 << 0) +#else +#define MINT6_1PL 0xFFFF +#endif + +#if (INT2PL >= INT6PL) || (INT2PL == 0) +#define MINT6_2PL ~(1 << 1) +#else +#define MINT6_2PL 0xFFFF +#endif + +#if (INT3PL >= INT6PL) || (INT3PL == 0) +#define MINT6_3PL ~(1 << 2) +#else +#define MINT6_3PL 0xFFFF +#endif + +#if (INT4PL >= INT6PL) || (INT4PL == 0) +#define MINT6_4PL ~(1 << 3) +#else +#define MINT6_4PL 0xFFFF +#endif + +#if (INT5PL >= INT6PL) || (INT5PL == 0) +#define MINT6_5PL ~(1 << 4) +#else +#define MINT6_5PL 0xFFFF +#endif + +#if (INT6PL == 0) +#define MINT6_6PL ~(1 << 5) +#else +#define MINT6_6PL 0xFFFF +#endif + +#if (INT7PL >= INT6PL) || (INT7PL == 0) +#define MINT6_7PL ~(1 << 6) +#else +#define MINT6_7PL 0xFFFF +#endif + +#if (INT8PL >= INT6PL) || (INT8PL == 0) +#define MINT6_8PL ~(1 << 7) +#else +#define MINT6_8PL 0xFFFF +#endif + +#if (INT9PL >= INT6PL) || (INT9PL == 0) +#define MINT6_9PL ~(1 << 8) +#else +#define MINT6_9PL 0xFFFF +#endif + +#if (INT10PL >= INT6PL) || (INT10PL == 0) +#define MINT6_10PL ~(1 << 9) +#else +#define MINT6_10PL 0xFFFF +#endif + +#if (INT11PL >= INT6PL) || (INT11PL == 0) +#define MINT6_11PL ~(1 << 10) +#else +#define MINT6_11PL 0xFFFF +#endif + +#if (INT12PL >= INT6PL) || (INT12PL == 0) +#define MINT6_12PL ~(1 << 11) +#else +#define MINT6_12PL 0xFFFF +#endif + +#if (INT13PL >= INT6PL) || (INT13PL == 0) +#define MINT6_13PL ~(1 << 12) +#else +#define MINT6_13PL 0xFFFF +#endif + +#if (INT14PL >= INT6PL) || (INT14PL == 0) +#define MINT6_14PL ~(1 << 13) +#else +#define MINT6_14PL 0xFFFF +#endif + +#if (INT15PL >= INT6PL) || (INT15PL == 0) +#define MINT6_15PL ~(1 << 14) +#else +#define MINT6_15PL 0xFFFF +#endif + +#if (INT16PL >= INT6PL) || (INT16PL == 0) +#define MINT6_16PL ~(1 << 15) +#else +#define MINT6_16PL 0xFFFF +#endif + +#define MINT6 (MINT6_1PL & MINT6_2PL & MINT6_3PL & MINT6_4PL & \ + MINT6_5PL & MINT6_6PL & MINT6_7PL & MINT6_8PL & \ + MINT6_9PL & MINT6_10PL & MINT6_11PL & MINT6_12PL & \ + MINT6_13PL & MINT6_14PL & MINT6_15PL & MINT6_16PL) +// End Of MINT6. + +// Beginning of MINT7: +#if (INT1PL >= INT7PL) || (INT1PL == 0) +#define MINT7_1PL ~(1 << 0) +#else +#define MINT7_1PL 0xFFFF +#endif + +#if (INT2PL >= INT7PL) || (INT2PL == 0) +#define MINT7_2PL ~(1 << 1) +#else +#define MINT7_2PL 0xFFFF +#endif + +#if (INT3PL >= INT7PL) || (INT3PL == 0) +#define MINT7_3PL ~(1 << 2) +#else +#define MINT7_3PL 0xFFFF +#endif + +#if (INT4PL >= INT7PL) || (INT4PL == 0) +#define MINT7_4PL ~(1 << 3) +#else +#define MINT7_4PL 0xFFFF +#endif + +#if (INT5PL >= INT7PL) || (INT5PL == 0) +#define MINT7_5PL ~(1 << 4) +#else +#define MINT7_5PL 0xFFFF +#endif + +#if (INT6PL >= INT7PL) || (INT6PL == 0) +#define MINT7_6PL ~(1 << 5) +#else +#define MINT7_6PL 0xFFFF +#endif + +#if (INT7PL == 0) +#define MINT7_7PL ~(1 << 6) +#else +#define MINT7_7PL 0xFFFF +#endif + +#if (INT8PL >= INT7PL) || (INT8PL == 0) +#define MINT7_8PL ~(1 << 7) +#else +#define MINT7_8PL 0xFFFF +#endif + +#if (INT9PL >= INT7PL) || (INT9PL == 0) +#define MINT7_9PL ~(1 << 8) +#else +#define MINT7_9PL 0xFFFF +#endif + +#if (INT10PL >= INT7PL) || (INT10PL == 0) +#define MINT7_10PL ~(1 << 9) +#else +#define MINT7_10PL 0xFFFF +#endif + +#if (INT11PL >= INT7PL) || (INT11PL == 0) +#define MINT7_11PL ~(1 << 10) +#else +#define MINT7_11PL 0xFFFF +#endif + +#if (INT12PL >= INT7PL) || (INT12PL == 0) +#define MINT7_12PL ~(1 << 11) +#else +#define MINT7_12PL 0xFFFF +#endif + +#if (INT13PL >= INT7PL) || (INT13PL == 0) +#define MINT7_13PL ~(1 << 12) +#else +#define MINT7_13PL 0xFFFF +#endif + +#if (INT14PL >= INT7PL) || (INT14PL == 0) +#define MINT7_14PL ~(1 << 13) +#else +#define MINT7_14PL 0xFFFF +#endif + +#if (INT15PL >= INT7PL) || (INT15PL == 0) +#define MINT7_15PL ~(1 << 14) +#else +#define MINT7_15PL 0xFFFF +#endif + +#if (INT16PL >= INT7PL) || (INT16PL == 0) +#define MINT7_16PL ~(1 << 15) +#else +#define MINT7_16PL 0xFFFF +#endif + +#define MINT7 (MINT7_1PL & MINT7_2PL & MINT7_3PL & MINT7_4PL & \ + MINT7_5PL & MINT7_6PL & MINT7_7PL & MINT7_8PL & \ + MINT7_9PL & MINT7_10PL & MINT7_11PL & MINT7_12PL & \ + MINT7_13PL & MINT7_14PL & MINT7_15PL & MINT7_16PL) +// End Of MINT7. + +// Beginning of MINT8: +#if (INT1PL >= INT8PL) || (INT1PL == 0) +#define MINT8_1PL ~(1 << 0) +#else +#define MINT8_1PL 0xFFFF +#endif + +#if (INT2PL >= INT8PL) || (INT2PL == 0) +#define MINT8_2PL ~(1 << 1) +#else +#define MINT8_2PL 0xFFFF +#endif + +#if (INT3PL >= INT8PL) || (INT3PL == 0) +#define MINT8_3PL ~(1 << 2) +#else +#define MINT8_3PL 0xFFFF +#endif + +#if (INT4PL >= INT8PL) || (INT4PL == 0) +#define MINT8_4PL ~(1 << 3) +#else +#define MINT8_4PL 0xFFFF +#endif + +#if (INT5PL >= INT8PL) || (INT5PL == 0) +#define MINT8_5PL ~(1 << 4) +#else +#define MINT8_5PL 0xFFFF +#endif + +#if (INT6PL >= INT8PL) || (INT6PL == 0) +#define MINT8_6PL ~(1 << 5) +#else +#define MINT8_6PL 0xFFFF +#endif + +#if (INT7PL >= INT8PL) || (INT7PL == 0) +#define MINT8_7PL ~(1 << 6) +#else +#define MINT8_7PL 0xFFFF +#endif + +#if (INT8PL == 0) +#define MINT8_8PL ~(1 << 7) +#else +#define MINT8_8PL 0xFFFF +#endif + +#if (INT9PL >= INT8PL) || (INT9PL == 0) +#define MINT8_9PL ~(1 << 8) +#else +#define MINT8_9PL 0xFFFF +#endif + +#if (INT10PL >= INT8PL) || (INT10PL == 0) +#define MINT8_10PL ~(1 << 9) +#else +#define MINT8_10PL 0xFFFF +#endif + +#if (INT11PL >= INT8PL) || (INT11PL == 0) +#define MINT8_11PL ~(1 << 10) +#else +#define MINT8_11PL 0xFFFF +#endif + +#if (INT12PL >= INT8PL) || (INT12PL == 0) +#define MINT8_12PL ~(1 << 11) +#else +#define MINT8_12PL 0xFFFF +#endif + +#if (INT13PL >= INT8PL) || (INT13PL == 0) +#define MINT8_13PL ~(1 << 12) +#else +#define MINT8_13PL 0xFFFF +#endif + +#if (INT14PL >= INT8PL) || (INT14PL == 0) +#define MINT8_14PL ~(1 << 13) +#else +#define MINT8_14PL 0xFFFF +#endif + +#if (INT15PL >= INT8PL) || (INT15PL == 0) +#define MINT8_15PL ~(1 << 14) +#else +#define MINT8_15PL 0xFFFF +#endif + +#if (INT16PL >= INT8PL) || (INT16PL == 0) +#define MINT8_16PL ~(1 << 15) +#else +#define MINT8_16PL 0xFFFF +#endif + +#define MINT8 (MINT8_1PL & MINT8_2PL & MINT8_3PL & MINT8_4PL & \ + MINT8_5PL & MINT8_6PL & MINT8_7PL & MINT8_8PL & \ + MINT8_9PL & MINT8_10PL & MINT8_11PL & MINT8_12PL & \ + MINT8_13PL & MINT8_14PL & MINT8_15PL & MINT8_16PL) +// End Of MINT8. + +// Beginning of MINT9: +#if (INT1PL >= INT9PL) || (INT1PL == 0) +#define MINT9_1PL ~(1 << 0) +#else +#define MINT9_1PL 0xFFFF +#endif + +#if (INT2PL >= INT9PL) || (INT2PL == 0) +#define MINT9_2PL ~(1 << 1) +#else +#define MINT9_2PL 0xFFFF +#endif + +#if (INT3PL >= INT9PL) || (INT3PL == 0) +#define MINT9_3PL ~(1 << 2) +#else +#define MINT9_3PL 0xFFFF +#endif + +#if (INT4PL >= INT9PL) || (INT4PL == 0) +#define MINT9_4PL ~(1 << 3) +#else +#define MINT9_4PL 0xFFFF +#endif + +#if (INT5PL >= INT9PL) || (INT5PL == 0) +#define MINT9_5PL ~(1 << 4) +#else +#define MINT9_5PL 0xFFFF +#endif + +#if (INT6PL >= INT9PL) || (INT6PL == 0) +#define MINT9_6PL ~(1 << 5) +#else +#define MINT9_6PL 0xFFFF +#endif + +#if (INT7PL >= INT9PL) || (INT7PL == 0) +#define MINT9_7PL ~(1 << 6) +#else +#define MINT9_7PL 0xFFFF +#endif + +#if (INT8PL >= INT9PL) || (INT8PL == 0) +#define MINT9_8PL ~(1 << 7) +#else +#define MINT9_8PL 0xFFFF +#endif + +#if (INT9PL == 0) +#define MINT9_9PL ~(1 << 8) +#else +#define MINT9_9PL 0xFFFF +#endif + +#if (INT10PL >= INT9PL) || (INT10PL == 0) +#define MINT9_10PL ~(1 << 9) +#else +#define MINT9_10PL 0xFFFF +#endif + +#if (INT11PL >= INT9PL) || (INT11PL == 0) +#define MINT9_11PL ~(1 << 10) +#else +#define MINT9_11PL 0xFFFF +#endif + +#if (INT12PL >= INT9PL) || (INT12PL == 0) +#define MINT9_12PL ~(1 << 11) +#else +#define MINT9_12PL 0xFFFF +#endif + +#if (INT13PL >= INT9PL) || (INT13PL == 0) +#define MINT9_13PL ~(1 << 12) +#else +#define MINT9_13PL 0xFFFF +#endif + +#if (INT14PL >= INT9PL) || (INT14PL == 0) +#define MINT9_14PL ~(1 << 13) +#else +#define MINT9_14PL 0xFFFF +#endif + +#if (INT15PL >= INT9PL) || (INT15PL == 0) +#define MINT9_15PL ~(1 << 14) +#else +#define MINT9_15PL 0xFFFF +#endif + +#if (INT16PL >= INT9PL) || (INT16PL == 0) +#define MINT9_16PL ~(1 << 15) +#else +#define MINT9_16PL 0xFFFF +#endif + +#define MINT9 (MINT9_1PL & MINT9_2PL & MINT9_3PL & MINT9_4PL & \ + MINT9_5PL & MINT9_6PL & MINT9_7PL & MINT9_8PL & \ + MINT9_9PL & MINT9_10PL & MINT9_11PL & MINT9_12PL & \ + MINT9_13PL & MINT9_14PL & MINT9_15PL & MINT9_16PL) +// End Of MINT9. + +// Beginning of MINT10: +#if (INT1PL >= INT10PL) || (INT1PL == 0) +#define MINT10_1PL ~(1 << 0) +#else +#define MINT10_1PL 0xFFFF +#endif + +#if (INT2PL >= INT10PL) || (INT2PL == 0) +#define MINT10_2PL ~(1 << 1) +#else +#define MINT10_2PL 0xFFFF +#endif + +#if (INT3PL >= INT10PL) || (INT3PL == 0) +#define MINT10_3PL ~(1 << 2) +#else +#define MINT10_3PL 0xFFFF +#endif + +#if (INT4PL >= INT10PL) || (INT4PL == 0) +#define MINT10_4PL ~(1 << 3) +#else +#define MINT10_4PL 0xFFFF +#endif + +#if (INT5PL >= INT10PL) || (INT5PL == 0) +#define MINT10_5PL ~(1 << 4) +#else +#define MINT10_5PL 0xFFFF +#endif + +#if (INT6PL >= INT10PL) || (INT6PL == 0) +#define MINT10_6PL ~(1 << 5) +#else +#define MINT10_6PL 0xFFFF +#endif + +#if (INT7PL >= INT10PL) || (INT7PL == 0) +#define MINT10_7PL ~(1 << 6) +#else +#define MINT10_7PL 0xFFFF +#endif + +#if (INT8PL >= INT10PL) || (INT8PL == 0) +#define MINT10_8PL ~(1 << 7) +#else +#define MINT10_8PL 0xFFFF +#endif + +#if (INT9PL >= INT10PL) || (INT9PL == 0) +#define MINT10_9PL ~(1 << 8) +#else +#define MINT10_9PL 0xFFFF +#endif + +#if (INT10PL == 0) +#define MINT10_10PL ~(1 << 9) +#else +#define MINT10_10PL 0xFFFF +#endif + +#if (INT11PL >= INT10PL) || (INT11PL == 0) +#define MINT10_11PL ~(1 << 10) +#else +#define MINT10_11PL 0xFFFF +#endif + +#if (INT12PL >= INT10PL) || (INT12PL == 0) +#define MINT10_12PL ~(1 << 11) +#else +#define MINT10_12PL 0xFFFF +#endif + +#if (INT13PL >= INT10PL) || (INT13PL == 0) +#define MINT10_13PL ~(1 << 12) +#else +#define MINT10_13PL 0xFFFF +#endif + +#if (INT14PL >= INT10PL) || (INT14PL == 0) +#define MINT10_14PL ~(1 << 13) +#else +#define MINT10_14PL 0xFFFF +#endif + +#if (INT15PL >= INT10PL) || (INT15PL == 0) +#define MINT10_15PL ~(1 << 14) +#else +#define MINT10_15PL 0xFFFF +#endif + +#if (INT16PL >= INT10PL) || (INT16PL == 0) +#define MINT10_16PL ~(1 << 15) +#else +#define MINT10_16PL 0xFFFF +#endif + +#define MINT10 (MINT10_1PL & MINT10_2PL & MINT10_3PL & MINT10_4PL & \ + MINT10_5PL & MINT10_6PL & MINT10_7PL & MINT10_8PL & \ + MINT10_9PL & MINT10_10PL & MINT10_11PL & MINT10_12PL & \ + MINT10_13PL & MINT10_14PL & MINT10_15PL & MINT10_16PL) +// End Of MINT10. + +// Beginning of MINT11: +#if (INT1PL >= INT11PL) || (INT1PL == 0) +#define MINT11_1PL ~(1 << 0) +#else +#define MINT11_1PL 0xFFFF +#endif + +#if (INT2PL >= INT11PL) || (INT2PL == 0) +#define MINT11_2PL ~(1 << 1) +#else +#define MINT11_2PL 0xFFFF +#endif + +#if (INT3PL >= INT11PL) || (INT3PL == 0) +#define MINT11_3PL ~(1 << 2) +#else +#define MINT11_3PL 0xFFFF +#endif + +#if (INT4PL >= INT11PL) || (INT4PL == 0) +#define MINT11_4PL ~(1 << 3) +#else +#define MINT11_4PL 0xFFFF +#endif + +#if (INT5PL >= INT11PL) || (INT5PL == 0) +#define MINT11_5PL ~(1 << 4) +#else +#define MINT11_5PL 0xFFFF +#endif + +#if (INT6PL >= INT11PL) || (INT6PL == 0) +#define MINT11_6PL ~(1 << 5) +#else +#define MINT11_6PL 0xFFFF +#endif + +#if (INT7PL >= INT11PL) || (INT7PL == 0) +#define MINT11_7PL ~(1 << 6) +#else +#define MINT11_7PL 0xFFFF +#endif + +#if (INT8PL >= INT11PL) || (INT8PL == 0) +#define MINT11_8PL ~(1 << 7) +#else +#define MINT11_8PL 0xFFFF +#endif + +#if (INT9PL >= INT11PL) || (INT9PL == 0) +#define MINT11_9PL ~(1 << 8) +#else +#define MINT11_9PL 0xFFFF +#endif + +#if (INT10PL >= INT11PL) || (INT10PL == 0) +#define MINT11_10PL ~(1 << 9) +#else +#define MINT11_10PL 0xFFFF +#endif + +#if (INT11PL == 0) +#define MINT11_11PL ~(1 << 10) +#else +#define MINT11_11PL 0xFFFF +#endif + +#if (INT12PL >= INT11PL) || (INT12PL == 0) +#define MINT11_12PL ~(1 << 11) +#else +#define MINT11_12PL 0xFFFF +#endif + +#if (INT13PL >= INT11PL) || (INT13PL == 0) +#define MINT11_13PL ~(1 << 12) +#else +#define MINT11_13PL 0xFFFF +#endif + +#if (INT14PL >= INT11PL) || (INT14PL == 0) +#define MINT11_14PL ~(1 << 13) +#else +#define MINT11_14PL 0xFFFF +#endif + +#if (INT15PL >= INT11PL) || (INT15PL == 0) +#define MINT11_15PL ~(1 << 14) +#else +#define MINT11_15PL 0xFFFF +#endif + +#if (INT16PL >= INT11PL) || (INT16PL == 0) +#define MINT11_16PL ~(1 << 15) +#else +#define MINT11_16PL 0xFFFF +#endif + +#define MINT11 (MINT11_1PL & MINT11_2PL & MINT11_3PL & MINT11_4PL & \ + MINT11_5PL & MINT11_6PL & MINT11_7PL & MINT11_8PL & \ + MINT11_9PL & MINT11_10PL & MINT11_11PL & MINT11_12PL & \ + MINT11_13PL & MINT11_14PL & MINT11_15PL & MINT11_16PL) +// End Of MINT11. + +// Beginning of MINT12: +#if (INT1PL >= INT12PL) || (INT1PL == 0) +#define MINT12_1PL ~(1 << 0) +#else +#define MINT12_1PL 0xFFFF +#endif + +#if (INT2PL >= INT12PL) || (INT2PL == 0) +#define MINT12_2PL ~(1 << 1) +#else +#define MINT12_2PL 0xFFFF +#endif + +#if (INT3PL >= INT12PL) || (INT3PL == 0) +#define MINT12_3PL ~(1 << 2) +#else +#define MINT12_3PL 0xFFFF +#endif + +#if (INT4PL >= INT12PL) || (INT4PL == 0) +#define MINT12_4PL ~(1 << 3) +#else +#define MINT12_4PL 0xFFFF +#endif + +#if (INT5PL >= INT12PL) || (INT5PL == 0) +#define MINT12_5PL ~(1 << 4) +#else +#define MINT12_5PL 0xFFFF +#endif + +#if (INT6PL >= INT12PL) || (INT6PL == 0) +#define MINT12_6PL ~(1 << 5) +#else +#define MINT12_6PL 0xFFFF +#endif + +#if (INT7PL >= INT12PL) || (INT7PL == 0) +#define MINT12_7PL ~(1 << 6) +#else +#define MINT12_7PL 0xFFFF +#endif + +#if (INT8PL >= INT12PL) || (INT8PL == 0) +#define MINT12_8PL ~(1 << 7) +#else +#define MINT12_8PL 0xFFFF +#endif + +#if (INT9PL >= INT12PL) || (INT9PL == 0) +#define MINT12_9PL ~(1 << 8) +#else +#define MINT12_9PL 0xFFFF +#endif + +#if (INT10PL >= INT12PL) || (INT10PL == 0) +#define MINT12_10PL ~(1 << 9) +#else +#define MINT12_10PL 0xFFFF +#endif + +#if (INT11PL >= INT12PL) || (INT11PL == 0) +#define MINT12_11PL ~(1 << 10) +#else +#define MINT12_11PL 0xFFFF +#endif + +#if (INT12PL == 0) +#define MINT12_12PL ~(1 << 11) +#else +#define MINT12_12PL 0xFFFF +#endif + +#if (INT13PL >= INT12PL) || (INT13PL == 0) +#define MINT12_13PL ~(1 << 12) +#else +#define MINT12_13PL 0xFFFF +#endif + +#if (INT14PL >= INT12PL) || (INT14PL == 0) +#define MINT12_14PL ~(1 << 13) +#else +#define MINT12_14PL 0xFFFF +#endif + +#if (INT15PL >= INT12PL) || (INT15PL == 0) +#define MINT12_15PL ~(1 << 14) +#else +#define MINT12_15PL 0xFFFF +#endif + +#if (INT16PL >= INT12PL) || (INT16PL == 0) +#define MINT12_16PL ~(1 << 15) +#else +#define MINT12_16PL 0xFFFF +#endif + +#define MINT12 (MINT12_1PL & MINT12_2PL & MINT12_3PL & MINT12_4PL & \ + MINT12_5PL & MINT12_6PL & MINT12_7PL & MINT12_8PL & \ + MINT12_9PL & MINT12_10PL & MINT12_11PL & MINT12_12PL & \ + MINT12_13PL & MINT12_14PL & MINT12_15PL & MINT12_16PL) +// End Of MINT12. + +// Beginning of MINT13: +#if (INT1PL >= INT13PL) || (INT1PL == 0) +#define MINT13_1PL ~(1 << 0) +#else +#define MINT13_1PL 0xFFFF +#endif + +#if (INT2PL >= INT13PL) || (INT2PL == 0) +#define MINT13_2PL ~(1 << 1) +#else +#define MINT13_2PL 0xFFFF +#endif + +#if (INT3PL >= INT13PL) || (INT3PL == 0) +#define MINT13_3PL ~(1 << 2) +#else +#define MINT13_3PL 0xFFFF +#endif + +#if (INT4PL >= INT13PL) || (INT4PL == 0) +#define MINT13_4PL ~(1 << 3) +#else +#define MINT13_4PL 0xFFFF +#endif + +#if (INT5PL >= INT13PL) || (INT5PL == 0) +#define MINT13_5PL ~(1 << 4) +#else +#define MINT13_5PL 0xFFFF +#endif + +#if (INT6PL >= INT13PL) || (INT6PL == 0) +#define MINT13_6PL ~(1 << 5) +#else +#define MINT13_6PL 0xFFFF +#endif + +#if (INT7PL >= INT13PL) || (INT7PL == 0) +#define MINT13_7PL ~(1 << 6) +#else +#define MINT13_7PL 0xFFFF +#endif + +#if (INT8PL >= INT13PL) || (INT8PL == 0) +#define MINT13_8PL ~(1 << 7) +#else +#define MINT13_8PL 0xFFFF +#endif + +#if (INT9PL >= INT13PL) || (INT9PL == 0) +#define MINT13_9PL ~(1 << 8) +#else +#define MINT13_9PL 0xFFFF +#endif + +#if (INT10PL >= INT13PL) || (INT10PL == 0) +#define MINT13_10PL ~(1 << 9) +#else +#define MINT13_10PL 0xFFFF +#endif + +#if (INT11PL >= INT13PL) || (INT11PL == 0) +#define MINT13_11PL ~(1 << 10) +#else +#define MINT13_11PL 0xFFFF +#endif + +#if (INT12PL >= INT13PL) || (INT12PL == 0) +#define MINT13_12PL ~(1 << 11) +#else +#define MINT13_12PL 0xFFFF +#endif + +#if (INT13PL == 0) +#define MINT13_13PL ~(1 << 12) +#else +#define MINT13_13PL 0xFFFF +#endif + +#if (INT14PL >= INT13PL) || (INT14PL == 0) +#define MINT13_14PL ~(1 << 13) +#else +#define MINT13_14PL 0xFFFF +#endif + +#if (INT15PL >= INT13PL) || (INT15PL == 0) +#define MINT13_15PL ~(1 << 14) +#else +#define MINT13_15PL 0xFFFF +#endif + +#if (INT16PL >= INT13PL) || (INT16PL == 0) +#define MINT13_16PL ~(1 << 15) +#else +#define MINT13_16PL 0xFFFF +#endif + +#define MINT13 (MINT13_1PL & MINT13_2PL & MINT13_3PL & MINT13_4PL & \ + MINT13_5PL & MINT13_6PL & MINT13_7PL & MINT13_8PL & \ + MINT13_9PL & MINT13_10PL & MINT13_11PL & MINT13_12PL & \ + MINT13_13PL & MINT13_14PL & MINT13_15PL & MINT13_16PL) +// End Of MINT13. + +// Beginning of MINT14: +#if (INT1PL >= INT14PL) || (INT1PL == 0) +#define MINT14_1PL ~(1 << 0) +#else +#define MINT14_1PL 0xFFFF +#endif + +#if (INT2PL >= INT14PL) || (INT2PL == 0) +#define MINT14_2PL ~(1 << 1) +#else +#define MINT14_2PL 0xFFFF +#endif + +#if (INT3PL >= INT14PL) || (INT3PL == 0) +#define MINT14_3PL ~(1 << 2) +#else +#define MINT14_3PL 0xFFFF +#endif + +#if (INT4PL >= INT14PL) || (INT4PL == 0) +#define MINT14_4PL ~(1 << 3) +#else +#define MINT14_4PL 0xFFFF +#endif + +#if (INT5PL >= INT14PL) || (INT5PL == 0) +#define MINT14_5PL ~(1 << 4) +#else +#define MINT14_5PL 0xFFFF +#endif + +#if (INT6PL >= INT14PL) || (INT6PL == 0) +#define MINT14_6PL ~(1 << 5) +#else +#define MINT14_6PL 0xFFFF +#endif + +#if (INT7PL >= INT14PL) || (INT7PL == 0) +#define MINT14_7PL ~(1 << 6) +#else +#define MINT14_7PL 0xFFFF +#endif + +#if (INT8PL >= INT14PL) || (INT8PL == 0) +#define MINT14_8PL ~(1 << 7) +#else +#define MINT14_8PL 0xFFFF +#endif + +#if (INT9PL >= INT14PL) || (INT9PL == 0) +#define MINT14_9PL ~(1 << 8) +#else +#define MINT14_9PL 0xFFFF +#endif + +#if (INT10PL >= INT14PL) || (INT10PL == 0) +#define MINT14_10PL ~(1 << 9) +#else +#define MINT14_10PL 0xFFFF +#endif + +#if (INT11PL >= INT14PL) || (INT11PL == 0) +#define MINT14_11PL ~(1 << 10) +#else +#define MINT14_11PL 0xFFFF +#endif + +#if (INT12PL >= INT14PL) || (INT12PL == 0) +#define MINT14_12PL ~(1 << 11) +#else +#define MINT14_12PL 0xFFFF +#endif + +#if (INT13PL >= INT14PL) || (INT13PL == 0) +#define MINT14_13PL ~(1 << 12) +#else +#define MINT14_13PL 0xFFFF +#endif + +#define MINT14_14PL ~(1 << 13) + +#if (INT15PL >= INT14PL) || (INT15PL == 0) +#define MINT14_15PL ~(1 << 14) +#else +#define MINT14_15PL 0xFFFF +#endif + +#if (INT16PL >= INT14PL) || (INT16PL == 0) +#define MINT14_16PL ~(1 << 15) +#else +#define MINT14_16PL 0xFFFF +#endif + +#define MINT14 (MINT14_1PL & MINT14_2PL & MINT14_3PL & MINT14_4PL & \ + MINT14_5PL & MINT14_6PL & MINT14_7PL & MINT14_8PL & \ + MINT14_9PL & MINT14_10PL & MINT14_11PL & MINT14_12PL & \ + MINT14_13PL & MINT14_14PL & MINT14_15PL & MINT14_16PL) +// End Of MINT14. + +// Beginning of MINT15: +#if (INT1PL >= INT15PL) || (INT1PL == 0) +#define MINT15_1PL ~(1 << 0) +#else +#define MINT15_1PL 0xFFFF +#endif + +#if (INT2PL >= INT15PL) || (INT2PL == 0) +#define MINT15_2PL ~(1 << 1) +#else +#define MINT15_2PL 0xFFFF +#endif + +#if (INT3PL >= INT15PL) || (INT3PL == 0) +#define MINT15_3PL ~(1 << 2) +#else +#define MINT15_3PL 0xFFFF +#endif + +#if (INT4PL >= INT15PL) || (INT4PL == 0) +#define MINT15_4PL ~(1 << 3) +#else +#define MINT15_4PL 0xFFFF +#endif + +#if (INT5PL >= INT15PL) || (INT5PL == 0) +#define MINT15_5PL ~(1 << 4) +#else +#define MINT15_5PL 0xFFFF +#endif + +#if (INT6PL >= INT15PL) || (INT6PL == 0) +#define MINT15_6PL ~(1 << 5) +#else +#define MINT15_6PL 0xFFFF +#endif + +#if (INT7PL >= INT15PL) || (INT7PL == 0) +#define MINT15_7PL ~(1 << 6) +#else +#define MINT15_7PL 0xFFFF +#endif + +#if (INT8PL >= INT15PL) || (INT8PL == 0) +#define MINT15_8PL ~(1 << 7) +#else +#define MINT15_8PL 0xFFFF +#endif + +#if (INT9PL >= INT15PL) || (INT9PL == 0) +#define MINT15_9PL ~(1 << 8) +#else +#define MINT15_9PL 0xFFFF +#endif + +#if (INT10PL >= INT15PL) || (INT10PL == 0) +#define MINT15_10PL ~(1 << 9) +#else +#define MINT15_10PL 0xFFFF +#endif + +#if (INT11PL >= INT15PL) || (INT11PL == 0) +#define MINT15_11PL ~(1 << 10) +#else +#define MINT15_11PL 0xFFFF +#endif + +#if (INT12PL >= INT15PL) || (INT12PL == 0) +#define MINT15_12PL ~(1 << 11) +#else +#define MINT15_12PL 0xFFFF +#endif + +#if (INT13PL >= INT15PL) || (INT13PL == 0) +#define MINT15_13PL ~(1 << 12) +#else +#define MINT15_13PL 0xFFFF +#endif + +#if (INT14PL >= INT15PL) || (INT14PL == 0) +#define MINT15_14PL ~(1 << 13) +#else +#define MINT15_14PL 0xFFFF +#endif + +#define MINT15_15PL ~(1 << 14) + +#if (INT16PL >= INT15PL) || (INT16PL == 0) +#define MINT15_16PL ~(1 << 15) +#else +#define MINT15_16PL 0xFFFF +#endif + +#define MINT15 (MINT15_1PL & MINT15_2PL & MINT15_3PL & MINT15_4PL & \ + MINT15_5PL & MINT15_6PL & MINT15_7PL & MINT15_8PL & \ + MINT15_9PL & MINT15_10PL & MINT15_11PL & MINT15_12PL & \ + MINT15_13PL & MINT15_14PL & MINT15_15PL & MINT15_16PL) +// End Of MINT15. + +// Beginning of MINT16: +#if (INT1PL >= INT16PL) || (INT1PL == 0) +#define MINT16_1PL ~(1 << 0) +#else +#define MINT16_1PL 0xFFFF +#endif + +#if (INT2PL >= INT16PL) || (INT2PL == 0) +#define MINT16_2PL ~(1 << 1) +#else +#define MINT16_2PL 0xFFFF +#endif + +#if (INT3PL >= INT16PL) || (INT3PL == 0) +#define MINT16_3PL ~(1 << 2) +#else +#define MINT16_3PL 0xFFFF +#endif + +#if (INT4PL >= INT16PL) || (INT4PL == 0) +#define MINT16_4PL ~(1 << 3) +#else +#define MINT16_4PL 0xFFFF +#endif + +#if (INT5PL >= INT16PL) || (INT5PL == 0) +#define MINT16_5PL ~(1 << 4) +#else +#define MINT16_5PL 0xFFFF +#endif + +#if (INT6PL >= INT16PL) || (INT6PL == 0) +#define MINT16_6PL ~(1 << 5) +#else +#define MINT16_6PL 0xFFFF +#endif + +#if (INT7PL >= INT16PL) || (INT7PL == 0) +#define MINT16_7PL ~(1 << 6) +#else +#define MINT16_7PL 0xFFFF +#endif + +#if (INT8PL >= INT16PL) || (INT8PL == 0) +#define MINT16_8PL ~(1 << 7) +#else +#define MINT16_8PL 0xFFFF +#endif + +#if (INT9PL >= INT16PL) || (INT9PL == 0) +#define MINT16_9PL ~(1 << 8) +#else +#define MINT16_9PL 0xFFFF +#endif + +#if (INT10PL >= INT16PL) || (INT10PL == 0) +#define MINT16_10PL ~(1 << 9) +#else +#define MINT16_10PL 0xFFFF +#endif + +#if (INT11PL >= INT16PL) || (INT11PL == 0) +#define MINT16_11PL ~(1 << 10) +#else +#define MINT16_11PL 0xFFFF +#endif + +#if (INT12PL >= INT16PL) || (INT12PL == 0) +#define MINT16_12PL ~(1 << 11) +#else +#define MINT16_12PL 0xFFFF +#endif + +#if (INT13PL >= INT16PL) || (INT13PL == 0) +#define MINT16_13PL ~(1 << 12) +#else +#define MINT16_13PL 0xFFFF +#endif + +#if (INT14PL >= INT16PL) || (INT14PL == 0) +#define MINT16_14PL ~(1 << 13) +#else +#define MINT16_14PL 0xFFFF +#endif + +#if (INT15PL >= INT16PL) || (INT15PL == 0) +#define MINT16_15PL ~(1 << 14) +#else +#define MINT16_15PL 0xFFFF +#endif + +#define MINT16_16PL ~(1 << 15) + +#define MINT16 (MINT16_1PL & MINT16_2PL & MINT16_3PL & MINT16_4PL & \ + MINT16_5PL & MINT16_6PL & MINT16_7PL & MINT16_8PL & \ + MINT16_9PL & MINT16_10PL & MINT16_11PL & MINT16_12PL & \ + MINT16_13PL & MINT16_14PL & MINT16_15PL & MINT16_16PL) +// End Of MINT16. + +// +// Automatically generate PIEIER1 interrupt masks MG11 to MG116: +// + +// Beginning of MG11: +#if (G1_2PL >= G1_1PL) || (G1_2PL == 0) +#define MG1_1_12PL ~(1 << 1) +#else +#define MG1_1_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_1PL) || (G1_3PL == 0) +#define MG1_1_13PL ~(1 << 2) +#else +#define MG1_1_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_1PL) || (G1_4PL == 0) +#define MG1_1_14PL ~(1 << 3) +#else +#define MG1_1_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_1PL) || (G1_5PL == 0) +#define MG1_1_15PL ~(1 << 4) +#else +#define MG1_1_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_1PL) || (G1_6PL == 0) +#define MG1_1_16PL ~(1 << 5) +#else +#define MG1_1_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_1PL) || (G1_7PL == 0) +#define MG1_1_17PL ~(1 << 6) +#else +#define MG1_1_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_1PL) || (G1_8PL == 0) +#define MG1_1_18PL ~(1 << 7) +#else +#define MG1_1_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_1PL) || (G1_9PL == 0) +#define MG1_1_19PL ~(1 << 8) +#else +#define MG1_1_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_1PL) || (G1_10PL == 0) +#define MG1_1_110PL ~(1 << 9) +#else +#define MG1_1_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_1PL) || (G1_11PL == 0) +#define MG1_1_111PL ~(1 << 10) +#else +#define MG1_1_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_1PL) || (G1_12PL == 0) +#define MG1_1_112PL ~(1 << 11) +#else +#define MG1_1_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_1PL) || (G1_13PL == 0) +#define MG1_1_113PL ~(1 << 12) +#else +#define MG1_1_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_1PL) || (G1_14PL == 0) +#define MG1_1_114PL ~(1 << 13) +#else +#define MG1_1_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_1PL) || (G1_15PL == 0) +#define MG1_1_115PL ~(1 << 14) +#else +#define MG1_1_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_1PL) || (G1_16PL == 0) +#define MG1_1_116PL ~(1 << 15) +#else +#define MG1_1_116PL 0xFFFF +#endif + +#define MG1_1_11PL 0xFFFE +#define MG1_1 (MG1_1_11PL & MG1_1_12PL & MG1_1_13PL & MG1_1_14PL & \ + MG1_1_15PL & MG1_1_16PL & MG1_1_17PL & MG1_1_18PL & \ + MG1_1_19PL & MG1_1_110PL & MG1_1_111PL & MG1_1_112PL & \ + MG1_1_113PL & MG1_1_114PL & MG1_1_115PL & MG1_1_116PL) +// End of MG1_1: +// Beginning of MG12: +#if (G1_1PL >= G1_2PL) || (G1_1PL == 0) +#define MG1_2_11PL ~(1 << 0) +#else +#define MG1_2_11PL 0xFFFF +#endif + +#if (G1_3PL >= G1_2PL) || (G1_3PL == 0) +#define MG1_2_13PL ~(1 << 2) +#else +#define MG1_2_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_2PL) || (G1_4PL == 0) +#define MG1_2_14PL ~(1 << 3) +#else +#define MG1_2_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_2PL) || (G1_5PL == 0) +#define MG1_2_15PL ~(1 << 4) +#else +#define MG1_2_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_2PL) || (G1_6PL == 0) +#define MG1_2_16PL ~(1 << 5) +#else +#define MG1_2_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_2PL) || (G1_7PL == 0) +#define MG1_2_17PL ~(1 << 6) +#else +#define MG1_2_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_2PL) || (G1_8PL == 0) +#define MG1_2_18PL ~(1 << 7) +#else +#define MG1_2_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_2PL) || (G1_9PL == 0) +#define MG1_2_19PL ~(1 << 8) +#else +#define MG1_2_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_2PL) || (G1_10PL == 0) +#define MG1_2_110PL ~(1 << 9) +#else +#define MG1_2_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_2PL) || (G1_11PL == 0) +#define MG1_2_111PL ~(1 << 10) +#else +#define MG1_2_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_2PL) || (G1_12PL == 0) +#define MG1_2_112PL ~(1 << 11) +#else +#define MG1_2_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_2PL) || (G1_13PL == 0) +#define MG1_2_113PL ~(1 << 12) +#else +#define MG1_2_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_2PL) || (G1_14PL == 0) +#define MG1_2_114PL ~(1 << 13) +#else +#define MG1_2_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_2PL) || (G1_15PL == 0) +#define MG1_2_115PL ~(1 << 14) +#else +#define MG1_2_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_2PL) || (G1_16PL == 0) +#define MG1_2_116PL ~(1 << 15) +#else +#define MG1_2_116PL 0xFFFF +#endif + +#define MG1_2_12PL 0xFFFD +#define MG1_2 (MG1_2_11PL & MG1_2_12PL & MG1_2_13PL & MG1_2_14PL & \ + MG1_2_15PL & MG1_2_16PL & MG1_2_17PL & MG1_2_18PL & \ + MG1_2_19PL & MG1_2_110PL & MG1_2_111PL & MG1_2_112PL & \ + MG1_2_113PL & MG1_2_114PL & MG1_2_115PL & MG1_2_116PL) +// End of MG1_2: +// Beginning of MG13: +#if (G1_1PL >= G1_3PL) || (G1_1PL == 0) +#define MG1_3_11PL ~(1 << 0) +#else +#define MG1_3_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_3PL) || (G1_2PL == 0) +#define MG1_3_12PL ~(1 << 1) +#else +#define MG1_3_12PL 0xFFFF +#endif + +#if (G1_4PL >= G1_3PL) || (G1_4PL == 0) +#define MG1_3_14PL ~(1 << 3) +#else +#define MG1_3_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_3PL) || (G1_5PL == 0) +#define MG1_3_15PL ~(1 << 4) +#else +#define MG1_3_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_3PL) || (G1_6PL == 0) +#define MG1_3_16PL ~(1 << 5) +#else +#define MG1_3_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_3PL) || (G1_7PL == 0) +#define MG1_3_17PL ~(1 << 6) +#else +#define MG1_3_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_3PL) || (G1_8PL == 0) +#define MG1_3_18PL ~(1 << 7) +#else +#define MG1_3_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_3PL) || (G1_9PL == 0) +#define MG1_3_19PL ~(1 << 8) +#else +#define MG1_3_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_3PL) || (G1_10PL == 0) +#define MG1_3_110PL ~(1 << 9) +#else +#define MG1_3_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_3PL) || (G1_11PL == 0) +#define MG1_3_111PL ~(1 << 10) +#else +#define MG1_3_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_3PL) || (G1_12PL == 0) +#define MG1_3_112PL ~(1 << 11) +#else +#define MG1_3_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_3PL) || (G1_13PL == 0) +#define MG1_3_113PL ~(1 << 12) +#else +#define MG1_3_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_3PL) || (G1_14PL == 0) +#define MG1_3_114PL ~(1 << 13) +#else +#define MG1_3_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_3PL) || (G1_15PL == 0) +#define MG1_3_115PL ~(1 << 14) +#else +#define MG1_3_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_3PL) || (G1_16PL == 0) +#define MG1_3_116PL ~(1 << 15) +#else +#define MG1_3_116PL 0xFFFF +#endif + +#define MG1_3_13PL 0xFFFB +#define MG1_3 (MG1_3_11PL & MG1_3_12PL & MG1_3_13PL & MG1_3_14PL & \ + MG1_3_15PL & MG1_3_16PL & MG1_3_17PL & MG1_3_18PL & \ + MG1_3_19PL & MG1_3_110PL & MG1_3_111PL & MG1_3_112PL & \ + MG1_3_113PL & MG1_3_114PL & MG1_3_115PL & MG1_3_116PL) +// End of MG1_3: +// Beginning of MG14: +#if (G1_1PL >= G1_4PL) || (G1_1PL == 0) +#define MG1_4_11PL ~(1 << 0) +#else +#define MG1_4_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_4PL) || (G1_2PL == 0) +#define MG1_4_12PL ~(1 << 1) +#else +#define MG1_4_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_4PL) || (G1_3PL == 0) +#define MG1_4_13PL ~(1 << 2) +#else +#define MG1_4_13PL 0xFFFF +#endif + +#if (G1_5PL >= G1_4PL) || (G1_5PL == 0) +#define MG1_4_15PL ~(1 << 4) +#else +#define MG1_4_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_4PL) || (G1_6PL == 0) +#define MG1_4_16PL ~(1 << 5) +#else +#define MG1_4_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_4PL) || (G1_7PL == 0) +#define MG1_4_17PL ~(1 << 6) +#else +#define MG1_4_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_4PL) || (G1_8PL == 0) +#define MG1_4_18PL ~(1 << 7) +#else +#define MG1_4_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_4PL) || (G1_9PL == 0) +#define MG1_4_19PL ~(1 << 8) +#else +#define MG1_4_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_4PL) || (G1_10PL == 0) +#define MG1_4_110PL ~(1 << 9) +#else +#define MG1_4_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_4PL) || (G1_11PL == 0) +#define MG1_4_111PL ~(1 << 10) +#else +#define MG1_4_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_4PL) || (G1_12PL == 0) +#define MG1_4_112PL ~(1 << 11) +#else +#define MG1_4_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_4PL) || (G1_13PL == 0) +#define MG1_4_113PL ~(1 << 12) +#else +#define MG1_4_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_4PL) || (G1_14PL == 0) +#define MG1_4_114PL ~(1 << 13) +#else +#define MG1_4_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_4PL) || (G1_15PL == 0) +#define MG1_4_115PL ~(1 << 14) +#else +#define MG1_4_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_4PL) || (G1_16PL == 0) +#define MG1_4_116PL ~(1 << 15) +#else +#define MG1_4_116PL 0xFFFF +#endif + +#define MG1_4_14PL 0xFFF7 +#define MG1_4 (MG1_4_11PL & MG1_4_12PL & MG1_4_13PL & MG1_4_14PL & \ + MG1_4_15PL & MG1_4_16PL & MG1_4_17PL & MG1_4_18PL & \ + MG1_4_19PL & MG1_4_110PL & MG1_4_111PL & MG1_4_112PL & \ + MG1_4_113PL & MG1_4_114PL & MG1_4_115PL & MG1_4_116PL) +// End of MG1_4: +// Beginning of MG15: +#if (G1_1PL >= G1_5PL) || (G1_1PL == 0) +#define MG1_5_11PL ~(1 << 0) +#else +#define MG1_5_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_5PL) || (G1_2PL == 0) +#define MG1_5_12PL ~(1 << 1) +#else +#define MG1_5_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_5PL) || (G1_3PL == 0) +#define MG1_5_13PL ~(1 << 2) +#else +#define MG1_5_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_5PL) || (G1_4PL == 0) +#define MG1_5_14PL ~(1 << 3) +#else +#define MG1_5_14PL 0xFFFF +#endif + +#if (G1_6PL >= G1_5PL) || (G1_6PL == 0) +#define MG1_5_16PL ~(1 << 5) +#else +#define MG1_5_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_5PL) || (G1_7PL == 0) +#define MG1_5_17PL ~(1 << 6) +#else +#define MG1_5_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_5PL) || (G1_8PL == 0) +#define MG1_5_18PL ~(1 << 7) +#else +#define MG1_5_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_5PL) || (G1_9PL == 0) +#define MG1_5_19PL ~(1 << 8) +#else +#define MG1_5_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_5PL) || (G1_10PL == 0) +#define MG1_5_110PL ~(1 << 9) +#else +#define MG1_5_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_5PL) || (G1_11PL == 0) +#define MG1_5_111PL ~(1 << 10) +#else +#define MG1_5_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_5PL) || (G1_12PL == 0) +#define MG1_5_112PL ~(1 << 11) +#else +#define MG1_5_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_5PL) || (G1_13PL == 0) +#define MG1_5_113PL ~(1 << 12) +#else +#define MG1_5_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_5PL) || (G1_14PL == 0) +#define MG1_5_114PL ~(1 << 13) +#else +#define MG1_5_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_5PL) || (G1_15PL == 0) +#define MG1_5_115PL ~(1 << 14) +#else +#define MG1_5_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_5PL) || (G1_16PL == 0) +#define MG1_5_116PL ~(1 << 15) +#else +#define MG1_5_116PL 0xFFFF +#endif + +#define MG1_5_15PL 0xFFEF +#define MG1_5 (MG1_5_11PL & MG1_5_12PL & MG1_5_13PL & MG1_5_14PL & \ + MG1_5_15PL & MG1_5_16PL & MG1_5_17PL & MG1_5_18PL & \ + MG1_5_19PL & MG1_5_110PL & MG1_5_111PL & MG1_5_112PL & \ + MG1_5_113PL & MG1_5_114PL & MG1_5_115PL & MG1_5_116PL) +// End of MG1_5: +// Beginning of MG16: +#if (G1_1PL >= G1_6PL) || (G1_1PL == 0) +#define MG1_6_11PL ~(1 << 0) +#else +#define MG1_6_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_6PL) || (G1_2PL == 0) +#define MG1_6_12PL ~(1 << 1) +#else +#define MG1_6_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_6PL) || (G1_3PL == 0) +#define MG1_6_13PL ~(1 << 2) +#else +#define MG1_6_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_6PL) || (G1_4PL == 0) +#define MG1_6_14PL ~(1 << 3) +#else +#define MG1_6_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_6PL) || (G1_5PL == 0) +#define MG1_6_15PL ~(1 << 4) +#else +#define MG1_6_15PL 0xFFFF +#endif + +#if (G1_7PL >= G1_6PL) || (G1_7PL == 0) +#define MG1_6_17PL ~(1 << 6) +#else +#define MG1_6_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_6PL) || (G1_8PL == 0) +#define MG1_6_18PL ~(1 << 7) +#else +#define MG1_6_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_6PL) || (G1_9PL == 0) +#define MG1_6_19PL ~(1 << 8) +#else +#define MG1_6_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_6PL) || (G1_10PL == 0) +#define MG1_6_110PL ~(1 << 9) +#else +#define MG1_6_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_6PL) || (G1_11PL == 0) +#define MG1_6_111PL ~(1 << 10) +#else +#define MG1_6_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_6PL) || (G1_12PL == 0) +#define MG1_6_112PL ~(1 << 11) +#else +#define MG1_6_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_6PL) || (G1_13PL == 0) +#define MG1_6_113PL ~(1 << 12) +#else +#define MG1_6_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_6PL) || (G1_14PL == 0) +#define MG1_6_114PL ~(1 << 13) +#else +#define MG1_6_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_6PL) || (G1_15PL == 0) +#define MG1_6_115PL ~(1 << 14) +#else +#define MG1_6_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_6PL) || (G1_16PL == 0) +#define MG1_6_116PL ~(1 << 15) +#else +#define MG1_6_116PL 0xFFFF +#endif + +#define MG1_6_16PL 0xFFDF +#define MG1_6 (MG1_6_11PL & MG1_6_12PL & MG1_6_13PL & MG1_6_14PL & \ + MG1_6_15PL & MG1_6_16PL & MG1_6_17PL & MG1_6_18PL & \ + MG1_6_19PL & MG1_6_110PL & MG1_6_111PL & MG1_6_112PL & \ + MG1_6_113PL & MG1_6_114PL & MG1_6_115PL & MG1_6_116PL) +// End of MG1_6: +// Beginning of MG17: +#if (G1_1PL >= G1_7PL) || (G1_1PL == 0) +#define MG1_7_11PL ~(1 << 0) +#else +#define MG1_7_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_7PL) || (G1_2PL == 0) +#define MG1_7_12PL ~(1 << 1) +#else +#define MG1_7_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_7PL) || (G1_3PL == 0) +#define MG1_7_13PL ~(1 << 2) +#else +#define MG1_7_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_7PL) || (G1_4PL == 0) +#define MG1_7_14PL ~(1 << 3) +#else +#define MG1_7_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_7PL) || (G1_5PL == 0) +#define MG1_7_15PL ~(1 << 4) +#else +#define MG1_7_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_7PL) || (G1_6PL == 0) +#define MG1_7_16PL ~(1 << 5) +#else +#define MG1_7_16PL 0xFFFF +#endif + +#if (G1_8PL >= G1_7PL) || (G1_8PL == 0) +#define MG1_7_18PL ~(1 << 7) +#else +#define MG1_7_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_7PL) || (G1_9PL == 0) +#define MG1_7_19PL ~(1 << 8) +#else +#define MG1_7_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_7PL) || (G1_10PL == 0) +#define MG1_7_110PL ~(1 << 9) +#else +#define MG1_7_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_7PL) || (G1_11PL == 0) +#define MG1_7_111PL ~(1 << 10) +#else +#define MG1_7_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_7PL) || (G1_12PL == 0) +#define MG1_7_112PL ~(1 << 11) +#else +#define MG1_7_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_7PL) || (G1_13PL == 0) +#define MG1_7_113PL ~(1 << 12) +#else +#define MG1_7_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_7PL) || (G1_14PL == 0) +#define MG1_7_114PL ~(1 << 13) +#else +#define MG1_7_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_7PL) || (G1_15PL == 0) +#define MG1_7_115PL ~(1 << 14) +#else +#define MG1_7_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_7PL) || (G1_16PL == 0) +#define MG1_7_116PL ~(1 << 15) +#else +#define MG1_7_116PL 0xFFFF +#endif + +#define MG1_7_17PL 0xFFBF +#define MG1_7 (MG1_7_11PL & MG1_7_12PL & MG1_7_13PL & MG1_7_14PL & \ + MG1_7_15PL & MG1_7_16PL & MG1_7_17PL & MG1_7_18PL & \ + MG1_7_19PL & MG1_7_110PL & MG1_7_111PL & MG1_7_112PL & \ + MG1_7_113PL & MG1_7_114PL & MG1_7_115PL & MG1_7_116PL) +// End of MG1_7: +// Beginning of MG18: +#if (G1_1PL >= G1_8PL) || (G1_1PL == 0) +#define MG1_8_11PL ~(1 << 0) +#else +#define MG1_8_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_8PL) || (G1_2PL == 0) +#define MG1_8_12PL ~(1 << 1) +#else +#define MG1_8_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_8PL) || (G1_3PL == 0) +#define MG1_8_13PL ~(1 << 2) +#else +#define MG1_8_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_8PL) || (G1_4PL == 0) +#define MG1_8_14PL ~(1 << 3) +#else +#define MG1_8_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_8PL) || (G1_5PL == 0) +#define MG1_8_15PL ~(1 << 4) +#else +#define MG1_8_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_8PL) || (G1_6PL == 0) +#define MG1_8_16PL ~(1 << 5) +#else +#define MG1_8_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_8PL) || (G1_7PL == 0) +#define MG1_8_17PL ~(1 << 6) +#else +#define MG1_8_17PL 0xFFFF +#endif + +#if (G1_9PL >= G1_8PL) || (G1_9PL == 0) +#define MG1_8_19PL ~(1 << 8) +#else +#define MG1_8_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_8PL) || (G1_10PL == 0) +#define MG1_8_110PL ~(1 << 9) +#else +#define MG1_8_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_8PL) || (G1_11PL == 0) +#define MG1_8_111PL ~(1 << 10) +#else +#define MG1_8_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_8PL) || (G1_12PL == 0) +#define MG1_8_112PL ~(1 << 11) +#else +#define MG1_8_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_8PL) || (G1_13PL == 0) +#define MG1_8_113PL ~(1 << 12) +#else +#define MG1_8_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_8PL) || (G1_14PL == 0) +#define MG1_8_114PL ~(1 << 13) +#else +#define MG1_8_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_8PL) || (G1_15PL == 0) +#define MG1_8_115PL ~(1 << 14) +#else +#define MG1_8_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_8PL) || (G1_16PL == 0) +#define MG1_8_116PL ~(1 << 15) +#else +#define MG1_8_116PL 0xFFFF +#endif + +#define MG1_8_18PL 0xFF7F +#define MG1_8 (MG1_8_11PL & MG1_8_12PL & MG1_8_13PL & MG1_8_14PL & \ + MG1_8_15PL & MG1_8_16PL & MG1_8_17PL & MG1_8_18PL & \ + MG1_8_19PL & MG1_8_110PL & MG1_8_111PL & MG1_8_112PL & \ + MG1_8_113PL & MG1_8_114PL & MG1_8_115PL & MG1_8_116PL) +// End of MG1_8: +// Beginning of MG19: +#if (G1_1PL >= G1_9PL) || (G1_1PL == 0) +#define MG1_9_11PL ~(1 << 0) +#else +#define MG1_9_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_9PL) || (G1_2PL == 0) +#define MG1_9_12PL ~(1 << 1) +#else +#define MG1_9_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_9PL) || (G1_3PL == 0) +#define MG1_9_13PL ~(1 << 2) +#else +#define MG1_9_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_9PL) || (G1_4PL == 0) +#define MG1_9_14PL ~(1 << 3) +#else +#define MG1_9_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_9PL) || (G1_5PL == 0) +#define MG1_9_15PL ~(1 << 4) +#else +#define MG1_9_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_9PL) || (G1_6PL == 0) +#define MG1_9_16PL ~(1 << 5) +#else +#define MG1_9_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_9PL) || (G1_7PL == 0) +#define MG1_9_17PL ~(1 << 6) +#else +#define MG1_9_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_9PL) || (G1_8PL == 0) +#define MG1_9_18PL ~(1 << 7) +#else +#define MG1_9_18PL 0xFFFF +#endif + +#if (G1_10PL >= G1_9PL) || (G1_10PL == 0) +#define MG1_9_110PL ~(1 << 9) +#else +#define MG1_9_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_9PL) || (G1_11PL == 0) +#define MG1_9_111PL ~(1 << 10) +#else +#define MG1_9_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_9PL) || (G1_12PL == 0) +#define MG1_9_112PL ~(1 << 11) +#else +#define MG1_9_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_9PL) || (G1_13PL == 0) +#define MG1_9_113PL ~(1 << 12) +#else +#define MG1_9_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_9PL) || (G1_14PL == 0) +#define MG1_9_114PL ~(1 << 13) +#else +#define MG1_9_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_9PL) || (G1_15PL == 0) +#define MG1_9_115PL ~(1 << 14) +#else +#define MG1_9_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_9PL) || (G1_16PL == 0) +#define MG1_9_116PL ~(1 << 15) +#else +#define MG1_9_116PL 0xFFFF +#endif + +#define MG1_9_19PL 0xFEFF +#define MG1_9 (MG1_9_11PL & MG1_9_12PL & MG1_9_13PL & MG1_9_14PL & \ + MG1_9_15PL & MG1_9_16PL & MG1_9_17PL & MG1_9_18PL & \ + MG1_9_19PL & MG1_9_110PL & MG1_9_111PL & MG1_9_112PL & \ + MG1_9_113PL & MG1_9_114PL & MG1_9_115PL & MG1_9_116PL) +// End of MG1_9: +// Beginning of MG110: +#if (G1_1PL >= G1_10PL) || (G1_1PL == 0) +#define MG1_10_11PL ~(1 << 0) +#else +#define MG1_10_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_10PL) || (G1_2PL == 0) +#define MG1_10_12PL ~(1 << 1) +#else +#define MG1_10_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_10PL) || (G1_3PL == 0) +#define MG1_10_13PL ~(1 << 2) +#else +#define MG1_10_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_10PL) || (G1_4PL == 0) +#define MG1_10_14PL ~(1 << 3) +#else +#define MG1_10_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_10PL) || (G1_5PL == 0) +#define MG1_10_15PL ~(1 << 4) +#else +#define MG1_10_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_10PL) || (G1_6PL == 0) +#define MG1_10_16PL ~(1 << 5) +#else +#define MG1_10_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_10PL) || (G1_7PL == 0) +#define MG1_10_17PL ~(1 << 6) +#else +#define MG1_10_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_10PL) || (G1_8PL == 0) +#define MG1_10_18PL ~(1 << 7) +#else +#define MG1_10_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_10PL) || (G1_9PL == 0) +#define MG1_10_19PL ~(1 << 8) +#else +#define MG1_10_19PL 0xFFFF +#endif + +#if (G1_11PL >= G1_10PL) || (G1_11PL == 0) +#define MG1_10_111PL ~(1 << 10) +#else +#define MG1_10_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_10PL) || (G1_12PL == 0) +#define MG1_10_112PL ~(1 << 11) +#else +#define MG1_10_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_10PL) || (G1_13PL == 0) +#define MG1_10_113PL ~(1 << 12) +#else +#define MG1_10_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_10PL) || (G1_14PL == 0) +#define MG1_10_114PL ~(1 << 13) +#else +#define MG1_10_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_10PL) || (G1_15PL == 0) +#define MG1_10_115PL ~(1 << 14) +#else +#define MG1_10_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_10PL) || (G1_16PL == 0) +#define MG1_10_116PL ~(1 << 15) +#else +#define MG1_10_116PL 0xFFFF +#endif + +#define MG1_10_110PL 0xFDFF +#define MG1_10 (MG1_10_11PL & MG1_10_12PL & MG1_10_13PL & MG1_10_14PL & \ + MG1_10_15PL & MG1_10_16PL & MG1_10_17PL & MG1_10_18PL & \ + MG1_10_19PL & MG1_10_110PL & MG1_10_111PL & MG1_10_112PL & \ + MG1_10_113PL & MG1_10_114PL & MG1_10_115PL & MG1_10_116PL) +// End of MG1_10: +// Beginning of MG111: +#if (G1_1PL >= G1_11PL) || (G1_1PL == 0) +#define MG1_11_11PL ~(1 << 0) +#else +#define MG1_11_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_11PL) || (G1_2PL == 0) +#define MG1_11_12PL ~(1 << 1) +#else +#define MG1_11_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_11PL) || (G1_3PL == 0) +#define MG1_11_13PL ~(1 << 2) +#else +#define MG1_11_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_11PL) || (G1_4PL == 0) +#define MG1_11_14PL ~(1 << 3) +#else +#define MG1_11_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_11PL) || (G1_5PL == 0) +#define MG1_11_15PL ~(1 << 4) +#else +#define MG1_11_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_11PL) || (G1_6PL == 0) +#define MG1_11_16PL ~(1 << 5) +#else +#define MG1_11_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_11PL) || (G1_7PL == 0) +#define MG1_11_17PL ~(1 << 6) +#else +#define MG1_11_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_11PL) || (G1_8PL == 0) +#define MG1_11_18PL ~(1 << 7) +#else +#define MG1_11_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_11PL) || (G1_9PL == 0) +#define MG1_11_19PL ~(1 << 8) +#else +#define MG1_11_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_11PL) || (G1_10PL == 0) +#define MG1_11_110PL ~(1 << 9) +#else +#define MG1_11_110PL 0xFFFF +#endif + +#if (G1_12PL >= G1_11PL) || (G1_12PL == 0) +#define MG1_11_112PL ~(1 << 11) +#else +#define MG1_11_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_11PL) || (G1_13PL == 0) +#define MG1_11_113PL ~(1 << 12) +#else +#define MG1_11_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_11PL) || (G1_14PL == 0) +#define MG1_11_114PL ~(1 << 13) +#else +#define MG1_11_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_11PL) || (G1_15PL == 0) +#define MG1_11_115PL ~(1 << 14) +#else +#define MG1_11_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_11PL) || (G1_16PL == 0) +#define MG1_11_116PL ~(1 << 15) +#else +#define MG1_11_116PL 0xFFFF +#endif + +#define MG1_11_111PL 0xFBFF +#define MG1_11 (MG1_11_11PL & MG1_11_12PL & MG1_11_13PL & MG1_11_14PL & \ + MG1_11_15PL & MG1_11_16PL & MG1_11_17PL & MG1_11_18PL & \ + MG1_11_19PL & MG1_11_110PL & MG1_11_111PL & MG1_11_112PL & \ + MG1_11_113PL & MG1_11_114PL & MG1_11_115PL & MG1_11_116PL) +// End of MG1_11: +// Beginning of MG112: +#if (G1_1PL >= G1_12PL) || (G1_1PL == 0) +#define MG1_12_11PL ~(1 << 0) +#else +#define MG1_12_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_12PL) || (G1_2PL == 0) +#define MG1_12_12PL ~(1 << 1) +#else +#define MG1_12_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_12PL) || (G1_3PL == 0) +#define MG1_12_13PL ~(1 << 2) +#else +#define MG1_12_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_12PL) || (G1_4PL == 0) +#define MG1_12_14PL ~(1 << 3) +#else +#define MG1_12_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_12PL) || (G1_5PL == 0) +#define MG1_12_15PL ~(1 << 4) +#else +#define MG1_12_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_12PL) || (G1_6PL == 0) +#define MG1_12_16PL ~(1 << 5) +#else +#define MG1_12_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_12PL) || (G1_7PL == 0) +#define MG1_12_17PL ~(1 << 6) +#else +#define MG1_12_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_12PL) || (G1_8PL == 0) +#define MG1_12_18PL ~(1 << 7) +#else +#define MG1_12_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_12PL) || (G1_9PL == 0) +#define MG1_12_19PL ~(1 << 8) +#else +#define MG1_12_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_12PL) || (G1_10PL == 0) +#define MG1_12_110PL ~(1 << 9) +#else +#define MG1_12_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_12PL) || (G1_11PL == 0) +#define MG1_12_111PL ~(1 << 10) +#else +#define MG1_12_111PL 0xFFFF +#endif + +#if (G1_13PL >= G1_12PL) || (G1_13PL == 0) +#define MG1_12_113PL ~(1 << 12) +#else +#define MG1_12_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_12PL) || (G1_14PL == 0) +#define MG1_12_114PL ~(1 << 13) +#else +#define MG1_12_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_12PL) || (G1_15PL == 0) +#define MG1_12_115PL ~(1 << 14) +#else +#define MG1_12_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_12PL) || (G1_16PL == 0) +#define MG1_12_116PL ~(1 << 15) +#else +#define MG1_12_116PL 0xFFFF +#endif + +#define MG1_12_112PL 0xF7FF +#define MG1_12 (MG1_12_11PL & MG1_12_12PL & MG1_12_13PL & MG1_12_14PL & \ + MG1_12_15PL & MG1_12_16PL & MG1_12_17PL & MG1_12_18PL & \ + MG1_12_19PL & MG1_12_110PL & MG1_12_111PL & MG1_12_112PL & \ + MG1_12_113PL & MG1_12_114PL & MG1_12_115PL & MG1_12_116PL) +// End of MG1_12: +// Beginning of MG113: +#if (G1_1PL >= G1_13PL) || (G1_1PL == 0) +#define MG1_13_11PL ~(1 << 0) +#else +#define MG1_13_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_13PL) || (G1_2PL == 0) +#define MG1_13_12PL ~(1 << 1) +#else +#define MG1_13_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_13PL) || (G1_3PL == 0) +#define MG1_13_13PL ~(1 << 2) +#else +#define MG1_13_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_13PL) || (G1_4PL == 0) +#define MG1_13_14PL ~(1 << 3) +#else +#define MG1_13_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_13PL) || (G1_5PL == 0) +#define MG1_13_15PL ~(1 << 4) +#else +#define MG1_13_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_13PL) || (G1_6PL == 0) +#define MG1_13_16PL ~(1 << 5) +#else +#define MG1_13_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_13PL) || (G1_7PL == 0) +#define MG1_13_17PL ~(1 << 6) +#else +#define MG1_13_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_13PL) || (G1_8PL == 0) +#define MG1_13_18PL ~(1 << 7) +#else +#define MG1_13_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_13PL) || (G1_9PL == 0) +#define MG1_13_19PL ~(1 << 8) +#else +#define MG1_13_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_13PL) || (G1_10PL == 0) +#define MG1_13_110PL ~(1 << 9) +#else +#define MG1_13_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_13PL) || (G1_11PL == 0) +#define MG1_13_111PL ~(1 << 10) +#else +#define MG1_13_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_13PL) || (G1_12PL == 0) +#define MG1_13_112PL ~(1 << 11) +#else +#define MG1_13_112PL 0xFFFF +#endif + +#if (G1_14PL >= G1_13PL) || (G1_14PL == 0) +#define MG1_13_114PL ~(1 << 13) +#else +#define MG1_13_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_13PL) || (G1_15PL == 0) +#define MG1_13_115PL ~(1 << 14) +#else +#define MG1_13_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_13PL) || (G1_16PL == 0) +#define MG1_13_116PL ~(1 << 15) +#else +#define MG1_13_116PL 0xFFFF +#endif + +#define MG1_13_113PL 0xEFFF +#define MG1_13 (MG1_13_11PL & MG1_13_12PL & MG1_13_13PL & MG1_13_14PL & \ + MG1_13_15PL & MG1_13_16PL & MG1_13_17PL & MG1_13_18PL & \ + MG1_13_19PL & MG1_13_110PL & MG1_13_111PL & MG1_13_112PL & \ + MG1_13_113PL & MG1_13_114PL & MG1_13_115PL & MG1_13_116PL) +// End of MG1_13: +// Beginning of MG114: +#if (G1_1PL >= G1_14PL) || (G1_1PL == 0) +#define MG1_14_11PL ~(1 << 0) +#else +#define MG1_14_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_14PL) || (G1_2PL == 0) +#define MG1_14_12PL ~(1 << 1) +#else +#define MG1_14_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_14PL) || (G1_3PL == 0) +#define MG1_14_13PL ~(1 << 2) +#else +#define MG1_14_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_14PL) || (G1_4PL == 0) +#define MG1_14_14PL ~(1 << 3) +#else +#define MG1_14_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_14PL) || (G1_5PL == 0) +#define MG1_14_15PL ~(1 << 4) +#else +#define MG1_14_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_14PL) || (G1_6PL == 0) +#define MG1_14_16PL ~(1 << 5) +#else +#define MG1_14_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_14PL) || (G1_7PL == 0) +#define MG1_14_17PL ~(1 << 6) +#else +#define MG1_14_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_14PL) || (G1_8PL == 0) +#define MG1_14_18PL ~(1 << 7) +#else +#define MG1_14_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_14PL) || (G1_9PL == 0) +#define MG1_14_19PL ~(1 << 8) +#else +#define MG1_14_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_14PL) || (G1_10PL == 0) +#define MG1_14_110PL ~(1 << 9) +#else +#define MG1_14_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_14PL) || (G1_11PL == 0) +#define MG1_14_111PL ~(1 << 10) +#else +#define MG1_14_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_14PL) || (G1_12PL == 0) +#define MG1_14_112PL ~(1 << 11) +#else +#define MG1_14_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_14PL) || (G1_13PL == 0) +#define MG1_14_113PL ~(1 << 12) +#else +#define MG1_14_113PL 0xFFFF +#endif + +#if (G1_15PL >= G1_14PL) || (G1_15PL == 0) +#define MG1_14_115PL ~(1 << 14) +#else +#define MG1_14_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_14PL) || (G1_16PL == 0) +#define MG1_14_116PL ~(1 << 15) +#else +#define MG1_14_116PL 0xFFFF +#endif + +#define MG1_14_114PL 0xDFFF +#define MG1_14 (MG1_14_11PL & MG1_14_12PL & MG1_14_13PL & MG1_14_14PL & \ + MG1_14_15PL & MG1_14_16PL & MG1_14_17PL & MG1_14_18PL & \ + MG1_14_19PL & MG1_14_110PL & MG1_14_111PL & MG1_14_112PL & \ + MG1_14_113PL & MG1_14_114PL & MG1_14_115PL & MG1_14_116PL) +// End of MG1_14: +// Beginning of MG115: +#if (G1_1PL >= G1_15PL) || (G1_1PL == 0) +#define MG1_15_11PL ~(1 << 0) +#else +#define MG1_15_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_15PL) || (G1_2PL == 0) +#define MG1_15_12PL ~(1 << 1) +#else +#define MG1_15_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_15PL) || (G1_3PL == 0) +#define MG1_15_13PL ~(1 << 2) +#else +#define MG1_15_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_15PL) || (G1_4PL == 0) +#define MG1_15_14PL ~(1 << 3) +#else +#define MG1_15_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_15PL) || (G1_5PL == 0) +#define MG1_15_15PL ~(1 << 4) +#else +#define MG1_15_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_15PL) || (G1_6PL == 0) +#define MG1_15_16PL ~(1 << 5) +#else +#define MG1_15_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_15PL) || (G1_7PL == 0) +#define MG1_15_17PL ~(1 << 6) +#else +#define MG1_15_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_15PL) || (G1_8PL == 0) +#define MG1_15_18PL ~(1 << 7) +#else +#define MG1_15_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_15PL) || (G1_9PL == 0) +#define MG1_15_19PL ~(1 << 8) +#else +#define MG1_15_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_15PL) || (G1_10PL == 0) +#define MG1_15_110PL ~(1 << 9) +#else +#define MG1_15_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_15PL) || (G1_11PL == 0) +#define MG1_15_111PL ~(1 << 10) +#else +#define MG1_15_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_15PL) || (G1_12PL == 0) +#define MG1_15_112PL ~(1 << 11) +#else +#define MG1_15_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_15PL) || (G1_13PL == 0) +#define MG1_15_113PL ~(1 << 12) +#else +#define MG1_15_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_15PL) || (G1_14PL == 0) +#define MG1_15_114PL ~(1 << 13) +#else +#define MG1_15_114PL 0xFFFF +#endif + +#if (G1_16PL >= G1_15PL) || (G1_16PL == 0) +#define MG1_15_116PL ~(1 << 15) +#else +#define MG1_15_116PL 0xFFFF +#endif + +#define MG1_15_115PL 0xBFFF +#define MG1_15 (MG1_15_11PL & MG1_15_12PL & MG1_15_13PL & MG1_15_14PL & \ + MG1_15_15PL & MG1_15_16PL & MG1_15_17PL & MG1_15_18PL & \ + MG1_15_19PL & MG1_15_110PL & MG1_15_111PL & MG1_15_112PL & \ + MG1_15_113PL & MG1_15_114PL & MG1_15_115PL & MG1_15_116PL) +// End of MG1_15: +// Beginning of MG116: +#if (G1_1PL >= G1_16PL) || (G1_1PL == 0) +#define MG1_16_11PL ~(1 << 0) +#else +#define MG1_16_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_16PL) || (G1_2PL == 0) +#define MG1_16_12PL ~(1 << 1) +#else +#define MG1_16_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_16PL) || (G1_3PL == 0) +#define MG1_16_13PL ~(1 << 2) +#else +#define MG1_16_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_16PL) || (G1_4PL == 0) +#define MG1_16_14PL ~(1 << 3) +#else +#define MG1_16_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_16PL) || (G1_5PL == 0) +#define MG1_16_15PL ~(1 << 4) +#else +#define MG1_16_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_16PL) || (G1_6PL == 0) +#define MG1_16_16PL ~(1 << 5) +#else +#define MG1_16_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_16PL) || (G1_7PL == 0) +#define MG1_16_17PL ~(1 << 6) +#else +#define MG1_16_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_16PL) || (G1_8PL == 0) +#define MG1_16_18PL ~(1 << 7) +#else +#define MG1_16_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_16PL) || (G1_9PL == 0) +#define MG1_16_19PL ~(1 << 8) +#else +#define MG1_16_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_16PL) || (G1_10PL == 0) +#define MG1_16_110PL ~(1 << 9) +#else +#define MG1_16_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_16PL) || (G1_11PL == 0) +#define MG1_16_111PL ~(1 << 10) +#else +#define MG1_16_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_16PL) || (G1_12PL == 0) +#define MG1_16_112PL ~(1 << 11) +#else +#define MG1_16_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_16PL) || (G1_13PL == 0) +#define MG1_16_113PL ~(1 << 12) +#else +#define MG1_16_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_16PL) || (G1_14PL == 0) +#define MG1_16_114PL ~(1 << 13) +#else +#define MG1_16_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_16PL) || (G1_15PL == 0) +#define MG1_16_115PL ~(1 << 14) +#else +#define MG1_16_115PL 0xFFFF +#endif + +#define MG1_16_116PL 0x7FFF +#define MG1_16 (MG1_16_11PL & MG1_16_12PL & MG1_16_13PL & MG1_16_14PL & \ + MG1_16_15PL & MG1_16_16PL & MG1_16_17PL & MG1_16_18PL & \ + MG1_16_19PL & MG1_16_110PL & MG1_16_111PL & MG1_16_112PL & \ + MG1_16_113PL & MG1_16_114PL & MG1_16_115PL & MG1_16_116PL) +// End of MG1_16: + + +// +// Automatically generate PIEIER2 interrupt masks MG21 to MG216: +// + +// Beginning of MG21: +#if (G2_2PL >= G2_1PL) || (G2_2PL == 0) +#define MG2_1_12PL ~(1 << 1) +#else +#define MG2_1_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_1PL) || (G2_3PL == 0) +#define MG2_1_13PL ~(1 << 2) +#else +#define MG2_1_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_1PL) || (G2_4PL == 0) +#define MG2_1_14PL ~(1 << 3) +#else +#define MG2_1_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_1PL) || (G2_5PL == 0) +#define MG2_1_15PL ~(1 << 4) +#else +#define MG2_1_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_1PL) || (G2_6PL == 0) +#define MG2_1_16PL ~(1 << 5) +#else +#define MG2_1_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_1PL) || (G2_7PL == 0) +#define MG2_1_17PL ~(1 << 6) +#else +#define MG2_1_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_1PL) || (G2_8PL == 0) +#define MG2_1_18PL ~(1 << 7) +#else +#define MG2_1_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_1PL) || (G2_9PL == 0) +#define MG2_1_19PL ~(1 << 8) +#else +#define MG2_1_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_1PL) || (G2_10PL == 0) +#define MG2_1_110PL ~(1 << 9) +#else +#define MG2_1_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_1PL) || (G2_11PL == 0) +#define MG2_1_111PL ~(1 << 10) +#else +#define MG2_1_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_1PL) || (G2_12PL == 0) +#define MG2_1_112PL ~(1 << 11) +#else +#define MG2_1_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_1PL) || (G2_13PL == 0) +#define MG2_1_113PL ~(1 << 12) +#else +#define MG2_1_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_1PL) || (G2_14PL == 0) +#define MG2_1_114PL ~(1 << 13) +#else +#define MG2_1_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_1PL) || (G2_15PL == 0) +#define MG2_1_115PL ~(1 << 14) +#else +#define MG2_1_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_1PL) || (G2_16PL == 0) +#define MG2_1_116PL ~(1 << 15) +#else +#define MG2_1_116PL 0xFFFF +#endif + +#define MG2_1_11PL 0xFFFE +#define MG2_1 (MG2_1_11PL & MG2_1_12PL & MG2_1_13PL & MG2_1_14PL & \ + MG2_1_15PL & MG2_1_16PL & MG2_1_17PL & MG2_1_18PL & \ + MG2_1_19PL & MG2_1_110PL & MG2_1_111PL & MG2_1_112PL & \ + MG2_1_113PL & MG2_1_114PL & MG2_1_115PL & MG2_1_116PL) +// End of MG2_1: +// Beginning of MG22: +#if (G2_1PL >= G2_2PL) || (G2_1PL == 0) +#define MG2_2_11PL ~(1 << 0) +#else +#define MG2_2_11PL 0xFFFF +#endif + +#if (G2_3PL >= G2_2PL) || (G2_3PL == 0) +#define MG2_2_13PL ~(1 << 2) +#else +#define MG2_2_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_2PL) || (G2_4PL == 0) +#define MG2_2_14PL ~(1 << 3) +#else +#define MG2_2_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_2PL) || (G2_5PL == 0) +#define MG2_2_15PL ~(1 << 4) +#else +#define MG2_2_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_2PL) || (G2_6PL == 0) +#define MG2_2_16PL ~(1 << 5) +#else +#define MG2_2_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_2PL) || (G2_7PL == 0) +#define MG2_2_17PL ~(1 << 6) +#else +#define MG2_2_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_2PL) || (G2_8PL == 0) +#define MG2_2_18PL ~(1 << 7) +#else +#define MG2_2_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_2PL) || (G2_9PL == 0) +#define MG2_2_19PL ~(1 << 8) +#else +#define MG2_2_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_2PL) || (G2_10PL == 0) +#define MG2_2_110PL ~(1 << 9) +#else +#define MG2_2_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_2PL) || (G2_11PL == 0) +#define MG2_2_111PL ~(1 << 10) +#else +#define MG2_2_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_2PL) || (G2_12PL == 0) +#define MG2_2_112PL ~(1 << 11) +#else +#define MG2_2_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_2PL) || (G2_13PL == 0) +#define MG2_2_113PL ~(1 << 12) +#else +#define MG2_2_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_2PL) || (G2_14PL == 0) +#define MG2_2_114PL ~(1 << 13) +#else +#define MG2_2_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_2PL) || (G2_15PL == 0) +#define MG2_2_115PL ~(1 << 14) +#else +#define MG2_2_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_2PL) || (G2_16PL == 0) +#define MG2_2_116PL ~(1 << 15) +#else +#define MG2_2_116PL 0xFFFF +#endif + +#define MG2_2_12PL 0xFFFD +#define MG2_2 (MG2_2_11PL & MG2_2_12PL & MG2_2_13PL & MG2_2_14PL & \ + MG2_2_15PL & MG2_2_16PL & MG2_2_17PL & MG2_2_18PL & \ + MG2_2_19PL & MG2_2_110PL & MG2_2_111PL & MG2_2_112PL & \ + MG2_2_113PL & MG2_2_114PL & MG2_2_115PL & MG2_2_116PL) +// End of MG2_2: +// Beginning of MG23: +#if (G2_1PL >= G2_3PL) || (G2_1PL == 0) +#define MG2_3_11PL ~(1 << 0) +#else +#define MG2_3_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_3PL) || (G2_2PL == 0) +#define MG2_3_12PL ~(1 << 1) +#else +#define MG2_3_12PL 0xFFFF +#endif + +#if (G2_4PL >= G2_3PL) || (G2_4PL == 0) +#define MG2_3_14PL ~(1 << 3) +#else +#define MG2_3_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_3PL) || (G2_5PL == 0) +#define MG2_3_15PL ~(1 << 4) +#else +#define MG2_3_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_3PL) || (G2_6PL == 0) +#define MG2_3_16PL ~(1 << 5) +#else +#define MG2_3_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_3PL) || (G2_7PL == 0) +#define MG2_3_17PL ~(1 << 6) +#else +#define MG2_3_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_3PL) || (G2_8PL == 0) +#define MG2_3_18PL ~(1 << 7) +#else +#define MG2_3_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_3PL) || (G2_9PL == 0) +#define MG2_3_19PL ~(1 << 8) +#else +#define MG2_3_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_3PL) || (G2_10PL == 0) +#define MG2_3_110PL ~(1 << 9) +#else +#define MG2_3_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_3PL) || (G2_11PL == 0) +#define MG2_3_111PL ~(1 << 10) +#else +#define MG2_3_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_3PL) || (G2_12PL == 0) +#define MG2_3_112PL ~(1 << 11) +#else +#define MG2_3_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_3PL) || (G2_13PL == 0) +#define MG2_3_113PL ~(1 << 12) +#else +#define MG2_3_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_3PL) || (G2_14PL == 0) +#define MG2_3_114PL ~(1 << 13) +#else +#define MG2_3_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_3PL) || (G2_15PL == 0) +#define MG2_3_115PL ~(1 << 14) +#else +#define MG2_3_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_3PL) || (G2_16PL == 0) +#define MG2_3_116PL ~(1 << 15) +#else +#define MG2_3_116PL 0xFFFF +#endif + +#define MG2_3_13PL 0xFFFB +#define MG2_3 (MG2_3_11PL & MG2_3_12PL & MG2_3_13PL & MG2_3_14PL & \ + MG2_3_15PL & MG2_3_16PL & MG2_3_17PL & MG2_3_18PL & \ + MG2_3_19PL & MG2_3_110PL & MG2_3_111PL & MG2_3_112PL & \ + MG2_3_113PL & MG2_3_114PL & MG2_3_115PL & MG2_3_116PL) +// End of MG2_3: +// Beginning of MG24: +#if (G2_1PL >= G2_4PL) || (G2_1PL == 0) +#define MG2_4_11PL ~(1 << 0) +#else +#define MG2_4_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_4PL) || (G2_2PL == 0) +#define MG2_4_12PL ~(1 << 1) +#else +#define MG2_4_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_4PL) || (G2_3PL == 0) +#define MG2_4_13PL ~(1 << 2) +#else +#define MG2_4_13PL 0xFFFF +#endif + +#if (G2_5PL >= G2_4PL) || (G2_5PL == 0) +#define MG2_4_15PL ~(1 << 4) +#else +#define MG2_4_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_4PL) || (G2_6PL == 0) +#define MG2_4_16PL ~(1 << 5) +#else +#define MG2_4_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_4PL) || (G2_7PL == 0) +#define MG2_4_17PL ~(1 << 6) +#else +#define MG2_4_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_4PL) || (G2_8PL == 0) +#define MG2_4_18PL ~(1 << 7) +#else +#define MG2_4_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_4PL) || (G2_9PL == 0) +#define MG2_4_19PL ~(1 << 8) +#else +#define MG2_4_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_4PL) || (G2_10PL == 0) +#define MG2_4_110PL ~(1 << 9) +#else +#define MG2_4_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_4PL) || (G2_11PL == 0) +#define MG2_4_111PL ~(1 << 10) +#else +#define MG2_4_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_4PL) || (G2_12PL == 0) +#define MG2_4_112PL ~(1 << 11) +#else +#define MG2_4_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_4PL) || (G2_13PL == 0) +#define MG2_4_113PL ~(1 << 12) +#else +#define MG2_4_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_4PL) || (G2_14PL == 0) +#define MG2_4_114PL ~(1 << 13) +#else +#define MG2_4_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_4PL) || (G2_15PL == 0) +#define MG2_4_115PL ~(1 << 14) +#else +#define MG2_4_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_4PL) || (G2_16PL == 0) +#define MG2_4_116PL ~(1 << 15) +#else +#define MG2_4_116PL 0xFFFF +#endif + +#define MG2_4_14PL 0xFFF7 +#define MG2_4 (MG2_4_11PL & MG2_4_12PL & MG2_4_13PL & MG2_4_14PL & \ + MG2_4_15PL & MG2_4_16PL & MG2_4_17PL & MG2_4_18PL & \ + MG2_4_19PL & MG2_4_110PL & MG2_4_111PL & MG2_4_112PL & \ + MG2_4_113PL & MG2_4_114PL & MG2_4_115PL & MG2_4_116PL) +// End of MG2_4: +// Beginning of MG25: +#if (G2_1PL >= G2_5PL) || (G2_1PL == 0) +#define MG2_5_11PL ~(1 << 0) +#else +#define MG2_5_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_5PL) || (G2_2PL == 0) +#define MG2_5_12PL ~(1 << 1) +#else +#define MG2_5_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_5PL) || (G2_3PL == 0) +#define MG2_5_13PL ~(1 << 2) +#else +#define MG2_5_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_5PL) || (G2_4PL == 0) +#define MG2_5_14PL ~(1 << 3) +#else +#define MG2_5_14PL 0xFFFF +#endif + +#if (G2_6PL >= G2_5PL) || (G2_6PL == 0) +#define MG2_5_16PL ~(1 << 5) +#else +#define MG2_5_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_5PL) || (G2_7PL == 0) +#define MG2_5_17PL ~(1 << 6) +#else +#define MG2_5_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_5PL) || (G2_8PL == 0) +#define MG2_5_18PL ~(1 << 7) +#else +#define MG2_5_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_5PL) || (G2_9PL == 0) +#define MG2_5_19PL ~(1 << 8) +#else +#define MG2_5_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_5PL) || (G2_10PL == 0) +#define MG2_5_110PL ~(1 << 9) +#else +#define MG2_5_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_5PL) || (G2_11PL == 0) +#define MG2_5_111PL ~(1 << 10) +#else +#define MG2_5_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_5PL) || (G2_12PL == 0) +#define MG2_5_112PL ~(1 << 11) +#else +#define MG2_5_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_5PL) || (G2_13PL == 0) +#define MG2_5_113PL ~(1 << 12) +#else +#define MG2_5_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_5PL) || (G2_14PL == 0) +#define MG2_5_114PL ~(1 << 13) +#else +#define MG2_5_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_5PL) || (G2_15PL == 0) +#define MG2_5_115PL ~(1 << 14) +#else +#define MG2_5_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_5PL) || (G2_16PL == 0) +#define MG2_5_116PL ~(1 << 15) +#else +#define MG2_5_116PL 0xFFFF +#endif + +#define MG2_5_15PL 0xFFEF +#define MG2_5 (MG2_5_11PL & MG2_5_12PL & MG2_5_13PL & MG2_5_14PL & \ + MG2_5_15PL & MG2_5_16PL & MG2_5_17PL & MG2_5_18PL & \ + MG2_5_19PL & MG2_5_110PL & MG2_5_111PL & MG2_5_112PL & \ + MG2_5_113PL & MG2_5_114PL & MG2_5_115PL & MG2_5_116PL) +// End of MG2_5: +// Beginning of MG26: +#if (G2_1PL >= G2_6PL) || (G2_1PL == 0) +#define MG2_6_11PL ~(1 << 0) +#else +#define MG2_6_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_6PL) || (G2_2PL == 0) +#define MG2_6_12PL ~(1 << 1) +#else +#define MG2_6_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_6PL) || (G2_3PL == 0) +#define MG2_6_13PL ~(1 << 2) +#else +#define MG2_6_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_6PL) || (G2_4PL == 0) +#define MG2_6_14PL ~(1 << 3) +#else +#define MG2_6_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_6PL) || (G2_5PL == 0) +#define MG2_6_15PL ~(1 << 4) +#else +#define MG2_6_15PL 0xFFFF +#endif + +#if (G2_7PL >= G2_6PL) || (G2_7PL == 0) +#define MG2_6_17PL ~(1 << 6) +#else +#define MG2_6_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_6PL) || (G2_8PL == 0) +#define MG2_6_18PL ~(1 << 7) +#else +#define MG2_6_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_6PL) || (G2_9PL == 0) +#define MG2_6_19PL ~(1 << 8) +#else +#define MG2_6_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_6PL) || (G2_10PL == 0) +#define MG2_6_110PL ~(1 << 9) +#else +#define MG2_6_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_6PL) || (G2_11PL == 0) +#define MG2_6_111PL ~(1 << 10) +#else +#define MG2_6_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_6PL) || (G2_12PL == 0) +#define MG2_6_112PL ~(1 << 11) +#else +#define MG2_6_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_6PL) || (G2_13PL == 0) +#define MG2_6_113PL ~(1 << 12) +#else +#define MG2_6_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_6PL) || (G2_14PL == 0) +#define MG2_6_114PL ~(1 << 13) +#else +#define MG2_6_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_6PL) || (G2_15PL == 0) +#define MG2_6_115PL ~(1 << 14) +#else +#define MG2_6_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_6PL) || (G2_16PL == 0) +#define MG2_6_116PL ~(1 << 15) +#else +#define MG2_6_116PL 0xFFFF +#endif + +#define MG2_6_16PL 0xFFDF +#define MG2_6 (MG2_6_11PL & MG2_6_12PL & MG2_6_13PL & MG2_6_14PL & \ + MG2_6_15PL & MG2_6_16PL & MG2_6_17PL & MG2_6_18PL & \ + MG2_6_19PL & MG2_6_110PL & MG2_6_111PL & MG2_6_112PL & \ + MG2_6_113PL & MG2_6_114PL & MG2_6_115PL & MG2_6_116PL) +// End of MG2_6: +// Beginning of MG27: +#if (G2_1PL >= G2_7PL) || (G2_1PL == 0) +#define MG2_7_11PL ~(1 << 0) +#else +#define MG2_7_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_7PL) || (G2_2PL == 0) +#define MG2_7_12PL ~(1 << 1) +#else +#define MG2_7_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_7PL) || (G2_3PL == 0) +#define MG2_7_13PL ~(1 << 2) +#else +#define MG2_7_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_7PL) || (G2_4PL == 0) +#define MG2_7_14PL ~(1 << 3) +#else +#define MG2_7_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_7PL) || (G2_5PL == 0) +#define MG2_7_15PL ~(1 << 4) +#else +#define MG2_7_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_7PL) || (G2_6PL == 0) +#define MG2_7_16PL ~(1 << 5) +#else +#define MG2_7_16PL 0xFFFF +#endif + +#if (G2_8PL >= G2_7PL) || (G2_8PL == 0) +#define MG2_7_18PL ~(1 << 7) +#else +#define MG2_7_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_7PL) || (G2_9PL == 0) +#define MG2_7_19PL ~(1 << 8) +#else +#define MG2_7_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_7PL) || (G2_10PL == 0) +#define MG2_7_110PL ~(1 << 9) +#else +#define MG2_7_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_7PL) || (G2_11PL == 0) +#define MG2_7_111PL ~(1 << 10) +#else +#define MG2_7_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_7PL) || (G2_12PL == 0) +#define MG2_7_112PL ~(1 << 11) +#else +#define MG2_7_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_7PL) || (G2_13PL == 0) +#define MG2_7_113PL ~(1 << 12) +#else +#define MG2_7_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_7PL) || (G2_14PL == 0) +#define MG2_7_114PL ~(1 << 13) +#else +#define MG2_7_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_7PL) || (G2_15PL == 0) +#define MG2_7_115PL ~(1 << 14) +#else +#define MG2_7_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_7PL) || (G2_16PL == 0) +#define MG2_7_116PL ~(1 << 15) +#else +#define MG2_7_116PL 0xFFFF +#endif + +#define MG2_7_17PL 0xFFBF +#define MG2_7 (MG2_7_11PL & MG2_7_12PL & MG2_7_13PL & MG2_7_14PL & \ + MG2_7_15PL & MG2_7_16PL & MG2_7_17PL & MG2_7_18PL & \ + MG2_7_19PL & MG2_7_110PL & MG2_7_111PL & MG2_7_112PL & \ + MG2_7_113PL & MG2_7_114PL & MG2_7_115PL & MG2_7_116PL) +// End of MG2_7: +// Beginning of MG28: +#if (G2_1PL >= G2_8PL) || (G2_1PL == 0) +#define MG2_8_11PL ~(1 << 0) +#else +#define MG2_8_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_8PL) || (G2_2PL == 0) +#define MG2_8_12PL ~(1 << 1) +#else +#define MG2_8_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_8PL) || (G2_3PL == 0) +#define MG2_8_13PL ~(1 << 2) +#else +#define MG2_8_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_8PL) || (G2_4PL == 0) +#define MG2_8_14PL ~(1 << 3) +#else +#define MG2_8_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_8PL) || (G2_5PL == 0) +#define MG2_8_15PL ~(1 << 4) +#else +#define MG2_8_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_8PL) || (G2_6PL == 0) +#define MG2_8_16PL ~(1 << 5) +#else +#define MG2_8_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_8PL) || (G2_7PL == 0) +#define MG2_8_17PL ~(1 << 6) +#else +#define MG2_8_17PL 0xFFFF +#endif + +#if (G2_9PL >= G2_8PL) || (G2_9PL == 0) +#define MG2_8_19PL ~(1 << 8) +#else +#define MG2_8_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_8PL) || (G2_10PL == 0) +#define MG2_8_110PL ~(1 << 9) +#else +#define MG2_8_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_8PL) || (G2_11PL == 0) +#define MG2_8_111PL ~(1 << 10) +#else +#define MG2_8_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_8PL) || (G2_12PL == 0) +#define MG2_8_112PL ~(1 << 11) +#else +#define MG2_8_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_8PL) || (G2_13PL == 0) +#define MG2_8_113PL ~(1 << 12) +#else +#define MG2_8_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_8PL) || (G2_14PL == 0) +#define MG2_8_114PL ~(1 << 13) +#else +#define MG2_8_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_8PL) || (G2_15PL == 0) +#define MG2_8_115PL ~(1 << 14) +#else +#define MG2_8_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_8PL) || (G2_16PL == 0) +#define MG2_8_116PL ~(1 << 15) +#else +#define MG2_8_116PL 0xFFFF +#endif + +#define MG2_8_18PL 0xFF7F +#define MG2_8 (MG2_8_11PL & MG2_8_12PL & MG2_8_13PL & MG2_8_14PL & \ + MG2_8_15PL & MG2_8_16PL & MG2_8_17PL & MG2_8_18PL & \ + MG2_8_19PL & MG2_8_110PL & MG2_8_111PL & MG2_8_112PL & \ + MG2_8_113PL & MG2_8_114PL & MG2_8_115PL & MG2_8_116PL) +// End of MG2_8: +// Beginning of MG29: +#if (G2_1PL >= G2_9PL) || (G2_1PL == 0) +#define MG2_9_11PL ~(1 << 0) +#else +#define MG2_9_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_9PL) || (G2_2PL == 0) +#define MG2_9_12PL ~(1 << 1) +#else +#define MG2_9_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_9PL) || (G2_3PL == 0) +#define MG2_9_13PL ~(1 << 2) +#else +#define MG2_9_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_9PL) || (G2_4PL == 0) +#define MG2_9_14PL ~(1 << 3) +#else +#define MG2_9_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_9PL) || (G2_5PL == 0) +#define MG2_9_15PL ~(1 << 4) +#else +#define MG2_9_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_9PL) || (G2_6PL == 0) +#define MG2_9_16PL ~(1 << 5) +#else +#define MG2_9_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_9PL) || (G2_7PL == 0) +#define MG2_9_17PL ~(1 << 6) +#else +#define MG2_9_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_9PL) || (G2_8PL == 0) +#define MG2_9_18PL ~(1 << 7) +#else +#define MG2_9_18PL 0xFFFF +#endif + +#if (G2_10PL >= G2_9PL) || (G2_10PL == 0) +#define MG2_9_110PL ~(1 << 9) +#else +#define MG2_9_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_9PL) || (G2_11PL == 0) +#define MG2_9_111PL ~(1 << 10) +#else +#define MG2_9_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_9PL) || (G2_12PL == 0) +#define MG2_9_112PL ~(1 << 11) +#else +#define MG2_9_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_9PL) || (G2_13PL == 0) +#define MG2_9_113PL ~(1 << 12) +#else +#define MG2_9_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_9PL) || (G2_14PL == 0) +#define MG2_9_114PL ~(1 << 13) +#else +#define MG2_9_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_9PL) || (G2_15PL == 0) +#define MG2_9_115PL ~(1 << 14) +#else +#define MG2_9_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_9PL) || (G2_16PL == 0) +#define MG2_9_116PL ~(1 << 15) +#else +#define MG2_9_116PL 0xFFFF +#endif + +#define MG2_9_19PL 0xFEFF +#define MG2_9 (MG2_9_11PL & MG2_9_12PL & MG2_9_13PL & MG2_9_14PL & \ + MG2_9_15PL & MG2_9_16PL & MG2_9_17PL & MG2_9_18PL & \ + MG2_9_19PL & MG2_9_110PL & MG2_9_111PL & MG2_9_112PL & \ + MG2_9_113PL & MG2_9_114PL & MG2_9_115PL & MG2_9_116PL) +// End of MG2_9: +// Beginning of MG210: +#if (G2_1PL >= G2_10PL) || (G2_1PL == 0) +#define MG2_10_11PL ~(1 << 0) +#else +#define MG2_10_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_10PL) || (G2_2PL == 0) +#define MG2_10_12PL ~(1 << 1) +#else +#define MG2_10_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_10PL) || (G2_3PL == 0) +#define MG2_10_13PL ~(1 << 2) +#else +#define MG2_10_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_10PL) || (G2_4PL == 0) +#define MG2_10_14PL ~(1 << 3) +#else +#define MG2_10_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_10PL) || (G2_5PL == 0) +#define MG2_10_15PL ~(1 << 4) +#else +#define MG2_10_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_10PL) || (G2_6PL == 0) +#define MG2_10_16PL ~(1 << 5) +#else +#define MG2_10_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_10PL) || (G2_7PL == 0) +#define MG2_10_17PL ~(1 << 6) +#else +#define MG2_10_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_10PL) || (G2_8PL == 0) +#define MG2_10_18PL ~(1 << 7) +#else +#define MG2_10_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_10PL) || (G2_9PL == 0) +#define MG2_10_19PL ~(1 << 8) +#else +#define MG2_10_19PL 0xFFFF +#endif + +#if (G2_11PL >= G2_10PL) || (G2_11PL == 0) +#define MG2_10_111PL ~(1 << 10) +#else +#define MG2_10_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_10PL) || (G2_12PL == 0) +#define MG2_10_112PL ~(1 << 11) +#else +#define MG2_10_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_10PL) || (G2_13PL == 0) +#define MG2_10_113PL ~(1 << 12) +#else +#define MG2_10_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_10PL) || (G2_14PL == 0) +#define MG2_10_114PL ~(1 << 13) +#else +#define MG2_10_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_10PL) || (G2_15PL == 0) +#define MG2_10_115PL ~(1 << 14) +#else +#define MG2_10_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_10PL) || (G2_16PL == 0) +#define MG2_10_116PL ~(1 << 15) +#else +#define MG2_10_116PL 0xFFFF +#endif + +#define MG2_10_110PL 0xFDFF +#define MG2_10 (MG2_10_11PL & MG2_10_12PL & MG2_10_13PL & MG2_10_14PL & \ + MG2_10_15PL & MG2_10_16PL & MG2_10_17PL & MG2_10_18PL & \ + MG2_10_19PL & MG2_10_110PL & MG2_10_111PL & MG2_10_112PL & \ + MG2_10_113PL & MG2_10_114PL & MG2_10_115PL & MG2_10_116PL) +// End of MG2_10: +// Beginning of MG211: +#if (G2_1PL >= G2_11PL) || (G2_1PL == 0) +#define MG2_11_11PL ~(1 << 0) +#else +#define MG2_11_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_11PL) || (G2_2PL == 0) +#define MG2_11_12PL ~(1 << 1) +#else +#define MG2_11_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_11PL) || (G2_3PL == 0) +#define MG2_11_13PL ~(1 << 2) +#else +#define MG2_11_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_11PL) || (G2_4PL == 0) +#define MG2_11_14PL ~(1 << 3) +#else +#define MG2_11_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_11PL) || (G2_5PL == 0) +#define MG2_11_15PL ~(1 << 4) +#else +#define MG2_11_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_11PL) || (G2_6PL == 0) +#define MG2_11_16PL ~(1 << 5) +#else +#define MG2_11_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_11PL) || (G2_7PL == 0) +#define MG2_11_17PL ~(1 << 6) +#else +#define MG2_11_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_11PL) || (G2_8PL == 0) +#define MG2_11_18PL ~(1 << 7) +#else +#define MG2_11_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_11PL) || (G2_9PL == 0) +#define MG2_11_19PL ~(1 << 8) +#else +#define MG2_11_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_11PL) || (G2_10PL == 0) +#define MG2_11_110PL ~(1 << 9) +#else +#define MG2_11_110PL 0xFFFF +#endif + +#if (G2_12PL >= G2_11PL) || (G2_12PL == 0) +#define MG2_11_112PL ~(1 << 11) +#else +#define MG2_11_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_11PL) || (G2_13PL == 0) +#define MG2_11_113PL ~(1 << 12) +#else +#define MG2_11_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_11PL) || (G2_14PL == 0) +#define MG2_11_114PL ~(1 << 13) +#else +#define MG2_11_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_11PL) || (G2_15PL == 0) +#define MG2_11_115PL ~(1 << 14) +#else +#define MG2_11_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_11PL) || (G2_16PL == 0) +#define MG2_11_116PL ~(1 << 15) +#else +#define MG2_11_116PL 0xFFFF +#endif + +#define MG2_11_111PL 0xFBFF +#define MG2_11 (MG2_11_11PL & MG2_11_12PL & MG2_11_13PL & MG2_11_14PL & \ + MG2_11_15PL & MG2_11_16PL & MG2_11_17PL & MG2_11_18PL & \ + MG2_11_19PL & MG2_11_110PL & MG2_11_111PL & MG2_11_112PL & \ + MG2_11_113PL & MG2_11_114PL & MG2_11_115PL & MG2_11_116PL) +// End of MG2_11: +// Beginning of MG212: +#if (G2_1PL >= G2_12PL) || (G2_1PL == 0) +#define MG2_12_11PL ~(1 << 0) +#else +#define MG2_12_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_12PL) || (G2_2PL == 0) +#define MG2_12_12PL ~(1 << 1) +#else +#define MG2_12_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_12PL) || (G2_3PL == 0) +#define MG2_12_13PL ~(1 << 2) +#else +#define MG2_12_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_12PL) || (G2_4PL == 0) +#define MG2_12_14PL ~(1 << 3) +#else +#define MG2_12_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_12PL) || (G2_5PL == 0) +#define MG2_12_15PL ~(1 << 4) +#else +#define MG2_12_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_12PL) || (G2_6PL == 0) +#define MG2_12_16PL ~(1 << 5) +#else +#define MG2_12_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_12PL) || (G2_7PL == 0) +#define MG2_12_17PL ~(1 << 6) +#else +#define MG2_12_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_12PL) || (G2_8PL == 0) +#define MG2_12_18PL ~(1 << 7) +#else +#define MG2_12_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_12PL) || (G2_9PL == 0) +#define MG2_12_19PL ~(1 << 8) +#else +#define MG2_12_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_12PL) || (G2_10PL == 0) +#define MG2_12_110PL ~(1 << 9) +#else +#define MG2_12_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_12PL) || (G2_11PL == 0) +#define MG2_12_111PL ~(1 << 10) +#else +#define MG2_12_111PL 0xFFFF +#endif + +#if (G2_13PL >= G2_12PL) || (G2_13PL == 0) +#define MG2_12_113PL ~(1 << 12) +#else +#define MG2_12_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_12PL) || (G2_14PL == 0) +#define MG2_12_114PL ~(1 << 13) +#else +#define MG2_12_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_12PL) || (G2_15PL == 0) +#define MG2_12_115PL ~(1 << 14) +#else +#define MG2_12_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_12PL) || (G2_16PL == 0) +#define MG2_12_116PL ~(1 << 15) +#else +#define MG2_12_116PL 0xFFFF +#endif + +#define MG2_12_112PL 0xF7FF +#define MG2_12 (MG2_12_11PL & MG2_12_12PL & MG2_12_13PL & MG2_12_14PL & \ + MG2_12_15PL & MG2_12_16PL & MG2_12_17PL & MG2_12_18PL & \ + MG2_12_19PL & MG2_12_110PL & MG2_12_111PL & MG2_12_112PL & \ + MG2_12_113PL & MG2_12_114PL & MG2_12_115PL & MG2_12_116PL) +// End of MG2_12: +// Beginning of MG213: +#if (G2_1PL >= G2_13PL) || (G2_1PL == 0) +#define MG2_13_11PL ~(1 << 0) +#else +#define MG2_13_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_13PL) || (G2_2PL == 0) +#define MG2_13_12PL ~(1 << 1) +#else +#define MG2_13_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_13PL) || (G2_3PL == 0) +#define MG2_13_13PL ~(1 << 2) +#else +#define MG2_13_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_13PL) || (G2_4PL == 0) +#define MG2_13_14PL ~(1 << 3) +#else +#define MG2_13_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_13PL) || (G2_5PL == 0) +#define MG2_13_15PL ~(1 << 4) +#else +#define MG2_13_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_13PL) || (G2_6PL == 0) +#define MG2_13_16PL ~(1 << 5) +#else +#define MG2_13_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_13PL) || (G2_7PL == 0) +#define MG2_13_17PL ~(1 << 6) +#else +#define MG2_13_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_13PL) || (G2_8PL == 0) +#define MG2_13_18PL ~(1 << 7) +#else +#define MG2_13_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_13PL) || (G2_9PL == 0) +#define MG2_13_19PL ~(1 << 8) +#else +#define MG2_13_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_13PL) || (G2_10PL == 0) +#define MG2_13_110PL ~(1 << 9) +#else +#define MG2_13_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_13PL) || (G2_11PL == 0) +#define MG2_13_111PL ~(1 << 10) +#else +#define MG2_13_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_13PL) || (G2_12PL == 0) +#define MG2_13_112PL ~(1 << 11) +#else +#define MG2_13_112PL 0xFFFF +#endif + +#if (G2_14PL >= G2_13PL) || (G2_14PL == 0) +#define MG2_13_114PL ~(1 << 13) +#else +#define MG2_13_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_13PL) || (G2_15PL == 0) +#define MG2_13_115PL ~(1 << 14) +#else +#define MG2_13_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_13PL) || (G2_16PL == 0) +#define MG2_13_116PL ~(1 << 15) +#else +#define MG2_13_116PL 0xFFFF +#endif + +#define MG2_13_113PL 0xEFFF +#define MG2_13 (MG2_13_11PL & MG2_13_12PL & MG2_13_13PL & MG2_13_14PL & \ + MG2_13_15PL & MG2_13_16PL & MG2_13_17PL & MG2_13_18PL & \ + MG2_13_19PL & MG2_13_110PL & MG2_13_111PL & MG2_13_112PL & \ + MG2_13_113PL & MG2_13_114PL & MG2_13_115PL & MG2_13_116PL) +// End of MG2_13: +// Beginning of MG214: +#if (G2_1PL >= G2_14PL) || (G2_1PL == 0) +#define MG2_14_11PL ~(1 << 0) +#else +#define MG2_14_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_14PL) || (G2_2PL == 0) +#define MG2_14_12PL ~(1 << 1) +#else +#define MG2_14_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_14PL) || (G2_3PL == 0) +#define MG2_14_13PL ~(1 << 2) +#else +#define MG2_14_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_14PL) || (G2_4PL == 0) +#define MG2_14_14PL ~(1 << 3) +#else +#define MG2_14_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_14PL) || (G2_5PL == 0) +#define MG2_14_15PL ~(1 << 4) +#else +#define MG2_14_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_14PL) || (G2_6PL == 0) +#define MG2_14_16PL ~(1 << 5) +#else +#define MG2_14_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_14PL) || (G2_7PL == 0) +#define MG2_14_17PL ~(1 << 6) +#else +#define MG2_14_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_14PL) || (G2_8PL == 0) +#define MG2_14_18PL ~(1 << 7) +#else +#define MG2_14_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_14PL) || (G2_9PL == 0) +#define MG2_14_19PL ~(1 << 8) +#else +#define MG2_14_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_14PL) || (G2_10PL == 0) +#define MG2_14_110PL ~(1 << 9) +#else +#define MG2_14_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_14PL) || (G2_11PL == 0) +#define MG2_14_111PL ~(1 << 10) +#else +#define MG2_14_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_14PL) || (G2_12PL == 0) +#define MG2_14_112PL ~(1 << 11) +#else +#define MG2_14_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_14PL) || (G2_13PL == 0) +#define MG2_14_113PL ~(1 << 12) +#else +#define MG2_14_113PL 0xFFFF +#endif + +#if (G2_15PL >= G2_14PL) || (G2_15PL == 0) +#define MG2_14_115PL ~(1 << 14) +#else +#define MG2_14_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_14PL) || (G2_16PL == 0) +#define MG2_14_116PL ~(1 << 15) +#else +#define MG2_14_116PL 0xFFFF +#endif + +#define MG2_14_114PL 0xDFFF +#define MG2_14 (MG2_14_11PL & MG2_14_12PL & MG2_14_13PL & MG2_14_14PL & \ + MG2_14_15PL & MG2_14_16PL & MG2_14_17PL & MG2_14_18PL & \ + MG2_14_19PL & MG2_14_110PL & MG2_14_111PL & MG2_14_112PL & \ + MG2_14_113PL & MG2_14_114PL & MG2_14_115PL & MG2_14_116PL) +// End of MG2_14: +// Beginning of MG215: +#if (G2_1PL >= G2_15PL) || (G2_1PL == 0) +#define MG2_15_11PL ~(1 << 0) +#else +#define MG2_15_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_15PL) || (G2_2PL == 0) +#define MG2_15_12PL ~(1 << 1) +#else +#define MG2_15_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_15PL) || (G2_3PL == 0) +#define MG2_15_13PL ~(1 << 2) +#else +#define MG2_15_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_15PL) || (G2_4PL == 0) +#define MG2_15_14PL ~(1 << 3) +#else +#define MG2_15_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_15PL) || (G2_5PL == 0) +#define MG2_15_15PL ~(1 << 4) +#else +#define MG2_15_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_15PL) || (G2_6PL == 0) +#define MG2_15_16PL ~(1 << 5) +#else +#define MG2_15_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_15PL) || (G2_7PL == 0) +#define MG2_15_17PL ~(1 << 6) +#else +#define MG2_15_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_15PL) || (G2_8PL == 0) +#define MG2_15_18PL ~(1 << 7) +#else +#define MG2_15_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_15PL) || (G2_9PL == 0) +#define MG2_15_19PL ~(1 << 8) +#else +#define MG2_15_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_15PL) || (G2_10PL == 0) +#define MG2_15_110PL ~(1 << 9) +#else +#define MG2_15_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_15PL) || (G2_11PL == 0) +#define MG2_15_111PL ~(1 << 10) +#else +#define MG2_15_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_15PL) || (G2_12PL == 0) +#define MG2_15_112PL ~(1 << 11) +#else +#define MG2_15_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_15PL) || (G2_13PL == 0) +#define MG2_15_113PL ~(1 << 12) +#else +#define MG2_15_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_15PL) || (G2_14PL == 0) +#define MG2_15_114PL ~(1 << 13) +#else +#define MG2_15_114PL 0xFFFF +#endif + +#if (G2_16PL >= G2_15PL) || (G2_16PL == 0) +#define MG2_15_116PL ~(1 << 15) +#else +#define MG2_15_116PL 0xFFFF +#endif + +#define MG2_15_115PL 0xBFFF +#define MG2_15 (MG2_15_11PL & MG2_15_12PL & MG2_15_13PL & MG2_15_14PL & \ + MG2_15_15PL & MG2_15_16PL & MG2_15_17PL & MG2_15_18PL & \ + MG2_15_19PL & MG2_15_110PL & MG2_15_111PL & MG2_15_112PL & \ + MG2_15_113PL & MG2_15_114PL & MG2_15_115PL & MG2_15_116PL) +// End of MG2_15: +// Beginning of MG216: +#if (G2_1PL >= G2_16PL) || (G2_1PL == 0) +#define MG2_16_11PL ~(1 << 0) +#else +#define MG2_16_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_16PL) || (G2_2PL == 0) +#define MG2_16_12PL ~(1 << 1) +#else +#define MG2_16_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_16PL) || (G2_3PL == 0) +#define MG2_16_13PL ~(1 << 2) +#else +#define MG2_16_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_16PL) || (G2_4PL == 0) +#define MG2_16_14PL ~(1 << 3) +#else +#define MG2_16_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_16PL) || (G2_5PL == 0) +#define MG2_16_15PL ~(1 << 4) +#else +#define MG2_16_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_16PL) || (G2_6PL == 0) +#define MG2_16_16PL ~(1 << 5) +#else +#define MG2_16_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_16PL) || (G2_7PL == 0) +#define MG2_16_17PL ~(1 << 6) +#else +#define MG2_16_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_16PL) || (G2_8PL == 0) +#define MG2_16_18PL ~(1 << 7) +#else +#define MG2_16_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_16PL) || (G2_9PL == 0) +#define MG2_16_19PL ~(1 << 8) +#else +#define MG2_16_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_16PL) || (G2_10PL == 0) +#define MG2_16_110PL ~(1 << 9) +#else +#define MG2_16_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_16PL) || (G2_11PL == 0) +#define MG2_16_111PL ~(1 << 10) +#else +#define MG2_16_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_16PL) || (G2_12PL == 0) +#define MG2_16_112PL ~(1 << 11) +#else +#define MG2_16_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_16PL) || (G2_13PL == 0) +#define MG2_16_113PL ~(1 << 12) +#else +#define MG2_16_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_16PL) || (G2_14PL == 0) +#define MG2_16_114PL ~(1 << 13) +#else +#define MG2_16_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_16PL) || (G2_15PL == 0) +#define MG2_16_115PL ~(1 << 14) +#else +#define MG2_16_115PL 0xFFFF +#endif + +#define MG2_16_116PL 0x7FFF +#define MG2_16 (MG2_16_11PL & MG2_16_12PL & MG2_16_13PL & MG2_16_14PL & \ + MG2_16_15PL & MG2_16_16PL & MG2_16_17PL & MG2_16_18PL & \ + MG2_16_19PL & MG2_16_110PL & MG2_16_111PL & MG2_16_112PL & \ + MG2_16_113PL & MG2_16_114PL & MG2_16_115PL & MG2_16_116PL) +// End of MG2_16: + + +// +// Automatically generate PIEIER3 interrupt masks MG31 to MG316: +// + +// Beginning of MG31: +#if (G3_2PL >= G3_1PL) || (G3_2PL == 0) +#define MG3_1_12PL ~(1 << 1) +#else +#define MG3_1_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_1PL) || (G3_3PL == 0) +#define MG3_1_13PL ~(1 << 2) +#else +#define MG3_1_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_1PL) || (G3_4PL == 0) +#define MG3_1_14PL ~(1 << 3) +#else +#define MG3_1_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_1PL) || (G3_5PL == 0) +#define MG3_1_15PL ~(1 << 4) +#else +#define MG3_1_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_1PL) || (G3_6PL == 0) +#define MG3_1_16PL ~(1 << 5) +#else +#define MG3_1_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_1PL) || (G3_7PL == 0) +#define MG3_1_17PL ~(1 << 6) +#else +#define MG3_1_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_1PL) || (G3_8PL == 0) +#define MG3_1_18PL ~(1 << 7) +#else +#define MG3_1_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_1PL) || (G3_9PL == 0) +#define MG3_1_19PL ~(1 << 8) +#else +#define MG3_1_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_1PL) || (G3_10PL == 0) +#define MG3_1_110PL ~(1 << 9) +#else +#define MG3_1_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_1PL) || (G3_11PL == 0) +#define MG3_1_111PL ~(1 << 10) +#else +#define MG3_1_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_1PL) || (G3_12PL == 0) +#define MG3_1_112PL ~(1 << 11) +#else +#define MG3_1_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_1PL) || (G3_13PL == 0) +#define MG3_1_113PL ~(1 << 12) +#else +#define MG3_1_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_1PL) || (G3_14PL == 0) +#define MG3_1_114PL ~(1 << 13) +#else +#define MG3_1_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_1PL) || (G3_15PL == 0) +#define MG3_1_115PL ~(1 << 14) +#else +#define MG3_1_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_1PL) || (G3_16PL == 0) +#define MG3_1_116PL ~(1 << 15) +#else +#define MG3_1_116PL 0xFFFF +#endif + +#define MG3_1_11PL 0xFFFE +#define MG3_1 (MG3_1_11PL & MG3_1_12PL & MG3_1_13PL & MG3_1_14PL & \ + MG3_1_15PL & MG3_1_16PL & MG3_1_17PL & MG3_1_18PL & \ + MG3_1_19PL & MG3_1_110PL & MG3_1_111PL & MG3_1_112PL & \ + MG3_1_113PL & MG3_1_114PL & MG3_1_115PL & MG3_1_116PL) +// End of MG3_1: +// Beginning of MG32: +#if (G3_1PL >= G3_2PL) || (G3_1PL == 0) +#define MG3_2_11PL ~(1 << 0) +#else +#define MG3_2_11PL 0xFFFF +#endif + +#if (G3_3PL >= G3_2PL) || (G3_3PL == 0) +#define MG3_2_13PL ~(1 << 2) +#else +#define MG3_2_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_2PL) || (G3_4PL == 0) +#define MG3_2_14PL ~(1 << 3) +#else +#define MG3_2_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_2PL) || (G3_5PL == 0) +#define MG3_2_15PL ~(1 << 4) +#else +#define MG3_2_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_2PL) || (G3_6PL == 0) +#define MG3_2_16PL ~(1 << 5) +#else +#define MG3_2_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_2PL) || (G3_7PL == 0) +#define MG3_2_17PL ~(1 << 6) +#else +#define MG3_2_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_2PL) || (G3_8PL == 0) +#define MG3_2_18PL ~(1 << 7) +#else +#define MG3_2_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_2PL) || (G3_9PL == 0) +#define MG3_2_19PL ~(1 << 8) +#else +#define MG3_2_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_2PL) || (G3_10PL == 0) +#define MG3_2_110PL ~(1 << 9) +#else +#define MG3_2_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_2PL) || (G3_11PL == 0) +#define MG3_2_111PL ~(1 << 10) +#else +#define MG3_2_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_2PL) || (G3_12PL == 0) +#define MG3_2_112PL ~(1 << 11) +#else +#define MG3_2_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_2PL) || (G3_13PL == 0) +#define MG3_2_113PL ~(1 << 12) +#else +#define MG3_2_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_2PL) || (G3_14PL == 0) +#define MG3_2_114PL ~(1 << 13) +#else +#define MG3_2_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_2PL) || (G3_15PL == 0) +#define MG3_2_115PL ~(1 << 14) +#else +#define MG3_2_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_2PL) || (G3_16PL == 0) +#define MG3_2_116PL ~(1 << 15) +#else +#define MG3_2_116PL 0xFFFF +#endif + +#define MG3_2_12PL 0xFFFD +#define MG3_2 (MG3_2_11PL & MG3_2_12PL & MG3_2_13PL & MG3_2_14PL & \ + MG3_2_15PL & MG3_2_16PL & MG3_2_17PL & MG3_2_18PL & \ + MG3_2_19PL & MG3_2_110PL & MG3_2_111PL & MG3_2_112PL & \ + MG3_2_113PL & MG3_2_114PL & MG3_2_115PL & MG3_2_116PL) +// End of MG3_2: +// Beginning of MG33: +#if (G3_1PL >= G3_3PL) || (G3_1PL == 0) +#define MG3_3_11PL ~(1 << 0) +#else +#define MG3_3_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_3PL) || (G3_2PL == 0) +#define MG3_3_12PL ~(1 << 1) +#else +#define MG3_3_12PL 0xFFFF +#endif + +#if (G3_4PL >= G3_3PL) || (G3_4PL == 0) +#define MG3_3_14PL ~(1 << 3) +#else +#define MG3_3_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_3PL) || (G3_5PL == 0) +#define MG3_3_15PL ~(1 << 4) +#else +#define MG3_3_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_3PL) || (G3_6PL == 0) +#define MG3_3_16PL ~(1 << 5) +#else +#define MG3_3_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_3PL) || (G3_7PL == 0) +#define MG3_3_17PL ~(1 << 6) +#else +#define MG3_3_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_3PL) || (G3_8PL == 0) +#define MG3_3_18PL ~(1 << 7) +#else +#define MG3_3_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_3PL) || (G3_9PL == 0) +#define MG3_3_19PL ~(1 << 8) +#else +#define MG3_3_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_3PL) || (G3_10PL == 0) +#define MG3_3_110PL ~(1 << 9) +#else +#define MG3_3_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_3PL) || (G3_11PL == 0) +#define MG3_3_111PL ~(1 << 10) +#else +#define MG3_3_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_3PL) || (G3_12PL == 0) +#define MG3_3_112PL ~(1 << 11) +#else +#define MG3_3_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_3PL) || (G3_13PL == 0) +#define MG3_3_113PL ~(1 << 12) +#else +#define MG3_3_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_3PL) || (G3_14PL == 0) +#define MG3_3_114PL ~(1 << 13) +#else +#define MG3_3_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_3PL) || (G3_15PL == 0) +#define MG3_3_115PL ~(1 << 14) +#else +#define MG3_3_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_3PL) || (G3_16PL == 0) +#define MG3_3_116PL ~(1 << 15) +#else +#define MG3_3_116PL 0xFFFF +#endif + +#define MG3_3_13PL 0xFFFB +#define MG3_3 (MG3_3_11PL & MG3_3_12PL & MG3_3_13PL & MG3_3_14PL & \ + MG3_3_15PL & MG3_3_16PL & MG3_3_17PL & MG3_3_18PL & \ + MG3_3_19PL & MG3_3_110PL & MG3_3_111PL & MG3_3_112PL & \ + MG3_3_113PL & MG3_3_114PL & MG3_3_115PL & MG3_3_116PL) +// End of MG3_3: +// Beginning of MG34: +#if (G3_1PL >= G3_4PL) || (G3_1PL == 0) +#define MG3_4_11PL ~(1 << 0) +#else +#define MG3_4_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_4PL) || (G3_2PL == 0) +#define MG3_4_12PL ~(1 << 1) +#else +#define MG3_4_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_4PL) || (G3_3PL == 0) +#define MG3_4_13PL ~(1 << 2) +#else +#define MG3_4_13PL 0xFFFF +#endif + +#if (G3_5PL >= G3_4PL) || (G3_5PL == 0) +#define MG3_4_15PL ~(1 << 4) +#else +#define MG3_4_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_4PL) || (G3_6PL == 0) +#define MG3_4_16PL ~(1 << 5) +#else +#define MG3_4_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_4PL) || (G3_7PL == 0) +#define MG3_4_17PL ~(1 << 6) +#else +#define MG3_4_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_4PL) || (G3_8PL == 0) +#define MG3_4_18PL ~(1 << 7) +#else +#define MG3_4_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_4PL) || (G3_9PL == 0) +#define MG3_4_19PL ~(1 << 8) +#else +#define MG3_4_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_4PL) || (G3_10PL == 0) +#define MG3_4_110PL ~(1 << 9) +#else +#define MG3_4_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_4PL) || (G3_11PL == 0) +#define MG3_4_111PL ~(1 << 10) +#else +#define MG3_4_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_4PL) || (G3_12PL == 0) +#define MG3_4_112PL ~(1 << 11) +#else +#define MG3_4_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_4PL) || (G3_13PL == 0) +#define MG3_4_113PL ~(1 << 12) +#else +#define MG3_4_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_4PL) || (G3_14PL == 0) +#define MG3_4_114PL ~(1 << 13) +#else +#define MG3_4_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_4PL) || (G3_15PL == 0) +#define MG3_4_115PL ~(1 << 14) +#else +#define MG3_4_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_4PL) || (G3_16PL == 0) +#define MG3_4_116PL ~(1 << 15) +#else +#define MG3_4_116PL 0xFFFF +#endif + +#define MG3_4_14PL 0xFFF7 +#define MG3_4 (MG3_4_11PL & MG3_4_12PL & MG3_4_13PL & MG3_4_14PL & \ + MG3_4_15PL & MG3_4_16PL & MG3_4_17PL & MG3_4_18PL & \ + MG3_4_19PL & MG3_4_110PL & MG3_4_111PL & MG3_4_112PL & \ + MG3_4_113PL & MG3_4_114PL & MG3_4_115PL & MG3_4_116PL) +// End of MG3_4: +// Beginning of MG35: +#if (G3_1PL >= G3_5PL) || (G3_1PL == 0) +#define MG3_5_11PL ~(1 << 0) +#else +#define MG3_5_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_5PL) || (G3_2PL == 0) +#define MG3_5_12PL ~(1 << 1) +#else +#define MG3_5_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_5PL) || (G3_3PL == 0) +#define MG3_5_13PL ~(1 << 2) +#else +#define MG3_5_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_5PL) || (G3_4PL == 0) +#define MG3_5_14PL ~(1 << 3) +#else +#define MG3_5_14PL 0xFFFF +#endif + +#if (G3_6PL >= G3_5PL) || (G3_6PL == 0) +#define MG3_5_16PL ~(1 << 5) +#else +#define MG3_5_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_5PL) || (G3_7PL == 0) +#define MG3_5_17PL ~(1 << 6) +#else +#define MG3_5_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_5PL) || (G3_8PL == 0) +#define MG3_5_18PL ~(1 << 7) +#else +#define MG3_5_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_5PL) || (G3_9PL == 0) +#define MG3_5_19PL ~(1 << 8) +#else +#define MG3_5_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_5PL) || (G3_10PL == 0) +#define MG3_5_110PL ~(1 << 9) +#else +#define MG3_5_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_5PL) || (G3_11PL == 0) +#define MG3_5_111PL ~(1 << 10) +#else +#define MG3_5_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_5PL) || (G3_12PL == 0) +#define MG3_5_112PL ~(1 << 11) +#else +#define MG3_5_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_5PL) || (G3_13PL == 0) +#define MG3_5_113PL ~(1 << 12) +#else +#define MG3_5_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_5PL) || (G3_14PL == 0) +#define MG3_5_114PL ~(1 << 13) +#else +#define MG3_5_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_5PL) || (G3_15PL == 0) +#define MG3_5_115PL ~(1 << 14) +#else +#define MG3_5_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_5PL) || (G3_16PL == 0) +#define MG3_5_116PL ~(1 << 15) +#else +#define MG3_5_116PL 0xFFFF +#endif + +#define MG3_5_15PL 0xFFEF +#define MG3_5 (MG3_5_11PL & MG3_5_12PL & MG3_5_13PL & MG3_5_14PL & \ + MG3_5_15PL & MG3_5_16PL & MG3_5_17PL & MG3_5_18PL & \ + MG3_5_19PL & MG3_5_110PL & MG3_5_111PL & MG3_5_112PL & \ + MG3_5_113PL & MG3_5_114PL & MG3_5_115PL & MG3_5_116PL) +// End of MG3_5: +// Beginning of MG36: +#if (G3_1PL >= G3_6PL) || (G3_1PL == 0) +#define MG3_6_11PL ~(1 << 0) +#else +#define MG3_6_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_6PL) || (G3_2PL == 0) +#define MG3_6_12PL ~(1 << 1) +#else +#define MG3_6_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_6PL) || (G3_3PL == 0) +#define MG3_6_13PL ~(1 << 2) +#else +#define MG3_6_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_6PL) || (G3_4PL == 0) +#define MG3_6_14PL ~(1 << 3) +#else +#define MG3_6_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_6PL) || (G3_5PL == 0) +#define MG3_6_15PL ~(1 << 4) +#else +#define MG3_6_15PL 0xFFFF +#endif + +#if (G3_7PL >= G3_6PL) || (G3_7PL == 0) +#define MG3_6_17PL ~(1 << 6) +#else +#define MG3_6_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_6PL) || (G3_8PL == 0) +#define MG3_6_18PL ~(1 << 7) +#else +#define MG3_6_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_6PL) || (G3_9PL == 0) +#define MG3_6_19PL ~(1 << 8) +#else +#define MG3_6_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_6PL) || (G3_10PL == 0) +#define MG3_6_110PL ~(1 << 9) +#else +#define MG3_6_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_6PL) || (G3_11PL == 0) +#define MG3_6_111PL ~(1 << 10) +#else +#define MG3_6_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_6PL) || (G3_12PL == 0) +#define MG3_6_112PL ~(1 << 11) +#else +#define MG3_6_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_6PL) || (G3_13PL == 0) +#define MG3_6_113PL ~(1 << 12) +#else +#define MG3_6_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_6PL) || (G3_14PL == 0) +#define MG3_6_114PL ~(1 << 13) +#else +#define MG3_6_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_6PL) || (G3_15PL == 0) +#define MG3_6_115PL ~(1 << 14) +#else +#define MG3_6_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_6PL) || (G3_16PL == 0) +#define MG3_6_116PL ~(1 << 15) +#else +#define MG3_6_116PL 0xFFFF +#endif + +#define MG3_6_16PL 0xFFDF +#define MG3_6 (MG3_6_11PL & MG3_6_12PL & MG3_6_13PL & MG3_6_14PL & \ + MG3_6_15PL & MG3_6_16PL & MG3_6_17PL & MG3_6_18PL & \ + MG3_6_19PL & MG3_6_110PL & MG3_6_111PL & MG3_6_112PL & \ + MG3_6_113PL & MG3_6_114PL & MG3_6_115PL & MG3_6_116PL) +// End of MG3_6: +// Beginning of MG37: +#if (G3_1PL >= G3_7PL) || (G3_1PL == 0) +#define MG3_7_11PL ~(1 << 0) +#else +#define MG3_7_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_7PL) || (G3_2PL == 0) +#define MG3_7_12PL ~(1 << 1) +#else +#define MG3_7_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_7PL) || (G3_3PL == 0) +#define MG3_7_13PL ~(1 << 2) +#else +#define MG3_7_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_7PL) || (G3_4PL == 0) +#define MG3_7_14PL ~(1 << 3) +#else +#define MG3_7_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_7PL) || (G3_5PL == 0) +#define MG3_7_15PL ~(1 << 4) +#else +#define MG3_7_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_7PL) || (G3_6PL == 0) +#define MG3_7_16PL ~(1 << 5) +#else +#define MG3_7_16PL 0xFFFF +#endif + +#if (G3_8PL >= G3_7PL) || (G3_8PL == 0) +#define MG3_7_18PL ~(1 << 7) +#else +#define MG3_7_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_7PL) || (G3_9PL == 0) +#define MG3_7_19PL ~(1 << 8) +#else +#define MG3_7_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_7PL) || (G3_10PL == 0) +#define MG3_7_110PL ~(1 << 9) +#else +#define MG3_7_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_7PL) || (G3_11PL == 0) +#define MG3_7_111PL ~(1 << 10) +#else +#define MG3_7_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_7PL) || (G3_12PL == 0) +#define MG3_7_112PL ~(1 << 11) +#else +#define MG3_7_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_7PL) || (G3_13PL == 0) +#define MG3_7_113PL ~(1 << 12) +#else +#define MG3_7_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_7PL) || (G3_14PL == 0) +#define MG3_7_114PL ~(1 << 13) +#else +#define MG3_7_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_7PL) || (G3_15PL == 0) +#define MG3_7_115PL ~(1 << 14) +#else +#define MG3_7_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_7PL) || (G3_16PL == 0) +#define MG3_7_116PL ~(1 << 15) +#else +#define MG3_7_116PL 0xFFFF +#endif + +#define MG3_7_17PL 0xFFBF +#define MG3_7 (MG3_7_11PL & MG3_7_12PL & MG3_7_13PL & MG3_7_14PL & \ + MG3_7_15PL & MG3_7_16PL & MG3_7_17PL & MG3_7_18PL & \ + MG3_7_19PL & MG3_7_110PL & MG3_7_111PL & MG3_7_112PL & \ + MG3_7_113PL & MG3_7_114PL & MG3_7_115PL & MG3_7_116PL) +// End of MG3_7: +// Beginning of MG38: +#if (G3_1PL >= G3_8PL) || (G3_1PL == 0) +#define MG3_8_11PL ~(1 << 0) +#else +#define MG3_8_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_8PL) || (G3_2PL == 0) +#define MG3_8_12PL ~(1 << 1) +#else +#define MG3_8_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_8PL) || (G3_3PL == 0) +#define MG3_8_13PL ~(1 << 2) +#else +#define MG3_8_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_8PL) || (G3_4PL == 0) +#define MG3_8_14PL ~(1 << 3) +#else +#define MG3_8_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_8PL) || (G3_5PL == 0) +#define MG3_8_15PL ~(1 << 4) +#else +#define MG3_8_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_8PL) || (G3_6PL == 0) +#define MG3_8_16PL ~(1 << 5) +#else +#define MG3_8_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_8PL) || (G3_7PL == 0) +#define MG3_8_17PL ~(1 << 6) +#else +#define MG3_8_17PL 0xFFFF +#endif + +#if (G3_9PL >= G3_8PL) || (G3_9PL == 0) +#define MG3_8_19PL ~(1 << 8) +#else +#define MG3_8_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_8PL) || (G3_10PL == 0) +#define MG3_8_110PL ~(1 << 9) +#else +#define MG3_8_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_8PL) || (G3_11PL == 0) +#define MG3_8_111PL ~(1 << 10) +#else +#define MG3_8_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_8PL) || (G3_12PL == 0) +#define MG3_8_112PL ~(1 << 11) +#else +#define MG3_8_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_8PL) || (G3_13PL == 0) +#define MG3_8_113PL ~(1 << 12) +#else +#define MG3_8_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_8PL) || (G3_14PL == 0) +#define MG3_8_114PL ~(1 << 13) +#else +#define MG3_8_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_8PL) || (G3_15PL == 0) +#define MG3_8_115PL ~(1 << 14) +#else +#define MG3_8_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_8PL) || (G3_16PL == 0) +#define MG3_8_116PL ~(1 << 15) +#else +#define MG3_8_116PL 0xFFFF +#endif + +#define MG3_8_18PL 0xFF7F +#define MG3_8 (MG3_8_11PL & MG3_8_12PL & MG3_8_13PL & MG3_8_14PL & \ + MG3_8_15PL & MG3_8_16PL & MG3_8_17PL & MG3_8_18PL & \ + MG3_8_19PL & MG3_8_110PL & MG3_8_111PL & MG3_8_112PL & \ + MG3_8_113PL & MG3_8_114PL & MG3_8_115PL & MG3_8_116PL) +// End of MG3_8: +// Beginning of MG39: +#if (G3_1PL >= G3_9PL) || (G3_1PL == 0) +#define MG3_9_11PL ~(1 << 0) +#else +#define MG3_9_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_9PL) || (G3_2PL == 0) +#define MG3_9_12PL ~(1 << 1) +#else +#define MG3_9_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_9PL) || (G3_3PL == 0) +#define MG3_9_13PL ~(1 << 2) +#else +#define MG3_9_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_9PL) || (G3_4PL == 0) +#define MG3_9_14PL ~(1 << 3) +#else +#define MG3_9_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_9PL) || (G3_5PL == 0) +#define MG3_9_15PL ~(1 << 4) +#else +#define MG3_9_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_9PL) || (G3_6PL == 0) +#define MG3_9_16PL ~(1 << 5) +#else +#define MG3_9_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_9PL) || (G3_7PL == 0) +#define MG3_9_17PL ~(1 << 6) +#else +#define MG3_9_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_9PL) || (G3_8PL == 0) +#define MG3_9_18PL ~(1 << 7) +#else +#define MG3_9_18PL 0xFFFF +#endif + +#if (G3_10PL >= G3_9PL) || (G3_10PL == 0) +#define MG3_9_110PL ~(1 << 9) +#else +#define MG3_9_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_9PL) || (G3_11PL == 0) +#define MG3_9_111PL ~(1 << 10) +#else +#define MG3_9_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_9PL) || (G3_12PL == 0) +#define MG3_9_112PL ~(1 << 11) +#else +#define MG3_9_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_9PL) || (G3_13PL == 0) +#define MG3_9_113PL ~(1 << 12) +#else +#define MG3_9_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_9PL) || (G3_14PL == 0) +#define MG3_9_114PL ~(1 << 13) +#else +#define MG3_9_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_9PL) || (G3_15PL == 0) +#define MG3_9_115PL ~(1 << 14) +#else +#define MG3_9_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_9PL) || (G3_16PL == 0) +#define MG3_9_116PL ~(1 << 15) +#else +#define MG3_9_116PL 0xFFFF +#endif + +#define MG3_9_19PL 0xFEFF +#define MG3_9 (MG3_9_11PL & MG3_9_12PL & MG3_9_13PL & MG3_9_14PL & \ + MG3_9_15PL & MG3_9_16PL & MG3_9_17PL & MG3_9_18PL & \ + MG3_9_19PL & MG3_9_110PL & MG3_9_111PL & MG3_9_112PL & \ + MG3_9_113PL & MG3_9_114PL & MG3_9_115PL & MG3_9_116PL) +// End of MG3_9: +// Beginning of MG310: +#if (G3_1PL >= G3_10PL) || (G3_1PL == 0) +#define MG3_10_11PL ~(1 << 0) +#else +#define MG3_10_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_10PL) || (G3_2PL == 0) +#define MG3_10_12PL ~(1 << 1) +#else +#define MG3_10_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_10PL) || (G3_3PL == 0) +#define MG3_10_13PL ~(1 << 2) +#else +#define MG3_10_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_10PL) || (G3_4PL == 0) +#define MG3_10_14PL ~(1 << 3) +#else +#define MG3_10_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_10PL) || (G3_5PL == 0) +#define MG3_10_15PL ~(1 << 4) +#else +#define MG3_10_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_10PL) || (G3_6PL == 0) +#define MG3_10_16PL ~(1 << 5) +#else +#define MG3_10_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_10PL) || (G3_7PL == 0) +#define MG3_10_17PL ~(1 << 6) +#else +#define MG3_10_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_10PL) || (G3_8PL == 0) +#define MG3_10_18PL ~(1 << 7) +#else +#define MG3_10_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_10PL) || (G3_9PL == 0) +#define MG3_10_19PL ~(1 << 8) +#else +#define MG3_10_19PL 0xFFFF +#endif + +#if (G3_11PL >= G3_10PL) || (G3_11PL == 0) +#define MG3_10_111PL ~(1 << 10) +#else +#define MG3_10_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_10PL) || (G3_12PL == 0) +#define MG3_10_112PL ~(1 << 11) +#else +#define MG3_10_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_10PL) || (G3_13PL == 0) +#define MG3_10_113PL ~(1 << 12) +#else +#define MG3_10_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_10PL) || (G3_14PL == 0) +#define MG3_10_114PL ~(1 << 13) +#else +#define MG3_10_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_10PL) || (G3_15PL == 0) +#define MG3_10_115PL ~(1 << 14) +#else +#define MG3_10_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_10PL) || (G3_16PL == 0) +#define MG3_10_116PL ~(1 << 15) +#else +#define MG3_10_116PL 0xFFFF +#endif + +#define MG3_10_110PL 0xFDFF +#define MG3_10 (MG3_10_11PL & MG3_10_12PL & MG3_10_13PL & MG3_10_14PL & \ + MG3_10_15PL & MG3_10_16PL & MG3_10_17PL & MG3_10_18PL & \ + MG3_10_19PL & MG3_10_110PL & MG3_10_111PL & MG3_10_112PL & \ + MG3_10_113PL & MG3_10_114PL & MG3_10_115PL & MG3_10_116PL) +// End of MG3_10: +// Beginning of MG311: +#if (G3_1PL >= G3_11PL) || (G3_1PL == 0) +#define MG3_11_11PL ~(1 << 0) +#else +#define MG3_11_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_11PL) || (G3_2PL == 0) +#define MG3_11_12PL ~(1 << 1) +#else +#define MG3_11_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_11PL) || (G3_3PL == 0) +#define MG3_11_13PL ~(1 << 2) +#else +#define MG3_11_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_11PL) || (G3_4PL == 0) +#define MG3_11_14PL ~(1 << 3) +#else +#define MG3_11_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_11PL) || (G3_5PL == 0) +#define MG3_11_15PL ~(1 << 4) +#else +#define MG3_11_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_11PL) || (G3_6PL == 0) +#define MG3_11_16PL ~(1 << 5) +#else +#define MG3_11_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_11PL) || (G3_7PL == 0) +#define MG3_11_17PL ~(1 << 6) +#else +#define MG3_11_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_11PL) || (G3_8PL == 0) +#define MG3_11_18PL ~(1 << 7) +#else +#define MG3_11_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_11PL) || (G3_9PL == 0) +#define MG3_11_19PL ~(1 << 8) +#else +#define MG3_11_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_11PL) || (G3_10PL == 0) +#define MG3_11_110PL ~(1 << 9) +#else +#define MG3_11_110PL 0xFFFF +#endif + +#if (G3_12PL >= G3_11PL) || (G3_12PL == 0) +#define MG3_11_112PL ~(1 << 11) +#else +#define MG3_11_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_11PL) || (G3_13PL == 0) +#define MG3_11_113PL ~(1 << 12) +#else +#define MG3_11_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_11PL) || (G3_14PL == 0) +#define MG3_11_114PL ~(1 << 13) +#else +#define MG3_11_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_11PL) || (G3_15PL == 0) +#define MG3_11_115PL ~(1 << 14) +#else +#define MG3_11_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_11PL) || (G3_16PL == 0) +#define MG3_11_116PL ~(1 << 15) +#else +#define MG3_11_116PL 0xFFFF +#endif + +#define MG3_11_111PL 0xFBFF +#define MG3_11 (MG3_11_11PL & MG3_11_12PL & MG3_11_13PL & MG3_11_14PL & \ + MG3_11_15PL & MG3_11_16PL & MG3_11_17PL & MG3_11_18PL & \ + MG3_11_19PL & MG3_11_110PL & MG3_11_111PL & MG3_11_112PL & \ + MG3_11_113PL & MG3_11_114PL & MG3_11_115PL & MG3_11_116PL) +// End of MG3_11: +// Beginning of MG312: +#if (G3_1PL >= G3_12PL) || (G3_1PL == 0) +#define MG3_12_11PL ~(1 << 0) +#else +#define MG3_12_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_12PL) || (G3_2PL == 0) +#define MG3_12_12PL ~(1 << 1) +#else +#define MG3_12_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_12PL) || (G3_3PL == 0) +#define MG3_12_13PL ~(1 << 2) +#else +#define MG3_12_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_12PL) || (G3_4PL == 0) +#define MG3_12_14PL ~(1 << 3) +#else +#define MG3_12_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_12PL) || (G3_5PL == 0) +#define MG3_12_15PL ~(1 << 4) +#else +#define MG3_12_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_12PL) || (G3_6PL == 0) +#define MG3_12_16PL ~(1 << 5) +#else +#define MG3_12_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_12PL) || (G3_7PL == 0) +#define MG3_12_17PL ~(1 << 6) +#else +#define MG3_12_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_12PL) || (G3_8PL == 0) +#define MG3_12_18PL ~(1 << 7) +#else +#define MG3_12_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_12PL) || (G3_9PL == 0) +#define MG3_12_19PL ~(1 << 8) +#else +#define MG3_12_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_12PL) || (G3_10PL == 0) +#define MG3_12_110PL ~(1 << 9) +#else +#define MG3_12_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_12PL) || (G3_11PL == 0) +#define MG3_12_111PL ~(1 << 10) +#else +#define MG3_12_111PL 0xFFFF +#endif + +#if (G3_13PL >= G3_12PL) || (G3_13PL == 0) +#define MG3_12_113PL ~(1 << 12) +#else +#define MG3_12_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_12PL) || (G3_14PL == 0) +#define MG3_12_114PL ~(1 << 13) +#else +#define MG3_12_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_12PL) || (G3_15PL == 0) +#define MG3_12_115PL ~(1 << 14) +#else +#define MG3_12_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_12PL) || (G3_16PL == 0) +#define MG3_12_116PL ~(1 << 15) +#else +#define MG3_12_116PL 0xFFFF +#endif + +#define MG3_12_112PL 0xF7FF +#define MG3_12 (MG3_12_11PL & MG3_12_12PL & MG3_12_13PL & MG3_12_14PL & \ + MG3_12_15PL & MG3_12_16PL & MG3_12_17PL & MG3_12_18PL & \ + MG3_12_19PL & MG3_12_110PL & MG3_12_111PL & MG3_12_112PL & \ + MG3_12_113PL & MG3_12_114PL & MG3_12_115PL & MG3_12_116PL) +// End of MG3_12: +// Beginning of MG313: +#if (G3_1PL >= G3_13PL) || (G3_1PL == 0) +#define MG3_13_11PL ~(1 << 0) +#else +#define MG3_13_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_13PL) || (G3_2PL == 0) +#define MG3_13_12PL ~(1 << 1) +#else +#define MG3_13_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_13PL) || (G3_3PL == 0) +#define MG3_13_13PL ~(1 << 2) +#else +#define MG3_13_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_13PL) || (G3_4PL == 0) +#define MG3_13_14PL ~(1 << 3) +#else +#define MG3_13_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_13PL) || (G3_5PL == 0) +#define MG3_13_15PL ~(1 << 4) +#else +#define MG3_13_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_13PL) || (G3_6PL == 0) +#define MG3_13_16PL ~(1 << 5) +#else +#define MG3_13_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_13PL) || (G3_7PL == 0) +#define MG3_13_17PL ~(1 << 6) +#else +#define MG3_13_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_13PL) || (G3_8PL == 0) +#define MG3_13_18PL ~(1 << 7) +#else +#define MG3_13_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_13PL) || (G3_9PL == 0) +#define MG3_13_19PL ~(1 << 8) +#else +#define MG3_13_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_13PL) || (G3_10PL == 0) +#define MG3_13_110PL ~(1 << 9) +#else +#define MG3_13_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_13PL) || (G3_11PL == 0) +#define MG3_13_111PL ~(1 << 10) +#else +#define MG3_13_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_13PL) || (G3_12PL == 0) +#define MG3_13_112PL ~(1 << 11) +#else +#define MG3_13_112PL 0xFFFF +#endif + +#if (G3_14PL >= G3_13PL) || (G3_14PL == 0) +#define MG3_13_114PL ~(1 << 13) +#else +#define MG3_13_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_13PL) || (G3_15PL == 0) +#define MG3_13_115PL ~(1 << 14) +#else +#define MG3_13_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_13PL) || (G3_16PL == 0) +#define MG3_13_116PL ~(1 << 15) +#else +#define MG3_13_116PL 0xFFFF +#endif + +#define MG3_13_113PL 0xEFFF +#define MG3_13 (MG3_13_11PL & MG3_13_12PL & MG3_13_13PL & MG3_13_14PL & \ + MG3_13_15PL & MG3_13_16PL & MG3_13_17PL & MG3_13_18PL & \ + MG3_13_19PL & MG3_13_110PL & MG3_13_111PL & MG3_13_112PL & \ + MG3_13_113PL & MG3_13_114PL & MG3_13_115PL & MG3_13_116PL) +// End of MG3_13: +// Beginning of MG314: +#if (G3_1PL >= G3_14PL) || (G3_1PL == 0) +#define MG3_14_11PL ~(1 << 0) +#else +#define MG3_14_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_14PL) || (G3_2PL == 0) +#define MG3_14_12PL ~(1 << 1) +#else +#define MG3_14_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_14PL) || (G3_3PL == 0) +#define MG3_14_13PL ~(1 << 2) +#else +#define MG3_14_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_14PL) || (G3_4PL == 0) +#define MG3_14_14PL ~(1 << 3) +#else +#define MG3_14_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_14PL) || (G3_5PL == 0) +#define MG3_14_15PL ~(1 << 4) +#else +#define MG3_14_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_14PL) || (G3_6PL == 0) +#define MG3_14_16PL ~(1 << 5) +#else +#define MG3_14_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_14PL) || (G3_7PL == 0) +#define MG3_14_17PL ~(1 << 6) +#else +#define MG3_14_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_14PL) || (G3_8PL == 0) +#define MG3_14_18PL ~(1 << 7) +#else +#define MG3_14_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_14PL) || (G3_9PL == 0) +#define MG3_14_19PL ~(1 << 8) +#else +#define MG3_14_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_14PL) || (G3_10PL == 0) +#define MG3_14_110PL ~(1 << 9) +#else +#define MG3_14_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_14PL) || (G3_11PL == 0) +#define MG3_14_111PL ~(1 << 10) +#else +#define MG3_14_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_14PL) || (G3_12PL == 0) +#define MG3_14_112PL ~(1 << 11) +#else +#define MG3_14_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_14PL) || (G3_13PL == 0) +#define MG3_14_113PL ~(1 << 12) +#else +#define MG3_14_113PL 0xFFFF +#endif + +#if (G3_15PL >= G3_14PL) || (G3_15PL == 0) +#define MG3_14_115PL ~(1 << 14) +#else +#define MG3_14_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_14PL) || (G3_16PL == 0) +#define MG3_14_116PL ~(1 << 15) +#else +#define MG3_14_116PL 0xFFFF +#endif + +#define MG3_14_114PL 0xDFFF +#define MG3_14 (MG3_14_11PL & MG3_14_12PL & MG3_14_13PL & MG3_14_14PL & \ + MG3_14_15PL & MG3_14_16PL & MG3_14_17PL & MG3_14_18PL & \ + MG3_14_19PL & MG3_14_110PL & MG3_14_111PL & MG3_14_112PL & \ + MG3_14_113PL & MG3_14_114PL & MG3_14_115PL & MG3_14_116PL) +// End of MG3_14: +// Beginning of MG315: +#if (G3_1PL >= G3_15PL) || (G3_1PL == 0) +#define MG3_15_11PL ~(1 << 0) +#else +#define MG3_15_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_15PL) || (G3_2PL == 0) +#define MG3_15_12PL ~(1 << 1) +#else +#define MG3_15_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_15PL) || (G3_3PL == 0) +#define MG3_15_13PL ~(1 << 2) +#else +#define MG3_15_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_15PL) || (G3_4PL == 0) +#define MG3_15_14PL ~(1 << 3) +#else +#define MG3_15_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_15PL) || (G3_5PL == 0) +#define MG3_15_15PL ~(1 << 4) +#else +#define MG3_15_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_15PL) || (G3_6PL == 0) +#define MG3_15_16PL ~(1 << 5) +#else +#define MG3_15_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_15PL) || (G3_7PL == 0) +#define MG3_15_17PL ~(1 << 6) +#else +#define MG3_15_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_15PL) || (G3_8PL == 0) +#define MG3_15_18PL ~(1 << 7) +#else +#define MG3_15_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_15PL) || (G3_9PL == 0) +#define MG3_15_19PL ~(1 << 8) +#else +#define MG3_15_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_15PL) || (G3_10PL == 0) +#define MG3_15_110PL ~(1 << 9) +#else +#define MG3_15_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_15PL) || (G3_11PL == 0) +#define MG3_15_111PL ~(1 << 10) +#else +#define MG3_15_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_15PL) || (G3_12PL == 0) +#define MG3_15_112PL ~(1 << 11) +#else +#define MG3_15_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_15PL) || (G3_13PL == 0) +#define MG3_15_113PL ~(1 << 12) +#else +#define MG3_15_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_15PL) || (G3_14PL == 0) +#define MG3_15_114PL ~(1 << 13) +#else +#define MG3_15_114PL 0xFFFF +#endif + +#if (G3_16PL >= G3_15PL) || (G3_16PL == 0) +#define MG3_15_116PL ~(1 << 15) +#else +#define MG3_15_116PL 0xFFFF +#endif + +#define MG3_15_115PL 0xBFFF +#define MG3_15 (MG3_15_11PL & MG3_15_12PL & MG3_15_13PL & MG3_15_14PL & \ + MG3_15_15PL & MG3_15_16PL & MG3_15_17PL & MG3_15_18PL & \ + MG3_15_19PL & MG3_15_110PL & MG3_15_111PL & MG3_15_112PL & \ + MG3_15_113PL & MG3_15_114PL & MG3_15_115PL & MG3_15_116PL) +// End of MG3_15: +// Beginning of MG316: +#if (G3_1PL >= G3_16PL) || (G3_1PL == 0) +#define MG3_16_11PL ~(1 << 0) +#else +#define MG3_16_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_16PL) || (G3_2PL == 0) +#define MG3_16_12PL ~(1 << 1) +#else +#define MG3_16_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_16PL) || (G3_3PL == 0) +#define MG3_16_13PL ~(1 << 2) +#else +#define MG3_16_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_16PL) || (G3_4PL == 0) +#define MG3_16_14PL ~(1 << 3) +#else +#define MG3_16_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_16PL) || (G3_5PL == 0) +#define MG3_16_15PL ~(1 << 4) +#else +#define MG3_16_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_16PL) || (G3_6PL == 0) +#define MG3_16_16PL ~(1 << 5) +#else +#define MG3_16_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_16PL) || (G3_7PL == 0) +#define MG3_16_17PL ~(1 << 6) +#else +#define MG3_16_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_16PL) || (G3_8PL == 0) +#define MG3_16_18PL ~(1 << 7) +#else +#define MG3_16_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_16PL) || (G3_9PL == 0) +#define MG3_16_19PL ~(1 << 8) +#else +#define MG3_16_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_16PL) || (G3_10PL == 0) +#define MG3_16_110PL ~(1 << 9) +#else +#define MG3_16_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_16PL) || (G3_11PL == 0) +#define MG3_16_111PL ~(1 << 10) +#else +#define MG3_16_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_16PL) || (G3_12PL == 0) +#define MG3_16_112PL ~(1 << 11) +#else +#define MG3_16_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_16PL) || (G3_13PL == 0) +#define MG3_16_113PL ~(1 << 12) +#else +#define MG3_16_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_16PL) || (G3_14PL == 0) +#define MG3_16_114PL ~(1 << 13) +#else +#define MG3_16_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_16PL) || (G3_15PL == 0) +#define MG3_16_115PL ~(1 << 14) +#else +#define MG3_16_115PL 0xFFFF +#endif + +#define MG3_16_116PL 0x7FFF +#define MG3_16 (MG3_16_11PL & MG3_16_12PL & MG3_16_13PL & MG3_16_14PL & \ + MG3_16_15PL & MG3_16_16PL & MG3_16_17PL & MG3_16_18PL & \ + MG3_16_19PL & MG3_16_110PL & MG3_16_111PL & MG3_16_112PL & \ + MG3_16_113PL & MG3_16_114PL & MG3_16_115PL & MG3_16_116PL) +// End of MG3_16: + + +// +// Automatically generate PIEIER4 interrupt masks MG41 to MG416: +// + +// Beginning of MG41: +#if (G4_2PL >= G4_1PL) || (G4_2PL == 0) +#define MG4_1_12PL ~(1 << 1) +#else +#define MG4_1_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_1PL) || (G4_3PL == 0) +#define MG4_1_13PL ~(1 << 2) +#else +#define MG4_1_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_1PL) || (G4_4PL == 0) +#define MG4_1_14PL ~(1 << 3) +#else +#define MG4_1_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_1PL) || (G4_5PL == 0) +#define MG4_1_15PL ~(1 << 4) +#else +#define MG4_1_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_1PL) || (G4_6PL == 0) +#define MG4_1_16PL ~(1 << 5) +#else +#define MG4_1_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_1PL) || (G4_7PL == 0) +#define MG4_1_17PL ~(1 << 6) +#else +#define MG4_1_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_1PL) || (G4_8PL == 0) +#define MG4_1_18PL ~(1 << 7) +#else +#define MG4_1_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_1PL) || (G4_9PL == 0) +#define MG4_1_19PL ~(1 << 8) +#else +#define MG4_1_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_1PL) || (G4_10PL == 0) +#define MG4_1_110PL ~(1 << 9) +#else +#define MG4_1_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_1PL) || (G4_11PL == 0) +#define MG4_1_111PL ~(1 << 10) +#else +#define MG4_1_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_1PL) || (G4_12PL == 0) +#define MG4_1_112PL ~(1 << 11) +#else +#define MG4_1_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_1PL) || (G4_13PL == 0) +#define MG4_1_113PL ~(1 << 12) +#else +#define MG4_1_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_1PL) || (G4_14PL == 0) +#define MG4_1_114PL ~(1 << 13) +#else +#define MG4_1_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_1PL) || (G4_15PL == 0) +#define MG4_1_115PL ~(1 << 14) +#else +#define MG4_1_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_1PL) || (G4_16PL == 0) +#define MG4_1_116PL ~(1 << 15) +#else +#define MG4_1_116PL 0xFFFF +#endif + +#define MG4_1_11PL 0xFFFE +#define MG4_1 (MG4_1_11PL & MG4_1_12PL & MG4_1_13PL & MG4_1_14PL & \ + MG4_1_15PL & MG4_1_16PL & MG4_1_17PL & MG4_1_18PL & \ + MG4_1_19PL & MG4_1_110PL & MG4_1_111PL & MG4_1_112PL & \ + MG4_1_113PL & MG4_1_114PL & MG4_1_115PL & MG4_1_116PL) +// End of MG4_1: +// Beginning of MG42: +#if (G4_1PL >= G4_2PL) || (G4_1PL == 0) +#define MG4_2_11PL ~(1 << 0) +#else +#define MG4_2_11PL 0xFFFF +#endif + +#if (G4_3PL >= G4_2PL) || (G4_3PL == 0) +#define MG4_2_13PL ~(1 << 2) +#else +#define MG4_2_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_2PL) || (G4_4PL == 0) +#define MG4_2_14PL ~(1 << 3) +#else +#define MG4_2_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_2PL) || (G4_5PL == 0) +#define MG4_2_15PL ~(1 << 4) +#else +#define MG4_2_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_2PL) || (G4_6PL == 0) +#define MG4_2_16PL ~(1 << 5) +#else +#define MG4_2_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_2PL) || (G4_7PL == 0) +#define MG4_2_17PL ~(1 << 6) +#else +#define MG4_2_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_2PL) || (G4_8PL == 0) +#define MG4_2_18PL ~(1 << 7) +#else +#define MG4_2_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_2PL) || (G4_9PL == 0) +#define MG4_2_19PL ~(1 << 8) +#else +#define MG4_2_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_2PL) || (G4_10PL == 0) +#define MG4_2_110PL ~(1 << 9) +#else +#define MG4_2_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_2PL) || (G4_11PL == 0) +#define MG4_2_111PL ~(1 << 10) +#else +#define MG4_2_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_2PL) || (G4_12PL == 0) +#define MG4_2_112PL ~(1 << 11) +#else +#define MG4_2_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_2PL) || (G4_13PL == 0) +#define MG4_2_113PL ~(1 << 12) +#else +#define MG4_2_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_2PL) || (G4_14PL == 0) +#define MG4_2_114PL ~(1 << 13) +#else +#define MG4_2_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_2PL) || (G4_15PL == 0) +#define MG4_2_115PL ~(1 << 14) +#else +#define MG4_2_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_2PL) || (G4_16PL == 0) +#define MG4_2_116PL ~(1 << 15) +#else +#define MG4_2_116PL 0xFFFF +#endif + +#define MG4_2_12PL 0xFFFD +#define MG4_2 (MG4_2_11PL & MG4_2_12PL & MG4_2_13PL & MG4_2_14PL & \ + MG4_2_15PL & MG4_2_16PL & MG4_2_17PL & MG4_2_18PL & \ + MG4_2_19PL & MG4_2_110PL & MG4_2_111PL & MG4_2_112PL & \ + MG4_2_113PL & MG4_2_114PL & MG4_2_115PL & MG4_2_116PL) +// End of MG4_2: +// Beginning of MG43: +#if (G4_1PL >= G4_3PL) || (G4_1PL == 0) +#define MG4_3_11PL ~(1 << 0) +#else +#define MG4_3_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_3PL) || (G4_2PL == 0) +#define MG4_3_12PL ~(1 << 1) +#else +#define MG4_3_12PL 0xFFFF +#endif + +#if (G4_4PL >= G4_3PL) || (G4_4PL == 0) +#define MG4_3_14PL ~(1 << 3) +#else +#define MG4_3_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_3PL) || (G4_5PL == 0) +#define MG4_3_15PL ~(1 << 4) +#else +#define MG4_3_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_3PL) || (G4_6PL == 0) +#define MG4_3_16PL ~(1 << 5) +#else +#define MG4_3_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_3PL) || (G4_7PL == 0) +#define MG4_3_17PL ~(1 << 6) +#else +#define MG4_3_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_3PL) || (G4_8PL == 0) +#define MG4_3_18PL ~(1 << 7) +#else +#define MG4_3_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_3PL) || (G4_9PL == 0) +#define MG4_3_19PL ~(1 << 8) +#else +#define MG4_3_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_3PL) || (G4_10PL == 0) +#define MG4_3_110PL ~(1 << 9) +#else +#define MG4_3_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_3PL) || (G4_11PL == 0) +#define MG4_3_111PL ~(1 << 10) +#else +#define MG4_3_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_3PL) || (G4_12PL == 0) +#define MG4_3_112PL ~(1 << 11) +#else +#define MG4_3_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_3PL) || (G4_13PL == 0) +#define MG4_3_113PL ~(1 << 12) +#else +#define MG4_3_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_3PL) || (G4_14PL == 0) +#define MG4_3_114PL ~(1 << 13) +#else +#define MG4_3_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_3PL) || (G4_15PL == 0) +#define MG4_3_115PL ~(1 << 14) +#else +#define MG4_3_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_3PL) || (G4_16PL == 0) +#define MG4_3_116PL ~(1 << 15) +#else +#define MG4_3_116PL 0xFFFF +#endif + +#define MG4_3_13PL 0xFFFB +#define MG4_3 (MG4_3_11PL & MG4_3_12PL & MG4_3_13PL & MG4_3_14PL & \ + MG4_3_15PL & MG4_3_16PL & MG4_3_17PL & MG4_3_18PL & \ + MG4_3_19PL & MG4_3_110PL & MG4_3_111PL & MG4_3_112PL & \ + MG4_3_113PL & MG4_3_114PL & MG4_3_115PL & MG4_3_116PL) +// End of MG4_3: +// Beginning of MG44: +#if (G4_1PL >= G4_4PL) || (G4_1PL == 0) +#define MG4_4_11PL ~(1 << 0) +#else +#define MG4_4_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_4PL) || (G4_2PL == 0) +#define MG4_4_12PL ~(1 << 1) +#else +#define MG4_4_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_4PL) || (G4_3PL == 0) +#define MG4_4_13PL ~(1 << 2) +#else +#define MG4_4_13PL 0xFFFF +#endif + +#if (G4_5PL >= G4_4PL) || (G4_5PL == 0) +#define MG4_4_15PL ~(1 << 4) +#else +#define MG4_4_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_4PL) || (G4_6PL == 0) +#define MG4_4_16PL ~(1 << 5) +#else +#define MG4_4_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_4PL) || (G4_7PL == 0) +#define MG4_4_17PL ~(1 << 6) +#else +#define MG4_4_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_4PL) || (G4_8PL == 0) +#define MG4_4_18PL ~(1 << 7) +#else +#define MG4_4_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_4PL) || (G4_9PL == 0) +#define MG4_4_19PL ~(1 << 8) +#else +#define MG4_4_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_4PL) || (G4_10PL == 0) +#define MG4_4_110PL ~(1 << 9) +#else +#define MG4_4_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_4PL) || (G4_11PL == 0) +#define MG4_4_111PL ~(1 << 10) +#else +#define MG4_4_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_4PL) || (G4_12PL == 0) +#define MG4_4_112PL ~(1 << 11) +#else +#define MG4_4_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_4PL) || (G4_13PL == 0) +#define MG4_4_113PL ~(1 << 12) +#else +#define MG4_4_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_4PL) || (G4_14PL == 0) +#define MG4_4_114PL ~(1 << 13) +#else +#define MG4_4_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_4PL) || (G4_15PL == 0) +#define MG4_4_115PL ~(1 << 14) +#else +#define MG4_4_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_4PL) || (G4_16PL == 0) +#define MG4_4_116PL ~(1 << 15) +#else +#define MG4_4_116PL 0xFFFF +#endif + +#define MG4_4_14PL 0xFFF7 +#define MG4_4 (MG4_4_11PL & MG4_4_12PL & MG4_4_13PL & MG4_4_14PL & \ + MG4_4_15PL & MG4_4_16PL & MG4_4_17PL & MG4_4_18PL & \ + MG4_4_19PL & MG4_4_110PL & MG4_4_111PL & MG4_4_112PL & \ + MG4_4_113PL & MG4_4_114PL & MG4_4_115PL & MG4_4_116PL) +// End of MG4_4: +// Beginning of MG45: +#if (G4_1PL >= G4_5PL) || (G4_1PL == 0) +#define MG4_5_11PL ~(1 << 0) +#else +#define MG4_5_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_5PL) || (G4_2PL == 0) +#define MG4_5_12PL ~(1 << 1) +#else +#define MG4_5_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_5PL) || (G4_3PL == 0) +#define MG4_5_13PL ~(1 << 2) +#else +#define MG4_5_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_5PL) || (G4_4PL == 0) +#define MG4_5_14PL ~(1 << 3) +#else +#define MG4_5_14PL 0xFFFF +#endif + +#if (G4_6PL >= G4_5PL) || (G4_6PL == 0) +#define MG4_5_16PL ~(1 << 5) +#else +#define MG4_5_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_5PL) || (G4_7PL == 0) +#define MG4_5_17PL ~(1 << 6) +#else +#define MG4_5_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_5PL) || (G4_8PL == 0) +#define MG4_5_18PL ~(1 << 7) +#else +#define MG4_5_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_5PL) || (G4_9PL == 0) +#define MG4_5_19PL ~(1 << 8) +#else +#define MG4_5_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_5PL) || (G4_10PL == 0) +#define MG4_5_110PL ~(1 << 9) +#else +#define MG4_5_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_5PL) || (G4_11PL == 0) +#define MG4_5_111PL ~(1 << 10) +#else +#define MG4_5_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_5PL) || (G4_12PL == 0) +#define MG4_5_112PL ~(1 << 11) +#else +#define MG4_5_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_5PL) || (G4_13PL == 0) +#define MG4_5_113PL ~(1 << 12) +#else +#define MG4_5_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_5PL) || (G4_14PL == 0) +#define MG4_5_114PL ~(1 << 13) +#else +#define MG4_5_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_5PL) || (G4_15PL == 0) +#define MG4_5_115PL ~(1 << 14) +#else +#define MG4_5_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_5PL) || (G4_16PL == 0) +#define MG4_5_116PL ~(1 << 15) +#else +#define MG4_5_116PL 0xFFFF +#endif + +#define MG4_5_15PL 0xFFEF +#define MG4_5 (MG4_5_11PL & MG4_5_12PL & MG4_5_13PL & MG4_5_14PL & \ + MG4_5_15PL & MG4_5_16PL & MG4_5_17PL & MG4_5_18PL & \ + MG4_5_19PL & MG4_5_110PL & MG4_5_111PL & MG4_5_112PL & \ + MG4_5_113PL & MG4_5_114PL & MG4_5_115PL & MG4_5_116PL) +// End of MG4_5: +// Beginning of MG46: +#if (G4_1PL >= G4_6PL) || (G4_1PL == 0) +#define MG4_6_11PL ~(1 << 0) +#else +#define MG4_6_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_6PL) || (G4_2PL == 0) +#define MG4_6_12PL ~(1 << 1) +#else +#define MG4_6_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_6PL) || (G4_3PL == 0) +#define MG4_6_13PL ~(1 << 2) +#else +#define MG4_6_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_6PL) || (G4_4PL == 0) +#define MG4_6_14PL ~(1 << 3) +#else +#define MG4_6_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_6PL) || (G4_5PL == 0) +#define MG4_6_15PL ~(1 << 4) +#else +#define MG4_6_15PL 0xFFFF +#endif + +#if (G4_7PL >= G4_6PL) || (G4_7PL == 0) +#define MG4_6_17PL ~(1 << 6) +#else +#define MG4_6_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_6PL) || (G4_8PL == 0) +#define MG4_6_18PL ~(1 << 7) +#else +#define MG4_6_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_6PL) || (G4_9PL == 0) +#define MG4_6_19PL ~(1 << 8) +#else +#define MG4_6_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_6PL) || (G4_10PL == 0) +#define MG4_6_110PL ~(1 << 9) +#else +#define MG4_6_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_6PL) || (G4_11PL == 0) +#define MG4_6_111PL ~(1 << 10) +#else +#define MG4_6_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_6PL) || (G4_12PL == 0) +#define MG4_6_112PL ~(1 << 11) +#else +#define MG4_6_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_6PL) || (G4_13PL == 0) +#define MG4_6_113PL ~(1 << 12) +#else +#define MG4_6_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_6PL) || (G4_14PL == 0) +#define MG4_6_114PL ~(1 << 13) +#else +#define MG4_6_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_6PL) || (G4_15PL == 0) +#define MG4_6_115PL ~(1 << 14) +#else +#define MG4_6_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_6PL) || (G4_16PL == 0) +#define MG4_6_116PL ~(1 << 15) +#else +#define MG4_6_116PL 0xFFFF +#endif + +#define MG4_6_16PL 0xFFDF +#define MG4_6 (MG4_6_11PL & MG4_6_12PL & MG4_6_13PL & MG4_6_14PL & \ + MG4_6_15PL & MG4_6_16PL & MG4_6_17PL & MG4_6_18PL & \ + MG4_6_19PL & MG4_6_110PL & MG4_6_111PL & MG4_6_112PL & \ + MG4_6_113PL & MG4_6_114PL & MG4_6_115PL & MG4_6_116PL) +// End of MG4_6: +// Beginning of MG47: +#if (G4_1PL >= G4_7PL) || (G4_1PL == 0) +#define MG4_7_11PL ~(1 << 0) +#else +#define MG4_7_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_7PL) || (G4_2PL == 0) +#define MG4_7_12PL ~(1 << 1) +#else +#define MG4_7_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_7PL) || (G4_3PL == 0) +#define MG4_7_13PL ~(1 << 2) +#else +#define MG4_7_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_7PL) || (G4_4PL == 0) +#define MG4_7_14PL ~(1 << 3) +#else +#define MG4_7_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_7PL) || (G4_5PL == 0) +#define MG4_7_15PL ~(1 << 4) +#else +#define MG4_7_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_7PL) || (G4_6PL == 0) +#define MG4_7_16PL ~(1 << 5) +#else +#define MG4_7_16PL 0xFFFF +#endif + +#if (G4_8PL >= G4_7PL) || (G4_8PL == 0) +#define MG4_7_18PL ~(1 << 7) +#else +#define MG4_7_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_7PL) || (G4_9PL == 0) +#define MG4_7_19PL ~(1 << 8) +#else +#define MG4_7_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_7PL) || (G4_10PL == 0) +#define MG4_7_110PL ~(1 << 9) +#else +#define MG4_7_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_7PL) || (G4_11PL == 0) +#define MG4_7_111PL ~(1 << 10) +#else +#define MG4_7_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_7PL) || (G4_12PL == 0) +#define MG4_7_112PL ~(1 << 11) +#else +#define MG4_7_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_7PL) || (G4_13PL == 0) +#define MG4_7_113PL ~(1 << 12) +#else +#define MG4_7_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_7PL) || (G4_14PL == 0) +#define MG4_7_114PL ~(1 << 13) +#else +#define MG4_7_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_7PL) || (G4_15PL == 0) +#define MG4_7_115PL ~(1 << 14) +#else +#define MG4_7_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_7PL) || (G4_16PL == 0) +#define MG4_7_116PL ~(1 << 15) +#else +#define MG4_7_116PL 0xFFFF +#endif + +#define MG4_7_17PL 0xFFBF +#define MG4_7 (MG4_7_11PL & MG4_7_12PL & MG4_7_13PL & MG4_7_14PL & \ + MG4_7_15PL & MG4_7_16PL & MG4_7_17PL & MG4_7_18PL & \ + MG4_7_19PL & MG4_7_110PL & MG4_7_111PL & MG4_7_112PL & \ + MG4_7_113PL & MG4_7_114PL & MG4_7_115PL & MG4_7_116PL) +// End of MG4_7: +// Beginning of MG48: +#if (G4_1PL >= G4_8PL) || (G4_1PL == 0) +#define MG4_8_11PL ~(1 << 0) +#else +#define MG4_8_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_8PL) || (G4_2PL == 0) +#define MG4_8_12PL ~(1 << 1) +#else +#define MG4_8_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_8PL) || (G4_3PL == 0) +#define MG4_8_13PL ~(1 << 2) +#else +#define MG4_8_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_8PL) || (G4_4PL == 0) +#define MG4_8_14PL ~(1 << 3) +#else +#define MG4_8_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_8PL) || (G4_5PL == 0) +#define MG4_8_15PL ~(1 << 4) +#else +#define MG4_8_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_8PL) || (G4_6PL == 0) +#define MG4_8_16PL ~(1 << 5) +#else +#define MG4_8_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_8PL) || (G4_7PL == 0) +#define MG4_8_17PL ~(1 << 6) +#else +#define MG4_8_17PL 0xFFFF +#endif + +#if (G4_9PL >= G4_8PL) || (G4_9PL == 0) +#define MG4_8_19PL ~(1 << 8) +#else +#define MG4_8_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_8PL) || (G4_10PL == 0) +#define MG4_8_110PL ~(1 << 9) +#else +#define MG4_8_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_8PL) || (G4_11PL == 0) +#define MG4_8_111PL ~(1 << 10) +#else +#define MG4_8_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_8PL) || (G4_12PL == 0) +#define MG4_8_112PL ~(1 << 11) +#else +#define MG4_8_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_8PL) || (G4_13PL == 0) +#define MG4_8_113PL ~(1 << 12) +#else +#define MG4_8_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_8PL) || (G4_14PL == 0) +#define MG4_8_114PL ~(1 << 13) +#else +#define MG4_8_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_8PL) || (G4_15PL == 0) +#define MG4_8_115PL ~(1 << 14) +#else +#define MG4_8_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_8PL) || (G4_16PL == 0) +#define MG4_8_116PL ~(1 << 15) +#else +#define MG4_8_116PL 0xFFFF +#endif + +#define MG4_8_18PL 0xFF7F +#define MG4_8 (MG4_8_11PL & MG4_8_12PL & MG4_8_13PL & MG4_8_14PL & \ + MG4_8_15PL & MG4_8_16PL & MG4_8_17PL & MG4_8_18PL & \ + MG4_8_19PL & MG4_8_110PL & MG4_8_111PL & MG4_8_112PL & \ + MG4_8_113PL & MG4_8_114PL & MG4_8_115PL & MG4_8_116PL) +// End of MG4_8: +// Beginning of MG49: +#if (G4_1PL >= G4_9PL) || (G4_1PL == 0) +#define MG4_9_11PL ~(1 << 0) +#else +#define MG4_9_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_9PL) || (G4_2PL == 0) +#define MG4_9_12PL ~(1 << 1) +#else +#define MG4_9_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_9PL) || (G4_3PL == 0) +#define MG4_9_13PL ~(1 << 2) +#else +#define MG4_9_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_9PL) || (G4_4PL == 0) +#define MG4_9_14PL ~(1 << 3) +#else +#define MG4_9_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_9PL) || (G4_5PL == 0) +#define MG4_9_15PL ~(1 << 4) +#else +#define MG4_9_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_9PL) || (G4_6PL == 0) +#define MG4_9_16PL ~(1 << 5) +#else +#define MG4_9_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_9PL) || (G4_7PL == 0) +#define MG4_9_17PL ~(1 << 6) +#else +#define MG4_9_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_9PL) || (G4_8PL == 0) +#define MG4_9_18PL ~(1 << 7) +#else +#define MG4_9_18PL 0xFFFF +#endif + +#if (G4_10PL >= G4_9PL) || (G4_10PL == 0) +#define MG4_9_110PL ~(1 << 9) +#else +#define MG4_9_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_9PL) || (G4_11PL == 0) +#define MG4_9_111PL ~(1 << 10) +#else +#define MG4_9_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_9PL) || (G4_12PL == 0) +#define MG4_9_112PL ~(1 << 11) +#else +#define MG4_9_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_9PL) || (G4_13PL == 0) +#define MG4_9_113PL ~(1 << 12) +#else +#define MG4_9_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_9PL) || (G4_14PL == 0) +#define MG4_9_114PL ~(1 << 13) +#else +#define MG4_9_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_9PL) || (G4_15PL == 0) +#define MG4_9_115PL ~(1 << 14) +#else +#define MG4_9_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_9PL) || (G4_16PL == 0) +#define MG4_9_116PL ~(1 << 15) +#else +#define MG4_9_116PL 0xFFFF +#endif + +#define MG4_9_19PL 0xFEFF +#define MG4_9 (MG4_9_11PL & MG4_9_12PL & MG4_9_13PL & MG4_9_14PL & \ + MG4_9_15PL & MG4_9_16PL & MG4_9_17PL & MG4_9_18PL & \ + MG4_9_19PL & MG4_9_110PL & MG4_9_111PL & MG4_9_112PL & \ + MG4_9_113PL & MG4_9_114PL & MG4_9_115PL & MG4_9_116PL) +// End of MG4_9: +// Beginning of MG410: +#if (G4_1PL >= G4_10PL) || (G4_1PL == 0) +#define MG4_10_11PL ~(1 << 0) +#else +#define MG4_10_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_10PL) || (G4_2PL == 0) +#define MG4_10_12PL ~(1 << 1) +#else +#define MG4_10_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_10PL) || (G4_3PL == 0) +#define MG4_10_13PL ~(1 << 2) +#else +#define MG4_10_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_10PL) || (G4_4PL == 0) +#define MG4_10_14PL ~(1 << 3) +#else +#define MG4_10_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_10PL) || (G4_5PL == 0) +#define MG4_10_15PL ~(1 << 4) +#else +#define MG4_10_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_10PL) || (G4_6PL == 0) +#define MG4_10_16PL ~(1 << 5) +#else +#define MG4_10_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_10PL) || (G4_7PL == 0) +#define MG4_10_17PL ~(1 << 6) +#else +#define MG4_10_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_10PL) || (G4_8PL == 0) +#define MG4_10_18PL ~(1 << 7) +#else +#define MG4_10_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_10PL) || (G4_9PL == 0) +#define MG4_10_19PL ~(1 << 8) +#else +#define MG4_10_19PL 0xFFFF +#endif + +#if (G4_11PL >= G4_10PL) || (G4_11PL == 0) +#define MG4_10_111PL ~(1 << 10) +#else +#define MG4_10_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_10PL) || (G4_12PL == 0) +#define MG4_10_112PL ~(1 << 11) +#else +#define MG4_10_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_10PL) || (G4_13PL == 0) +#define MG4_10_113PL ~(1 << 12) +#else +#define MG4_10_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_10PL) || (G4_14PL == 0) +#define MG4_10_114PL ~(1 << 13) +#else +#define MG4_10_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_10PL) || (G4_15PL == 0) +#define MG4_10_115PL ~(1 << 14) +#else +#define MG4_10_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_10PL) || (G4_16PL == 0) +#define MG4_10_116PL ~(1 << 15) +#else +#define MG4_10_116PL 0xFFFF +#endif + +#define MG4_10_110PL 0xFDFF +#define MG4_10 (MG4_10_11PL & MG4_10_12PL & MG4_10_13PL & MG4_10_14PL & \ + MG4_10_15PL & MG4_10_16PL & MG4_10_17PL & MG4_10_18PL & \ + MG4_10_19PL & MG4_10_110PL & MG4_10_111PL & MG4_10_112PL & \ + MG4_10_113PL & MG4_10_114PL & MG4_10_115PL & MG4_10_116PL) +// End of MG4_10: +// Beginning of MG411: +#if (G4_1PL >= G4_11PL) || (G4_1PL == 0) +#define MG4_11_11PL ~(1 << 0) +#else +#define MG4_11_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_11PL) || (G4_2PL == 0) +#define MG4_11_12PL ~(1 << 1) +#else +#define MG4_11_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_11PL) || (G4_3PL == 0) +#define MG4_11_13PL ~(1 << 2) +#else +#define MG4_11_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_11PL) || (G4_4PL == 0) +#define MG4_11_14PL ~(1 << 3) +#else +#define MG4_11_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_11PL) || (G4_5PL == 0) +#define MG4_11_15PL ~(1 << 4) +#else +#define MG4_11_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_11PL) || (G4_6PL == 0) +#define MG4_11_16PL ~(1 << 5) +#else +#define MG4_11_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_11PL) || (G4_7PL == 0) +#define MG4_11_17PL ~(1 << 6) +#else +#define MG4_11_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_11PL) || (G4_8PL == 0) +#define MG4_11_18PL ~(1 << 7) +#else +#define MG4_11_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_11PL) || (G4_9PL == 0) +#define MG4_11_19PL ~(1 << 8) +#else +#define MG4_11_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_11PL) || (G4_10PL == 0) +#define MG4_11_110PL ~(1 << 9) +#else +#define MG4_11_110PL 0xFFFF +#endif + +#if (G4_12PL >= G4_11PL) || (G4_12PL == 0) +#define MG4_11_112PL ~(1 << 11) +#else +#define MG4_11_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_11PL) || (G4_13PL == 0) +#define MG4_11_113PL ~(1 << 12) +#else +#define MG4_11_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_11PL) || (G4_14PL == 0) +#define MG4_11_114PL ~(1 << 13) +#else +#define MG4_11_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_11PL) || (G4_15PL == 0) +#define MG4_11_115PL ~(1 << 14) +#else +#define MG4_11_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_11PL) || (G4_16PL == 0) +#define MG4_11_116PL ~(1 << 15) +#else +#define MG4_11_116PL 0xFFFF +#endif + +#define MG4_11_111PL 0xFBFF +#define MG4_11 (MG4_11_11PL & MG4_11_12PL & MG4_11_13PL & MG4_11_14PL & \ + MG4_11_15PL & MG4_11_16PL & MG4_11_17PL & MG4_11_18PL & \ + MG4_11_19PL & MG4_11_110PL & MG4_11_111PL & MG4_11_112PL & \ + MG4_11_113PL & MG4_11_114PL & MG4_11_115PL & MG4_11_116PL) +// End of MG4_11: +// Beginning of MG412: +#if (G4_1PL >= G4_12PL) || (G4_1PL == 0) +#define MG4_12_11PL ~(1 << 0) +#else +#define MG4_12_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_12PL) || (G4_2PL == 0) +#define MG4_12_12PL ~(1 << 1) +#else +#define MG4_12_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_12PL) || (G4_3PL == 0) +#define MG4_12_13PL ~(1 << 2) +#else +#define MG4_12_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_12PL) || (G4_4PL == 0) +#define MG4_12_14PL ~(1 << 3) +#else +#define MG4_12_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_12PL) || (G4_5PL == 0) +#define MG4_12_15PL ~(1 << 4) +#else +#define MG4_12_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_12PL) || (G4_6PL == 0) +#define MG4_12_16PL ~(1 << 5) +#else +#define MG4_12_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_12PL) || (G4_7PL == 0) +#define MG4_12_17PL ~(1 << 6) +#else +#define MG4_12_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_12PL) || (G4_8PL == 0) +#define MG4_12_18PL ~(1 << 7) +#else +#define MG4_12_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_12PL) || (G4_9PL == 0) +#define MG4_12_19PL ~(1 << 8) +#else +#define MG4_12_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_12PL) || (G4_10PL == 0) +#define MG4_12_110PL ~(1 << 9) +#else +#define MG4_12_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_12PL) || (G4_11PL == 0) +#define MG4_12_111PL ~(1 << 10) +#else +#define MG4_12_111PL 0xFFFF +#endif + +#if (G4_13PL >= G4_12PL) || (G4_13PL == 0) +#define MG4_12_113PL ~(1 << 12) +#else +#define MG4_12_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_12PL) || (G4_14PL == 0) +#define MG4_12_114PL ~(1 << 13) +#else +#define MG4_12_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_12PL) || (G4_15PL == 0) +#define MG4_12_115PL ~(1 << 14) +#else +#define MG4_12_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_12PL) || (G4_16PL == 0) +#define MG4_12_116PL ~(1 << 15) +#else +#define MG4_12_116PL 0xFFFF +#endif + +#define MG4_12_112PL 0xF7FF +#define MG4_12 (MG4_12_11PL & MG4_12_12PL & MG4_12_13PL & MG4_12_14PL & \ + MG4_12_15PL & MG4_12_16PL & MG4_12_17PL & MG4_12_18PL & \ + MG4_12_19PL & MG4_12_110PL & MG4_12_111PL & MG4_12_112PL & \ + MG4_12_113PL & MG4_12_114PL & MG4_12_115PL & MG4_12_116PL) +// End of MG4_12: +// Beginning of MG413: +#if (G4_1PL >= G4_13PL) || (G4_1PL == 0) +#define MG4_13_11PL ~(1 << 0) +#else +#define MG4_13_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_13PL) || (G4_2PL == 0) +#define MG4_13_12PL ~(1 << 1) +#else +#define MG4_13_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_13PL) || (G4_3PL == 0) +#define MG4_13_13PL ~(1 << 2) +#else +#define MG4_13_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_13PL) || (G4_4PL == 0) +#define MG4_13_14PL ~(1 << 3) +#else +#define MG4_13_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_13PL) || (G4_5PL == 0) +#define MG4_13_15PL ~(1 << 4) +#else +#define MG4_13_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_13PL) || (G4_6PL == 0) +#define MG4_13_16PL ~(1 << 5) +#else +#define MG4_13_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_13PL) || (G4_7PL == 0) +#define MG4_13_17PL ~(1 << 6) +#else +#define MG4_13_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_13PL) || (G4_8PL == 0) +#define MG4_13_18PL ~(1 << 7) +#else +#define MG4_13_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_13PL) || (G4_9PL == 0) +#define MG4_13_19PL ~(1 << 8) +#else +#define MG4_13_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_13PL) || (G4_10PL == 0) +#define MG4_13_110PL ~(1 << 9) +#else +#define MG4_13_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_13PL) || (G4_11PL == 0) +#define MG4_13_111PL ~(1 << 10) +#else +#define MG4_13_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_13PL) || (G4_12PL == 0) +#define MG4_13_112PL ~(1 << 11) +#else +#define MG4_13_112PL 0xFFFF +#endif + +#if (G4_14PL >= G4_13PL) || (G4_14PL == 0) +#define MG4_13_114PL ~(1 << 13) +#else +#define MG4_13_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_13PL) || (G4_15PL == 0) +#define MG4_13_115PL ~(1 << 14) +#else +#define MG4_13_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_13PL) || (G4_16PL == 0) +#define MG4_13_116PL ~(1 << 15) +#else +#define MG4_13_116PL 0xFFFF +#endif + +#define MG4_13_113PL 0xEFFF +#define MG4_13 (MG4_13_11PL & MG4_13_12PL & MG4_13_13PL & MG4_13_14PL & \ + MG4_13_15PL & MG4_13_16PL & MG4_13_17PL & MG4_13_18PL & \ + MG4_13_19PL & MG4_13_110PL & MG4_13_111PL & MG4_13_112PL & \ + MG4_13_113PL & MG4_13_114PL & MG4_13_115PL & MG4_13_116PL) +// End of MG4_13: +// Beginning of MG414: +#if (G4_1PL >= G4_14PL) || (G4_1PL == 0) +#define MG4_14_11PL ~(1 << 0) +#else +#define MG4_14_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_14PL) || (G4_2PL == 0) +#define MG4_14_12PL ~(1 << 1) +#else +#define MG4_14_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_14PL) || (G4_3PL == 0) +#define MG4_14_13PL ~(1 << 2) +#else +#define MG4_14_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_14PL) || (G4_4PL == 0) +#define MG4_14_14PL ~(1 << 3) +#else +#define MG4_14_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_14PL) || (G4_5PL == 0) +#define MG4_14_15PL ~(1 << 4) +#else +#define MG4_14_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_14PL) || (G4_6PL == 0) +#define MG4_14_16PL ~(1 << 5) +#else +#define MG4_14_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_14PL) || (G4_7PL == 0) +#define MG4_14_17PL ~(1 << 6) +#else +#define MG4_14_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_14PL) || (G4_8PL == 0) +#define MG4_14_18PL ~(1 << 7) +#else +#define MG4_14_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_14PL) || (G4_9PL == 0) +#define MG4_14_19PL ~(1 << 8) +#else +#define MG4_14_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_14PL) || (G4_10PL == 0) +#define MG4_14_110PL ~(1 << 9) +#else +#define MG4_14_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_14PL) || (G4_11PL == 0) +#define MG4_14_111PL ~(1 << 10) +#else +#define MG4_14_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_14PL) || (G4_12PL == 0) +#define MG4_14_112PL ~(1 << 11) +#else +#define MG4_14_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_14PL) || (G4_13PL == 0) +#define MG4_14_113PL ~(1 << 12) +#else +#define MG4_14_113PL 0xFFFF +#endif + +#if (G4_15PL >= G4_14PL) || (G4_15PL == 0) +#define MG4_14_115PL ~(1 << 14) +#else +#define MG4_14_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_14PL) || (G4_16PL == 0) +#define MG4_14_116PL ~(1 << 15) +#else +#define MG4_14_116PL 0xFFFF +#endif + +#define MG4_14_114PL 0xDFFF +#define MG4_14 (MG4_14_11PL & MG4_14_12PL & MG4_14_13PL & MG4_14_14PL & \ + MG4_14_15PL & MG4_14_16PL & MG4_14_17PL & MG4_14_18PL & \ + MG4_14_19PL & MG4_14_110PL & MG4_14_111PL & MG4_14_112PL & \ + MG4_14_113PL & MG4_14_114PL & MG4_14_115PL & MG4_14_116PL) +// End of MG4_14: +// Beginning of MG415: +#if (G4_1PL >= G4_15PL) || (G4_1PL == 0) +#define MG4_15_11PL ~(1 << 0) +#else +#define MG4_15_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_15PL) || (G4_2PL == 0) +#define MG4_15_12PL ~(1 << 1) +#else +#define MG4_15_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_15PL) || (G4_3PL == 0) +#define MG4_15_13PL ~(1 << 2) +#else +#define MG4_15_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_15PL) || (G4_4PL == 0) +#define MG4_15_14PL ~(1 << 3) +#else +#define MG4_15_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_15PL) || (G4_5PL == 0) +#define MG4_15_15PL ~(1 << 4) +#else +#define MG4_15_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_15PL) || (G4_6PL == 0) +#define MG4_15_16PL ~(1 << 5) +#else +#define MG4_15_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_15PL) || (G4_7PL == 0) +#define MG4_15_17PL ~(1 << 6) +#else +#define MG4_15_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_15PL) || (G4_8PL == 0) +#define MG4_15_18PL ~(1 << 7) +#else +#define MG4_15_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_15PL) || (G4_9PL == 0) +#define MG4_15_19PL ~(1 << 8) +#else +#define MG4_15_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_15PL) || (G4_10PL == 0) +#define MG4_15_110PL ~(1 << 9) +#else +#define MG4_15_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_15PL) || (G4_11PL == 0) +#define MG4_15_111PL ~(1 << 10) +#else +#define MG4_15_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_15PL) || (G4_12PL == 0) +#define MG4_15_112PL ~(1 << 11) +#else +#define MG4_15_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_15PL) || (G4_13PL == 0) +#define MG4_15_113PL ~(1 << 12) +#else +#define MG4_15_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_15PL) || (G4_14PL == 0) +#define MG4_15_114PL ~(1 << 13) +#else +#define MG4_15_114PL 0xFFFF +#endif + +#if (G4_16PL >= G4_15PL) || (G4_16PL == 0) +#define MG4_15_116PL ~(1 << 15) +#else +#define MG4_15_116PL 0xFFFF +#endif + +#define MG4_15_115PL 0xBFFF +#define MG4_15 (MG4_15_11PL & MG4_15_12PL & MG4_15_13PL & MG4_15_14PL & \ + MG4_15_15PL & MG4_15_16PL & MG4_15_17PL & MG4_15_18PL & \ + MG4_15_19PL & MG4_15_110PL & MG4_15_111PL & MG4_15_112PL & \ + MG4_15_113PL & MG4_15_114PL & MG4_15_115PL & MG4_15_116PL) +// End of MG4_15: +// Beginning of MG416: +#if (G4_1PL >= G4_16PL) || (G4_1PL == 0) +#define MG4_16_11PL ~(1 << 0) +#else +#define MG4_16_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_16PL) || (G4_2PL == 0) +#define MG4_16_12PL ~(1 << 1) +#else +#define MG4_16_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_16PL) || (G4_3PL == 0) +#define MG4_16_13PL ~(1 << 2) +#else +#define MG4_16_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_16PL) || (G4_4PL == 0) +#define MG4_16_14PL ~(1 << 3) +#else +#define MG4_16_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_16PL) || (G4_5PL == 0) +#define MG4_16_15PL ~(1 << 4) +#else +#define MG4_16_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_16PL) || (G4_6PL == 0) +#define MG4_16_16PL ~(1 << 5) +#else +#define MG4_16_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_16PL) || (G4_7PL == 0) +#define MG4_16_17PL ~(1 << 6) +#else +#define MG4_16_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_16PL) || (G4_8PL == 0) +#define MG4_16_18PL ~(1 << 7) +#else +#define MG4_16_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_16PL) || (G4_9PL == 0) +#define MG4_16_19PL ~(1 << 8) +#else +#define MG4_16_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_16PL) || (G4_10PL == 0) +#define MG4_16_110PL ~(1 << 9) +#else +#define MG4_16_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_16PL) || (G4_11PL == 0) +#define MG4_16_111PL ~(1 << 10) +#else +#define MG4_16_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_16PL) || (G4_12PL == 0) +#define MG4_16_112PL ~(1 << 11) +#else +#define MG4_16_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_16PL) || (G4_13PL == 0) +#define MG4_16_113PL ~(1 << 12) +#else +#define MG4_16_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_16PL) || (G4_14PL == 0) +#define MG4_16_114PL ~(1 << 13) +#else +#define MG4_16_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_16PL) || (G4_15PL == 0) +#define MG4_16_115PL ~(1 << 14) +#else +#define MG4_16_115PL 0xFFFF +#endif + +#define MG4_16_116PL 0x7FFF +#define MG4_16 (MG4_16_11PL & MG4_16_12PL & MG4_16_13PL & MG4_16_14PL & \ + MG4_16_15PL & MG4_16_16PL & MG4_16_17PL & MG4_16_18PL & \ + MG4_16_19PL & MG4_16_110PL & MG4_16_111PL & MG4_16_112PL & \ + MG4_16_113PL & MG4_16_114PL & MG4_16_115PL & MG4_16_116PL) +// End of MG4_16: + + +// +// Automatically generate PIEIER5 interrupt masks MG51 to MG516: +// + +// Beginning of MG51: +#if (G5_2PL >= G5_1PL) || (G5_2PL == 0) +#define MG5_1_12PL ~(1 << 1) +#else +#define MG5_1_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_1PL) || (G5_3PL == 0) +#define MG5_1_13PL ~(1 << 2) +#else +#define MG5_1_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_1PL) || (G5_4PL == 0) +#define MG5_1_14PL ~(1 << 3) +#else +#define MG5_1_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_1PL) || (G5_5PL == 0) +#define MG5_1_15PL ~(1 << 4) +#else +#define MG5_1_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_1PL) || (G5_6PL == 0) +#define MG5_1_16PL ~(1 << 5) +#else +#define MG5_1_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_1PL) || (G5_7PL == 0) +#define MG5_1_17PL ~(1 << 6) +#else +#define MG5_1_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_1PL) || (G5_8PL == 0) +#define MG5_1_18PL ~(1 << 7) +#else +#define MG5_1_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_1PL) || (G5_9PL == 0) +#define MG5_1_19PL ~(1 << 8) +#else +#define MG5_1_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_1PL) || (G5_10PL == 0) +#define MG5_1_110PL ~(1 << 9) +#else +#define MG5_1_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_1PL) || (G5_11PL == 0) +#define MG5_1_111PL ~(1 << 10) +#else +#define MG5_1_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_1PL) || (G5_12PL == 0) +#define MG5_1_112PL ~(1 << 11) +#else +#define MG5_1_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_1PL) || (G5_13PL == 0) +#define MG5_1_113PL ~(1 << 12) +#else +#define MG5_1_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_1PL) || (G5_14PL == 0) +#define MG5_1_114PL ~(1 << 13) +#else +#define MG5_1_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_1PL) || (G5_15PL == 0) +#define MG5_1_115PL ~(1 << 14) +#else +#define MG5_1_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_1PL) || (G5_16PL == 0) +#define MG5_1_116PL ~(1 << 15) +#else +#define MG5_1_116PL 0xFFFF +#endif + +#define MG5_1_11PL 0xFFFE +#define MG5_1 (MG5_1_11PL & MG5_1_12PL & MG5_1_13PL & MG5_1_14PL & \ + MG5_1_15PL & MG5_1_16PL & MG5_1_17PL & MG5_1_18PL & \ + MG5_1_19PL & MG5_1_110PL & MG5_1_111PL & MG5_1_112PL & \ + MG5_1_113PL & MG5_1_114PL & MG5_1_115PL & MG5_1_116PL) +// End of MG5_1: +// Beginning of MG52: +#if (G5_1PL >= G5_2PL) || (G5_1PL == 0) +#define MG5_2_11PL ~(1 << 0) +#else +#define MG5_2_11PL 0xFFFF +#endif + +#if (G5_3PL >= G5_2PL) || (G5_3PL == 0) +#define MG5_2_13PL ~(1 << 2) +#else +#define MG5_2_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_2PL) || (G5_4PL == 0) +#define MG5_2_14PL ~(1 << 3) +#else +#define MG5_2_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_2PL) || (G5_5PL == 0) +#define MG5_2_15PL ~(1 << 4) +#else +#define MG5_2_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_2PL) || (G5_6PL == 0) +#define MG5_2_16PL ~(1 << 5) +#else +#define MG5_2_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_2PL) || (G5_7PL == 0) +#define MG5_2_17PL ~(1 << 6) +#else +#define MG5_2_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_2PL) || (G5_8PL == 0) +#define MG5_2_18PL ~(1 << 7) +#else +#define MG5_2_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_2PL) || (G5_9PL == 0) +#define MG5_2_19PL ~(1 << 8) +#else +#define MG5_2_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_2PL) || (G5_10PL == 0) +#define MG5_2_110PL ~(1 << 9) +#else +#define MG5_2_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_2PL) || (G5_11PL == 0) +#define MG5_2_111PL ~(1 << 10) +#else +#define MG5_2_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_2PL) || (G5_12PL == 0) +#define MG5_2_112PL ~(1 << 11) +#else +#define MG5_2_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_2PL) || (G5_13PL == 0) +#define MG5_2_113PL ~(1 << 12) +#else +#define MG5_2_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_2PL) || (G5_14PL == 0) +#define MG5_2_114PL ~(1 << 13) +#else +#define MG5_2_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_2PL) || (G5_15PL == 0) +#define MG5_2_115PL ~(1 << 14) +#else +#define MG5_2_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_2PL) || (G5_16PL == 0) +#define MG5_2_116PL ~(1 << 15) +#else +#define MG5_2_116PL 0xFFFF +#endif + +#define MG5_2_12PL 0xFFFD +#define MG5_2 (MG5_2_11PL & MG5_2_12PL & MG5_2_13PL & MG5_2_14PL & \ + MG5_2_15PL & MG5_2_16PL & MG5_2_17PL & MG5_2_18PL & \ + MG5_2_19PL & MG5_2_110PL & MG5_2_111PL & MG5_2_112PL & \ + MG5_2_113PL & MG5_2_114PL & MG5_2_115PL & MG5_2_116PL) +// End of MG5_2: +// Beginning of MG53: +#if (G5_1PL >= G5_3PL) || (G5_1PL == 0) +#define MG5_3_11PL ~(1 << 0) +#else +#define MG5_3_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_3PL) || (G5_2PL == 0) +#define MG5_3_12PL ~(1 << 1) +#else +#define MG5_3_12PL 0xFFFF +#endif + +#if (G5_4PL >= G5_3PL) || (G5_4PL == 0) +#define MG5_3_14PL ~(1 << 3) +#else +#define MG5_3_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_3PL) || (G5_5PL == 0) +#define MG5_3_15PL ~(1 << 4) +#else +#define MG5_3_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_3PL) || (G5_6PL == 0) +#define MG5_3_16PL ~(1 << 5) +#else +#define MG5_3_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_3PL) || (G5_7PL == 0) +#define MG5_3_17PL ~(1 << 6) +#else +#define MG5_3_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_3PL) || (G5_8PL == 0) +#define MG5_3_18PL ~(1 << 7) +#else +#define MG5_3_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_3PL) || (G5_9PL == 0) +#define MG5_3_19PL ~(1 << 8) +#else +#define MG5_3_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_3PL) || (G5_10PL == 0) +#define MG5_3_110PL ~(1 << 9) +#else +#define MG5_3_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_3PL) || (G5_11PL == 0) +#define MG5_3_111PL ~(1 << 10) +#else +#define MG5_3_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_3PL) || (G5_12PL == 0) +#define MG5_3_112PL ~(1 << 11) +#else +#define MG5_3_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_3PL) || (G5_13PL == 0) +#define MG5_3_113PL ~(1 << 12) +#else +#define MG5_3_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_3PL) || (G5_14PL == 0) +#define MG5_3_114PL ~(1 << 13) +#else +#define MG5_3_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_3PL) || (G5_15PL == 0) +#define MG5_3_115PL ~(1 << 14) +#else +#define MG5_3_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_3PL) || (G5_16PL == 0) +#define MG5_3_116PL ~(1 << 15) +#else +#define MG5_3_116PL 0xFFFF +#endif + +#define MG5_3_13PL 0xFFFB +#define MG5_3 (MG5_3_11PL & MG5_3_12PL & MG5_3_13PL & MG5_3_14PL & \ + MG5_3_15PL & MG5_3_16PL & MG5_3_17PL & MG5_3_18PL & \ + MG5_3_19PL & MG5_3_110PL & MG5_3_111PL & MG5_3_112PL & \ + MG5_3_113PL & MG5_3_114PL & MG5_3_115PL & MG5_3_116PL) +// End of MG5_3: +// Beginning of MG54: +#if (G5_1PL >= G5_4PL) || (G5_1PL == 0) +#define MG5_4_11PL ~(1 << 0) +#else +#define MG5_4_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_4PL) || (G5_2PL == 0) +#define MG5_4_12PL ~(1 << 1) +#else +#define MG5_4_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_4PL) || (G5_3PL == 0) +#define MG5_4_13PL ~(1 << 2) +#else +#define MG5_4_13PL 0xFFFF +#endif + +#if (G5_5PL >= G5_4PL) || (G5_5PL == 0) +#define MG5_4_15PL ~(1 << 4) +#else +#define MG5_4_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_4PL) || (G5_6PL == 0) +#define MG5_4_16PL ~(1 << 5) +#else +#define MG5_4_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_4PL) || (G5_7PL == 0) +#define MG5_4_17PL ~(1 << 6) +#else +#define MG5_4_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_4PL) || (G5_8PL == 0) +#define MG5_4_18PL ~(1 << 7) +#else +#define MG5_4_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_4PL) || (G5_9PL == 0) +#define MG5_4_19PL ~(1 << 8) +#else +#define MG5_4_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_4PL) || (G5_10PL == 0) +#define MG5_4_110PL ~(1 << 9) +#else +#define MG5_4_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_4PL) || (G5_11PL == 0) +#define MG5_4_111PL ~(1 << 10) +#else +#define MG5_4_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_4PL) || (G5_12PL == 0) +#define MG5_4_112PL ~(1 << 11) +#else +#define MG5_4_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_4PL) || (G5_13PL == 0) +#define MG5_4_113PL ~(1 << 12) +#else +#define MG5_4_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_4PL) || (G5_14PL == 0) +#define MG5_4_114PL ~(1 << 13) +#else +#define MG5_4_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_4PL) || (G5_15PL == 0) +#define MG5_4_115PL ~(1 << 14) +#else +#define MG5_4_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_4PL) || (G5_16PL == 0) +#define MG5_4_116PL ~(1 << 15) +#else +#define MG5_4_116PL 0xFFFF +#endif + +#define MG5_4_14PL 0xFFF7 +#define MG5_4 (MG5_4_11PL & MG5_4_12PL & MG5_4_13PL & MG5_4_14PL & \ + MG5_4_15PL & MG5_4_16PL & MG5_4_17PL & MG5_4_18PL & \ + MG5_4_19PL & MG5_4_110PL & MG5_4_111PL & MG5_4_112PL & \ + MG5_4_113PL & MG5_4_114PL & MG5_4_115PL & MG5_4_116PL) +// End of MG5_4: +// Beginning of MG55: +#if (G5_1PL >= G5_5PL) || (G5_1PL == 0) +#define MG5_5_11PL ~(1 << 0) +#else +#define MG5_5_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_5PL) || (G5_2PL == 0) +#define MG5_5_12PL ~(1 << 1) +#else +#define MG5_5_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_5PL) || (G5_3PL == 0) +#define MG5_5_13PL ~(1 << 2) +#else +#define MG5_5_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_5PL) || (G5_4PL == 0) +#define MG5_5_14PL ~(1 << 3) +#else +#define MG5_5_14PL 0xFFFF +#endif + +#if (G5_6PL >= G5_5PL) || (G5_6PL == 0) +#define MG5_5_16PL ~(1 << 5) +#else +#define MG5_5_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_5PL) || (G5_7PL == 0) +#define MG5_5_17PL ~(1 << 6) +#else +#define MG5_5_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_5PL) || (G5_8PL == 0) +#define MG5_5_18PL ~(1 << 7) +#else +#define MG5_5_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_5PL) || (G5_9PL == 0) +#define MG5_5_19PL ~(1 << 8) +#else +#define MG5_5_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_5PL) || (G5_10PL == 0) +#define MG5_5_110PL ~(1 << 9) +#else +#define MG5_5_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_5PL) || (G5_11PL == 0) +#define MG5_5_111PL ~(1 << 10) +#else +#define MG5_5_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_5PL) || (G5_12PL == 0) +#define MG5_5_112PL ~(1 << 11) +#else +#define MG5_5_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_5PL) || (G5_13PL == 0) +#define MG5_5_113PL ~(1 << 12) +#else +#define MG5_5_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_5PL) || (G5_14PL == 0) +#define MG5_5_114PL ~(1 << 13) +#else +#define MG5_5_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_5PL) || (G5_15PL == 0) +#define MG5_5_115PL ~(1 << 14) +#else +#define MG5_5_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_5PL) || (G5_16PL == 0) +#define MG5_5_116PL ~(1 << 15) +#else +#define MG5_5_116PL 0xFFFF +#endif + +#define MG5_5_15PL 0xFFEF +#define MG5_5 (MG5_5_11PL & MG5_5_12PL & MG5_5_13PL & MG5_5_14PL & \ + MG5_5_15PL & MG5_5_16PL & MG5_5_17PL & MG5_5_18PL & \ + MG5_5_19PL & MG5_5_110PL & MG5_5_111PL & MG5_5_112PL & \ + MG5_5_113PL & MG5_5_114PL & MG5_5_115PL & MG5_5_116PL) +// End of MG5_5: +// Beginning of MG56: +#if (G5_1PL >= G5_6PL) || (G5_1PL == 0) +#define MG5_6_11PL ~(1 << 0) +#else +#define MG5_6_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_6PL) || (G5_2PL == 0) +#define MG5_6_12PL ~(1 << 1) +#else +#define MG5_6_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_6PL) || (G5_3PL == 0) +#define MG5_6_13PL ~(1 << 2) +#else +#define MG5_6_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_6PL) || (G5_4PL == 0) +#define MG5_6_14PL ~(1 << 3) +#else +#define MG5_6_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_6PL) || (G5_5PL == 0) +#define MG5_6_15PL ~(1 << 4) +#else +#define MG5_6_15PL 0xFFFF +#endif + +#if (G5_7PL >= G5_6PL) || (G5_7PL == 0) +#define MG5_6_17PL ~(1 << 6) +#else +#define MG5_6_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_6PL) || (G5_8PL == 0) +#define MG5_6_18PL ~(1 << 7) +#else +#define MG5_6_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_6PL) || (G5_9PL == 0) +#define MG5_6_19PL ~(1 << 8) +#else +#define MG5_6_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_6PL) || (G5_10PL == 0) +#define MG5_6_110PL ~(1 << 9) +#else +#define MG5_6_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_6PL) || (G5_11PL == 0) +#define MG5_6_111PL ~(1 << 10) +#else +#define MG5_6_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_6PL) || (G5_12PL == 0) +#define MG5_6_112PL ~(1 << 11) +#else +#define MG5_6_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_6PL) || (G5_13PL == 0) +#define MG5_6_113PL ~(1 << 12) +#else +#define MG5_6_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_6PL) || (G5_14PL == 0) +#define MG5_6_114PL ~(1 << 13) +#else +#define MG5_6_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_6PL) || (G5_15PL == 0) +#define MG5_6_115PL ~(1 << 14) +#else +#define MG5_6_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_6PL) || (G5_16PL == 0) +#define MG5_6_116PL ~(1 << 15) +#else +#define MG5_6_116PL 0xFFFF +#endif + +#define MG5_6_16PL 0xFFDF +#define MG5_6 (MG5_6_11PL & MG5_6_12PL & MG5_6_13PL & MG5_6_14PL & \ + MG5_6_15PL & MG5_6_16PL & MG5_6_17PL & MG5_6_18PL & \ + MG5_6_19PL & MG5_6_110PL & MG5_6_111PL & MG5_6_112PL & \ + MG5_6_113PL & MG5_6_114PL & MG5_6_115PL & MG5_6_116PL) +// End of MG5_6: +// Beginning of MG57: +#if (G5_1PL >= G5_7PL) || (G5_1PL == 0) +#define MG5_7_11PL ~(1 << 0) +#else +#define MG5_7_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_7PL) || (G5_2PL == 0) +#define MG5_7_12PL ~(1 << 1) +#else +#define MG5_7_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_7PL) || (G5_3PL == 0) +#define MG5_7_13PL ~(1 << 2) +#else +#define MG5_7_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_7PL) || (G5_4PL == 0) +#define MG5_7_14PL ~(1 << 3) +#else +#define MG5_7_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_7PL) || (G5_5PL == 0) +#define MG5_7_15PL ~(1 << 4) +#else +#define MG5_7_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_7PL) || (G5_6PL == 0) +#define MG5_7_16PL ~(1 << 5) +#else +#define MG5_7_16PL 0xFFFF +#endif + +#if (G5_8PL >= G5_7PL) || (G5_8PL == 0) +#define MG5_7_18PL ~(1 << 7) +#else +#define MG5_7_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_7PL) || (G5_9PL == 0) +#define MG5_7_19PL ~(1 << 8) +#else +#define MG5_7_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_7PL) || (G5_10PL == 0) +#define MG5_7_110PL ~(1 << 9) +#else +#define MG5_7_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_7PL) || (G5_11PL == 0) +#define MG5_7_111PL ~(1 << 10) +#else +#define MG5_7_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_7PL) || (G5_12PL == 0) +#define MG5_7_112PL ~(1 << 11) +#else +#define MG5_7_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_7PL) || (G5_13PL == 0) +#define MG5_7_113PL ~(1 << 12) +#else +#define MG5_7_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_7PL) || (G5_14PL == 0) +#define MG5_7_114PL ~(1 << 13) +#else +#define MG5_7_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_7PL) || (G5_15PL == 0) +#define MG5_7_115PL ~(1 << 14) +#else +#define MG5_7_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_7PL) || (G5_16PL == 0) +#define MG5_7_116PL ~(1 << 15) +#else +#define MG5_7_116PL 0xFFFF +#endif + +#define MG5_7_17PL 0xFFBF +#define MG5_7 (MG5_7_11PL & MG5_7_12PL & MG5_7_13PL & MG5_7_14PL & \ + MG5_7_15PL & MG5_7_16PL & MG5_7_17PL & MG5_7_18PL & \ + MG5_7_19PL & MG5_7_110PL & MG5_7_111PL & MG5_7_112PL & \ + MG5_7_113PL & MG5_7_114PL & MG5_7_115PL & MG5_7_116PL) +// End of MG5_7: +// Beginning of MG58: +#if (G5_1PL >= G5_8PL) || (G5_1PL == 0) +#define MG5_8_11PL ~(1 << 0) +#else +#define MG5_8_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_8PL) || (G5_2PL == 0) +#define MG5_8_12PL ~(1 << 1) +#else +#define MG5_8_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_8PL) || (G5_3PL == 0) +#define MG5_8_13PL ~(1 << 2) +#else +#define MG5_8_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_8PL) || (G5_4PL == 0) +#define MG5_8_14PL ~(1 << 3) +#else +#define MG5_8_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_8PL) || (G5_5PL == 0) +#define MG5_8_15PL ~(1 << 4) +#else +#define MG5_8_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_8PL) || (G5_6PL == 0) +#define MG5_8_16PL ~(1 << 5) +#else +#define MG5_8_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_8PL) || (G5_7PL == 0) +#define MG5_8_17PL ~(1 << 6) +#else +#define MG5_8_17PL 0xFFFF +#endif + +#if (G5_9PL >= G5_8PL) || (G5_9PL == 0) +#define MG5_8_19PL ~(1 << 8) +#else +#define MG5_8_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_8PL) || (G5_10PL == 0) +#define MG5_8_110PL ~(1 << 9) +#else +#define MG5_8_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_8PL) || (G5_11PL == 0) +#define MG5_8_111PL ~(1 << 10) +#else +#define MG5_8_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_8PL) || (G5_12PL == 0) +#define MG5_8_112PL ~(1 << 11) +#else +#define MG5_8_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_8PL) || (G5_13PL == 0) +#define MG5_8_113PL ~(1 << 12) +#else +#define MG5_8_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_8PL) || (G5_14PL == 0) +#define MG5_8_114PL ~(1 << 13) +#else +#define MG5_8_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_8PL) || (G5_15PL == 0) +#define MG5_8_115PL ~(1 << 14) +#else +#define MG5_8_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_8PL) || (G5_16PL == 0) +#define MG5_8_116PL ~(1 << 15) +#else +#define MG5_8_116PL 0xFFFF +#endif + +#define MG5_8_18PL 0xFF7F +#define MG5_8 (MG5_8_11PL & MG5_8_12PL & MG5_8_13PL & MG5_8_14PL & \ + MG5_8_15PL & MG5_8_16PL & MG5_8_17PL & MG5_8_18PL & \ + MG5_8_19PL & MG5_8_110PL & MG5_8_111PL & MG5_8_112PL & \ + MG5_8_113PL & MG5_8_114PL & MG5_8_115PL & MG5_8_116PL) +// End of MG5_8: +// Beginning of MG59: +#if (G5_1PL >= G5_9PL) || (G5_1PL == 0) +#define MG5_9_11PL ~(1 << 0) +#else +#define MG5_9_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_9PL) || (G5_2PL == 0) +#define MG5_9_12PL ~(1 << 1) +#else +#define MG5_9_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_9PL) || (G5_3PL == 0) +#define MG5_9_13PL ~(1 << 2) +#else +#define MG5_9_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_9PL) || (G5_4PL == 0) +#define MG5_9_14PL ~(1 << 3) +#else +#define MG5_9_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_9PL) || (G5_5PL == 0) +#define MG5_9_15PL ~(1 << 4) +#else +#define MG5_9_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_9PL) || (G5_6PL == 0) +#define MG5_9_16PL ~(1 << 5) +#else +#define MG5_9_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_9PL) || (G5_7PL == 0) +#define MG5_9_17PL ~(1 << 6) +#else +#define MG5_9_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_9PL) || (G5_8PL == 0) +#define MG5_9_18PL ~(1 << 7) +#else +#define MG5_9_18PL 0xFFFF +#endif + +#if (G5_10PL >= G5_9PL) || (G5_10PL == 0) +#define MG5_9_110PL ~(1 << 9) +#else +#define MG5_9_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_9PL) || (G5_11PL == 0) +#define MG5_9_111PL ~(1 << 10) +#else +#define MG5_9_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_9PL) || (G5_12PL == 0) +#define MG5_9_112PL ~(1 << 11) +#else +#define MG5_9_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_9PL) || (G5_13PL == 0) +#define MG5_9_113PL ~(1 << 12) +#else +#define MG5_9_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_9PL) || (G5_14PL == 0) +#define MG5_9_114PL ~(1 << 13) +#else +#define MG5_9_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_9PL) || (G5_15PL == 0) +#define MG5_9_115PL ~(1 << 14) +#else +#define MG5_9_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_9PL) || (G5_16PL == 0) +#define MG5_9_116PL ~(1 << 15) +#else +#define MG5_9_116PL 0xFFFF +#endif + +#define MG5_9_19PL 0xFEFF +#define MG5_9 (MG5_9_11PL & MG5_9_12PL & MG5_9_13PL & MG5_9_14PL & \ + MG5_9_15PL & MG5_9_16PL & MG5_9_17PL & MG5_9_18PL & \ + MG5_9_19PL & MG5_9_110PL & MG5_9_111PL & MG5_9_112PL & \ + MG5_9_113PL & MG5_9_114PL & MG5_9_115PL & MG5_9_116PL) +// End of MG5_9: +// Beginning of MG510: +#if (G5_1PL >= G5_10PL) || (G5_1PL == 0) +#define MG5_10_11PL ~(1 << 0) +#else +#define MG5_10_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_10PL) || (G5_2PL == 0) +#define MG5_10_12PL ~(1 << 1) +#else +#define MG5_10_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_10PL) || (G5_3PL == 0) +#define MG5_10_13PL ~(1 << 2) +#else +#define MG5_10_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_10PL) || (G5_4PL == 0) +#define MG5_10_14PL ~(1 << 3) +#else +#define MG5_10_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_10PL) || (G5_5PL == 0) +#define MG5_10_15PL ~(1 << 4) +#else +#define MG5_10_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_10PL) || (G5_6PL == 0) +#define MG5_10_16PL ~(1 << 5) +#else +#define MG5_10_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_10PL) || (G5_7PL == 0) +#define MG5_10_17PL ~(1 << 6) +#else +#define MG5_10_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_10PL) || (G5_8PL == 0) +#define MG5_10_18PL ~(1 << 7) +#else +#define MG5_10_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_10PL) || (G5_9PL == 0) +#define MG5_10_19PL ~(1 << 8) +#else +#define MG5_10_19PL 0xFFFF +#endif + +#if (G5_11PL >= G5_10PL) || (G5_11PL == 0) +#define MG5_10_111PL ~(1 << 10) +#else +#define MG5_10_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_10PL) || (G5_12PL == 0) +#define MG5_10_112PL ~(1 << 11) +#else +#define MG5_10_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_10PL) || (G5_13PL == 0) +#define MG5_10_113PL ~(1 << 12) +#else +#define MG5_10_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_10PL) || (G5_14PL == 0) +#define MG5_10_114PL ~(1 << 13) +#else +#define MG5_10_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_10PL) || (G5_15PL == 0) +#define MG5_10_115PL ~(1 << 14) +#else +#define MG5_10_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_10PL) || (G5_16PL == 0) +#define MG5_10_116PL ~(1 << 15) +#else +#define MG5_10_116PL 0xFFFF +#endif + +#define MG5_10_110PL 0xFDFF +#define MG5_10 (MG5_10_11PL & MG5_10_12PL & MG5_10_13PL & MG5_10_14PL & \ + MG5_10_15PL & MG5_10_16PL & MG5_10_17PL & MG5_10_18PL & \ + MG5_10_19PL & MG5_10_110PL & MG5_10_111PL & MG5_10_112PL & \ + MG5_10_113PL & MG5_10_114PL & MG5_10_115PL & MG5_10_116PL) +// End of MG5_10: +// Beginning of MG511: +#if (G5_1PL >= G5_11PL) || (G5_1PL == 0) +#define MG5_11_11PL ~(1 << 0) +#else +#define MG5_11_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_11PL) || (G5_2PL == 0) +#define MG5_11_12PL ~(1 << 1) +#else +#define MG5_11_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_11PL) || (G5_3PL == 0) +#define MG5_11_13PL ~(1 << 2) +#else +#define MG5_11_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_11PL) || (G5_4PL == 0) +#define MG5_11_14PL ~(1 << 3) +#else +#define MG5_11_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_11PL) || (G5_5PL == 0) +#define MG5_11_15PL ~(1 << 4) +#else +#define MG5_11_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_11PL) || (G5_6PL == 0) +#define MG5_11_16PL ~(1 << 5) +#else +#define MG5_11_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_11PL) || (G5_7PL == 0) +#define MG5_11_17PL ~(1 << 6) +#else +#define MG5_11_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_11PL) || (G5_8PL == 0) +#define MG5_11_18PL ~(1 << 7) +#else +#define MG5_11_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_11PL) || (G5_9PL == 0) +#define MG5_11_19PL ~(1 << 8) +#else +#define MG5_11_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_11PL) || (G5_10PL == 0) +#define MG5_11_110PL ~(1 << 9) +#else +#define MG5_11_110PL 0xFFFF +#endif + +#if (G5_12PL >= G5_11PL) || (G5_12PL == 0) +#define MG5_11_112PL ~(1 << 11) +#else +#define MG5_11_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_11PL) || (G5_13PL == 0) +#define MG5_11_113PL ~(1 << 12) +#else +#define MG5_11_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_11PL) || (G5_14PL == 0) +#define MG5_11_114PL ~(1 << 13) +#else +#define MG5_11_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_11PL) || (G5_15PL == 0) +#define MG5_11_115PL ~(1 << 14) +#else +#define MG5_11_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_11PL) || (G5_16PL == 0) +#define MG5_11_116PL ~(1 << 15) +#else +#define MG5_11_116PL 0xFFFF +#endif + +#define MG5_11_111PL 0xFBFF +#define MG5_11 (MG5_11_11PL & MG5_11_12PL & MG5_11_13PL & MG5_11_14PL & \ + MG5_11_15PL & MG5_11_16PL & MG5_11_17PL & MG5_11_18PL & \ + MG5_11_19PL & MG5_11_110PL & MG5_11_111PL & MG5_11_112PL & \ + MG5_11_113PL & MG5_11_114PL & MG5_11_115PL & MG5_11_116PL) +// End of MG5_11: +// Beginning of MG512: +#if (G5_1PL >= G5_12PL) || (G5_1PL == 0) +#define MG5_12_11PL ~(1 << 0) +#else +#define MG5_12_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_12PL) || (G5_2PL == 0) +#define MG5_12_12PL ~(1 << 1) +#else +#define MG5_12_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_12PL) || (G5_3PL == 0) +#define MG5_12_13PL ~(1 << 2) +#else +#define MG5_12_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_12PL) || (G5_4PL == 0) +#define MG5_12_14PL ~(1 << 3) +#else +#define MG5_12_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_12PL) || (G5_5PL == 0) +#define MG5_12_15PL ~(1 << 4) +#else +#define MG5_12_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_12PL) || (G5_6PL == 0) +#define MG5_12_16PL ~(1 << 5) +#else +#define MG5_12_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_12PL) || (G5_7PL == 0) +#define MG5_12_17PL ~(1 << 6) +#else +#define MG5_12_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_12PL) || (G5_8PL == 0) +#define MG5_12_18PL ~(1 << 7) +#else +#define MG5_12_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_12PL) || (G5_9PL == 0) +#define MG5_12_19PL ~(1 << 8) +#else +#define MG5_12_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_12PL) || (G5_10PL == 0) +#define MG5_12_110PL ~(1 << 9) +#else +#define MG5_12_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_12PL) || (G5_11PL == 0) +#define MG5_12_111PL ~(1 << 10) +#else +#define MG5_12_111PL 0xFFFF +#endif + +#if (G5_13PL >= G5_12PL) || (G5_13PL == 0) +#define MG5_12_113PL ~(1 << 12) +#else +#define MG5_12_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_12PL) || (G5_14PL == 0) +#define MG5_12_114PL ~(1 << 13) +#else +#define MG5_12_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_12PL) || (G5_15PL == 0) +#define MG5_12_115PL ~(1 << 14) +#else +#define MG5_12_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_12PL) || (G5_16PL == 0) +#define MG5_12_116PL ~(1 << 15) +#else +#define MG5_12_116PL 0xFFFF +#endif + +#define MG5_12_112PL 0xF7FF +#define MG5_12 (MG5_12_11PL & MG5_12_12PL & MG5_12_13PL & MG5_12_14PL & \ + MG5_12_15PL & MG5_12_16PL & MG5_12_17PL & MG5_12_18PL & \ + MG5_12_19PL & MG5_12_110PL & MG5_12_111PL & MG5_12_112PL & \ + MG5_12_113PL & MG5_12_114PL & MG5_12_115PL & MG5_12_116PL) +// End of MG5_12: +// Beginning of MG513: +#if (G5_1PL >= G5_13PL) || (G5_1PL == 0) +#define MG5_13_11PL ~(1 << 0) +#else +#define MG5_13_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_13PL) || (G5_2PL == 0) +#define MG5_13_12PL ~(1 << 1) +#else +#define MG5_13_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_13PL) || (G5_3PL == 0) +#define MG5_13_13PL ~(1 << 2) +#else +#define MG5_13_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_13PL) || (G5_4PL == 0) +#define MG5_13_14PL ~(1 << 3) +#else +#define MG5_13_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_13PL) || (G5_5PL == 0) +#define MG5_13_15PL ~(1 << 4) +#else +#define MG5_13_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_13PL) || (G5_6PL == 0) +#define MG5_13_16PL ~(1 << 5) +#else +#define MG5_13_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_13PL) || (G5_7PL == 0) +#define MG5_13_17PL ~(1 << 6) +#else +#define MG5_13_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_13PL) || (G5_8PL == 0) +#define MG5_13_18PL ~(1 << 7) +#else +#define MG5_13_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_13PL) || (G5_9PL == 0) +#define MG5_13_19PL ~(1 << 8) +#else +#define MG5_13_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_13PL) || (G5_10PL == 0) +#define MG5_13_110PL ~(1 << 9) +#else +#define MG5_13_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_13PL) || (G5_11PL == 0) +#define MG5_13_111PL ~(1 << 10) +#else +#define MG5_13_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_13PL) || (G5_12PL == 0) +#define MG5_13_112PL ~(1 << 11) +#else +#define MG5_13_112PL 0xFFFF +#endif + +#if (G5_14PL >= G5_13PL) || (G5_14PL == 0) +#define MG5_13_114PL ~(1 << 13) +#else +#define MG5_13_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_13PL) || (G5_15PL == 0) +#define MG5_13_115PL ~(1 << 14) +#else +#define MG5_13_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_13PL) || (G5_16PL == 0) +#define MG5_13_116PL ~(1 << 15) +#else +#define MG5_13_116PL 0xFFFF +#endif + +#define MG5_13_113PL 0xEFFF +#define MG5_13 (MG5_13_11PL & MG5_13_12PL & MG5_13_13PL & MG5_13_14PL & \ + MG5_13_15PL & MG5_13_16PL & MG5_13_17PL & MG5_13_18PL & \ + MG5_13_19PL & MG5_13_110PL & MG5_13_111PL & MG5_13_112PL & \ + MG5_13_113PL & MG5_13_114PL & MG5_13_115PL & MG5_13_116PL) +// End of MG5_13: +// Beginning of MG514: +#if (G5_1PL >= G5_14PL) || (G5_1PL == 0) +#define MG5_14_11PL ~(1 << 0) +#else +#define MG5_14_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_14PL) || (G5_2PL == 0) +#define MG5_14_12PL ~(1 << 1) +#else +#define MG5_14_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_14PL) || (G5_3PL == 0) +#define MG5_14_13PL ~(1 << 2) +#else +#define MG5_14_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_14PL) || (G5_4PL == 0) +#define MG5_14_14PL ~(1 << 3) +#else +#define MG5_14_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_14PL) || (G5_5PL == 0) +#define MG5_14_15PL ~(1 << 4) +#else +#define MG5_14_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_14PL) || (G5_6PL == 0) +#define MG5_14_16PL ~(1 << 5) +#else +#define MG5_14_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_14PL) || (G5_7PL == 0) +#define MG5_14_17PL ~(1 << 6) +#else +#define MG5_14_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_14PL) || (G5_8PL == 0) +#define MG5_14_18PL ~(1 << 7) +#else +#define MG5_14_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_14PL) || (G5_9PL == 0) +#define MG5_14_19PL ~(1 << 8) +#else +#define MG5_14_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_14PL) || (G5_10PL == 0) +#define MG5_14_110PL ~(1 << 9) +#else +#define MG5_14_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_14PL) || (G5_11PL == 0) +#define MG5_14_111PL ~(1 << 10) +#else +#define MG5_14_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_14PL) || (G5_12PL == 0) +#define MG5_14_112PL ~(1 << 11) +#else +#define MG5_14_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_14PL) || (G5_13PL == 0) +#define MG5_14_113PL ~(1 << 12) +#else +#define MG5_14_113PL 0xFFFF +#endif + +#if (G5_15PL >= G5_14PL) || (G5_15PL == 0) +#define MG5_14_115PL ~(1 << 14) +#else +#define MG5_14_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_14PL) || (G5_16PL == 0) +#define MG5_14_116PL ~(1 << 15) +#else +#define MG5_14_116PL 0xFFFF +#endif + +#define MG5_14_114PL 0xDFFF +#define MG5_14 (MG5_14_11PL & MG5_14_12PL & MG5_14_13PL & MG5_14_14PL & \ + MG5_14_15PL & MG5_14_16PL & MG5_14_17PL & MG5_14_18PL & \ + MG5_14_19PL & MG5_14_110PL & MG5_14_111PL & MG5_14_112PL & \ + MG5_14_113PL & MG5_14_114PL & MG5_14_115PL & MG5_14_116PL) +// End of MG5_14: +// Beginning of MG515: +#if (G5_1PL >= G5_15PL) || (G5_1PL == 0) +#define MG5_15_11PL ~(1 << 0) +#else +#define MG5_15_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_15PL) || (G5_2PL == 0) +#define MG5_15_12PL ~(1 << 1) +#else +#define MG5_15_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_15PL) || (G5_3PL == 0) +#define MG5_15_13PL ~(1 << 2) +#else +#define MG5_15_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_15PL) || (G5_4PL == 0) +#define MG5_15_14PL ~(1 << 3) +#else +#define MG5_15_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_15PL) || (G5_5PL == 0) +#define MG5_15_15PL ~(1 << 4) +#else +#define MG5_15_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_15PL) || (G5_6PL == 0) +#define MG5_15_16PL ~(1 << 5) +#else +#define MG5_15_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_15PL) || (G5_7PL == 0) +#define MG5_15_17PL ~(1 << 6) +#else +#define MG5_15_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_15PL) || (G5_8PL == 0) +#define MG5_15_18PL ~(1 << 7) +#else +#define MG5_15_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_15PL) || (G5_9PL == 0) +#define MG5_15_19PL ~(1 << 8) +#else +#define MG5_15_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_15PL) || (G5_10PL == 0) +#define MG5_15_110PL ~(1 << 9) +#else +#define MG5_15_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_15PL) || (G5_11PL == 0) +#define MG5_15_111PL ~(1 << 10) +#else +#define MG5_15_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_15PL) || (G5_12PL == 0) +#define MG5_15_112PL ~(1 << 11) +#else +#define MG5_15_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_15PL) || (G5_13PL == 0) +#define MG5_15_113PL ~(1 << 12) +#else +#define MG5_15_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_15PL) || (G5_14PL == 0) +#define MG5_15_114PL ~(1 << 13) +#else +#define MG5_15_114PL 0xFFFF +#endif + +#if (G5_16PL >= G5_15PL) || (G5_16PL == 0) +#define MG5_15_116PL ~(1 << 15) +#else +#define MG5_15_116PL 0xFFFF +#endif + +#define MG5_15_115PL 0xBFFF +#define MG5_15 (MG5_15_11PL & MG5_15_12PL & MG5_15_13PL & MG5_15_14PL & \ + MG5_15_15PL & MG5_15_16PL & MG5_15_17PL & MG5_15_18PL & \ + MG5_15_19PL & MG5_15_110PL & MG5_15_111PL & MG5_15_112PL & \ + MG5_15_113PL & MG5_15_114PL & MG5_15_115PL & MG5_15_116PL) +// End of MG5_15: +// Beginning of MG516: +#if (G5_1PL >= G5_16PL) || (G5_1PL == 0) +#define MG5_16_11PL ~(1 << 0) +#else +#define MG5_16_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_16PL) || (G5_2PL == 0) +#define MG5_16_12PL ~(1 << 1) +#else +#define MG5_16_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_16PL) || (G5_3PL == 0) +#define MG5_16_13PL ~(1 << 2) +#else +#define MG5_16_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_16PL) || (G5_4PL == 0) +#define MG5_16_14PL ~(1 << 3) +#else +#define MG5_16_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_16PL) || (G5_5PL == 0) +#define MG5_16_15PL ~(1 << 4) +#else +#define MG5_16_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_16PL) || (G5_6PL == 0) +#define MG5_16_16PL ~(1 << 5) +#else +#define MG5_16_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_16PL) || (G5_7PL == 0) +#define MG5_16_17PL ~(1 << 6) +#else +#define MG5_16_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_16PL) || (G5_8PL == 0) +#define MG5_16_18PL ~(1 << 7) +#else +#define MG5_16_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_16PL) || (G5_9PL == 0) +#define MG5_16_19PL ~(1 << 8) +#else +#define MG5_16_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_16PL) || (G5_10PL == 0) +#define MG5_16_110PL ~(1 << 9) +#else +#define MG5_16_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_16PL) || (G5_11PL == 0) +#define MG5_16_111PL ~(1 << 10) +#else +#define MG5_16_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_16PL) || (G5_12PL == 0) +#define MG5_16_112PL ~(1 << 11) +#else +#define MG5_16_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_16PL) || (G5_13PL == 0) +#define MG5_16_113PL ~(1 << 12) +#else +#define MG5_16_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_16PL) || (G5_14PL == 0) +#define MG5_16_114PL ~(1 << 13) +#else +#define MG5_16_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_16PL) || (G5_15PL == 0) +#define MG5_16_115PL ~(1 << 14) +#else +#define MG5_16_115PL 0xFFFF +#endif + +#define MG5_16_116PL 0x7FFF +#define MG5_16 (MG5_16_11PL & MG5_16_12PL & MG5_16_13PL & MG5_16_14PL & \ + MG5_16_15PL & MG5_16_16PL & MG5_16_17PL & MG5_16_18PL & \ + MG5_16_19PL & MG5_16_110PL & MG5_16_111PL & MG5_16_112PL & \ + MG5_16_113PL & MG5_16_114PL & MG5_16_115PL & MG5_16_116PL) +// End of MG5_16: + + +// +// Automatically generate PIEIER6 interrupt masks MG61 to MG616: +// + +// Beginning of MG61: +#if (G6_2PL >= G6_1PL) || (G6_2PL == 0) +#define MG6_1_12PL ~(1 << 1) +#else +#define MG6_1_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_1PL) || (G6_3PL == 0) +#define MG6_1_13PL ~(1 << 2) +#else +#define MG6_1_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_1PL) || (G6_4PL == 0) +#define MG6_1_14PL ~(1 << 3) +#else +#define MG6_1_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_1PL) || (G6_5PL == 0) +#define MG6_1_15PL ~(1 << 4) +#else +#define MG6_1_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_1PL) || (G6_6PL == 0) +#define MG6_1_16PL ~(1 << 5) +#else +#define MG6_1_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_1PL) || (G6_7PL == 0) +#define MG6_1_17PL ~(1 << 6) +#else +#define MG6_1_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_1PL) || (G6_8PL == 0) +#define MG6_1_18PL ~(1 << 7) +#else +#define MG6_1_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_1PL) || (G6_9PL == 0) +#define MG6_1_19PL ~(1 << 8) +#else +#define MG6_1_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_1PL) || (G6_10PL == 0) +#define MG6_1_110PL ~(1 << 9) +#else +#define MG6_1_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_1PL) || (G6_11PL == 0) +#define MG6_1_111PL ~(1 << 10) +#else +#define MG6_1_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_1PL) || (G6_12PL == 0) +#define MG6_1_112PL ~(1 << 11) +#else +#define MG6_1_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_1PL) || (G6_13PL == 0) +#define MG6_1_113PL ~(1 << 12) +#else +#define MG6_1_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_1PL) || (G6_14PL == 0) +#define MG6_1_114PL ~(1 << 13) +#else +#define MG6_1_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_1PL) || (G6_15PL == 0) +#define MG6_1_115PL ~(1 << 14) +#else +#define MG6_1_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_1PL) || (G6_16PL == 0) +#define MG6_1_116PL ~(1 << 15) +#else +#define MG6_1_116PL 0xFFFF +#endif + +#define MG6_1_11PL 0xFFFE +#define MG6_1 (MG6_1_11PL & MG6_1_12PL & MG6_1_13PL & MG6_1_14PL & \ + MG6_1_15PL & MG6_1_16PL & MG6_1_17PL & MG6_1_18PL & \ + MG6_1_19PL & MG6_1_110PL & MG6_1_111PL & MG6_1_112PL & \ + MG6_1_113PL & MG6_1_114PL & MG6_1_115PL & MG6_1_116PL) +// End of MG6_1: +// Beginning of MG62: +#if (G6_1PL >= G6_2PL) || (G6_1PL == 0) +#define MG6_2_11PL ~(1 << 0) +#else +#define MG6_2_11PL 0xFFFF +#endif + +#if (G6_3PL >= G6_2PL) || (G6_3PL == 0) +#define MG6_2_13PL ~(1 << 2) +#else +#define MG6_2_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_2PL) || (G6_4PL == 0) +#define MG6_2_14PL ~(1 << 3) +#else +#define MG6_2_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_2PL) || (G6_5PL == 0) +#define MG6_2_15PL ~(1 << 4) +#else +#define MG6_2_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_2PL) || (G6_6PL == 0) +#define MG6_2_16PL ~(1 << 5) +#else +#define MG6_2_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_2PL) || (G6_7PL == 0) +#define MG6_2_17PL ~(1 << 6) +#else +#define MG6_2_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_2PL) || (G6_8PL == 0) +#define MG6_2_18PL ~(1 << 7) +#else +#define MG6_2_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_2PL) || (G6_9PL == 0) +#define MG6_2_19PL ~(1 << 8) +#else +#define MG6_2_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_2PL) || (G6_10PL == 0) +#define MG6_2_110PL ~(1 << 9) +#else +#define MG6_2_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_2PL) || (G6_11PL == 0) +#define MG6_2_111PL ~(1 << 10) +#else +#define MG6_2_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_2PL) || (G6_12PL == 0) +#define MG6_2_112PL ~(1 << 11) +#else +#define MG6_2_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_2PL) || (G6_13PL == 0) +#define MG6_2_113PL ~(1 << 12) +#else +#define MG6_2_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_2PL) || (G6_14PL == 0) +#define MG6_2_114PL ~(1 << 13) +#else +#define MG6_2_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_2PL) || (G6_15PL == 0) +#define MG6_2_115PL ~(1 << 14) +#else +#define MG6_2_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_2PL) || (G6_16PL == 0) +#define MG6_2_116PL ~(1 << 15) +#else +#define MG6_2_116PL 0xFFFF +#endif + +#define MG6_2_12PL 0xFFFD +#define MG6_2 (MG6_2_11PL & MG6_2_12PL & MG6_2_13PL & MG6_2_14PL & \ + MG6_2_15PL & MG6_2_16PL & MG6_2_17PL & MG6_2_18PL & \ + MG6_2_19PL & MG6_2_110PL & MG6_2_111PL & MG6_2_112PL & \ + MG6_2_113PL & MG6_2_114PL & MG6_2_115PL & MG6_2_116PL) +// End of MG6_2: +// Beginning of MG63: +#if (G6_1PL >= G6_3PL) || (G6_1PL == 0) +#define MG6_3_11PL ~(1 << 0) +#else +#define MG6_3_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_3PL) || (G6_2PL == 0) +#define MG6_3_12PL ~(1 << 1) +#else +#define MG6_3_12PL 0xFFFF +#endif + +#if (G6_4PL >= G6_3PL) || (G6_4PL == 0) +#define MG6_3_14PL ~(1 << 3) +#else +#define MG6_3_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_3PL) || (G6_5PL == 0) +#define MG6_3_15PL ~(1 << 4) +#else +#define MG6_3_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_3PL) || (G6_6PL == 0) +#define MG6_3_16PL ~(1 << 5) +#else +#define MG6_3_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_3PL) || (G6_7PL == 0) +#define MG6_3_17PL ~(1 << 6) +#else +#define MG6_3_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_3PL) || (G6_8PL == 0) +#define MG6_3_18PL ~(1 << 7) +#else +#define MG6_3_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_3PL) || (G6_9PL == 0) +#define MG6_3_19PL ~(1 << 8) +#else +#define MG6_3_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_3PL) || (G6_10PL == 0) +#define MG6_3_110PL ~(1 << 9) +#else +#define MG6_3_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_3PL) || (G6_11PL == 0) +#define MG6_3_111PL ~(1 << 10) +#else +#define MG6_3_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_3PL) || (G6_12PL == 0) +#define MG6_3_112PL ~(1 << 11) +#else +#define MG6_3_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_3PL) || (G6_13PL == 0) +#define MG6_3_113PL ~(1 << 12) +#else +#define MG6_3_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_3PL) || (G6_14PL == 0) +#define MG6_3_114PL ~(1 << 13) +#else +#define MG6_3_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_3PL) || (G6_15PL == 0) +#define MG6_3_115PL ~(1 << 14) +#else +#define MG6_3_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_3PL) || (G6_16PL == 0) +#define MG6_3_116PL ~(1 << 15) +#else +#define MG6_3_116PL 0xFFFF +#endif + +#define MG6_3_13PL 0xFFFB +#define MG6_3 (MG6_3_11PL & MG6_3_12PL & MG6_3_13PL & MG6_3_14PL & \ + MG6_3_15PL & MG6_3_16PL & MG6_3_17PL & MG6_3_18PL & \ + MG6_3_19PL & MG6_3_110PL & MG6_3_111PL & MG6_3_112PL & \ + MG6_3_113PL & MG6_3_114PL & MG6_3_115PL & MG6_3_116PL) +// End of MG6_3: +// Beginning of MG64: +#if (G6_1PL >= G6_4PL) || (G6_1PL == 0) +#define MG6_4_11PL ~(1 << 0) +#else +#define MG6_4_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_4PL) || (G6_2PL == 0) +#define MG6_4_12PL ~(1 << 1) +#else +#define MG6_4_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_4PL) || (G6_3PL == 0) +#define MG6_4_13PL ~(1 << 2) +#else +#define MG6_4_13PL 0xFFFF +#endif + +#if (G6_5PL >= G6_4PL) || (G6_5PL == 0) +#define MG6_4_15PL ~(1 << 4) +#else +#define MG6_4_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_4PL) || (G6_6PL == 0) +#define MG6_4_16PL ~(1 << 5) +#else +#define MG6_4_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_4PL) || (G6_7PL == 0) +#define MG6_4_17PL ~(1 << 6) +#else +#define MG6_4_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_4PL) || (G6_8PL == 0) +#define MG6_4_18PL ~(1 << 7) +#else +#define MG6_4_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_4PL) || (G6_9PL == 0) +#define MG6_4_19PL ~(1 << 8) +#else +#define MG6_4_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_4PL) || (G6_10PL == 0) +#define MG6_4_110PL ~(1 << 9) +#else +#define MG6_4_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_4PL) || (G6_11PL == 0) +#define MG6_4_111PL ~(1 << 10) +#else +#define MG6_4_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_4PL) || (G6_12PL == 0) +#define MG6_4_112PL ~(1 << 11) +#else +#define MG6_4_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_4PL) || (G6_13PL == 0) +#define MG6_4_113PL ~(1 << 12) +#else +#define MG6_4_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_4PL) || (G6_14PL == 0) +#define MG6_4_114PL ~(1 << 13) +#else +#define MG6_4_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_4PL) || (G6_15PL == 0) +#define MG6_4_115PL ~(1 << 14) +#else +#define MG6_4_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_4PL) || (G6_16PL == 0) +#define MG6_4_116PL ~(1 << 15) +#else +#define MG6_4_116PL 0xFFFF +#endif + +#define MG6_4_14PL 0xFFF7 +#define MG6_4 (MG6_4_11PL & MG6_4_12PL & MG6_4_13PL & MG6_4_14PL & \ + MG6_4_15PL & MG6_4_16PL & MG6_4_17PL & MG6_4_18PL & \ + MG6_4_19PL & MG6_4_110PL & MG6_4_111PL & MG6_4_112PL & \ + MG6_4_113PL & MG6_4_114PL & MG6_4_115PL & MG6_4_116PL) +// End of MG6_4: +// Beginning of MG65: +#if (G6_1PL >= G6_5PL) || (G6_1PL == 0) +#define MG6_5_11PL ~(1 << 0) +#else +#define MG6_5_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_5PL) || (G6_2PL == 0) +#define MG6_5_12PL ~(1 << 1) +#else +#define MG6_5_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_5PL) || (G6_3PL == 0) +#define MG6_5_13PL ~(1 << 2) +#else +#define MG6_5_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_5PL) || (G6_4PL == 0) +#define MG6_5_14PL ~(1 << 3) +#else +#define MG6_5_14PL 0xFFFF +#endif + +#if (G6_6PL >= G6_5PL) || (G6_6PL == 0) +#define MG6_5_16PL ~(1 << 5) +#else +#define MG6_5_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_5PL) || (G6_7PL == 0) +#define MG6_5_17PL ~(1 << 6) +#else +#define MG6_5_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_5PL) || (G6_8PL == 0) +#define MG6_5_18PL ~(1 << 7) +#else +#define MG6_5_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_5PL) || (G6_9PL == 0) +#define MG6_5_19PL ~(1 << 8) +#else +#define MG6_5_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_5PL) || (G6_10PL == 0) +#define MG6_5_110PL ~(1 << 9) +#else +#define MG6_5_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_5PL) || (G6_11PL == 0) +#define MG6_5_111PL ~(1 << 10) +#else +#define MG6_5_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_5PL) || (G6_12PL == 0) +#define MG6_5_112PL ~(1 << 11) +#else +#define MG6_5_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_5PL) || (G6_13PL == 0) +#define MG6_5_113PL ~(1 << 12) +#else +#define MG6_5_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_5PL) || (G6_14PL == 0) +#define MG6_5_114PL ~(1 << 13) +#else +#define MG6_5_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_5PL) || (G6_15PL == 0) +#define MG6_5_115PL ~(1 << 14) +#else +#define MG6_5_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_5PL) || (G6_16PL == 0) +#define MG6_5_116PL ~(1 << 15) +#else +#define MG6_5_116PL 0xFFFF +#endif + +#define MG6_5_15PL 0xFFEF +#define MG6_5 (MG6_5_11PL & MG6_5_12PL & MG6_5_13PL & MG6_5_14PL & \ + MG6_5_15PL & MG6_5_16PL & MG6_5_17PL & MG6_5_18PL & \ + MG6_5_19PL & MG6_5_110PL & MG6_5_111PL & MG6_5_112PL & \ + MG6_5_113PL & MG6_5_114PL & MG6_5_115PL & MG6_5_116PL) +// End of MG6_5: +// Beginning of MG66: +#if (G6_1PL >= G6_6PL) || (G6_1PL == 0) +#define MG6_6_11PL ~(1 << 0) +#else +#define MG6_6_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_6PL) || (G6_2PL == 0) +#define MG6_6_12PL ~(1 << 1) +#else +#define MG6_6_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_6PL) || (G6_3PL == 0) +#define MG6_6_13PL ~(1 << 2) +#else +#define MG6_6_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_6PL) || (G6_4PL == 0) +#define MG6_6_14PL ~(1 << 3) +#else +#define MG6_6_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_6PL) || (G6_5PL == 0) +#define MG6_6_15PL ~(1 << 4) +#else +#define MG6_6_15PL 0xFFFF +#endif + +#if (G6_7PL >= G6_6PL) || (G6_7PL == 0) +#define MG6_6_17PL ~(1 << 6) +#else +#define MG6_6_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_6PL) || (G6_8PL == 0) +#define MG6_6_18PL ~(1 << 7) +#else +#define MG6_6_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_6PL) || (G6_9PL == 0) +#define MG6_6_19PL ~(1 << 8) +#else +#define MG6_6_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_6PL) || (G6_10PL == 0) +#define MG6_6_110PL ~(1 << 9) +#else +#define MG6_6_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_6PL) || (G6_11PL == 0) +#define MG6_6_111PL ~(1 << 10) +#else +#define MG6_6_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_6PL) || (G6_12PL == 0) +#define MG6_6_112PL ~(1 << 11) +#else +#define MG6_6_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_6PL) || (G6_13PL == 0) +#define MG6_6_113PL ~(1 << 12) +#else +#define MG6_6_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_6PL) || (G6_14PL == 0) +#define MG6_6_114PL ~(1 << 13) +#else +#define MG6_6_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_6PL) || (G6_15PL == 0) +#define MG6_6_115PL ~(1 << 14) +#else +#define MG6_6_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_6PL) || (G6_16PL == 0) +#define MG6_6_116PL ~(1 << 15) +#else +#define MG6_6_116PL 0xFFFF +#endif + +#define MG6_6_16PL 0xFFDF +#define MG6_6 (MG6_6_11PL & MG6_6_12PL & MG6_6_13PL & MG6_6_14PL & \ + MG6_6_15PL & MG6_6_16PL & MG6_6_17PL & MG6_6_18PL & \ + MG6_6_19PL & MG6_6_110PL & MG6_6_111PL & MG6_6_112PL & \ + MG6_6_113PL & MG6_6_114PL & MG6_6_115PL & MG6_6_116PL) +// End of MG6_6: +// Beginning of MG67: +#if (G6_1PL >= G6_7PL) || (G6_1PL == 0) +#define MG6_7_11PL ~(1 << 0) +#else +#define MG6_7_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_7PL) || (G6_2PL == 0) +#define MG6_7_12PL ~(1 << 1) +#else +#define MG6_7_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_7PL) || (G6_3PL == 0) +#define MG6_7_13PL ~(1 << 2) +#else +#define MG6_7_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_7PL) || (G6_4PL == 0) +#define MG6_7_14PL ~(1 << 3) +#else +#define MG6_7_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_7PL) || (G6_5PL == 0) +#define MG6_7_15PL ~(1 << 4) +#else +#define MG6_7_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_7PL) || (G6_6PL == 0) +#define MG6_7_16PL ~(1 << 5) +#else +#define MG6_7_16PL 0xFFFF +#endif + +#if (G6_8PL >= G6_7PL) || (G6_8PL == 0) +#define MG6_7_18PL ~(1 << 7) +#else +#define MG6_7_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_7PL) || (G6_9PL == 0) +#define MG6_7_19PL ~(1 << 8) +#else +#define MG6_7_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_7PL) || (G6_10PL == 0) +#define MG6_7_110PL ~(1 << 9) +#else +#define MG6_7_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_7PL) || (G6_11PL == 0) +#define MG6_7_111PL ~(1 << 10) +#else +#define MG6_7_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_7PL) || (G6_12PL == 0) +#define MG6_7_112PL ~(1 << 11) +#else +#define MG6_7_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_7PL) || (G6_13PL == 0) +#define MG6_7_113PL ~(1 << 12) +#else +#define MG6_7_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_7PL) || (G6_14PL == 0) +#define MG6_7_114PL ~(1 << 13) +#else +#define MG6_7_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_7PL) || (G6_15PL == 0) +#define MG6_7_115PL ~(1 << 14) +#else +#define MG6_7_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_7PL) || (G6_16PL == 0) +#define MG6_7_116PL ~(1 << 15) +#else +#define MG6_7_116PL 0xFFFF +#endif + +#define MG6_7_17PL 0xFFBF +#define MG6_7 (MG6_7_11PL & MG6_7_12PL & MG6_7_13PL & MG6_7_14PL & \ + MG6_7_15PL & MG6_7_16PL & MG6_7_17PL & MG6_7_18PL & \ + MG6_7_19PL & MG6_7_110PL & MG6_7_111PL & MG6_7_112PL & \ + MG6_7_113PL & MG6_7_114PL & MG6_7_115PL & MG6_7_116PL) +// End of MG6_7: +// Beginning of MG68: +#if (G6_1PL >= G6_8PL) || (G6_1PL == 0) +#define MG6_8_11PL ~(1 << 0) +#else +#define MG6_8_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_8PL) || (G6_2PL == 0) +#define MG6_8_12PL ~(1 << 1) +#else +#define MG6_8_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_8PL) || (G6_3PL == 0) +#define MG6_8_13PL ~(1 << 2) +#else +#define MG6_8_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_8PL) || (G6_4PL == 0) +#define MG6_8_14PL ~(1 << 3) +#else +#define MG6_8_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_8PL) || (G6_5PL == 0) +#define MG6_8_15PL ~(1 << 4) +#else +#define MG6_8_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_8PL) || (G6_6PL == 0) +#define MG6_8_16PL ~(1 << 5) +#else +#define MG6_8_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_8PL) || (G6_7PL == 0) +#define MG6_8_17PL ~(1 << 6) +#else +#define MG6_8_17PL 0xFFFF +#endif + +#if (G6_9PL >= G6_8PL) || (G6_9PL == 0) +#define MG6_8_19PL ~(1 << 8) +#else +#define MG6_8_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_8PL) || (G6_10PL == 0) +#define MG6_8_110PL ~(1 << 9) +#else +#define MG6_8_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_8PL) || (G6_11PL == 0) +#define MG6_8_111PL ~(1 << 10) +#else +#define MG6_8_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_8PL) || (G6_12PL == 0) +#define MG6_8_112PL ~(1 << 11) +#else +#define MG6_8_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_8PL) || (G6_13PL == 0) +#define MG6_8_113PL ~(1 << 12) +#else +#define MG6_8_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_8PL) || (G6_14PL == 0) +#define MG6_8_114PL ~(1 << 13) +#else +#define MG6_8_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_8PL) || (G6_15PL == 0) +#define MG6_8_115PL ~(1 << 14) +#else +#define MG6_8_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_8PL) || (G6_16PL == 0) +#define MG6_8_116PL ~(1 << 15) +#else +#define MG6_8_116PL 0xFFFF +#endif + +#define MG6_8_18PL 0xFF7F +#define MG6_8 (MG6_8_11PL & MG6_8_12PL & MG6_8_13PL & MG6_8_14PL & \ + MG6_8_15PL & MG6_8_16PL & MG6_8_17PL & MG6_8_18PL & \ + MG6_8_19PL & MG6_8_110PL & MG6_8_111PL & MG6_8_112PL & \ + MG6_8_113PL & MG6_8_114PL & MG6_8_115PL & MG6_8_116PL) +// End of MG6_8: +// Beginning of MG69: +#if (G6_1PL >= G6_9PL) || (G6_1PL == 0) +#define MG6_9_11PL ~(1 << 0) +#else +#define MG6_9_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_9PL) || (G6_2PL == 0) +#define MG6_9_12PL ~(1 << 1) +#else +#define MG6_9_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_9PL) || (G6_3PL == 0) +#define MG6_9_13PL ~(1 << 2) +#else +#define MG6_9_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_9PL) || (G6_4PL == 0) +#define MG6_9_14PL ~(1 << 3) +#else +#define MG6_9_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_9PL) || (G6_5PL == 0) +#define MG6_9_15PL ~(1 << 4) +#else +#define MG6_9_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_9PL) || (G6_6PL == 0) +#define MG6_9_16PL ~(1 << 5) +#else +#define MG6_9_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_9PL) || (G6_7PL == 0) +#define MG6_9_17PL ~(1 << 6) +#else +#define MG6_9_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_9PL) || (G6_8PL == 0) +#define MG6_9_18PL ~(1 << 7) +#else +#define MG6_9_18PL 0xFFFF +#endif + +#if (G6_10PL >= G6_9PL) || (G6_10PL == 0) +#define MG6_9_110PL ~(1 << 9) +#else +#define MG6_9_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_9PL) || (G6_11PL == 0) +#define MG6_9_111PL ~(1 << 10) +#else +#define MG6_9_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_9PL) || (G6_12PL == 0) +#define MG6_9_112PL ~(1 << 11) +#else +#define MG6_9_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_9PL) || (G6_13PL == 0) +#define MG6_9_113PL ~(1 << 12) +#else +#define MG6_9_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_9PL) || (G6_14PL == 0) +#define MG6_9_114PL ~(1 << 13) +#else +#define MG6_9_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_9PL) || (G6_15PL == 0) +#define MG6_9_115PL ~(1 << 14) +#else +#define MG6_9_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_9PL) || (G6_16PL == 0) +#define MG6_9_116PL ~(1 << 15) +#else +#define MG6_9_116PL 0xFFFF +#endif + +#define MG6_9_19PL 0xFEFF +#define MG6_9 (MG6_9_11PL & MG6_9_12PL & MG6_9_13PL & MG6_9_14PL & \ + MG6_9_15PL & MG6_9_16PL & MG6_9_17PL & MG6_9_18PL & \ + MG6_9_19PL & MG6_9_110PL & MG6_9_111PL & MG6_9_112PL & \ + MG6_9_113PL & MG6_9_114PL & MG6_9_115PL & MG6_9_116PL) +// End of MG6_9: +// Beginning of MG610: +#if (G6_1PL >= G6_10PL) || (G6_1PL == 0) +#define MG6_10_11PL ~(1 << 0) +#else +#define MG6_10_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_10PL) || (G6_2PL == 0) +#define MG6_10_12PL ~(1 << 1) +#else +#define MG6_10_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_10PL) || (G6_3PL == 0) +#define MG6_10_13PL ~(1 << 2) +#else +#define MG6_10_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_10PL) || (G6_4PL == 0) +#define MG6_10_14PL ~(1 << 3) +#else +#define MG6_10_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_10PL) || (G6_5PL == 0) +#define MG6_10_15PL ~(1 << 4) +#else +#define MG6_10_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_10PL) || (G6_6PL == 0) +#define MG6_10_16PL ~(1 << 5) +#else +#define MG6_10_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_10PL) || (G6_7PL == 0) +#define MG6_10_17PL ~(1 << 6) +#else +#define MG6_10_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_10PL) || (G6_8PL == 0) +#define MG6_10_18PL ~(1 << 7) +#else +#define MG6_10_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_10PL) || (G6_9PL == 0) +#define MG6_10_19PL ~(1 << 8) +#else +#define MG6_10_19PL 0xFFFF +#endif + +#if (G6_11PL >= G6_10PL) || (G6_11PL == 0) +#define MG6_10_111PL ~(1 << 10) +#else +#define MG6_10_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_10PL) || (G6_12PL == 0) +#define MG6_10_112PL ~(1 << 11) +#else +#define MG6_10_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_10PL) || (G6_13PL == 0) +#define MG6_10_113PL ~(1 << 12) +#else +#define MG6_10_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_10PL) || (G6_14PL == 0) +#define MG6_10_114PL ~(1 << 13) +#else +#define MG6_10_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_10PL) || (G6_15PL == 0) +#define MG6_10_115PL ~(1 << 14) +#else +#define MG6_10_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_10PL) || (G6_16PL == 0) +#define MG6_10_116PL ~(1 << 15) +#else +#define MG6_10_116PL 0xFFFF +#endif + +#define MG6_10_110PL 0xFDFF +#define MG6_10 (MG6_10_11PL & MG6_10_12PL & MG6_10_13PL & MG6_10_14PL & \ + MG6_10_15PL & MG6_10_16PL & MG6_10_17PL & MG6_10_18PL & \ + MG6_10_19PL & MG6_10_110PL & MG6_10_111PL & MG6_10_112PL & \ + MG6_10_113PL & MG6_10_114PL & MG6_10_115PL & MG6_10_116PL) +// End of MG6_10: +// Beginning of MG611: +#if (G6_1PL >= G6_11PL) || (G6_1PL == 0) +#define MG6_11_11PL ~(1 << 0) +#else +#define MG6_11_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_11PL) || (G6_2PL == 0) +#define MG6_11_12PL ~(1 << 1) +#else +#define MG6_11_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_11PL) || (G6_3PL == 0) +#define MG6_11_13PL ~(1 << 2) +#else +#define MG6_11_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_11PL) || (G6_4PL == 0) +#define MG6_11_14PL ~(1 << 3) +#else +#define MG6_11_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_11PL) || (G6_5PL == 0) +#define MG6_11_15PL ~(1 << 4) +#else +#define MG6_11_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_11PL) || (G6_6PL == 0) +#define MG6_11_16PL ~(1 << 5) +#else +#define MG6_11_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_11PL) || (G6_7PL == 0) +#define MG6_11_17PL ~(1 << 6) +#else +#define MG6_11_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_11PL) || (G6_8PL == 0) +#define MG6_11_18PL ~(1 << 7) +#else +#define MG6_11_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_11PL) || (G6_9PL == 0) +#define MG6_11_19PL ~(1 << 8) +#else +#define MG6_11_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_11PL) || (G6_10PL == 0) +#define MG6_11_110PL ~(1 << 9) +#else +#define MG6_11_110PL 0xFFFF +#endif + +#if (G6_12PL >= G6_11PL) || (G6_12PL == 0) +#define MG6_11_112PL ~(1 << 11) +#else +#define MG6_11_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_11PL) || (G6_13PL == 0) +#define MG6_11_113PL ~(1 << 12) +#else +#define MG6_11_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_11PL) || (G6_14PL == 0) +#define MG6_11_114PL ~(1 << 13) +#else +#define MG6_11_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_11PL) || (G6_15PL == 0) +#define MG6_11_115PL ~(1 << 14) +#else +#define MG6_11_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_11PL) || (G6_16PL == 0) +#define MG6_11_116PL ~(1 << 15) +#else +#define MG6_11_116PL 0xFFFF +#endif + +#define MG6_11_111PL 0xFBFF +#define MG6_11 (MG6_11_11PL & MG6_11_12PL & MG6_11_13PL & MG6_11_14PL & \ + MG6_11_15PL & MG6_11_16PL & MG6_11_17PL & MG6_11_18PL & \ + MG6_11_19PL & MG6_11_110PL & MG6_11_111PL & MG6_11_112PL & \ + MG6_11_113PL & MG6_11_114PL & MG6_11_115PL & MG6_11_116PL) +// End of MG6_11: +// Beginning of MG612: +#if (G6_1PL >= G6_12PL) || (G6_1PL == 0) +#define MG6_12_11PL ~(1 << 0) +#else +#define MG6_12_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_12PL) || (G6_2PL == 0) +#define MG6_12_12PL ~(1 << 1) +#else +#define MG6_12_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_12PL) || (G6_3PL == 0) +#define MG6_12_13PL ~(1 << 2) +#else +#define MG6_12_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_12PL) || (G6_4PL == 0) +#define MG6_12_14PL ~(1 << 3) +#else +#define MG6_12_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_12PL) || (G6_5PL == 0) +#define MG6_12_15PL ~(1 << 4) +#else +#define MG6_12_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_12PL) || (G6_6PL == 0) +#define MG6_12_16PL ~(1 << 5) +#else +#define MG6_12_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_12PL) || (G6_7PL == 0) +#define MG6_12_17PL ~(1 << 6) +#else +#define MG6_12_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_12PL) || (G6_8PL == 0) +#define MG6_12_18PL ~(1 << 7) +#else +#define MG6_12_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_12PL) || (G6_9PL == 0) +#define MG6_12_19PL ~(1 << 8) +#else +#define MG6_12_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_12PL) || (G6_10PL == 0) +#define MG6_12_110PL ~(1 << 9) +#else +#define MG6_12_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_12PL) || (G6_11PL == 0) +#define MG6_12_111PL ~(1 << 10) +#else +#define MG6_12_111PL 0xFFFF +#endif + +#if (G6_13PL >= G6_12PL) || (G6_13PL == 0) +#define MG6_12_113PL ~(1 << 12) +#else +#define MG6_12_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_12PL) || (G6_14PL == 0) +#define MG6_12_114PL ~(1 << 13) +#else +#define MG6_12_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_12PL) || (G6_15PL == 0) +#define MG6_12_115PL ~(1 << 14) +#else +#define MG6_12_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_12PL) || (G6_16PL == 0) +#define MG6_12_116PL ~(1 << 15) +#else +#define MG6_12_116PL 0xFFFF +#endif + +#define MG6_12_112PL 0xF7FF +#define MG6_12 (MG6_12_11PL & MG6_12_12PL & MG6_12_13PL & MG6_12_14PL & \ + MG6_12_15PL & MG6_12_16PL & MG6_12_17PL & MG6_12_18PL & \ + MG6_12_19PL & MG6_12_110PL & MG6_12_111PL & MG6_12_112PL & \ + MG6_12_113PL & MG6_12_114PL & MG6_12_115PL & MG6_12_116PL) +// End of MG6_12: +// Beginning of MG613: +#if (G6_1PL >= G6_13PL) || (G6_1PL == 0) +#define MG6_13_11PL ~(1 << 0) +#else +#define MG6_13_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_13PL) || (G6_2PL == 0) +#define MG6_13_12PL ~(1 << 1) +#else +#define MG6_13_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_13PL) || (G6_3PL == 0) +#define MG6_13_13PL ~(1 << 2) +#else +#define MG6_13_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_13PL) || (G6_4PL == 0) +#define MG6_13_14PL ~(1 << 3) +#else +#define MG6_13_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_13PL) || (G6_5PL == 0) +#define MG6_13_15PL ~(1 << 4) +#else +#define MG6_13_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_13PL) || (G6_6PL == 0) +#define MG6_13_16PL ~(1 << 5) +#else +#define MG6_13_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_13PL) || (G6_7PL == 0) +#define MG6_13_17PL ~(1 << 6) +#else +#define MG6_13_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_13PL) || (G6_8PL == 0) +#define MG6_13_18PL ~(1 << 7) +#else +#define MG6_13_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_13PL) || (G6_9PL == 0) +#define MG6_13_19PL ~(1 << 8) +#else +#define MG6_13_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_13PL) || (G6_10PL == 0) +#define MG6_13_110PL ~(1 << 9) +#else +#define MG6_13_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_13PL) || (G6_11PL == 0) +#define MG6_13_111PL ~(1 << 10) +#else +#define MG6_13_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_13PL) || (G6_12PL == 0) +#define MG6_13_112PL ~(1 << 11) +#else +#define MG6_13_112PL 0xFFFF +#endif + +#if (G6_14PL >= G6_13PL) || (G6_14PL == 0) +#define MG6_13_114PL ~(1 << 13) +#else +#define MG6_13_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_13PL) || (G6_15PL == 0) +#define MG6_13_115PL ~(1 << 14) +#else +#define MG6_13_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_13PL) || (G6_16PL == 0) +#define MG6_13_116PL ~(1 << 15) +#else +#define MG6_13_116PL 0xFFFF +#endif + +#define MG6_13_113PL 0xEFFF +#define MG6_13 (MG6_13_11PL & MG6_13_12PL & MG6_13_13PL & MG6_13_14PL & \ + MG6_13_15PL & MG6_13_16PL & MG6_13_17PL & MG6_13_18PL & \ + MG6_13_19PL & MG6_13_110PL & MG6_13_111PL & MG6_13_112PL & \ + MG6_13_113PL & MG6_13_114PL & MG6_13_115PL & MG6_13_116PL) +// End of MG6_13: +// Beginning of MG614: +#if (G6_1PL >= G6_14PL) || (G6_1PL == 0) +#define MG6_14_11PL ~(1 << 0) +#else +#define MG6_14_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_14PL) || (G6_2PL == 0) +#define MG6_14_12PL ~(1 << 1) +#else +#define MG6_14_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_14PL) || (G6_3PL == 0) +#define MG6_14_13PL ~(1 << 2) +#else +#define MG6_14_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_14PL) || (G6_4PL == 0) +#define MG6_14_14PL ~(1 << 3) +#else +#define MG6_14_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_14PL) || (G6_5PL == 0) +#define MG6_14_15PL ~(1 << 4) +#else +#define MG6_14_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_14PL) || (G6_6PL == 0) +#define MG6_14_16PL ~(1 << 5) +#else +#define MG6_14_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_14PL) || (G6_7PL == 0) +#define MG6_14_17PL ~(1 << 6) +#else +#define MG6_14_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_14PL) || (G6_8PL == 0) +#define MG6_14_18PL ~(1 << 7) +#else +#define MG6_14_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_14PL) || (G6_9PL == 0) +#define MG6_14_19PL ~(1 << 8) +#else +#define MG6_14_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_14PL) || (G6_10PL == 0) +#define MG6_14_110PL ~(1 << 9) +#else +#define MG6_14_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_14PL) || (G6_11PL == 0) +#define MG6_14_111PL ~(1 << 10) +#else +#define MG6_14_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_14PL) || (G6_12PL == 0) +#define MG6_14_112PL ~(1 << 11) +#else +#define MG6_14_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_14PL) || (G6_13PL == 0) +#define MG6_14_113PL ~(1 << 12) +#else +#define MG6_14_113PL 0xFFFF +#endif + +#if (G6_15PL >= G6_14PL) || (G6_15PL == 0) +#define MG6_14_115PL ~(1 << 14) +#else +#define MG6_14_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_14PL) || (G6_16PL == 0) +#define MG6_14_116PL ~(1 << 15) +#else +#define MG6_14_116PL 0xFFFF +#endif + +#define MG6_14_114PL 0xDFFF +#define MG6_14 (MG6_14_11PL & MG6_14_12PL & MG6_14_13PL & MG6_14_14PL & \ + MG6_14_15PL & MG6_14_16PL & MG6_14_17PL & MG6_14_18PL & \ + MG6_14_19PL & MG6_14_110PL & MG6_14_111PL & MG6_14_112PL & \ + MG6_14_113PL & MG6_14_114PL & MG6_14_115PL & MG6_14_116PL) +// End of MG6_14: +// Beginning of MG615: +#if (G6_1PL >= G6_15PL) || (G6_1PL == 0) +#define MG6_15_11PL ~(1 << 0) +#else +#define MG6_15_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_15PL) || (G6_2PL == 0) +#define MG6_15_12PL ~(1 << 1) +#else +#define MG6_15_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_15PL) || (G6_3PL == 0) +#define MG6_15_13PL ~(1 << 2) +#else +#define MG6_15_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_15PL) || (G6_4PL == 0) +#define MG6_15_14PL ~(1 << 3) +#else +#define MG6_15_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_15PL) || (G6_5PL == 0) +#define MG6_15_15PL ~(1 << 4) +#else +#define MG6_15_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_15PL) || (G6_6PL == 0) +#define MG6_15_16PL ~(1 << 5) +#else +#define MG6_15_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_15PL) || (G6_7PL == 0) +#define MG6_15_17PL ~(1 << 6) +#else +#define MG6_15_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_15PL) || (G6_8PL == 0) +#define MG6_15_18PL ~(1 << 7) +#else +#define MG6_15_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_15PL) || (G6_9PL == 0) +#define MG6_15_19PL ~(1 << 8) +#else +#define MG6_15_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_15PL) || (G6_10PL == 0) +#define MG6_15_110PL ~(1 << 9) +#else +#define MG6_15_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_15PL) || (G6_11PL == 0) +#define MG6_15_111PL ~(1 << 10) +#else +#define MG6_15_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_15PL) || (G6_12PL == 0) +#define MG6_15_112PL ~(1 << 11) +#else +#define MG6_15_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_15PL) || (G6_13PL == 0) +#define MG6_15_113PL ~(1 << 12) +#else +#define MG6_15_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_15PL) || (G6_14PL == 0) +#define MG6_15_114PL ~(1 << 13) +#else +#define MG6_15_114PL 0xFFFF +#endif + +#if (G6_16PL >= G6_15PL) || (G6_16PL == 0) +#define MG6_15_116PL ~(1 << 15) +#else +#define MG6_15_116PL 0xFFFF +#endif + +#define MG6_15_115PL 0xBFFF +#define MG6_15 (MG6_15_11PL & MG6_15_12PL & MG6_15_13PL & MG6_15_14PL & \ + MG6_15_15PL & MG6_15_16PL & MG6_15_17PL & MG6_15_18PL & \ + MG6_15_19PL & MG6_15_110PL & MG6_15_111PL & MG6_15_112PL & \ + MG6_15_113PL & MG6_15_114PL & MG6_15_115PL & MG6_15_116PL) +// End of MG6_15: +// Beginning of MG616: +#if (G6_1PL >= G6_16PL) || (G6_1PL == 0) +#define MG6_16_11PL ~(1 << 0) +#else +#define MG6_16_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_16PL) || (G6_2PL == 0) +#define MG6_16_12PL ~(1 << 1) +#else +#define MG6_16_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_16PL) || (G6_3PL == 0) +#define MG6_16_13PL ~(1 << 2) +#else +#define MG6_16_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_16PL) || (G6_4PL == 0) +#define MG6_16_14PL ~(1 << 3) +#else +#define MG6_16_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_16PL) || (G6_5PL == 0) +#define MG6_16_15PL ~(1 << 4) +#else +#define MG6_16_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_16PL) || (G6_6PL == 0) +#define MG6_16_16PL ~(1 << 5) +#else +#define MG6_16_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_16PL) || (G6_7PL == 0) +#define MG6_16_17PL ~(1 << 6) +#else +#define MG6_16_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_16PL) || (G6_8PL == 0) +#define MG6_16_18PL ~(1 << 7) +#else +#define MG6_16_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_16PL) || (G6_9PL == 0) +#define MG6_16_19PL ~(1 << 8) +#else +#define MG6_16_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_16PL) || (G6_10PL == 0) +#define MG6_16_110PL ~(1 << 9) +#else +#define MG6_16_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_16PL) || (G6_11PL == 0) +#define MG6_16_111PL ~(1 << 10) +#else +#define MG6_16_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_16PL) || (G6_12PL == 0) +#define MG6_16_112PL ~(1 << 11) +#else +#define MG6_16_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_16PL) || (G6_13PL == 0) +#define MG6_16_113PL ~(1 << 12) +#else +#define MG6_16_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_16PL) || (G6_14PL == 0) +#define MG6_16_114PL ~(1 << 13) +#else +#define MG6_16_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_16PL) || (G6_15PL == 0) +#define MG6_16_115PL ~(1 << 14) +#else +#define MG6_16_115PL 0xFFFF +#endif + +#define MG6_16_116PL 0x7FFF +#define MG6_16 (MG6_16_11PL & MG6_16_12PL & MG6_16_13PL & MG6_16_14PL & \ + MG6_16_15PL & MG6_16_16PL & MG6_16_17PL & MG6_16_18PL & \ + MG6_16_19PL & MG6_16_110PL & MG6_16_111PL & MG6_16_112PL & \ + MG6_16_113PL & MG6_16_114PL & MG6_16_115PL & MG6_16_116PL) +// End of MG6_16: + + +// +// Automatically generate PIEIER7 interrupt masks MG71 to MG716: +// + +// Beginning of MG71: +#if (G7_2PL >= G7_1PL) || (G7_2PL == 0) +#define MG7_1_12PL ~(1 << 1) +#else +#define MG7_1_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_1PL) || (G7_3PL == 0) +#define MG7_1_13PL ~(1 << 2) +#else +#define MG7_1_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_1PL) || (G7_4PL == 0) +#define MG7_1_14PL ~(1 << 3) +#else +#define MG7_1_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_1PL) || (G7_5PL == 0) +#define MG7_1_15PL ~(1 << 4) +#else +#define MG7_1_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_1PL) || (G7_6PL == 0) +#define MG7_1_16PL ~(1 << 5) +#else +#define MG7_1_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_1PL) || (G7_7PL == 0) +#define MG7_1_17PL ~(1 << 6) +#else +#define MG7_1_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_1PL) || (G7_8PL == 0) +#define MG7_1_18PL ~(1 << 7) +#else +#define MG7_1_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_1PL) || (G7_9PL == 0) +#define MG7_1_19PL ~(1 << 8) +#else +#define MG7_1_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_1PL) || (G7_10PL == 0) +#define MG7_1_110PL ~(1 << 9) +#else +#define MG7_1_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_1PL) || (G7_11PL == 0) +#define MG7_1_111PL ~(1 << 10) +#else +#define MG7_1_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_1PL) || (G7_12PL == 0) +#define MG7_1_112PL ~(1 << 11) +#else +#define MG7_1_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_1PL) || (G7_13PL == 0) +#define MG7_1_113PL ~(1 << 12) +#else +#define MG7_1_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_1PL) || (G7_14PL == 0) +#define MG7_1_114PL ~(1 << 13) +#else +#define MG7_1_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_1PL) || (G7_15PL == 0) +#define MG7_1_115PL ~(1 << 14) +#else +#define MG7_1_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_1PL) || (G7_16PL == 0) +#define MG7_1_116PL ~(1 << 15) +#else +#define MG7_1_116PL 0xFFFF +#endif + +#define MG7_1_11PL 0xFFFE +#define MG7_1 (MG7_1_11PL & MG7_1_12PL & MG7_1_13PL & MG7_1_14PL & \ + MG7_1_15PL & MG7_1_16PL & MG7_1_17PL & MG7_1_18PL & \ + MG7_1_19PL & MG7_1_110PL & MG7_1_111PL & MG7_1_112PL & \ + MG7_1_113PL & MG7_1_114PL & MG7_1_115PL & MG7_1_116PL) +// End of MG7_1: +// Beginning of MG72: +#if (G7_1PL >= G7_2PL) || (G7_1PL == 0) +#define MG7_2_11PL ~(1 << 0) +#else +#define MG7_2_11PL 0xFFFF +#endif + +#if (G7_3PL >= G7_2PL) || (G7_3PL == 0) +#define MG7_2_13PL ~(1 << 2) +#else +#define MG7_2_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_2PL) || (G7_4PL == 0) +#define MG7_2_14PL ~(1 << 3) +#else +#define MG7_2_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_2PL) || (G7_5PL == 0) +#define MG7_2_15PL ~(1 << 4) +#else +#define MG7_2_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_2PL) || (G7_6PL == 0) +#define MG7_2_16PL ~(1 << 5) +#else +#define MG7_2_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_2PL) || (G7_7PL == 0) +#define MG7_2_17PL ~(1 << 6) +#else +#define MG7_2_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_2PL) || (G7_8PL == 0) +#define MG7_2_18PL ~(1 << 7) +#else +#define MG7_2_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_2PL) || (G7_9PL == 0) +#define MG7_2_19PL ~(1 << 8) +#else +#define MG7_2_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_2PL) || (G7_10PL == 0) +#define MG7_2_110PL ~(1 << 9) +#else +#define MG7_2_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_2PL) || (G7_11PL == 0) +#define MG7_2_111PL ~(1 << 10) +#else +#define MG7_2_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_2PL) || (G7_12PL == 0) +#define MG7_2_112PL ~(1 << 11) +#else +#define MG7_2_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_2PL) || (G7_13PL == 0) +#define MG7_2_113PL ~(1 << 12) +#else +#define MG7_2_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_2PL) || (G7_14PL == 0) +#define MG7_2_114PL ~(1 << 13) +#else +#define MG7_2_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_2PL) || (G7_15PL == 0) +#define MG7_2_115PL ~(1 << 14) +#else +#define MG7_2_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_2PL) || (G7_16PL == 0) +#define MG7_2_116PL ~(1 << 15) +#else +#define MG7_2_116PL 0xFFFF +#endif + +#define MG7_2_12PL 0xFFFD +#define MG7_2 (MG7_2_11PL & MG7_2_12PL & MG7_2_13PL & MG7_2_14PL & \ + MG7_2_15PL & MG7_2_16PL & MG7_2_17PL & MG7_2_18PL & \ + MG7_2_19PL & MG7_2_110PL & MG7_2_111PL & MG7_2_112PL & \ + MG7_2_113PL & MG7_2_114PL & MG7_2_115PL & MG7_2_116PL) +// End of MG7_2: +// Beginning of MG73: +#if (G7_1PL >= G7_3PL) || (G7_1PL == 0) +#define MG7_3_11PL ~(1 << 0) +#else +#define MG7_3_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_3PL) || (G7_2PL == 0) +#define MG7_3_12PL ~(1 << 1) +#else +#define MG7_3_12PL 0xFFFF +#endif + +#if (G7_4PL >= G7_3PL) || (G7_4PL == 0) +#define MG7_3_14PL ~(1 << 3) +#else +#define MG7_3_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_3PL) || (G7_5PL == 0) +#define MG7_3_15PL ~(1 << 4) +#else +#define MG7_3_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_3PL) || (G7_6PL == 0) +#define MG7_3_16PL ~(1 << 5) +#else +#define MG7_3_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_3PL) || (G7_7PL == 0) +#define MG7_3_17PL ~(1 << 6) +#else +#define MG7_3_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_3PL) || (G7_8PL == 0) +#define MG7_3_18PL ~(1 << 7) +#else +#define MG7_3_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_3PL) || (G7_9PL == 0) +#define MG7_3_19PL ~(1 << 8) +#else +#define MG7_3_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_3PL) || (G7_10PL == 0) +#define MG7_3_110PL ~(1 << 9) +#else +#define MG7_3_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_3PL) || (G7_11PL == 0) +#define MG7_3_111PL ~(1 << 10) +#else +#define MG7_3_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_3PL) || (G7_12PL == 0) +#define MG7_3_112PL ~(1 << 11) +#else +#define MG7_3_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_3PL) || (G7_13PL == 0) +#define MG7_3_113PL ~(1 << 12) +#else +#define MG7_3_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_3PL) || (G7_14PL == 0) +#define MG7_3_114PL ~(1 << 13) +#else +#define MG7_3_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_3PL) || (G7_15PL == 0) +#define MG7_3_115PL ~(1 << 14) +#else +#define MG7_3_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_3PL) || (G7_16PL == 0) +#define MG7_3_116PL ~(1 << 15) +#else +#define MG7_3_116PL 0xFFFF +#endif + +#define MG7_3_13PL 0xFFFB +#define MG7_3 (MG7_3_11PL & MG7_3_12PL & MG7_3_13PL & MG7_3_14PL & \ + MG7_3_15PL & MG7_3_16PL & MG7_3_17PL & MG7_3_18PL & \ + MG7_3_19PL & MG7_3_110PL & MG7_3_111PL & MG7_3_112PL & \ + MG7_3_113PL & MG7_3_114PL & MG7_3_115PL & MG7_3_116PL) +// End of MG7_3: +// Beginning of MG74: +#if (G7_1PL >= G7_4PL) || (G7_1PL == 0) +#define MG7_4_11PL ~(1 << 0) +#else +#define MG7_4_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_4PL) || (G7_2PL == 0) +#define MG7_4_12PL ~(1 << 1) +#else +#define MG7_4_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_4PL) || (G7_3PL == 0) +#define MG7_4_13PL ~(1 << 2) +#else +#define MG7_4_13PL 0xFFFF +#endif + +#if (G7_5PL >= G7_4PL) || (G7_5PL == 0) +#define MG7_4_15PL ~(1 << 4) +#else +#define MG7_4_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_4PL) || (G7_6PL == 0) +#define MG7_4_16PL ~(1 << 5) +#else +#define MG7_4_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_4PL) || (G7_7PL == 0) +#define MG7_4_17PL ~(1 << 6) +#else +#define MG7_4_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_4PL) || (G7_8PL == 0) +#define MG7_4_18PL ~(1 << 7) +#else +#define MG7_4_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_4PL) || (G7_9PL == 0) +#define MG7_4_19PL ~(1 << 8) +#else +#define MG7_4_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_4PL) || (G7_10PL == 0) +#define MG7_4_110PL ~(1 << 9) +#else +#define MG7_4_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_4PL) || (G7_11PL == 0) +#define MG7_4_111PL ~(1 << 10) +#else +#define MG7_4_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_4PL) || (G7_12PL == 0) +#define MG7_4_112PL ~(1 << 11) +#else +#define MG7_4_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_4PL) || (G7_13PL == 0) +#define MG7_4_113PL ~(1 << 12) +#else +#define MG7_4_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_4PL) || (G7_14PL == 0) +#define MG7_4_114PL ~(1 << 13) +#else +#define MG7_4_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_4PL) || (G7_15PL == 0) +#define MG7_4_115PL ~(1 << 14) +#else +#define MG7_4_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_4PL) || (G7_16PL == 0) +#define MG7_4_116PL ~(1 << 15) +#else +#define MG7_4_116PL 0xFFFF +#endif + +#define MG7_4_14PL 0xFFF7 +#define MG7_4 (MG7_4_11PL & MG7_4_12PL & MG7_4_13PL & MG7_4_14PL & \ + MG7_4_15PL & MG7_4_16PL & MG7_4_17PL & MG7_4_18PL & \ + MG7_4_19PL & MG7_4_110PL & MG7_4_111PL & MG7_4_112PL & \ + MG7_4_113PL & MG7_4_114PL & MG7_4_115PL & MG7_4_116PL) +// End of MG7_4: +// Beginning of MG75: +#if (G7_1PL >= G7_5PL) || (G7_1PL == 0) +#define MG7_5_11PL ~(1 << 0) +#else +#define MG7_5_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_5PL) || (G7_2PL == 0) +#define MG7_5_12PL ~(1 << 1) +#else +#define MG7_5_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_5PL) || (G7_3PL == 0) +#define MG7_5_13PL ~(1 << 2) +#else +#define MG7_5_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_5PL) || (G7_4PL == 0) +#define MG7_5_14PL ~(1 << 3) +#else +#define MG7_5_14PL 0xFFFF +#endif + +#if (G7_6PL >= G7_5PL) || (G7_6PL == 0) +#define MG7_5_16PL ~(1 << 5) +#else +#define MG7_5_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_5PL) || (G7_7PL == 0) +#define MG7_5_17PL ~(1 << 6) +#else +#define MG7_5_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_5PL) || (G7_8PL == 0) +#define MG7_5_18PL ~(1 << 7) +#else +#define MG7_5_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_5PL) || (G7_9PL == 0) +#define MG7_5_19PL ~(1 << 8) +#else +#define MG7_5_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_5PL) || (G7_10PL == 0) +#define MG7_5_110PL ~(1 << 9) +#else +#define MG7_5_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_5PL) || (G7_11PL == 0) +#define MG7_5_111PL ~(1 << 10) +#else +#define MG7_5_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_5PL) || (G7_12PL == 0) +#define MG7_5_112PL ~(1 << 11) +#else +#define MG7_5_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_5PL) || (G7_13PL == 0) +#define MG7_5_113PL ~(1 << 12) +#else +#define MG7_5_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_5PL) || (G7_14PL == 0) +#define MG7_5_114PL ~(1 << 13) +#else +#define MG7_5_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_5PL) || (G7_15PL == 0) +#define MG7_5_115PL ~(1 << 14) +#else +#define MG7_5_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_5PL) || (G7_16PL == 0) +#define MG7_5_116PL ~(1 << 15) +#else +#define MG7_5_116PL 0xFFFF +#endif + +#define MG7_5_15PL 0xFFEF +#define MG7_5 (MG7_5_11PL & MG7_5_12PL & MG7_5_13PL & MG7_5_14PL & \ + MG7_5_15PL & MG7_5_16PL & MG7_5_17PL & MG7_5_18PL & \ + MG7_5_19PL & MG7_5_110PL & MG7_5_111PL & MG7_5_112PL & \ + MG7_5_113PL & MG7_5_114PL & MG7_5_115PL & MG7_5_116PL) +// End of MG7_5: +// Beginning of MG76: +#if (G7_1PL >= G7_6PL) || (G7_1PL == 0) +#define MG7_6_11PL ~(1 << 0) +#else +#define MG7_6_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_6PL) || (G7_2PL == 0) +#define MG7_6_12PL ~(1 << 1) +#else +#define MG7_6_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_6PL) || (G7_3PL == 0) +#define MG7_6_13PL ~(1 << 2) +#else +#define MG7_6_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_6PL) || (G7_4PL == 0) +#define MG7_6_14PL ~(1 << 3) +#else +#define MG7_6_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_6PL) || (G7_5PL == 0) +#define MG7_6_15PL ~(1 << 4) +#else +#define MG7_6_15PL 0xFFFF +#endif + +#if (G7_7PL >= G7_6PL) || (G7_7PL == 0) +#define MG7_6_17PL ~(1 << 6) +#else +#define MG7_6_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_6PL) || (G7_8PL == 0) +#define MG7_6_18PL ~(1 << 7) +#else +#define MG7_6_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_6PL) || (G7_9PL == 0) +#define MG7_6_19PL ~(1 << 8) +#else +#define MG7_6_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_6PL) || (G7_10PL == 0) +#define MG7_6_110PL ~(1 << 9) +#else +#define MG7_6_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_6PL) || (G7_11PL == 0) +#define MG7_6_111PL ~(1 << 10) +#else +#define MG7_6_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_6PL) || (G7_12PL == 0) +#define MG7_6_112PL ~(1 << 11) +#else +#define MG7_6_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_6PL) || (G7_13PL == 0) +#define MG7_6_113PL ~(1 << 12) +#else +#define MG7_6_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_6PL) || (G7_14PL == 0) +#define MG7_6_114PL ~(1 << 13) +#else +#define MG7_6_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_6PL) || (G7_15PL == 0) +#define MG7_6_115PL ~(1 << 14) +#else +#define MG7_6_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_6PL) || (G7_16PL == 0) +#define MG7_6_116PL ~(1 << 15) +#else +#define MG7_6_116PL 0xFFFF +#endif + +#define MG7_6_16PL 0xFFDF +#define MG7_6 (MG7_6_11PL & MG7_6_12PL & MG7_6_13PL & MG7_6_14PL & \ + MG7_6_15PL & MG7_6_16PL & MG7_6_17PL & MG7_6_18PL & \ + MG7_6_19PL & MG7_6_110PL & MG7_6_111PL & MG7_6_112PL & \ + MG7_6_113PL & MG7_6_114PL & MG7_6_115PL & MG7_6_116PL) +// End of MG7_6: +// Beginning of MG77: +#if (G7_1PL >= G7_7PL) || (G7_1PL == 0) +#define MG7_7_11PL ~(1 << 0) +#else +#define MG7_7_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_7PL) || (G7_2PL == 0) +#define MG7_7_12PL ~(1 << 1) +#else +#define MG7_7_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_7PL) || (G7_3PL == 0) +#define MG7_7_13PL ~(1 << 2) +#else +#define MG7_7_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_7PL) || (G7_4PL == 0) +#define MG7_7_14PL ~(1 << 3) +#else +#define MG7_7_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_7PL) || (G7_5PL == 0) +#define MG7_7_15PL ~(1 << 4) +#else +#define MG7_7_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_7PL) || (G7_6PL == 0) +#define MG7_7_16PL ~(1 << 5) +#else +#define MG7_7_16PL 0xFFFF +#endif + +#if (G7_8PL >= G7_7PL) || (G7_8PL == 0) +#define MG7_7_18PL ~(1 << 7) +#else +#define MG7_7_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_7PL) || (G7_9PL == 0) +#define MG7_7_19PL ~(1 << 8) +#else +#define MG7_7_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_7PL) || (G7_10PL == 0) +#define MG7_7_110PL ~(1 << 9) +#else +#define MG7_7_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_7PL) || (G7_11PL == 0) +#define MG7_7_111PL ~(1 << 10) +#else +#define MG7_7_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_7PL) || (G7_12PL == 0) +#define MG7_7_112PL ~(1 << 11) +#else +#define MG7_7_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_7PL) || (G7_13PL == 0) +#define MG7_7_113PL ~(1 << 12) +#else +#define MG7_7_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_7PL) || (G7_14PL == 0) +#define MG7_7_114PL ~(1 << 13) +#else +#define MG7_7_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_7PL) || (G7_15PL == 0) +#define MG7_7_115PL ~(1 << 14) +#else +#define MG7_7_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_7PL) || (G7_16PL == 0) +#define MG7_7_116PL ~(1 << 15) +#else +#define MG7_7_116PL 0xFFFF +#endif + +#define MG7_7_17PL 0xFFBF +#define MG7_7 (MG7_7_11PL & MG7_7_12PL & MG7_7_13PL & MG7_7_14PL & \ + MG7_7_15PL & MG7_7_16PL & MG7_7_17PL & MG7_7_18PL & \ + MG7_7_19PL & MG7_7_110PL & MG7_7_111PL & MG7_7_112PL & \ + MG7_7_113PL & MG7_7_114PL & MG7_7_115PL & MG7_7_116PL) +// End of MG7_7: +// Beginning of MG78: +#if (G7_1PL >= G7_8PL) || (G7_1PL == 0) +#define MG7_8_11PL ~(1 << 0) +#else +#define MG7_8_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_8PL) || (G7_2PL == 0) +#define MG7_8_12PL ~(1 << 1) +#else +#define MG7_8_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_8PL) || (G7_3PL == 0) +#define MG7_8_13PL ~(1 << 2) +#else +#define MG7_8_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_8PL) || (G7_4PL == 0) +#define MG7_8_14PL ~(1 << 3) +#else +#define MG7_8_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_8PL) || (G7_5PL == 0) +#define MG7_8_15PL ~(1 << 4) +#else +#define MG7_8_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_8PL) || (G7_6PL == 0) +#define MG7_8_16PL ~(1 << 5) +#else +#define MG7_8_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_8PL) || (G7_7PL == 0) +#define MG7_8_17PL ~(1 << 6) +#else +#define MG7_8_17PL 0xFFFF +#endif + +#if (G7_9PL >= G7_8PL) || (G7_9PL == 0) +#define MG7_8_19PL ~(1 << 8) +#else +#define MG7_8_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_8PL) || (G7_10PL == 0) +#define MG7_8_110PL ~(1 << 9) +#else +#define MG7_8_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_8PL) || (G7_11PL == 0) +#define MG7_8_111PL ~(1 << 10) +#else +#define MG7_8_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_8PL) || (G7_12PL == 0) +#define MG7_8_112PL ~(1 << 11) +#else +#define MG7_8_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_8PL) || (G7_13PL == 0) +#define MG7_8_113PL ~(1 << 12) +#else +#define MG7_8_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_8PL) || (G7_14PL == 0) +#define MG7_8_114PL ~(1 << 13) +#else +#define MG7_8_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_8PL) || (G7_15PL == 0) +#define MG7_8_115PL ~(1 << 14) +#else +#define MG7_8_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_8PL) || (G7_16PL == 0) +#define MG7_8_116PL ~(1 << 15) +#else +#define MG7_8_116PL 0xFFFF +#endif + +#define MG7_8_18PL 0xFF7F +#define MG7_8 (MG7_8_11PL & MG7_8_12PL & MG7_8_13PL & MG7_8_14PL & \ + MG7_8_15PL & MG7_8_16PL & MG7_8_17PL & MG7_8_18PL & \ + MG7_8_19PL & MG7_8_110PL & MG7_8_111PL & MG7_8_112PL & \ + MG7_8_113PL & MG7_8_114PL & MG7_8_115PL & MG7_8_116PL) +// End of MG7_8: +// Beginning of MG79: +#if (G7_1PL >= G7_9PL) || (G7_1PL == 0) +#define MG7_9_11PL ~(1 << 0) +#else +#define MG7_9_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_9PL) || (G7_2PL == 0) +#define MG7_9_12PL ~(1 << 1) +#else +#define MG7_9_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_9PL) || (G7_3PL == 0) +#define MG7_9_13PL ~(1 << 2) +#else +#define MG7_9_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_9PL) || (G7_4PL == 0) +#define MG7_9_14PL ~(1 << 3) +#else +#define MG7_9_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_9PL) || (G7_5PL == 0) +#define MG7_9_15PL ~(1 << 4) +#else +#define MG7_9_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_9PL) || (G7_6PL == 0) +#define MG7_9_16PL ~(1 << 5) +#else +#define MG7_9_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_9PL) || (G7_7PL == 0) +#define MG7_9_17PL ~(1 << 6) +#else +#define MG7_9_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_9PL) || (G7_8PL == 0) +#define MG7_9_18PL ~(1 << 7) +#else +#define MG7_9_18PL 0xFFFF +#endif + +#if (G7_10PL >= G7_9PL) || (G7_10PL == 0) +#define MG7_9_110PL ~(1 << 9) +#else +#define MG7_9_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_9PL) || (G7_11PL == 0) +#define MG7_9_111PL ~(1 << 10) +#else +#define MG7_9_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_9PL) || (G7_12PL == 0) +#define MG7_9_112PL ~(1 << 11) +#else +#define MG7_9_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_9PL) || (G7_13PL == 0) +#define MG7_9_113PL ~(1 << 12) +#else +#define MG7_9_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_9PL) || (G7_14PL == 0) +#define MG7_9_114PL ~(1 << 13) +#else +#define MG7_9_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_9PL) || (G7_15PL == 0) +#define MG7_9_115PL ~(1 << 14) +#else +#define MG7_9_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_9PL) || (G7_16PL == 0) +#define MG7_9_116PL ~(1 << 15) +#else +#define MG7_9_116PL 0xFFFF +#endif + +#define MG7_9_19PL 0xFEFF +#define MG7_9 (MG7_9_11PL & MG7_9_12PL & MG7_9_13PL & MG7_9_14PL & \ + MG7_9_15PL & MG7_9_16PL & MG7_9_17PL & MG7_9_18PL & \ + MG7_9_19PL & MG7_9_110PL & MG7_9_111PL & MG7_9_112PL & \ + MG7_9_113PL & MG7_9_114PL & MG7_9_115PL & MG7_9_116PL) +// End of MG7_9: +// Beginning of MG710: +#if (G7_1PL >= G7_10PL) || (G7_1PL == 0) +#define MG7_10_11PL ~(1 << 0) +#else +#define MG7_10_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_10PL) || (G7_2PL == 0) +#define MG7_10_12PL ~(1 << 1) +#else +#define MG7_10_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_10PL) || (G7_3PL == 0) +#define MG7_10_13PL ~(1 << 2) +#else +#define MG7_10_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_10PL) || (G7_4PL == 0) +#define MG7_10_14PL ~(1 << 3) +#else +#define MG7_10_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_10PL) || (G7_5PL == 0) +#define MG7_10_15PL ~(1 << 4) +#else +#define MG7_10_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_10PL) || (G7_6PL == 0) +#define MG7_10_16PL ~(1 << 5) +#else +#define MG7_10_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_10PL) || (G7_7PL == 0) +#define MG7_10_17PL ~(1 << 6) +#else +#define MG7_10_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_10PL) || (G7_8PL == 0) +#define MG7_10_18PL ~(1 << 7) +#else +#define MG7_10_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_10PL) || (G7_9PL == 0) +#define MG7_10_19PL ~(1 << 8) +#else +#define MG7_10_19PL 0xFFFF +#endif + +#if (G7_11PL >= G7_10PL) || (G7_11PL == 0) +#define MG7_10_111PL ~(1 << 10) +#else +#define MG7_10_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_10PL) || (G7_12PL == 0) +#define MG7_10_112PL ~(1 << 11) +#else +#define MG7_10_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_10PL) || (G7_13PL == 0) +#define MG7_10_113PL ~(1 << 12) +#else +#define MG7_10_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_10PL) || (G7_14PL == 0) +#define MG7_10_114PL ~(1 << 13) +#else +#define MG7_10_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_10PL) || (G7_15PL == 0) +#define MG7_10_115PL ~(1 << 14) +#else +#define MG7_10_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_10PL) || (G7_16PL == 0) +#define MG7_10_116PL ~(1 << 15) +#else +#define MG7_10_116PL 0xFFFF +#endif + +#define MG7_10_110PL 0xFDFF +#define MG7_10 (MG7_10_11PL & MG7_10_12PL & MG7_10_13PL & MG7_10_14PL & \ + MG7_10_15PL & MG7_10_16PL & MG7_10_17PL & MG7_10_18PL & \ + MG7_10_19PL & MG7_10_110PL & MG7_10_111PL & MG7_10_112PL & \ + MG7_10_113PL & MG7_10_114PL & MG7_10_115PL & MG7_10_116PL) +// End of MG7_10: +// Beginning of MG711: +#if (G7_1PL >= G7_11PL) || (G7_1PL == 0) +#define MG7_11_11PL ~(1 << 0) +#else +#define MG7_11_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_11PL) || (G7_2PL == 0) +#define MG7_11_12PL ~(1 << 1) +#else +#define MG7_11_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_11PL) || (G7_3PL == 0) +#define MG7_11_13PL ~(1 << 2) +#else +#define MG7_11_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_11PL) || (G7_4PL == 0) +#define MG7_11_14PL ~(1 << 3) +#else +#define MG7_11_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_11PL) || (G7_5PL == 0) +#define MG7_11_15PL ~(1 << 4) +#else +#define MG7_11_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_11PL) || (G7_6PL == 0) +#define MG7_11_16PL ~(1 << 5) +#else +#define MG7_11_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_11PL) || (G7_7PL == 0) +#define MG7_11_17PL ~(1 << 6) +#else +#define MG7_11_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_11PL) || (G7_8PL == 0) +#define MG7_11_18PL ~(1 << 7) +#else +#define MG7_11_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_11PL) || (G7_9PL == 0) +#define MG7_11_19PL ~(1 << 8) +#else +#define MG7_11_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_11PL) || (G7_10PL == 0) +#define MG7_11_110PL ~(1 << 9) +#else +#define MG7_11_110PL 0xFFFF +#endif + +#if (G7_12PL >= G7_11PL) || (G7_12PL == 0) +#define MG7_11_112PL ~(1 << 11) +#else +#define MG7_11_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_11PL) || (G7_13PL == 0) +#define MG7_11_113PL ~(1 << 12) +#else +#define MG7_11_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_11PL) || (G7_14PL == 0) +#define MG7_11_114PL ~(1 << 13) +#else +#define MG7_11_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_11PL) || (G7_15PL == 0) +#define MG7_11_115PL ~(1 << 14) +#else +#define MG7_11_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_11PL) || (G7_16PL == 0) +#define MG7_11_116PL ~(1 << 15) +#else +#define MG7_11_116PL 0xFFFF +#endif + +#define MG7_11_111PL 0xFBFF +#define MG7_11 (MG7_11_11PL & MG7_11_12PL & MG7_11_13PL & MG7_11_14PL & \ + MG7_11_15PL & MG7_11_16PL & MG7_11_17PL & MG7_11_18PL & \ + MG7_11_19PL & MG7_11_110PL & MG7_11_111PL & MG7_11_112PL & \ + MG7_11_113PL & MG7_11_114PL & MG7_11_115PL & MG7_11_116PL) +// End of MG7_11: +// Beginning of MG712: +#if (G7_1PL >= G7_12PL) || (G7_1PL == 0) +#define MG7_12_11PL ~(1 << 0) +#else +#define MG7_12_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_12PL) || (G7_2PL == 0) +#define MG7_12_12PL ~(1 << 1) +#else +#define MG7_12_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_12PL) || (G7_3PL == 0) +#define MG7_12_13PL ~(1 << 2) +#else +#define MG7_12_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_12PL) || (G7_4PL == 0) +#define MG7_12_14PL ~(1 << 3) +#else +#define MG7_12_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_12PL) || (G7_5PL == 0) +#define MG7_12_15PL ~(1 << 4) +#else +#define MG7_12_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_12PL) || (G7_6PL == 0) +#define MG7_12_16PL ~(1 << 5) +#else +#define MG7_12_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_12PL) || (G7_7PL == 0) +#define MG7_12_17PL ~(1 << 6) +#else +#define MG7_12_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_12PL) || (G7_8PL == 0) +#define MG7_12_18PL ~(1 << 7) +#else +#define MG7_12_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_12PL) || (G7_9PL == 0) +#define MG7_12_19PL ~(1 << 8) +#else +#define MG7_12_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_12PL) || (G7_10PL == 0) +#define MG7_12_110PL ~(1 << 9) +#else +#define MG7_12_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_12PL) || (G7_11PL == 0) +#define MG7_12_111PL ~(1 << 10) +#else +#define MG7_12_111PL 0xFFFF +#endif + +#if (G7_13PL >= G7_12PL) || (G7_13PL == 0) +#define MG7_12_113PL ~(1 << 12) +#else +#define MG7_12_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_12PL) || (G7_14PL == 0) +#define MG7_12_114PL ~(1 << 13) +#else +#define MG7_12_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_12PL) || (G7_15PL == 0) +#define MG7_12_115PL ~(1 << 14) +#else +#define MG7_12_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_12PL) || (G7_16PL == 0) +#define MG7_12_116PL ~(1 << 15) +#else +#define MG7_12_116PL 0xFFFF +#endif + +#define MG7_12_112PL 0xF7FF +#define MG7_12 (MG7_12_11PL & MG7_12_12PL & MG7_12_13PL & MG7_12_14PL & \ + MG7_12_15PL & MG7_12_16PL & MG7_12_17PL & MG7_12_18PL & \ + MG7_12_19PL & MG7_12_110PL & MG7_12_111PL & MG7_12_112PL & \ + MG7_12_113PL & MG7_12_114PL & MG7_12_115PL & MG7_12_116PL) +// End of MG7_12: +// Beginning of MG713: +#if (G7_1PL >= G7_13PL) || (G7_1PL == 0) +#define MG7_13_11PL ~(1 << 0) +#else +#define MG7_13_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_13PL) || (G7_2PL == 0) +#define MG7_13_12PL ~(1 << 1) +#else +#define MG7_13_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_13PL) || (G7_3PL == 0) +#define MG7_13_13PL ~(1 << 2) +#else +#define MG7_13_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_13PL) || (G7_4PL == 0) +#define MG7_13_14PL ~(1 << 3) +#else +#define MG7_13_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_13PL) || (G7_5PL == 0) +#define MG7_13_15PL ~(1 << 4) +#else +#define MG7_13_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_13PL) || (G7_6PL == 0) +#define MG7_13_16PL ~(1 << 5) +#else +#define MG7_13_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_13PL) || (G7_7PL == 0) +#define MG7_13_17PL ~(1 << 6) +#else +#define MG7_13_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_13PL) || (G7_8PL == 0) +#define MG7_13_18PL ~(1 << 7) +#else +#define MG7_13_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_13PL) || (G7_9PL == 0) +#define MG7_13_19PL ~(1 << 8) +#else +#define MG7_13_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_13PL) || (G7_10PL == 0) +#define MG7_13_110PL ~(1 << 9) +#else +#define MG7_13_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_13PL) || (G7_11PL == 0) +#define MG7_13_111PL ~(1 << 10) +#else +#define MG7_13_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_13PL) || (G7_12PL == 0) +#define MG7_13_112PL ~(1 << 11) +#else +#define MG7_13_112PL 0xFFFF +#endif + +#if (G7_14PL >= G7_13PL) || (G7_14PL == 0) +#define MG7_13_114PL ~(1 << 13) +#else +#define MG7_13_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_13PL) || (G7_15PL == 0) +#define MG7_13_115PL ~(1 << 14) +#else +#define MG7_13_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_13PL) || (G7_16PL == 0) +#define MG7_13_116PL ~(1 << 15) +#else +#define MG7_13_116PL 0xFFFF +#endif + +#define MG7_13_113PL 0xEFFF +#define MG7_13 (MG7_13_11PL & MG7_13_12PL & MG7_13_13PL & MG7_13_14PL & \ + MG7_13_15PL & MG7_13_16PL & MG7_13_17PL & MG7_13_18PL & \ + MG7_13_19PL & MG7_13_110PL & MG7_13_111PL & MG7_13_112PL & \ + MG7_13_113PL & MG7_13_114PL & MG7_13_115PL & MG7_13_116PL) +// End of MG7_13: +// Beginning of MG714: +#if (G7_1PL >= G7_14PL) || (G7_1PL == 0) +#define MG7_14_11PL ~(1 << 0) +#else +#define MG7_14_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_14PL) || (G7_2PL == 0) +#define MG7_14_12PL ~(1 << 1) +#else +#define MG7_14_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_14PL) || (G7_3PL == 0) +#define MG7_14_13PL ~(1 << 2) +#else +#define MG7_14_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_14PL) || (G7_4PL == 0) +#define MG7_14_14PL ~(1 << 3) +#else +#define MG7_14_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_14PL) || (G7_5PL == 0) +#define MG7_14_15PL ~(1 << 4) +#else +#define MG7_14_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_14PL) || (G7_6PL == 0) +#define MG7_14_16PL ~(1 << 5) +#else +#define MG7_14_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_14PL) || (G7_7PL == 0) +#define MG7_14_17PL ~(1 << 6) +#else +#define MG7_14_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_14PL) || (G7_8PL == 0) +#define MG7_14_18PL ~(1 << 7) +#else +#define MG7_14_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_14PL) || (G7_9PL == 0) +#define MG7_14_19PL ~(1 << 8) +#else +#define MG7_14_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_14PL) || (G7_10PL == 0) +#define MG7_14_110PL ~(1 << 9) +#else +#define MG7_14_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_14PL) || (G7_11PL == 0) +#define MG7_14_111PL ~(1 << 10) +#else +#define MG7_14_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_14PL) || (G7_12PL == 0) +#define MG7_14_112PL ~(1 << 11) +#else +#define MG7_14_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_14PL) || (G7_13PL == 0) +#define MG7_14_113PL ~(1 << 12) +#else +#define MG7_14_113PL 0xFFFF +#endif + +#if (G7_15PL >= G7_14PL) || (G7_15PL == 0) +#define MG7_14_115PL ~(1 << 14) +#else +#define MG7_14_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_14PL) || (G7_16PL == 0) +#define MG7_14_116PL ~(1 << 15) +#else +#define MG7_14_116PL 0xFFFF +#endif + +#define MG7_14_114PL 0xDFFF +#define MG7_14 (MG7_14_11PL & MG7_14_12PL & MG7_14_13PL & MG7_14_14PL & \ + MG7_14_15PL & MG7_14_16PL & MG7_14_17PL & MG7_14_18PL & \ + MG7_14_19PL & MG7_14_110PL & MG7_14_111PL & MG7_14_112PL & \ + MG7_14_113PL & MG7_14_114PL & MG7_14_115PL & MG7_14_116PL) +// End of MG7_14: +// Beginning of MG715: +#if (G7_1PL >= G7_15PL) || (G7_1PL == 0) +#define MG7_15_11PL ~(1 << 0) +#else +#define MG7_15_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_15PL) || (G7_2PL == 0) +#define MG7_15_12PL ~(1 << 1) +#else +#define MG7_15_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_15PL) || (G7_3PL == 0) +#define MG7_15_13PL ~(1 << 2) +#else +#define MG7_15_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_15PL) || (G7_4PL == 0) +#define MG7_15_14PL ~(1 << 3) +#else +#define MG7_15_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_15PL) || (G7_5PL == 0) +#define MG7_15_15PL ~(1 << 4) +#else +#define MG7_15_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_15PL) || (G7_6PL == 0) +#define MG7_15_16PL ~(1 << 5) +#else +#define MG7_15_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_15PL) || (G7_7PL == 0) +#define MG7_15_17PL ~(1 << 6) +#else +#define MG7_15_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_15PL) || (G7_8PL == 0) +#define MG7_15_18PL ~(1 << 7) +#else +#define MG7_15_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_15PL) || (G7_9PL == 0) +#define MG7_15_19PL ~(1 << 8) +#else +#define MG7_15_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_15PL) || (G7_10PL == 0) +#define MG7_15_110PL ~(1 << 9) +#else +#define MG7_15_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_15PL) || (G7_11PL == 0) +#define MG7_15_111PL ~(1 << 10) +#else +#define MG7_15_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_15PL) || (G7_12PL == 0) +#define MG7_15_112PL ~(1 << 11) +#else +#define MG7_15_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_15PL) || (G7_13PL == 0) +#define MG7_15_113PL ~(1 << 12) +#else +#define MG7_15_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_15PL) || (G7_14PL == 0) +#define MG7_15_114PL ~(1 << 13) +#else +#define MG7_15_114PL 0xFFFF +#endif + +#if (G7_16PL >= G7_15PL) || (G7_16PL == 0) +#define MG7_15_116PL ~(1 << 15) +#else +#define MG7_15_116PL 0xFFFF +#endif + +#define MG7_15_115PL 0xBFFF +#define MG7_15 (MG7_15_11PL & MG7_15_12PL & MG7_15_13PL & MG7_15_14PL & \ + MG7_15_15PL & MG7_15_16PL & MG7_15_17PL & MG7_15_18PL & \ + MG7_15_19PL & MG7_15_110PL & MG7_15_111PL & MG7_15_112PL & \ + MG7_15_113PL & MG7_15_114PL & MG7_15_115PL & MG7_15_116PL) +// End of MG7_15: +// Beginning of MG716: +#if (G7_1PL >= G7_16PL) || (G7_1PL == 0) +#define MG7_16_11PL ~(1 << 0) +#else +#define MG7_16_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_16PL) || (G7_2PL == 0) +#define MG7_16_12PL ~(1 << 1) +#else +#define MG7_16_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_16PL) || (G7_3PL == 0) +#define MG7_16_13PL ~(1 << 2) +#else +#define MG7_16_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_16PL) || (G7_4PL == 0) +#define MG7_16_14PL ~(1 << 3) +#else +#define MG7_16_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_16PL) || (G7_5PL == 0) +#define MG7_16_15PL ~(1 << 4) +#else +#define MG7_16_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_16PL) || (G7_6PL == 0) +#define MG7_16_16PL ~(1 << 5) +#else +#define MG7_16_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_16PL) || (G7_7PL == 0) +#define MG7_16_17PL ~(1 << 6) +#else +#define MG7_16_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_16PL) || (G7_8PL == 0) +#define MG7_16_18PL ~(1 << 7) +#else +#define MG7_16_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_16PL) || (G7_9PL == 0) +#define MG7_16_19PL ~(1 << 8) +#else +#define MG7_16_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_16PL) || (G7_10PL == 0) +#define MG7_16_110PL ~(1 << 9) +#else +#define MG7_16_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_16PL) || (G7_11PL == 0) +#define MG7_16_111PL ~(1 << 10) +#else +#define MG7_16_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_16PL) || (G7_12PL == 0) +#define MG7_16_112PL ~(1 << 11) +#else +#define MG7_16_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_16PL) || (G7_13PL == 0) +#define MG7_16_113PL ~(1 << 12) +#else +#define MG7_16_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_16PL) || (G7_14PL == 0) +#define MG7_16_114PL ~(1 << 13) +#else +#define MG7_16_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_16PL) || (G7_15PL == 0) +#define MG7_16_115PL ~(1 << 14) +#else +#define MG7_16_115PL 0xFFFF +#endif + +#define MG7_16_116PL 0x7FFF +#define MG7_16 (MG7_16_11PL & MG7_16_12PL & MG7_16_13PL & MG7_16_14PL & \ + MG7_16_15PL & MG7_16_16PL & MG7_16_17PL & MG7_16_18PL & \ + MG7_16_19PL & MG7_16_110PL & MG7_16_111PL & MG7_16_112PL & \ + MG7_16_113PL & MG7_16_114PL & MG7_16_115PL & MG7_16_116PL) +// End of MG7_16: + + +// +// Automatically generate PIEIER8 interrupt masks MG81 to MG816: +// + +// Beginning of MG81: +#if (G8_2PL >= G8_1PL) || (G8_2PL == 0) +#define MG8_1_12PL ~(1 << 1) +#else +#define MG8_1_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_1PL) || (G8_3PL == 0) +#define MG8_1_13PL ~(1 << 2) +#else +#define MG8_1_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_1PL) || (G8_4PL == 0) +#define MG8_1_14PL ~(1 << 3) +#else +#define MG8_1_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_1PL) || (G8_5PL == 0) +#define MG8_1_15PL ~(1 << 4) +#else +#define MG8_1_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_1PL) || (G8_6PL == 0) +#define MG8_1_16PL ~(1 << 5) +#else +#define MG8_1_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_1PL) || (G8_7PL == 0) +#define MG8_1_17PL ~(1 << 6) +#else +#define MG8_1_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_1PL) || (G8_8PL == 0) +#define MG8_1_18PL ~(1 << 7) +#else +#define MG8_1_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_1PL) || (G8_9PL == 0) +#define MG8_1_19PL ~(1 << 8) +#else +#define MG8_1_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_1PL) || (G8_10PL == 0) +#define MG8_1_110PL ~(1 << 9) +#else +#define MG8_1_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_1PL) || (G8_11PL == 0) +#define MG8_1_111PL ~(1 << 10) +#else +#define MG8_1_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_1PL) || (G8_12PL == 0) +#define MG8_1_112PL ~(1 << 11) +#else +#define MG8_1_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_1PL) || (G8_13PL == 0) +#define MG8_1_113PL ~(1 << 12) +#else +#define MG8_1_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_1PL) || (G8_14PL == 0) +#define MG8_1_114PL ~(1 << 13) +#else +#define MG8_1_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_1PL) || (G8_15PL == 0) +#define MG8_1_115PL ~(1 << 14) +#else +#define MG8_1_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_1PL) || (G8_16PL == 0) +#define MG8_1_116PL ~(1 << 15) +#else +#define MG8_1_116PL 0xFFFF +#endif + +#define MG8_1_11PL 0xFFFE +#define MG8_1 (MG8_1_11PL & MG8_1_12PL & MG8_1_13PL & MG8_1_14PL & \ + MG8_1_15PL & MG8_1_16PL & MG8_1_17PL & MG8_1_18PL & \ + MG8_1_19PL & MG8_1_110PL & MG8_1_111PL & MG8_1_112PL & \ + MG8_1_113PL & MG8_1_114PL & MG8_1_115PL & MG8_1_116PL) +// End of MG8_1: +// Beginning of MG82: +#if (G8_1PL >= G8_2PL) || (G8_1PL == 0) +#define MG8_2_11PL ~(1 << 0) +#else +#define MG8_2_11PL 0xFFFF +#endif + +#if (G8_3PL >= G8_2PL) || (G8_3PL == 0) +#define MG8_2_13PL ~(1 << 2) +#else +#define MG8_2_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_2PL) || (G8_4PL == 0) +#define MG8_2_14PL ~(1 << 3) +#else +#define MG8_2_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_2PL) || (G8_5PL == 0) +#define MG8_2_15PL ~(1 << 4) +#else +#define MG8_2_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_2PL) || (G8_6PL == 0) +#define MG8_2_16PL ~(1 << 5) +#else +#define MG8_2_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_2PL) || (G8_7PL == 0) +#define MG8_2_17PL ~(1 << 6) +#else +#define MG8_2_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_2PL) || (G8_8PL == 0) +#define MG8_2_18PL ~(1 << 7) +#else +#define MG8_2_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_2PL) || (G8_9PL == 0) +#define MG8_2_19PL ~(1 << 8) +#else +#define MG8_2_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_2PL) || (G8_10PL == 0) +#define MG8_2_110PL ~(1 << 9) +#else +#define MG8_2_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_2PL) || (G8_11PL == 0) +#define MG8_2_111PL ~(1 << 10) +#else +#define MG8_2_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_2PL) || (G8_12PL == 0) +#define MG8_2_112PL ~(1 << 11) +#else +#define MG8_2_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_2PL) || (G8_13PL == 0) +#define MG8_2_113PL ~(1 << 12) +#else +#define MG8_2_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_2PL) || (G8_14PL == 0) +#define MG8_2_114PL ~(1 << 13) +#else +#define MG8_2_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_2PL) || (G8_15PL == 0) +#define MG8_2_115PL ~(1 << 14) +#else +#define MG8_2_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_2PL) || (G8_16PL == 0) +#define MG8_2_116PL ~(1 << 15) +#else +#define MG8_2_116PL 0xFFFF +#endif + +#define MG8_2_12PL 0xFFFD +#define MG8_2 (MG8_2_11PL & MG8_2_12PL & MG8_2_13PL & MG8_2_14PL & \ + MG8_2_15PL & MG8_2_16PL & MG8_2_17PL & MG8_2_18PL & \ + MG8_2_19PL & MG8_2_110PL & MG8_2_111PL & MG8_2_112PL & \ + MG8_2_113PL & MG8_2_114PL & MG8_2_115PL & MG8_2_116PL) +// End of MG8_2: +// Beginning of MG83: +#if (G8_1PL >= G8_3PL) || (G8_1PL == 0) +#define MG8_3_11PL ~(1 << 0) +#else +#define MG8_3_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_3PL) || (G8_2PL == 0) +#define MG8_3_12PL ~(1 << 1) +#else +#define MG8_3_12PL 0xFFFF +#endif + +#if (G8_4PL >= G8_3PL) || (G8_4PL == 0) +#define MG8_3_14PL ~(1 << 3) +#else +#define MG8_3_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_3PL) || (G8_5PL == 0) +#define MG8_3_15PL ~(1 << 4) +#else +#define MG8_3_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_3PL) || (G8_6PL == 0) +#define MG8_3_16PL ~(1 << 5) +#else +#define MG8_3_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_3PL) || (G8_7PL == 0) +#define MG8_3_17PL ~(1 << 6) +#else +#define MG8_3_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_3PL) || (G8_8PL == 0) +#define MG8_3_18PL ~(1 << 7) +#else +#define MG8_3_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_3PL) || (G8_9PL == 0) +#define MG8_3_19PL ~(1 << 8) +#else +#define MG8_3_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_3PL) || (G8_10PL == 0) +#define MG8_3_110PL ~(1 << 9) +#else +#define MG8_3_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_3PL) || (G8_11PL == 0) +#define MG8_3_111PL ~(1 << 10) +#else +#define MG8_3_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_3PL) || (G8_12PL == 0) +#define MG8_3_112PL ~(1 << 11) +#else +#define MG8_3_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_3PL) || (G8_13PL == 0) +#define MG8_3_113PL ~(1 << 12) +#else +#define MG8_3_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_3PL) || (G8_14PL == 0) +#define MG8_3_114PL ~(1 << 13) +#else +#define MG8_3_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_3PL) || (G8_15PL == 0) +#define MG8_3_115PL ~(1 << 14) +#else +#define MG8_3_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_3PL) || (G8_16PL == 0) +#define MG8_3_116PL ~(1 << 15) +#else +#define MG8_3_116PL 0xFFFF +#endif + +#define MG8_3_13PL 0xFFFB +#define MG8_3 (MG8_3_11PL & MG8_3_12PL & MG8_3_13PL & MG8_3_14PL & \ + MG8_3_15PL & MG8_3_16PL & MG8_3_17PL & MG8_3_18PL & \ + MG8_3_19PL & MG8_3_110PL & MG8_3_111PL & MG8_3_112PL & \ + MG8_3_113PL & MG8_3_114PL & MG8_3_115PL & MG8_3_116PL) +// End of MG8_3: +// Beginning of MG84: +#if (G8_1PL >= G8_4PL) || (G8_1PL == 0) +#define MG8_4_11PL ~(1 << 0) +#else +#define MG8_4_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_4PL) || (G8_2PL == 0) +#define MG8_4_12PL ~(1 << 1) +#else +#define MG8_4_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_4PL) || (G8_3PL == 0) +#define MG8_4_13PL ~(1 << 2) +#else +#define MG8_4_13PL 0xFFFF +#endif + +#if (G8_5PL >= G8_4PL) || (G8_5PL == 0) +#define MG8_4_15PL ~(1 << 4) +#else +#define MG8_4_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_4PL) || (G8_6PL == 0) +#define MG8_4_16PL ~(1 << 5) +#else +#define MG8_4_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_4PL) || (G8_7PL == 0) +#define MG8_4_17PL ~(1 << 6) +#else +#define MG8_4_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_4PL) || (G8_8PL == 0) +#define MG8_4_18PL ~(1 << 7) +#else +#define MG8_4_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_4PL) || (G8_9PL == 0) +#define MG8_4_19PL ~(1 << 8) +#else +#define MG8_4_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_4PL) || (G8_10PL == 0) +#define MG8_4_110PL ~(1 << 9) +#else +#define MG8_4_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_4PL) || (G8_11PL == 0) +#define MG8_4_111PL ~(1 << 10) +#else +#define MG8_4_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_4PL) || (G8_12PL == 0) +#define MG8_4_112PL ~(1 << 11) +#else +#define MG8_4_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_4PL) || (G8_13PL == 0) +#define MG8_4_113PL ~(1 << 12) +#else +#define MG8_4_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_4PL) || (G8_14PL == 0) +#define MG8_4_114PL ~(1 << 13) +#else +#define MG8_4_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_4PL) || (G8_15PL == 0) +#define MG8_4_115PL ~(1 << 14) +#else +#define MG8_4_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_4PL) || (G8_16PL == 0) +#define MG8_4_116PL ~(1 << 15) +#else +#define MG8_4_116PL 0xFFFF +#endif + +#define MG8_4_14PL 0xFFF7 +#define MG8_4 (MG8_4_11PL & MG8_4_12PL & MG8_4_13PL & MG8_4_14PL & \ + MG8_4_15PL & MG8_4_16PL & MG8_4_17PL & MG8_4_18PL & \ + MG8_4_19PL & MG8_4_110PL & MG8_4_111PL & MG8_4_112PL & \ + MG8_4_113PL & MG8_4_114PL & MG8_4_115PL & MG8_4_116PL) +// End of MG8_4: +// Beginning of MG85: +#if (G8_1PL >= G8_5PL) || (G8_1PL == 0) +#define MG8_5_11PL ~(1 << 0) +#else +#define MG8_5_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_5PL) || (G8_2PL == 0) +#define MG8_5_12PL ~(1 << 1) +#else +#define MG8_5_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_5PL) || (G8_3PL == 0) +#define MG8_5_13PL ~(1 << 2) +#else +#define MG8_5_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_5PL) || (G8_4PL == 0) +#define MG8_5_14PL ~(1 << 3) +#else +#define MG8_5_14PL 0xFFFF +#endif + +#if (G8_6PL >= G8_5PL) || (G8_6PL == 0) +#define MG8_5_16PL ~(1 << 5) +#else +#define MG8_5_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_5PL) || (G8_7PL == 0) +#define MG8_5_17PL ~(1 << 6) +#else +#define MG8_5_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_5PL) || (G8_8PL == 0) +#define MG8_5_18PL ~(1 << 7) +#else +#define MG8_5_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_5PL) || (G8_9PL == 0) +#define MG8_5_19PL ~(1 << 8) +#else +#define MG8_5_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_5PL) || (G8_10PL == 0) +#define MG8_5_110PL ~(1 << 9) +#else +#define MG8_5_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_5PL) || (G8_11PL == 0) +#define MG8_5_111PL ~(1 << 10) +#else +#define MG8_5_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_5PL) || (G8_12PL == 0) +#define MG8_5_112PL ~(1 << 11) +#else +#define MG8_5_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_5PL) || (G8_13PL == 0) +#define MG8_5_113PL ~(1 << 12) +#else +#define MG8_5_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_5PL) || (G8_14PL == 0) +#define MG8_5_114PL ~(1 << 13) +#else +#define MG8_5_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_5PL) || (G8_15PL == 0) +#define MG8_5_115PL ~(1 << 14) +#else +#define MG8_5_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_5PL) || (G8_16PL == 0) +#define MG8_5_116PL ~(1 << 15) +#else +#define MG8_5_116PL 0xFFFF +#endif + +#define MG8_5_15PL 0xFFEF +#define MG8_5 (MG8_5_11PL & MG8_5_12PL & MG8_5_13PL & MG8_5_14PL & \ + MG8_5_15PL & MG8_5_16PL & MG8_5_17PL & MG8_5_18PL & \ + MG8_5_19PL & MG8_5_110PL & MG8_5_111PL & MG8_5_112PL & \ + MG8_5_113PL & MG8_5_114PL & MG8_5_115PL & MG8_5_116PL) +// End of MG8_5: +// Beginning of MG86: +#if (G8_1PL >= G8_6PL) || (G8_1PL == 0) +#define MG8_6_11PL ~(1 << 0) +#else +#define MG8_6_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_6PL) || (G8_2PL == 0) +#define MG8_6_12PL ~(1 << 1) +#else +#define MG8_6_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_6PL) || (G8_3PL == 0) +#define MG8_6_13PL ~(1 << 2) +#else +#define MG8_6_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_6PL) || (G8_4PL == 0) +#define MG8_6_14PL ~(1 << 3) +#else +#define MG8_6_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_6PL) || (G8_5PL == 0) +#define MG8_6_15PL ~(1 << 4) +#else +#define MG8_6_15PL 0xFFFF +#endif + +#if (G8_7PL >= G8_6PL) || (G8_7PL == 0) +#define MG8_6_17PL ~(1 << 6) +#else +#define MG8_6_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_6PL) || (G8_8PL == 0) +#define MG8_6_18PL ~(1 << 7) +#else +#define MG8_6_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_6PL) || (G8_9PL == 0) +#define MG8_6_19PL ~(1 << 8) +#else +#define MG8_6_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_6PL) || (G8_10PL == 0) +#define MG8_6_110PL ~(1 << 9) +#else +#define MG8_6_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_6PL) || (G8_11PL == 0) +#define MG8_6_111PL ~(1 << 10) +#else +#define MG8_6_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_6PL) || (G8_12PL == 0) +#define MG8_6_112PL ~(1 << 11) +#else +#define MG8_6_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_6PL) || (G8_13PL == 0) +#define MG8_6_113PL ~(1 << 12) +#else +#define MG8_6_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_6PL) || (G8_14PL == 0) +#define MG8_6_114PL ~(1 << 13) +#else +#define MG8_6_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_6PL) || (G8_15PL == 0) +#define MG8_6_115PL ~(1 << 14) +#else +#define MG8_6_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_6PL) || (G8_16PL == 0) +#define MG8_6_116PL ~(1 << 15) +#else +#define MG8_6_116PL 0xFFFF +#endif + +#define MG8_6_16PL 0xFFDF +#define MG8_6 (MG8_6_11PL & MG8_6_12PL & MG8_6_13PL & MG8_6_14PL & \ + MG8_6_15PL & MG8_6_16PL & MG8_6_17PL & MG8_6_18PL & \ + MG8_6_19PL & MG8_6_110PL & MG8_6_111PL & MG8_6_112PL & \ + MG8_6_113PL & MG8_6_114PL & MG8_6_115PL & MG8_6_116PL) +// End of MG8_6: +// Beginning of MG87: +#if (G8_1PL >= G8_7PL) || (G8_1PL == 0) +#define MG8_7_11PL ~(1 << 0) +#else +#define MG8_7_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_7PL) || (G8_2PL == 0) +#define MG8_7_12PL ~(1 << 1) +#else +#define MG8_7_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_7PL) || (G8_3PL == 0) +#define MG8_7_13PL ~(1 << 2) +#else +#define MG8_7_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_7PL) || (G8_4PL == 0) +#define MG8_7_14PL ~(1 << 3) +#else +#define MG8_7_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_7PL) || (G8_5PL == 0) +#define MG8_7_15PL ~(1 << 4) +#else +#define MG8_7_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_7PL) || (G8_6PL == 0) +#define MG8_7_16PL ~(1 << 5) +#else +#define MG8_7_16PL 0xFFFF +#endif + +#if (G8_8PL >= G8_7PL) || (G8_8PL == 0) +#define MG8_7_18PL ~(1 << 7) +#else +#define MG8_7_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_7PL) || (G8_9PL == 0) +#define MG8_7_19PL ~(1 << 8) +#else +#define MG8_7_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_7PL) || (G8_10PL == 0) +#define MG8_7_110PL ~(1 << 9) +#else +#define MG8_7_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_7PL) || (G8_11PL == 0) +#define MG8_7_111PL ~(1 << 10) +#else +#define MG8_7_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_7PL) || (G8_12PL == 0) +#define MG8_7_112PL ~(1 << 11) +#else +#define MG8_7_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_7PL) || (G8_13PL == 0) +#define MG8_7_113PL ~(1 << 12) +#else +#define MG8_7_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_7PL) || (G8_14PL == 0) +#define MG8_7_114PL ~(1 << 13) +#else +#define MG8_7_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_7PL) || (G8_15PL == 0) +#define MG8_7_115PL ~(1 << 14) +#else +#define MG8_7_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_7PL) || (G8_16PL == 0) +#define MG8_7_116PL ~(1 << 15) +#else +#define MG8_7_116PL 0xFFFF +#endif + +#define MG8_7_17PL 0xFFBF +#define MG8_7 (MG8_7_11PL & MG8_7_12PL & MG8_7_13PL & MG8_7_14PL & \ + MG8_7_15PL & MG8_7_16PL & MG8_7_17PL & MG8_7_18PL & \ + MG8_7_19PL & MG8_7_110PL & MG8_7_111PL & MG8_7_112PL & \ + MG8_7_113PL & MG8_7_114PL & MG8_7_115PL & MG8_7_116PL) +// End of MG8_7: +// Beginning of MG88: +#if (G8_1PL >= G8_8PL) || (G8_1PL == 0) +#define MG8_8_11PL ~(1 << 0) +#else +#define MG8_8_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_8PL) || (G8_2PL == 0) +#define MG8_8_12PL ~(1 << 1) +#else +#define MG8_8_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_8PL) || (G8_3PL == 0) +#define MG8_8_13PL ~(1 << 2) +#else +#define MG8_8_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_8PL) || (G8_4PL == 0) +#define MG8_8_14PL ~(1 << 3) +#else +#define MG8_8_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_8PL) || (G8_5PL == 0) +#define MG8_8_15PL ~(1 << 4) +#else +#define MG8_8_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_8PL) || (G8_6PL == 0) +#define MG8_8_16PL ~(1 << 5) +#else +#define MG8_8_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_8PL) || (G8_7PL == 0) +#define MG8_8_17PL ~(1 << 6) +#else +#define MG8_8_17PL 0xFFFF +#endif + +#if (G8_9PL >= G8_8PL) || (G8_9PL == 0) +#define MG8_8_19PL ~(1 << 8) +#else +#define MG8_8_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_8PL) || (G8_10PL == 0) +#define MG8_8_110PL ~(1 << 9) +#else +#define MG8_8_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_8PL) || (G8_11PL == 0) +#define MG8_8_111PL ~(1 << 10) +#else +#define MG8_8_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_8PL) || (G8_12PL == 0) +#define MG8_8_112PL ~(1 << 11) +#else +#define MG8_8_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_8PL) || (G8_13PL == 0) +#define MG8_8_113PL ~(1 << 12) +#else +#define MG8_8_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_8PL) || (G8_14PL == 0) +#define MG8_8_114PL ~(1 << 13) +#else +#define MG8_8_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_8PL) || (G8_15PL == 0) +#define MG8_8_115PL ~(1 << 14) +#else +#define MG8_8_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_8PL) || (G8_16PL == 0) +#define MG8_8_116PL ~(1 << 15) +#else +#define MG8_8_116PL 0xFFFF +#endif + +#define MG8_8_18PL 0xFF7F +#define MG8_8 (MG8_8_11PL & MG8_8_12PL & MG8_8_13PL & MG8_8_14PL & \ + MG8_8_15PL & MG8_8_16PL & MG8_8_17PL & MG8_8_18PL & \ + MG8_8_19PL & MG8_8_110PL & MG8_8_111PL & MG8_8_112PL & \ + MG8_8_113PL & MG8_8_114PL & MG8_8_115PL & MG8_8_116PL) +// End of MG8_8: +// Beginning of MG89: +#if (G8_1PL >= G8_9PL) || (G8_1PL == 0) +#define MG8_9_11PL ~(1 << 0) +#else +#define MG8_9_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_9PL) || (G8_2PL == 0) +#define MG8_9_12PL ~(1 << 1) +#else +#define MG8_9_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_9PL) || (G8_3PL == 0) +#define MG8_9_13PL ~(1 << 2) +#else +#define MG8_9_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_9PL) || (G8_4PL == 0) +#define MG8_9_14PL ~(1 << 3) +#else +#define MG8_9_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_9PL) || (G8_5PL == 0) +#define MG8_9_15PL ~(1 << 4) +#else +#define MG8_9_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_9PL) || (G8_6PL == 0) +#define MG8_9_16PL ~(1 << 5) +#else +#define MG8_9_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_9PL) || (G8_7PL == 0) +#define MG8_9_17PL ~(1 << 6) +#else +#define MG8_9_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_9PL) || (G8_8PL == 0) +#define MG8_9_18PL ~(1 << 7) +#else +#define MG8_9_18PL 0xFFFF +#endif + +#if (G8_10PL >= G8_9PL) || (G8_10PL == 0) +#define MG8_9_110PL ~(1 << 9) +#else +#define MG8_9_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_9PL) || (G8_11PL == 0) +#define MG8_9_111PL ~(1 << 10) +#else +#define MG8_9_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_9PL) || (G8_12PL == 0) +#define MG8_9_112PL ~(1 << 11) +#else +#define MG8_9_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_9PL) || (G8_13PL == 0) +#define MG8_9_113PL ~(1 << 12) +#else +#define MG8_9_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_9PL) || (G8_14PL == 0) +#define MG8_9_114PL ~(1 << 13) +#else +#define MG8_9_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_9PL) || (G8_15PL == 0) +#define MG8_9_115PL ~(1 << 14) +#else +#define MG8_9_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_9PL) || (G8_16PL == 0) +#define MG8_9_116PL ~(1 << 15) +#else +#define MG8_9_116PL 0xFFFF +#endif + +#define MG8_9_19PL 0xFEFF +#define MG8_9 (MG8_9_11PL & MG8_9_12PL & MG8_9_13PL & MG8_9_14PL & \ + MG8_9_15PL & MG8_9_16PL & MG8_9_17PL & MG8_9_18PL & \ + MG8_9_19PL & MG8_9_110PL & MG8_9_111PL & MG8_9_112PL & \ + MG8_9_113PL & MG8_9_114PL & MG8_9_115PL & MG8_9_116PL) +// End of MG8_9: +// Beginning of MG810: +#if (G8_1PL >= G8_10PL) || (G8_1PL == 0) +#define MG8_10_11PL ~(1 << 0) +#else +#define MG8_10_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_10PL) || (G8_2PL == 0) +#define MG8_10_12PL ~(1 << 1) +#else +#define MG8_10_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_10PL) || (G8_3PL == 0) +#define MG8_10_13PL ~(1 << 2) +#else +#define MG8_10_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_10PL) || (G8_4PL == 0) +#define MG8_10_14PL ~(1 << 3) +#else +#define MG8_10_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_10PL) || (G8_5PL == 0) +#define MG8_10_15PL ~(1 << 4) +#else +#define MG8_10_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_10PL) || (G8_6PL == 0) +#define MG8_10_16PL ~(1 << 5) +#else +#define MG8_10_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_10PL) || (G8_7PL == 0) +#define MG8_10_17PL ~(1 << 6) +#else +#define MG8_10_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_10PL) || (G8_8PL == 0) +#define MG8_10_18PL ~(1 << 7) +#else +#define MG8_10_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_10PL) || (G8_9PL == 0) +#define MG8_10_19PL ~(1 << 8) +#else +#define MG8_10_19PL 0xFFFF +#endif + +#if (G8_11PL >= G8_10PL) || (G8_11PL == 0) +#define MG8_10_111PL ~(1 << 10) +#else +#define MG8_10_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_10PL) || (G8_12PL == 0) +#define MG8_10_112PL ~(1 << 11) +#else +#define MG8_10_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_10PL) || (G8_13PL == 0) +#define MG8_10_113PL ~(1 << 12) +#else +#define MG8_10_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_10PL) || (G8_14PL == 0) +#define MG8_10_114PL ~(1 << 13) +#else +#define MG8_10_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_10PL) || (G8_15PL == 0) +#define MG8_10_115PL ~(1 << 14) +#else +#define MG8_10_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_10PL) || (G8_16PL == 0) +#define MG8_10_116PL ~(1 << 15) +#else +#define MG8_10_116PL 0xFFFF +#endif + +#define MG8_10_110PL 0xFDFF +#define MG8_10 (MG8_10_11PL & MG8_10_12PL & MG8_10_13PL & MG8_10_14PL & \ + MG8_10_15PL & MG8_10_16PL & MG8_10_17PL & MG8_10_18PL & \ + MG8_10_19PL & MG8_10_110PL & MG8_10_111PL & MG8_10_112PL & \ + MG8_10_113PL & MG8_10_114PL & MG8_10_115PL & MG8_10_116PL) +// End of MG8_10: +// Beginning of MG811: +#if (G8_1PL >= G8_11PL) || (G8_1PL == 0) +#define MG8_11_11PL ~(1 << 0) +#else +#define MG8_11_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_11PL) || (G8_2PL == 0) +#define MG8_11_12PL ~(1 << 1) +#else +#define MG8_11_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_11PL) || (G8_3PL == 0) +#define MG8_11_13PL ~(1 << 2) +#else +#define MG8_11_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_11PL) || (G8_4PL == 0) +#define MG8_11_14PL ~(1 << 3) +#else +#define MG8_11_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_11PL) || (G8_5PL == 0) +#define MG8_11_15PL ~(1 << 4) +#else +#define MG8_11_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_11PL) || (G8_6PL == 0) +#define MG8_11_16PL ~(1 << 5) +#else +#define MG8_11_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_11PL) || (G8_7PL == 0) +#define MG8_11_17PL ~(1 << 6) +#else +#define MG8_11_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_11PL) || (G8_8PL == 0) +#define MG8_11_18PL ~(1 << 7) +#else +#define MG8_11_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_11PL) || (G8_9PL == 0) +#define MG8_11_19PL ~(1 << 8) +#else +#define MG8_11_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_11PL) || (G8_10PL == 0) +#define MG8_11_110PL ~(1 << 9) +#else +#define MG8_11_110PL 0xFFFF +#endif + +#if (G8_12PL >= G8_11PL) || (G8_12PL == 0) +#define MG8_11_112PL ~(1 << 11) +#else +#define MG8_11_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_11PL) || (G8_13PL == 0) +#define MG8_11_113PL ~(1 << 12) +#else +#define MG8_11_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_11PL) || (G8_14PL == 0) +#define MG8_11_114PL ~(1 << 13) +#else +#define MG8_11_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_11PL) || (G8_15PL == 0) +#define MG8_11_115PL ~(1 << 14) +#else +#define MG8_11_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_11PL) || (G8_16PL == 0) +#define MG8_11_116PL ~(1 << 15) +#else +#define MG8_11_116PL 0xFFFF +#endif + +#define MG8_11_111PL 0xFBFF +#define MG8_11 (MG8_11_11PL & MG8_11_12PL & MG8_11_13PL & MG8_11_14PL & \ + MG8_11_15PL & MG8_11_16PL & MG8_11_17PL & MG8_11_18PL & \ + MG8_11_19PL & MG8_11_110PL & MG8_11_111PL & MG8_11_112PL & \ + MG8_11_113PL & MG8_11_114PL & MG8_11_115PL & MG8_11_116PL) +// End of MG8_11: +// Beginning of MG812: +#if (G8_1PL >= G8_12PL) || (G8_1PL == 0) +#define MG8_12_11PL ~(1 << 0) +#else +#define MG8_12_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_12PL) || (G8_2PL == 0) +#define MG8_12_12PL ~(1 << 1) +#else +#define MG8_12_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_12PL) || (G8_3PL == 0) +#define MG8_12_13PL ~(1 << 2) +#else +#define MG8_12_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_12PL) || (G8_4PL == 0) +#define MG8_12_14PL ~(1 << 3) +#else +#define MG8_12_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_12PL) || (G8_5PL == 0) +#define MG8_12_15PL ~(1 << 4) +#else +#define MG8_12_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_12PL) || (G8_6PL == 0) +#define MG8_12_16PL ~(1 << 5) +#else +#define MG8_12_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_12PL) || (G8_7PL == 0) +#define MG8_12_17PL ~(1 << 6) +#else +#define MG8_12_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_12PL) || (G8_8PL == 0) +#define MG8_12_18PL ~(1 << 7) +#else +#define MG8_12_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_12PL) || (G8_9PL == 0) +#define MG8_12_19PL ~(1 << 8) +#else +#define MG8_12_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_12PL) || (G8_10PL == 0) +#define MG8_12_110PL ~(1 << 9) +#else +#define MG8_12_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_12PL) || (G8_11PL == 0) +#define MG8_12_111PL ~(1 << 10) +#else +#define MG8_12_111PL 0xFFFF +#endif + +#if (G8_13PL >= G8_12PL) || (G8_13PL == 0) +#define MG8_12_113PL ~(1 << 12) +#else +#define MG8_12_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_12PL) || (G8_14PL == 0) +#define MG8_12_114PL ~(1 << 13) +#else +#define MG8_12_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_12PL) || (G8_15PL == 0) +#define MG8_12_115PL ~(1 << 14) +#else +#define MG8_12_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_12PL) || (G8_16PL == 0) +#define MG8_12_116PL ~(1 << 15) +#else +#define MG8_12_116PL 0xFFFF +#endif + +#define MG8_12_112PL 0xF7FF +#define MG8_12 (MG8_12_11PL & MG8_12_12PL & MG8_12_13PL & MG8_12_14PL & \ + MG8_12_15PL & MG8_12_16PL & MG8_12_17PL & MG8_12_18PL & \ + MG8_12_19PL & MG8_12_110PL & MG8_12_111PL & MG8_12_112PL & \ + MG8_12_113PL & MG8_12_114PL & MG8_12_115PL & MG8_12_116PL) +// End of MG8_12: +// Beginning of MG813: +#if (G8_1PL >= G8_13PL) || (G8_1PL == 0) +#define MG8_13_11PL ~(1 << 0) +#else +#define MG8_13_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_13PL) || (G8_2PL == 0) +#define MG8_13_12PL ~(1 << 1) +#else +#define MG8_13_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_13PL) || (G8_3PL == 0) +#define MG8_13_13PL ~(1 << 2) +#else +#define MG8_13_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_13PL) || (G8_4PL == 0) +#define MG8_13_14PL ~(1 << 3) +#else +#define MG8_13_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_13PL) || (G8_5PL == 0) +#define MG8_13_15PL ~(1 << 4) +#else +#define MG8_13_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_13PL) || (G8_6PL == 0) +#define MG8_13_16PL ~(1 << 5) +#else +#define MG8_13_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_13PL) || (G8_7PL == 0) +#define MG8_13_17PL ~(1 << 6) +#else +#define MG8_13_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_13PL) || (G8_8PL == 0) +#define MG8_13_18PL ~(1 << 7) +#else +#define MG8_13_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_13PL) || (G8_9PL == 0) +#define MG8_13_19PL ~(1 << 8) +#else +#define MG8_13_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_13PL) || (G8_10PL == 0) +#define MG8_13_110PL ~(1 << 9) +#else +#define MG8_13_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_13PL) || (G8_11PL == 0) +#define MG8_13_111PL ~(1 << 10) +#else +#define MG8_13_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_13PL) || (G8_12PL == 0) +#define MG8_13_112PL ~(1 << 11) +#else +#define MG8_13_112PL 0xFFFF +#endif + +#if (G8_14PL >= G8_13PL) || (G8_14PL == 0) +#define MG8_13_114PL ~(1 << 13) +#else +#define MG8_13_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_13PL) || (G8_15PL == 0) +#define MG8_13_115PL ~(1 << 14) +#else +#define MG8_13_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_13PL) || (G8_16PL == 0) +#define MG8_13_116PL ~(1 << 15) +#else +#define MG8_13_116PL 0xFFFF +#endif + +#define MG8_13_113PL 0xEFFF +#define MG8_13 (MG8_13_11PL & MG8_13_12PL & MG8_13_13PL & MG8_13_14PL & \ + MG8_13_15PL & MG8_13_16PL & MG8_13_17PL & MG8_13_18PL & \ + MG8_13_19PL & MG8_13_110PL & MG8_13_111PL & MG8_13_112PL & \ + MG8_13_113PL & MG8_13_114PL & MG8_13_115PL & MG8_13_116PL) +// End of MG8_13: +// Beginning of MG814: +#if (G8_1PL >= G8_14PL) || (G8_1PL == 0) +#define MG8_14_11PL ~(1 << 0) +#else +#define MG8_14_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_14PL) || (G8_2PL == 0) +#define MG8_14_12PL ~(1 << 1) +#else +#define MG8_14_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_14PL) || (G8_3PL == 0) +#define MG8_14_13PL ~(1 << 2) +#else +#define MG8_14_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_14PL) || (G8_4PL == 0) +#define MG8_14_14PL ~(1 << 3) +#else +#define MG8_14_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_14PL) || (G8_5PL == 0) +#define MG8_14_15PL ~(1 << 4) +#else +#define MG8_14_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_14PL) || (G8_6PL == 0) +#define MG8_14_16PL ~(1 << 5) +#else +#define MG8_14_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_14PL) || (G8_7PL == 0) +#define MG8_14_17PL ~(1 << 6) +#else +#define MG8_14_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_14PL) || (G8_8PL == 0) +#define MG8_14_18PL ~(1 << 7) +#else +#define MG8_14_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_14PL) || (G8_9PL == 0) +#define MG8_14_19PL ~(1 << 8) +#else +#define MG8_14_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_14PL) || (G8_10PL == 0) +#define MG8_14_110PL ~(1 << 9) +#else +#define MG8_14_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_14PL) || (G8_11PL == 0) +#define MG8_14_111PL ~(1 << 10) +#else +#define MG8_14_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_14PL) || (G8_12PL == 0) +#define MG8_14_112PL ~(1 << 11) +#else +#define MG8_14_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_14PL) || (G8_13PL == 0) +#define MG8_14_113PL ~(1 << 12) +#else +#define MG8_14_113PL 0xFFFF +#endif + +#if (G8_15PL >= G8_14PL) || (G8_15PL == 0) +#define MG8_14_115PL ~(1 << 14) +#else +#define MG8_14_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_14PL) || (G8_16PL == 0) +#define MG8_14_116PL ~(1 << 15) +#else +#define MG8_14_116PL 0xFFFF +#endif + +#define MG8_14_114PL 0xDFFF +#define MG8_14 (MG8_14_11PL & MG8_14_12PL & MG8_14_13PL & MG8_14_14PL & \ + MG8_14_15PL & MG8_14_16PL & MG8_14_17PL & MG8_14_18PL & \ + MG8_14_19PL & MG8_14_110PL & MG8_14_111PL & MG8_14_112PL & \ + MG8_14_113PL & MG8_14_114PL & MG8_14_115PL & MG8_14_116PL) +// End of MG8_14: +// Beginning of MG815: +#if (G8_1PL >= G8_15PL) || (G8_1PL == 0) +#define MG8_15_11PL ~(1 << 0) +#else +#define MG8_15_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_15PL) || (G8_2PL == 0) +#define MG8_15_12PL ~(1 << 1) +#else +#define MG8_15_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_15PL) || (G8_3PL == 0) +#define MG8_15_13PL ~(1 << 2) +#else +#define MG8_15_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_15PL) || (G8_4PL == 0) +#define MG8_15_14PL ~(1 << 3) +#else +#define MG8_15_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_15PL) || (G8_5PL == 0) +#define MG8_15_15PL ~(1 << 4) +#else +#define MG8_15_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_15PL) || (G8_6PL == 0) +#define MG8_15_16PL ~(1 << 5) +#else +#define MG8_15_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_15PL) || (G8_7PL == 0) +#define MG8_15_17PL ~(1 << 6) +#else +#define MG8_15_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_15PL) || (G8_8PL == 0) +#define MG8_15_18PL ~(1 << 7) +#else +#define MG8_15_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_15PL) || (G8_9PL == 0) +#define MG8_15_19PL ~(1 << 8) +#else +#define MG8_15_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_15PL) || (G8_10PL == 0) +#define MG8_15_110PL ~(1 << 9) +#else +#define MG8_15_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_15PL) || (G8_11PL == 0) +#define MG8_15_111PL ~(1 << 10) +#else +#define MG8_15_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_15PL) || (G8_12PL == 0) +#define MG8_15_112PL ~(1 << 11) +#else +#define MG8_15_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_15PL) || (G8_13PL == 0) +#define MG8_15_113PL ~(1 << 12) +#else +#define MG8_15_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_15PL) || (G8_14PL == 0) +#define MG8_15_114PL ~(1 << 13) +#else +#define MG8_15_114PL 0xFFFF +#endif + +#if (G8_16PL >= G8_15PL) || (G8_16PL == 0) +#define MG8_15_116PL ~(1 << 15) +#else +#define MG8_15_116PL 0xFFFF +#endif + +#define MG8_15_115PL 0xBFFF +#define MG8_15 (MG8_15_11PL & MG8_15_12PL & MG8_15_13PL & MG8_15_14PL & \ + MG8_15_15PL & MG8_15_16PL & MG8_15_17PL & MG8_15_18PL & \ + MG8_15_19PL & MG8_15_110PL & MG8_15_111PL & MG8_15_112PL & \ + MG8_15_113PL & MG8_15_114PL & MG8_15_115PL & MG8_15_116PL) +// End of MG8_15: +// Beginning of MG816: +#if (G8_1PL >= G8_16PL) || (G8_1PL == 0) +#define MG8_16_11PL ~(1 << 0) +#else +#define MG8_16_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_16PL) || (G8_2PL == 0) +#define MG8_16_12PL ~(1 << 1) +#else +#define MG8_16_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_16PL) || (G8_3PL == 0) +#define MG8_16_13PL ~(1 << 2) +#else +#define MG8_16_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_16PL) || (G8_4PL == 0) +#define MG8_16_14PL ~(1 << 3) +#else +#define MG8_16_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_16PL) || (G8_5PL == 0) +#define MG8_16_15PL ~(1 << 4) +#else +#define MG8_16_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_16PL) || (G8_6PL == 0) +#define MG8_16_16PL ~(1 << 5) +#else +#define MG8_16_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_16PL) || (G8_7PL == 0) +#define MG8_16_17PL ~(1 << 6) +#else +#define MG8_16_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_16PL) || (G8_8PL == 0) +#define MG8_16_18PL ~(1 << 7) +#else +#define MG8_16_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_16PL) || (G8_9PL == 0) +#define MG8_16_19PL ~(1 << 8) +#else +#define MG8_16_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_16PL) || (G8_10PL == 0) +#define MG8_16_110PL ~(1 << 9) +#else +#define MG8_16_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_16PL) || (G8_11PL == 0) +#define MG8_16_111PL ~(1 << 10) +#else +#define MG8_16_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_16PL) || (G8_12PL == 0) +#define MG8_16_112PL ~(1 << 11) +#else +#define MG8_16_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_16PL) || (G8_13PL == 0) +#define MG8_16_113PL ~(1 << 12) +#else +#define MG8_16_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_16PL) || (G8_14PL == 0) +#define MG8_16_114PL ~(1 << 13) +#else +#define MG8_16_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_16PL) || (G8_15PL == 0) +#define MG8_16_115PL ~(1 << 14) +#else +#define MG8_16_115PL 0xFFFF +#endif + +#define MG8_16_116PL 0x7FFF +#define MG8_16 (MG8_16_11PL & MG8_16_12PL & MG8_16_13PL & MG8_16_14PL & \ + MG8_16_15PL & MG8_16_16PL & MG8_16_17PL & MG8_16_18PL & \ + MG8_16_19PL & MG8_16_110PL & MG8_16_111PL & MG8_16_112PL & \ + MG8_16_113PL & MG8_16_114PL & MG8_16_115PL & MG8_16_116PL) +// End of MG8_16: + + +// +// Automatically generate PIEIER9 interrupt masks MG91 to MG916: +// + +// Beginning of MG91: +#if (G9_2PL >= G9_1PL) || (G9_2PL == 0) +#define MG9_1_12PL ~(1 << 1) +#else +#define MG9_1_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_1PL) || (G9_3PL == 0) +#define MG9_1_13PL ~(1 << 2) +#else +#define MG9_1_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_1PL) || (G9_4PL == 0) +#define MG9_1_14PL ~(1 << 3) +#else +#define MG9_1_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_1PL) || (G9_5PL == 0) +#define MG9_1_15PL ~(1 << 4) +#else +#define MG9_1_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_1PL) || (G9_6PL == 0) +#define MG9_1_16PL ~(1 << 5) +#else +#define MG9_1_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_1PL) || (G9_7PL == 0) +#define MG9_1_17PL ~(1 << 6) +#else +#define MG9_1_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_1PL) || (G9_8PL == 0) +#define MG9_1_18PL ~(1 << 7) +#else +#define MG9_1_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_1PL) || (G9_9PL == 0) +#define MG9_1_19PL ~(1 << 8) +#else +#define MG9_1_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_1PL) || (G9_10PL == 0) +#define MG9_1_110PL ~(1 << 9) +#else +#define MG9_1_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_1PL) || (G9_11PL == 0) +#define MG9_1_111PL ~(1 << 10) +#else +#define MG9_1_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_1PL) || (G9_12PL == 0) +#define MG9_1_112PL ~(1 << 11) +#else +#define MG9_1_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_1PL) || (G9_13PL == 0) +#define MG9_1_113PL ~(1 << 12) +#else +#define MG9_1_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_1PL) || (G9_14PL == 0) +#define MG9_1_114PL ~(1 << 13) +#else +#define MG9_1_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_1PL) || (G9_15PL == 0) +#define MG9_1_115PL ~(1 << 14) +#else +#define MG9_1_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_1PL) || (G9_16PL == 0) +#define MG9_1_116PL ~(1 << 15) +#else +#define MG9_1_116PL 0xFFFF +#endif + +#define MG9_1_11PL 0xFFFE +#define MG9_1 (MG9_1_11PL & MG9_1_12PL & MG9_1_13PL & MG9_1_14PL & \ + MG9_1_15PL & MG9_1_16PL & MG9_1_17PL & MG9_1_18PL & \ + MG9_1_19PL & MG9_1_110PL & MG9_1_111PL & MG9_1_112PL & \ + MG9_1_113PL & MG9_1_114PL & MG9_1_115PL & MG9_1_116PL) +// End of MG9_1: +// Beginning of MG92: +#if (G9_1PL >= G9_2PL) || (G9_1PL == 0) +#define MG9_2_11PL ~(1 << 0) +#else +#define MG9_2_11PL 0xFFFF +#endif + +#if (G9_3PL >= G9_2PL) || (G9_3PL == 0) +#define MG9_2_13PL ~(1 << 2) +#else +#define MG9_2_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_2PL) || (G9_4PL == 0) +#define MG9_2_14PL ~(1 << 3) +#else +#define MG9_2_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_2PL) || (G9_5PL == 0) +#define MG9_2_15PL ~(1 << 4) +#else +#define MG9_2_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_2PL) || (G9_6PL == 0) +#define MG9_2_16PL ~(1 << 5) +#else +#define MG9_2_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_2PL) || (G9_7PL == 0) +#define MG9_2_17PL ~(1 << 6) +#else +#define MG9_2_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_2PL) || (G9_8PL == 0) +#define MG9_2_18PL ~(1 << 7) +#else +#define MG9_2_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_2PL) || (G9_9PL == 0) +#define MG9_2_19PL ~(1 << 8) +#else +#define MG9_2_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_2PL) || (G9_10PL == 0) +#define MG9_2_110PL ~(1 << 9) +#else +#define MG9_2_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_2PL) || (G9_11PL == 0) +#define MG9_2_111PL ~(1 << 10) +#else +#define MG9_2_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_2PL) || (G9_12PL == 0) +#define MG9_2_112PL ~(1 << 11) +#else +#define MG9_2_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_2PL) || (G9_13PL == 0) +#define MG9_2_113PL ~(1 << 12) +#else +#define MG9_2_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_2PL) || (G9_14PL == 0) +#define MG9_2_114PL ~(1 << 13) +#else +#define MG9_2_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_2PL) || (G9_15PL == 0) +#define MG9_2_115PL ~(1 << 14) +#else +#define MG9_2_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_2PL) || (G9_16PL == 0) +#define MG9_2_116PL ~(1 << 15) +#else +#define MG9_2_116PL 0xFFFF +#endif + +#define MG9_2_12PL 0xFFFD +#define MG9_2 (MG9_2_11PL & MG9_2_12PL & MG9_2_13PL & MG9_2_14PL & \ + MG9_2_15PL & MG9_2_16PL & MG9_2_17PL & MG9_2_18PL & \ + MG9_2_19PL & MG9_2_110PL & MG9_2_111PL & MG9_2_112PL & \ + MG9_2_113PL & MG9_2_114PL & MG9_2_115PL & MG9_2_116PL) +// End of MG9_2: +// Beginning of MG93: +#if (G9_1PL >= G9_3PL) || (G9_1PL == 0) +#define MG9_3_11PL ~(1 << 0) +#else +#define MG9_3_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_3PL) || (G9_2PL == 0) +#define MG9_3_12PL ~(1 << 1) +#else +#define MG9_3_12PL 0xFFFF +#endif + +#if (G9_4PL >= G9_3PL) || (G9_4PL == 0) +#define MG9_3_14PL ~(1 << 3) +#else +#define MG9_3_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_3PL) || (G9_5PL == 0) +#define MG9_3_15PL ~(1 << 4) +#else +#define MG9_3_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_3PL) || (G9_6PL == 0) +#define MG9_3_16PL ~(1 << 5) +#else +#define MG9_3_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_3PL) || (G9_7PL == 0) +#define MG9_3_17PL ~(1 << 6) +#else +#define MG9_3_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_3PL) || (G9_8PL == 0) +#define MG9_3_18PL ~(1 << 7) +#else +#define MG9_3_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_3PL) || (G9_9PL == 0) +#define MG9_3_19PL ~(1 << 8) +#else +#define MG9_3_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_3PL) || (G9_10PL == 0) +#define MG9_3_110PL ~(1 << 9) +#else +#define MG9_3_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_3PL) || (G9_11PL == 0) +#define MG9_3_111PL ~(1 << 10) +#else +#define MG9_3_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_3PL) || (G9_12PL == 0) +#define MG9_3_112PL ~(1 << 11) +#else +#define MG9_3_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_3PL) || (G9_13PL == 0) +#define MG9_3_113PL ~(1 << 12) +#else +#define MG9_3_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_3PL) || (G9_14PL == 0) +#define MG9_3_114PL ~(1 << 13) +#else +#define MG9_3_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_3PL) || (G9_15PL == 0) +#define MG9_3_115PL ~(1 << 14) +#else +#define MG9_3_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_3PL) || (G9_16PL == 0) +#define MG9_3_116PL ~(1 << 15) +#else +#define MG9_3_116PL 0xFFFF +#endif + +#define MG9_3_13PL 0xFFFB +#define MG9_3 (MG9_3_11PL & MG9_3_12PL & MG9_3_13PL & MG9_3_14PL & \ + MG9_3_15PL & MG9_3_16PL & MG9_3_17PL & MG9_3_18PL & \ + MG9_3_19PL & MG9_3_110PL & MG9_3_111PL & MG9_3_112PL & \ + MG9_3_113PL & MG9_3_114PL & MG9_3_115PL & MG9_3_116PL) +// End of MG9_3: +// Beginning of MG94: +#if (G9_1PL >= G9_4PL) || (G9_1PL == 0) +#define MG9_4_11PL ~(1 << 0) +#else +#define MG9_4_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_4PL) || (G9_2PL == 0) +#define MG9_4_12PL ~(1 << 1) +#else +#define MG9_4_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_4PL) || (G9_3PL == 0) +#define MG9_4_13PL ~(1 << 2) +#else +#define MG9_4_13PL 0xFFFF +#endif + +#if (G9_5PL >= G9_4PL) || (G9_5PL == 0) +#define MG9_4_15PL ~(1 << 4) +#else +#define MG9_4_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_4PL) || (G9_6PL == 0) +#define MG9_4_16PL ~(1 << 5) +#else +#define MG9_4_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_4PL) || (G9_7PL == 0) +#define MG9_4_17PL ~(1 << 6) +#else +#define MG9_4_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_4PL) || (G9_8PL == 0) +#define MG9_4_18PL ~(1 << 7) +#else +#define MG9_4_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_4PL) || (G9_9PL == 0) +#define MG9_4_19PL ~(1 << 8) +#else +#define MG9_4_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_4PL) || (G9_10PL == 0) +#define MG9_4_110PL ~(1 << 9) +#else +#define MG9_4_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_4PL) || (G9_11PL == 0) +#define MG9_4_111PL ~(1 << 10) +#else +#define MG9_4_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_4PL) || (G9_12PL == 0) +#define MG9_4_112PL ~(1 << 11) +#else +#define MG9_4_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_4PL) || (G9_13PL == 0) +#define MG9_4_113PL ~(1 << 12) +#else +#define MG9_4_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_4PL) || (G9_14PL == 0) +#define MG9_4_114PL ~(1 << 13) +#else +#define MG9_4_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_4PL) || (G9_15PL == 0) +#define MG9_4_115PL ~(1 << 14) +#else +#define MG9_4_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_4PL) || (G9_16PL == 0) +#define MG9_4_116PL ~(1 << 15) +#else +#define MG9_4_116PL 0xFFFF +#endif + +#define MG9_4_14PL 0xFFF7 +#define MG9_4 (MG9_4_11PL & MG9_4_12PL & MG9_4_13PL & MG9_4_14PL & \ + MG9_4_15PL & MG9_4_16PL & MG9_4_17PL & MG9_4_18PL & \ + MG9_4_19PL & MG9_4_110PL & MG9_4_111PL & MG9_4_112PL & \ + MG9_4_113PL & MG9_4_114PL & MG9_4_115PL & MG9_4_116PL) +// End of MG9_4: +// Beginning of MG95: +#if (G9_1PL >= G9_5PL) || (G9_1PL == 0) +#define MG9_5_11PL ~(1 << 0) +#else +#define MG9_5_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_5PL) || (G9_2PL == 0) +#define MG9_5_12PL ~(1 << 1) +#else +#define MG9_5_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_5PL) || (G9_3PL == 0) +#define MG9_5_13PL ~(1 << 2) +#else +#define MG9_5_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_5PL) || (G9_4PL == 0) +#define MG9_5_14PL ~(1 << 3) +#else +#define MG9_5_14PL 0xFFFF +#endif + +#if (G9_6PL >= G9_5PL) || (G9_6PL == 0) +#define MG9_5_16PL ~(1 << 5) +#else +#define MG9_5_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_5PL) || (G9_7PL == 0) +#define MG9_5_17PL ~(1 << 6) +#else +#define MG9_5_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_5PL) || (G9_8PL == 0) +#define MG9_5_18PL ~(1 << 7) +#else +#define MG9_5_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_5PL) || (G9_9PL == 0) +#define MG9_5_19PL ~(1 << 8) +#else +#define MG9_5_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_5PL) || (G9_10PL == 0) +#define MG9_5_110PL ~(1 << 9) +#else +#define MG9_5_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_5PL) || (G9_11PL == 0) +#define MG9_5_111PL ~(1 << 10) +#else +#define MG9_5_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_5PL) || (G9_12PL == 0) +#define MG9_5_112PL ~(1 << 11) +#else +#define MG9_5_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_5PL) || (G9_13PL == 0) +#define MG9_5_113PL ~(1 << 12) +#else +#define MG9_5_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_5PL) || (G9_14PL == 0) +#define MG9_5_114PL ~(1 << 13) +#else +#define MG9_5_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_5PL) || (G9_15PL == 0) +#define MG9_5_115PL ~(1 << 14) +#else +#define MG9_5_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_5PL) || (G9_16PL == 0) +#define MG9_5_116PL ~(1 << 15) +#else +#define MG9_5_116PL 0xFFFF +#endif + +#define MG9_5_15PL 0xFFEF +#define MG9_5 (MG9_5_11PL & MG9_5_12PL & MG9_5_13PL & MG9_5_14PL & \ + MG9_5_15PL & MG9_5_16PL & MG9_5_17PL & MG9_5_18PL & \ + MG9_5_19PL & MG9_5_110PL & MG9_5_111PL & MG9_5_112PL & \ + MG9_5_113PL & MG9_5_114PL & MG9_5_115PL & MG9_5_116PL) +// End of MG9_5: +// Beginning of MG96: +#if (G9_1PL >= G9_6PL) || (G9_1PL == 0) +#define MG9_6_11PL ~(1 << 0) +#else +#define MG9_6_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_6PL) || (G9_2PL == 0) +#define MG9_6_12PL ~(1 << 1) +#else +#define MG9_6_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_6PL) || (G9_3PL == 0) +#define MG9_6_13PL ~(1 << 2) +#else +#define MG9_6_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_6PL) || (G9_4PL == 0) +#define MG9_6_14PL ~(1 << 3) +#else +#define MG9_6_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_6PL) || (G9_5PL == 0) +#define MG9_6_15PL ~(1 << 4) +#else +#define MG9_6_15PL 0xFFFF +#endif + +#if (G9_7PL >= G9_6PL) || (G9_7PL == 0) +#define MG9_6_17PL ~(1 << 6) +#else +#define MG9_6_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_6PL) || (G9_8PL == 0) +#define MG9_6_18PL ~(1 << 7) +#else +#define MG9_6_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_6PL) || (G9_9PL == 0) +#define MG9_6_19PL ~(1 << 8) +#else +#define MG9_6_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_6PL) || (G9_10PL == 0) +#define MG9_6_110PL ~(1 << 9) +#else +#define MG9_6_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_6PL) || (G9_11PL == 0) +#define MG9_6_111PL ~(1 << 10) +#else +#define MG9_6_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_6PL) || (G9_12PL == 0) +#define MG9_6_112PL ~(1 << 11) +#else +#define MG9_6_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_6PL) || (G9_13PL == 0) +#define MG9_6_113PL ~(1 << 12) +#else +#define MG9_6_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_6PL) || (G9_14PL == 0) +#define MG9_6_114PL ~(1 << 13) +#else +#define MG9_6_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_6PL) || (G9_15PL == 0) +#define MG9_6_115PL ~(1 << 14) +#else +#define MG9_6_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_6PL) || (G9_16PL == 0) +#define MG9_6_116PL ~(1 << 15) +#else +#define MG9_6_116PL 0xFFFF +#endif + +#define MG9_6_16PL 0xFFDF +#define MG9_6 (MG9_6_11PL & MG9_6_12PL & MG9_6_13PL & MG9_6_14PL & \ + MG9_6_15PL & MG9_6_16PL & MG9_6_17PL & MG9_6_18PL & \ + MG9_6_19PL & MG9_6_110PL & MG9_6_111PL & MG9_6_112PL & \ + MG9_6_113PL & MG9_6_114PL & MG9_6_115PL & MG9_6_116PL) +// End of MG9_6: +// Beginning of MG97: +#if (G9_1PL >= G9_7PL) || (G9_1PL == 0) +#define MG9_7_11PL ~(1 << 0) +#else +#define MG9_7_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_7PL) || (G9_2PL == 0) +#define MG9_7_12PL ~(1 << 1) +#else +#define MG9_7_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_7PL) || (G9_3PL == 0) +#define MG9_7_13PL ~(1 << 2) +#else +#define MG9_7_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_7PL) || (G9_4PL == 0) +#define MG9_7_14PL ~(1 << 3) +#else +#define MG9_7_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_7PL) || (G9_5PL == 0) +#define MG9_7_15PL ~(1 << 4) +#else +#define MG9_7_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_7PL) || (G9_6PL == 0) +#define MG9_7_16PL ~(1 << 5) +#else +#define MG9_7_16PL 0xFFFF +#endif + +#if (G9_8PL >= G9_7PL) || (G9_8PL == 0) +#define MG9_7_18PL ~(1 << 7) +#else +#define MG9_7_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_7PL) || (G9_9PL == 0) +#define MG9_7_19PL ~(1 << 8) +#else +#define MG9_7_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_7PL) || (G9_10PL == 0) +#define MG9_7_110PL ~(1 << 9) +#else +#define MG9_7_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_7PL) || (G9_11PL == 0) +#define MG9_7_111PL ~(1 << 10) +#else +#define MG9_7_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_7PL) || (G9_12PL == 0) +#define MG9_7_112PL ~(1 << 11) +#else +#define MG9_7_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_7PL) || (G9_13PL == 0) +#define MG9_7_113PL ~(1 << 12) +#else +#define MG9_7_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_7PL) || (G9_14PL == 0) +#define MG9_7_114PL ~(1 << 13) +#else +#define MG9_7_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_7PL) || (G9_15PL == 0) +#define MG9_7_115PL ~(1 << 14) +#else +#define MG9_7_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_7PL) || (G9_16PL == 0) +#define MG9_7_116PL ~(1 << 15) +#else +#define MG9_7_116PL 0xFFFF +#endif + +#define MG9_7_17PL 0xFFBF +#define MG9_7 (MG9_7_11PL & MG9_7_12PL & MG9_7_13PL & MG9_7_14PL & \ + MG9_7_15PL & MG9_7_16PL & MG9_7_17PL & MG9_7_18PL & \ + MG9_7_19PL & MG9_7_110PL & MG9_7_111PL & MG9_7_112PL & \ + MG9_7_113PL & MG9_7_114PL & MG9_7_115PL & MG9_7_116PL) +// End of MG9_7: +// Beginning of MG98: +#if (G9_1PL >= G9_8PL) || (G9_1PL == 0) +#define MG9_8_11PL ~(1 << 0) +#else +#define MG9_8_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_8PL) || (G9_2PL == 0) +#define MG9_8_12PL ~(1 << 1) +#else +#define MG9_8_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_8PL) || (G9_3PL == 0) +#define MG9_8_13PL ~(1 << 2) +#else +#define MG9_8_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_8PL) || (G9_4PL == 0) +#define MG9_8_14PL ~(1 << 3) +#else +#define MG9_8_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_8PL) || (G9_5PL == 0) +#define MG9_8_15PL ~(1 << 4) +#else +#define MG9_8_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_8PL) || (G9_6PL == 0) +#define MG9_8_16PL ~(1 << 5) +#else +#define MG9_8_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_8PL) || (G9_7PL == 0) +#define MG9_8_17PL ~(1 << 6) +#else +#define MG9_8_17PL 0xFFFF +#endif + +#if (G9_9PL >= G9_8PL) || (G9_9PL == 0) +#define MG9_8_19PL ~(1 << 8) +#else +#define MG9_8_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_8PL) || (G9_10PL == 0) +#define MG9_8_110PL ~(1 << 9) +#else +#define MG9_8_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_8PL) || (G9_11PL == 0) +#define MG9_8_111PL ~(1 << 10) +#else +#define MG9_8_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_8PL) || (G9_12PL == 0) +#define MG9_8_112PL ~(1 << 11) +#else +#define MG9_8_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_8PL) || (G9_13PL == 0) +#define MG9_8_113PL ~(1 << 12) +#else +#define MG9_8_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_8PL) || (G9_14PL == 0) +#define MG9_8_114PL ~(1 << 13) +#else +#define MG9_8_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_8PL) || (G9_15PL == 0) +#define MG9_8_115PL ~(1 << 14) +#else +#define MG9_8_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_8PL) || (G9_16PL == 0) +#define MG9_8_116PL ~(1 << 15) +#else +#define MG9_8_116PL 0xFFFF +#endif + +#define MG9_8_18PL 0xFF7F +#define MG9_8 (MG9_8_11PL & MG9_8_12PL & MG9_8_13PL & MG9_8_14PL & \ + MG9_8_15PL & MG9_8_16PL & MG9_8_17PL & MG9_8_18PL & \ + MG9_8_19PL & MG9_8_110PL & MG9_8_111PL & MG9_8_112PL & \ + MG9_8_113PL & MG9_8_114PL & MG9_8_115PL & MG9_8_116PL) +// End of MG9_8: +// Beginning of MG99: +#if (G9_1PL >= G9_9PL) || (G9_1PL == 0) +#define MG9_9_11PL ~(1 << 0) +#else +#define MG9_9_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_9PL) || (G9_2PL == 0) +#define MG9_9_12PL ~(1 << 1) +#else +#define MG9_9_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_9PL) || (G9_3PL == 0) +#define MG9_9_13PL ~(1 << 2) +#else +#define MG9_9_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_9PL) || (G9_4PL == 0) +#define MG9_9_14PL ~(1 << 3) +#else +#define MG9_9_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_9PL) || (G9_5PL == 0) +#define MG9_9_15PL ~(1 << 4) +#else +#define MG9_9_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_9PL) || (G9_6PL == 0) +#define MG9_9_16PL ~(1 << 5) +#else +#define MG9_9_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_9PL) || (G9_7PL == 0) +#define MG9_9_17PL ~(1 << 6) +#else +#define MG9_9_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_9PL) || (G9_8PL == 0) +#define MG9_9_18PL ~(1 << 7) +#else +#define MG9_9_18PL 0xFFFF +#endif + +#if (G9_10PL >= G9_9PL) || (G9_10PL == 0) +#define MG9_9_110PL ~(1 << 9) +#else +#define MG9_9_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_9PL) || (G9_11PL == 0) +#define MG9_9_111PL ~(1 << 10) +#else +#define MG9_9_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_9PL) || (G9_12PL == 0) +#define MG9_9_112PL ~(1 << 11) +#else +#define MG9_9_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_9PL) || (G9_13PL == 0) +#define MG9_9_113PL ~(1 << 12) +#else +#define MG9_9_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_9PL) || (G9_14PL == 0) +#define MG9_9_114PL ~(1 << 13) +#else +#define MG9_9_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_9PL) || (G9_15PL == 0) +#define MG9_9_115PL ~(1 << 14) +#else +#define MG9_9_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_9PL) || (G9_16PL == 0) +#define MG9_9_116PL ~(1 << 15) +#else +#define MG9_9_116PL 0xFFFF +#endif + +#define MG9_9_19PL 0xFEFF +#define MG9_9 (MG9_9_11PL & MG9_9_12PL & MG9_9_13PL & MG9_9_14PL & \ + MG9_9_15PL & MG9_9_16PL & MG9_9_17PL & MG9_9_18PL & \ + MG9_9_19PL & MG9_9_110PL & MG9_9_111PL & MG9_9_112PL & \ + MG9_9_113PL & MG9_9_114PL & MG9_9_115PL & MG9_9_116PL) +// End of MG9_9: +// Beginning of MG910: +#if (G9_1PL >= G9_10PL) || (G9_1PL == 0) +#define MG9_10_11PL ~(1 << 0) +#else +#define MG9_10_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_10PL) || (G9_2PL == 0) +#define MG9_10_12PL ~(1 << 1) +#else +#define MG9_10_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_10PL) || (G9_3PL == 0) +#define MG9_10_13PL ~(1 << 2) +#else +#define MG9_10_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_10PL) || (G9_4PL == 0) +#define MG9_10_14PL ~(1 << 3) +#else +#define MG9_10_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_10PL) || (G9_5PL == 0) +#define MG9_10_15PL ~(1 << 4) +#else +#define MG9_10_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_10PL) || (G9_6PL == 0) +#define MG9_10_16PL ~(1 << 5) +#else +#define MG9_10_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_10PL) || (G9_7PL == 0) +#define MG9_10_17PL ~(1 << 6) +#else +#define MG9_10_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_10PL) || (G9_8PL == 0) +#define MG9_10_18PL ~(1 << 7) +#else +#define MG9_10_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_10PL) || (G9_9PL == 0) +#define MG9_10_19PL ~(1 << 8) +#else +#define MG9_10_19PL 0xFFFF +#endif + +#if (G9_11PL >= G9_10PL) || (G9_11PL == 0) +#define MG9_10_111PL ~(1 << 10) +#else +#define MG9_10_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_10PL) || (G9_12PL == 0) +#define MG9_10_112PL ~(1 << 11) +#else +#define MG9_10_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_10PL) || (G9_13PL == 0) +#define MG9_10_113PL ~(1 << 12) +#else +#define MG9_10_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_10PL) || (G9_14PL == 0) +#define MG9_10_114PL ~(1 << 13) +#else +#define MG9_10_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_10PL) || (G9_15PL == 0) +#define MG9_10_115PL ~(1 << 14) +#else +#define MG9_10_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_10PL) || (G9_16PL == 0) +#define MG9_10_116PL ~(1 << 15) +#else +#define MG9_10_116PL 0xFFFF +#endif + +#define MG9_10_110PL 0xFDFF +#define MG9_10 (MG9_10_11PL & MG9_10_12PL & MG9_10_13PL & MG9_10_14PL & \ + MG9_10_15PL & MG9_10_16PL & MG9_10_17PL & MG9_10_18PL & \ + MG9_10_19PL & MG9_10_110PL & MG9_10_111PL & MG9_10_112PL & \ + MG9_10_113PL & MG9_10_114PL & MG9_10_115PL & MG9_10_116PL) +// End of MG9_10: +// Beginning of MG911: +#if (G9_1PL >= G9_11PL) || (G9_1PL == 0) +#define MG9_11_11PL ~(1 << 0) +#else +#define MG9_11_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_11PL) || (G9_2PL == 0) +#define MG9_11_12PL ~(1 << 1) +#else +#define MG9_11_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_11PL) || (G9_3PL == 0) +#define MG9_11_13PL ~(1 << 2) +#else +#define MG9_11_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_11PL) || (G9_4PL == 0) +#define MG9_11_14PL ~(1 << 3) +#else +#define MG9_11_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_11PL) || (G9_5PL == 0) +#define MG9_11_15PL ~(1 << 4) +#else +#define MG9_11_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_11PL) || (G9_6PL == 0) +#define MG9_11_16PL ~(1 << 5) +#else +#define MG9_11_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_11PL) || (G9_7PL == 0) +#define MG9_11_17PL ~(1 << 6) +#else +#define MG9_11_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_11PL) || (G9_8PL == 0) +#define MG9_11_18PL ~(1 << 7) +#else +#define MG9_11_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_11PL) || (G9_9PL == 0) +#define MG9_11_19PL ~(1 << 8) +#else +#define MG9_11_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_11PL) || (G9_10PL == 0) +#define MG9_11_110PL ~(1 << 9) +#else +#define MG9_11_110PL 0xFFFF +#endif + +#if (G9_12PL >= G9_11PL) || (G9_12PL == 0) +#define MG9_11_112PL ~(1 << 11) +#else +#define MG9_11_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_11PL) || (G9_13PL == 0) +#define MG9_11_113PL ~(1 << 12) +#else +#define MG9_11_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_11PL) || (G9_14PL == 0) +#define MG9_11_114PL ~(1 << 13) +#else +#define MG9_11_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_11PL) || (G9_15PL == 0) +#define MG9_11_115PL ~(1 << 14) +#else +#define MG9_11_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_11PL) || (G9_16PL == 0) +#define MG9_11_116PL ~(1 << 15) +#else +#define MG9_11_116PL 0xFFFF +#endif + +#define MG9_11_111PL 0xFBFF +#define MG9_11 (MG9_11_11PL & MG9_11_12PL & MG9_11_13PL & MG9_11_14PL & \ + MG9_11_15PL & MG9_11_16PL & MG9_11_17PL & MG9_11_18PL & \ + MG9_11_19PL & MG9_11_110PL & MG9_11_111PL & MG9_11_112PL & \ + MG9_11_113PL & MG9_11_114PL & MG9_11_115PL & MG9_11_116PL) +// End of MG9_11: +// Beginning of MG912: +#if (G9_1PL >= G9_12PL) || (G9_1PL == 0) +#define MG9_12_11PL ~(1 << 0) +#else +#define MG9_12_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_12PL) || (G9_2PL == 0) +#define MG9_12_12PL ~(1 << 1) +#else +#define MG9_12_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_12PL) || (G9_3PL == 0) +#define MG9_12_13PL ~(1 << 2) +#else +#define MG9_12_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_12PL) || (G9_4PL == 0) +#define MG9_12_14PL ~(1 << 3) +#else +#define MG9_12_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_12PL) || (G9_5PL == 0) +#define MG9_12_15PL ~(1 << 4) +#else +#define MG9_12_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_12PL) || (G9_6PL == 0) +#define MG9_12_16PL ~(1 << 5) +#else +#define MG9_12_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_12PL) || (G9_7PL == 0) +#define MG9_12_17PL ~(1 << 6) +#else +#define MG9_12_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_12PL) || (G9_8PL == 0) +#define MG9_12_18PL ~(1 << 7) +#else +#define MG9_12_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_12PL) || (G9_9PL == 0) +#define MG9_12_19PL ~(1 << 8) +#else +#define MG9_12_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_12PL) || (G9_10PL == 0) +#define MG9_12_110PL ~(1 << 9) +#else +#define MG9_12_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_12PL) || (G9_11PL == 0) +#define MG9_12_111PL ~(1 << 10) +#else +#define MG9_12_111PL 0xFFFF +#endif + +#if (G9_13PL >= G9_12PL) || (G9_13PL == 0) +#define MG9_12_113PL ~(1 << 12) +#else +#define MG9_12_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_12PL) || (G9_14PL == 0) +#define MG9_12_114PL ~(1 << 13) +#else +#define MG9_12_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_12PL) || (G9_15PL == 0) +#define MG9_12_115PL ~(1 << 14) +#else +#define MG9_12_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_12PL) || (G9_16PL == 0) +#define MG9_12_116PL ~(1 << 15) +#else +#define MG9_12_116PL 0xFFFF +#endif + +#define MG9_12_112PL 0xF7FF +#define MG9_12 (MG9_12_11PL & MG9_12_12PL & MG9_12_13PL & MG9_12_14PL & \ + MG9_12_15PL & MG9_12_16PL & MG9_12_17PL & MG9_12_18PL & \ + MG9_12_19PL & MG9_12_110PL & MG9_12_111PL & MG9_12_112PL & \ + MG9_12_113PL & MG9_12_114PL & MG9_12_115PL & MG9_12_116PL) +// End of MG9_12: +// Beginning of MG913: +#if (G9_1PL >= G9_13PL) || (G9_1PL == 0) +#define MG9_13_11PL ~(1 << 0) +#else +#define MG9_13_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_13PL) || (G9_2PL == 0) +#define MG9_13_12PL ~(1 << 1) +#else +#define MG9_13_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_13PL) || (G9_3PL == 0) +#define MG9_13_13PL ~(1 << 2) +#else +#define MG9_13_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_13PL) || (G9_4PL == 0) +#define MG9_13_14PL ~(1 << 3) +#else +#define MG9_13_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_13PL) || (G9_5PL == 0) +#define MG9_13_15PL ~(1 << 4) +#else +#define MG9_13_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_13PL) || (G9_6PL == 0) +#define MG9_13_16PL ~(1 << 5) +#else +#define MG9_13_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_13PL) || (G9_7PL == 0) +#define MG9_13_17PL ~(1 << 6) +#else +#define MG9_13_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_13PL) || (G9_8PL == 0) +#define MG9_13_18PL ~(1 << 7) +#else +#define MG9_13_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_13PL) || (G9_9PL == 0) +#define MG9_13_19PL ~(1 << 8) +#else +#define MG9_13_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_13PL) || (G9_10PL == 0) +#define MG9_13_110PL ~(1 << 9) +#else +#define MG9_13_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_13PL) || (G9_11PL == 0) +#define MG9_13_111PL ~(1 << 10) +#else +#define MG9_13_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_13PL) || (G9_12PL == 0) +#define MG9_13_112PL ~(1 << 11) +#else +#define MG9_13_112PL 0xFFFF +#endif + +#if (G9_14PL >= G9_13PL) || (G9_14PL == 0) +#define MG9_13_114PL ~(1 << 13) +#else +#define MG9_13_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_13PL) || (G9_15PL == 0) +#define MG9_13_115PL ~(1 << 14) +#else +#define MG9_13_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_13PL) || (G9_16PL == 0) +#define MG9_13_116PL ~(1 << 15) +#else +#define MG9_13_116PL 0xFFFF +#endif + +#define MG9_13_113PL 0xEFFF +#define MG9_13 (MG9_13_11PL & MG9_13_12PL & MG9_13_13PL & MG9_13_14PL & \ + MG9_13_15PL & MG9_13_16PL & MG9_13_17PL & MG9_13_18PL & \ + MG9_13_19PL & MG9_13_110PL & MG9_13_111PL & MG9_13_112PL & \ + MG9_13_113PL & MG9_13_114PL & MG9_13_115PL & MG9_13_116PL) +// End of MG9_13: +// Beginning of MG914: +#if (G9_1PL >= G9_14PL) || (G9_1PL == 0) +#define MG9_14_11PL ~(1 << 0) +#else +#define MG9_14_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_14PL) || (G9_2PL == 0) +#define MG9_14_12PL ~(1 << 1) +#else +#define MG9_14_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_14PL) || (G9_3PL == 0) +#define MG9_14_13PL ~(1 << 2) +#else +#define MG9_14_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_14PL) || (G9_4PL == 0) +#define MG9_14_14PL ~(1 << 3) +#else +#define MG9_14_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_14PL) || (G9_5PL == 0) +#define MG9_14_15PL ~(1 << 4) +#else +#define MG9_14_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_14PL) || (G9_6PL == 0) +#define MG9_14_16PL ~(1 << 5) +#else +#define MG9_14_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_14PL) || (G9_7PL == 0) +#define MG9_14_17PL ~(1 << 6) +#else +#define MG9_14_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_14PL) || (G9_8PL == 0) +#define MG9_14_18PL ~(1 << 7) +#else +#define MG9_14_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_14PL) || (G9_9PL == 0) +#define MG9_14_19PL ~(1 << 8) +#else +#define MG9_14_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_14PL) || (G9_10PL == 0) +#define MG9_14_110PL ~(1 << 9) +#else +#define MG9_14_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_14PL) || (G9_11PL == 0) +#define MG9_14_111PL ~(1 << 10) +#else +#define MG9_14_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_14PL) || (G9_12PL == 0) +#define MG9_14_112PL ~(1 << 11) +#else +#define MG9_14_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_14PL) || (G9_13PL == 0) +#define MG9_14_113PL ~(1 << 12) +#else +#define MG9_14_113PL 0xFFFF +#endif + +#if (G9_15PL >= G9_14PL) || (G9_15PL == 0) +#define MG9_14_115PL ~(1 << 14) +#else +#define MG9_14_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_14PL) || (G9_16PL == 0) +#define MG9_14_116PL ~(1 << 15) +#else +#define MG9_14_116PL 0xFFFF +#endif + +#define MG9_14_114PL 0xDFFF +#define MG9_14 (MG9_14_11PL & MG9_14_12PL & MG9_14_13PL & MG9_14_14PL & \ + MG9_14_15PL & MG9_14_16PL & MG9_14_17PL & MG9_14_18PL & \ + MG9_14_19PL & MG9_14_110PL & MG9_14_111PL & MG9_14_112PL & \ + MG9_14_113PL & MG9_14_114PL & MG9_14_115PL & MG9_14_116PL) +// End of MG9_14: +// Beginning of MG915: +#if (G9_1PL >= G9_15PL) || (G9_1PL == 0) +#define MG9_15_11PL ~(1 << 0) +#else +#define MG9_15_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_15PL) || (G9_2PL == 0) +#define MG9_15_12PL ~(1 << 1) +#else +#define MG9_15_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_15PL) || (G9_3PL == 0) +#define MG9_15_13PL ~(1 << 2) +#else +#define MG9_15_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_15PL) || (G9_4PL == 0) +#define MG9_15_14PL ~(1 << 3) +#else +#define MG9_15_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_15PL) || (G9_5PL == 0) +#define MG9_15_15PL ~(1 << 4) +#else +#define MG9_15_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_15PL) || (G9_6PL == 0) +#define MG9_15_16PL ~(1 << 5) +#else +#define MG9_15_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_15PL) || (G9_7PL == 0) +#define MG9_15_17PL ~(1 << 6) +#else +#define MG9_15_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_15PL) || (G9_8PL == 0) +#define MG9_15_18PL ~(1 << 7) +#else +#define MG9_15_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_15PL) || (G9_9PL == 0) +#define MG9_15_19PL ~(1 << 8) +#else +#define MG9_15_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_15PL) || (G9_10PL == 0) +#define MG9_15_110PL ~(1 << 9) +#else +#define MG9_15_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_15PL) || (G9_11PL == 0) +#define MG9_15_111PL ~(1 << 10) +#else +#define MG9_15_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_15PL) || (G9_12PL == 0) +#define MG9_15_112PL ~(1 << 11) +#else +#define MG9_15_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_15PL) || (G9_13PL == 0) +#define MG9_15_113PL ~(1 << 12) +#else +#define MG9_15_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_15PL) || (G9_14PL == 0) +#define MG9_15_114PL ~(1 << 13) +#else +#define MG9_15_114PL 0xFFFF +#endif + +#if (G9_16PL >= G9_15PL) || (G9_16PL == 0) +#define MG9_15_116PL ~(1 << 15) +#else +#define MG9_15_116PL 0xFFFF +#endif + +#define MG9_15_115PL 0xBFFF +#define MG9_15 (MG9_15_11PL & MG9_15_12PL & MG9_15_13PL & MG9_15_14PL & \ + MG9_15_15PL & MG9_15_16PL & MG9_15_17PL & MG9_15_18PL & \ + MG9_15_19PL & MG9_15_110PL & MG9_15_111PL & MG9_15_112PL & \ + MG9_15_113PL & MG9_15_114PL & MG9_15_115PL & MG9_15_116PL) +// End of MG9_15: +// Beginning of MG916: +#if (G9_1PL >= G9_16PL) || (G9_1PL == 0) +#define MG9_16_11PL ~(1 << 0) +#else +#define MG9_16_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_16PL) || (G9_2PL == 0) +#define MG9_16_12PL ~(1 << 1) +#else +#define MG9_16_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_16PL) || (G9_3PL == 0) +#define MG9_16_13PL ~(1 << 2) +#else +#define MG9_16_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_16PL) || (G9_4PL == 0) +#define MG9_16_14PL ~(1 << 3) +#else +#define MG9_16_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_16PL) || (G9_5PL == 0) +#define MG9_16_15PL ~(1 << 4) +#else +#define MG9_16_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_16PL) || (G9_6PL == 0) +#define MG9_16_16PL ~(1 << 5) +#else +#define MG9_16_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_16PL) || (G9_7PL == 0) +#define MG9_16_17PL ~(1 << 6) +#else +#define MG9_16_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_16PL) || (G9_8PL == 0) +#define MG9_16_18PL ~(1 << 7) +#else +#define MG9_16_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_16PL) || (G9_9PL == 0) +#define MG9_16_19PL ~(1 << 8) +#else +#define MG9_16_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_16PL) || (G9_10PL == 0) +#define MG9_16_110PL ~(1 << 9) +#else +#define MG9_16_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_16PL) || (G9_11PL == 0) +#define MG9_16_111PL ~(1 << 10) +#else +#define MG9_16_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_16PL) || (G9_12PL == 0) +#define MG9_16_112PL ~(1 << 11) +#else +#define MG9_16_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_16PL) || (G9_13PL == 0) +#define MG9_16_113PL ~(1 << 12) +#else +#define MG9_16_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_16PL) || (G9_14PL == 0) +#define MG9_16_114PL ~(1 << 13) +#else +#define MG9_16_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_16PL) || (G9_15PL == 0) +#define MG9_16_115PL ~(1 << 14) +#else +#define MG9_16_115PL 0xFFFF +#endif + +#define MG9_16_116PL 0x7FFF +#define MG9_16 (MG9_16_11PL & MG9_16_12PL & MG9_16_13PL & MG9_16_14PL & \ + MG9_16_15PL & MG9_16_16PL & MG9_16_17PL & MG9_16_18PL & \ + MG9_16_19PL & MG9_16_110PL & MG9_16_111PL & MG9_16_112PL & \ + MG9_16_113PL & MG9_16_114PL & MG9_16_115PL & MG9_16_116PL) +// End of MG9_16: + + +// +// Automatically generate PIEIER10 interrupt masks MG101 to MG1016: +// + +// Beginning of MG101: +#if (G10_2PL >= G10_1PL) || (G10_2PL == 0) +#define MG10_1_12PL ~(1 << 1) +#else +#define MG10_1_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_1PL) || (G10_3PL == 0) +#define MG10_1_13PL ~(1 << 2) +#else +#define MG10_1_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_1PL) || (G10_4PL == 0) +#define MG10_1_14PL ~(1 << 3) +#else +#define MG10_1_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_1PL) || (G10_5PL == 0) +#define MG10_1_15PL ~(1 << 4) +#else +#define MG10_1_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_1PL) || (G10_6PL == 0) +#define MG10_1_16PL ~(1 << 5) +#else +#define MG10_1_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_1PL) || (G10_7PL == 0) +#define MG10_1_17PL ~(1 << 6) +#else +#define MG10_1_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_1PL) || (G10_8PL == 0) +#define MG10_1_18PL ~(1 << 7) +#else +#define MG10_1_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_1PL) || (G10_9PL == 0) +#define MG10_1_19PL ~(1 << 8) +#else +#define MG10_1_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_1PL) || (G10_10PL == 0) +#define MG10_1_110PL ~(1 << 9) +#else +#define MG10_1_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_1PL) || (G10_11PL == 0) +#define MG10_1_111PL ~(1 << 10) +#else +#define MG10_1_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_1PL) || (G10_12PL == 0) +#define MG10_1_112PL ~(1 << 11) +#else +#define MG10_1_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_1PL) || (G10_13PL == 0) +#define MG10_1_113PL ~(1 << 12) +#else +#define MG10_1_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_1PL) || (G10_14PL == 0) +#define MG10_1_114PL ~(1 << 13) +#else +#define MG10_1_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_1PL) || (G10_15PL == 0) +#define MG10_1_115PL ~(1 << 14) +#else +#define MG10_1_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_1PL) || (G10_16PL == 0) +#define MG10_1_116PL ~(1 << 15) +#else +#define MG10_1_116PL 0xFFFF +#endif + +#define MG10_1_11PL 0xFFFE +#define MG10_1 (MG10_1_11PL & MG10_1_12PL & MG10_1_13PL & MG10_1_14PL & \ + MG10_1_15PL & MG10_1_16PL & MG10_1_17PL & MG10_1_18PL & \ + MG10_1_19PL & MG10_1_110PL & MG10_1_111PL & MG10_1_112PL & \ + MG10_1_113PL & MG10_1_114PL & MG10_1_115PL & MG10_1_116PL) +// End of MG10_1: +// Beginning of MG102: +#if (G10_1PL >= G10_2PL) || (G10_1PL == 0) +#define MG10_2_11PL ~(1 << 0) +#else +#define MG10_2_11PL 0xFFFF +#endif + +#if (G10_3PL >= G10_2PL) || (G10_3PL == 0) +#define MG10_2_13PL ~(1 << 2) +#else +#define MG10_2_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_2PL) || (G10_4PL == 0) +#define MG10_2_14PL ~(1 << 3) +#else +#define MG10_2_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_2PL) || (G10_5PL == 0) +#define MG10_2_15PL ~(1 << 4) +#else +#define MG10_2_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_2PL) || (G10_6PL == 0) +#define MG10_2_16PL ~(1 << 5) +#else +#define MG10_2_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_2PL) || (G10_7PL == 0) +#define MG10_2_17PL ~(1 << 6) +#else +#define MG10_2_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_2PL) || (G10_8PL == 0) +#define MG10_2_18PL ~(1 << 7) +#else +#define MG10_2_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_2PL) || (G10_9PL == 0) +#define MG10_2_19PL ~(1 << 8) +#else +#define MG10_2_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_2PL) || (G10_10PL == 0) +#define MG10_2_110PL ~(1 << 9) +#else +#define MG10_2_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_2PL) || (G10_11PL == 0) +#define MG10_2_111PL ~(1 << 10) +#else +#define MG10_2_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_2PL) || (G10_12PL == 0) +#define MG10_2_112PL ~(1 << 11) +#else +#define MG10_2_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_2PL) || (G10_13PL == 0) +#define MG10_2_113PL ~(1 << 12) +#else +#define MG10_2_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_2PL) || (G10_14PL == 0) +#define MG10_2_114PL ~(1 << 13) +#else +#define MG10_2_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_2PL) || (G10_15PL == 0) +#define MG10_2_115PL ~(1 << 14) +#else +#define MG10_2_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_2PL) || (G10_16PL == 0) +#define MG10_2_116PL ~(1 << 15) +#else +#define MG10_2_116PL 0xFFFF +#endif + +#define MG10_2_12PL 0xFFFD +#define MG10_2 (MG10_2_11PL & MG10_2_12PL & MG10_2_13PL & MG10_2_14PL & \ + MG10_2_15PL & MG10_2_16PL & MG10_2_17PL & MG10_2_18PL & \ + MG10_2_19PL & MG10_2_110PL & MG10_2_111PL & MG10_2_112PL & \ + MG10_2_113PL & MG10_2_114PL & MG10_2_115PL & MG10_2_116PL) +// End of MG10_2: +// Beginning of MG103: +#if (G10_1PL >= G10_3PL) || (G10_1PL == 0) +#define MG10_3_11PL ~(1 << 0) +#else +#define MG10_3_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_3PL) || (G10_2PL == 0) +#define MG10_3_12PL ~(1 << 1) +#else +#define MG10_3_12PL 0xFFFF +#endif + +#if (G10_4PL >= G10_3PL) || (G10_4PL == 0) +#define MG10_3_14PL ~(1 << 3) +#else +#define MG10_3_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_3PL) || (G10_5PL == 0) +#define MG10_3_15PL ~(1 << 4) +#else +#define MG10_3_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_3PL) || (G10_6PL == 0) +#define MG10_3_16PL ~(1 << 5) +#else +#define MG10_3_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_3PL) || (G10_7PL == 0) +#define MG10_3_17PL ~(1 << 6) +#else +#define MG10_3_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_3PL) || (G10_8PL == 0) +#define MG10_3_18PL ~(1 << 7) +#else +#define MG10_3_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_3PL) || (G10_9PL == 0) +#define MG10_3_19PL ~(1 << 8) +#else +#define MG10_3_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_3PL) || (G10_10PL == 0) +#define MG10_3_110PL ~(1 << 9) +#else +#define MG10_3_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_3PL) || (G10_11PL == 0) +#define MG10_3_111PL ~(1 << 10) +#else +#define MG10_3_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_3PL) || (G10_12PL == 0) +#define MG10_3_112PL ~(1 << 11) +#else +#define MG10_3_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_3PL) || (G10_13PL == 0) +#define MG10_3_113PL ~(1 << 12) +#else +#define MG10_3_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_3PL) || (G10_14PL == 0) +#define MG10_3_114PL ~(1 << 13) +#else +#define MG10_3_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_3PL) || (G10_15PL == 0) +#define MG10_3_115PL ~(1 << 14) +#else +#define MG10_3_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_3PL) || (G10_16PL == 0) +#define MG10_3_116PL ~(1 << 15) +#else +#define MG10_3_116PL 0xFFFF +#endif + +#define MG10_3_13PL 0xFFFB +#define MG10_3 (MG10_3_11PL & MG10_3_12PL & MG10_3_13PL & MG10_3_14PL & \ + MG10_3_15PL & MG10_3_16PL & MG10_3_17PL & MG10_3_18PL & \ + MG10_3_19PL & MG10_3_110PL & MG10_3_111PL & MG10_3_112PL & \ + MG10_3_113PL & MG10_3_114PL & MG10_3_115PL & MG10_3_116PL) +// End of MG10_3: +// Beginning of MG104: +#if (G10_1PL >= G10_4PL) || (G10_1PL == 0) +#define MG10_4_11PL ~(1 << 0) +#else +#define MG10_4_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_4PL) || (G10_2PL == 0) +#define MG10_4_12PL ~(1 << 1) +#else +#define MG10_4_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_4PL) || (G10_3PL == 0) +#define MG10_4_13PL ~(1 << 2) +#else +#define MG10_4_13PL 0xFFFF +#endif + +#if (G10_5PL >= G10_4PL) || (G10_5PL == 0) +#define MG10_4_15PL ~(1 << 4) +#else +#define MG10_4_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_4PL) || (G10_6PL == 0) +#define MG10_4_16PL ~(1 << 5) +#else +#define MG10_4_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_4PL) || (G10_7PL == 0) +#define MG10_4_17PL ~(1 << 6) +#else +#define MG10_4_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_4PL) || (G10_8PL == 0) +#define MG10_4_18PL ~(1 << 7) +#else +#define MG10_4_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_4PL) || (G10_9PL == 0) +#define MG10_4_19PL ~(1 << 8) +#else +#define MG10_4_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_4PL) || (G10_10PL == 0) +#define MG10_4_110PL ~(1 << 9) +#else +#define MG10_4_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_4PL) || (G10_11PL == 0) +#define MG10_4_111PL ~(1 << 10) +#else +#define MG10_4_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_4PL) || (G10_12PL == 0) +#define MG10_4_112PL ~(1 << 11) +#else +#define MG10_4_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_4PL) || (G10_13PL == 0) +#define MG10_4_113PL ~(1 << 12) +#else +#define MG10_4_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_4PL) || (G10_14PL == 0) +#define MG10_4_114PL ~(1 << 13) +#else +#define MG10_4_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_4PL) || (G10_15PL == 0) +#define MG10_4_115PL ~(1 << 14) +#else +#define MG10_4_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_4PL) || (G10_16PL == 0) +#define MG10_4_116PL ~(1 << 15) +#else +#define MG10_4_116PL 0xFFFF +#endif + +#define MG10_4_14PL 0xFFF7 +#define MG10_4 (MG10_4_11PL & MG10_4_12PL & MG10_4_13PL & MG10_4_14PL & \ + MG10_4_15PL & MG10_4_16PL & MG10_4_17PL & MG10_4_18PL & \ + MG10_4_19PL & MG10_4_110PL & MG10_4_111PL & MG10_4_112PL & \ + MG10_4_113PL & MG10_4_114PL & MG10_4_115PL & MG10_4_116PL) +// End of MG10_4: +// Beginning of MG105: +#if (G10_1PL >= G10_5PL) || (G10_1PL == 0) +#define MG10_5_11PL ~(1 << 0) +#else +#define MG10_5_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_5PL) || (G10_2PL == 0) +#define MG10_5_12PL ~(1 << 1) +#else +#define MG10_5_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_5PL) || (G10_3PL == 0) +#define MG10_5_13PL ~(1 << 2) +#else +#define MG10_5_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_5PL) || (G10_4PL == 0) +#define MG10_5_14PL ~(1 << 3) +#else +#define MG10_5_14PL 0xFFFF +#endif + +#if (G10_6PL >= G10_5PL) || (G10_6PL == 0) +#define MG10_5_16PL ~(1 << 5) +#else +#define MG10_5_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_5PL) || (G10_7PL == 0) +#define MG10_5_17PL ~(1 << 6) +#else +#define MG10_5_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_5PL) || (G10_8PL == 0) +#define MG10_5_18PL ~(1 << 7) +#else +#define MG10_5_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_5PL) || (G10_9PL == 0) +#define MG10_5_19PL ~(1 << 8) +#else +#define MG10_5_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_5PL) || (G10_10PL == 0) +#define MG10_5_110PL ~(1 << 9) +#else +#define MG10_5_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_5PL) || (G10_11PL == 0) +#define MG10_5_111PL ~(1 << 10) +#else +#define MG10_5_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_5PL) || (G10_12PL == 0) +#define MG10_5_112PL ~(1 << 11) +#else +#define MG10_5_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_5PL) || (G10_13PL == 0) +#define MG10_5_113PL ~(1 << 12) +#else +#define MG10_5_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_5PL) || (G10_14PL == 0) +#define MG10_5_114PL ~(1 << 13) +#else +#define MG10_5_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_5PL) || (G10_15PL == 0) +#define MG10_5_115PL ~(1 << 14) +#else +#define MG10_5_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_5PL) || (G10_16PL == 0) +#define MG10_5_116PL ~(1 << 15) +#else +#define MG10_5_116PL 0xFFFF +#endif + +#define MG10_5_15PL 0xFFEF +#define MG10_5 (MG10_5_11PL & MG10_5_12PL & MG10_5_13PL & MG10_5_14PL & \ + MG10_5_15PL & MG10_5_16PL & MG10_5_17PL & MG10_5_18PL & \ + MG10_5_19PL & MG10_5_110PL & MG10_5_111PL & MG10_5_112PL & \ + MG10_5_113PL & MG10_5_114PL & MG10_5_115PL & MG10_5_116PL) +// End of MG10_5: +// Beginning of MG106: +#if (G10_1PL >= G10_6PL) || (G10_1PL == 0) +#define MG10_6_11PL ~(1 << 0) +#else +#define MG10_6_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_6PL) || (G10_2PL == 0) +#define MG10_6_12PL ~(1 << 1) +#else +#define MG10_6_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_6PL) || (G10_3PL == 0) +#define MG10_6_13PL ~(1 << 2) +#else +#define MG10_6_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_6PL) || (G10_4PL == 0) +#define MG10_6_14PL ~(1 << 3) +#else +#define MG10_6_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_6PL) || (G10_5PL == 0) +#define MG10_6_15PL ~(1 << 4) +#else +#define MG10_6_15PL 0xFFFF +#endif + +#if (G10_7PL >= G10_6PL) || (G10_7PL == 0) +#define MG10_6_17PL ~(1 << 6) +#else +#define MG10_6_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_6PL) || (G10_8PL == 0) +#define MG10_6_18PL ~(1 << 7) +#else +#define MG10_6_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_6PL) || (G10_9PL == 0) +#define MG10_6_19PL ~(1 << 8) +#else +#define MG10_6_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_6PL) || (G10_10PL == 0) +#define MG10_6_110PL ~(1 << 9) +#else +#define MG10_6_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_6PL) || (G10_11PL == 0) +#define MG10_6_111PL ~(1 << 10) +#else +#define MG10_6_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_6PL) || (G10_12PL == 0) +#define MG10_6_112PL ~(1 << 11) +#else +#define MG10_6_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_6PL) || (G10_13PL == 0) +#define MG10_6_113PL ~(1 << 12) +#else +#define MG10_6_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_6PL) || (G10_14PL == 0) +#define MG10_6_114PL ~(1 << 13) +#else +#define MG10_6_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_6PL) || (G10_15PL == 0) +#define MG10_6_115PL ~(1 << 14) +#else +#define MG10_6_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_6PL) || (G10_16PL == 0) +#define MG10_6_116PL ~(1 << 15) +#else +#define MG10_6_116PL 0xFFFF +#endif + +#define MG10_6_16PL 0xFFDF +#define MG10_6 (MG10_6_11PL & MG10_6_12PL & MG10_6_13PL & MG10_6_14PL & \ + MG10_6_15PL & MG10_6_16PL & MG10_6_17PL & MG10_6_18PL & \ + MG10_6_19PL & MG10_6_110PL & MG10_6_111PL & MG10_6_112PL & \ + MG10_6_113PL & MG10_6_114PL & MG10_6_115PL & MG10_6_116PL) +// End of MG10_6: +// Beginning of MG107: +#if (G10_1PL >= G10_7PL) || (G10_1PL == 0) +#define MG10_7_11PL ~(1 << 0) +#else +#define MG10_7_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_7PL) || (G10_2PL == 0) +#define MG10_7_12PL ~(1 << 1) +#else +#define MG10_7_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_7PL) || (G10_3PL == 0) +#define MG10_7_13PL ~(1 << 2) +#else +#define MG10_7_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_7PL) || (G10_4PL == 0) +#define MG10_7_14PL ~(1 << 3) +#else +#define MG10_7_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_7PL) || (G10_5PL == 0) +#define MG10_7_15PL ~(1 << 4) +#else +#define MG10_7_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_7PL) || (G10_6PL == 0) +#define MG10_7_16PL ~(1 << 5) +#else +#define MG10_7_16PL 0xFFFF +#endif + +#if (G10_8PL >= G10_7PL) || (G10_8PL == 0) +#define MG10_7_18PL ~(1 << 7) +#else +#define MG10_7_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_7PL) || (G10_9PL == 0) +#define MG10_7_19PL ~(1 << 8) +#else +#define MG10_7_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_7PL) || (G10_10PL == 0) +#define MG10_7_110PL ~(1 << 9) +#else +#define MG10_7_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_7PL) || (G10_11PL == 0) +#define MG10_7_111PL ~(1 << 10) +#else +#define MG10_7_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_7PL) || (G10_12PL == 0) +#define MG10_7_112PL ~(1 << 11) +#else +#define MG10_7_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_7PL) || (G10_13PL == 0) +#define MG10_7_113PL ~(1 << 12) +#else +#define MG10_7_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_7PL) || (G10_14PL == 0) +#define MG10_7_114PL ~(1 << 13) +#else +#define MG10_7_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_7PL) || (G10_15PL == 0) +#define MG10_7_115PL ~(1 << 14) +#else +#define MG10_7_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_7PL) || (G10_16PL == 0) +#define MG10_7_116PL ~(1 << 15) +#else +#define MG10_7_116PL 0xFFFF +#endif + +#define MG10_7_17PL 0xFFBF +#define MG10_7 (MG10_7_11PL & MG10_7_12PL & MG10_7_13PL & MG10_7_14PL & \ + MG10_7_15PL & MG10_7_16PL & MG10_7_17PL & MG10_7_18PL & \ + MG10_7_19PL & MG10_7_110PL & MG10_7_111PL & MG10_7_112PL & \ + MG10_7_113PL & MG10_7_114PL & MG10_7_115PL & MG10_7_116PL) +// End of MG10_7: +// Beginning of MG108: +#if (G10_1PL >= G10_8PL) || (G10_1PL == 0) +#define MG10_8_11PL ~(1 << 0) +#else +#define MG10_8_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_8PL) || (G10_2PL == 0) +#define MG10_8_12PL ~(1 << 1) +#else +#define MG10_8_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_8PL) || (G10_3PL == 0) +#define MG10_8_13PL ~(1 << 2) +#else +#define MG10_8_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_8PL) || (G10_4PL == 0) +#define MG10_8_14PL ~(1 << 3) +#else +#define MG10_8_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_8PL) || (G10_5PL == 0) +#define MG10_8_15PL ~(1 << 4) +#else +#define MG10_8_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_8PL) || (G10_6PL == 0) +#define MG10_8_16PL ~(1 << 5) +#else +#define MG10_8_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_8PL) || (G10_7PL == 0) +#define MG10_8_17PL ~(1 << 6) +#else +#define MG10_8_17PL 0xFFFF +#endif + +#if (G10_9PL >= G10_8PL) || (G10_9PL == 0) +#define MG10_8_19PL ~(1 << 8) +#else +#define MG10_8_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_8PL) || (G10_10PL == 0) +#define MG10_8_110PL ~(1 << 9) +#else +#define MG10_8_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_8PL) || (G10_11PL == 0) +#define MG10_8_111PL ~(1 << 10) +#else +#define MG10_8_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_8PL) || (G10_12PL == 0) +#define MG10_8_112PL ~(1 << 11) +#else +#define MG10_8_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_8PL) || (G10_13PL == 0) +#define MG10_8_113PL ~(1 << 12) +#else +#define MG10_8_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_8PL) || (G10_14PL == 0) +#define MG10_8_114PL ~(1 << 13) +#else +#define MG10_8_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_8PL) || (G10_15PL == 0) +#define MG10_8_115PL ~(1 << 14) +#else +#define MG10_8_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_8PL) || (G10_16PL == 0) +#define MG10_8_116PL ~(1 << 15) +#else +#define MG10_8_116PL 0xFFFF +#endif + +#define MG10_8_18PL 0xFF7F +#define MG10_8 (MG10_8_11PL & MG10_8_12PL & MG10_8_13PL & MG10_8_14PL & \ + MG10_8_15PL & MG10_8_16PL & MG10_8_17PL & MG10_8_18PL & \ + MG10_8_19PL & MG10_8_110PL & MG10_8_111PL & MG10_8_112PL & \ + MG10_8_113PL & MG10_8_114PL & MG10_8_115PL & MG10_8_116PL) +// End of MG10_8: +// Beginning of MG109: +#if (G10_1PL >= G10_9PL) || (G10_1PL == 0) +#define MG10_9_11PL ~(1 << 0) +#else +#define MG10_9_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_9PL) || (G10_2PL == 0) +#define MG10_9_12PL ~(1 << 1) +#else +#define MG10_9_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_9PL) || (G10_3PL == 0) +#define MG10_9_13PL ~(1 << 2) +#else +#define MG10_9_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_9PL) || (G10_4PL == 0) +#define MG10_9_14PL ~(1 << 3) +#else +#define MG10_9_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_9PL) || (G10_5PL == 0) +#define MG10_9_15PL ~(1 << 4) +#else +#define MG10_9_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_9PL) || (G10_6PL == 0) +#define MG10_9_16PL ~(1 << 5) +#else +#define MG10_9_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_9PL) || (G10_7PL == 0) +#define MG10_9_17PL ~(1 << 6) +#else +#define MG10_9_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_9PL) || (G10_8PL == 0) +#define MG10_9_18PL ~(1 << 7) +#else +#define MG10_9_18PL 0xFFFF +#endif + +#if (G10_10PL >= G10_9PL) || (G10_10PL == 0) +#define MG10_9_110PL ~(1 << 9) +#else +#define MG10_9_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_9PL) || (G10_11PL == 0) +#define MG10_9_111PL ~(1 << 10) +#else +#define MG10_9_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_9PL) || (G10_12PL == 0) +#define MG10_9_112PL ~(1 << 11) +#else +#define MG10_9_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_9PL) || (G10_13PL == 0) +#define MG10_9_113PL ~(1 << 12) +#else +#define MG10_9_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_9PL) || (G10_14PL == 0) +#define MG10_9_114PL ~(1 << 13) +#else +#define MG10_9_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_9PL) || (G10_15PL == 0) +#define MG10_9_115PL ~(1 << 14) +#else +#define MG10_9_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_9PL) || (G10_16PL == 0) +#define MG10_9_116PL ~(1 << 15) +#else +#define MG10_9_116PL 0xFFFF +#endif + +#define MG10_9_19PL 0xFEFF +#define MG10_9 (MG10_9_11PL & MG10_9_12PL & MG10_9_13PL & MG10_9_14PL & \ + MG10_9_15PL & MG10_9_16PL & MG10_9_17PL & MG10_9_18PL & \ + MG10_9_19PL & MG10_9_110PL & MG10_9_111PL & MG10_9_112PL & \ + MG10_9_113PL & MG10_9_114PL & MG10_9_115PL & MG10_9_116PL) +// End of MG10_9: +// Beginning of MG1010: +#if (G10_1PL >= G10_10PL) || (G10_1PL == 0) +#define MG10_10_11PL ~(1 << 0) +#else +#define MG10_10_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_10PL) || (G10_2PL == 0) +#define MG10_10_12PL ~(1 << 1) +#else +#define MG10_10_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_10PL) || (G10_3PL == 0) +#define MG10_10_13PL ~(1 << 2) +#else +#define MG10_10_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_10PL) || (G10_4PL == 0) +#define MG10_10_14PL ~(1 << 3) +#else +#define MG10_10_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_10PL) || (G10_5PL == 0) +#define MG10_10_15PL ~(1 << 4) +#else +#define MG10_10_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_10PL) || (G10_6PL == 0) +#define MG10_10_16PL ~(1 << 5) +#else +#define MG10_10_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_10PL) || (G10_7PL == 0) +#define MG10_10_17PL ~(1 << 6) +#else +#define MG10_10_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_10PL) || (G10_8PL == 0) +#define MG10_10_18PL ~(1 << 7) +#else +#define MG10_10_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_10PL) || (G10_9PL == 0) +#define MG10_10_19PL ~(1 << 8) +#else +#define MG10_10_19PL 0xFFFF +#endif + +#if (G10_11PL >= G10_10PL) || (G10_11PL == 0) +#define MG10_10_111PL ~(1 << 10) +#else +#define MG10_10_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_10PL) || (G10_12PL == 0) +#define MG10_10_112PL ~(1 << 11) +#else +#define MG10_10_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_10PL) || (G10_13PL == 0) +#define MG10_10_113PL ~(1 << 12) +#else +#define MG10_10_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_10PL) || (G10_14PL == 0) +#define MG10_10_114PL ~(1 << 13) +#else +#define MG10_10_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_10PL) || (G10_15PL == 0) +#define MG10_10_115PL ~(1 << 14) +#else +#define MG10_10_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_10PL) || (G10_16PL == 0) +#define MG10_10_116PL ~(1 << 15) +#else +#define MG10_10_116PL 0xFFFF +#endif + +#define MG10_10_110PL 0xFDFF +#define MG10_10 (MG10_10_11PL & MG10_10_12PL & MG10_10_13PL & MG10_10_14PL & \ + MG10_10_15PL & MG10_10_16PL & MG10_10_17PL & MG10_10_18PL & \ + MG10_10_19PL & MG10_10_110PL & MG10_10_111PL & MG10_10_112PL & \ + MG10_10_113PL & MG10_10_114PL & MG10_10_115PL & MG10_10_116PL) +// End of MG10_10: +// Beginning of MG1011: +#if (G10_1PL >= G10_11PL) || (G10_1PL == 0) +#define MG10_11_11PL ~(1 << 0) +#else +#define MG10_11_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_11PL) || (G10_2PL == 0) +#define MG10_11_12PL ~(1 << 1) +#else +#define MG10_11_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_11PL) || (G10_3PL == 0) +#define MG10_11_13PL ~(1 << 2) +#else +#define MG10_11_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_11PL) || (G10_4PL == 0) +#define MG10_11_14PL ~(1 << 3) +#else +#define MG10_11_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_11PL) || (G10_5PL == 0) +#define MG10_11_15PL ~(1 << 4) +#else +#define MG10_11_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_11PL) || (G10_6PL == 0) +#define MG10_11_16PL ~(1 << 5) +#else +#define MG10_11_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_11PL) || (G10_7PL == 0) +#define MG10_11_17PL ~(1 << 6) +#else +#define MG10_11_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_11PL) || (G10_8PL == 0) +#define MG10_11_18PL ~(1 << 7) +#else +#define MG10_11_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_11PL) || (G10_9PL == 0) +#define MG10_11_19PL ~(1 << 8) +#else +#define MG10_11_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_11PL) || (G10_10PL == 0) +#define MG10_11_110PL ~(1 << 9) +#else +#define MG10_11_110PL 0xFFFF +#endif + +#if (G10_12PL >= G10_11PL) || (G10_12PL == 0) +#define MG10_11_112PL ~(1 << 11) +#else +#define MG10_11_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_11PL) || (G10_13PL == 0) +#define MG10_11_113PL ~(1 << 12) +#else +#define MG10_11_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_11PL) || (G10_14PL == 0) +#define MG10_11_114PL ~(1 << 13) +#else +#define MG10_11_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_11PL) || (G10_15PL == 0) +#define MG10_11_115PL ~(1 << 14) +#else +#define MG10_11_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_11PL) || (G10_16PL == 0) +#define MG10_11_116PL ~(1 << 15) +#else +#define MG10_11_116PL 0xFFFF +#endif + +#define MG10_11_111PL 0xFBFF +#define MG10_11 (MG10_11_11PL & MG10_11_12PL & MG10_11_13PL & MG10_11_14PL & \ + MG10_11_15PL & MG10_11_16PL & MG10_11_17PL & MG10_11_18PL & \ + MG10_11_19PL & MG10_11_110PL & MG10_11_111PL & MG10_11_112PL & \ + MG10_11_113PL & MG10_11_114PL & MG10_11_115PL & MG10_11_116PL) +// End of MG10_11: +// Beginning of MG1012: +#if (G10_1PL >= G10_12PL) || (G10_1PL == 0) +#define MG10_12_11PL ~(1 << 0) +#else +#define MG10_12_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_12PL) || (G10_2PL == 0) +#define MG10_12_12PL ~(1 << 1) +#else +#define MG10_12_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_12PL) || (G10_3PL == 0) +#define MG10_12_13PL ~(1 << 2) +#else +#define MG10_12_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_12PL) || (G10_4PL == 0) +#define MG10_12_14PL ~(1 << 3) +#else +#define MG10_12_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_12PL) || (G10_5PL == 0) +#define MG10_12_15PL ~(1 << 4) +#else +#define MG10_12_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_12PL) || (G10_6PL == 0) +#define MG10_12_16PL ~(1 << 5) +#else +#define MG10_12_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_12PL) || (G10_7PL == 0) +#define MG10_12_17PL ~(1 << 6) +#else +#define MG10_12_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_12PL) || (G10_8PL == 0) +#define MG10_12_18PL ~(1 << 7) +#else +#define MG10_12_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_12PL) || (G10_9PL == 0) +#define MG10_12_19PL ~(1 << 8) +#else +#define MG10_12_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_12PL) || (G10_10PL == 0) +#define MG10_12_110PL ~(1 << 9) +#else +#define MG10_12_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_12PL) || (G10_11PL == 0) +#define MG10_12_111PL ~(1 << 10) +#else +#define MG10_12_111PL 0xFFFF +#endif + +#if (G10_13PL >= G10_12PL) || (G10_13PL == 0) +#define MG10_12_113PL ~(1 << 12) +#else +#define MG10_12_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_12PL) || (G10_14PL == 0) +#define MG10_12_114PL ~(1 << 13) +#else +#define MG10_12_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_12PL) || (G10_15PL == 0) +#define MG10_12_115PL ~(1 << 14) +#else +#define MG10_12_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_12PL) || (G10_16PL == 0) +#define MG10_12_116PL ~(1 << 15) +#else +#define MG10_12_116PL 0xFFFF +#endif + +#define MG10_12_112PL 0xF7FF +#define MG10_12 (MG10_12_11PL & MG10_12_12PL & MG10_12_13PL & MG10_12_14PL & \ + MG10_12_15PL & MG10_12_16PL & MG10_12_17PL & MG10_12_18PL & \ + MG10_12_19PL & MG10_12_110PL & MG10_12_111PL & MG10_12_112PL & \ + MG10_12_113PL & MG10_12_114PL & MG10_12_115PL & MG10_12_116PL) +// End of MG10_12: +// Beginning of MG1013: +#if (G10_1PL >= G10_13PL) || (G10_1PL == 0) +#define MG10_13_11PL ~(1 << 0) +#else +#define MG10_13_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_13PL) || (G10_2PL == 0) +#define MG10_13_12PL ~(1 << 1) +#else +#define MG10_13_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_13PL) || (G10_3PL == 0) +#define MG10_13_13PL ~(1 << 2) +#else +#define MG10_13_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_13PL) || (G10_4PL == 0) +#define MG10_13_14PL ~(1 << 3) +#else +#define MG10_13_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_13PL) || (G10_5PL == 0) +#define MG10_13_15PL ~(1 << 4) +#else +#define MG10_13_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_13PL) || (G10_6PL == 0) +#define MG10_13_16PL ~(1 << 5) +#else +#define MG10_13_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_13PL) || (G10_7PL == 0) +#define MG10_13_17PL ~(1 << 6) +#else +#define MG10_13_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_13PL) || (G10_8PL == 0) +#define MG10_13_18PL ~(1 << 7) +#else +#define MG10_13_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_13PL) || (G10_9PL == 0) +#define MG10_13_19PL ~(1 << 8) +#else +#define MG10_13_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_13PL) || (G10_10PL == 0) +#define MG10_13_110PL ~(1 << 9) +#else +#define MG10_13_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_13PL) || (G10_11PL == 0) +#define MG10_13_111PL ~(1 << 10) +#else +#define MG10_13_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_13PL) || (G10_12PL == 0) +#define MG10_13_112PL ~(1 << 11) +#else +#define MG10_13_112PL 0xFFFF +#endif + +#if (G10_14PL >= G10_13PL) || (G10_14PL == 0) +#define MG10_13_114PL ~(1 << 13) +#else +#define MG10_13_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_13PL) || (G10_15PL == 0) +#define MG10_13_115PL ~(1 << 14) +#else +#define MG10_13_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_13PL) || (G10_16PL == 0) +#define MG10_13_116PL ~(1 << 15) +#else +#define MG10_13_116PL 0xFFFF +#endif + +#define MG10_13_113PL 0xEFFF +#define MG10_13 (MG10_13_11PL & MG10_13_12PL & MG10_13_13PL & MG10_13_14PL & \ + MG10_13_15PL & MG10_13_16PL & MG10_13_17PL & MG10_13_18PL & \ + MG10_13_19PL & MG10_13_110PL & MG10_13_111PL & MG10_13_112PL & \ + MG10_13_113PL & MG10_13_114PL & MG10_13_115PL & MG10_13_116PL) +// End of MG10_13: +// Beginning of MG1014: +#if (G10_1PL >= G10_14PL) || (G10_1PL == 0) +#define MG10_14_11PL ~(1 << 0) +#else +#define MG10_14_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_14PL) || (G10_2PL == 0) +#define MG10_14_12PL ~(1 << 1) +#else +#define MG10_14_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_14PL) || (G10_3PL == 0) +#define MG10_14_13PL ~(1 << 2) +#else +#define MG10_14_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_14PL) || (G10_4PL == 0) +#define MG10_14_14PL ~(1 << 3) +#else +#define MG10_14_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_14PL) || (G10_5PL == 0) +#define MG10_14_15PL ~(1 << 4) +#else +#define MG10_14_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_14PL) || (G10_6PL == 0) +#define MG10_14_16PL ~(1 << 5) +#else +#define MG10_14_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_14PL) || (G10_7PL == 0) +#define MG10_14_17PL ~(1 << 6) +#else +#define MG10_14_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_14PL) || (G10_8PL == 0) +#define MG10_14_18PL ~(1 << 7) +#else +#define MG10_14_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_14PL) || (G10_9PL == 0) +#define MG10_14_19PL ~(1 << 8) +#else +#define MG10_14_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_14PL) || (G10_10PL == 0) +#define MG10_14_110PL ~(1 << 9) +#else +#define MG10_14_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_14PL) || (G10_11PL == 0) +#define MG10_14_111PL ~(1 << 10) +#else +#define MG10_14_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_14PL) || (G10_12PL == 0) +#define MG10_14_112PL ~(1 << 11) +#else +#define MG10_14_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_14PL) || (G10_13PL == 0) +#define MG10_14_113PL ~(1 << 12) +#else +#define MG10_14_113PL 0xFFFF +#endif + +#if (G10_15PL >= G10_14PL) || (G10_15PL == 0) +#define MG10_14_115PL ~(1 << 14) +#else +#define MG10_14_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_14PL) || (G10_16PL == 0) +#define MG10_14_116PL ~(1 << 15) +#else +#define MG10_14_116PL 0xFFFF +#endif + +#define MG10_14_114PL 0xDFFF +#define MG10_14 (MG10_14_11PL & MG10_14_12PL & MG10_14_13PL & MG10_14_14PL & \ + MG10_14_15PL & MG10_14_16PL & MG10_14_17PL & MG10_14_18PL & \ + MG10_14_19PL & MG10_14_110PL & MG10_14_111PL & MG10_14_112PL & \ + MG10_14_113PL & MG10_14_114PL & MG10_14_115PL & MG10_14_116PL) +// End of MG10_14: +// Beginning of MG1015: +#if (G10_1PL >= G10_15PL) || (G10_1PL == 0) +#define MG10_15_11PL ~(1 << 0) +#else +#define MG10_15_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_15PL) || (G10_2PL == 0) +#define MG10_15_12PL ~(1 << 1) +#else +#define MG10_15_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_15PL) || (G10_3PL == 0) +#define MG10_15_13PL ~(1 << 2) +#else +#define MG10_15_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_15PL) || (G10_4PL == 0) +#define MG10_15_14PL ~(1 << 3) +#else +#define MG10_15_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_15PL) || (G10_5PL == 0) +#define MG10_15_15PL ~(1 << 4) +#else +#define MG10_15_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_15PL) || (G10_6PL == 0) +#define MG10_15_16PL ~(1 << 5) +#else +#define MG10_15_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_15PL) || (G10_7PL == 0) +#define MG10_15_17PL ~(1 << 6) +#else +#define MG10_15_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_15PL) || (G10_8PL == 0) +#define MG10_15_18PL ~(1 << 7) +#else +#define MG10_15_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_15PL) || (G10_9PL == 0) +#define MG10_15_19PL ~(1 << 8) +#else +#define MG10_15_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_15PL) || (G10_10PL == 0) +#define MG10_15_110PL ~(1 << 9) +#else +#define MG10_15_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_15PL) || (G10_11PL == 0) +#define MG10_15_111PL ~(1 << 10) +#else +#define MG10_15_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_15PL) || (G10_12PL == 0) +#define MG10_15_112PL ~(1 << 11) +#else +#define MG10_15_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_15PL) || (G10_13PL == 0) +#define MG10_15_113PL ~(1 << 12) +#else +#define MG10_15_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_15PL) || (G10_14PL == 0) +#define MG10_15_114PL ~(1 << 13) +#else +#define MG10_15_114PL 0xFFFF +#endif + +#if (G10_16PL >= G10_15PL) || (G10_16PL == 0) +#define MG10_15_116PL ~(1 << 15) +#else +#define MG10_15_116PL 0xFFFF +#endif + +#define MG10_15_115PL 0xBFFF +#define MG10_15 (MG10_15_11PL & MG10_15_12PL & MG10_15_13PL & MG10_15_14PL & \ + MG10_15_15PL & MG10_15_16PL & MG10_15_17PL & MG10_15_18PL & \ + MG10_15_19PL & MG10_15_110PL & MG10_15_111PL & MG10_15_112PL & \ + MG10_15_113PL & MG10_15_114PL & MG10_15_115PL & MG10_15_116PL) +// End of MG10_15: +// Beginning of MG1016: +#if (G10_1PL >= G10_16PL) || (G10_1PL == 0) +#define MG10_16_11PL ~(1 << 0) +#else +#define MG10_16_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_16PL) || (G10_2PL == 0) +#define MG10_16_12PL ~(1 << 1) +#else +#define MG10_16_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_16PL) || (G10_3PL == 0) +#define MG10_16_13PL ~(1 << 2) +#else +#define MG10_16_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_16PL) || (G10_4PL == 0) +#define MG10_16_14PL ~(1 << 3) +#else +#define MG10_16_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_16PL) || (G10_5PL == 0) +#define MG10_16_15PL ~(1 << 4) +#else +#define MG10_16_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_16PL) || (G10_6PL == 0) +#define MG10_16_16PL ~(1 << 5) +#else +#define MG10_16_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_16PL) || (G10_7PL == 0) +#define MG10_16_17PL ~(1 << 6) +#else +#define MG10_16_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_16PL) || (G10_8PL == 0) +#define MG10_16_18PL ~(1 << 7) +#else +#define MG10_16_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_16PL) || (G10_9PL == 0) +#define MG10_16_19PL ~(1 << 8) +#else +#define MG10_16_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_16PL) || (G10_10PL == 0) +#define MG10_16_110PL ~(1 << 9) +#else +#define MG10_16_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_16PL) || (G10_11PL == 0) +#define MG10_16_111PL ~(1 << 10) +#else +#define MG10_16_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_16PL) || (G10_12PL == 0) +#define MG10_16_112PL ~(1 << 11) +#else +#define MG10_16_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_16PL) || (G10_13PL == 0) +#define MG10_16_113PL ~(1 << 12) +#else +#define MG10_16_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_16PL) || (G10_14PL == 0) +#define MG10_16_114PL ~(1 << 13) +#else +#define MG10_16_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_16PL) || (G10_15PL == 0) +#define MG10_16_115PL ~(1 << 14) +#else +#define MG10_16_115PL 0xFFFF +#endif + +#define MG10_16_116PL 0x7FFF +#define MG10_16 (MG10_16_11PL & MG10_16_12PL & MG10_16_13PL & MG10_16_14PL & \ + MG10_16_15PL & MG10_16_16PL & MG10_16_17PL & MG10_16_18PL & \ + MG10_16_19PL & MG10_16_110PL & MG10_16_111PL & MG10_16_112PL & \ + MG10_16_113PL & MG10_16_114PL & MG10_16_115PL & MG10_16_116PL) +// End of MG10_16: + + +// +// Automatically generate PIEIER11 interrupt masks MG111 to MG1116: +// + +// Beginning of MG111: +#if (G11_2PL >= G11_1PL) || (G11_2PL == 0) +#define MG11_1_12PL ~(1 << 1) +#else +#define MG11_1_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_1PL) || (G11_3PL == 0) +#define MG11_1_13PL ~(1 << 2) +#else +#define MG11_1_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_1PL) || (G11_4PL == 0) +#define MG11_1_14PL ~(1 << 3) +#else +#define MG11_1_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_1PL) || (G11_5PL == 0) +#define MG11_1_15PL ~(1 << 4) +#else +#define MG11_1_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_1PL) || (G11_6PL == 0) +#define MG11_1_16PL ~(1 << 5) +#else +#define MG11_1_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_1PL) || (G11_7PL == 0) +#define MG11_1_17PL ~(1 << 6) +#else +#define MG11_1_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_1PL) || (G11_8PL == 0) +#define MG11_1_18PL ~(1 << 7) +#else +#define MG11_1_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_1PL) || (G11_9PL == 0) +#define MG11_1_19PL ~(1 << 8) +#else +#define MG11_1_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_1PL) || (G11_10PL == 0) +#define MG11_1_110PL ~(1 << 9) +#else +#define MG11_1_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_1PL) || (G11_11PL == 0) +#define MG11_1_111PL ~(1 << 10) +#else +#define MG11_1_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_1PL) || (G11_12PL == 0) +#define MG11_1_112PL ~(1 << 11) +#else +#define MG11_1_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_1PL) || (G11_13PL == 0) +#define MG11_1_113PL ~(1 << 12) +#else +#define MG11_1_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_1PL) || (G11_14PL == 0) +#define MG11_1_114PL ~(1 << 13) +#else +#define MG11_1_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_1PL) || (G11_15PL == 0) +#define MG11_1_115PL ~(1 << 14) +#else +#define MG11_1_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_1PL) || (G11_16PL == 0) +#define MG11_1_116PL ~(1 << 15) +#else +#define MG11_1_116PL 0xFFFF +#endif + +#define MG11_1_11PL 0xFFFE +#define MG11_1 (MG11_1_11PL & MG11_1_12PL & MG11_1_13PL & MG11_1_14PL & \ + MG11_1_15PL & MG11_1_16PL & MG11_1_17PL & MG11_1_18PL & \ + MG11_1_19PL & MG11_1_110PL & MG11_1_111PL & MG11_1_112PL & \ + MG11_1_113PL & MG11_1_114PL & MG11_1_115PL & MG11_1_116PL) +// End of MG11_1: +// Beginning of MG112: +#if (G11_1PL >= G11_2PL) || (G11_1PL == 0) +#define MG11_2_11PL ~(1 << 0) +#else +#define MG11_2_11PL 0xFFFF +#endif + +#if (G11_3PL >= G11_2PL) || (G11_3PL == 0) +#define MG11_2_13PL ~(1 << 2) +#else +#define MG11_2_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_2PL) || (G11_4PL == 0) +#define MG11_2_14PL ~(1 << 3) +#else +#define MG11_2_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_2PL) || (G11_5PL == 0) +#define MG11_2_15PL ~(1 << 4) +#else +#define MG11_2_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_2PL) || (G11_6PL == 0) +#define MG11_2_16PL ~(1 << 5) +#else +#define MG11_2_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_2PL) || (G11_7PL == 0) +#define MG11_2_17PL ~(1 << 6) +#else +#define MG11_2_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_2PL) || (G11_8PL == 0) +#define MG11_2_18PL ~(1 << 7) +#else +#define MG11_2_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_2PL) || (G11_9PL == 0) +#define MG11_2_19PL ~(1 << 8) +#else +#define MG11_2_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_2PL) || (G11_10PL == 0) +#define MG11_2_110PL ~(1 << 9) +#else +#define MG11_2_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_2PL) || (G11_11PL == 0) +#define MG11_2_111PL ~(1 << 10) +#else +#define MG11_2_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_2PL) || (G11_12PL == 0) +#define MG11_2_112PL ~(1 << 11) +#else +#define MG11_2_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_2PL) || (G11_13PL == 0) +#define MG11_2_113PL ~(1 << 12) +#else +#define MG11_2_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_2PL) || (G11_14PL == 0) +#define MG11_2_114PL ~(1 << 13) +#else +#define MG11_2_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_2PL) || (G11_15PL == 0) +#define MG11_2_115PL ~(1 << 14) +#else +#define MG11_2_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_2PL) || (G11_16PL == 0) +#define MG11_2_116PL ~(1 << 15) +#else +#define MG11_2_116PL 0xFFFF +#endif + +#define MG11_2_12PL 0xFFFD +#define MG11_2 (MG11_2_11PL & MG11_2_12PL & MG11_2_13PL & MG11_2_14PL & \ + MG11_2_15PL & MG11_2_16PL & MG11_2_17PL & MG11_2_18PL & \ + MG11_2_19PL & MG11_2_110PL & MG11_2_111PL & MG11_2_112PL & \ + MG11_2_113PL & MG11_2_114PL & MG11_2_115PL & MG11_2_116PL) +// End of MG11_2: +// Beginning of MG113: +#if (G11_1PL >= G11_3PL) || (G11_1PL == 0) +#define MG11_3_11PL ~(1 << 0) +#else +#define MG11_3_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_3PL) || (G11_2PL == 0) +#define MG11_3_12PL ~(1 << 1) +#else +#define MG11_3_12PL 0xFFFF +#endif + +#if (G11_4PL >= G11_3PL) || (G11_4PL == 0) +#define MG11_3_14PL ~(1 << 3) +#else +#define MG11_3_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_3PL) || (G11_5PL == 0) +#define MG11_3_15PL ~(1 << 4) +#else +#define MG11_3_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_3PL) || (G11_6PL == 0) +#define MG11_3_16PL ~(1 << 5) +#else +#define MG11_3_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_3PL) || (G11_7PL == 0) +#define MG11_3_17PL ~(1 << 6) +#else +#define MG11_3_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_3PL) || (G11_8PL == 0) +#define MG11_3_18PL ~(1 << 7) +#else +#define MG11_3_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_3PL) || (G11_9PL == 0) +#define MG11_3_19PL ~(1 << 8) +#else +#define MG11_3_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_3PL) || (G11_10PL == 0) +#define MG11_3_110PL ~(1 << 9) +#else +#define MG11_3_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_3PL) || (G11_11PL == 0) +#define MG11_3_111PL ~(1 << 10) +#else +#define MG11_3_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_3PL) || (G11_12PL == 0) +#define MG11_3_112PL ~(1 << 11) +#else +#define MG11_3_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_3PL) || (G11_13PL == 0) +#define MG11_3_113PL ~(1 << 12) +#else +#define MG11_3_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_3PL) || (G11_14PL == 0) +#define MG11_3_114PL ~(1 << 13) +#else +#define MG11_3_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_3PL) || (G11_15PL == 0) +#define MG11_3_115PL ~(1 << 14) +#else +#define MG11_3_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_3PL) || (G11_16PL == 0) +#define MG11_3_116PL ~(1 << 15) +#else +#define MG11_3_116PL 0xFFFF +#endif + +#define MG11_3_13PL 0xFFFB +#define MG11_3 (MG11_3_11PL & MG11_3_12PL & MG11_3_13PL & MG11_3_14PL & \ + MG11_3_15PL & MG11_3_16PL & MG11_3_17PL & MG11_3_18PL & \ + MG11_3_19PL & MG11_3_110PL & MG11_3_111PL & MG11_3_112PL & \ + MG11_3_113PL & MG11_3_114PL & MG11_3_115PL & MG11_3_116PL) +// End of MG11_3: +// Beginning of MG114: +#if (G11_1PL >= G11_4PL) || (G11_1PL == 0) +#define MG11_4_11PL ~(1 << 0) +#else +#define MG11_4_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_4PL) || (G11_2PL == 0) +#define MG11_4_12PL ~(1 << 1) +#else +#define MG11_4_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_4PL) || (G11_3PL == 0) +#define MG11_4_13PL ~(1 << 2) +#else +#define MG11_4_13PL 0xFFFF +#endif + +#if (G11_5PL >= G11_4PL) || (G11_5PL == 0) +#define MG11_4_15PL ~(1 << 4) +#else +#define MG11_4_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_4PL) || (G11_6PL == 0) +#define MG11_4_16PL ~(1 << 5) +#else +#define MG11_4_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_4PL) || (G11_7PL == 0) +#define MG11_4_17PL ~(1 << 6) +#else +#define MG11_4_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_4PL) || (G11_8PL == 0) +#define MG11_4_18PL ~(1 << 7) +#else +#define MG11_4_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_4PL) || (G11_9PL == 0) +#define MG11_4_19PL ~(1 << 8) +#else +#define MG11_4_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_4PL) || (G11_10PL == 0) +#define MG11_4_110PL ~(1 << 9) +#else +#define MG11_4_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_4PL) || (G11_11PL == 0) +#define MG11_4_111PL ~(1 << 10) +#else +#define MG11_4_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_4PL) || (G11_12PL == 0) +#define MG11_4_112PL ~(1 << 11) +#else +#define MG11_4_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_4PL) || (G11_13PL == 0) +#define MG11_4_113PL ~(1 << 12) +#else +#define MG11_4_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_4PL) || (G11_14PL == 0) +#define MG11_4_114PL ~(1 << 13) +#else +#define MG11_4_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_4PL) || (G11_15PL == 0) +#define MG11_4_115PL ~(1 << 14) +#else +#define MG11_4_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_4PL) || (G11_16PL == 0) +#define MG11_4_116PL ~(1 << 15) +#else +#define MG11_4_116PL 0xFFFF +#endif + +#define MG11_4_14PL 0xFFF7 +#define MG11_4 (MG11_4_11PL & MG11_4_12PL & MG11_4_13PL & MG11_4_14PL & \ + MG11_4_15PL & MG11_4_16PL & MG11_4_17PL & MG11_4_18PL & \ + MG11_4_19PL & MG11_4_110PL & MG11_4_111PL & MG11_4_112PL & \ + MG11_4_113PL & MG11_4_114PL & MG11_4_115PL & MG11_4_116PL) +// End of MG11_4: +// Beginning of MG115: +#if (G11_1PL >= G11_5PL) || (G11_1PL == 0) +#define MG11_5_11PL ~(1 << 0) +#else +#define MG11_5_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_5PL) || (G11_2PL == 0) +#define MG11_5_12PL ~(1 << 1) +#else +#define MG11_5_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_5PL) || (G11_3PL == 0) +#define MG11_5_13PL ~(1 << 2) +#else +#define MG11_5_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_5PL) || (G11_4PL == 0) +#define MG11_5_14PL ~(1 << 3) +#else +#define MG11_5_14PL 0xFFFF +#endif + +#if (G11_6PL >= G11_5PL) || (G11_6PL == 0) +#define MG11_5_16PL ~(1 << 5) +#else +#define MG11_5_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_5PL) || (G11_7PL == 0) +#define MG11_5_17PL ~(1 << 6) +#else +#define MG11_5_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_5PL) || (G11_8PL == 0) +#define MG11_5_18PL ~(1 << 7) +#else +#define MG11_5_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_5PL) || (G11_9PL == 0) +#define MG11_5_19PL ~(1 << 8) +#else +#define MG11_5_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_5PL) || (G11_10PL == 0) +#define MG11_5_110PL ~(1 << 9) +#else +#define MG11_5_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_5PL) || (G11_11PL == 0) +#define MG11_5_111PL ~(1 << 10) +#else +#define MG11_5_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_5PL) || (G11_12PL == 0) +#define MG11_5_112PL ~(1 << 11) +#else +#define MG11_5_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_5PL) || (G11_13PL == 0) +#define MG11_5_113PL ~(1 << 12) +#else +#define MG11_5_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_5PL) || (G11_14PL == 0) +#define MG11_5_114PL ~(1 << 13) +#else +#define MG11_5_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_5PL) || (G11_15PL == 0) +#define MG11_5_115PL ~(1 << 14) +#else +#define MG11_5_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_5PL) || (G11_16PL == 0) +#define MG11_5_116PL ~(1 << 15) +#else +#define MG11_5_116PL 0xFFFF +#endif + +#define MG11_5_15PL 0xFFEF +#define MG11_5 (MG11_5_11PL & MG11_5_12PL & MG11_5_13PL & MG11_5_14PL & \ + MG11_5_15PL & MG11_5_16PL & MG11_5_17PL & MG11_5_18PL & \ + MG11_5_19PL & MG11_5_110PL & MG11_5_111PL & MG11_5_112PL & \ + MG11_5_113PL & MG11_5_114PL & MG11_5_115PL & MG11_5_116PL) +// End of MG11_5: +// Beginning of MG116: +#if (G11_1PL >= G11_6PL) || (G11_1PL == 0) +#define MG11_6_11PL ~(1 << 0) +#else +#define MG11_6_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_6PL) || (G11_2PL == 0) +#define MG11_6_12PL ~(1 << 1) +#else +#define MG11_6_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_6PL) || (G11_3PL == 0) +#define MG11_6_13PL ~(1 << 2) +#else +#define MG11_6_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_6PL) || (G11_4PL == 0) +#define MG11_6_14PL ~(1 << 3) +#else +#define MG11_6_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_6PL) || (G11_5PL == 0) +#define MG11_6_15PL ~(1 << 4) +#else +#define MG11_6_15PL 0xFFFF +#endif + +#if (G11_7PL >= G11_6PL) || (G11_7PL == 0) +#define MG11_6_17PL ~(1 << 6) +#else +#define MG11_6_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_6PL) || (G11_8PL == 0) +#define MG11_6_18PL ~(1 << 7) +#else +#define MG11_6_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_6PL) || (G11_9PL == 0) +#define MG11_6_19PL ~(1 << 8) +#else +#define MG11_6_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_6PL) || (G11_10PL == 0) +#define MG11_6_110PL ~(1 << 9) +#else +#define MG11_6_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_6PL) || (G11_11PL == 0) +#define MG11_6_111PL ~(1 << 10) +#else +#define MG11_6_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_6PL) || (G11_12PL == 0) +#define MG11_6_112PL ~(1 << 11) +#else +#define MG11_6_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_6PL) || (G11_13PL == 0) +#define MG11_6_113PL ~(1 << 12) +#else +#define MG11_6_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_6PL) || (G11_14PL == 0) +#define MG11_6_114PL ~(1 << 13) +#else +#define MG11_6_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_6PL) || (G11_15PL == 0) +#define MG11_6_115PL ~(1 << 14) +#else +#define MG11_6_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_6PL) || (G11_16PL == 0) +#define MG11_6_116PL ~(1 << 15) +#else +#define MG11_6_116PL 0xFFFF +#endif + +#define MG11_6_16PL 0xFFDF +#define MG11_6 (MG11_6_11PL & MG11_6_12PL & MG11_6_13PL & MG11_6_14PL & \ + MG11_6_15PL & MG11_6_16PL & MG11_6_17PL & MG11_6_18PL & \ + MG11_6_19PL & MG11_6_110PL & MG11_6_111PL & MG11_6_112PL & \ + MG11_6_113PL & MG11_6_114PL & MG11_6_115PL & MG11_6_116PL) +// End of MG11_6: +// Beginning of MG117: +#if (G11_1PL >= G11_7PL) || (G11_1PL == 0) +#define MG11_7_11PL ~(1 << 0) +#else +#define MG11_7_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_7PL) || (G11_2PL == 0) +#define MG11_7_12PL ~(1 << 1) +#else +#define MG11_7_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_7PL) || (G11_3PL == 0) +#define MG11_7_13PL ~(1 << 2) +#else +#define MG11_7_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_7PL) || (G11_4PL == 0) +#define MG11_7_14PL ~(1 << 3) +#else +#define MG11_7_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_7PL) || (G11_5PL == 0) +#define MG11_7_15PL ~(1 << 4) +#else +#define MG11_7_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_7PL) || (G11_6PL == 0) +#define MG11_7_16PL ~(1 << 5) +#else +#define MG11_7_16PL 0xFFFF +#endif + +#if (G11_8PL >= G11_7PL) || (G11_8PL == 0) +#define MG11_7_18PL ~(1 << 7) +#else +#define MG11_7_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_7PL) || (G11_9PL == 0) +#define MG11_7_19PL ~(1 << 8) +#else +#define MG11_7_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_7PL) || (G11_10PL == 0) +#define MG11_7_110PL ~(1 << 9) +#else +#define MG11_7_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_7PL) || (G11_11PL == 0) +#define MG11_7_111PL ~(1 << 10) +#else +#define MG11_7_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_7PL) || (G11_12PL == 0) +#define MG11_7_112PL ~(1 << 11) +#else +#define MG11_7_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_7PL) || (G11_13PL == 0) +#define MG11_7_113PL ~(1 << 12) +#else +#define MG11_7_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_7PL) || (G11_14PL == 0) +#define MG11_7_114PL ~(1 << 13) +#else +#define MG11_7_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_7PL) || (G11_15PL == 0) +#define MG11_7_115PL ~(1 << 14) +#else +#define MG11_7_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_7PL) || (G11_16PL == 0) +#define MG11_7_116PL ~(1 << 15) +#else +#define MG11_7_116PL 0xFFFF +#endif + +#define MG11_7_17PL 0xFFBF +#define MG11_7 (MG11_7_11PL & MG11_7_12PL & MG11_7_13PL & MG11_7_14PL & \ + MG11_7_15PL & MG11_7_16PL & MG11_7_17PL & MG11_7_18PL & \ + MG11_7_19PL & MG11_7_110PL & MG11_7_111PL & MG11_7_112PL & \ + MG11_7_113PL & MG11_7_114PL & MG11_7_115PL & MG11_7_116PL) +// End of MG11_7: +// Beginning of MG118: +#if (G11_1PL >= G11_8PL) || (G11_1PL == 0) +#define MG11_8_11PL ~(1 << 0) +#else +#define MG11_8_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_8PL) || (G11_2PL == 0) +#define MG11_8_12PL ~(1 << 1) +#else +#define MG11_8_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_8PL) || (G11_3PL == 0) +#define MG11_8_13PL ~(1 << 2) +#else +#define MG11_8_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_8PL) || (G11_4PL == 0) +#define MG11_8_14PL ~(1 << 3) +#else +#define MG11_8_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_8PL) || (G11_5PL == 0) +#define MG11_8_15PL ~(1 << 4) +#else +#define MG11_8_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_8PL) || (G11_6PL == 0) +#define MG11_8_16PL ~(1 << 5) +#else +#define MG11_8_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_8PL) || (G11_7PL == 0) +#define MG11_8_17PL ~(1 << 6) +#else +#define MG11_8_17PL 0xFFFF +#endif + +#if (G11_9PL >= G11_8PL) || (G11_9PL == 0) +#define MG11_8_19PL ~(1 << 8) +#else +#define MG11_8_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_8PL) || (G11_10PL == 0) +#define MG11_8_110PL ~(1 << 9) +#else +#define MG11_8_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_8PL) || (G11_11PL == 0) +#define MG11_8_111PL ~(1 << 10) +#else +#define MG11_8_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_8PL) || (G11_12PL == 0) +#define MG11_8_112PL ~(1 << 11) +#else +#define MG11_8_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_8PL) || (G11_13PL == 0) +#define MG11_8_113PL ~(1 << 12) +#else +#define MG11_8_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_8PL) || (G11_14PL == 0) +#define MG11_8_114PL ~(1 << 13) +#else +#define MG11_8_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_8PL) || (G11_15PL == 0) +#define MG11_8_115PL ~(1 << 14) +#else +#define MG11_8_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_8PL) || (G11_16PL == 0) +#define MG11_8_116PL ~(1 << 15) +#else +#define MG11_8_116PL 0xFFFF +#endif + +#define MG11_8_18PL 0xFF7F +#define MG11_8 (MG11_8_11PL & MG11_8_12PL & MG11_8_13PL & MG11_8_14PL & \ + MG11_8_15PL & MG11_8_16PL & MG11_8_17PL & MG11_8_18PL & \ + MG11_8_19PL & MG11_8_110PL & MG11_8_111PL & MG11_8_112PL & \ + MG11_8_113PL & MG11_8_114PL & MG11_8_115PL & MG11_8_116PL) +// End of MG11_8: +// Beginning of MG119: +#if (G11_1PL >= G11_9PL) || (G11_1PL == 0) +#define MG11_9_11PL ~(1 << 0) +#else +#define MG11_9_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_9PL) || (G11_2PL == 0) +#define MG11_9_12PL ~(1 << 1) +#else +#define MG11_9_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_9PL) || (G11_3PL == 0) +#define MG11_9_13PL ~(1 << 2) +#else +#define MG11_9_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_9PL) || (G11_4PL == 0) +#define MG11_9_14PL ~(1 << 3) +#else +#define MG11_9_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_9PL) || (G11_5PL == 0) +#define MG11_9_15PL ~(1 << 4) +#else +#define MG11_9_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_9PL) || (G11_6PL == 0) +#define MG11_9_16PL ~(1 << 5) +#else +#define MG11_9_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_9PL) || (G11_7PL == 0) +#define MG11_9_17PL ~(1 << 6) +#else +#define MG11_9_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_9PL) || (G11_8PL == 0) +#define MG11_9_18PL ~(1 << 7) +#else +#define MG11_9_18PL 0xFFFF +#endif + +#if (G11_10PL >= G11_9PL) || (G11_10PL == 0) +#define MG11_9_110PL ~(1 << 9) +#else +#define MG11_9_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_9PL) || (G11_11PL == 0) +#define MG11_9_111PL ~(1 << 10) +#else +#define MG11_9_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_9PL) || (G11_12PL == 0) +#define MG11_9_112PL ~(1 << 11) +#else +#define MG11_9_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_9PL) || (G11_13PL == 0) +#define MG11_9_113PL ~(1 << 12) +#else +#define MG11_9_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_9PL) || (G11_14PL == 0) +#define MG11_9_114PL ~(1 << 13) +#else +#define MG11_9_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_9PL) || (G11_15PL == 0) +#define MG11_9_115PL ~(1 << 14) +#else +#define MG11_9_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_9PL) || (G11_16PL == 0) +#define MG11_9_116PL ~(1 << 15) +#else +#define MG11_9_116PL 0xFFFF +#endif + +#define MG11_9_19PL 0xFEFF +#define MG11_9 (MG11_9_11PL & MG11_9_12PL & MG11_9_13PL & MG11_9_14PL & \ + MG11_9_15PL & MG11_9_16PL & MG11_9_17PL & MG11_9_18PL & \ + MG11_9_19PL & MG11_9_110PL & MG11_9_111PL & MG11_9_112PL & \ + MG11_9_113PL & MG11_9_114PL & MG11_9_115PL & MG11_9_116PL) +// End of MG11_9: +// Beginning of MG1110: +#if (G11_1PL >= G11_10PL) || (G11_1PL == 0) +#define MG11_10_11PL ~(1 << 0) +#else +#define MG11_10_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_10PL) || (G11_2PL == 0) +#define MG11_10_12PL ~(1 << 1) +#else +#define MG11_10_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_10PL) || (G11_3PL == 0) +#define MG11_10_13PL ~(1 << 2) +#else +#define MG11_10_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_10PL) || (G11_4PL == 0) +#define MG11_10_14PL ~(1 << 3) +#else +#define MG11_10_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_10PL) || (G11_5PL == 0) +#define MG11_10_15PL ~(1 << 4) +#else +#define MG11_10_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_10PL) || (G11_6PL == 0) +#define MG11_10_16PL ~(1 << 5) +#else +#define MG11_10_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_10PL) || (G11_7PL == 0) +#define MG11_10_17PL ~(1 << 6) +#else +#define MG11_10_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_10PL) || (G11_8PL == 0) +#define MG11_10_18PL ~(1 << 7) +#else +#define MG11_10_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_10PL) || (G11_9PL == 0) +#define MG11_10_19PL ~(1 << 8) +#else +#define MG11_10_19PL 0xFFFF +#endif + +#if (G11_11PL >= G11_10PL) || (G11_11PL == 0) +#define MG11_10_111PL ~(1 << 10) +#else +#define MG11_10_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_10PL) || (G11_12PL == 0) +#define MG11_10_112PL ~(1 << 11) +#else +#define MG11_10_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_10PL) || (G11_13PL == 0) +#define MG11_10_113PL ~(1 << 12) +#else +#define MG11_10_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_10PL) || (G11_14PL == 0) +#define MG11_10_114PL ~(1 << 13) +#else +#define MG11_10_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_10PL) || (G11_15PL == 0) +#define MG11_10_115PL ~(1 << 14) +#else +#define MG11_10_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_10PL) || (G11_16PL == 0) +#define MG11_10_116PL ~(1 << 15) +#else +#define MG11_10_116PL 0xFFFF +#endif + +#define MG11_10_110PL 0xFDFF +#define MG11_10 (MG11_10_11PL & MG11_10_12PL & MG11_10_13PL & MG11_10_14PL & \ + MG11_10_15PL & MG11_10_16PL & MG11_10_17PL & MG11_10_18PL & \ + MG11_10_19PL & MG11_10_110PL & MG11_10_111PL & MG11_10_112PL & \ + MG11_10_113PL & MG11_10_114PL & MG11_10_115PL & MG11_10_116PL) +// End of MG11_10: +// Beginning of MG1111: +#if (G11_1PL >= G11_11PL) || (G11_1PL == 0) +#define MG11_11_11PL ~(1 << 0) +#else +#define MG11_11_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_11PL) || (G11_2PL == 0) +#define MG11_11_12PL ~(1 << 1) +#else +#define MG11_11_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_11PL) || (G11_3PL == 0) +#define MG11_11_13PL ~(1 << 2) +#else +#define MG11_11_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_11PL) || (G11_4PL == 0) +#define MG11_11_14PL ~(1 << 3) +#else +#define MG11_11_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_11PL) || (G11_5PL == 0) +#define MG11_11_15PL ~(1 << 4) +#else +#define MG11_11_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_11PL) || (G11_6PL == 0) +#define MG11_11_16PL ~(1 << 5) +#else +#define MG11_11_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_11PL) || (G11_7PL == 0) +#define MG11_11_17PL ~(1 << 6) +#else +#define MG11_11_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_11PL) || (G11_8PL == 0) +#define MG11_11_18PL ~(1 << 7) +#else +#define MG11_11_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_11PL) || (G11_9PL == 0) +#define MG11_11_19PL ~(1 << 8) +#else +#define MG11_11_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_11PL) || (G11_10PL == 0) +#define MG11_11_110PL ~(1 << 9) +#else +#define MG11_11_110PL 0xFFFF +#endif + +#if (G11_12PL >= G11_11PL) || (G11_12PL == 0) +#define MG11_11_112PL ~(1 << 11) +#else +#define MG11_11_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_11PL) || (G11_13PL == 0) +#define MG11_11_113PL ~(1 << 12) +#else +#define MG11_11_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_11PL) || (G11_14PL == 0) +#define MG11_11_114PL ~(1 << 13) +#else +#define MG11_11_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_11PL) || (G11_15PL == 0) +#define MG11_11_115PL ~(1 << 14) +#else +#define MG11_11_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_11PL) || (G11_16PL == 0) +#define MG11_11_116PL ~(1 << 15) +#else +#define MG11_11_116PL 0xFFFF +#endif + +#define MG11_11_111PL 0xFBFF +#define MG11_11 (MG11_11_11PL & MG11_11_12PL & MG11_11_13PL & MG11_11_14PL & \ + MG11_11_15PL & MG11_11_16PL & MG11_11_17PL & MG11_11_18PL & \ + MG11_11_19PL & MG11_11_110PL & MG11_11_111PL & MG11_11_112PL & \ + MG11_11_113PL & MG11_11_114PL & MG11_11_115PL & MG11_11_116PL) +// End of MG11_11: +// Beginning of MG1112: +#if (G11_1PL >= G11_12PL) || (G11_1PL == 0) +#define MG11_12_11PL ~(1 << 0) +#else +#define MG11_12_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_12PL) || (G11_2PL == 0) +#define MG11_12_12PL ~(1 << 1) +#else +#define MG11_12_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_12PL) || (G11_3PL == 0) +#define MG11_12_13PL ~(1 << 2) +#else +#define MG11_12_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_12PL) || (G11_4PL == 0) +#define MG11_12_14PL ~(1 << 3) +#else +#define MG11_12_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_12PL) || (G11_5PL == 0) +#define MG11_12_15PL ~(1 << 4) +#else +#define MG11_12_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_12PL) || (G11_6PL == 0) +#define MG11_12_16PL ~(1 << 5) +#else +#define MG11_12_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_12PL) || (G11_7PL == 0) +#define MG11_12_17PL ~(1 << 6) +#else +#define MG11_12_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_12PL) || (G11_8PL == 0) +#define MG11_12_18PL ~(1 << 7) +#else +#define MG11_12_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_12PL) || (G11_9PL == 0) +#define MG11_12_19PL ~(1 << 8) +#else +#define MG11_12_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_12PL) || (G11_10PL == 0) +#define MG11_12_110PL ~(1 << 9) +#else +#define MG11_12_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_12PL) || (G11_11PL == 0) +#define MG11_12_111PL ~(1 << 10) +#else +#define MG11_12_111PL 0xFFFF +#endif + +#if (G11_13PL >= G11_12PL) || (G11_13PL == 0) +#define MG11_12_113PL ~(1 << 12) +#else +#define MG11_12_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_12PL) || (G11_14PL == 0) +#define MG11_12_114PL ~(1 << 13) +#else +#define MG11_12_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_12PL) || (G11_15PL == 0) +#define MG11_12_115PL ~(1 << 14) +#else +#define MG11_12_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_12PL) || (G11_16PL == 0) +#define MG11_12_116PL ~(1 << 15) +#else +#define MG11_12_116PL 0xFFFF +#endif + +#define MG11_12_112PL 0xF7FF +#define MG11_12 (MG11_12_11PL & MG11_12_12PL & MG11_12_13PL & MG11_12_14PL & \ + MG11_12_15PL & MG11_12_16PL & MG11_12_17PL & MG11_12_18PL & \ + MG11_12_19PL & MG11_12_110PL & MG11_12_111PL & MG11_12_112PL & \ + MG11_12_113PL & MG11_12_114PL & MG11_12_115PL & MG11_12_116PL) +// End of MG11_12: +// Beginning of MG1113: +#if (G11_1PL >= G11_13PL) || (G11_1PL == 0) +#define MG11_13_11PL ~(1 << 0) +#else +#define MG11_13_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_13PL) || (G11_2PL == 0) +#define MG11_13_12PL ~(1 << 1) +#else +#define MG11_13_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_13PL) || (G11_3PL == 0) +#define MG11_13_13PL ~(1 << 2) +#else +#define MG11_13_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_13PL) || (G11_4PL == 0) +#define MG11_13_14PL ~(1 << 3) +#else +#define MG11_13_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_13PL) || (G11_5PL == 0) +#define MG11_13_15PL ~(1 << 4) +#else +#define MG11_13_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_13PL) || (G11_6PL == 0) +#define MG11_13_16PL ~(1 << 5) +#else +#define MG11_13_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_13PL) || (G11_7PL == 0) +#define MG11_13_17PL ~(1 << 6) +#else +#define MG11_13_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_13PL) || (G11_8PL == 0) +#define MG11_13_18PL ~(1 << 7) +#else +#define MG11_13_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_13PL) || (G11_9PL == 0) +#define MG11_13_19PL ~(1 << 8) +#else +#define MG11_13_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_13PL) || (G11_10PL == 0) +#define MG11_13_110PL ~(1 << 9) +#else +#define MG11_13_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_13PL) || (G11_11PL == 0) +#define MG11_13_111PL ~(1 << 10) +#else +#define MG11_13_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_13PL) || (G11_12PL == 0) +#define MG11_13_112PL ~(1 << 11) +#else +#define MG11_13_112PL 0xFFFF +#endif + +#if (G11_14PL >= G11_13PL) || (G11_14PL == 0) +#define MG11_13_114PL ~(1 << 13) +#else +#define MG11_13_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_13PL) || (G11_15PL == 0) +#define MG11_13_115PL ~(1 << 14) +#else +#define MG11_13_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_13PL) || (G11_16PL == 0) +#define MG11_13_116PL ~(1 << 15) +#else +#define MG11_13_116PL 0xFFFF +#endif + +#define MG11_13_113PL 0xEFFF +#define MG11_13 (MG11_13_11PL & MG11_13_12PL & MG11_13_13PL & MG11_13_14PL & \ + MG11_13_15PL & MG11_13_16PL & MG11_13_17PL & MG11_13_18PL & \ + MG11_13_19PL & MG11_13_110PL & MG11_13_111PL & MG11_13_112PL & \ + MG11_13_113PL & MG11_13_114PL & MG11_13_115PL & MG11_13_116PL) +// End of MG11_13: +// Beginning of MG1114: +#if (G11_1PL >= G11_14PL) || (G11_1PL == 0) +#define MG11_14_11PL ~(1 << 0) +#else +#define MG11_14_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_14PL) || (G11_2PL == 0) +#define MG11_14_12PL ~(1 << 1) +#else +#define MG11_14_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_14PL) || (G11_3PL == 0) +#define MG11_14_13PL ~(1 << 2) +#else +#define MG11_14_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_14PL) || (G11_4PL == 0) +#define MG11_14_14PL ~(1 << 3) +#else +#define MG11_14_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_14PL) || (G11_5PL == 0) +#define MG11_14_15PL ~(1 << 4) +#else +#define MG11_14_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_14PL) || (G11_6PL == 0) +#define MG11_14_16PL ~(1 << 5) +#else +#define MG11_14_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_14PL) || (G11_7PL == 0) +#define MG11_14_17PL ~(1 << 6) +#else +#define MG11_14_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_14PL) || (G11_8PL == 0) +#define MG11_14_18PL ~(1 << 7) +#else +#define MG11_14_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_14PL) || (G11_9PL == 0) +#define MG11_14_19PL ~(1 << 8) +#else +#define MG11_14_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_14PL) || (G11_10PL == 0) +#define MG11_14_110PL ~(1 << 9) +#else +#define MG11_14_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_14PL) || (G11_11PL == 0) +#define MG11_14_111PL ~(1 << 10) +#else +#define MG11_14_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_14PL) || (G11_12PL == 0) +#define MG11_14_112PL ~(1 << 11) +#else +#define MG11_14_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_14PL) || (G11_13PL == 0) +#define MG11_14_113PL ~(1 << 12) +#else +#define MG11_14_113PL 0xFFFF +#endif + +#if (G11_15PL >= G11_14PL) || (G11_15PL == 0) +#define MG11_14_115PL ~(1 << 14) +#else +#define MG11_14_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_14PL) || (G11_16PL == 0) +#define MG11_14_116PL ~(1 << 15) +#else +#define MG11_14_116PL 0xFFFF +#endif + +#define MG11_14_114PL 0xDFFF +#define MG11_14 (MG11_14_11PL & MG11_14_12PL & MG11_14_13PL & MG11_14_14PL & \ + MG11_14_15PL & MG11_14_16PL & MG11_14_17PL & MG11_14_18PL & \ + MG11_14_19PL & MG11_14_110PL & MG11_14_111PL & MG11_14_112PL & \ + MG11_14_113PL & MG11_14_114PL & MG11_14_115PL & MG11_14_116PL) +// End of MG11_14: +// Beginning of MG1115: +#if (G11_1PL >= G11_15PL) || (G11_1PL == 0) +#define MG11_15_11PL ~(1 << 0) +#else +#define MG11_15_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_15PL) || (G11_2PL == 0) +#define MG11_15_12PL ~(1 << 1) +#else +#define MG11_15_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_15PL) || (G11_3PL == 0) +#define MG11_15_13PL ~(1 << 2) +#else +#define MG11_15_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_15PL) || (G11_4PL == 0) +#define MG11_15_14PL ~(1 << 3) +#else +#define MG11_15_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_15PL) || (G11_5PL == 0) +#define MG11_15_15PL ~(1 << 4) +#else +#define MG11_15_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_15PL) || (G11_6PL == 0) +#define MG11_15_16PL ~(1 << 5) +#else +#define MG11_15_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_15PL) || (G11_7PL == 0) +#define MG11_15_17PL ~(1 << 6) +#else +#define MG11_15_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_15PL) || (G11_8PL == 0) +#define MG11_15_18PL ~(1 << 7) +#else +#define MG11_15_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_15PL) || (G11_9PL == 0) +#define MG11_15_19PL ~(1 << 8) +#else +#define MG11_15_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_15PL) || (G11_10PL == 0) +#define MG11_15_110PL ~(1 << 9) +#else +#define MG11_15_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_15PL) || (G11_11PL == 0) +#define MG11_15_111PL ~(1 << 10) +#else +#define MG11_15_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_15PL) || (G11_12PL == 0) +#define MG11_15_112PL ~(1 << 11) +#else +#define MG11_15_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_15PL) || (G11_13PL == 0) +#define MG11_15_113PL ~(1 << 12) +#else +#define MG11_15_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_15PL) || (G11_14PL == 0) +#define MG11_15_114PL ~(1 << 13) +#else +#define MG11_15_114PL 0xFFFF +#endif + +#if (G11_16PL >= G11_15PL) || (G11_16PL == 0) +#define MG11_15_116PL ~(1 << 15) +#else +#define MG11_15_116PL 0xFFFF +#endif + +#define MG11_15_115PL 0xBFFF +#define MG11_15 (MG11_15_11PL & MG11_15_12PL & MG11_15_13PL & MG11_15_14PL & \ + MG11_15_15PL & MG11_15_16PL & MG11_15_17PL & MG11_15_18PL & \ + MG11_15_19PL & MG11_15_110PL & MG11_15_111PL & MG11_15_112PL & \ + MG11_15_113PL & MG11_15_114PL & MG11_15_115PL & MG11_15_116PL) +// End of MG11_15: +// Beginning of MG1116: +#if (G11_1PL >= G11_16PL) || (G11_1PL == 0) +#define MG11_16_11PL ~(1 << 0) +#else +#define MG11_16_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_16PL) || (G11_2PL == 0) +#define MG11_16_12PL ~(1 << 1) +#else +#define MG11_16_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_16PL) || (G11_3PL == 0) +#define MG11_16_13PL ~(1 << 2) +#else +#define MG11_16_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_16PL) || (G11_4PL == 0) +#define MG11_16_14PL ~(1 << 3) +#else +#define MG11_16_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_16PL) || (G11_5PL == 0) +#define MG11_16_15PL ~(1 << 4) +#else +#define MG11_16_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_16PL) || (G11_6PL == 0) +#define MG11_16_16PL ~(1 << 5) +#else +#define MG11_16_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_16PL) || (G11_7PL == 0) +#define MG11_16_17PL ~(1 << 6) +#else +#define MG11_16_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_16PL) || (G11_8PL == 0) +#define MG11_16_18PL ~(1 << 7) +#else +#define MG11_16_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_16PL) || (G11_9PL == 0) +#define MG11_16_19PL ~(1 << 8) +#else +#define MG11_16_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_16PL) || (G11_10PL == 0) +#define MG11_16_110PL ~(1 << 9) +#else +#define MG11_16_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_16PL) || (G11_11PL == 0) +#define MG11_16_111PL ~(1 << 10) +#else +#define MG11_16_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_16PL) || (G11_12PL == 0) +#define MG11_16_112PL ~(1 << 11) +#else +#define MG11_16_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_16PL) || (G11_13PL == 0) +#define MG11_16_113PL ~(1 << 12) +#else +#define MG11_16_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_16PL) || (G11_14PL == 0) +#define MG11_16_114PL ~(1 << 13) +#else +#define MG11_16_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_16PL) || (G11_15PL == 0) +#define MG11_16_115PL ~(1 << 14) +#else +#define MG11_16_115PL 0xFFFF +#endif + +#define MG11_16_116PL 0x7FFF +#define MG11_16 (MG11_16_11PL & MG11_16_12PL & MG11_16_13PL & MG11_16_14PL & \ + MG11_16_15PL & MG11_16_16PL & MG11_16_17PL & MG11_16_18PL & \ + MG11_16_19PL & MG11_16_110PL & MG11_16_111PL & MG11_16_112PL & \ + MG11_16_113PL & MG11_16_114PL & MG11_16_115PL & MG11_16_116PL) +// End of MG11_16: + + +// +// Automatically generate PIEIER12 interrupt masks MG121 to MG1216: +// + +// Beginning of MG121: +#if (G12_2PL >= G12_1PL) || (G12_2PL == 0) +#define MG12_1_12PL ~(1 << 1) +#else +#define MG12_1_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_1PL) || (G12_3PL == 0) +#define MG12_1_13PL ~(1 << 2) +#else +#define MG12_1_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_1PL) || (G12_4PL == 0) +#define MG12_1_14PL ~(1 << 3) +#else +#define MG12_1_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_1PL) || (G12_5PL == 0) +#define MG12_1_15PL ~(1 << 4) +#else +#define MG12_1_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_1PL) || (G12_6PL == 0) +#define MG12_1_16PL ~(1 << 5) +#else +#define MG12_1_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_1PL) || (G12_7PL == 0) +#define MG12_1_17PL ~(1 << 6) +#else +#define MG12_1_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_1PL) || (G12_8PL == 0) +#define MG12_1_18PL ~(1 << 7) +#else +#define MG12_1_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_1PL) || (G12_9PL == 0) +#define MG12_1_19PL ~(1 << 8) +#else +#define MG12_1_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_1PL) || (G12_10PL == 0) +#define MG12_1_110PL ~(1 << 9) +#else +#define MG12_1_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_1PL) || (G12_11PL == 0) +#define MG12_1_111PL ~(1 << 10) +#else +#define MG12_1_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_1PL) || (G12_12PL == 0) +#define MG12_1_112PL ~(1 << 11) +#else +#define MG12_1_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_1PL) || (G12_13PL == 0) +#define MG12_1_113PL ~(1 << 12) +#else +#define MG12_1_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_1PL) || (G12_14PL == 0) +#define MG12_1_114PL ~(1 << 13) +#else +#define MG12_1_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_1PL) || (G12_15PL == 0) +#define MG12_1_115PL ~(1 << 14) +#else +#define MG12_1_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_1PL) || (G12_16PL == 0) +#define MG12_1_116PL ~(1 << 15) +#else +#define MG12_1_116PL 0xFFFF +#endif + +#define MG12_1_11PL 0xFFFE +#define MG12_1 (MG12_1_11PL & MG12_1_12PL & MG12_1_13PL & MG12_1_14PL & \ + MG12_1_15PL & MG12_1_16PL & MG12_1_17PL & MG12_1_18PL & \ + MG12_1_19PL & MG12_1_110PL & MG12_1_111PL & MG12_1_112PL & \ + MG12_1_113PL & MG12_1_114PL & MG12_1_115PL & MG12_1_116PL) +// End of MG12_1: +// Beginning of MG122: +#if (G12_1PL >= G12_2PL) || (G12_1PL == 0) +#define MG12_2_11PL ~(1 << 0) +#else +#define MG12_2_11PL 0xFFFF +#endif + +#if (G12_3PL >= G12_2PL) || (G12_3PL == 0) +#define MG12_2_13PL ~(1 << 2) +#else +#define MG12_2_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_2PL) || (G12_4PL == 0) +#define MG12_2_14PL ~(1 << 3) +#else +#define MG12_2_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_2PL) || (G12_5PL == 0) +#define MG12_2_15PL ~(1 << 4) +#else +#define MG12_2_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_2PL) || (G12_6PL == 0) +#define MG12_2_16PL ~(1 << 5) +#else +#define MG12_2_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_2PL) || (G12_7PL == 0) +#define MG12_2_17PL ~(1 << 6) +#else +#define MG12_2_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_2PL) || (G12_8PL == 0) +#define MG12_2_18PL ~(1 << 7) +#else +#define MG12_2_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_2PL) || (G12_9PL == 0) +#define MG12_2_19PL ~(1 << 8) +#else +#define MG12_2_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_2PL) || (G12_10PL == 0) +#define MG12_2_110PL ~(1 << 9) +#else +#define MG12_2_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_2PL) || (G12_11PL == 0) +#define MG12_2_111PL ~(1 << 10) +#else +#define MG12_2_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_2PL) || (G12_12PL == 0) +#define MG12_2_112PL ~(1 << 11) +#else +#define MG12_2_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_2PL) || (G12_13PL == 0) +#define MG12_2_113PL ~(1 << 12) +#else +#define MG12_2_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_2PL) || (G12_14PL == 0) +#define MG12_2_114PL ~(1 << 13) +#else +#define MG12_2_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_2PL) || (G12_15PL == 0) +#define MG12_2_115PL ~(1 << 14) +#else +#define MG12_2_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_2PL) || (G12_16PL == 0) +#define MG12_2_116PL ~(1 << 15) +#else +#define MG12_2_116PL 0xFFFF +#endif + +#define MG12_2_12PL 0xFFFD +#define MG12_2 (MG12_2_11PL & MG12_2_12PL & MG12_2_13PL & MG12_2_14PL & \ + MG12_2_15PL & MG12_2_16PL & MG12_2_17PL & MG12_2_18PL & \ + MG12_2_19PL & MG12_2_110PL & MG12_2_111PL & MG12_2_112PL & \ + MG12_2_113PL & MG12_2_114PL & MG12_2_115PL & MG12_2_116PL) +// End of MG12_2: +// Beginning of MG123: +#if (G12_1PL >= G12_3PL) || (G12_1PL == 0) +#define MG12_3_11PL ~(1 << 0) +#else +#define MG12_3_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_3PL) || (G12_2PL == 0) +#define MG12_3_12PL ~(1 << 1) +#else +#define MG12_3_12PL 0xFFFF +#endif + +#if (G12_4PL >= G12_3PL) || (G12_4PL == 0) +#define MG12_3_14PL ~(1 << 3) +#else +#define MG12_3_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_3PL) || (G12_5PL == 0) +#define MG12_3_15PL ~(1 << 4) +#else +#define MG12_3_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_3PL) || (G12_6PL == 0) +#define MG12_3_16PL ~(1 << 5) +#else +#define MG12_3_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_3PL) || (G12_7PL == 0) +#define MG12_3_17PL ~(1 << 6) +#else +#define MG12_3_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_3PL) || (G12_8PL == 0) +#define MG12_3_18PL ~(1 << 7) +#else +#define MG12_3_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_3PL) || (G12_9PL == 0) +#define MG12_3_19PL ~(1 << 8) +#else +#define MG12_3_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_3PL) || (G12_10PL == 0) +#define MG12_3_110PL ~(1 << 9) +#else +#define MG12_3_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_3PL) || (G12_11PL == 0) +#define MG12_3_111PL ~(1 << 10) +#else +#define MG12_3_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_3PL) || (G12_12PL == 0) +#define MG12_3_112PL ~(1 << 11) +#else +#define MG12_3_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_3PL) || (G12_13PL == 0) +#define MG12_3_113PL ~(1 << 12) +#else +#define MG12_3_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_3PL) || (G12_14PL == 0) +#define MG12_3_114PL ~(1 << 13) +#else +#define MG12_3_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_3PL) || (G12_15PL == 0) +#define MG12_3_115PL ~(1 << 14) +#else +#define MG12_3_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_3PL) || (G12_16PL == 0) +#define MG12_3_116PL ~(1 << 15) +#else +#define MG12_3_116PL 0xFFFF +#endif + +#define MG12_3_13PL 0xFFFB +#define MG12_3 (MG12_3_11PL & MG12_3_12PL & MG12_3_13PL & MG12_3_14PL & \ + MG12_3_15PL & MG12_3_16PL & MG12_3_17PL & MG12_3_18PL & \ + MG12_3_19PL & MG12_3_110PL & MG12_3_111PL & MG12_3_112PL & \ + MG12_3_113PL & MG12_3_114PL & MG12_3_115PL & MG12_3_116PL) +// End of MG12_3: +// Beginning of MG124: +#if (G12_1PL >= G12_4PL) || (G12_1PL == 0) +#define MG12_4_11PL ~(1 << 0) +#else +#define MG12_4_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_4PL) || (G12_2PL == 0) +#define MG12_4_12PL ~(1 << 1) +#else +#define MG12_4_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_4PL) || (G12_3PL == 0) +#define MG12_4_13PL ~(1 << 2) +#else +#define MG12_4_13PL 0xFFFF +#endif + +#if (G12_5PL >= G12_4PL) || (G12_5PL == 0) +#define MG12_4_15PL ~(1 << 4) +#else +#define MG12_4_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_4PL) || (G12_6PL == 0) +#define MG12_4_16PL ~(1 << 5) +#else +#define MG12_4_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_4PL) || (G12_7PL == 0) +#define MG12_4_17PL ~(1 << 6) +#else +#define MG12_4_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_4PL) || (G12_8PL == 0) +#define MG12_4_18PL ~(1 << 7) +#else +#define MG12_4_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_4PL) || (G12_9PL == 0) +#define MG12_4_19PL ~(1 << 8) +#else +#define MG12_4_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_4PL) || (G12_10PL == 0) +#define MG12_4_110PL ~(1 << 9) +#else +#define MG12_4_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_4PL) || (G12_11PL == 0) +#define MG12_4_111PL ~(1 << 10) +#else +#define MG12_4_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_4PL) || (G12_12PL == 0) +#define MG12_4_112PL ~(1 << 11) +#else +#define MG12_4_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_4PL) || (G12_13PL == 0) +#define MG12_4_113PL ~(1 << 12) +#else +#define MG12_4_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_4PL) || (G12_14PL == 0) +#define MG12_4_114PL ~(1 << 13) +#else +#define MG12_4_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_4PL) || (G12_15PL == 0) +#define MG12_4_115PL ~(1 << 14) +#else +#define MG12_4_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_4PL) || (G12_16PL == 0) +#define MG12_4_116PL ~(1 << 15) +#else +#define MG12_4_116PL 0xFFFF +#endif + +#define MG12_4_14PL 0xFFF7 +#define MG12_4 (MG12_4_11PL & MG12_4_12PL & MG12_4_13PL & MG12_4_14PL & \ + MG12_4_15PL & MG12_4_16PL & MG12_4_17PL & MG12_4_18PL & \ + MG12_4_19PL & MG12_4_110PL & MG12_4_111PL & MG12_4_112PL & \ + MG12_4_113PL & MG12_4_114PL & MG12_4_115PL & MG12_4_116PL) +// End of MG12_4: +// Beginning of MG125: +#if (G12_1PL >= G12_5PL) || (G12_1PL == 0) +#define MG12_5_11PL ~(1 << 0) +#else +#define MG12_5_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_5PL) || (G12_2PL == 0) +#define MG12_5_12PL ~(1 << 1) +#else +#define MG12_5_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_5PL) || (G12_3PL == 0) +#define MG12_5_13PL ~(1 << 2) +#else +#define MG12_5_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_5PL) || (G12_4PL == 0) +#define MG12_5_14PL ~(1 << 3) +#else +#define MG12_5_14PL 0xFFFF +#endif + +#if (G12_6PL >= G12_5PL) || (G12_6PL == 0) +#define MG12_5_16PL ~(1 << 5) +#else +#define MG12_5_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_5PL) || (G12_7PL == 0) +#define MG12_5_17PL ~(1 << 6) +#else +#define MG12_5_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_5PL) || (G12_8PL == 0) +#define MG12_5_18PL ~(1 << 7) +#else +#define MG12_5_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_5PL) || (G12_9PL == 0) +#define MG12_5_19PL ~(1 << 8) +#else +#define MG12_5_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_5PL) || (G12_10PL == 0) +#define MG12_5_110PL ~(1 << 9) +#else +#define MG12_5_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_5PL) || (G12_11PL == 0) +#define MG12_5_111PL ~(1 << 10) +#else +#define MG12_5_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_5PL) || (G12_12PL == 0) +#define MG12_5_112PL ~(1 << 11) +#else +#define MG12_5_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_5PL) || (G12_13PL == 0) +#define MG12_5_113PL ~(1 << 12) +#else +#define MG12_5_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_5PL) || (G12_14PL == 0) +#define MG12_5_114PL ~(1 << 13) +#else +#define MG12_5_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_5PL) || (G12_15PL == 0) +#define MG12_5_115PL ~(1 << 14) +#else +#define MG12_5_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_5PL) || (G12_16PL == 0) +#define MG12_5_116PL ~(1 << 15) +#else +#define MG12_5_116PL 0xFFFF +#endif + +#define MG12_5_15PL 0xFFEF +#define MG12_5 (MG12_5_11PL & MG12_5_12PL & MG12_5_13PL & MG12_5_14PL & \ + MG12_5_15PL & MG12_5_16PL & MG12_5_17PL & MG12_5_18PL & \ + MG12_5_19PL & MG12_5_110PL & MG12_5_111PL & MG12_5_112PL & \ + MG12_5_113PL & MG12_5_114PL & MG12_5_115PL & MG12_5_116PL) +// End of MG12_5: +// Beginning of MG126: +#if (G12_1PL >= G12_6PL) || (G12_1PL == 0) +#define MG12_6_11PL ~(1 << 0) +#else +#define MG12_6_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_6PL) || (G12_2PL == 0) +#define MG12_6_12PL ~(1 << 1) +#else +#define MG12_6_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_6PL) || (G12_3PL == 0) +#define MG12_6_13PL ~(1 << 2) +#else +#define MG12_6_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_6PL) || (G12_4PL == 0) +#define MG12_6_14PL ~(1 << 3) +#else +#define MG12_6_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_6PL) || (G12_5PL == 0) +#define MG12_6_15PL ~(1 << 4) +#else +#define MG12_6_15PL 0xFFFF +#endif + +#if (G12_7PL >= G12_6PL) || (G12_7PL == 0) +#define MG12_6_17PL ~(1 << 6) +#else +#define MG12_6_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_6PL) || (G12_8PL == 0) +#define MG12_6_18PL ~(1 << 7) +#else +#define MG12_6_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_6PL) || (G12_9PL == 0) +#define MG12_6_19PL ~(1 << 8) +#else +#define MG12_6_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_6PL) || (G12_10PL == 0) +#define MG12_6_110PL ~(1 << 9) +#else +#define MG12_6_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_6PL) || (G12_11PL == 0) +#define MG12_6_111PL ~(1 << 10) +#else +#define MG12_6_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_6PL) || (G12_12PL == 0) +#define MG12_6_112PL ~(1 << 11) +#else +#define MG12_6_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_6PL) || (G12_13PL == 0) +#define MG12_6_113PL ~(1 << 12) +#else +#define MG12_6_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_6PL) || (G12_14PL == 0) +#define MG12_6_114PL ~(1 << 13) +#else +#define MG12_6_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_6PL) || (G12_15PL == 0) +#define MG12_6_115PL ~(1 << 14) +#else +#define MG12_6_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_6PL) || (G12_16PL == 0) +#define MG12_6_116PL ~(1 << 15) +#else +#define MG12_6_116PL 0xFFFF +#endif + +#define MG12_6_16PL 0xFFDF +#define MG12_6 (MG12_6_11PL & MG12_6_12PL & MG12_6_13PL & MG12_6_14PL & \ + MG12_6_15PL & MG12_6_16PL & MG12_6_17PL & MG12_6_18PL & \ + MG12_6_19PL & MG12_6_110PL & MG12_6_111PL & MG12_6_112PL & \ + MG12_6_113PL & MG12_6_114PL & MG12_6_115PL & MG12_6_116PL) +// End of MG12_6: +// Beginning of MG127: +#if (G12_1PL >= G12_7PL) || (G12_1PL == 0) +#define MG12_7_11PL ~(1 << 0) +#else +#define MG12_7_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_7PL) || (G12_2PL == 0) +#define MG12_7_12PL ~(1 << 1) +#else +#define MG12_7_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_7PL) || (G12_3PL == 0) +#define MG12_7_13PL ~(1 << 2) +#else +#define MG12_7_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_7PL) || (G12_4PL == 0) +#define MG12_7_14PL ~(1 << 3) +#else +#define MG12_7_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_7PL) || (G12_5PL == 0) +#define MG12_7_15PL ~(1 << 4) +#else +#define MG12_7_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_7PL) || (G12_6PL == 0) +#define MG12_7_16PL ~(1 << 5) +#else +#define MG12_7_16PL 0xFFFF +#endif + +#if (G12_8PL >= G12_7PL) || (G12_8PL == 0) +#define MG12_7_18PL ~(1 << 7) +#else +#define MG12_7_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_7PL) || (G12_9PL == 0) +#define MG12_7_19PL ~(1 << 8) +#else +#define MG12_7_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_7PL) || (G12_10PL == 0) +#define MG12_7_110PL ~(1 << 9) +#else +#define MG12_7_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_7PL) || (G12_11PL == 0) +#define MG12_7_111PL ~(1 << 10) +#else +#define MG12_7_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_7PL) || (G12_12PL == 0) +#define MG12_7_112PL ~(1 << 11) +#else +#define MG12_7_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_7PL) || (G12_13PL == 0) +#define MG12_7_113PL ~(1 << 12) +#else +#define MG12_7_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_7PL) || (G12_14PL == 0) +#define MG12_7_114PL ~(1 << 13) +#else +#define MG12_7_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_7PL) || (G12_15PL == 0) +#define MG12_7_115PL ~(1 << 14) +#else +#define MG12_7_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_7PL) || (G12_16PL == 0) +#define MG12_7_116PL ~(1 << 15) +#else +#define MG12_7_116PL 0xFFFF +#endif + +#define MG12_7_17PL 0xFFBF +#define MG12_7 (MG12_7_11PL & MG12_7_12PL & MG12_7_13PL & MG12_7_14PL & \ + MG12_7_15PL & MG12_7_16PL & MG12_7_17PL & MG12_7_18PL & \ + MG12_7_19PL & MG12_7_110PL & MG12_7_111PL & MG12_7_112PL & \ + MG12_7_113PL & MG12_7_114PL & MG12_7_115PL & MG12_7_116PL) +// End of MG12_7: +// Beginning of MG128: +#if (G12_1PL >= G12_8PL) || (G12_1PL == 0) +#define MG12_8_11PL ~(1 << 0) +#else +#define MG12_8_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_8PL) || (G12_2PL == 0) +#define MG12_8_12PL ~(1 << 1) +#else +#define MG12_8_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_8PL) || (G12_3PL == 0) +#define MG12_8_13PL ~(1 << 2) +#else +#define MG12_8_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_8PL) || (G12_4PL == 0) +#define MG12_8_14PL ~(1 << 3) +#else +#define MG12_8_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_8PL) || (G12_5PL == 0) +#define MG12_8_15PL ~(1 << 4) +#else +#define MG12_8_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_8PL) || (G12_6PL == 0) +#define MG12_8_16PL ~(1 << 5) +#else +#define MG12_8_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_8PL) || (G12_7PL == 0) +#define MG12_8_17PL ~(1 << 6) +#else +#define MG12_8_17PL 0xFFFF +#endif + +#if (G12_9PL >= G12_8PL) || (G12_9PL == 0) +#define MG12_8_19PL ~(1 << 8) +#else +#define MG12_8_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_8PL) || (G12_10PL == 0) +#define MG12_8_110PL ~(1 << 9) +#else +#define MG12_8_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_8PL) || (G12_11PL == 0) +#define MG12_8_111PL ~(1 << 10) +#else +#define MG12_8_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_8PL) || (G12_12PL == 0) +#define MG12_8_112PL ~(1 << 11) +#else +#define MG12_8_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_8PL) || (G12_13PL == 0) +#define MG12_8_113PL ~(1 << 12) +#else +#define MG12_8_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_8PL) || (G12_14PL == 0) +#define MG12_8_114PL ~(1 << 13) +#else +#define MG12_8_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_8PL) || (G12_15PL == 0) +#define MG12_8_115PL ~(1 << 14) +#else +#define MG12_8_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_8PL) || (G12_16PL == 0) +#define MG12_8_116PL ~(1 << 15) +#else +#define MG12_8_116PL 0xFFFF +#endif + +#define MG12_8_18PL 0xFF7F +#define MG12_8 (MG12_8_11PL & MG12_8_12PL & MG12_8_13PL & MG12_8_14PL & \ + MG12_8_15PL & MG12_8_16PL & MG12_8_17PL & MG12_8_18PL & \ + MG12_8_19PL & MG12_8_110PL & MG12_8_111PL & MG12_8_112PL & \ + MG12_8_113PL & MG12_8_114PL & MG12_8_115PL & MG12_8_116PL) +// End of MG12_8: +// Beginning of MG129: +#if (G12_1PL >= G12_9PL) || (G12_1PL == 0) +#define MG12_9_11PL ~(1 << 0) +#else +#define MG12_9_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_9PL) || (G12_2PL == 0) +#define MG12_9_12PL ~(1 << 1) +#else +#define MG12_9_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_9PL) || (G12_3PL == 0) +#define MG12_9_13PL ~(1 << 2) +#else +#define MG12_9_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_9PL) || (G12_4PL == 0) +#define MG12_9_14PL ~(1 << 3) +#else +#define MG12_9_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_9PL) || (G12_5PL == 0) +#define MG12_9_15PL ~(1 << 4) +#else +#define MG12_9_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_9PL) || (G12_6PL == 0) +#define MG12_9_16PL ~(1 << 5) +#else +#define MG12_9_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_9PL) || (G12_7PL == 0) +#define MG12_9_17PL ~(1 << 6) +#else +#define MG12_9_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_9PL) || (G12_8PL == 0) +#define MG12_9_18PL ~(1 << 7) +#else +#define MG12_9_18PL 0xFFFF +#endif + +#if (G12_10PL >= G12_9PL) || (G12_10PL == 0) +#define MG12_9_110PL ~(1 << 9) +#else +#define MG12_9_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_9PL) || (G12_11PL == 0) +#define MG12_9_111PL ~(1 << 10) +#else +#define MG12_9_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_9PL) || (G12_12PL == 0) +#define MG12_9_112PL ~(1 << 11) +#else +#define MG12_9_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_9PL) || (G12_13PL == 0) +#define MG12_9_113PL ~(1 << 12) +#else +#define MG12_9_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_9PL) || (G12_14PL == 0) +#define MG12_9_114PL ~(1 << 13) +#else +#define MG12_9_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_9PL) || (G12_15PL == 0) +#define MG12_9_115PL ~(1 << 14) +#else +#define MG12_9_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_9PL) || (G12_16PL == 0) +#define MG12_9_116PL ~(1 << 15) +#else +#define MG12_9_116PL 0xFFFF +#endif + +#define MG12_9_19PL 0xFEFF +#define MG12_9 (MG12_9_11PL & MG12_9_12PL & MG12_9_13PL & MG12_9_14PL & \ + MG12_9_15PL & MG12_9_16PL & MG12_9_17PL & MG12_9_18PL & \ + MG12_9_19PL & MG12_9_110PL & MG12_9_111PL & MG12_9_112PL & \ + MG12_9_113PL & MG12_9_114PL & MG12_9_115PL & MG12_9_116PL) +// End of MG12_9: +// Beginning of MG1210: +#if (G12_1PL >= G12_10PL) || (G12_1PL == 0) +#define MG12_10_11PL ~(1 << 0) +#else +#define MG12_10_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_10PL) || (G12_2PL == 0) +#define MG12_10_12PL ~(1 << 1) +#else +#define MG12_10_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_10PL) || (G12_3PL == 0) +#define MG12_10_13PL ~(1 << 2) +#else +#define MG12_10_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_10PL) || (G12_4PL == 0) +#define MG12_10_14PL ~(1 << 3) +#else +#define MG12_10_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_10PL) || (G12_5PL == 0) +#define MG12_10_15PL ~(1 << 4) +#else +#define MG12_10_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_10PL) || (G12_6PL == 0) +#define MG12_10_16PL ~(1 << 5) +#else +#define MG12_10_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_10PL) || (G12_7PL == 0) +#define MG12_10_17PL ~(1 << 6) +#else +#define MG12_10_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_10PL) || (G12_8PL == 0) +#define MG12_10_18PL ~(1 << 7) +#else +#define MG12_10_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_10PL) || (G12_9PL == 0) +#define MG12_10_19PL ~(1 << 8) +#else +#define MG12_10_19PL 0xFFFF +#endif + +#if (G12_11PL >= G12_10PL) || (G12_11PL == 0) +#define MG12_10_111PL ~(1 << 10) +#else +#define MG12_10_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_10PL) || (G12_12PL == 0) +#define MG12_10_112PL ~(1 << 11) +#else +#define MG12_10_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_10PL) || (G12_13PL == 0) +#define MG12_10_113PL ~(1 << 12) +#else +#define MG12_10_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_10PL) || (G12_14PL == 0) +#define MG12_10_114PL ~(1 << 13) +#else +#define MG12_10_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_10PL) || (G12_15PL == 0) +#define MG12_10_115PL ~(1 << 14) +#else +#define MG12_10_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_10PL) || (G12_16PL == 0) +#define MG12_10_116PL ~(1 << 15) +#else +#define MG12_10_116PL 0xFFFF +#endif + +#define MG12_10_110PL 0xFDFF +#define MG12_10 (MG12_10_11PL & MG12_10_12PL & MG12_10_13PL & MG12_10_14PL & \ + MG12_10_15PL & MG12_10_16PL & MG12_10_17PL & MG12_10_18PL & \ + MG12_10_19PL & MG12_10_110PL & MG12_10_111PL & MG12_10_112PL & \ + MG12_10_113PL & MG12_10_114PL & MG12_10_115PL & MG12_10_116PL) +// End of MG12_10: +// Beginning of MG1211: +#if (G12_1PL >= G12_11PL) || (G12_1PL == 0) +#define MG12_11_11PL ~(1 << 0) +#else +#define MG12_11_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_11PL) || (G12_2PL == 0) +#define MG12_11_12PL ~(1 << 1) +#else +#define MG12_11_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_11PL) || (G12_3PL == 0) +#define MG12_11_13PL ~(1 << 2) +#else +#define MG12_11_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_11PL) || (G12_4PL == 0) +#define MG12_11_14PL ~(1 << 3) +#else +#define MG12_11_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_11PL) || (G12_5PL == 0) +#define MG12_11_15PL ~(1 << 4) +#else +#define MG12_11_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_11PL) || (G12_6PL == 0) +#define MG12_11_16PL ~(1 << 5) +#else +#define MG12_11_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_11PL) || (G12_7PL == 0) +#define MG12_11_17PL ~(1 << 6) +#else +#define MG12_11_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_11PL) || (G12_8PL == 0) +#define MG12_11_18PL ~(1 << 7) +#else +#define MG12_11_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_11PL) || (G12_9PL == 0) +#define MG12_11_19PL ~(1 << 8) +#else +#define MG12_11_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_11PL) || (G12_10PL == 0) +#define MG12_11_110PL ~(1 << 9) +#else +#define MG12_11_110PL 0xFFFF +#endif + +#if (G12_12PL >= G12_11PL) || (G12_12PL == 0) +#define MG12_11_112PL ~(1 << 11) +#else +#define MG12_11_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_11PL) || (G12_13PL == 0) +#define MG12_11_113PL ~(1 << 12) +#else +#define MG12_11_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_11PL) || (G12_14PL == 0) +#define MG12_11_114PL ~(1 << 13) +#else +#define MG12_11_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_11PL) || (G12_15PL == 0) +#define MG12_11_115PL ~(1 << 14) +#else +#define MG12_11_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_11PL) || (G12_16PL == 0) +#define MG12_11_116PL ~(1 << 15) +#else +#define MG12_11_116PL 0xFFFF +#endif + +#define MG12_11_111PL 0xFBFF +#define MG12_11 (MG12_11_11PL & MG12_11_12PL & MG12_11_13PL & MG12_11_14PL & \ + MG12_11_15PL & MG12_11_16PL & MG12_11_17PL & MG12_11_18PL & \ + MG12_11_19PL & MG12_11_110PL & MG12_11_111PL & MG12_11_112PL & \ + MG12_11_113PL & MG12_11_114PL & MG12_11_115PL & MG12_11_116PL) +// End of MG12_11: +// Beginning of MG1212: +#if (G12_1PL >= G12_12PL) || (G12_1PL == 0) +#define MG12_12_11PL ~(1 << 0) +#else +#define MG12_12_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_12PL) || (G12_2PL == 0) +#define MG12_12_12PL ~(1 << 1) +#else +#define MG12_12_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_12PL) || (G12_3PL == 0) +#define MG12_12_13PL ~(1 << 2) +#else +#define MG12_12_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_12PL) || (G12_4PL == 0) +#define MG12_12_14PL ~(1 << 3) +#else +#define MG12_12_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_12PL) || (G12_5PL == 0) +#define MG12_12_15PL ~(1 << 4) +#else +#define MG12_12_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_12PL) || (G12_6PL == 0) +#define MG12_12_16PL ~(1 << 5) +#else +#define MG12_12_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_12PL) || (G12_7PL == 0) +#define MG12_12_17PL ~(1 << 6) +#else +#define MG12_12_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_12PL) || (G12_8PL == 0) +#define MG12_12_18PL ~(1 << 7) +#else +#define MG12_12_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_12PL) || (G12_9PL == 0) +#define MG12_12_19PL ~(1 << 8) +#else +#define MG12_12_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_12PL) || (G12_10PL == 0) +#define MG12_12_110PL ~(1 << 9) +#else +#define MG12_12_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_12PL) || (G12_11PL == 0) +#define MG12_12_111PL ~(1 << 10) +#else +#define MG12_12_111PL 0xFFFF +#endif + +#if (G12_13PL >= G12_12PL) || (G12_13PL == 0) +#define MG12_12_113PL ~(1 << 12) +#else +#define MG12_12_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_12PL) || (G12_14PL == 0) +#define MG12_12_114PL ~(1 << 13) +#else +#define MG12_12_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_12PL) || (G12_15PL == 0) +#define MG12_12_115PL ~(1 << 14) +#else +#define MG12_12_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_12PL) || (G12_16PL == 0) +#define MG12_12_116PL ~(1 << 15) +#else +#define MG12_12_116PL 0xFFFF +#endif + +#define MG12_12_112PL 0xF7FF +#define MG12_12 (MG12_12_11PL & MG12_12_12PL & MG12_12_13PL & MG12_12_14PL & \ + MG12_12_15PL & MG12_12_16PL & MG12_12_17PL & MG12_12_18PL & \ + MG12_12_19PL & MG12_12_110PL & MG12_12_111PL & MG12_12_112PL & \ + MG12_12_113PL & MG12_12_114PL & MG12_12_115PL & MG12_12_116PL) +// End of MG12_12: +// Beginning of MG1213: +#if (G12_1PL >= G12_13PL) || (G12_1PL == 0) +#define MG12_13_11PL ~(1 << 0) +#else +#define MG12_13_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_13PL) || (G12_2PL == 0) +#define MG12_13_12PL ~(1 << 1) +#else +#define MG12_13_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_13PL) || (G12_3PL == 0) +#define MG12_13_13PL ~(1 << 2) +#else +#define MG12_13_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_13PL) || (G12_4PL == 0) +#define MG12_13_14PL ~(1 << 3) +#else +#define MG12_13_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_13PL) || (G12_5PL == 0) +#define MG12_13_15PL ~(1 << 4) +#else +#define MG12_13_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_13PL) || (G12_6PL == 0) +#define MG12_13_16PL ~(1 << 5) +#else +#define MG12_13_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_13PL) || (G12_7PL == 0) +#define MG12_13_17PL ~(1 << 6) +#else +#define MG12_13_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_13PL) || (G12_8PL == 0) +#define MG12_13_18PL ~(1 << 7) +#else +#define MG12_13_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_13PL) || (G12_9PL == 0) +#define MG12_13_19PL ~(1 << 8) +#else +#define MG12_13_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_13PL) || (G12_10PL == 0) +#define MG12_13_110PL ~(1 << 9) +#else +#define MG12_13_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_13PL) || (G12_11PL == 0) +#define MG12_13_111PL ~(1 << 10) +#else +#define MG12_13_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_13PL) || (G12_12PL == 0) +#define MG12_13_112PL ~(1 << 11) +#else +#define MG12_13_112PL 0xFFFF +#endif + +#if (G12_14PL >= G12_13PL) || (G12_14PL == 0) +#define MG12_13_114PL ~(1 << 13) +#else +#define MG12_13_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_13PL) || (G12_15PL == 0) +#define MG12_13_115PL ~(1 << 14) +#else +#define MG12_13_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_13PL) || (G12_16PL == 0) +#define MG12_13_116PL ~(1 << 15) +#else +#define MG12_13_116PL 0xFFFF +#endif + +#define MG12_13_113PL 0xEFFF +#define MG12_13 (MG12_13_11PL & MG12_13_12PL & MG12_13_13PL & MG12_13_14PL & \ + MG12_13_15PL & MG12_13_16PL & MG12_13_17PL & MG12_13_18PL & \ + MG12_13_19PL & MG12_13_110PL & MG12_13_111PL & MG12_13_112PL & \ + MG12_13_113PL & MG12_13_114PL & MG12_13_115PL & MG12_13_116PL) +// End of MG12_13: +// Beginning of MG1214: +#if (G12_1PL >= G12_14PL) || (G12_1PL == 0) +#define MG12_14_11PL ~(1 << 0) +#else +#define MG12_14_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_14PL) || (G12_2PL == 0) +#define MG12_14_12PL ~(1 << 1) +#else +#define MG12_14_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_14PL) || (G12_3PL == 0) +#define MG12_14_13PL ~(1 << 2) +#else +#define MG12_14_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_14PL) || (G12_4PL == 0) +#define MG12_14_14PL ~(1 << 3) +#else +#define MG12_14_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_14PL) || (G12_5PL == 0) +#define MG12_14_15PL ~(1 << 4) +#else +#define MG12_14_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_14PL) || (G12_6PL == 0) +#define MG12_14_16PL ~(1 << 5) +#else +#define MG12_14_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_14PL) || (G12_7PL == 0) +#define MG12_14_17PL ~(1 << 6) +#else +#define MG12_14_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_14PL) || (G12_8PL == 0) +#define MG12_14_18PL ~(1 << 7) +#else +#define MG12_14_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_14PL) || (G12_9PL == 0) +#define MG12_14_19PL ~(1 << 8) +#else +#define MG12_14_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_14PL) || (G12_10PL == 0) +#define MG12_14_110PL ~(1 << 9) +#else +#define MG12_14_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_14PL) || (G12_11PL == 0) +#define MG12_14_111PL ~(1 << 10) +#else +#define MG12_14_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_14PL) || (G12_12PL == 0) +#define MG12_14_112PL ~(1 << 11) +#else +#define MG12_14_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_14PL) || (G12_13PL == 0) +#define MG12_14_113PL ~(1 << 12) +#else +#define MG12_14_113PL 0xFFFF +#endif + +#if (G12_15PL >= G12_14PL) || (G12_15PL == 0) +#define MG12_14_115PL ~(1 << 14) +#else +#define MG12_14_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_14PL) || (G12_16PL == 0) +#define MG12_14_116PL ~(1 << 15) +#else +#define MG12_14_116PL 0xFFFF +#endif + +#define MG12_14_114PL 0xDFFF +#define MG12_14 (MG12_14_11PL & MG12_14_12PL & MG12_14_13PL & MG12_14_14PL & \ + MG12_14_15PL & MG12_14_16PL & MG12_14_17PL & MG12_14_18PL & \ + MG12_14_19PL & MG12_14_110PL & MG12_14_111PL & MG12_14_112PL & \ + MG12_14_113PL & MG12_14_114PL & MG12_14_115PL & MG12_14_116PL) +// End of MG12_14: +// Beginning of MG1215: +#if (G12_1PL >= G12_15PL) || (G12_1PL == 0) +#define MG12_15_11PL ~(1 << 0) +#else +#define MG12_15_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_15PL) || (G12_2PL == 0) +#define MG12_15_12PL ~(1 << 1) +#else +#define MG12_15_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_15PL) || (G12_3PL == 0) +#define MG12_15_13PL ~(1 << 2) +#else +#define MG12_15_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_15PL) || (G12_4PL == 0) +#define MG12_15_14PL ~(1 << 3) +#else +#define MG12_15_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_15PL) || (G12_5PL == 0) +#define MG12_15_15PL ~(1 << 4) +#else +#define MG12_15_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_15PL) || (G12_6PL == 0) +#define MG12_15_16PL ~(1 << 5) +#else +#define MG12_15_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_15PL) || (G12_7PL == 0) +#define MG12_15_17PL ~(1 << 6) +#else +#define MG12_15_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_15PL) || (G12_8PL == 0) +#define MG12_15_18PL ~(1 << 7) +#else +#define MG12_15_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_15PL) || (G12_9PL == 0) +#define MG12_15_19PL ~(1 << 8) +#else +#define MG12_15_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_15PL) || (G12_10PL == 0) +#define MG12_15_110PL ~(1 << 9) +#else +#define MG12_15_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_15PL) || (G12_11PL == 0) +#define MG12_15_111PL ~(1 << 10) +#else +#define MG12_15_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_15PL) || (G12_12PL == 0) +#define MG12_15_112PL ~(1 << 11) +#else +#define MG12_15_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_15PL) || (G12_13PL == 0) +#define MG12_15_113PL ~(1 << 12) +#else +#define MG12_15_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_15PL) || (G12_14PL == 0) +#define MG12_15_114PL ~(1 << 13) +#else +#define MG12_15_114PL 0xFFFF +#endif + +#if (G12_16PL >= G12_15PL) || (G12_16PL == 0) +#define MG12_15_116PL ~(1 << 15) +#else +#define MG12_15_116PL 0xFFFF +#endif + +#define MG12_15_115PL 0xBFFF +#define MG12_15 (MG12_15_11PL & MG12_15_12PL & MG12_15_13PL & MG12_15_14PL & \ + MG12_15_15PL & MG12_15_16PL & MG12_15_17PL & MG12_15_18PL & \ + MG12_15_19PL & MG12_15_110PL & MG12_15_111PL & MG12_15_112PL & \ + MG12_15_113PL & MG12_15_114PL & MG12_15_115PL & MG12_15_116PL) +// End of MG12_15: +// Beginning of MG1216: +#if (G12_1PL >= G12_16PL) || (G12_1PL == 0) +#define MG12_16_11PL ~(1 << 0) +#else +#define MG12_16_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_16PL) || (G12_2PL == 0) +#define MG12_16_12PL ~(1 << 1) +#else +#define MG12_16_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_16PL) || (G12_3PL == 0) +#define MG12_16_13PL ~(1 << 2) +#else +#define MG12_16_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_16PL) || (G12_4PL == 0) +#define MG12_16_14PL ~(1 << 3) +#else +#define MG12_16_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_16PL) || (G12_5PL == 0) +#define MG12_16_15PL ~(1 << 4) +#else +#define MG12_16_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_16PL) || (G12_6PL == 0) +#define MG12_16_16PL ~(1 << 5) +#else +#define MG12_16_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_16PL) || (G12_7PL == 0) +#define MG12_16_17PL ~(1 << 6) +#else +#define MG12_16_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_16PL) || (G12_8PL == 0) +#define MG12_16_18PL ~(1 << 7) +#else +#define MG12_16_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_16PL) || (G12_9PL == 0) +#define MG12_16_19PL ~(1 << 8) +#else +#define MG12_16_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_16PL) || (G12_10PL == 0) +#define MG12_16_110PL ~(1 << 9) +#else +#define MG12_16_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_16PL) || (G12_11PL == 0) +#define MG12_16_111PL ~(1 << 10) +#else +#define MG12_16_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_16PL) || (G12_12PL == 0) +#define MG12_16_112PL ~(1 << 11) +#else +#define MG12_16_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_16PL) || (G12_13PL == 0) +#define MG12_16_113PL ~(1 << 12) +#else +#define MG12_16_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_16PL) || (G12_14PL == 0) +#define MG12_16_114PL ~(1 << 13) +#else +#define MG12_16_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_16PL) || (G12_15PL == 0) +#define MG12_16_115PL ~(1 << 14) +#else +#define MG12_16_115PL 0xFFFF +#endif + +#define MG12_16_116PL 0x7FFF +#define MG12_16 (MG12_16_11PL & MG12_16_12PL & MG12_16_13PL & MG12_16_14PL & \ + MG12_16_15PL & MG12_16_16PL & MG12_16_17PL & MG12_16_18PL & \ + MG12_16_19PL & MG12_16_110PL & MG12_16_111PL & MG12_16_112PL & \ + MG12_16_113PL & MG12_16_114PL & MG12_16_115PL & MG12_16_116PL) +// End of MG12_16: + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // eof + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_SysCtrl_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_SysCtrl_defines.h new file mode 100644 index 00000000000..a0f342d14c2 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_SysCtrl_defines.h @@ -0,0 +1,63 @@ +//########################################################################### +// +// FILE: F2837xD_SysCtrl_defines.h +// +// TITLE: F2837xD LPM support definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SYSCTRL_DEFINES_H +#define F2837xD_SYSCTRL_DEFINES_H + +// +// Defines +// +#define LPM_IDLE 0x0 +#define LPM_STANDBY 0x1 +#define LPM_HALT 0x2 +#define LPM_HIB 0x3 + +// +//Key value used for write access to the flash pump semaphore register +// +#define IPC_PUMP_KEY 0x5a5a0000 + +#endif // end of F2837xD_SYSCTRL_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Systick_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Systick_defines.h new file mode 100644 index 00000000000..dbf45cb249b --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Systick_defines.h @@ -0,0 +1,80 @@ +//########################################################################### +// +// FILE: systick.h +// +// TITLE: Stellaris style wrapper driver for C28x CPU Timer 0. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Function Prototypes +// +extern void SysTickInit(void); +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +// +// Mark the end of the C bindings section for C++ compilers. +// +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_Upp_defines.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_Upp_defines.h new file mode 100644 index 00000000000..43d602bfb01 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_Upp_defines.h @@ -0,0 +1,86 @@ +//########################################################################### +// +// FILE: F2837xD_Upp_defines.h +// +// TITLE: #defines used in Upp examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_UPP_DEFINES_H +#define F2837xD_UPP_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define uPP_TX_MSGRAM_ADDR 0x6C00 +#define uPP_TX_MSGRAM_SIZE 512 + +#define uPP_RX_MSGRAM_ADDR 0x6E00 +#define uPP_RX_MSGRAM_SIZE 512 + +#define uPP_RX_MODE 0 +#define uPP_TX_MODE 1 + +#define uPP_SDR 0 +#define uPP_DDR 1 + +#define uPP_TX_SIZE_64B 0 +#define uPP_TX_SIZE_128B 1 +#define uPP_TX_SIZE_256B 3 + +#define uPP_RX_SIZE_64B 0 +#define uPP_RX_SIZE_128B 1 +#define uPP_RX_SIZE_256B 3 + +#define uPP_INT_EOWI 0x8 +#define uPP_INT_EOLI 0x10 +#define uPP_INT_EOWQ 0x800 +#define uPP_INT_EOLQ 0x1000 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_UPP_DEFINES_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_cputimervars.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_cputimervars.h new file mode 100644 index 00000000000..0f32f58aeae --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_cputimervars.h @@ -0,0 +1,138 @@ +//########################################################################### +// +// FILE: F2837xD_Cputimers.h +// +// TITLE: F2837xD Device CPUTIMERS Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_CPUTIMERVARS_H +#define F2837xD_CPUTIMERVARS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Globals +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +extern struct CPUTIMER_VARS CpuTimer0; +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines +// + +// +// Start Timer: +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// Start Timer: +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +// +// Function Prototypes +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of F2837xD_CPUTIMERVARS_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_defaultisr.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_defaultisr.h new file mode 100644 index 00000000000..3f351d85b7c --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_defaultisr.h @@ -0,0 +1,216 @@ +//########################################################################### +// +// FILE: F2837xD_defaultisr.h +// +// TITLE: F2837xD Device Default Interrupt Service Routines Definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_DEFAULT_ISR_H +#define F2837xD_DEFAULT_ISR_H +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the F2837xD_pievect.h +// file. +// +interrupt void TIMER1_ISR(void); // CPU Timer 1 Interrupt +interrupt void TIMER2_ISR(void); // CPU Timer 2 Interrupt +interrupt void DATALOG_ISR(void); // Datalogging Interrupt +interrupt void RTOS_ISR(void); // RTOS Interrupt +interrupt void EMU_ISR(void); // Emulation Interrupt +interrupt void NMI_ISR(void); // Non-Maskable Interrupt +interrupt void ILLEGAL_ISR(void); // Illegal Operation Trap +interrupt void USER1_ISR(void); // User Defined Trap 1 +interrupt void USER2_ISR(void); // User Defined Trap 2 +interrupt void USER3_ISR(void); // User Defined Trap 3 +interrupt void USER4_ISR(void); // User Defined Trap 4 +interrupt void USER5_ISR(void); // User Defined Trap 5 +interrupt void USER6_ISR(void); // User Defined Trap 6 +interrupt void USER7_ISR(void); // User Defined Trap 7 +interrupt void USER8_ISR(void); // User Defined Trap 8 +interrupt void USER9_ISR(void); // User Defined Trap 9 +interrupt void USER10_ISR(void); // User Defined Trap 10 +interrupt void USER11_ISR(void); // User Defined Trap 11 +interrupt void USER12_ISR(void); // User Defined Trap 12 +interrupt void ADCA1_ISR(void); // 1.1 - ADCA Interrupt 1 +interrupt void ADCB1_ISR(void); // 1.2 - ADCB Interrupt 1 +interrupt void ADCC1_ISR(void); // 1.3 - ADCC Interrupt 1 +interrupt void XINT1_ISR(void); // 1.4 - XINT1 Interrupt +interrupt void XINT2_ISR(void); // 1.5 - XINT2 Interrupt +interrupt void ADCD1_ISR(void); // 1.6 - ADCD Interrupt 1 +interrupt void TIMER0_ISR(void); // 1.7 - Timer 0 Interrupt +interrupt void WAKE_ISR(void); // 1.8 - Standby and Halt Wakeup Interrupt +interrupt void EPWM1_TZ_ISR(void); // 2.1 - ePWM1 Trip Zone Interrupt +interrupt void EPWM2_TZ_ISR(void); // 2.2 - ePWM2 Trip Zone Interrupt +interrupt void EPWM3_TZ_ISR(void); // 2.3 - ePWM3 Trip Zone Interrupt +interrupt void EPWM4_TZ_ISR(void); // 2.4 - ePWM4 Trip Zone Interrupt +interrupt void EPWM5_TZ_ISR(void); // 2.5 - ePWM5 Trip Zone Interrupt +interrupt void EPWM6_TZ_ISR(void); // 2.6 - ePWM6 Trip Zone Interrupt +interrupt void EPWM7_TZ_ISR(void); // 2.7 - ePWM7 Trip Zone Interrupt +interrupt void EPWM8_TZ_ISR(void); // 2.8 - ePWM8 Trip Zone Interrupt +interrupt void EPWM1_ISR(void); // 3.1 - ePWM1 Interrupt +interrupt void EPWM2_ISR(void); // 3.2 - ePWM2 Interrupt +interrupt void EPWM3_ISR(void); // 3.3 - ePWM3 Interrupt +interrupt void EPWM4_ISR(void); // 3.4 - ePWM4 Interrupt +interrupt void EPWM5_ISR(void); // 3.5 - ePWM5 Interrupt +interrupt void EPWM6_ISR(void); // 3.6 - ePWM6 Interrupt +interrupt void EPWM7_ISR(void); // 3.7 - ePWM7 Interrupt +interrupt void EPWM8_ISR(void); // 3.8 - ePWM8 Interrupt +interrupt void ECAP1_ISR(void); // 4.1 - eCAP1 Interrupt +interrupt void ECAP2_ISR(void); // 4.2 - eCAP2 Interrupt +interrupt void ECAP3_ISR(void); // 4.3 - eCAP3 Interrupt +interrupt void ECAP4_ISR(void); // 4.4 - eCAP4 Interrupt +interrupt void ECAP5_ISR(void); // 4.5 - eCAP5 Interrupt +interrupt void ECAP6_ISR(void); // 4.6 - eCAP6 Interrupt +interrupt void EQEP1_ISR(void); // 5.1 - eQEP1 Interrupt +interrupt void EQEP2_ISR(void); // 5.2 - eQEP2 Interrupt +interrupt void EQEP3_ISR(void); // 5.3 - eQEP3 Interrupt +interrupt void SPIA_RX_ISR(void); // 6.1 - SPIA Receive Interrupt +interrupt void SPIA_TX_ISR(void); // 6.2 - SPIA Transmit Interrupt +interrupt void SPIB_RX_ISR(void); // 6.3 - SPIB Receive Interrupt +interrupt void SPIB_TX_ISR(void); // 6.4 - SPIB Transmit Interrupt +interrupt void MCBSPA_RX_ISR(void); // 6.5 - McBSPA Receive Interrupt +interrupt void MCBSPA_TX_ISR(void); // 6.6 - McBSPA Transmit Interrupt +interrupt void MCBSPB_RX_ISR(void); // 6.7 - McBSPB Receive Interrupt +interrupt void MCBSPB_TX_ISR(void); // 6.8 - McBSPB Transmit Interrupt +interrupt void DMA_CH1_ISR(void); // 7.1 - DMA Channel 1 Interrupt +interrupt void DMA_CH2_ISR(void); // 7.2 - DMA Channel 2 Interrupt +interrupt void DMA_CH3_ISR(void); // 7.3 - DMA Channel 3 Interrupt +interrupt void DMA_CH4_ISR(void); // 7.4 - DMA Channel 4 Interrupt +interrupt void DMA_CH5_ISR(void); // 7.5 - DMA Channel 5 Interrupt +interrupt void DMA_CH6_ISR(void); // 7.6 - DMA Channel 6 Interrupt +interrupt void I2CA_ISR(void); // 8.1 - I2CA Interrupt 1 +interrupt void I2CA_FIFO_ISR(void); // 8.2 - I2CA Interrupt 2 +interrupt void I2CB_ISR(void); // 8.3 - I2CB Interrupt 1 +interrupt void I2CB_FIFO_ISR(void); // 8.4 - I2CB Interrupt 2 +interrupt void SCIC_RX_ISR(void); // 8.5 - SCIC Receive Interrupt +interrupt void SCIC_TX_ISR(void); // 8.6 - SCIC Transmit Interrupt +interrupt void SCID_RX_ISR(void); // 8.7 - SCID Receive Interrupt +interrupt void SCID_TX_ISR(void); // 8.8 - SCID Transmit Interrupt +interrupt void SCIA_RX_ISR(void); // 9.1 - SCIA Receive Interrupt +interrupt void SCIA_TX_ISR(void); // 9.2 - SCIA Transmit Interrupt +interrupt void SCIB_RX_ISR(void); // 9.3 - SCIB Receive Interrupt +interrupt void SCIB_TX_ISR(void); // 9.4 - SCIB Transmit Interrupt +interrupt void CANA0_ISR(void); // 9.5 - CANA Interrupt 0 +interrupt void CANA1_ISR(void); // 9.6 - CANA Interrupt 1 +interrupt void CANB0_ISR(void); // 9.7 - CANB Interrupt 0 +interrupt void CANB1_ISR(void); // 9.8 - CANB Interrupt 1 +interrupt void ADCA_EVT_ISR(void); // 10.1 - ADCA Event Interrupt +interrupt void ADCA2_ISR(void); // 10.2 - ADCA Interrupt 2 +interrupt void ADCA3_ISR(void); // 10.3 - ADCA Interrupt 3 +interrupt void ADCA4_ISR(void); // 10.4 - ADCA Interrupt 4 +interrupt void ADCB_EVT_ISR(void); // 10.5 - ADCB Event Interrupt +interrupt void ADCB2_ISR(void); // 10.6 - ADCB Interrupt 2 +interrupt void ADCB3_ISR(void); // 10.7 - ADCB Interrupt 3 +interrupt void ADCB4_ISR(void); // 10.8 - ADCB Interrupt 4 +interrupt void CLA1_1_ISR(void); // 11.1 - CLA1 Interrupt 1 +interrupt void CLA1_2_ISR(void); // 11.2 - CLA1 Interrupt 2 +interrupt void CLA1_3_ISR(void); // 11.3 - CLA1 Interrupt 3 +interrupt void CLA1_4_ISR(void); // 11.4 - CLA1 Interrupt 4 +interrupt void CLA1_5_ISR(void); // 11.5 - CLA1 Interrupt 5 +interrupt void CLA1_6_ISR(void); // 11.6 - CLA1 Interrupt 6 +interrupt void CLA1_7_ISR(void); // 11.7 - CLA1 Interrupt 7 +interrupt void CLA1_8_ISR(void); // 11.8 - CLA1 Interrupt 8 +interrupt void XINT3_ISR(void); // 12.1 - XINT3 Interrupt +interrupt void XINT4_ISR(void); // 12.2 - XINT4 Interrupt +interrupt void XINT5_ISR(void); // 12.3 - XINT5 Interrupt +interrupt void VCU_ISR(void); // 12.6 - VCU Interrupt +interrupt void FPU_OVERFLOW_ISR(void); // 12.7 - FPU Overflow Interrupt +interrupt void FPU_UNDERFLOW_ISR(void); // 12.8 - FPU Underflow Interrupt +interrupt void IPC0_ISR(void); // 1.13 - IPC Interrupt 0 +interrupt void IPC1_ISR(void); // 1.14 - IPC Interrupt 1 +interrupt void IPC2_ISR(void); // 1.15 - IPC Interrupt 2 +interrupt void IPC3_ISR(void); // 1.16 - IPC Interrupt 3 +interrupt void EPWM9_TZ_ISR(void); // 2.9 - ePWM9 Trip Zone Interrupt +interrupt void EPWM10_TZ_ISR(void); // 2.10 - ePWM10 Trip Zone Interrupt +interrupt void EPWM11_TZ_ISR(void); // 2.11 - ePWM11 Trip Zone Interrupt +interrupt void EPWM12_TZ_ISR(void); // 2.12 - ePWM12 Trip Zone Interrupt +interrupt void EPWM9_ISR(void); // 3.9 - ePWM9 Interrupt +interrupt void EPWM10_ISR(void); // 3.10 - ePWM10 Interrupt +interrupt void EPWM11_ISR(void); // 3.11 - ePWM11 Interrupt +interrupt void EPWM12_ISR(void); // 3.12 - ePWM12 Interrupt +interrupt void SD1_ISR(void); // 5.9 - SD1 Interrupt +interrupt void SD2_ISR(void); // 5.10 - SD2 Interrupt +interrupt void SPIC_RX_ISR(void); // 6.9 - SPIC Receive Interrupt +interrupt void SPIC_TX_ISR(void); // 6.10 - SPIC Transmit Interrupt +interrupt void UPPA_ISR(void); // 8.15 - uPPA Interrupt +interrupt void USBA_ISR(void); // 9.15 - USBA Interrupt +interrupt void ADCC_EVT_ISR(void); // 10.9 - ADCC Event Interrupt +interrupt void ADCC2_ISR(void); // 10.10 - ADCC Interrupt 2 +interrupt void ADCC3_ISR(void); // 10.11 - ADCC Interrupt 3 +interrupt void ADCC4_ISR(void); // 10.12 - ADCC Interrupt 4 +interrupt void ADCD_EVT_ISR(void); // 10.13 - ADCD Event Interrupt +interrupt void ADCD2_ISR(void); // 10.14 - ADCD Interrupt 2 +interrupt void ADCD3_ISR(void); // 10.15 - ADCD Interrupt 3 +interrupt void ADCD4_ISR(void); // 10.16 - ADCD Interrupt 4 +interrupt void EMIF_ERROR_ISR(void); // 12.9 - EMIF Error Interrupt +interrupt void RAM_CORRECTABLE_ERROR_ISR(void); // 12.10 - RAM Correctable + // Error Interrupt +interrupt void FLASH_CORRECTABLE_ERROR_ISR(void); // 12.11 - Flash Correctable + // Error Interrupt +interrupt void RAM_ACCESS_VIOLATION_ISR(void); // 12.12 - RAM Access + // Violation Interrupt +interrupt void SYS_PLL_SLIP_ISR(void); // 12.13 - System PLL Slip + // Interrupt +interrupt void AUX_PLL_SLIP_ISR(void); // 12.14 - Auxiliary PLL + // Slip Interrupt +interrupt void CLA_OVERFLOW_ISR(void); // 12.15 - CLA Overflow + // Interrupt +interrupt void CLA_UNDERFLOW_ISR(void); // 12.16 - CLA Underflow + // Interrupt + +// +// Catch-all for PIE Reserved Locations for testing purposes: +// +interrupt void PIE_RESERVED_ISR(void); // Reserved ISR +interrupt void EMPTY_ISR(void); // Only does a return +interrupt void NOTUSED_ISR(void); // Unused ISR +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of F2837xD_PIEVECT_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_sci_io.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_sci_io.h new file mode 100644 index 00000000000..41ecacb9be2 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_sci_io.h @@ -0,0 +1,70 @@ +//########################################################################### +// +// FILE: F2837xD_sci_io.h +// +// TITLE: Prototypes for SCI redirection to STDIO +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SCI_IO_H +#define F2837xD_SCI_IO_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Function Prototypes +// +extern int SCI_open(const char * path, unsigned flags, int llv_fd); +extern int SCI_close(int dev_fd); +extern int SCI_read(int dev_fd, char * buf, unsigned count); +extern int SCI_write(int dev_fd, char * buf, unsigned count); +extern off_t SCI_lseek(int dev_fd, off_t offset, int origin); +extern int SCI_unlink(const char * path); +extern int SCI_rename(const char * old_name, const char * new_name); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_sdfm_drivers.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_sdfm_drivers.h new file mode 100644 index 00000000000..0cde1ad5ae5 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_sdfm_drivers.h @@ -0,0 +1,530 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm_drivers.h +// +// TITLE: Defines and Macros for the SDFM driver Controller +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SDFM_DRIVERS_H +#define F2837xD_SDFM_DRIVERS_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// This is used to select either SDFM module 1 & SDFM module 2 +// +#define SDFM1 1 //Can be used to select SDFM module 1 +#define SDFM2 2 //Can be used to select SDFM module 2 + +// +// Max OSR values of different modules +// +#define COMPARATOR_MAX_OSR 32 //Max OSR for comparator +#define DATA_FILTER_MAX_OSR 256 //Max OSR for Data filter + +// +// Different Input Control modes +// These values can be passed as argument to Sdfm_configureInputCtrl() +// +#define MODE_0 0 //Used to select Mode0 : + //Modulator clock rate = Modulator data rate +#define MODE_1 1 //Used to select MODE1 : + //Modulator clock rate = (Modulator data rate / 2) +#define MODE_2 2 //Used to select MODE2 : + //Manchester encoded data + //(Modulator clock is encoded into data) +#define MODE_3 3 //Used to select MODE3 : + //Modulator clock rate = (2 x Modulator data rate) + +// +// The following are values that can be passed to following functions +// +// (1) Sdfm_configureInputCtrl() +// (2) Sdfm_configureComparator() +// (3) Sdfm_configureData_filter() +// (4) Sdfm_configureInterrupt() +// +#define FILTER1 0x01 //Used to select filter1 for comparator or Data filter +#define FILTER2 0x02 //Used to select filter2 for comparator or Data filter +#define FILTER3 0x04 //Used to select filter3 for comparator or Data filter +#define FILTER4 0x08 //Used to select filter4 for comparator or Data filter + +// +// The following are values that can be passed to Sdfm_configureData_filter() +// +#define FILTER_DISABLE 0 //Used to disable filter +#define FILTER_ENABLE 1 //Used to enable filter + +// +// The following are values that can be passed to following functions +// +// (1) Sdfm_configureComparator() +// (2) Sdfm_configureData_filter() +// +#define SINCFAST 0x00 //Used to select Sincfast filter type for comparator + //or Data filter +#define SINC1 0x01 //Used to select Sinc1 filter type for comparator + //or Data filter +#define SINC2 0x02 //Used to select Sinc2 filter type for comparator + //or Data filter +#define SINC3 0x03 //Used to select Sinc3 filter type for comparator + //or Data filter + +// +// Enable / Disable High-level threshold interrupt for Comparator filter output +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define IEH_DISABLE 0 //Used to disable over value interrupt to CPU +#define IEH_ENABLE 1 //Used to enable over value interrupt to CPU + +// +// Enable / Disable Low-level threshold interrupt for Comparator filter output +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define IEL_DISABLE 0 //Used to disable under value interrupt to CPU +#define IEL_ENABLE 1 //Used to enable under value interrupt to CPU + +// +//Enable / Disable modulator failure interrupt +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define MFIE_DISABLE 0 //Used to disable modulator failure interrupt to CPU +#define MFIE_ENABLE 1 //Used to enable modulator failure interrupt to CPU + +// +// Enable / Disable Acknowledge flag +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define AE_DISABLE 0 //Used to disable new filter data acknowledge + //interrupt to CPU +#define AE_ENABLE 1 //Used to enable new filter data acknowledge + //interrupt to CPU + +// +// Sinc Filter Reset enable / disable for External Reset from PWM Compare +// output +// This following value can be passed to Sdfm_configureExternalreset() +// +#define FILTER_1_EXT_RESET_DISABLE 0 +#define FILTER_1_EXT_RESET_ENABLE 1 +#define FILTER_2_EXT_RESET_DISABLE 0 +#define FILTER_2_EXT_RESET_ENABLE 1 +#define FILTER_3_EXT_RESET_DISABLE 0 +#define FILTER_3_EXT_RESET_ENABLE 1 +#define FILTER_4_EXT_RESET_DISABLE 0 +#define FILTER_4_EXT_RESET_ENABLE 1 + +// +// Filter output data can be represented in 16 bit (or) 32 bit format +// This value can be passed to Sdfm_configureData_filter() +// +#define DATA_16_BIT 0 //Data stored in 16b 2's complement +#define DATA_32_BIT 1 //Data stored in 32b 2's complement + +// +// Macro to read the SDFM1 filter data in 16 bit format +// +#define SDFM1_READ_FILTER1_DATA_16BIT *(volatile Uint16 *)0x5E17 +#define SDFM1_READ_FILTER2_DATA_16BIT *(volatile Uint16 *)0x5E27 +#define SDFM1_READ_FILTER3_DATA_16BIT *(volatile Uint16 *)0x5E37 +#define SDFM1_READ_FILTER4_DATA_16BIT *(volatile Uint16 *)0x5E47 + +// +// Macro to read the SDFM1 filter data in 32 bit format +// +#define SDFM1_READ_FILTER1_DATA_32BIT *(volatile Uint32 *)0x5E16 +#define SDFM1_READ_FILTER2_DATA_32BIT *(volatile Uint32 *)0x5E26 +#define SDFM1_READ_FILTER3_DATA_32BIT *(volatile Uint32 *)0x5E36 +#define SDFM1_READ_FILTER4_DATA_32BIT *(volatile Uint32 *)0x5E46 + +// +// Macro to read the SDFM2 filter data in 16 bit format +// +#define SDFM2_READ_FILTER1_DATA_16BIT *(volatile Uint16 *)0x5E97 +#define SDFM2_READ_FILTER2_DATA_16BIT *(volatile Uint16 *)0x5EA7 +#define SDFM2_READ_FILTER3_DATA_16BIT *(volatile Uint16 *)0x5EB7 +#define SDFM2_READ_FILTER4_DATA_16BIT *(volatile Uint16 *)0x5EC7 + +// +// Macro to read the SDFM2 filter data in 32 bit format +// +#define SDFM2_READ_FILTER1_DATA_32BIT *(volatile Uint16 *)0x5E96 +#define SDFM2_READ_FILTER2_DATA_32BIT *(volatile Uint16 *)0x5EA6 +#define SDFM2_READ_FILTER3_DATA_32BIT *(volatile Uint16 *)0x5EB6 +#define SDFM2_READ_FILTER4_DATA_32BIT *(volatile Uint16 *)0x5EC6 + +// +// The following are defines for different OSR values +// +#define OSR_1 0 +#define OSR_2 1 +#define OSR_3 2 +#define OSR_4 3 +#define OSR_5 4 +#define OSR_6 5 +#define OSR_7 6 +#define OSR_8 7 +#define OSR_9 8 +#define OSR_10 9 +#define OSR_11 10 +#define OSR_12 11 +#define OSR_13 12 +#define OSR_14 13 +#define OSR_15 14 +#define OSR_16 15 +#define OSR_17 16 +#define OSR_18 17 +#define OSR_19 18 +#define OSR_20 19 +#define OSR_21 20 +#define OSR_22 21 +#define OSR_23 22 +#define OSR_24 23 +#define OSR_25 24 +#define OSR_26 25 +#define OSR_27 26 +#define OSR_28 27 +#define OSR_29 28 +#define OSR_30 29 +#define OSR_31 30 +#define OSR_32 31 +#define OSR_33 32 +#define OSR_34 33 +#define OSR_35 34 +#define OSR_36 35 +#define OSR_37 36 +#define OSR_38 37 +#define OSR_39 38 +#define OSR_40 39 +#define OSR_41 40 +#define OSR_42 41 +#define OSR_43 42 +#define OSR_44 43 +#define OSR_45 44 +#define OSR_46 45 +#define OSR_47 46 +#define OSR_48 47 +#define OSR_49 48 +#define OSR_50 49 +#define OSR_51 50 +#define OSR_52 51 +#define OSR_53 52 +#define OSR_54 53 +#define OSR_55 54 +#define OSR_56 55 +#define OSR_57 56 +#define OSR_58 57 +#define OSR_59 58 +#define OSR_60 59 +#define OSR_61 60 +#define OSR_62 61 +#define OSR_63 62 +#define OSR_64 63 +#define OSR_65 64 +#define OSR_66 65 +#define OSR_67 66 +#define OSR_68 67 +#define OSR_69 68 +#define OSR_70 69 +#define OSR_71 70 +#define OSR_72 71 +#define OSR_73 72 +#define OSR_74 73 +#define OSR_75 74 +#define OSR_76 75 +#define OSR_77 76 +#define OSR_78 77 +#define OSR_79 78 +#define OSR_80 79 +#define OSR_81 80 +#define OSR_82 81 +#define OSR_83 82 +#define OSR_84 83 +#define OSR_85 84 +#define OSR_86 85 +#define OSR_87 86 +#define OSR_88 87 +#define OSR_89 88 +#define OSR_90 89 +#define OSR_91 90 +#define OSR_92 91 +#define OSR_93 92 +#define OSR_94 93 +#define OSR_95 94 +#define OSR_96 95 +#define OSR_97 96 +#define OSR_98 97 +#define OSR_99 98 +#define OSR_100 99 +#define OSR_101 100 +#define OSR_102 101 +#define OSR_103 102 +#define OSR_104 103 +#define OSR_105 104 +#define OSR_106 105 +#define OSR_107 106 +#define OSR_108 107 +#define OSR_109 108 +#define OSR_110 109 +#define OSR_111 110 +#define OSR_112 111 +#define OSR_113 112 +#define OSR_114 113 +#define OSR_115 114 +#define OSR_116 115 +#define OSR_117 116 +#define OSR_118 117 +#define OSR_119 118 +#define OSR_120 119 +#define OSR_121 120 +#define OSR_122 121 +#define OSR_123 122 +#define OSR_124 123 +#define OSR_125 124 +#define OSR_126 125 +#define OSR_127 126 +#define OSR_128 127 +#define OSR_129 128 +#define OSR_130 129 +#define OSR_131 130 +#define OSR_132 131 +#define OSR_133 132 +#define OSR_134 133 +#define OSR_135 134 +#define OSR_136 135 +#define OSR_137 136 +#define OSR_138 137 +#define OSR_139 138 +#define OSR_140 139 +#define OSR_141 140 +#define OSR_142 141 +#define OSR_143 142 +#define OSR_144 143 +#define OSR_145 144 +#define OSR_146 145 +#define OSR_147 146 +#define OSR_148 147 +#define OSR_149 148 +#define OSR_150 149 +#define OSR_151 150 +#define OSR_152 151 +#define OSR_153 152 +#define OSR_154 153 +#define OSR_155 154 +#define OSR_156 155 +#define OSR_157 156 +#define OSR_158 157 +#define OSR_159 158 +#define OSR_160 159 +#define OSR_161 160 +#define OSR_162 161 +#define OSR_163 162 +#define OSR_164 163 +#define OSR_165 164 +#define OSR_166 165 +#define OSR_167 166 +#define OSR_168 167 +#define OSR_169 168 +#define OSR_170 169 +#define OSR_171 170 +#define OSR_172 171 +#define OSR_173 172 +#define OSR_174 173 +#define OSR_175 174 +#define OSR_176 175 +#define OSR_177 176 +#define OSR_178 177 +#define OSR_179 178 +#define OSR_180 179 +#define OSR_181 180 +#define OSR_182 181 +#define OSR_183 182 +#define OSR_184 183 +#define OSR_185 184 +#define OSR_186 185 +#define OSR_187 186 +#define OSR_188 187 +#define OSR_189 188 +#define OSR_190 189 +#define OSR_191 190 +#define OSR_192 191 +#define OSR_193 192 +#define OSR_194 193 +#define OSR_195 194 +#define OSR_196 195 +#define OSR_197 196 +#define OSR_198 197 +#define OSR_199 198 +#define OSR_200 199 +#define OSR_201 200 +#define OSR_202 201 +#define OSR_203 202 +#define OSR_204 203 +#define OSR_205 204 +#define OSR_206 205 +#define OSR_207 206 +#define OSR_208 207 +#define OSR_209 208 +#define OSR_210 209 +#define OSR_211 210 +#define OSR_212 211 +#define OSR_213 212 +#define OSR_214 213 +#define OSR_215 214 +#define OSR_216 215 +#define OSR_217 216 +#define OSR_218 217 +#define OSR_219 218 +#define OSR_220 219 +#define OSR_221 220 +#define OSR_222 221 +#define OSR_223 222 +#define OSR_224 223 +#define OSR_225 224 +#define OSR_226 225 +#define OSR_227 226 +#define OSR_228 227 +#define OSR_229 228 +#define OSR_230 229 +#define OSR_231 230 +#define OSR_232 231 +#define OSR_233 232 +#define OSR_234 233 +#define OSR_235 234 +#define OSR_236 235 +#define OSR_237 236 +#define OSR_238 237 +#define OSR_239 238 +#define OSR_240 239 +#define OSR_241 240 +#define OSR_242 241 +#define OSR_243 242 +#define OSR_244 243 +#define OSR_245 244 +#define OSR_246 245 +#define OSR_247 246 +#define OSR_248 247 +#define OSR_249 248 +#define OSR_250 249 +#define OSR_251 250 +#define OSR_252 251 +#define OSR_253 252 +#define OSR_254 253 +#define OSR_255 254 +#define OSR_256 255 + +// +// The following are defines for different OSR values +// +#define SHIFT_0_BITS 0 +#define SHIFT_1_BITS 1 +#define SHIFT_2_BITS 2 +#define SHIFT_3_BITS 3 +#define SHIFT_4_BITS 4 +#define SHIFT_5_BITS 5 +#define SHIFT_6_BITS 6 +#define SHIFT_7_BITS 7 +#define SHIFT_8_BITS 8 +#define SHIFT_9_BITS 9 +#define SHIFT_10_BITS 10 +#define SHIFT_11_BITS 11 +#define SHIFT_12_BITS 12 +#define SHIFT_13_BITS 13 +#define SHIFT_14_BITS 14 +#define SHIFT_15_BITS 15 +#define SHIFT_16_BITS 16 +#define SHIFT_17_BITS 17 +#define SHIFT_18_BITS 18 +#define SHIFT_19_BITS 19 +#define SHIFT_20_BITS 20 +#define SHIFT_21_BITS 21 +#define SHIFT_22_BITS 22 +#define SHIFT_23_BITS 23 +#define SHIFT_24_BITS 24 +#define SHIFT_25_BITS 25 +#define SHIFT_26_BITS 26 +#define SHIFT_27_BITS 27 +#define SHIFT_28_BITS 28 +#define SHIFT_29_BITS 29 +#define SHIFT_30_BITS 30 +#define SHIFT_31_BITS 31 + +// +// Function prototypes +// +extern void Sdfm_configureInputCtrl(Uint16 SDFM_number, + Uint16 Filter_number, Uint16 mode); +extern void Sdfm_configureComparator(Uint16 SDFM_number, + Uint16 Filter_number, Uint16 Filter_type, + Uint16 OSR, Uint16 HLT, Uint16 LLT); +extern void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 Filter_switch, Uint16 filterType, + Uint16 OSR, Uint16 DR_switch, + Uint16 shift_bits); +extern void Sdfm_enableMFE(Uint16 SDFM_number); +extern void Sdfm_disableMFE(Uint16 SDFM_number); +extern void Sdfm_configureInterrupt(Uint16 SDFM_number, Uint16 Filter_number, + Uint16 IEH_Switch, Uint16 IEL_Switch, + Uint16 MFIE_Switch, Uint16 AE_Switch); +extern void Sdfm_enableMIE(Uint16 SDFM_number); +extern void Sdfm_disableMIE(Uint16 SDFM_number); +extern void Sdfm_configureExternalreset(Uint16 SDFM_number, + Uint16 filter1_Config_ext_reset, + Uint16 filter2_Config_ext_reset, + Uint16 filter3_Config_ext_reset, + Uint16 filter4_Config_ext_reset); +extern Uint32 Sdfm_readFlagRegister(Uint16 SDFM_number); +extern void Sdfm_clearFlagRegister(Uint16 sdfmNumber, + Uint32 sdfmReadFlagRegister); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_SDFM_DRIVERS_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F2837xD_struct.h b/bsp/tms320f28379d/libraries/common/include/F2837xD_struct.h new file mode 100644 index 00000000000..bd307dd782b --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F2837xD_struct.h @@ -0,0 +1,82 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm_strut.h +// +// TITLE: contains structures used for the SDFM driver. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SDFM_STRUCT_H +#define F2837xD_SDFM_STRUCT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_CPUTIMER 4 +#define MAX_ECAP 7 +#define MAX_EPWM 13 +#define MAX_EQEP 4 +#define MAX_I2C 2 +#define MAX_MCBSP 2 +#define MAX_SCI 2 +#define MAX_SPI 4 +#define MAX_ADC 5 +#define MAX_SDFM 3 +#define MAX_TRIPSEL 15 + +extern volatile Uint16 *TRIP_SEL[MAX_TRIPSEL]; +extern volatile struct ADC_REGS *ADC[MAX_ADC]; +extern volatile struct CPUTIMER_REGS *CPUTIMER[MAX_CPUTIMER]; +extern volatile struct ECAP_REGS *ECAP[MAX_ECAP]; +extern volatile struct EPWM_REGS *EPWM[MAX_EPWM]; +extern volatile struct EQEP_REGS *EQEP[MAX_EQEP]; +extern volatile struct I2C_REGS *I2C[MAX_I2C]; +extern volatile struct McBSP_REGS *MCBSP[MAX_MCBSP]; +extern volatile struct SCI_REGS *SCI[MAX_SCI]; +extern volatile struct SPI_REGS *SPI[MAX_SPI]; +extern volatile struct SDFM_REGS *SDFM[MAX_SDFM]; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_SDFM_STRUCT_H + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/F28x_Project.h b/bsp/tms320f28379d/libraries/common/include/F28x_Project.h new file mode 100644 index 00000000000..ffdaa6e98c4 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/F28x_Project.h @@ -0,0 +1,58 @@ +//########################################################################### +// +// FILE: F28x_Project.h +// +// TITLE: F28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F28X_PROJECT_H +#define F28X_PROJECT_H + +// +// Included Files +// +#include "F2837xD_Cla_typedefs.h" // F2837xD CLA Type definitions +#include "F2837xD_device.h" // F2837xD Headerfile Include File +#include "F2837xD_Examples.h" // F2837xD Examples Include File + + +#endif // end of F28X_PROJECT_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/device.h b/bsp/tms320f28379d/libraries/common/include/device.h new file mode 100644 index 00000000000..9a8e0ad33e2 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/device.h @@ -0,0 +1,199 @@ +//############################################################################# +// +// FILE: device.h +// +// TITLE: Device setup for examples. +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "driverlib.h" + +#if (!defined(CPU1) && !defined(CPU2)) +#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \ +the offsets in your header files will be inaccurate." +#endif + +#if (defined(CPU1) && defined(CPU2)) +#error "You have defined both CPU1 and CPU2 in your project properties. Only \ +a single CPU should be defined." +#endif + +//***************************************************************************** +// +// Defines for pin numbers and other GPIO configuration +// +//***************************************************************************** +// +// LEDs +// +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 + +// +// SCI for USB-to-UART adapter on FTDI chip +// +#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX + +// +// CANA +// +#define DEVICE_GPIO_PIN_CANTXA 31U // GPIO number for CANTXA +#define DEVICE_GPIO_PIN_CANRXA 30U // GPIO number for CANRXA + +// +// CAN External Loopback +// +#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX + +//***************************************************************************** +// +// Defines related to clock configuration +// +//***************************************************************************** +// +// Launchpad Configuration +// +#ifdef _LAUNCHXL_F28379D + +// +// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 10000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2) + +// +// ControlCARD Configuration +// +#else + +// +// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 20000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2) + +#endif + +// +// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default +// low speed peripheral clock divider of 4. Update the code below if a +// different LSPCLK divider is used! +// +#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) + +//***************************************************************************** +// +// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro +// will convert the desired delay in microseconds to the count value expected +// by the function. \b x is the number of microseconds to delay. +// +//***************************************************************************** +#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ + (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) + +//***************************************************************************** +// +// Defines, Globals, and Header Includes related to Flash Support +// +//***************************************************************************** +#ifdef _FLASH +#include + +extern uint16_t RamfuncsLoadStart; +extern uint16_t RamfuncsLoadEnd; +extern uint16_t RamfuncsLoadSize; +extern uint16_t RamfuncsRunStart; +extern uint16_t RamfuncsRunEnd; +extern uint16_t RamfuncsRunSize; + +#define DEVICE_FLASH_WAITSTATES 3 + +#endif + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void Device_init(void); +extern void Device_enableAllPeripherals(void); +extern void Device_initGPIO(void); +extern void Device_enableUnbondedGPIOPullupsFor176Pin(void); +extern void Device_enableUnbondedGPIOPullupsFor100Pin(void); +extern void Device_enableUnbondedGPIOPullups(void); +extern void __error__(char *filename, uint32_t line); + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/driverlib.h b/bsp/tms320f28379d/libraries/common/include/driverlib.h new file mode 100644 index 00000000000..0dd941033fa --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/driverlib.h @@ -0,0 +1,82 @@ +//############################################################################# +// +// FILE: driverlib.h +// +// TITLE: C28x Driverlib Header File +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# +#ifndef DRIVERLIB_H +#define DRIVERLIB_H + +#include "inc/hw_memmap.h" + +#include "adc.h" +#include "asysctl.h" +#include "can.h" +#include "cla.h" +#include "cmpss.h" +#include "cpu.h" +#include "cputimer.h" +#include "dac.h" +#include "dcsm.h" +#include "debug.h" +#include "dma.h" +#include "ecap.h" +#include "emif.h" +#include "epwm.h" +#include "eqep.h" +#include "flash.h" +#include "gpio.h" +#include "hrpwm.h" +#include "i2c.h" +#include "interrupt.h" +#include "mcbsp.h" +#include "memcfg.h" +#include "pin_map.h" +#include "sci.h" +#include "sdfm.h" +#include "spi.h" +#include "sysctl.h" +#include "upp.h" +#include "version.h" +#include "xbar.h" + +#endif // end of DRIVERLIB_H definition + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/include/usb.h b/bsp/tms320f28379d/libraries/common/include/usb.h new file mode 100644 index 00000000000..1eb1f8396e2 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/usb.h @@ -0,0 +1,561 @@ +//########################################################################### +// +// FILE: usb.h +// +// TITLE: Prototypes for the USB Interface Driver. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + + +#ifndef __DRIVERLIB_USB_H__ +#define __DRIVERLIB_USB_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are defines for the g_usUSBFlags variable +// +//***************************************************************************** +#define USB_VBUS_VALID 0x0001 +#define USB_ID_HOST 0x0002 +#define USB_ID_DEVICE 0x0000 +#define USB_PFLT_ACTIVE 0x0004 + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ui32Flags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled +#define USB_INTCTRL_RESET 0x00000004 // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002 // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0xFFFF0000 // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x0000FFFF // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous + // transfer +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +//***************************************************************************** +// +// The following are special values that can be passed to +// USBHostEndpointConfig() as the ui32NAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define USB_EP_8 0x00000080 // Endpoint 8 +#define USB_EP_9 0x00000090 // Endpoint 9 +#define USB_EP_10 0x000000A0 // Endpoint 10 +#define USB_EP_11 0x000000B0 // Endpoint 11 +#define USB_EP_12 0x000000C0 // Endpoint 12 +#define USB_EP_13 0x000000D0 // Endpoint 13 +#define USB_EP_14 0x000000E0 // Endpoint 14 +#define USB_EP_15 0x000000F0 // Endpoint 15 +#define NUM_USB_EP 16 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) (((uint32_t)(x) << 4) & 0xFF) +#define USBEPToIndex(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO +#define USB_FIFO_SZ_4096 0x00000009 // 4096 byte FIFO +#define USB_FIFO_SZ_8_DB 0x00000010 // 8 byte double buffered FIFO + // (occupying 16 bytes) +#define USB_FIFO_SZ_16_DB 0x00000011 // 16 byte double buffered FIFO + // (occupying 32 bytes) +#define USB_FIFO_SZ_32_DB 0x00000012 // 32 byte double buffered FIFO + // (occupying 64 bytes) +#define USB_FIFO_SZ_64_DB 0x00000013 // 64 byte double buffered FIFO + // (occupying 128 bytes) +#define USB_FIFO_SZ_128_DB 0x00000014 // 128 byte double buffered FIFO + // (occupying 256 bytes) +#define USB_FIFO_SZ_256_DB 0x00000015 // 256 byte double buffered FIFO + // (occupying 512 bytes) +#define USB_FIFO_SZ_512_DB 0x00000016 // 512 byte double buffered FIFO + // (occupying 1024 bytes) +#define USB_FIFO_SZ_1024_DB 0x00000017 // 1024 byte double buffered FIFO + // (occupying 2048 bytes) +#define USB_FIFO_SZ_2048_DB 0x00000018 // 2048 byte double buffered FIFO + // (occupying 4096 bytes) + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USB_FIFO_SIZE_DB_FLAG 0x00000010 +#define USBFIFOSizeToBytes(x) ((uint32_t)8 << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of + // the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of + // the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t USBDevAddrGet(uint32_t ui32Base); +extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address); +extern void USBDevConnect(uint32_t ui32Base); +extern void USBDevDisconnect(uint32_t ui32Base); +extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config); +extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size); +extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void USBEndpointDataToggleClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint); +extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags); +extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBFrameNumberGet(uint32_t ui32Base); +extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void USBHostEndpointDataAck(uint32_t ui32Base, + uint32_t ui32Endpoint); +extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags); +extern void USBHostEndpointStatusClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostPwrDisable(uint32_t ui32Base); +extern void USBHostPwrEnable(uint32_t ui32Base); +extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags); +extern void USBHostPwrFaultDisable(uint32_t ui32Base); +extern void USBHostPwrFaultEnable(uint32_t ui32Base); +extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestStatus(uint32_t ui32Base); +extern void USBHostReset(uint32_t ui32Base, bool bStart); +extern void USBHostResume(uint32_t ui32Base, bool bStart); +extern uint32_t USBHostSpeedGet(uint32_t ui32Base); +extern void USBHostSuspend(uint32_t ui32Base); +extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatus(uint32_t ui32Base, uint32_t *ui32IntStatusEP); +extern uint32_t USBIntStatusControl(uint32_t ui32Base); +extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base); +extern void USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void USBIntUnregister(uint32_t ui32Base); +extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart); +extern uint32_t USBModeGet(uint32_t ui32Base); +extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern void USBHostMode(uint32_t ui32Base); +extern void USBDevMode(uint32_t ui32Base); +extern void USBOTGMode(uint32_t ui32Base); +extern void USBPHYPowerOff(uint32_t ui32Base); +extern void USBPHYPowerOn(uint32_t ui32Base); +extern uint32_t USBNumEndpointsGet(uint32_t ui32Base); + +//***************************************************************************** +// The following are values that can be passed to USBIntEnable() and +// USBIntDisable() as the ulIntFlags parameter, and are returned from +// USBIntStatus(). +//***************************************************************************** +#define USB_INT_ALL 0xFF030E0F // All Interrupt sources +#define USB_INT_STATUS 0xFF000000 // Status Interrupts +#define USB_INT_VBUS_ERR 0x80000000 // VBUS Error +#define USB_INT_SESSION_START 0x40000000 // Session Start Detected +#define USB_INT_SESSION_END 0x20000000 // Session End Detected +#define USB_INT_DISCONNECT 0x20000000 // Disconnect Detected +#define USB_INT_CONNECT 0x10000000 // Device Connect Detected +#define USB_INT_SOF 0x08000000 // Start of Frame Detected +#define USB_INT_BABBLE 0x04000000 // Babble signaled +#define USB_INT_RESET 0x04000000 // Reset signaled +#define USB_INT_RESUME 0x02000000 // Resume detected +#define USB_INT_SUSPEND 0x01000000 // Suspend detected +#define USB_INT_MODE_DETECT 0x00020000 // Mode value valid +#define USB_INT_POWER_FAULT 0x00010000 // Power Fault detected +#define USB_INT_HOST_IN 0x00000E00 // Host IN Interrupts +#define USB_INT_DEV_OUT 0x00000E00 // Device OUT Interrupts +#define USB_INT_HOST_IN_EP3 0x00000800 // Endpoint 3 Host IN Interrupt +#define USB_INT_HOST_IN_EP2 0x00000400 // Endpoint 2 Host IN Interrupt +#define USB_INT_HOST_IN_EP1 0x00000200 // Endpoint 1 Host IN Interrupt +#define USB_INT_DEV_OUT_EP3 0x00000800 // Endpoint 3 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP2 0x00000400 // Endpoint 2 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP1 0x00000200 // Endpoint 1 Device OUT Interrupt +#define USB_INT_HOST_OUT 0x0000000E // Host OUT Interrupts +#define USB_INT_DEV_IN 0x0000000E // Device IN Interrupts +#define USB_INT_HOST_OUT_EP3 0x00000008 // Endpoint 3 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP2 0x00000004 // Endpoint 2 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP1 0x00000002 // Endpoint 1 HOST_OUT Interrupt +#define USB_INT_DEV_IN_EP3 0x00000008 // Endpoint 3 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP2 0x00000004 // Endpoint 2 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP1 0x00000002 // Endpoint 1 DEV_IN Interrupt +#define USB_INT_EP0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_USB_H__ diff --git a/bsp/tms320f28379d/libraries/common/include/usb_hal.h b/bsp/tms320f28379d/libraries/common/include/usb_hal.h new file mode 100644 index 00000000000..d89577ebc38 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/include/usb_hal.h @@ -0,0 +1,82 @@ +//########################################################################### +// FILE: usb_hal.h +// TITLE: Compatability layer for ported software. +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __USB_HAL_H__ +#define __USB_HAL_H__ + +//***************************************************************************** +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + + + +//***************************************************************************** +//! \addtogroup c2000_specific +//! @{ +//***************************************************************************** + +extern void USBGPIOEnable(void); +extern void USBGPIODisable(void); +extern void USBDelay(uint32_t ui32Delay); + +extern void f28x_USB0DeviceIntHandler(void); +extern void f28x_USB0HostIntHandler(void); +extern void f28x_USB0DualModeIntHandler(void); +extern void f28x_USB0OTGModeIntHandler(void); + + +//***************************************************************************** +// Mark the end of the C bindings section for C++ compilers. +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + +#endif // __F28X_USB_HAL_H__ + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Adc.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Adc.c new file mode 100644 index 00000000000..3959c44698a --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Adc.c @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: F2837xD_Adc.c +// +// TITLE: F2837xD Adc Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// AdcSetMode - Set the resolution and signalmode for a given ADC. This will +// ensure that the correct trim is loaded. +// +// NOTE!!! There is no EALLOW/EDIS in this function! You need to make sure you +// perform the EALLOW before calling this function or else the ADC registers +// will not be configured. +// +void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode) +{ + Uint16 adcOffsetTrimOTPIndex; //index into OTP table of ADC offset trims + Uint16 adcOffsetTrim; //temporary ADC offset trim + + // + //re-populate INL trim + // + CalAdcINL(adc); + + if(0xFFFF != *((Uint16*)GetAdcOffsetTrimOTP)) + { + // + //offset trim function is programmed into OTP, so call it + // + + // + //calculate the index into OTP table of offset trims and call + //function to return the correct offset trim + // +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + adcOffsetTrimOTPIndex = 4*adc + 1*signalmode; + } + else + { + adcOffsetTrimOTPIndex = 4*adc + 1*signalmode + 2; + } + + adcOffsetTrim = (*GetAdcOffsetTrimOTP)(adcOffsetTrimOTPIndex); + } + else + { + // + //offset trim function is not populated, so set offset trim to 0 + // + adcOffsetTrim = 0; + } + + // + // Apply the resolution and signalmode to the specified ADC. + // Also apply the offset trim and, if needed, linearity trim correction. + // + switch(adc) + { + case ADC_ADCA: + { + AdcaRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdcaRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcaRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + //12-bit linearity trim workaround + // + AdcaRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcaRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCB: + { + AdcbRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdcbRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcbRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + //12-bit linearity trim workaround + // + AdcbRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcbRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCC: + { + AdccRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdccRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdccRegs.ADCCTL2.bit.RESOLUTION = 0; + // + //12-bit linearity trim workaround + // + AdccRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdccRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCD: + { + AdcdRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdcdRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcdRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + //12-bit linearity trim workaround + // + AdcdRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcdRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + } +} + +// +// CalAdcINL - Loads INL trim values from OTP into the trim registers of the +// specified ADC. Use only as part of AdcSetMode function, since +// linearity trim correction is needed for some modes. +// +void CalAdcINL(Uint16 adc) +{ + switch(adc) + { + case ADC_ADCA: + if(0xFFFF != *((Uint16*)CalAdcaINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdcaINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + case ADC_ADCB: + if(0xFFFF != *((Uint16*)CalAdcbINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdcbINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + case ADC_ADCC: + if(0xFFFF != *((Uint16*)CalAdccINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdccINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + case ADC_ADCD: + if(0xFFFF != *((Uint16*)CalAdcdINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdcdINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + } +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_CodeStartBranch.asm b/bsp/tms320f28379d/libraries/common/source/F2837xD_CodeStartBranch.asm new file mode 100644 index 00000000000..cd08bf30c06 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_CodeStartBranch.asm @@ -0,0 +1,111 @@ +;//########################################################################### +;// +;// FILE: F2837xD_CodeStartBranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// In addition, the example F2837xD projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The code_start code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// $TI Release: F2837xD Support Library v3.05.00.00 $ +;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +;// $Copyright: +;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + +*********************************************************************** + +WD_DISABLE .set 0 ;set to 1 to disable WD, else set to 0 + + .ref _c_int00 + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB _c_int00 ;Branch to start of boot._asm in RTS library + .endif + +;end codestart section + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .text +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot._asm in RTS library + + .endif + +;end wd_disable + + .end + +;// +;// End of file. +;// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_CpuTimers.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_CpuTimers.c new file mode 100644 index 00000000000..1a0877ea6df --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_CpuTimers.c @@ -0,0 +1,181 @@ +//########################################################################### +// +// FILE: F2837xD_CpuTimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Globals +// +struct CPUTIMER_VARS CpuTimer0; +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +// +// InitCpuTimers - This function initializes all three CPU timers to a known +// state. +// +void InitCpuTimers(void) +{ + // + // CPU Timer 0 + // Initialize address pointers to respective timer registers: + // + CpuTimer0.RegsAddr = &CpuTimer0Regs; + + // + // Initialize timer period to maximum: + // + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + // + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + + // + // Make sure timer is stopped: + // + CpuTimer0Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value: + // + CpuTimer0Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters: + // + CpuTimer0.InterruptCount = 0; + + // + // Initialize address pointers to respective timer registers: + // + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + + // + // Initialize timer period to maximum: + // + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + // + CpuTimer1Regs.TPR.all = 0; + CpuTimer1Regs.TPRH.all = 0; + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + + // + // Make sure timers are stopped: + // + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value: + // + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters: + // + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; +} + +// +// ConfigCpuTimer - This function initializes the selected timer to the period +// specified by the "Freq" and "Period" parameters. The "Freq" +// is entered as "MHz" and the period in "uSeconds". The timer +// is held in the stopped state after configuration. +// +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // + // Initialize timer period: + // + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + + // + // Counter decrements PRD+1 times each period + // + Timer->RegsAddr->PRD.all = temp - 1; + + // + // Set pre-scale counter to divide by 1 (SYSCLKOUT): + // + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // + // Initialize timer control register: + // + Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart + // Timer + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 0; + Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled + Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer + // Interrupt + + // + // Reset interrupt counter: + // + Timer->InterruptCount = 0; +} + + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_DBGIER.asm b/bsp/tms320f28379d/libraries/common/source/F2837xD_DBGIER.asm new file mode 100644 index 00000000000..951fe6a28a9 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_DBGIER.asm @@ -0,0 +1,60 @@ +;//########################################################################### +;// +;// FILE: F2837xD_DBGIER.asm +;// +;// TITLE: Set the DBGIER register +;// +;// DESCRIPTION: +;// +;// Function to set the DBGIER register (for realtime emulation). +;// Function Prototype: void SetDBGIER(Uint16) +;// Usage: SetDBGIER(value); +;// Input Parameters: Uint16 value = value to put in DBGIER register. +;// Return Value: none +;// +;//########################################################################### +;// $TI Release: F2837xD Support Library v3.05.00.00 $ +;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +;// $Copyright: +;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + .global _SetDBGIER + .text + +_SetDBGIER: + MOV *SP++,AL + POP DBGIER + LRETR + +;// +;// End of file +;// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_DefaultISR.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_DefaultISR.c new file mode 100644 index 00000000000..bd589343b6e --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_DefaultISR.c @@ -0,0 +1,3138 @@ +//########################################################################### +// +// FILE: F2837xD_DefaultISR.c +// +// TITLE: F2837xD Device Default Interrupt Service Routines +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// CPU Timer 1 Interrupt +// +interrupt void TIMER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// CPU Timer 2 Interrupt +// +interrupt void TIMER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Datalogging Interrupt +// +interrupt void DATALOG_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// RTOS Interrupt +// +interrupt void RTOS_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Emulation Interrupt +// +interrupt void EMU_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Non-Maskable Interrupt +// +interrupt void NMI_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Illegal Operation Trap +// +interrupt void ILLEGAL_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 1 +// +interrupt void USER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 2 +// +interrupt void USER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 3 +// +interrupt void USER3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 4 +// +interrupt void USER4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 5 +// +interrupt void USER5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 6 +// +interrupt void USER6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 7 +// +interrupt void USER7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 8 +// +interrupt void USER8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 9 +// +interrupt void USER9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 10 +// +interrupt void USER10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 11 +// +interrupt void USER11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 12 +// +interrupt void USER12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.1 - ADCA Interrupt 1 +// +interrupt void ADCA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.2 - ADCB Interrupt 1 +// +interrupt void ADCB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.3 - ADCC Interrupt 1 +// +interrupt void ADCC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.4 - XINT1 Interrupt +// +interrupt void XINT1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.5 - XINT2 Interrupt +// +interrupt void XINT2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.6 - ADCD Interrupt 1 +// +interrupt void ADCD1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.7 - Timer 0 Interrupt +// +interrupt void TIMER0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.8 - Standby and Halt Wakeup Interrupt +// +interrupt void WAKE_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.1 - ePWM1 Trip Zone Interrupt +// +interrupt void EPWM1_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.2 - ePWM2 Trip Zone Interrupt +// +interrupt void EPWM2_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.3 - ePWM3 Trip Zone Interrupt +// +interrupt void EPWM3_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.4 - ePWM4 Trip Zone Interrupt +// +interrupt void EPWM4_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.5 - ePWM5 Trip Zone Interrupt +// +interrupt void EPWM5_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.6 - ePWM6 Trip Zone Interrupt +// +interrupt void EPWM6_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.7 - ePWM7 Trip Zone Interrupt +// +interrupt void EPWM7_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.8 - ePWM8 Trip Zone Interrupt +// +interrupt void EPWM8_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.1 - ePWM1 Interrupt +// +interrupt void EPWM1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.2 - ePWM2 Interrupt +// +interrupt void EPWM2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.3 - ePWM3 Interrupt +// +interrupt void EPWM3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.4 - ePWM4 Interrupt +// +interrupt void EPWM4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.5 - ePWM5 Interrupt +// +interrupt void EPWM5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.6 - ePWM6 Interrupt +// +interrupt void EPWM6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.7 - ePWM7 Interrupt +// +interrupt void EPWM7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.8 - ePWM8 Interrupt +// +interrupt void EPWM8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.1 - eCAP1 Interrupt +// +interrupt void ECAP1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.2 - eCAP2 Interrupt +// +interrupt void ECAP2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.3 - eCAP3 Interrupt +// +interrupt void ECAP3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.4 - eCAP4 Interrupt +// +interrupt void ECAP4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.5 - eCAP5 Interrupt +// +interrupt void ECAP5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.6 - eCAP6 Interrupt +// +interrupt void ECAP6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.1 - eQEP1 Interrupt +// +interrupt void EQEP1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.2 - eQEP2 Interrupt +// +interrupt void EQEP2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.3 - eQEP3 Interrupt +// +interrupt void EQEP3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.1 - SPIA Receive Interrupt +// +interrupt void SPIA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.2 - SPIA Transmit Interrupt +// +interrupt void SPIA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.3 - SPIB Receive Interrupt +// +interrupt void SPIB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.4 - SPIB Transmit Interrupt +// +interrupt void SPIB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.5 - McBSPA Receive Interrupt +// +interrupt void MCBSPA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.6 - McBSPA Transmit Interrupt +// +interrupt void MCBSPA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.7 - McBSPB Receive Interrupt +// +interrupt void MCBSPB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.8 - McBSPB Transmit Interrupt +// +interrupt void MCBSPB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.1 - DMA Channel 1 Interrupt +// +interrupt void DMA_CH1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.2 - DMA Channel 2 Interrupt +// +interrupt void DMA_CH2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.3 - DMA Channel 3 Interrupt +// +interrupt void DMA_CH3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.4 - DMA Channel 4 Interrupt +// +interrupt void DMA_CH4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.5 - DMA Channel 5 Interrupt +// +interrupt void DMA_CH5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.6 - DMA Channel 6 Interrupt +// +interrupt void DMA_CH6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.1 - I2CA Interrupt 1 +// +interrupt void I2CA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.2 - I2CA Interrupt 2 +// +interrupt void I2CA_FIFO_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.3 - I2CB Interrupt 1 +// +interrupt void I2CB_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.4 - I2CB Interrupt 2 +// +interrupt void I2CB_FIFO_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.5 - SCIC Receive Interrupt +// +interrupt void SCIC_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.6 - SCIC Transmit Interrupt +// +interrupt void SCIC_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.7 - SCID Receive Interrupt +// +interrupt void SCID_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.8 - SCID Transmit Interrupt +// +interrupt void SCID_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.1 - SCIA Receive Interrupt +// +interrupt void SCIA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.2 - SCIA Transmit Interrupt +// +interrupt void SCIA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.3 - SCIB Receive Interrupt +// +interrupt void SCIB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.4 - SCIB Transmit Interrupt +// +interrupt void SCIB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.5 - CANA Interrupt 0 +// +interrupt void CANA0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.6 - CANA Interrupt 1 +// +interrupt void CANA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.7 - CANB Interrupt 0 +// +interrupt void CANB0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.8 - CANB Interrupt 1 +// +interrupt void CANB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.1 - ADCA Event Interrupt +// +interrupt void ADCA_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.2 - ADCA Interrupt 2 +// +interrupt void ADCA2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.3 - ADCA Interrupt 3 +// +interrupt void ADCA3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.4 - ADCA Interrupt 4 +// +interrupt void ADCA4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.5 - ADCB Event Interrupt +// +interrupt void ADCB_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.6 - ADCB Interrupt 2 +// +interrupt void ADCB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.7 - ADCB Interrupt 3 +// +interrupt void ADCB3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.8 - ADCB Interrupt 4 +// +interrupt void ADCB4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.1 - CLA1 Interrupt 1 +// +interrupt void CLA1_1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.2 - CLA1 Interrupt 2 +// +interrupt void CLA1_2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.3 - CLA1 Interrupt 3 +// +interrupt void CLA1_3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.4 - CLA1 Interrupt 4 +// +interrupt void CLA1_4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.5 - CLA1 Interrupt 5 +// +interrupt void CLA1_5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.6 - CLA1 Interrupt 6 +// +interrupt void CLA1_6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.7 - CLA1 Interrupt 7 +// +interrupt void CLA1_7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.8 - CLA1 Interrupt 8 +// +interrupt void CLA1_8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.1 - XINT3 Interrupt +// +interrupt void XINT3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.2 - XINT4 Interrupt +// +interrupt void XINT4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.3 - XINT5 Interrupt +// +interrupt void XINT5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.6 - VCU Interrupt +// +interrupt void VCU_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.7 - FPU Overflow Interrupt +// +interrupt void FPU_OVERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.8 - FPU Underflow Interrupt +// +interrupt void FPU_UNDERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.13 - IPC Interrupt 0 +// +interrupt void IPC0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.14 - IPC Interrupt 1 +// +interrupt void IPC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.15 - IPC Interrupt 2 +// +interrupt void IPC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.16 - IPC Interrupt 3 +// +interrupt void IPC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.9 - ePWM9 Trip Zone Interrupt +// +interrupt void EPWM9_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.10 - ePWM10 Trip Zone Interrupt +// +interrupt void EPWM10_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.11 - ePWM11 Trip Zone Interrupt +// +interrupt void EPWM11_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.12 - ePWM12 Trip Zone Interrupt +// +interrupt void EPWM12_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.9 - ePWM9 Interrupt +// +interrupt void EPWM9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.10 - ePWM10 Interrupt +// +interrupt void EPWM10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.11 - ePWM11 Interrupt +// +interrupt void EPWM11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.12 - ePWM12 Interrupt +// +interrupt void EPWM12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.9 - SD1 Interrupt +// +interrupt void SD1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.10 - SD2 Interrupt +// +interrupt void SD2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.9 - SPIC Receive Interrupt +// +interrupt void SPIC_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.10 - SPIC Transmit Interrupt +// +interrupt void SPIC_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.15 - uPPA Interrupt +// +interrupt void UPPA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.15 - USBA Interrupt +// +interrupt void USBA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.9 - ADCC Event Interrupt +// +interrupt void ADCC_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.10 - ADCC Interrupt 2 +// +interrupt void ADCC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.11 - ADCC Interrupt 3 +// +interrupt void ADCC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.12 - ADCC Interrupt 4 +// +interrupt void ADCC4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.13 - ADCD Event Interrupt +// +interrupt void ADCD_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.14 - ADCD Interrupt 2 +// +interrupt void ADCD2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.15 - ADCD Interrupt 3 +// +interrupt void ADCD3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.16 - ADCD Interrupt 4 +// +interrupt void ADCD4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.9 - EMIF Error Interrupt +// +interrupt void EMIF_ERROR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.10 - RAM Correctable Error Interrupt +// +interrupt void RAM_CORRECTABLE_ERROR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.11 - Flash Correctable Error Interrupt +// +interrupt void FLASH_CORRECTABLE_ERROR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.12 - RAM Access Violation Interrupt +// +interrupt void RAM_ACCESS_VIOLATION_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.13 - System PLL Slip Interrupt +// +interrupt void SYS_PLL_SLIP_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.14 - Auxiliary PLL Slip Interrupt +// +interrupt void AUX_PLL_SLIP_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.15 - CLA Overflow Interrupt +// +interrupt void CLA_OVERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.16 - CLA Underflow Interrupt +// +interrupt void CLA_UNDERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Catch-all Default ISRs: +// + +// +// PIE_RESERVED_ISR - Reserved ISR +// +interrupt void PIE_RESERVED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// EMPTY_ISR - Only does a return +// +interrupt void EMPTY_ISR(void) +{ + +} + +// +// NOTUSED_ISR - Unused ISR +// +interrupt void NOTUSED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Dma.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Dma.c new file mode 100644 index 00000000000..ca5593c8516 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Dma.c @@ -0,0 +1,1100 @@ +//########################################################################### +// +// FILE: F2837xD_DMA.c +// +// TITLE: F2837xD Device DMA Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// DMAInitialize - This function initializes the DMA to a known state. +// +void DMAInitialize(void) +{ + EALLOW; + + // + // Perform a hard reset on DMA + // + DmaRegs.DMACTRL.bit.HARDRESET = 1; + __asm (" nop"); // one NOP required after HARDRESET + + // + // Allow DMA to run free on emulation suspend + // + DmaRegs.DEBUGCTRL.bit.FREE = 1; + + EDIS; +} + +// +// DMACH1AddrConfig - DMA Channel 1 Address Configuration +// +void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to + // beginning of + // source buffer + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to + // beginning of + // destination buffer + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH1BurstConfig - DMA Channel 1 Burst size configuration +// +void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) + // x-ferred in a burst. + DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between + // each word x-ferred. + + EDIS; +} + +// +// DMACH1TransferConfig - DMA Channel 1 Transfer size configuration +// +void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored + // when WRAP occurs. + DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored + // when WRAP occurs. + + EDIS; +} + +// +// DMACH1WrapConfig - DMA Channel 1 Wrap size configuration +// +void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH1ModeConfig - DMA Channel 1 Mode configuration +// +void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = persel; + DmaRegs.CH1.MODE.bit.PERINTSEL = 1; + DmaRegs.CH1.MODE.bit.PERINTE = perinte; + DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH1.MODE.bit.DATASIZE = datasize; + DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH1.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: interrupt and sync error flags + // + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH1 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; + + EDIS; +} + +// +// StartDMACH1 - This function starts DMA Channel 1. +// +void StartDMACH1(void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH2AddrConfig - DMA Channel 2 Address Configuration +// +void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to + // beginning of + // source buffer. + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH2BurstConfig - DMA Channel 2 Burst size configuration +// +void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH2TransferConfig - DMA Channel 2 Transfer size Configuration +// +void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH2WrapConfig - DMA Channel 2 Wrap size configuration +// +void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH2ModeConfig - DMA Channel 2 Mode configuration +// +void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = persel; + DmaRegs.CH2.MODE.bit.PERINTSEL = 2; + DmaRegs.CH2.MODE.bit.PERINTE = perinte; + DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH2.MODE.bit.DATASIZE = datasize; + DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH2.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH2 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; + + EDIS; +} + +// +// StartDMACH2 - This function starts DMA Channel 2. +// +void StartDMACH2(void) +{ + EALLOW; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH3AddrConfig - DMA Channel 3 Address configuration +// +void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH3BurstConfig - DMA Channel 3 burst size configuration +// +void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH3TransferConfig - DMA channel 3 transfer size configuration +// +void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH3WrapConfig - DMA Channel 3 wrap size configuration +// +void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N + // bursts. + DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH3ModeConfig - DMA Channel 3 mode configuration +// +void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH3 = persel; + DmaRegs.CH3.MODE.bit.PERINTSEL = 3; + DmaRegs.CH3.MODE.bit.PERINTE = perinte; + DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH3.MODE.bit.DATASIZE = datasize; + DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH3.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: interrupt flags and sync error flags + // + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH3 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx3 = 1; + + EDIS; +} + +// +// StartDMACH3 - This function starts DMA Channel 3. +// +void StartDMACH3(void) +{ + EALLOW; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH4AddrConfig - DMA Channel 4 address configuration +// +void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH4BurstConfig - DMA Channel 4 burst size configuration +// +void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH4TransferConfig - DMA channel 4 transfer size configuration +// +void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH4WrapConfig - DMA channel 4 wrap size configuration +// +void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH4ModeConfig - DMA Channel 4 mode configuration +// +void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH4 = persel; + DmaRegs.CH4.MODE.bit.PERINTSEL = 4; + DmaRegs.CH4.MODE.bit.PERINTE = perinte; + DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH4.MODE.bit.DATASIZE = datasize; + DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH4.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH4 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx4 = 1; + + EDIS; +} + +// +// StartDMACH4 - This function starts DMA Channel 4. +// +void StartDMACH4(void) +{ + EALLOW; + DmaRegs.CH4.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH5AddrConfig - DMA channel 5 address configuration +// +void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH5BurstConfig - DMA Channel 5 burst size configuration +// +void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH5TransferConfig - DMA channel 5 transfer size configuration +// +void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH5WrapConfig - DMA Channel 5 wrap size configuration +// +void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH5ModeConfig - DMA Channel 5 mode configuration +// +void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = persel; + DmaRegs.CH5.MODE.bit.PERINTSEL = 5; + DmaRegs.CH5.MODE.bit.PERINTE = perinte; + DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH5.MODE.bit.DATASIZE = datasize; + DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH5.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH5 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx5 = 1; + + EDIS; +} + +// +// StartDMACH5 - This function starts DMA Channel 5. +// +void StartDMACH5(void) +{ + EALLOW; + DmaRegs.CH5.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH6AddrConfig - DMA Channel 6 address configuration +// +void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH6BurstConfig - DMA Channel 6 burst size configuration +// +void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH6TransferConfig - DMA channel 6 transfer size configuration +// +void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH6WrapConfig - DMA Channel 6 wrap size configuration +// +void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N + // bursts. + DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH6ModeConfig - DMA Channel 6 mode configuration +// +void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = persel; + DmaRegs.CH6.MODE.bit.PERINTSEL = 6; + DmaRegs.CH6.MODE.bit.PERINTE = perinte; + DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH6.MODE.bit.DATASIZE = datasize; + DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH6.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH6 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx6 = 1; + + EDIS; +} + +// +// StartDMACH6 - This function starts DMA Channel 6. +// +void StartDMACH6(void) +{ + EALLOW; + DmaRegs.CH6.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// NOTE: +// Following functions are required for EMIF as the address is out of +// 22bit range +// + +// +// DMACH1AddrConfig32bit - DMA Channel 1 address configuration for 32bit +// +void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH2AddrConfig32bit - DMA Channel 2 address configuration for 32bit +// +void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH3AddrConfig32bit - DMA Channel 3 address configuration for 32bit +// +void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH4AddrConfig32bit - DMA Channel 4 address configuration for 32bit +// +void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH5AddrConfig32bit - DMA Channel 5 address configuration for 32bit +// +void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH6AddrConfig32bit - DMA Channel 6 address configuration for 32bit +// +void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_ECap.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_ECap.c new file mode 100644 index 00000000000..d9dcfab62e1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_ECap.c @@ -0,0 +1,147 @@ +//########################################################################### +// +// FILE: F2837xD_ECap.c +// +// TITLE: F2837xD eCAP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitECap - This function initializes the eCAP(s) to a known state. +// +void InitECap(void) +{ + // Initialize eCAP1/2/3/4/5/6 + + //tbd... +} + +// +// InitECapGpio - This function initializes GPIO pins to function as ECAP pins +// Each GPIO pin can be configured as a GPIO pin or up to 3 +// different peripheral functional pins. By default all pins +// come up as GPIO inputs after reset. +// Caution: +// For each eCAP peripheral +// Only one GPIO pin should be enabled for ECAP operation. +// Comment out other unwanted lines. +// +void InitECapGpio() +{ +} + +// +// InitECap1Gpio - Initialize ECAP1 GPIOs +// +void InitECap1Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT7SELECT = pin; // Set eCAP1 source to GPIO-pin + EDIS; +} + +// +// InitECap2Gpio - Initialize ECAP2 GPIOs +// +void InitECap2Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT8SELECT = pin; // Set eCAP2 source to GPIO-pin + EDIS; +} + +// +// InitECap3Gpio - Initialize ECAP3 GPIOs +// +void InitECap3Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT9SELECT = pin; // Set eCAP3 source to GPIO-pin + EDIS; +} + +// +// InitECap4Gpio - Initialize ECAP4 GPIOs +// +void InitECap4Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT10SELECT = pin; // Set eCAP4 source to GPIO-pin + EDIS; +} + +// +// InitECap5Gpio - Initialize ECAP5 GPIOs +// +void InitECap5Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT11SELECT = pin; // Set eCAP5 source to GPIO-pin + EDIS; +} + +// +// InitECap6Gpio - Initialize ECAP6 GPIOs +// +void InitECap6Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT12SELECT = pin; // Set eCAP6 source to GPIO-pin + EDIS; +} + +// +// InitAPwm1Gpio - Initialize EPWM1 GPIOs +// +void InitAPwm1Gpio() +{ + EALLOW; + OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX0 = 3; // Select ECAP1.OUT on Mux0 + OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX0 = 1; // Enable MUX0 for ECAP1.OUT + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Select OUTPUTXBAR3 on GPIO5 + EDIS; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_EPwm.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_EPwm.c new file mode 100644 index 00000000000..2581fe46c9d --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_EPwm.c @@ -0,0 +1,436 @@ +//########################################################################### +// +// FILE: F2837xD_EPwm.c +// +// TITLE: F2837xD EPwm Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitEPwmGpio - Initialize all EPWM modules' GPIOs +// +void InitEPwmGpio(void) +{ + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + InitEPwm5Gpio(); + InitEPwm6Gpio(); + InitEPwm7Gpio(); + InitEPwm8Gpio(); + InitEPwm9Gpio(); + InitEPwm10Gpio(); + InitEPwm11Gpio(); + InitEPwm12Gpio(); +} + +// +// InitEPwm1Gpio - Initialize EPWM1 GPIOs +// +void InitEPwm1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B) + // GpioCtrlRegs.GPEPUD.bit.GPIO145 = 1; // Disable pull-up on GPIO145 (EPWM1A) + // GpioCtrlRegs.GPEPUD.bit.GPIO146 = 1; // Disable pull-up on GPIO146 (EPWM1B) + + // + // Configure EPWM-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM1 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B + // GpioCtrlRegs.GPEMUX2.bit.GPIO145 = 1; // Configure GPIO145 as EPWM1A + // GpioCtrlRegs.GPEMUX2.bit.GPIO146 = 1; // Configure GPIO0146 as EPWM1B + + EDIS; +} + +// +// InitEPwm2Gpio - Initialize EPWM2 GPIOs +// +void InitEPwm2Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B) + // GpioCtrlRegs.GPEPUD.bit.GPIO147 = 1; // Disable pull-up on GPIO147 (EPWM2A) + // GpioCtrlRegs.GPEPUD.bit.GPIO148 = 1; // Disable pull-up on GPIO148 (EPWM2B) + + // + // Configure EPwm-2 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM2 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B + // GpioCtrlRegs.GPEMUX2.bit.GPIO147 = 1; // Configure GPIO147 as EPWM2A + // GpioCtrlRegs.GPEMUX2.bit.GPIO148 = 1; // Configure GPIO148 as EPWM2B + + EDIS; +} + +// +// InitEPwm3Gpio - Initialize EPWM3 GPIOs +// +void InitEPwm3Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B) + // GpioCtrlRegs.GPEPUD.bit.GPIO149 = 1; // Disable pull-up on GPIO149 (EPWM3A) + // GpioCtrlRegs.GPEPUD.bit.GPIO150 = 1; // Disable pull-up on GPIO150 (EPWM3B) + + // + // Configure EPwm-3 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM3 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B + // GpioCtrlRegs.GPEMUX2.bit.GPIO149 = 1; // Configure GPIO149 as EPWM3A + // GpioCtrlRegs.GPEMUX2.bit.GPIO150 = 1; // Configure GPIO150 as EPWM3B + + EDIS; +} + +// +// InitEPwm4Gpio - Initialize EPWM4 GPIOs +// +void InitEPwm4Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EPWM4A) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EPWM4B) + // GpioCtrlRegs.GPEPUD.bit.GPIO151 = 1; // Disable pull-up on GPIO151 (EPWM4A) + // GpioCtrlRegs.GPEPUD.bit.GPIO152 = 1; // Disable pull-up on GPIO152 (EPWM4B) + + // + // Configure EPWM-4 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM4 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B + // GpioCtrlRegs.GPEMUX2.bit.GPIO151 = 1; // Configure GPIO151 as EPWM4A + // GpioCtrlRegs.GPEMUX2.bit.GPIO152 = 1; // Configure GPIO152 as EPWM4B + + EDIS; +} + +// +// InitEPwm5Gpio - Initialize EPWM5 GPIOs +// +void InitEPwm5Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EPWM5A) + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EPWM5B) + // GpioCtrlRegs.GPEPUD.bit.GPIO153 = 1; // Disable pull-up on GPIO153 (EPWM5A) + // GpioCtrlRegs.GPEPUD.bit.GPIO154 = 1; // Disable pull-up on GPIO154 (EPWM5B) + + // + // Configure EPWM-5 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM5 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B + // GpioCtrlRegs.GPEMUX2.bit.GPIO153 = 1; // Configure GPIO153 as EPWM5A + // GpioCtrlRegs.GPEMUX2.bit.GPIO154 = 1; // Configure GPIO0154 as EPWM5B + + EDIS; +} + +// +// InitEPwm6Gpio - Initialize EPWM6 GPIOs +// +void InitEPwm6Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EPWM6A) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EPWM6B) + // GpioCtrlRegs.GPEPUD.bit.GPIO155 = 1; // Disable pull-up on GPIO155 (EPWM6A) + // GpioCtrlRegs.GPEPUD.bit.GPIO156 = 1; // Disable pull-up on GPIO156 (EPWM6B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B + // GpioCtrlRegs.GPEMUX2.bit.GPIO155 = 1; // Configure GPIO155 as EPWM6A + // GpioCtrlRegs.GPEMUX2.bit.GPIO156 = 1; // Configure GPIO156 as EPWM6B + + EDIS; +} + +// +// InitEPwm7Gpio - Initialize EPWM7 GPIOs +// +void InitEPwm7Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EPWM7A) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EPWM7B) + // GpioCtrlRegs.GPEPUD.bit.GPIO157 = 1; // Disable pull-up on GPIO157 (EPWM7A) + // GpioCtrlRegs.GPEPUD.bit.GPIO158 = 1; // Disable pull-up on GPIO158 (EPWM7B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EPWM7A + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EPWM7B + // GpioCtrlRegs.GPEMUX2.bit.GPIO157 = 1; // Configure GPIO157 as EPWM7A + // GpioCtrlRegs.GPEMUX2.bit.GPIO158 = 1; // Configure GPIO158 as EPWM7B + + EDIS; +} + +// +// InitEPwm8Gpio - Initialize EPWM8 GPIOs +// +void InitEPwm8Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (EPWM8A) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (EPWM8B) +// GpioCtrlRegs.GPEPUD.bit.GPIO159 = 1; // Disable pull-up on GPIO159 (EPWM8A) +// GpioCtrlRegs.GPFPUD.bit.GPIO160 = 1; // Disable pull-up on GPIO160 (EPWM8B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as EPWM8A + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as EPWM8B + // GpioCtrlRegs.GPEMUX2.bit.GPIO159 = 1; // Configure GPIO159 as EPWM8A + // GpioCtrlRegs.GPFMUX1.bit.GPIO160 = 1; // Configure GPIO160 as EPWM8B + + EDIS; +} + +// +// InitEPwm9Gpio - Initialize EPWM9 GPIOs +// +void InitEPwm9Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO161 = 1; // Disable pull-up on GPIO161 (EPWM9A) + GpioCtrlRegs.GPFPUD.bit.GPIO162 = 1; // Disable pull-up on GPIO162 (EPWM9B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO161 = 1; // Configure GPIO161 as EPWM9A + GpioCtrlRegs.GPFMUX1.bit.GPIO162 = 1; // Configure GPIO162 as EPWM9B + + EDIS; +} + +// +// InitEPwm10Gpio - Initialize EPWM10 GPIOs +// +void InitEPwm10Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO163 = 1; // Disable pull-up on GPIO163 (EPWM10A) + GpioCtrlRegs.GPFPUD.bit.GPIO164 = 1; // Disable pull-up on GPIO164 (EPWM10B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO163 = 1; // Configure GPIO163 as EPWM10A + GpioCtrlRegs.GPFMUX1.bit.GPIO164 = 1; // Configure GPIO164 as EPWM10B + + EDIS; +} + +// +// InitEPwm11Gpio - Initialize EPWM11 GPIOs +// +void InitEPwm11Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO165 = 1; // Disable pull-up on GPIO165 (EPWM11A) + GpioCtrlRegs.GPFPUD.bit.GPIO166 = 1; // Disable pull-up on GPIO166 (EPWM11B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO165 = 1; // Configure GPIO165 as EPWM11A + GpioCtrlRegs.GPFMUX1.bit.GPIO166 = 1; // Configure GPIO166 as EPWM11B + + EDIS; +} + +// +// InitEPwm12Gpio - Initialize EPWM12 GPIOs +// +void InitEPwm12Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO167 = 1; // Disable pull-up on GPIO167 (EPWM12A) + GpioCtrlRegs.GPFPUD.bit.GPIO168 = 1; // Disable pull-up on GPIO168 (EPWM12B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO167 = 1; // Configure GPIO167 as EPWM12A + GpioCtrlRegs.GPFMUX1.bit.GPIO168 = 1; // Configure GPIO168 as EPWM12B + + EDIS; +} diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_EQep.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_EQep.c new file mode 100644 index 00000000000..90629e6f40b --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_EQep.c @@ -0,0 +1,389 @@ +//########################################################################### +// +// FILE: F2837xD_EQep.c +// +// TITLE: F2837xD eQEP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitEQep - This function initializes the eQEP(s) to a known state. +// +void InitEQep(void) +{ + // Initialize eQEP1 + + //tbd... +} + +// +// InitEQepGpio - This function initializes GPIO pins to function as eQEP pins +// Each GPIO pin can be configured as a GPIO pin or up to 3 +// different peripheral functional pins. By default all pins +// come up as GPIO inputs after reset. +// Caution: +// For each eQEP peripheral +// Only one GPIO pin should be enabled for EQEPxA operation. +// Only one GPIO pin should be enabled for EQEPxB operation. +// Only one GPIO pin should be enabled for EQEPxS operation. +// Only one GPIO pin should be enabled for EQEPxI operation. +// Comment out other unwanted lines. +// +void InitEQepGpio() +{ + InitEQep1Gpio(); + InitEQep2Gpio(); + InitEQep3Gpio(); +} + +// +// InitEQep1Gpio - Initialize EQEP-1 GPIOs +// Caution: +// For each eQEP peripheral +// Only one GPIO pin should be enabled for EQEPxA operation. +// Only one GPIO pin should be enabled for EQEPxB operation. +// Only one GPIO pin should be enabled for EQEPxS operation. +// Only one GPIO pin should be enabled for EQEPxI operation. +// Comment out other unwanted lines. +// +void InitEQep1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EQEP1A) +// GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EQEP1B) +// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EQEP1S) +// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EQEP1I) + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (EQEP1A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (EQEP1B) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; // Disable pull-up on GPIO22 (EQEP1S) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; // Disable pull-up on GPIO23 (EQEP1I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO50 = 1; // Disable pull-up on GPIO50 (EQEP1A) +// GpioCtrlRegs.GPBPUD.bit.GPIO51 = 1; // Disable pull-up on GPIO51 (EQEP1B) +// GpioCtrlRegs.GPBPUD.bit.GPIO52 = 1; // Disable pull-up on GPIO52 (EQEP1S) +// GpioCtrlRegs.GPBPUD.bit.GPIO53 = 1; // Disable pull-up on GPIO53 (EQEP1I) + +// GpioCtrlRegs.GPDPUD.bit.GPIO96 = 1; // Disable pull-up on GPIO96 (EQEP1A) +// GpioCtrlRegs.GPDPUD.bit.GPIO97 = 1; // Disable pull-up on GPIO97 (EQEP1B) +// GpioCtrlRegs.GPDPUD.bit.GPIO98 = 1; // Disable pull-up on GPIO98 (EQEP1S) +// GpioCtrlRegs.GPDPUD.bit.GPIO99 = 1; // Disable pull-up on GPIO99 (EQEP1I) + + // + // Synchronize inputs to SYSCLK + // Synchronization can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 0; // Sync GPIO10 to SYSCLK (EQEP1A) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Sync GPIO11 to SYSCLK (EQEP1B) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Sync GPIO12 to SYSCLK (EQEP1S) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Sync GPIO13 to SYSCLK (EQEP1I) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync GPIO20 to SYSCLK (EQEP1A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync GPIO21 to SYSCLK (EQEP1B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync GPIO22 to SYSCLK (EQEP1S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync GPIO23 to SYSCLK (EQEP1I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync GPIO50 to SYSCLK (EQEP1A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync GPIO51 to SYSCLK (EQEP1B) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync GPIO52 to SYSCLK (EQEP1S) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync GPIO53 to SYSCLK (EQEP1I) + +// GpioCtrlRegs.GPDQSEL1.bit.GPIO96 = 0; // Sync GPIO96 to SYSCLK (EQEP1A) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO97 = 0; // Sync GPIO97 to SYSCLK (EQEP1B) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO98 = 0; // Sync GPIO98 to SYSCLK (EQEP1S) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO99 = 0; // Sync GPIO99 to SYSCLK (EQEP1I) + + // + // Configure EQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EQEP1 functional + // pins. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A +// GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A +// GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B +// GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B +// GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S +// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S +// GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I +// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I + +// GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A +// GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B +// GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S +// GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I + +// GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A +// GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A +// GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B +// GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B +// GpioCtrlRegs.GPDGMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S +// GpioCtrlRegs.GPDMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S +// GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I +// GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I + + EDIS; +} + +// +// InitEQep2Gpio - Initialize EQEP-2 GPIOs +// +void InitEQep2Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // Disable pull-up on GPIO24 (EQEP2A) + GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; // Disable pull-up on GPIO25 (EQEP2B) + GpioCtrlRegs.GPAPUD.bit.GPIO26 = 1; // Disable pull-up on GPIO26 (EQEP2S) + GpioCtrlRegs.GPAPUD.bit.GPIO27 = 1; // Disable pull-up on GPIO27 (EQEP2I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO54 = 1; // Disable pull-up on GPIO54 (EQEP2A) +// GpioCtrlRegs.GPBPUD.bit.GPIO55 = 1; // Disable pull-up on GPIO55 (EQEP2B) +// GpioCtrlRegs.GPBPUD.bit.GPIO56 = 1; // Disable pull-up on GPIO56 (EQEP2S) +// GpioCtrlRegs.GPBPUD.bit.GPIO57 = 1; // Disable pull-up on GPIO57 (EQEP2I) + +// GpioCtrlRegs.GPCPUD.bit.GPIO78 = 1; // Disable pull-up on GPIO78 (EQEP2A) +// GpioCtrlRegs.GPCPUD.bit.GPIO79 = 1; // Disable pull-up on GPIO79 (EQEP2B) +// GpioCtrlRegs.GPCPUD.bit.GPIO80 = 1; // Disable pull-up on GPIO80 (EQEP2S) +// GpioCtrlRegs.GPCPUD.bit.GPIO81 = 1; // Disable pull-up on GPIO81 (EQEP2I) + +// GpioCtrlRegs.GPDPUD.bit.GPIO100 = 1; // Disable pull-up on GPIO100 (EQEP2A) +// GpioCtrlRegs.GPDPUD.bit.GPIO101 = 1; // Disable pull-up on GPIO101 (EQEP2B) +// GpioCtrlRegs.GPDPUD.bit.GPIO102 = 1; // Disable pull-up on GPIO102 (EQEP2S) +// GpioCtrlRegs.GPDPUD.bit.GPIO103 = 1; // Disable pull-up on GPIO103 (EQEP2I) + + // + // Synchronize inputs to SYSCLK + // Synchronization can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync GPIO24 to SYSCLK (EQEP2A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync GPIO25 to SYSCLK (EQEP2B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync GPIO26 to SYSCLK (EQEP2S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync GPIO27 to SYSCLK (EQEP2I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; // Sync GPIO54 to SYSCLK (EQEP2A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 0; // Sync GPIO55 to SYSCLK (EQEP2B) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 0; // Sync GPIO56 to SYSCLK (EQEP2S) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 0; // Sync GPIO57 to SYSCLK (EQEP2I) + +// GpioCtrlRegs.GPCQSEL1.bit.GPIO78 = 0; // Sync GPIO78 to SYSCLK (EQEP2A) +// GpioCtrlRegs.GPCQSEL1.bit.GPIO79 = 0; // Sync GPIO79 to SYSCLK (EQEP2B) +// GpioCtrlRegs.GPCQSEL2.bit.GPIO80 = 0; // Sync GPIO80 to SYSCLK (EQEP2S) +// GpioCtrlRegs.GPCQSEL2.bit.GPIO81 = 0; // Sync GPIO81 to SYSCLK (EQEP2I) + +// GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 0; // Sync GPIO100 to SYSCLK (EQEP2A) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO101 = 0; // Sync GPIO101 to SYSCLK (EQEP2B) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 0; // Sync GPIO102 to SYSCLK (EQEP2S) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO103 = 0; // Sync GPIO103 to SYSCLK (EQEP2I) + + // + // Configure EQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EQEP2 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2S + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2I + +// GpioCtrlRegs.GPBGMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A +// GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A +// GpioCtrlRegs.GPBGMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B +// GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B +// GpioCtrlRegs.GPBGMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S +// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S +// GpioCtrlRegs.GPBGMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I +// GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I + +// GpioCtrlRegs.GPCGMUX1.bit.GPIO78 = 1; // Configure GPIO78 as EQEP2A +// GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 2; // Configure GPIO78 as EQEP2A +// GpioCtrlRegs.GPCGMUX1.bit.GPIO79 = 1; // Configure GPIO79 as EQEP2B +// GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 2; // Configure GPIO79 as EQEP2B +// GpioCtrlRegs.GPCGMUX2.bit.GPIO80 = 1; // Configure GPIO80 as EQEP2S +// GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 2; // Configure GPIO80 as EQEP2S +// GpioCtrlRegs.GPCGMUX2.bit.GPIO81 = 1; // Configure GPIO81 as EQEP2I +// GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 2; // Configure GPIO81 as EQEP2I + +// GpioCtrlRegs.GPDGMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A +// GpioCtrlRegs.GPDMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A +// GpioCtrlRegs.GPDGMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B +// GpioCtrlRegs.GPDMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B +// GpioCtrlRegs.GPDGMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S +// GpioCtrlRegs.GPDMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S +// GpioCtrlRegs.GPDGMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I +// GpioCtrlRegs.GPDMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I + + EDIS; +} + +// +// InitEQep3Gpio - Initialize EQEP-3 GPIOs +// +void InitEQep3Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EQEP3A) +// GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EQEP3B) +// GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EQEP3S) +// GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EQEP3I) + + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up on GPIO28 (EQEP3A) + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1; // Disable pull-up on GPIO29 (EQEP3B) + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 1; // Disable pull-up on GPIO30 (EQEP3S) + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 1; // Disable pull-up on GPIO31 (EQEP3I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO62 = 1; // Disable pull-up on GPIO62 (EQEP3A) +// GpioCtrlRegs.GPBPUD.bit.GPIO63 = 1; // Disable pull-up on GPIO63 (EQEP3B) +// GpioCtrlRegs.GPCPUD.bit.GPIO64 = 1; // Disable pull-up on GPIO64 (EQEP3S) +// GpioCtrlRegs.GPCPUD.bit.GPIO65 = 1; // Disable pull-up on GPIO65 (EQEP3I) + +// GpioCtrlRegs.GPDPUD.bit.GPIO104 = 1; // Disable pull-up on GPIO104 (EQEP3A) +// GpioCtrlRegs.GPDPUD.bit.GPIO105 = 1; // Disable pull-up on GPIO105 (EQEP3B) +// GpioCtrlRegs.GPDPUD.bit.GPIO106 = 1; // Disable pull-up on GPIO106 (EQEP3S) +// GpioCtrlRegs.GPDPUD.bit.GPIO107 = 1; // Disable pull-up on GPIO107 (EQEP3I) + + // + // Synchronize inputs to SYSCLK + // Synchronization can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Sync GPIO6 to SYSCLK (EQEP3A) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Sync GPIO7 to SYSCLK (EQEP3B) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0; // Sync GPIO8 to SYSCLK (EQEP3S) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Sync GPIO9 to SYSCLK (EQEP3I) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 0; // Sync GPIO28 to SYSCLK (EQEP3A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 0; // Sync GPIO29 to SYSCLK (EQEP3B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 0; // Sync GPIO30 to SYSCLK (EQEP3S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 0; // Sync GPIO31 to SYSCLK (EQEP3I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 0; // Sync GPIO62 to SYSCLK (EQEP3A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0; // Sync GPIO63 to SYSCLK (EQEP3B) +// GpioCtrlRegs.GPCQSEL1.bit.GPIO64 = 0; // Sync GPIO64 to SYSCLK (EQEP3S) +// GpioCtrlRegs.GPCQSEL1.bit.GPIO65 = 0; // Sync GPIO65 to SYSCLK (EQEP3I) + +// GpioCtrlRegs.GPDQSEL1.bit.GPIO104 = 0; // Sync GPIO104 to SYSCLK (EQEP3A) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO105 = 0; // Sync GPIO105 to SYSCLK (EQEP3B) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO106 = 0; // Sync GPIO106 to SYSCLK (EQEP3S) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO107 = 0; // Sync GPIO107 to SYSCLK (EQEP3I) + + // + // Configure EQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EQEP3 functional pins. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A +// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A +// GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B +// GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B +// GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S +// GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S +// GpioCtrlRegs.GPAGMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I +// GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I + + GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 1; // Configure GPIO28 as EQEP3A + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 2; // Configure GPIO28 as EQEP3A + GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 1; // Configure GPIO29 as EQEP3B + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 2; // Configure GPIO29 as EQEP3B + GpioCtrlRegs.GPAGMUX2.bit.GPIO30 = 1; // Configure GPIO30 as EQEP3S + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 2; // Configure GPIO30 as EQEP3S + GpioCtrlRegs.GPAGMUX2.bit.GPIO31 = 1; // Configure GPIO31 as EQEP3I + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 2; // Configure GPIO31 as EQEP3I + +// GpioCtrlRegs.GPBGMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A +// GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A +// GpioCtrlRegs.GPBGMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B +// GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B +// GpioCtrlRegs.GPCGMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S +// GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S +// GpioCtrlRegs.GPCGMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I +// GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I + +// GpioCtrlRegs.GPDGMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A +// GpioCtrlRegs.GPDMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A +// GpioCtrlRegs.GPDGMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B +// GpioCtrlRegs.GPDMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B +// GpioCtrlRegs.GPDGMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S +// GpioCtrlRegs.GPDMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S +// GpioCtrlRegs.GPDGMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I +// GpioCtrlRegs.GPDMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I + + EDIS; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Emif.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Emif.c new file mode 100644 index 00000000000..0f8ff9d52b8 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Emif.c @@ -0,0 +1,458 @@ +//########################################################################### +// +// FILE: F2837xD_Emif.c +// +// TITLE: F2837xD EMIF Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Emif1Initialize - This function initializes the EMIF1 to a known state. +// +void Emif1Initialize(void) +{ + EALLOW; + // + // Perform a Module soft reset on EMIF + // +#ifdef CPU1 + DevCfgRegs.SOFTPRES1.all = 0x1; + __asm (" nop"); + DevCfgRegs.SOFTPRES1.all = 0x0; +#endif + EDIS; +} + +// +// Emif2Initialize - This function initializes the EMIF2 to a known state. +// +void Emif2Initialize(void) +{ + EALLOW; + // + // Perform a Module soft reset on EMIF + // +#ifdef CPU1 + DevCfgRegs.SOFTPRES1.all = 0x2; + __asm (" nop"); + DevCfgRegs.SOFTPRES1.all = 0x0; +#endif + EDIS; +} + +// +// ASync_wait_config - Async wait configuration function +// +void ASync_wait_config(Uint16 inst, Uint16 wait_count, Uint16 wait_polarity) +{ + if (inst == 0) + { + // + // 7:0 Maximum Extended Wait cycles. + // + Emif1Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count; + + // + // 28 Wait Polarity for pad_wait_i[0]. + // + Emif1Regs.ASYNC_WCCR.bit.WP0 = wait_polarity; + } + else + { + // + // 7:0 Maximum Extended Wait cycles. + // + Emif2Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count; + + // + // 28 Wait Polarity for pad_wait_i[0]. + // + Emif2Regs.ASYNC_WCCR.bit.WP0 = wait_polarity; + } +} + +// +// ASync_cs2_config - Async CS2 Configuration +// +void ASync_cs2_config(Uint16 inst, Uint16 async_mem_data_width, + Uint16 turn_around_time, Uint16 r_hold_time, + Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, + Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, + Uint16 strobe_sel) +{ + if (inst == 0) + { + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif1Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width; + Emif1Regs.ASYNC_CS2_CR.bit.TA= turn_around_time; + Emif1Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time; + Emif1Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time; + Emif1Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup; + Emif1Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold; + Emif1Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe; + Emif1Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup; + Emif1Regs.ASYNC_CS2_CR.bit.EW = extend_wait; + Emif1Regs.ASYNC_CS2_CR.bit.SS = strobe_sel; + } + else + { + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif2Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width; + Emif2Regs.ASYNC_CS2_CR.bit.TA= turn_around_time; + Emif2Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time; + Emif2Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time; + Emif2Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup; + Emif2Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold; + Emif2Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe; + Emif2Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup; + Emif2Regs.ASYNC_CS2_CR.bit.EW = extend_wait; + Emif2Regs.ASYNC_CS2_CR.bit.SS = strobe_sel; + } +} + +// +// ASync_cs3_config - Async CS3 Configuration +// +void ASync_cs3_config(Uint16 inst, Uint16 async_mem_data_width, + Uint16 turn_around_time, Uint16 r_hold_time, + Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, + Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, + Uint16 strobe_sel) +{ + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif1Regs.ASYNC_CS3_CR.bit.ASIZE = async_mem_data_width; + Emif1Regs.ASYNC_CS3_CR.bit.TA= turn_around_time; + Emif1Regs.ASYNC_CS3_CR.bit.R_HOLD= r_hold_time; + Emif1Regs.ASYNC_CS3_CR.bit.R_STROBE = r_strobe_time; + Emif1Regs.ASYNC_CS3_CR.bit.R_SETUP = r_setup; + Emif1Regs.ASYNC_CS3_CR.bit.W_HOLD = w_hold; + Emif1Regs.ASYNC_CS3_CR.bit.W_STROBE = w_strobe; + Emif1Regs.ASYNC_CS3_CR.bit.W_SETUP = w_setup; + Emif1Regs.ASYNC_CS3_CR.bit.EW = extend_wait; + Emif1Regs.ASYNC_CS3_CR.bit.SS = strobe_sel; +} + +// +// ASync_cs4_config - Async CS4 Configuration +// +void ASync_cs4_config(Uint16 inst, Uint16 async_mem_data_width, + Uint16 turn_around_time, Uint16 r_hold_time, + Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, + Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, + Uint16 strobe_sel) +{ + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif1Regs.ASYNC_CS4_CR.bit.ASIZE = async_mem_data_width; + Emif1Regs.ASYNC_CS4_CR.bit.TA= turn_around_time; + Emif1Regs.ASYNC_CS4_CR.bit.R_HOLD= r_hold_time; + Emif1Regs.ASYNC_CS4_CR.bit.R_STROBE = r_strobe_time; + Emif1Regs.ASYNC_CS4_CR.bit.R_SETUP = r_setup; + Emif1Regs.ASYNC_CS4_CR.bit.W_HOLD = w_hold; + Emif1Regs.ASYNC_CS4_CR.bit.W_STROBE = w_strobe; + Emif1Regs.ASYNC_CS4_CR.bit.W_SETUP = w_setup; + Emif1Regs.ASYNC_CS4_CR.bit.EW = extend_wait; + Emif1Regs.ASYNC_CS4_CR.bit.SS = strobe_sel; +} + +#ifdef CPU1 +// +// setup_emif1_pinmux_async_16bit - function for EMIF1 GPIO pin setup +// +void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel) +{ + Uint16 i; + + for (i=28; i<=52; i++) + { + if ((i != 42) && (i != 43)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + for (i=63; i<=87; i++) + { + if (i != 84) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + GPIO_SetupPinMux(88,cpu_sel,3); + GPIO_SetupPinMux(89,cpu_sel,3); + GPIO_SetupPinMux(90,cpu_sel,3); + GPIO_SetupPinMux(91,cpu_sel,3); + GPIO_SetupPinMux(92,cpu_sel,3); + GPIO_SetupPinMux(93,cpu_sel,3); + GPIO_SetupPinMux(94,cpu_sel,2); + + // + //setup async mode and enable pull-ups for Data pins + // + for (i=69; i<=85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); // GPIO_ASYNC||GPIO_PULLUP + } + } +} + +// +// setup_emif1_pinmux_async_32bit - Setup pinmux for 32bit async +// +void setup_emif1_pinmux_async_32bit(Uint16 cpu_sel) +{ + Uint16 i; + + for (i=28; i<=87; i++) + { + if ((i != 42) && (i != 43) && (i != 84)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + GPIO_SetupPinMux(88,cpu_sel,3); + GPIO_SetupPinMux(89,cpu_sel,3); + GPIO_SetupPinMux(90,cpu_sel,3); + GPIO_SetupPinMux(91,cpu_sel,3); + GPIO_SetupPinMux(92,cpu_sel,3); + GPIO_SetupPinMux(93,cpu_sel,3); + GPIO_SetupPinMux(94,cpu_sel,2); + + // + //setup async mode for Data pins + // + for (i=53; i<=85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); + } + } +} + +// +// setup_emif2_pinmux_async_16bit - function for EMIF1 GPIO pin setup +// +void setup_emif2_pinmux_async_16bit(Uint16 cpu_sel) +{ + Uint16 i; + + for (i=96; i<=121; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + for (i=53; i<=68; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + // + //setup async mode for Data pins + // + for (i=53; i<=68; i++) + { + GPIO_SetupPinOptions(i,0,0x31); + } +} + +// +// setup_emif1_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM +// +void setup_emif1_pinmux_sdram_16bit(Uint16 cpu_sel) +{ + int i; + + for (i=29; i<=52; i++) + { + if ((i != 42) && (i != 43)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + for (i=69; i<=85; i++) + { + if (i != 84) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + for(i=86; i<=93; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + // + //configure Data pins for Async mode + // + for (i = 69; i <= 85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); + } + } + + GPIO_SetupPinOptions(88,0,0x31); + GPIO_SetupPinOptions(89,0,0x31); + GPIO_SetupPinOptions(90,0,0x31); + GPIO_SetupPinOptions(91,0,0x31); +} + +// +// setup_emif2_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM +// +void setup_emif2_pinmux_sdram_16bit(Uint16 cpu_sel) +{ + int i; + + for (i=53; i<=68; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + for (i=96; i<=121; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + // + //configure Data pins for Async mode + // + for (i = 53; i <= 68; i++) + { + GPIO_SetupPinOptions(i,0,0x31); + } +} + +// +// setup_emif1_pinmux_sdram_32bit - Setup pinmux for 32bit SDRAM +// +void setup_emif1_pinmux_sdram_32bit(Uint16 cpu_sel) +{ + int i; + + for (i=28; i<=85; i++) + { + if ((i != 42) && (i != 43) && (i != 84)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + for(i=86; i<=93; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + GPIO_SetupPinMux(94,cpu_sel,2); + + // + //configure Data pins for Async mode + // + for (i = 53; i <= 85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); + } + } + + GPIO_SetupPinOptions(88,0,0x31); + GPIO_SetupPinOptions(89,0,0x31); + GPIO_SetupPinOptions(90,0,0x31); + GPIO_SetupPinOptions(91,0,0x31); + } + +#endif // CPU1 + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Gpio.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Gpio.c new file mode 100644 index 00000000000..0c5927b5ed5 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Gpio.c @@ -0,0 +1,506 @@ +//########################################################################### +// +// FILE: F2837xD_Gpio.c +// +// TITLE: GPIO module support functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +//Low-level functions for GPIO configuration (CPU1 only) +// + +#ifdef CPU1 + // + // InitGpio - Sets all pins to be muxed to GPIO in input mode with pull-ups + // enabled. Also resets CPU control to CPU1 and disables open + // drain and polarity inversion and sets the qualification to + // synchronous. Also unlocks all GPIOs. Only one CPU should call + // this function. + // + void InitGpio() + { + volatile Uint32 *gpioBaseAddr; + Uint16 regOffset; + + // + //Disable pin locks + // + EALLOW; + GpioCtrlRegs.GPALOCK.all = 0x00000000; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPCLOCK.all = 0x00000000; + GpioCtrlRegs.GPDLOCK.all = 0x00000000; + GpioCtrlRegs.GPELOCK.all = 0x00000000; + GpioCtrlRegs.GPFLOCK.all = 0x00000000; + + // + // Fill all registers with zeros. Writing to each register separately + // for six GPIO modules would make this function *very* long. + // Fortunately, we'd be writing them all with zeros anyway, so this + // saves a lot of space. + // + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; + for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++) + { + // + //Hack to avoid enabling pull-ups on all pins. GPyPUD is offset + //0x0C in each register group of 0x40 words. Since this is a + //32-bit pointer, the addresses must be divided by 2. + // + if (regOffset % (0x40/2) != (0x0C/2)) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + } + + gpioBaseAddr = (Uint32 *)&GpioDataRegs; + for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + + EDIS; + } + + // + // GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The + // appropriate parameters can be found in the GPIO Muxed + // Pins table(4.4) in the datasheet. Use the GPIO index + // row (0 to 15) to select a muxing option for the GPIO. + // + void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *mux, *gmux, *csel; + Uint16 pin32, pin16, pin8; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pin8 = gpioNumber % 8; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Sanity check for valid cpu and peripheral values + // + if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF) + return; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyCSEL1-4. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + mux = gpioBaseAddr + GPYMUX + pin32/16; + gmux = gpioBaseAddr + GPYGMUX + pin32/16; + csel = gpioBaseAddr + GPYCSEL + pin32/8; + + // + //Now for the actual function + // + EALLOW; + + // + //To change the muxing, set the peripheral mux to 0/GPIO first to avoid + //glitches, then change the group mux, then set the peripheral mux to + //its target value. Finally, set the CPU select. This procedure is + //described in the TRM. Unfortunately, since we don't know the pin in + //advance we can't hardcode a bitfield reference, so there's some + //tricky bit twiddling here. + // + *mux &= ~(0x3UL << (2*pin16)); + *gmux &= ~(0x3UL << (2*pin16)); + *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16); + *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16); + + *csel &= ~(0x3L << (4*pin8)); + *csel |= (Uint32)(cpu & 0x3L) << (4*pin8); + + // + //WARNING: This code does not touch the analog mode select registers, + //which are needed to give the USB module control of its IOs. + // + EDIS; + } + + // + // GPIO_SetupPinOptions - Setup up the GPIO input/output options for the + // specified pin. + // + //The flags are a 16-bit mask produced by ORing together options. + //For input pins, the valid flags are: + //GPIO_PULLUP Enable pull-up + //GPIO_INVERT Enable input polarity inversion + //GPIO_SYNC Synchronize the input latch to PLLSYSCLK + // (default -- you don't need to specify this) + //GPIO_QUAL3 Use 3-sample qualification + //GPIO_QUAL6 Use 6-sample qualification + //GPIO_ASYNC Do not use synchronization or qualification + //(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed) + // + //For output pins, the valid flags are: + //GPIO_OPENDRAIN Output in open drain mode + //GPIO_PULLUP If open drain enabled, also enable the pull-up + //and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above. + // + //With no flags, the default input state is synchronous with no + //pull-up or polarity inversion. The default output state is + //the standard digital output. + // + void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *dir, *pud, *inv, *odr, *qsel; + Uint32 pin32, pin16, pinMask, qual; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + dir = gpioBaseAddr + GPYDIR; + pud = gpioBaseAddr + GPYPUD; + inv = gpioBaseAddr + GPYINV; + odr = gpioBaseAddr + GPYODR; + qsel = gpioBaseAddr + GPYQSEL + pin32/16; + + EALLOW; + + // + //Set the data direction + // + *dir &= ~pinMask; + if (output == 1) + { + // + //Output, with optional open drain mode and pull-up + // + *dir |= pinMask; + + // + //Enable open drain if necessary + // + if (flags & GPIO_OPENDRAIN) + { + *odr |= pinMask; + } + else + { + *odr &= ~pinMask; + } + + // + //Enable pull-up if necessary. Open drain mode must be active. + // + if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP)) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + } + else + { + // + //Input, with optional pull-up, qualification, and polarity + //inversion + // + *dir &= ~pinMask; + + // + //Enable pull-up if necessary + // + if (flags & GPIO_PULLUP) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + + // + //Invert polarity if necessary + // + if (flags & GPIO_INVERT) + { + *inv |= pinMask; + } + else + { + *inv &= ~pinMask; + } + } + + // + //Extract the qualification parameter and load it into the register. + //This is also needed for open drain outputs, so we might as well do it + //all the time. + // + qual = (flags & GPIO_ASYNC) / GPIO_QUAL3; + *qsel &= ~(0x3L << (2 * pin16)); + if (qual != 0x0) + { + *qsel |= qual << (2 * pin16); + } + + EDIS; + } + + // + // GPIO_SetupLock - Enable or disable the GPIO register bit lock for the + // specified pin. + // The valid flags are: + // GPIO_UNLOCK - Unlock the pin setup register bits for + // the specified pin + // GPIO_LOCK - Lock the pin setup register bits for the + // specified pin + // + void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *lock; + Uint32 pin32, pinMask; + + pin32 = gpioNumber % 32; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + lock = gpioBaseAddr + GPYLOCK; + + EALLOW; + if(flags) + { + //Lock the pin + *lock |= pinMask; + } + else + { + //Unlock the pin + *lock &= ~pinMask; + } + EDIS; + } + + // + //External interrupt setup + // + void GPIO_SetupXINT1Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT2Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT3Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT4Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT5Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin + EDIS; + } + + // + //GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded + // GPIOs on the 176PTP package: + // GPIOs Grp Bits + // 95-132 C 31 + // D 31:0 + // E 4:0 + // 134-168 E 31:6 + // F 8:0 + // + void GPIO_EnableUnbondedIOPullupsFor176Pin() + { + EALLOW; + GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95 + GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 + GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133 + GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 + EDIS; + } + + // + // GPIO_EnableUnbondedIOPullupsFor100Pin - Enable pullups for the unbonded + // GPIOs on the 100PZ package: + // GPIOs Grp Bits + // 0-1 A 1:0 + // 5-9 A 9:5 + // 22-40 A 31:22 + // B 8:0 + // 44-57 B 25:12 + // 67-68 C 4:3 + // 74-77 C 13:10 + // 79-83 C 19:15 + // 93-168 C 31:29 + // D 31:0 + // E 31:0 + // F 8:0 + // + void GPIO_EnableUnbondedIOPullupsFor100Pin() + { + EALLOW; + GpioCtrlRegs.GPAPUD.all = ~0xFFC003E3; //GPIOs 0-1, 5-9, 22-31 + GpioCtrlRegs.GPBPUD.all = ~0x03FFF1FF; //GPIOs 32-40, 44-57 + GpioCtrlRegs.GPCPUD.all = ~0xE10FBC18; //GPIOs 67-68, 74-77, 79-83, 93-95 + GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 + GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFFF; //GPIOs 128-159 + GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 + EDIS; + } + + // + // GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function + // this takes care of enabling IO pullups. + // + void GPIO_EnableUnbondedIOPullups() + { + // + //bits 8-10 have pin count + // + unsigned char pin_count = ((DevCfgRegs.PARTIDL.all & 0x00000700) >> 8) ; + + // + //5 = 100 pin + //6 = 176 pin + //7 = 337 pin + // + if(pin_count == 5) + { + GPIO_EnableUnbondedIOPullupsFor100Pin(); + } + else if (pin_count == 6) + { + GPIO_EnableUnbondedIOPullupsFor176Pin(); + } + else + { + //do nothing - this is 337 pin package + } + } + +#endif //CPU1 + +// +// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that +// this returns the actual state of the pin, not the state of +// the output latch. +// +Uint16 GPIO_ReadPin(Uint16 gpioNumber) +{ + volatile Uint32 *gpioDataReg; + Uint16 pinVal; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1; + + return pinVal; +} + +// +// GPIO_WritePin - Set the GPyDAT register bit for the specified pin. +// +void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal) +{ + volatile Uint32 *gpioDataReg; + Uint32 pinMask; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinMask = 1UL << (gpioNumber % 32); + + if (outVal == 0) + { + gpioDataReg[GPYCLEAR] = pinMask; + } + else + { + gpioDataReg[GPYSET] = pinMask; + } +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_I2C.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_I2C.c new file mode 100644 index 00000000000..d17266a9b07 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_I2C.c @@ -0,0 +1,301 @@ +//########################################################################### +// +// FILE: F2837xD_I2C.c +// +// TITLE: F2837xD I2C Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +//--------------------------------------------------------------------------- +// Example: I2cAGpioConfig(), I2cBGpioConfig() +//--------------------------------------------------------------------------- +// These functions configures GPIO pins to function as I2C pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// + +#ifdef CPU1 +// +// I2cAGpioConfig - Configure I2CA GPIOs +// 'I2caDataClkPin' should be assign with one of the +// possible I2C_A SDA - SDL GPIO pin Use defined Macros from +// "F2837xD_I2c_defines.h" for assignment +// +void I2cAGpioConfig(Uint16 I2caDataClkPin) +{ + EALLOW; + + switch(I2caDataClkPin) + { + case I2C_A_GPIO0_GPIO1: + + // + // Enable internal pull-up for the selected I2C pins + // Enable pull-up for GPIO0 (SDAA) + // Enable pull-up for GPIO1 (SDLA) + // + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; + + // + // Set qualification for the selected I2C pins + // Async/no qualification (I/ps sync to SYSCLKOUT by default) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 3; + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // Configure GPIO0 for SDAA operation + // Configure GPIO0 for SDAA operation + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 2; + + // + // Configure GPIO1 for SDLA operation + // Configure GPIO1 for SDLA operation + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; + + break; + + case I2C_A_GPIO32_GPIO33: + // + // Enable internal pull-up for the selected I2C pins + // + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; + + // + // Set qualification for the selected I2C pins + // + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; + + break; + + case I2C_A_GPIO42_GPIO43: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + break; + + case I2C_A_GPIO91_GPIO92: + // + // Enable internal pull-up for the selected I2C pins + // + GpioCtrlRegs.GPCPUD.bit.GPIO91 = 0; + GpioCtrlRegs.GPCPUD.bit.GPIO92 = 0; + + // + // Set qualification for the selected I2C pins + // + GpioCtrlRegs.GPCQSEL2.bit.GPIO91 = 3; + GpioCtrlRegs.GPCQSEL2.bit.GPIO92 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + GpioCtrlRegs.GPCGMUX2.bit.GPIO91 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO91 = 2; + GpioCtrlRegs.GPCGMUX2.bit.GPIO92 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO92 = 2; + break; + + case I2C_A_GPIO63104_GPIO105: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + break; + + default: + + break; + + } // End of Switch + EDIS; +} + +// +// I2cBGpioConfig - Configure I2CB GPIOs +// 'I2cbDataClkPin' should be assign with one of the possible +// I2C_B SDA - SDL GPIO pin Use defined Macros from +// "F2837xD_I2c_defines.h" for assignment +// +void I2cBGpioConfig(Uint16 I2cbDataClkPin) +{ + EALLOW; + + switch(I2cbDataClkPin) + { + case I2C_B_GPIO2_GPIO3: + // + // Enable internal pull-up for the selected I2C pins + // Enable pull-up for GPIO2 (SDAB) + // Enable pull-up for GPIO3 (SDLB) + // + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; + + // + // Set qualification for the selected I2C pins + // Async/no qualification (I/ps sync to SYSCLKOUT by default) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 3; + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // Configure GPIO2 for SDAB operation + // Configure GPIO3 for SDAB operation + // Configure GPIO1 for SDLB operation + // Configure GPIO1 for SDLB operation + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 2; + + GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; + + break; + + case I2C_B_GPIO134_GPIO35: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // + break; + + case I2C_B_GPIO40_GPIO41: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // + break; + + case I2C_B_GPIO66_GPIO69: + // + // Enable internal pull-up for the selected I2C pins + // + GpioCtrlRegs.GPCPUD.bit.GPIO66 = 0; //SDAB + GpioCtrlRegs.GPCPUD.bit.GPIO69 = 0; //SCLB + + // + // Set qualification for the selected I2C pins + // + GpioCtrlRegs.GPCQSEL1.bit.GPIO66 = 3; + GpioCtrlRegs.GPCQSEL1.bit.GPIO69 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // + GpioCtrlRegs.GPCGMUX1.bit.GPIO66 = 1; //0x6 + GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 2; + + GpioCtrlRegs.GPCGMUX1.bit.GPIO69 = 1; //0x6 + GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 2; + break; + + default: + break; + + } + EDIS; +} + +#endif + + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc.c new file mode 100644 index 00000000000..a58533c200b --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc.c @@ -0,0 +1,216 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc.c +// +// TITLE: Inter-Processor Communication module support functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#include + +// +// InitIpc - Initialize all IPC registers and clear all flags +// +void InitIpc() +{ + // + //Clear sent flags. Received flags must not be cleared locally + //to handle the case where the remote CPU starts executing first. + //In this case, a remote flag could be sent correctly and be + //incorrectly cleared by this function. Unfortunately, we're + //still left with a startup synchronization problem if the + //remote CPU has flags left over from a previous run. There's + //probably a better way of handling this. + // + IpcRegs.IPCCLR.all = 0xFFFFFFFF; + + // + //Clear commands + // + IpcRegs.IPCSENDCOM = 0; + IpcRegs.IPCSENDADDR = 0; + IpcRegs.IPCSENDDATA = 0; + IpcRegs.IPCLOCALREPLY = 0; + + // + //Clear boot status and pump semaphore + // + #if defined(CPU1) + IpcRegs.IPCBOOTMODE = 0; + #elif defined(CPU2) + IpcRegs.IPCBOOTSTS = 0; + #endif + ReleaseFlashPump(); +} + +// +// ReadIpcTimer - Read the current IPC timer value. The low register must be +// read first to latch a value in the high register. +// +unsigned long long ReadIpcTimer() +{ + Uint32 low, high; + + low = IpcRegs.IPCCOUNTERL; + high = IpcRegs.IPCCOUNTERH; + return ((unsigned long long)high << 32) | (unsigned long long)low; +} + +// +// SendIpcData - Copy data into the IPC send message RAM for this CPU and set +// a flag. If the specified 16-bit word length is greater than +// the size of the message RAM, the data is truncated. +// +void SendIpcData(void *data, Uint16 word_length, Uint16 flag) +{ + word_length = (word_length < MSG_RAM_SIZE) ? word_length : MSG_RAM_SIZE; + + memcpy(SEND_MSG_RAM, data, word_length); + + if (flag != NO_IPC_FLAG) + { + SendIpcFlag(flag); + } +} + +// +// RecvIpcData - Copy data out of the IPC receive message RAM for this CPU. If +// the specified 16-bit word length is greater than the size of +// the message RAM, the data is truncated. +// +void RecvIpcData(void *recv_buf, Uint16 word_length) +{ + word_length = (word_length < MSG_RAM_SIZE) ? word_length : MSG_RAM_SIZE; + memcpy(recv_buf, RECV_MSG_RAM, word_length); +} + +// +// FillIpcSendData - Fill the IPC send message RAM for this CPU with a constant +// value +// +void FillIpcSendData(Uint16 fill_data) +{ + memset(SEND_MSG_RAM, fill_data, MSG_RAM_SIZE); +} + +// +// SendIpcCommand - Write the send command, address, and data registers with +// the specified values, then set an IPC flag. +// +void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, Uint16 flag) +{ + IpcRegs.IPCSENDCOM = command; + IpcRegs.IPCSENDADDR = address; + IpcRegs.IPCSENDDATA = data; + + if (flag != NO_IPC_FLAG) + { + SendIpcFlag(flag); + } +} + +// +// SendIpcFlag - Set an IPC flag bit for the other CPU. Flags 0-3 will generate +// PIE interrupts. +// +void SendIpcFlag(Uint16 flag) +{ + IpcRegs.IPCSET.all = 1UL << flag; +} + +// +// AckIpcFlag - Acknowledge/clear a received IPC flag +// +void AckIpcFlag(Uint16 flag) +{ + IpcRegs.IPCACK.all = 1UL << flag; +} + +// +// CancelIpcFlag - Clear a sent IPC flag bit before the other CPU acknowledges +// it. You will normally never use this function. To clear a +// received flag, call AckIpcFlag() instead. +// +void CancelIpcFlag(Uint16 flag) +{ + IpcRegs.IPCCLR.all = 1UL << flag; +} + +// +// WaitForIpcFlag - Wait for any IPC flag in the specified mask to be set. +// WARNING: If you use this function to wait for an IPC +// interrupt, you must not clear the IPC flag in the interrupt +// handler. Otherwise, this function will never return. +// +void WaitForIpcFlag(Uint16 flag) +{ + // + //WARNING: Don't use this function to wait for an IPC interrupt! + // + while ((IpcRegs.IPCSTS.all & (1UL << flag)) == 0x00000000) {;} +} + +// +// WaitForIpcAck - Wait for any IPC flag in the specified mask to be +// acknowledged. +// +void WaitForIpcAck(Uint16 flag) +{ + while ((IpcRegs.IPCFLG.all & (1UL << flag)) != 0x00000000) {;} +} + +// +// IpcSync - Synchronize the two CPUs. Neither CPU will return from this +// function call before the other one enters it. Must be called with +// the same flag number on both CPUs. +// +void IpcSync(Uint16 flag) +{ + SendIpcFlag(flag); + WaitForIpcFlag(flag); + AckIpcFlag(flag); + WaitForIpcAck(flag); +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver.c new file mode 100644 index 00000000000..9b38efc7b57 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver.c @@ -0,0 +1,1702 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_Driver.c +// +// TITLE: F2837xD Inter-Processor Communication (IPC) API Driver Functions. +// +// DESCRIPTION: +// 28x API functions for inter-processor communications between the +// two CPUs. The IPC functions require the usage of the CPU1 to CPU2 +// and CPU2 to CPU1 MSG RAM's to store the circular ring +// buffer and indexes. Commands can be queued up in order on a single +// IPC interrupt channel. For those IPC commands which are not +// interdependent, multiple IPC interrupt channels may be used. +// The driver functions in this file are available only as +// sample functions for application development. Due to the generic +// nature of these functions and the cycle overhead inherent to a +// function call, the code is not intended to be used in cases where +// maximum efficiency is required in a system. +// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 +// Cores use this code. +// The active debug CPU will be referred to as Local CPU. +// When using this source code in CPU1, the term "local" +// will mean CPU1 and the term "remote" CPU will be mean CPU2. +// When using this source code in CPU2, the term "local" +// will mean CPU2 and the term "remote" CPU will be mean CPU1. +// +// The abbreviations LtoR and RtoL within the function names mean +// Local to Remote and Remote to Local respectively. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +//! \addtogroup ipc_driver_api +//! @{ +//***************************************************************************** +#include "F2837xD_device.h" +#include "F2837xD_Ipc_drivers.h" + +#if defined(CPU1) +#pragma DATA_SECTION(g_asIPCCPU1toCPU2Buffers, "PUTBUFFER"); +#pragma DATA_SECTION(g_usPutWriteIndexes, "PUTWRITEIDX"); +#pragma DATA_SECTION(g_usGetReadIndexes, "GETREADIDX"); + +#pragma DATA_SECTION(g_asIPCCPU2toCPU1Buffers, "GETBUFFER"); +#pragma DATA_SECTION(g_usGetWriteIndexes, "GETWRITEIDX"); +#pragma DATA_SECTION(g_usPutReadIndexes, "PUTREADIDX"); + +#elif defined(CPU2) + +#pragma DATA_SECTION(g_asIPCCPU2toCPU1Buffers, "PUTBUFFER"); +#pragma DATA_SECTION(g_usPutWriteIndexes, "PUTWRITEIDX"); +#pragma DATA_SECTION(g_usGetReadIndexes, "GETREADIDX"); + +#pragma DATA_SECTION(g_asIPCCPU1toCPU2Buffers, "GETBUFFER"); +#pragma DATA_SECTION(g_usGetWriteIndexes, "GETWRITEIDX"); +#pragma DATA_SECTION(g_usPutReadIndexes, "PUTREADIDX"); + +#endif + +// +// Global Circular Buffer Definitions +// +tIpcMessage g_asIPCCPU1toCPU2Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; +tIpcMessage g_asIPCCPU2toCPU1Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; + +// +// Global Circular Buffer Index Definitions +// +uint16_t g_usPutWriteIndexes[NUM_IPC_INTERRUPTS]; +uint16_t g_usPutReadIndexes[NUM_IPC_INTERRUPTS]; +uint16_t g_usGetWriteIndexes[NUM_IPC_INTERRUPTS]; +uint16_t g_usGetReadIndexes[NUM_IPC_INTERRUPTS]; + +//***************************************************************************** +// +//! Initializes System IPC driver controller +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param usCPU2IpcInterrupt specifies the CPU2 IPC interrupt number used by +//! psController. +//! \param usCPU1IpcInterrupt specifies the CPU1 IPC interrupt number used by +//! psController. +//! +//! This function initializes the IPC driver controller with circular buffer +//! and index addresses for an IPC interrupt pair. The +//! \e usCPU2IpcInterrupt and \e usCPU1IpcInterrupt parameters can be one of +//! the following values: +//! \b IPC_INT0, \b IPC_INT1, \b IPC_INT2, \b IPC_INT3. +//! +//! \note If an interrupt is currently in use by an \e tIpcController instance, +//! that particular interrupt should not be tied to a second \e tIpcController +//! instance. +//! +//! \note For a particular usCPU2IpcInterrupt - usCPU1IpcInterrupt pair, there +//! must be an instance of tIpcController defined and initialized on both the +//! CPU1 and CPU2 systems. +//! +//! \return None. +// +//***************************************************************************** +void +IPCInitialize (volatile tIpcController *psController, + uint16_t usCPU2IpcInterrupt, uint16_t usCPU1IpcInterrupt) +{ +#if defined(CPU1) + // CPU1toCPU2PutBuffer and Index Initialization + psController->psPutBuffer = &g_asIPCCPU1toCPU2Buffers[usCPU2IpcInterrupt-1][0]; + psController->pusPutWriteIndex = &g_usPutWriteIndexes[usCPU2IpcInterrupt-1]; + psController->pusGetReadIndex = &g_usGetReadIndexes[usCPU1IpcInterrupt-1]; + psController->ulPutFlag = (uint32_t)(1 << (usCPU2IpcInterrupt - 1)); + + // CPU1toCPU2GetBuffer and Index Initialization + psController->psGetBuffer = &g_asIPCCPU2toCPU1Buffers[usCPU1IpcInterrupt-1][0]; + psController->pusGetWriteIndex = &g_usGetWriteIndexes[usCPU1IpcInterrupt-1]; + psController->pusPutReadIndex = &g_usPutReadIndexes[usCPU2IpcInterrupt-1]; +#elif defined(CPU2) + // CPU2toCPU1PutBuffer and Index Initialization + psController->psPutBuffer = &g_asIPCCPU2toCPU1Buffers[usCPU1IpcInterrupt-1][0]; + psController->pusPutWriteIndex = &g_usPutWriteIndexes[usCPU1IpcInterrupt-1]; + psController->pusGetReadIndex = &g_usGetReadIndexes[usCPU2IpcInterrupt-1]; + psController->ulPutFlag = (uint32_t)(1 << (usCPU1IpcInterrupt - 1)); + + // CPU1toCPU2GetBuffer and Index Initialization + psController->psGetBuffer = &g_asIPCCPU1toCPU2Buffers[usCPU2IpcInterrupt-1][0]; + psController->pusGetWriteIndex = &g_usGetWriteIndexes[usCPU2IpcInterrupt-1]; + psController->pusPutReadIndex = &g_usPutReadIndexes[usCPU1IpcInterrupt-1]; +#endif + // Initialize PutBuffer WriteIndex = 0 and GetBuffer ReadIndex = 0 + *(psController->pusPutWriteIndex) = 0; + *(psController->pusGetReadIndex) = 0; +} + +//***************************************************************************** +// +//! Writes a message into the PutBuffer. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the address of the \e tIpcMessage instance to be +//! written to PutBuffer. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a free slot (1= wait until free spot available, 0 = exit with +//! STATUS_FAIL if no free slot). +//! +//! This function checks if there is a free slot in the PutBuffer. If so, it +//! puts the message pointed to by \e psMessage into the free slot and +//! increments the WriteIndex. Then it sets the appropriate IPC interrupt flag +//! specified by \e psController->usPutFlag. The \e bBlock parameter can be +//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return \b STATUS_FAIL if PutBuffer is full. \b STATUS_PASS if Put occurs +//! successfully. +// +//***************************************************************************** +uint16_t +IpcPut (volatile tIpcController *psController, tIpcMessage *psMessage, + uint16_t bBlock) +{ + uint16_t writeIndex; + uint16_t readIndex; + uint16_t returnStatus = STATUS_PASS; + + writeIndex = *(psController->pusPutWriteIndex); + readIndex = *(psController->pusPutReadIndex); + + // + // Wait until Put Buffer slot is free + // + while (((writeIndex + 1) & MAX_BUFFER_INDEX) == readIndex) + { + // + // If designated as a "Blocking" function, and Put buffer is full, + // return immediately with fail status. + // + if (!bBlock) + { + returnStatus = STATUS_FAIL; + break; + } + + readIndex = *(psController->pusPutReadIndex); + } + + if (returnStatus != STATUS_FAIL) + { + // + // When slot is free, Write Message to PutBuffer, update PutWriteIndex, + // and set the CPU IPC INT Flag + // + psController->psPutBuffer[writeIndex] = *psMessage; + + writeIndex = (writeIndex + 1) & MAX_BUFFER_INDEX; + *(psController->pusPutWriteIndex) = writeIndex; + + IpcRegs.IPCSET.all |= psController->ulPutFlag; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Reads a message from the GetBuffer. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the address of the \e tIpcMessage instance where +//! the message from GetBuffer should be written to. +//! \param bBlock specifies whether to allow function to block until GetBuffer +//! has a message (1= wait until message available, 0 = exit with STATUS_FAIL +//! if no message). +//! +//! This function checks if there is a message in the GetBuffer. If so, it gets +//! the message in the GetBuffer pointed to by the ReadIndex and writes it to +//! the address pointed to by \e psMessage. The \e bBlock parameter can be one +//! of the following +//! values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return \b STATUS_PASS if GetBuffer is empty. \b STATUS_FAIL if Get occurs +//! successfully. +// +//***************************************************************************** +uint16_t +IpcGet (volatile tIpcController *psController, tIpcMessage *psMessage, + uint16_t bBlock) +{ + uint16_t writeIndex; + uint16_t readIndex; + uint16_t returnStatus = STATUS_PASS; + + writeIndex = *(psController->pusGetWriteIndex); + readIndex = *(psController->pusGetReadIndex); + + // + // Loop while GetBuffer is empty + // + while (writeIndex == readIndex) + { + // + // If designated as a "Blocking" function, and Get buffer is empty, + // return immediately with fail status. + // + if (!bBlock) + { + returnStatus = STATUS_FAIL; + break; + } + + writeIndex = *(psController->pusGetWriteIndex); + } + + if (returnStatus != STATUS_FAIL) + { + // + // If there is a message in GetBuffer, Read Message and update + // the ReadIndex + // + *psMessage = psController->psGetBuffer[readIndex]; + + readIndex = (readIndex + 1) & MAX_BUFFER_INDEX; + *(psController->pusGetReadIndex) = readIndex; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sends a command to read either a 16- or 32-bit data word from the remote +//! CPU +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to read from +//! \param pvData is a pointer to the 16/32-bit variable where read data will +//! be stored. +//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag indicates the remote CPU to the local CPU Flag +//! number mask used to report when the read data is available at pvData. +//! (\e ulResponseFlag MUST use IPC flags 17-32, and not 1-16) +//! +//! This function will allow the local CPU system to send a 16/32-bit data +//! read command to the remote CPU system and set a ResponseFlag to track the +//! status of the read. +//! The remote CPU will respond with a DataWrite command which will place +//! the data in the local CPU address pointed to by \e pvData. When the local +//! CPU receives the DataWrite command and writes the read data into \e *pvData location, +//! it will clear the ResponseFlag, indicating to the rest of the system that +//! the data is ready. The \e usLength parameter can be one of the +//! following values: \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e +//! bBlock parameter can be one of the following values: \b ENABLE_BLOCKING or +//! \b DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataRead (volatile tIpcController *psController, uint32_t ulAddress, + void *pvData, uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + + uint16_t status; + tIpcMessage sMessage; + + // + // Set up read command, address, dataw1 = ResponseFlag | word length, + // dataw2 = address where word + // should be written to when returned. + // + sMessage.ulcommand = IPC_DATA_READ; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000)|(uint32_t)usLength; + sMessage.uldataw2 = (uint32_t)pvData; + + // + // Set ResponseFlag (cleared once data is read into address at pvData) + // Put Message into PutBuffer and set IPC INT flag + // + IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); + status = IpcPut (psController, &sMessage, bBlock); + + return status; + + // + //Note: Read Response will have sMessage.ulcommand = IPC_DATA_WRITE + // sMessage.uladdress = (uint32_t) pvData + // sMessage.uldataw1 = ulStatusFlag | + // (uint32_t) usLength; + // sMessage.uldataw2 = word to be read into + // pvData address. + // +} + +//***************************************************************************** +// +//! Sends the command to read either a 16- or 32-bit data word from remote +//! CPU system address to a write-protected local CPU address. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to read from +//! \param pvData is a pointer to the 16/32-bit variable where read data will +//! be stored. +//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag indicates the local CPU to remote CPU Flag number +//! mask used to report when the read data is available at pvData. +//! (\e ulResponseFlag MUST use IPC flags 17-32, and not 1-16) +//! +//! This function will allow the local CPU system to send a 16/32-bit data +//! read command to the remote CPU system and set a ResponseFlag to track the +//! status of the read. +//! The remote CPU system will respond with a DataWrite command which will +//! place the data in the local CPU address pointed to by \e pvData. +//! When the local CPU receives the DataWrite command and writes the read data +//! into \e *pvData location, it will clear the ResponseFlag, indicating to +//! the rest of the system that the data is ready. The \e usLength parameter +//! can be one of the following values: \b IPC_LENGTH_16_BITS or +//! \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be one of the following +//! values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataRead_Protected (volatile tIpcController *psController, + uint32_t ulAddress, void *pvData, uint16_t usLength, + uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up read command, address, dataw1 = ResponseFlag | word length, dataw2 + // = address where word should be written to when returned. + // + sMessage.ulcommand = IPC_DATA_READ_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000)|(uint32_t)usLength; + sMessage.uldataw2 = (uint32_t)pvData; + + // + // Set ResponseFlag (cleared once data is read into address at pvData) + // Put Message into PutBuffer and set IPC INT flag + // + IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); + status = IpcPut (psController, &sMessage, bBlock); + + return status; + // + // Note: Read Response will have sMessage.ulcommand = IPC_DATA_WRITE + // sMessage.uladdress = (uint32_t) pvData + // sMessage.uldataw1 = ulStatusFlag | + // (uint32_t) usLength; + // sMessage.uldataw2 = word to be read into + // pvData address. + // +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16-bit data word at the remote CPU system +//! address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! \e ulAddress. +//! 16-bit masks should fill the lower 16-bits (upper 16-bits will be all +//! 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to set bits specified by the +//! \e ulMask variable in a 16/32-bit word on the remote CPU system. The \e +//! usLength parameter can be one of the following values: \b IPC_LENGTH_16_BITS +//! or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be one of the +//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRSetBits(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up set bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_SET_BITS; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} +//***************************************************************************** +// +//! Sets the designated bits in a 16-bit write-protected data word at the +//! remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits +//! will be all 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to set bits specified by the +//! \e ulMask variable in a write-protected 16/32-bit word on the remote CPU +//! system. The \e usLength parameter can be one of the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be +//! one of the following values: +//! \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRSetBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, uint16_t usLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up set bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_SET_BITS_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16-bit data word at the remote CPU system +//! address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared +//! at \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits +//! will be all 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to clear bits specified by +//! the \e ulMask variable in a 16/32-bit word on the remote CPU system. The \e +//! usLength parameter can be one of the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be +//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRClearBits(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up clear bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_CLEAR_BITS; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16-bit write-protected data word at +//! remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the secondary CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared +//! at \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits +//! will be all 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to set bits specified by the +//! \e ulMask variable in a write-protected 16/32-bit word on the remote CPU +//! system. The \e usLength parameter can be one of the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be +//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRClearBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up clear bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_CLEAR_BITS_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to the remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote cpu address to write to +//! \param ulData specifies the 16/32-bit word which will be written. +//! For 16-bit words, only the lower 16-bits of ulData will be considered by +//! the master system. +//! \param usLength is the length of the word to write (1 = 16-bits, 2 = +//! 32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag is used to pass the \e ulResponseFlag back to the +//! remote cpu only when this function is called in response to \e +//! IPCMtoCDataRead(). Otherwise, set to 0. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! via the \e ulData variable to an address on the remote CPU system. +//! The \e usLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataWrite(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulData, uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up write command, address, dataw1 = ResponseFlag | word length, + // dataw2 = data to write + // + sMessage.ulcommand = IPC_DATA_WRITE; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulResponseFlag |(uint32_t)usLength; + sMessage.uldataw2 = ulData; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to a write-protected remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the write-protected remote CPU address to +//! write to +//! \param ulData specifies the 16/32-bit word which will be written. For +//! 16-bit words, only the lower 16-bits of ulData will be considered by the +//! master system. +//! \param usLength is the length of the word to write (1 = 16-bits, 2 = +//! 32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag is used to pass the \e ulResponseFlag back to the +//! remote CPU only when this function is called in response to \e +//! IPCMtoCDataRead(). Otherwise, set to 0. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! via the \e ulData variable to a write-protected address on the remote CPU +//! system. The \e usLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - +//! \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up write command, address, dataw1 = ResponseFlag | word length, + // dataw2 = data to write + // + sMessage.ulcommand = IPC_DATA_WRITE_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulResponseFlag |(uint32_t)usLength; + sMessage.uldataw2 = ulData; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Sends the command to read a block of data from remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU memory block starting address +//! to read from. +//! \param ulShareAddress specifies the local CPU shared memory address the +//! read block will read to. +//! \param usLength designates the block size in 16-bit words. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag indicates the local CPU to remote CPU Flag number +//! mask used to report when the read block data is available starting at +//! /e ulShareAddress. (\e ulResponseFlag MUST use IPC flags 17-32, and not +//! 1-16) +//! +//! This function will allow the local CPU system to send a read block +//! command to the remote CPU system and set a ResponseFlag to track the status +//! of the read. The remote CPU system will process the read and place the data +//! in shared memory at the location specified in the \e ulShareAddress +//! parameter and then clear the ResponseFlag, indicating that the block is +//! ready. The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. The \e ulResponseFlag parameter can +//! be any single one of the flags \b IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRBlockRead(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulShareAddress, uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up block read command, address, dataw1 = ResponseFlag | block length, + // dataw2 = remote CPU address in shared memory + // where block data should be read to + // (corresponding to local CPU ulShareAddress). + // + sMessage.ulcommand = IPC_BLOCK_READ; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000) |(uint32_t)usLength; + sMessage.uldataw2 = ulShareAddress; + + // + // Set ResponseFlag (cleared once data is read into Share Address location) + // Put Message into PutBuffer and set IPC INT flag + // + IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); + status = IpcPut (psController, &sMessage, bBlock); + + return status; + // + // Note: Read Block Response will occur in processing of ReadBlock (since + // remote CPU has access to shared memory) + // +} + +//***************************************************************************** +// +//! Writes a block of data to remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU memory block starting address +//! to write to. +//! \param ulShareAddress specifies the local CPU shared memory address where +//! data to write from resides. +//! \param usLength designates the block size in 16- or 32-bit words (depends +//! on \e usWordLength). +//! \param usWordLength designates the word size (16-bits = 1 or 32-bits = 2). +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to write a block of data to +//! the remote CPU system starting from the location specified by the +//! \e ulAdress parameter. Prior to calling this function, the local CPU +//! system code should place the data to write in shared memory starting at /e +//! ulShareAddress. +//! The \e usWordLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \note If the shared SARAM blocks are used to pass the RAM block between the +//! processors, the IPCReqMemAccess() function must be called first in order to +//! give the slave CPU write access to the shared memory block(s). +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRBlockWrite(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulShareAddress, uint16_t usLength, + uint16_t usWordLength, uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up block write command, address, dataw1 = block length, + // dataw2 = remote CPU shared mem address + // where write data resides + // + sMessage.ulcommand = IPC_BLOCK_WRITE; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ((uint32_t)(usWordLength)<<16) + (uint32_t)usLength; + sMessage.uldataw2 = ulShareAddress; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Writes a block of data to a write-protected remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the write-protected remote CPU block starting +//! address to write to. +//! \param ulShareAddress specifies the local CPU shared memory address where +//! data to write from resides. +//! \param usLength designates the block size in 16- or 32-bit words (depends +//! on \e usWordLength). +//! \param usWordLength designates the word size (16-bits = 1 or 32-bits = 2). +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to write a block of data to +//! a write-protected region on the remote CPU system starting from the +//! location specified by the \e ulAdress parameter. Prior to calling this +//! function, the local CPU system code should place the data to write in +//! shared memory starting at /e ulShareAddress. +//! The \e usWordLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \note If the shared SARAM blocks are used to pass the RAM block between the +//! processors, the IPCReqMemAccess() function must be called first in order to +//! give the the slave CPU write access to the shared memory block(s). +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRBlockWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulShareAddress, + uint16_t usLength, uint16_t usWordLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up block write command, address, dataw1 = block length, + // dataw2 = remote CPU shared mem address + // where write data resides + // + sMessage.ulcommand = IPC_BLOCK_WRITE_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ((uint32_t)(usWordLength)<<16) + (uint32_t)usLength; + sMessage.uldataw2 = ulShareAddress; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Calls remote CPU function with 1 optional parameter . +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU function address +//! \param ulParam specifies the 32-bit optional parameter value. If not used, +//! this can be a dummy value. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to call a function on the +//! remote CPU. The \e ulParam variable is a single optional 32-bit parameter +//! to pass to the function. The \e bBlock parameter can be one of the +//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRFunctionCall(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulParam, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up function call command, address, dataw1 = 32-bit parameter + // + sMessage.ulcommand = IPC_FUNC_CALL; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulParam; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Sends generic message to remote CPU system +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulCommand specifies 32-bit command word to insert into message. +//! \param ulAddress specifies 32-bit address word to insert into message. +//! \param ulDataW1 specifies 1st 32-bit data word to insert into message. +//! \param ulDataW2 specifies 2nd 32-bit data word to insert into message. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to send a generic message to +//! the remote CPU system. Note that the user should create a corresponding +//! function on the remote CPU side to interpret/use the message or fill +//! parameters in such a way that the existing IPC drivers can recognize the +//! command and properly process the message. +//! The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRSendMessage(volatile tIpcController *psController, uint32_t ulCommand, + uint32_t ulAddress, uint32_t ulDataW1, uint32_t ulDataW2, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Package message to send + // + sMessage.ulcommand = ulCommand; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulDataW1; + sMessage.uldataw2 = ulDataW2; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +#if defined (CPU2) +//***************************************************************************** +// +//! Slave CPU Configures master R/W/Exe Access to Shared SARAM. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulMask specifies the 32-bit mask for the GSxMSEL RAM control +//! register to indicate which GSx SARAM blocks the slave CPU is requesting +//! master access to. +//! \param usMaster specifies whether the CPU1 or CPU2 are given +//! master access to the GSx blocks. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the slave CPU system to configure master R/W/Exe +//! access to the GSx SARAM blocks specified by the /e ulMask parameter. The +//! function calls the \e IPCSetBits_Protected() or \e +//! IPCClearBits_Protected() functions, and therefore in the master CPU +//! application code, the corresponding functions should be called. +//! The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. The \e usMaster parameter can be +//! either: \b IPC_GSX_CPU2_MASTER or \b IPC_GSX_CPU1_MASTER. The \e ulMask +//! parameter can be any of the options: \b S0_ACCESS - \b S7_ACCESS. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCReqMemAccess (volatile tIpcController *psController, uint32_t ulMask, + uint16_t usMaster, uint16_t bBlock) +{ + uint16_t status = STATUS_PASS; + uint32_t GSxMSEL_REGaddress = (uint32_t)(&MemCfgRegs.GSxMSEL.all); + + if (usMaster == IPC_GSX_CPU2_MASTER) + { + if ((MemCfgRegs.GSxMSEL.all & ulMask) != ulMask) + { + status = + IPCLtoRSetBits_Protected (psController, GSxMSEL_REGaddress, + ulMask, IPC_LENGTH_32_BITS, + bBlock); + } + } + else if (usMaster == IPC_GSX_CPU1_MASTER) + { + if ((MemCfgRegs.GSxMSEL.all & ulMask) != 0) + { + status = + IPCLtoRClearBits_Protected (psController, GSxMSEL_REGaddress, + ulMask, IPC_LENGTH_32_BITS, + bBlock); + } + } + + return status; +} +#endif + +//***************************************************************************** +// +//! Responds to 16/32-bit data word write command the remote CPU system +//! +//! \param psMessage specifies the pointer to the message received from remote +//! CPU system which includes the 16/32-bit data word to write to the local CPU +//! address. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! received from the remote CPU system to the address indicated in \e +//! *psMessage. In the event that the IPC_DATA_WRITE command was received as a +//! result of an IPC_DATA_READ command, this function will also clear the IPC +//! response flag tracking the read so other threads in the local CPU system +//! will be aware that the data is ready. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataWrite(tIpcMessage *psMessage) +{ + // + // Data word length = dataw1 (15:0), responseFlag = valid only for IPC + // flags 17-32 + // + uint16_t length = (uint16_t) psMessage->uldataw1; + uint32_t responseFlag = (psMessage->uldataw1) & 0xFFFF0000; + + // + // Write 16/32-bit word to address + // + if (length == IPC_LENGTH_16_BITS) + { + *(uint16_t *)(psMessage->uladdress) = (uint16_t)psMessage->uldataw2; + } + else if (length == IPC_LENGTH_32_BITS) + { + *(uint32_t *)(psMessage->uladdress) = psMessage->uldataw2; + } + + // + // If data write command is in response to a data read command from remote + // CPU to local CPU clear ResponseFlag, indicating read data from remote + // CPU is ready. + // + IpcRegs.IPCCLR.all |= responseFlag; +} + +//***************************************************************************** +// +//! Responds to 16/32-bit write-protected data word write command from +//! secondary CPU system +//! +//! \param psMessage specifies the pointer to the message received from the +//! secondary CPU system which includes the 16/32-bit data word to write to the +//! local CPU address. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! received from the secondary CPU system to the write-protected address +//! indicated in \e *psMessage. +//! In the event that the IPC_DATA_WRITE_PROTECTED command was received as a +//! result of an IPC_DATA_READ_PROTECTED command, this function will also clear +//! the IPC response flag tracking the read so other threads in the local CPU +//! will be aware that the data is ready. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataWrite_Protected(tIpcMessage *psMessage) +{ + // + // Data word length = dataw1 (15:0), responseFlag = valid only for IPC + // flags 17-32 + // + uint16_t length = (uint16_t) psMessage->uldataw1; + uint32_t responseFlag = (psMessage->uldataw1) & 0xFFFF0000; + + // + // Allow access to EALLOW-protected registers. + // + EALLOW; + + // + // Write 16/32-bit word to EALLOW-protected address + // + if (length == IPC_LENGTH_16_BITS) + { + *(uint16_t *)(psMessage->uladdress) = (uint16_t)psMessage->uldataw2; + } + else if (length == IPC_LENGTH_32_BITS) + { + *(uint32_t *)(psMessage->uladdress) = psMessage->uldataw2; + } + + // + // Disable access to EALLOW-protected registers. + // + EDIS; + + // + // If data write command is in response to a data read command from local + // CPU to remote CPU, clear ResponseFlag, indicating read data from + // secondary CPU is ready + // + IpcRegs.IPCCLR.all |= responseFlag; +} + +//***************************************************************************** +// +//! Responds to 16/32-bit data word read command from remote CPU system. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the remote CPU system to read a 16/32-bit data +//! word at the local CPU address specified in /e psMessage, and send a Write +//! command with the read data back to the local CPU system. It will also send +//! the Response Flag used to track the read back to the remote CPU. +//! The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataRead(volatile tIpcController *psController, tIpcMessage *psMessage, + uint16_t bBlock) +{ + unsigned long ulReaddata; + uint16_t usLength; + + // + // If data word length = 16-bits, read the 16-bit value at the given + // address and cast as 32-bit word to send back to remote CPU. + // If data word length = 32-bits, read the 32-bit value at the given + // address. + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + ulReaddata = (unsigned long)(*(volatile uint16_t *)psMessage->uladdress); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + ulReaddata = *(unsigned long *)psMessage->uladdress; + } + + // + // Send a Write command to write the requested data to the remote CPU read + // into address. + // psMessage->uldataw2 contains remote CPU address where readdata will be + // written. + // psMessage->uldataw1 contains the read response flag in IPC flag 17-32. + // + IPCLtoRDataWrite(psController, psMessage->uldataw2, ulReaddata, usLength, + bBlock,(psMessage->uldataw1 & 0xFFFF0000)); +} + +//***************************************************************************** +// +//! Responds to 16/32-bit data word read command from remote CPU system. +//! to read into a write-protected word on the remote CPU system. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the remote CPU system to read a 16/32-bit data +//! word at the local CPU address specified in /e psMessage, and send a Write +//! Protected command with the read data back to the remote CPU system at a +//! write protected address. It will also send the Response Flag used to track +//! the read back to the remote CPU. The \e bBlock parameter can be one of the +//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataRead_Protected(volatile tIpcController *psController, + tIpcMessage *psMessage, uint16_t bBlock) +{ + unsigned long ulReaddata; + uint16_t usLength; + + // + // If data word length = 16-bits, read the 16-bit value at the given + // address and cast as 32-bit word to send back to remote CPU. + // If data word length = 32-bits, read the 32-bit value at the given + // address. + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + ulReaddata = (unsigned long)(*(volatile uint16_t *)psMessage->uladdress); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + ulReaddata = *(unsigned long *)psMessage->uladdress; + } + + // + // Send a Write command to write the requested data to the remote CPU read + // into address. + // psMessage->uldataw2 contains remote CPU address where readdata will be + // written. + // psMessage->uldataw1 contains the read response flag in IPC flag 17-32. + // + IPCLtoRDataWrite_Protected(psController, psMessage->uldataw2, ulReaddata, + usLength, bBlock, + (psMessage->uldataw1 & 0xFFFF0000)); +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at a local CPU system +//! address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the remote CPU system to set the bits in a +//! 16/32-bit word on the local CPU system via a local CPU address and mask +//! passed in via the \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLSetBits(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Determine length of word at psMessage->uladdress and then set bits based + // on either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress |= + (uint16_t) psMessage->uldataw2; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress |= psMessage->uldataw2; + } +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit write-protected data word at a +//! local CPU system address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the remote CPU system to set the bits in a write- +//! protected 16/32-bit word on the local CPU system via a local CPU address +//! and mask passed in via the \e psMessage. +//! +//! \return None +// +//***************************************************************************** +void +IPCRtoLSetBits_Protected(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Allow access to EALLOW-protected registers. + // + EALLOW; + + // + // Determine length of word at psMessage->uladdress and then set bits based + // on either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress |= + (uint16_t) psMessage->uldataw2; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress |= psMessage->uldataw2; + } + + // + // Disable access to EALLOW-protected registers. + // + EDIS; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 32-bit data word at a local CPU system +//! address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the remote CPU system to clear the bits in a +//! 16/32-bit word on the local CPU system via a local CPU address and mask +//! passed in via the \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLClearBits(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Determine length of word at psMessage->uladdress and then clear bits + // based on + // either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress &= + ~((uint16_t) psMessage->uldataw2); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress &= + ~(psMessage->uldataw2); + } +} + +//***************************************************************************** +// +//! Clears the designated bits in a write-protected 16/32-bit data word at a +//! local CPU system address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the secondary CPU system to clear the bits in a +//! 16/32-bit write-protected word on the local CPU system via a local +//! CPU address and mask passed in via the \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLClearBits_Protected(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Allow access to EALLOW-protected registers. + // + EALLOW; + + // + // Determine length of word at psMessage->uladdress and then clear bits + // based on + // either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress &= + ~((uint16_t) psMessage->uldataw2); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress &= + ~(psMessage->uldataw2); + } + + // + // Disable access to EALLOW-protected registers. + // + EDIS; +} + +//***************************************************************************** +// +//! Reads a block of data from a remote CPU system address and stores into +//! shared RAM +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will respond to the remote CPU system request to read a block +//! of data from the local control system, by reading the data and placing that +//! data into the shared RAM location specified in \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLBlockRead(tIpcMessage *psMessage) +{ + + uint16_t usLength; + volatile uint16_t* pusRAddress; + volatile uint16_t* pusWAddress; + uint16_t usIndex; + + pusRAddress = (volatile uint16_t *)psMessage->uladdress; + pusWAddress = (volatile uint16_t *)psMessage->uldataw2; + usLength = (uint16_t)psMessage->uldataw1; + + for (usIndex=0; usIndexuldataw1 & 0xFFFF0000); +} + +//***************************************************************************** +// +//! Writes a block of data to a local CPU system address from shared RAM +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will write a block of data to an address on the local CPU +//! system. +//! The data is first written by the remote CPU to shared RAM. This function +//! reads the shared RAM location, word size (16- or 32-bit), and block size +//! from \e psMessage and writes the block to the local address specified +//! in \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLBlockWrite(tIpcMessage *psMessage) +{ + uint16_t usLength; + uint16_t usWLength; + uint16_t usIndex; + + usLength = (uint16_t)psMessage->uldataw1; + usWLength = (uint16_t)((psMessage->uldataw1)>>16); + + // + // Determine data word access size to write to data block. + // + if (usWLength == IPC_LENGTH_16_BITS) + { + volatile uint16_t *pusWAddress = (volatile uint16_t *)psMessage->uladdress; + volatile uint16_t *pusRAddress = (volatile uint16_t *)psMessage->uldataw2; + for (usIndex=0; usIndexuladdress; + volatile unsigned long *pulRAddress = + (volatile unsigned long *)psMessage->uldataw2; + + for (usIndex=0; usIndexuldataw1; + usWLength = (uint16_t)((psMessage->uldataw1)>>16); + + // + // Determine data word access size to write to data block. + // (Writes registers accessible via APB bus must be 32-bits wide) + // + if (usWLength == IPC_LENGTH_16_BITS) + { + volatile uint16_t *pusWAddress = (volatile uint16_t *)psMessage->uladdress; + volatile uint16_t *pusRAddress = (volatile uint16_t *)psMessage->uldataw2; + for (usIndex=0; usIndexuladdress; + volatile unsigned long *pulRAddress = + (volatile unsigned long *)psMessage->uldataw2; + + for (usIndex=0; usIndexuladdress; + func_call(psMessage->uldataw1); +} + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Lite.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Lite.c new file mode 100644 index 00000000000..9f8dc61c9c1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Lite.c @@ -0,0 +1,1302 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_Driver_Lite.c +// +// TITLE: F2837xD Inter-Processor Communication (IPC) Lite API Driver +// Functions. +// +// DESCRIPTION: +// API functions for inter-processor communications between +// CPU1 control system and CPU2 control system (Lite version). The IPC +// Lite functions only allow for basic functions such as data writes, +// reads, bit setting, and bit clearing. The Lite functions do not +// require the usage of the MSG RAM's or shared memories and can only +// be used with a single IPC interrupt channel. Commands can only +// be processed one at a time without queuing. +// The driver functions in this file are available only as +// sample functions for application development. Due to the generic +// nature of these functions and the cycle overhead inherent to a +// function call, the code is not intended to be used in cases where +// maximum efficiency is required in a system. +// +// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 +// cores use this code. +// The active debug CPU will be referred to as Local CPU and the other +// CPU will be referred to as Remote CPU. +// When using this source code in CPU1, the term "local" +// will mean CPU1 and the term "remote" CPU will be mean CPU2. +// When using this source code in CPU2, the term "local" +// will mean CPU2 and the term "remote" CPU will be mean CPU1. +// +// The abbreviations LtoR and RtoL within the function names mean +// Local to Remote and Remote to Local respectively. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +//! \addtogroup ipc_lite_api IPC-Lite API Drivers +//! @{ +//***************************************************************************** +#include "F2837xD_device.h" +#include "F2837xD_Ipc_drivers.h" + +// +// Function Prototypes +// +void DelayLoop (void); + +//***************************************************************************** +// +//! Reads single word data result of Local to Remote IPC command +//! +//! \param pvData is a pointer to the 16/32-bit variable where the result data +//! will be stored. +//! \param usLength designates 16- or 32-bit read. +//! \param ulStatusFlag indicates the Local to Remote CPU Flag number mask used +//! to report the status of the command sent back from the Remote CPU. If +//! a status flag was not used with the command call, set this parameter to 0. +//! +//! Allows the caller to read the 16/32-bit data result of non-blocking IPC +//! functions from the IPCREMOTEREPLY register if the status flag is cleared +//! indicating the IPC command was successfully interpreted. If the status flag +//! is not cleared, the command was not recognized, and the function will +//! return STATUS_FAIL. To determine what data is read from a call to this +//! function, see the descriptions of the non-blocking IPC functions. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +//! The function returns \b STATUS_PASS or \b STATUS_FAIL. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRGetResult (void *pvData, uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // If Remote System never acknowledged Status Task, indicates command + // failure. + // + if (IpcRegs.IPCFLG.all & ulStatusFlag) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Read data. + // + if (usLength == IPC_LENGTH_16_BITS) + { + *(uint16_t *)pvData = IpcRegs.IPCREMOTEREPLY; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(uint32_t *)pvData = IpcRegs.IPCREMOTEREPLY; + } + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Reads either a 16- or 32-bit data word from the remote CPU System address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the remote address to read from +//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the remote system. +//! +//! This function will allow the Local CPU System to read 16/32-bit data from +//! the Remote CPU System into the IPCREMOTEREPLY register. After calling this +//! function, a call to \e IPCLiteLtoRGetResult() will read the data value in +//! the IPCREMOTEREPLY register into a 16- or 32-bit variable in the local CPU +//! application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRDataRead(uint32_t ulFlag, uint32_t ulAddress, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up read command, address, and word length. + // + if (usLength == IPC_LENGTH_16_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_READ_16; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_READ_32; + } + IpcRegs.IPCSENDADDR = ulAddress; + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at the remote CPU system +//! address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote address to write to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! remote ulAddress. For 16-bit mask, only the lower 16-bits of ulMask are +//! considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Remote system. +//! +//! This function will allow the Local CPU system to set bits specified by the +//! \e usMask variable in a 16/32-bit word on the Remote CPU system. The data +//! word at /e ulAddress after the set bits command is then read into the +//! IPCREMOTEREPLY register. After calling this function, a call to \e +//! IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local CPU application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRSetBits(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_16; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_32; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit write-protected data word at +//! the Remote CPU system address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU write-protected address to write +//! to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! Remote CPU ulAddress.For 16-bit mask, only the lower 16-bits of ulMask are +//! considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU system to set bits specified by the +//! \e usMask variable in a write-protected 16/32-bit word on the REmote CPU +//! system. +//! The data word at /e ulAddress after the set bits command is then read into +//! the IPCREMOTEREPLY register. After calling this function, a call to +//! \e IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRSetBits_Protected (uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_16_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_32_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at the remote CPU system +//! address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU address to write to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! the remote CPU ulAddress. (For 16-bit mask, only the lower 16-bits of +//! ulMask are considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU system to set bits specified by the +//! \e usMask variable in a 16/32-bit word on the Remote CPU system. The data +//! word at /e ulAddress after the set bits command is then read into the +//! IPCREMOTEREPLY register. After calling this function, a call to \e +//! IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local CPU application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRClearBits(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_16; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_32; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16/32-bit write-protected data word at +//! Remote CPU system address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU write-protected address to write +//! to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared +//! at Remote CPU ulAddress.For 16-bit mask, only the lower 16-bits of ulMask +//! are considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU system to clear bits specified by +//! the \e usMask variable in a write-protected 16/32-bit word on the Remote +//! CPU system. +//! The data word at /e ulAddress after the clear bits command is then read +//! into the IPCREMOTEREPLY register. After calling this function, a call to +//! \e IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local CPU application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRClearBits_Protected (uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_16_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_32_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to Remote CPU System address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU address to write to +//! \param ulData specifies the 16/32-bit word which will be written. +//! For 16-bit words, only the lower 16-bits of ulData will be considered by +//! the master system. +//! \param usLength is the length of the word to write (0 = 16-bits, 1 = +//! 32-bits) +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Remote CPU system. +//! +//! This function will allow the Local CPU System to write a 16/32-bit word +//! via the \e ulData variable to an address on the Remote CPU System. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRDataWrite(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up data write command, address, and data. For 16-bit write, + // Master system will look at lower 16-bits only. + // + if (usLength == IPC_LENGTH_16_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_16; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_32; + } + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulData; + + // + // Force IPC event on selected request task and enable status-checking + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to a protected Remote CPU System address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU address to write to +//! \param ulData specifies the 16/32-bit word which will be written. +//! For 16-bit words, only the lower 16-bits of ulData will be considered by +//! the master system. +//! \param usLength is the length of the word to write (0 = 16-bits, 1 = +//! 32-bits) +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU System to write a 16/32-bit word +//! via the \e ulData variable to a write-protected address on the Remote CPU +//! System. The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRDataWrite_Protected(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulData, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up data write command, address, and data. For 16-bit write, Master + // system will look at lower 16-bits only. + // + if (usLength == IPC_LENGTH_16_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_16_PROTECTED; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_32_PROTECTED; + } + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulData; + + // + // Force IPC event on selected request task and enable status-checking + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Calls a Remote CPU function with 1 optional parameter and an optional +//! return value. +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU function address +//! \param ulParam specifies the 32-bit optional parameter value +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Local CPU system to call a function on the +//! Remote CPU. The \e ulParam variable is a single optional 32-bit parameter +//! to pass to the function. The \e ulFlag parameter accepts any one of the +//! flag values \b IPC_FLAG1 - \b IPC_FLAG32. The \e ulStatusFlag parameter +//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 +//! and \b NO_FLAG. The function returns \b STATUS_PASS if the command is +//! successful or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRFunctionCall(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulParam, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Remote to Local request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up function call command, address, and parameter. + // + IpcRegs.IPCSENDCOM = IPC_FUNC_CALL; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulParam; + + // + // Force IPC event on selected request task and enable status-checking + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Slave Requests Master R/W/Exe Access to Shared SARAM. +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulMask specifies the 32-bit mask for the GSxMEMSEL RAM control +//! register to indicate which GSx SARAM blocks the Slave is requesting master +//! access to. +//! \param ulMaster specifies whether CPU1 or CPU2 should be the master of the +//! GSx RAM. +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the slave CPU System to request slave or master +//! mastership of any of the GSx Shared SARAM blocks. +//! The \e ulMaster parameter accepts the following values: +//! \b IPC_GSX_CPU2_MASTER or \b IPC_GSX_CPU1_MASTER. The \e ulStatusFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 +//! and \b NO_FLAG. The function returns \b STATUS_PASS if the command is +//! successful or \b STATUS_FAIL if the request or status flags are unavailable. +//! \note This function calls the \e IPCLiteLtoRSetBits_Protected() or the +//! \e IPCLiteLtoRClearBits_Protected function, and therefore in order to +//! process this function, the above 2 functions should be ready to be called +//! on the master system to process this command. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteReqMemAccess (uint32_t ulFlag, uint32_t ulMask, uint16_t ulMaster, + uint32_t ulStatusFlag) +{ + uint16_t status; + uint32_t GSxMSEL_REGaddress = (uint32_t)(&MemCfgRegs.GSxMSEL.all); + if (ulMaster == IPC_GSX_CPU2_MASTER) + { + status = + IPCLiteLtoRSetBits_Protected (ulFlag, GSxMSEL_REGaddress, ulMask, + IPC_LENGTH_32_BITS, + ulStatusFlag); + } + else if (ulMaster == IPC_GSX_CPU1_MASTER) + { + status = + IPCLiteLtoRClearBits_Protected (ulFlag, GSxMSEL_REGaddress, ulMask, + IPC_LENGTH_32_BITS, + ulStatusFlag); + } + + return status; +} + +//***************************************************************************** +// +//! Reads either a 16- or 32-bit data word from the Local CPU system address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to read 16/32-bit data from +//! the Local CPU system. The \e ulFlag parameter accepts any one of the +//! flag values \b IPC_FLAG1 - \b IPC_FLAG32, and the \e ulStatusFlag parameter +//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and +//! \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLDataRead(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + + uint32_t* pulRAddress; + uint16_t* pusRAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command and data length are correct for this function: + // Then read from requested address and write 16/32-bit data + // to IPCLOCALREPLY. Acknowledge the status flag + // and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_DATA_READ_16) + { + // + // Perform 16-bit read. + // + pusRAddress = (uint16_t *)IpcRegs.IPCRECVADDR; + IpcRegs.IPCLOCALREPLY = (uint32_t)(*pusRAddress); + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_DATA_READ_32) + { + pulRAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + IpcRegs.IPCLOCALREPLY = *pulRAddress; + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + //(Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at the Local CPU system +//! address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to set bits specified by a +//! mask variable in a 16/32-bit word on the Local CPU system, and then read +//! back the word into the IPCLOCALREPLY register. The \e ulFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, and the +//! \e ulStatusFlag parameter accepts any other one of the flag values \b +//! IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLSetBits(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then set the mask bits at the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_16) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress |= (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_32) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; + *pulAddress |= (uint32_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16-bit data word at the Local CPU system +//! write-protected address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to set bits specified by a +//! mask variable in a write-protected 16/32-bit word on the Local CPU system, +//! and then read back the word into the IPCLOCALREPLY register. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLSetBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag) +{ + + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then enable write access with EALLOW and + // set the mask bits at the requested address. + // Write back the 16-bit data to IPCLOCALREPLY. + // Restore write-protection with EDIS. + // Acknowledge the status flag and the task flag. + // + + EALLOW; + + if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_16_PROTECTED) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR; + *pusAddress |= (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_32_PROTECTED) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + *pulAddress |= (uint32_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + //(Indicates to the Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } + + EDIS; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16/32-bit data word at Local CPU system +//! address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to clear bits specified by a +//! mask variable in a 16/32-bit word on the Local CPU system, and then read +//! back the word into the IPCLOCALREPLY register. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLClearBits(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then clear the mask bits at the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_16) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress &= ~((uint16_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_32) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + *pulAddress &= ~((uint32_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16/32-bit data word at the Local CPU system +//! write-protected address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to clear bits specified by a +//! mask variable in a 16/32-bit word on the Local CPU system, and then read +//! back the word into the IPCLOCALREPLY register. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLClearBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then enable write access with EALLOW and + // clear the mask bits at the requested address. + // Write back the 16/32-bit data to IPCLOCALREPLY. + // Restore the status of the EALLOW register. + // Acknowledge the status flag and the task flag. + // + EALLOW; + + if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_16_PROTECTED) + { + + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress &= ~((uint16_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_32_PROTECTED) + { + + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; + *pulAddress &= ~((uint32_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = (uint32_t)*pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } + + EDIS; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to Local CPU system address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to write a 16/32-bit word +//! to an address on the Local CPU system. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLDataWrite(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint32_t* pulAddress; + uint16_t* pusAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then write the 16/32-bit data to the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_16) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress = (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_32) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; + *pulAddress = IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to a write-protected Local CPU system address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to write a 16/32-bit word +//! to an address on the Local CPU system. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLDataWrite_Protected(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint32_t* pulAddress; + uint16_t* pusAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then enable write access with EALLOW and + // write the 16/32-bit data to the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + EALLOW; + + if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_16_PROTECTED) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress = (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_32_PROTECTED) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + *pulAddress = IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } + + // + // Restore write-protection status. + // + EDIS; +} + +//***************************************************************************** +// +//! Calls a Local CPU function with a single optional parameter and return +//! value. +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to call a Local CPU function +//! with a single optional parameter and places an optional return value in the +//! IPCLOCALREPLY register. The \e ulFlag parameter accepts any one of the flag +//! values \b IPC_FLAG1 - \b IPC_FLAG32, and the \e ulStatusFlag parameter +//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and +//! \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLFunctionCall(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then call function at requested address + // and if there is a return value, insert into + // IPCLOCALREPLY register. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_FUNC_CALL) + { + tfIpcFuncCall func_call = (tfIpcFuncCall)IpcRegs.IPCRECVADDR; + IpcRegs.IPCLOCALREPLY = func_call(IpcRegs.IPCRECVDATA); + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + //(Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +void DelayLoop (void) +{ + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); +} + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Util.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Util.c new file mode 100644 index 00000000000..7f98a29ea1f --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Ipc_Driver_Util.c @@ -0,0 +1,469 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_Driver_Util.c +// +// TITLE: F2837xD Inter-Processor Communication (IPC) API Driver Utility +// Functions +// +// DESCRIPTION: +// API functions for inter-processor communications between the +// Local and Remote CPU system. +// The driver functions in this file are available only as +// sample functions for application development. Due to the generic +// nature of these functions and the cycle overhead inherent to a +// function call, the code is not intended to be used in cases where +// maximum efficiency is required in a system. +// +// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 +// cores use this code. +// The active debug CPU will be referred to as Local CPU and the other +// CPU will be referred to as Remote CPU. +// When using this source code in CPU1, the term "local" +// will mean CPU1 and the term "remote" CPU will be mean CPU2. +// When using this source code in CPU2, the term "local" +// will mean CPU2 and the term "remote" CPU will be mean CPU1. +// +// The abbreviations LtoR and RtoL within the function names mean +// Local to Remote and Remote to Local respectively. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup ipc_util_api +//! @{ +// +//***************************************************************************** +#include "F2837xD_device.h" +#include "F2837xD_GlobalPrototypes.h" +#include "F2837xD_Gpio_defines.h" +#include "F2837xD_Ipc_drivers.h" + +//***************************************************************************** +// +//! Local CPU Acknowledges Remote to Local IPC Flag. +//! +//! \param ulFlags specifies the IPC flag mask for flags being acknowledged. +//! +//! This function will allow the Local CPU system to acknowledge/clear the IPC +//! flag set by the Remote CPU system. The \e ulFlags parameter can be any of +//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLFlagAcknowledge (uint32_t ulFlags) +{ + IpcRegs.IPCACK.all |= ulFlags; +} + +//***************************************************************************** +// +//! Determines whether the given Remote to Local IPC flags are busy or not. +//! +//! \param ulFlags specifies Remote to Local IPC Flag number masks to check the +//! status of. +//! +//! Allows the caller to determine whether the designated IPC flags are +//! pending. The \e ulFlags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated +//! IPC flags are free. +// +//***************************************************************************** +Uint16 +IPCRtoLFlagBusy (uint32_t ulFlags) +{ + Uint16 returnStatus; + + if ((IpcRegs.IPCSTS.all & ulFlags) == 0) + { + returnStatus = 0; + } + else + { + returnStatus = 1; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Determines whether the given IPC flags are busy or not. +//! +//! \param ulFlags specifies Local to Remote IPC Flag number masks to check the +//! status of. +//! +//! Allows the caller to determine whether the designated IPC flags are +//! available for further control to master system communication. If \b 0 is +//! returned, then all designated tasks have completed and are available. +//! The \e ulFlags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated +//! IPC flags are free. +// +//***************************************************************************** +Uint16 +IPCLtoRFlagBusy (uint32_t ulFlags) +{ + Uint16 returnStatus; + + if ((IpcRegs.IPCFLG.all & ulFlags) == 0) + { + returnStatus = 0; + } + else + { + returnStatus = 1; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Local CPU Sets Local to Remote IPC Flag +//! +//! \param ulFlags specifies the IPC flag mask for flags being set. +//! +//! This function will allow the Local CPU system to set the designated IPC +//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +void +IPCLtoRFlagSet (uint32_t ulFlags) +{ + IpcRegs.IPCSET.all |= ulFlags; +} + +//***************************************************************************** +// +//! Local CPU Clears Local to Remote IPC Flag +//! +//! \param ulFlags specifies the IPC flag mask for flags being set. +//! +//! This function will allow the Local CPU system to set the designated IPC +//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +void +IPCLtoRFlagClear (uint32_t ulFlags) +{ + IpcRegs.IPCCLR.all |= ulFlags; +} + +//***************************************************************************** +// +//! Local Return CPU02 BOOT status +//! +//! This function returns the value at IPCBOOTSTS register. +//! +//! \return Boot status. +// +//***************************************************************************** +uint32_t +IPCGetBootStatus (void) +{ + return(IpcRegs.IPCBOOTSTS); +} + +#if defined (CPU1) +//***************************************************************************** +//! Executes a CPU02 control system bootloader. +//! +//! \param ulBootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. Unlike other IPCLite driver functions, this +//! function blocks and waits until the control system boot ROM is configured +//! and ready to receive CPU01 to CPU02 IPC INT0 interrupts. It then blocks and +//! waits until IPC INT0 and IPC FLAG31 are available in the CPU02 boot ROM +//! prior to sending the command to execute the selected bootloader. The \e +//! ulBootMode parameter accepts one of the following values: \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_SCI, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_SPI, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_I2C, \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN, +//! \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH. +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +uint16_t +IPCBootCPU2(uint32_t ulBootMode) +{ + uint32_t bootStatus; + uint16_t pin; + uint16_t returnStatus = STATUS_PASS; + + // + // If CPU2 has already booted, return a fail to let the application + // know that something is out of the ordinary. + // + bootStatus = IPCGetBootStatus() & 0x0000000F; + + if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK) + { + // + // Check if MSB is set as well + // + bootStatus = ((uint32_t)(IPCGetBootStatus() & 0x80000000)) >> 31U; + + if(bootStatus != 0) + { + returnStatus = STATUS_FAIL; + + return returnStatus; + } + } + + // + // Wait until CPU02 control system boot ROM is ready to receive + // CPU01 to CPU02 INT1 interrupts. + // + do + { + bootStatus = IPCGetBootStatus() & C2_BOOTROM_BOOTSTS_SYSTEM_READY; + } while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY)); + + // + // Loop until CPU02 control system IPC flags 1 and 32 are available + // + while ((IPCLtoRFlagBusy(IPC_FLAG0) == 1) || + (IPCLtoRFlagBusy(IPC_FLAG31) == 1)) + { + + } + + if (ulBootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Based on boot mode, enable pull-ups on peripheral pins and + // give GPIO pin control to CPU02 control system. + // + switch (ulBootMode) + { + case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI: + + EALLOW; + + // + //SCIA connected to CPU02 + // + DevCfgRegs.CPUSEL5.bit.SCI_A = 1; + + // + //Allows CPU02 bootrom to take control of clock + //configuration registers + // + ClkCfgRegs.CLKSEM.all = 0xA5A50000; + + ClkCfgRegs.LOSPCP.all = 0x0002; + EDIS; + + GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC); + GPIO_SetupPinMux(29,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(28,GPIO_MUX_CPU2,1); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI: + EALLOW; + + // + //SPI-A connected to CPU02 + // + DevCfgRegs.CPUSEL6.bit.SPI_A = 1; + + // + //Allows CPU02 bootrom to take control of clock configuration + // registers + // + ClkCfgRegs.CLKSEM.all = 0xA5A50000; + EDIS; + + GPIO_SetupPinOptions(16, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(16,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(17, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(17,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(18, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(18,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(19, GPIO_OUTPUT, GPIO_ASYNC); + GPIO_SetupPinMux(19,GPIO_MUX_CPU2,0); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C: + EALLOW; + + // + //I2CA connected to CPU02 + // + DevCfgRegs.CPUSEL7.bit.I2C_A = 1; + + // + //Allows CPU2 bootrom to take control of clock + //configuration registers + // + ClkCfgRegs.CLKSEM.all = 0xA5A50000; + ClkCfgRegs.LOSPCP.all = 0x0002; + EDIS; + GPIO_SetupPinOptions(32, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(32,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(33, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(33,GPIO_MUX_CPU2,1); + + break; + case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL: + + for(pin=58;pin<=65;pin++) + { + GPIO_SetupPinOptions(pin, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(pin,GPIO_MUX_CPU2,0); + } + + GPIO_SetupPinOptions(69, GPIO_OUTPUT, GPIO_ASYNC); + GPIO_SetupPinMux(69,GPIO_MUX_CPU2,0); + + GPIO_SetupPinOptions(70, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(70,GPIO_MUX_CPU2,0); + break; + + + case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN: + // + //Set up the GPIO mux to bring out CANATX on GPIO71 + //and CANARX on GPIO70 + // + EALLOW; + GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95 + + // + //Give CPU2 control just in case + // + GpioCtrlRegs.GPCCSEL1.bit.GPIO71 = GPIO_MUX_CPU2; + + // + //Set the extended mux to 0x5 + // + GpioCtrlRegs.GPCGMUX1.bit.GPIO71 = 0x1; + GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 0x1; + + // + //Set qualification to async just in case + // + GpioCtrlRegs.GPCQSEL1.bit.GPIO71 = 0x3; + + GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95 + + // + //Give CPU2 control just in case + // + GpioCtrlRegs.GPCCSEL1.bit.GPIO70 = GPIO_MUX_CPU2; + + // + //Set the extended mux to bring out CANATX + // + GpioCtrlRegs.GPCGMUX1.bit.GPIO70 = 0x1; + GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 0x1; + + // + //Set qualification to async just in case + // + GpioCtrlRegs.GPCQSEL1.bit.GPIO70 = 0x3; + GpioCtrlRegs.GPCLOCK.all = 0xFFFFFFFF; //Lock GPIOs 64-95 + ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = 0x0; + CpuSysRegs.PCLKCR10.bit.CAN_A = 1; + EDIS; + + break; + + } + + // + //CPU01 to CPU02 IPC Boot Mode Register + // + IpcRegs.IPCBOOTMODE = ulBootMode; + + // + // CPU01 To CPU02 IPC Command Register + // + IpcRegs.IPCSENDCOM = BROM_IPC_EXECUTE_BOOTMODE_CMD; + + // + // CPU01 to CPU02 IPC flag register + // + IpcRegs.IPCSET.all = 0x80000001; + + } + + + + return returnStatus; +} + + +#endif +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Mcbsp.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Mcbsp.c new file mode 100644 index 00000000000..b93b01a4ffc --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Mcbsp.c @@ -0,0 +1,584 @@ +//########################################################################### +// +// FILE: F2837xD_McBSP.c +// +// TITLE: F2837xD Device McBSP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate +// generator (SRG) cycles required for the Mcbsp initialization routine. +// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock +// generator (CLKG) cycles required for the Mcbsp initialization routine. +// + +// +// Defines +// +#define CPU_SPD 200E6 +#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) + // for examples +#define CLKGDV_VAL 1 + +// # of CPU cycles in 2 SRG cycles-init delay +#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ) + +// # of CPU cycles in 2 CLKG cycles-init delay +#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) + +// +// Function Prototypes +// +void delay_loop(void); // Delay function used for SRG initialization +void clkg_delay_loop(void); // Delay function used for CLKG initialization + +// +// InitMcbsp - This function initializes the McBSP to a known state. +// +void InitMcbspa(void) +{ + // + // Reset the McBSP + // Disable all interrupts + // Frame sync generator reset + // Sample rate generator reset + // Transmitter reset + // Receiver reset + // + McbspaRegs.SPCR2.bit.FRST = 0; + McbspaRegs.SPCR2.bit.GRST = 0; + McbspaRegs.SPCR2.bit.XRST = 0; + McbspaRegs.SPCR1.bit.RRST = 0; + + // + // Enable loop back mode + // This does not require external hardware + // + McbspaRegs.SPCR2.all = 0x0000; + McbspaRegs.SPCR1.all = 0x8000; + + // + // RX data delay is 1 bit + // TX data delay is 1 bit + // + McbspaRegs.RCR2.bit.RDATDLY = 1; + McbspaRegs.XCR2.bit.XDATDLY = 1; + + // + // No clock sync for CLKG + // Frame-synchronization period + // + McbspaRegs.SRGR2.bit.GSYNC = 0; + McbspaRegs.SRGR2.bit.FPER = 320; + + // + // Frame-synchronization pulses from + // the sample rate generator + // + McbspaRegs.SRGR2.bit.FSGM = 1; + + // + // Sample rate generator input clock is LSPCLK + // + McbspaRegs.SRGR2.bit.CLKSM = 1; + McbspaRegs.PCR.bit.SCLKME = 0; + + // + // Divide-down value for CLKG + // Frame-synchronization pulse width + // + McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; + clkg_delay_loop(); + McbspaRegs.SRGR1.bit.FWID = 1; + + // + // CLKX is driven by the sample rate generator + // Transmit frame synchronization generated by internal + // sample rate generator + // + McbspaRegs.PCR.bit.CLKXM = 1; + McbspaRegs.PCR.bit.FSXM = 1; + + // + // Enable Sample rate generator and + // wait at least 2 CLKG clock cycles + // + McbspaRegs.SPCR2.bit.GRST = 1; + clkg_delay_loop(); + + // + // Release from reset + // RX, TX and frame sync generator + // + McbspaRegs.SPCR2.bit.XRST = 1; + McbspaRegs.SPCR1.bit.RRST = 1; + McbspaRegs.SPCR2.bit.FRST = 1; +} + +// +// InitMcbspaInt - Enable TX and RX interrupts +// +void InitMcbspaInt(void) +{ + // Reset TX and RX + // Enable interrupts for TX and RX + // Release TX and RX + McbspaRegs.SPCR2.bit.XRST = 0; + McbspaRegs.SPCR1.bit.RRST = 0; + McbspaRegs.MFFINT.bit.XINT = 1; + McbspaRegs.MFFINT.bit.RINT = 1; + McbspaRegs.SPCR2.bit.XRST = 1; + McbspaRegs.SPCR1.bit.RRST = 1; +} + +// +// InitMcbspa8bit - McBSP uses an 8-bit word for both TX and RX +// +void InitMcbspa8bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 0; + McbspaRegs.XCR1.bit.XWDLEN1 = 0; +} + +// +// InitMcbspa12bit - McBSP uses an 12-bit word for both TX and RX +// +void InitMcbspa12bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 1; + McbspaRegs.XCR1.bit.XWDLEN1 = 1; +} + +// +// InitMcbspa16bit - McBSP uses an 16-bit word for both TX and RX +// +void InitMcbspa16bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 2; + McbspaRegs.XCR1.bit.XWDLEN1 = 2; +} + +// +// InitMcbspa20bit - McBSP uses an 20-bit word for both TX and RX +// +void InitMcbspa20bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 3; + McbspaRegs.XCR1.bit.XWDLEN1 = 3; +} + +// +// InitMcbspa24bit - McBSP uses an 24-bit word for both TX and RX +// +void InitMcbspa24bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 4; + McbspaRegs.XCR1.bit.XWDLEN1 = 4; +} + +// +// InitMcbspa32bit - McBSP uses an 32-bit word for both TX and RX +// +void InitMcbspa32bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 5; + McbspaRegs.XCR1.bit.XWDLEN1 = 5; +} + +// +// InitMcbspaGpio - Assign GPIO pins to the McBSP peripheral +// (Note: This function must be called from CPU1.) +// +void InitMcbspaGpio(void) +{ +#ifdef CPU1 + EALLOW; + + // + // This specifies which of the possible GPIO pins will be + // McBSPA functional pins. Comment out unwanted connections. + // Set qualification for selected input pins to asynchronous only + // This will select asynchronous (no qualification) for the selected pins. + // + + // + // MDXA + // GPIO20 + // GPIO84 + // + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; + + // + // MDRA + // GPIO21 with asynchronous qualification + // GPIO85 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; + //GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3; + + // + // MCLKXA + // GPIO22 with asynchronous qualification + // GPIO86 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; + //GpioCtrlRegs.GPCQSEL2.bit.GPIO86 = 3; + + // + // MCLKRA + // Select one of the following + // GPIO7 with asynchronous qualification + // GPIO58 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; + //GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; + //GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; + + // + // MFSXA + // GPIO23 with asynchronous qualification + // GPIO87 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; + //GpioCtrlRegs.GPCQSEL2.bit.GPIO87 = 3; + + // + // MFSRA + // Select one of the following + // GPIO5 with asynchronous qualification + // GPIO59 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; + GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; + //GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; + //GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; + + EDIS; +#endif +} + +// +// InitMcbspb - McBSPB initialization routine for examples +// +void InitMcbspb(void) +{ + // + // Reset the McBSP + // Disable all interrupts + // Frame sync generator reset + // Sample rate generator reset + // Transmitter reset + // Receiver reset + // + McbspbRegs.SPCR2.bit.FRST = 0; + McbspbRegs.SPCR2.bit.GRST = 0; + McbspbRegs.SPCR2.bit.XRST = 0; + McbspbRegs.SPCR1.bit.RRST = 0; + + // + // Enable loop back mode + // This does not require external hardware + // + McbspbRegs.SPCR2.all = 0x0000; + McbspbRegs.SPCR1.all = 0x8000; + + // + // RX data delay is 1 bit + // TX data delay is 1 bit + // + McbspbRegs.RCR2.bit.RDATDLY = 1; + McbspbRegs.XCR2.bit.XDATDLY = 1; + + // + // No clock sync for CLKG + // Frame-synchronization period + // + McbspbRegs.SRGR2.bit.GSYNC = 0; + McbspbRegs.SRGR2.bit.FPER = 320; + + // + // Frame-synchronization pulses from + // the sample rate generator + // + McbspbRegs.SRGR2.bit.FSGM = 1; + + // + // Sample rate generator input clock is LSPCLK + // + McbspbRegs.SRGR2.bit.CLKSM = 1; + McbspbRegs.PCR.bit.SCLKME = 0; + + // + // Divide-down value for CLKG + // Frame-synchronization pulse width + // + McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; + clkg_delay_loop(); + McbspbRegs.SRGR1.bit.FWID = 1; + + // + // CLKX is driven by the sample rate generator + // Transmit frame synchronization generated by internal + // sample rate generator + // + McbspbRegs.PCR.bit.CLKXM = 1; + McbspbRegs.PCR.bit.FSXM = 1; + + // + // Enable Sample rate generator and + // wait at least 2 CLKG clock cycles + // + McbspbRegs.SPCR2.bit.GRST = 1; + clkg_delay_loop(); + + // + // Release from reset + // RX, TX and frame sync generator + // + McbspbRegs.SPCR2.bit.XRST = 1; + McbspbRegs.SPCR1.bit.RRST = 1; + McbspbRegs.SPCR2.bit.FRST = 1; +} + +// +// InitMcbspbInt - Enable TX and RX interrupts +// +void InitMcbspbInt(void) +{ + // + // Reset TX and RX + // Enable interrupts for TX and RX + // Release TX and RX + // + McbspbRegs.SPCR2.bit.XRST = 0; + McbspbRegs.SPCR1.bit.RRST = 0; + McbspbRegs.MFFINT.bit.XINT = 1; + McbspbRegs.MFFINT.bit.RINT = 1; + McbspbRegs.SPCR2.bit.XRST = 1; + McbspbRegs.SPCR1.bit.RRST = 1; +} + +// +// InitMcbspb8bit - McBSPB uses an 8-bit word for both TX and RX +// +void InitMcbspb8bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 0; + McbspbRegs.XCR1.bit.XWDLEN1 = 0; +} + +// +// IniMcbspb12bit - McBSPB uses an 12-bit word for both TX and RX +// +void IniMcbspb12bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 1; + McbspbRegs.XCR1.bit.XWDLEN1 = 1; +} + +// +// InitMcbspb16bit - McBSPB uses an 16-bit word for both TX and RX +// +void InitMcbspb16bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 2; + McbspbRegs.XCR1.bit.XWDLEN1 = 2; +} + +// +// InitMcbspb20bit - McBSPB uses an 20-bit word for both TX and RX +// +void InitMcbspb20bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 3; + McbspbRegs.XCR1.bit.XWDLEN1 = 3; +} + +// +// InitMcbspb24bit - McBSPB uses an 24-bit word for both TX and RX +// +void InitMcbspb24bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 4; + McbspbRegs.XCR1.bit.XWDLEN1 = 4; +} + +// +// InitMcbspb32bit - McBSPB uses an 32-bit word for both TX and RX +// +void InitMcbspb32bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 5; + McbspbRegs.XCR1.bit.XWDLEN1 = 5; +} + +// +// InitMcbspbGpio - Assign GPIO pins to the McBSP peripheral +// (Note: This function must be called from CPU1.) +// +void InitMcbspbGpio(void) +{ +#ifdef CPU1 + EALLOW; + + // + // This specifies which of the possible GPIO pins will be + // McBSPB functional pins. Comment out unwanted connections. + // Set qualification for selected input pins to asynchronous only + // This will select asynchronous (no qualification) for the selected pins. + // + + // + // Select one of the following for MDXB + // GPIO24 + // GPIO84 + // + //GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2; + + // + // MDRB + // GPIO13 with asynchronous qualification + // GPIO25 with asynchronous qualification + // GPIO85 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; + //GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 2; + GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3; + + // + // MCLKXB + // GPIO14 with asynchronous qualification + // GPIO26 with asynchronous qualification + // GPIO86 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; + //GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 2; + GpioCtrlRegs.GPCQSEL2.bit.GPIO86= 3; + + // + // MCLKRB + // Select one of the following + // GPIO3 with asynchronous qualification + // GPIO60 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; + GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; + GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; + + // + // MFSXB + // GPIO15 with asynchronous qualification + // GPIO27 with asynchronous qualification + // GPIO87 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; + //GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 2; + GpioCtrlRegs.GPCQSEL2.bit.GPIO87= 3; + + // + // MFSRB + // Select one of the following + // GPIO1 with asynchronous qualification + // GPIO61 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; + GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; + GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; + + EDIS; + +#endif +} + +// +// delay_loop - Delay function (at least 2 SRG cycles) +// Required in McBSP initialization +// +void delay_loop(void) +{ + long i; + for (i = 0; i < MCBSP_INIT_DELAY; i++) {} +} + +// +// clkg_delay_loop - Delay function (at least 2 CLKG cycles) +// Required in McBSP init +// +void clkg_delay_loop(void) +{ + long i; + for (i = 0; i < MCBSP_CLKG_DELAY; i++) {} +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_PieCtrl.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_PieCtrl.c new file mode 100644 index 00000000000..e6be2e920cf --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_PieCtrl.c @@ -0,0 +1,121 @@ +//########################################################################### +// +// FILE: F2837xD_PieCtrl.c +// +// TITLE: F2837xD Device PIE Control Register Initialization Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" // F2837xD Headerfile Include File +#include "F2837xD_Examples.h" // F2837xD Examples Include File + +// +// InitPieCtrl - This function initializes the PIE control registers to a +// known state. +// +void InitPieCtrl(void) +{ + // + // Disable Interrupts at the CPU level: + // + DINT; + + // + // Disable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // + // Clear all PIEIER registers: + // + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // + // Clear all PIEIFR registers: + // + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; +} + +// +// EnableInterrupts - This function enables the PIE module and CPU __interrupts +// +void EnableInterrupts() +{ + // + // Enable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enables PIE to drive a pulse into the CPU + // + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // + // Enable Interrupts at the CPU level + // + EINT; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_PieVect.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_PieVect.c new file mode 100644 index 00000000000..20e8fbf74bd --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_PieVect.c @@ -0,0 +1,320 @@ +//########################################################################### +// +// FILE: F2837xD_PieVect.c +// +// TITLE: F2837xD Device PIE Vector Initialization Functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Globals +// +const struct PIE_VECT_TABLE PieVectTableInit = { + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + TIMER1_ISR, // CPU Timer 1 Interrupt + TIMER2_ISR, // CPU Timer 2 Interrupt + DATALOG_ISR, // Datalogging Interrupt + RTOS_ISR, // RTOS Interrupt + EMU_ISR, // Emulation Interrupt + NMI_ISR, // Non-Maskable Interrupt + ILLEGAL_ISR, // Illegal Operation Trap + USER1_ISR, // User Defined Trap 1 + USER2_ISR, // User Defined Trap 2 + USER3_ISR, // User Defined Trap 3 + USER4_ISR, // User Defined Trap 4 + USER5_ISR, // User Defined Trap 5 + USER6_ISR, // User Defined Trap 6 + USER7_ISR, // User Defined Trap 7 + USER8_ISR, // User Defined Trap 8 + USER9_ISR, // User Defined Trap 9 + USER10_ISR, // User Defined Trap 10 + USER11_ISR, // User Defined Trap 11 + USER12_ISR, // User Defined Trap 12 + ADCA1_ISR, // 1.1 - ADCA Interrupt 1 + ADCB1_ISR, // 1.2 - ADCB Interrupt 1 + ADCC1_ISR, // 1.3 - ADCC Interrupt 1 + XINT1_ISR, // 1.4 - XINT1 Interrupt + XINT2_ISR, // 1.5 - XINT2 Interrupt + ADCD1_ISR, // 1.6 - ADCD Interrupt 1 + TIMER0_ISR, // 1.7 - Timer 0 Interrupt + WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt + EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt + EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt + EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt + EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt + EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt + EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt + EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt + EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt + EPWM1_ISR, // 3.1 - ePWM1 Interrupt + EPWM2_ISR, // 3.2 - ePWM2 Interrupt + EPWM3_ISR, // 3.3 - ePWM3 Interrupt + EPWM4_ISR, // 3.4 - ePWM4 Interrupt + EPWM5_ISR, // 3.5 - ePWM5 Interrupt + EPWM6_ISR, // 3.6 - ePWM6 Interrupt + EPWM7_ISR, // 3.7 - ePWM7 Interrupt + EPWM8_ISR, // 3.8 - ePWM8 Interrupt + ECAP1_ISR, // 4.1 - eCAP1 Interrupt + ECAP2_ISR, // 4.2 - eCAP2 Interrupt + ECAP3_ISR, // 4.3 - eCAP3 Interrupt + ECAP4_ISR, // 4.4 - eCAP4 Interrupt + ECAP5_ISR, // 4.5 - eCAP5 Interrupt + ECAP6_ISR, // 4.6 - eCAP6 Interrupt + PIE_RESERVED_ISR, // 4.7 - Reserved + PIE_RESERVED_ISR, // 4.8 - Reserved + EQEP1_ISR, // 5.1 - eQEP1 Interrupt + EQEP2_ISR, // 5.2 - eQEP2 Interrupt + EQEP3_ISR, // 5.3 - eQEP3 Interrupt + PIE_RESERVED_ISR, // 5.4 - Reserved + PIE_RESERVED_ISR, // 5.5 - Reserved + PIE_RESERVED_ISR, // 5.6 - Reserved + PIE_RESERVED_ISR, // 5.7 - Reserved + PIE_RESERVED_ISR, // 5.8 - Reserved + SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt + SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt + SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt + SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt + MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt + MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt + MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt + MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt + DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt + DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt + DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt + DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt + DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt + DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt + PIE_RESERVED_ISR, // 7.7 - Reserved + PIE_RESERVED_ISR, // 7.8 - Reserved + I2CA_ISR, // 8.1 - I2CA Interrupt 1 + I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 + I2CB_ISR, // 8.3 - I2CB Interrupt 1 + I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 + SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt + SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt + SCID_RX_ISR, // 8.7 - SCID Receive Interrupt + SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt + SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt + SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt + SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt + SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt + CANA0_ISR, // 9.5 - CANA Interrupt 0 + CANA1_ISR, // 9.6 - CANA Interrupt 1 + CANB0_ISR, // 9.7 - CANB Interrupt 0 + CANB1_ISR, // 9.8 - CANB Interrupt 1 + ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt + ADCA2_ISR, // 10.2 - ADCA Interrupt 2 + ADCA3_ISR, // 10.3 - ADCA Interrupt 3 + ADCA4_ISR, // 10.4 - ADCA Interrupt 4 + ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt + ADCB2_ISR, // 10.6 - ADCB Interrupt 2 + ADCB3_ISR, // 10.7 - ADCB Interrupt 3 + ADCB4_ISR, // 10.8 - ADCB Interrupt 4 + CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 + CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 + CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 + CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 + CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 + CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 + CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 + CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 + XINT3_ISR, // 12.1 - XINT3 Interrupt + XINT4_ISR, // 12.2 - XINT4 Interrupt + XINT5_ISR, // 12.3 - XINT5 Interrupt + PIE_RESERVED_ISR, // 12.4 - Reserved + PIE_RESERVED_ISR, // 12.5 - Reserved + VCU_ISR, // 12.6 - VCU Interrupt + FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt + FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt + PIE_RESERVED_ISR, // 1.9 - Reserved + PIE_RESERVED_ISR, // 1.10 - Reserved + PIE_RESERVED_ISR, // 1.11 - Reserved + PIE_RESERVED_ISR, // 1.12 - Reserved + IPC0_ISR, // 1.13 - IPC Interrupt 0 + IPC1_ISR, // 1.14 - IPC Interrupt 1 + IPC2_ISR, // 1.15 - IPC Interrupt 2 + IPC3_ISR, // 1.16 - IPC Interrupt 3 + EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt + EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt + EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt + EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt + PIE_RESERVED_ISR, // 2.13 - Reserved + PIE_RESERVED_ISR, // 2.14 - Reserved + PIE_RESERVED_ISR, // 2.15 - Reserved + PIE_RESERVED_ISR, // 2.16 - Reserved + EPWM9_ISR, // 3.9 - ePWM9 Interrupt + EPWM10_ISR, // 3.10 - ePWM10 Interrupt + EPWM11_ISR, // 3.11 - ePWM11 Interrupt + EPWM12_ISR, // 3.12 - ePWM12 Interrupt + PIE_RESERVED_ISR, // 3.13 - Reserved + PIE_RESERVED_ISR, // 3.14 - Reserved + PIE_RESERVED_ISR, // 3.15 - Reserved + PIE_RESERVED_ISR, // 3.16 - Reserved + PIE_RESERVED_ISR, // 4.9 - Reserved + PIE_RESERVED_ISR, // 4.10 - Reserved + PIE_RESERVED_ISR, // 4.11 - Reserved + PIE_RESERVED_ISR, // 4.12 - Reserved + PIE_RESERVED_ISR, // 4.13 - Reserved + PIE_RESERVED_ISR, // 4.14 - Reserved + PIE_RESERVED_ISR, // 4.15 - Reserved + PIE_RESERVED_ISR, // 4.16 - Reserved + SD1_ISR, // 5.9 - SD1 Interrupt + SD2_ISR, // 5.10 - SD2 Interrupt + PIE_RESERVED_ISR, // 5.11 - Reserved + PIE_RESERVED_ISR, // 5.12 - Reserved + PIE_RESERVED_ISR, // 5.13 - Reserved + PIE_RESERVED_ISR, // 5.14 - Reserved + PIE_RESERVED_ISR, // 5.15 - Reserved + PIE_RESERVED_ISR, // 5.16 - Reserved + SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt + SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt + PIE_RESERVED_ISR, // 6.11 - Reserved + PIE_RESERVED_ISR, // 6.12 - Reserved + PIE_RESERVED_ISR, // 6.13 - Reserved + PIE_RESERVED_ISR, // 6.14 - Reserved + PIE_RESERVED_ISR, // 6.15 - Reserved + PIE_RESERVED_ISR, // 6.16 - Reserved + PIE_RESERVED_ISR, // 7.9 - Reserved + PIE_RESERVED_ISR, // 7.10 - Reserved + PIE_RESERVED_ISR, // 7.11 - Reserved + PIE_RESERVED_ISR, // 7.12 - Reserved + PIE_RESERVED_ISR, // 7.13 - Reserved + PIE_RESERVED_ISR, // 7.14 - Reserved + PIE_RESERVED_ISR, // 7.15 - Reserved + PIE_RESERVED_ISR, // 7.16 - Reserved + PIE_RESERVED_ISR, // 8.9 - Reserved + PIE_RESERVED_ISR, // 8.10 - Reserved + PIE_RESERVED_ISR, // 8.11 - Reserved + PIE_RESERVED_ISR, // 8.12 - Reserved + PIE_RESERVED_ISR, // 8.13 - Reserved + PIE_RESERVED_ISR, // 8.14 - Reserved +#ifdef CPU1 + UPPA_ISR, // 8.15 - uPPA Interrupt + PIE_RESERVED_ISR, // 8.16 - Reserved +#elif defined(CPU2) + PIE_RESERVED_ISR, // 8.15 - Reserved + PIE_RESERVED_ISR, // 8.16 - Reserved +#endif + PIE_RESERVED_ISR, // 9.9 - Reserved + PIE_RESERVED_ISR, // 9.10 - Reserved + PIE_RESERVED_ISR, // 9.11 - Reserved + PIE_RESERVED_ISR, // 9.12 - Reserved + PIE_RESERVED_ISR, // 9.13 - Reserved + PIE_RESERVED_ISR, // 9.14 - Reserved +#ifdef CPU1 + USBA_ISR, // 9.15 - USBA Interrupt +#elif defined(CPU2) + PIE_RESERVED_ISR, // 9.15 - Reserved +#endif + PIE_RESERVED_ISR, // 9.16 - Reserved + ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt + ADCC2_ISR, // 10.10 - ADCC Interrupt 2 + ADCC3_ISR, // 10.11 - ADCC Interrupt 3 + ADCC4_ISR, // 10.12 - ADCC Interrupt 4 + ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt + ADCD2_ISR, // 10.14 - ADCD Interrupt 2 + ADCD3_ISR, // 10.15 - ADCD Interrupt 3 + ADCD4_ISR, // 10.16 - ADCD Interrupt 4 + PIE_RESERVED_ISR, // 11.9 - Reserved + PIE_RESERVED_ISR, // 11.10 - Reserved + PIE_RESERVED_ISR, // 11.11 - Reserved + PIE_RESERVED_ISR, // 11.12 - Reserved + PIE_RESERVED_ISR, // 11.13 - Reserved + PIE_RESERVED_ISR, // 11.14 - Reserved + PIE_RESERVED_ISR, // 11.15 - Reserved + PIE_RESERVED_ISR, // 11.16 - Reserved + EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt + RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt + FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt + RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt + SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt + AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt + CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt + CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a +// known state and must be executed after boot time. +// +void InitPieVectTable(void) +{ + Uint16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + // + // Do not write over first 3 32-bit locations (these locations are + // initialized by Boot ROM with boot variables) + // + Source = Source + 3; + Dest = Dest + 3; + + EALLOW; + for(i = 0; i < 221; i++) + { + *Dest++ = *Source++; + } + EDIS; + + // + // Enable the PIE Vector Table + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_SWPrioritizedPieVect.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_SWPrioritizedPieVect.c new file mode 100644 index 00000000000..7c2b5d1f56b --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_SWPrioritizedPieVect.c @@ -0,0 +1,967 @@ +//########################################################################### +// +// FILE: F2837xD_SWPrioritizedPieVect.c +// +// TITLE: F2837xD Devices SW Prioritized PIE Vector Table Initialization. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#include "F2837xD_SWPrioritizedIsrLevels.h" + +const struct PIE_VECT_TABLE PieVectTableInit = +{ + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + + // + // Non-Peripheral Interrupts: + // + #if (INT13PL != 0) + TIMER1_ISR, // CPU Timer 1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT14PL != 0) + TIMER2_ISR, // CPU Timer 2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT15PL != 0) + DATALOG_ISR, // Datalogging interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT16PL != 0) + RTOS_ISR, // RTOS Interrupt + #else + INT_NOTUSED_ISR, + #endif + + EMU_ISR, // Emulation Interrupt + NMI_ISR, // Non-Maskable Interrupt + ILLEGAL_ISR, // Illegal Operation Trap + USER1_ISR, // User Defined Trap 1 + USER2_ISR, // User Defined Trap 2 + USER3_ISR, // User Defined Trap 3 + USER4_ISR, // User Defined Trap 4 + USER5_ISR, // User Defined Trap 5 + USER6_ISR, // User Defined Trap 6 + USER7_ISR, // User Defined Trap 7 + USER8_ISR, // User Defined Trap 8 + USER9_ISR, // User Defined Trap 9 + USER10_ISR, // User Defined Trap 10 + USER11_ISR, // User Defined Trap 11 + USER12_ISR, // User Defined Trap 12 + + // + // Group 1 PIE Vectors: + // + #if (G1_1PL != 0) + ADCA1_ISR, // 1.1 - ADCA Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_2PL != 0) + ADCB1_ISR, // 1.2 - ADCB Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_3PL != 0) + ADCC1_ISR, // 1.3 - ADCC Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_4PL != 0) + XINT1_ISR, // 1.4 - XINT1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_5PL != 0) + XINT2_ISR, // 1.5 - XINT2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_6PL != 0) + ADCD1_ISR, // 1.6 - ADCD Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_7PL != 0) + TIMER0_ISR, // 1.7 - Timer 0 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_8PL != 0) + WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 2 PIE Vectors: + // + #if (G2_1PL != 0) + EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_2PL != 0) + EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_3PL != 0) + EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_4PL != 0) + EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_5PL != 0) + EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_6PL != 0) + EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_7PL != 0) + EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_8PL != 0) + EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 3 PIE Vectors: + // + #if (G3_1PL != 0) + EPWM1_ISR, // 3.1 - ePWM1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_2PL != 0) + EPWM2_ISR, // 3.2 - ePWM2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_3PL != 0) + EPWM3_ISR, // 3.3 - ePWM3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_4PL != 0) + EPWM4_ISR, // 3.4 - ePWM4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_5PL != 0) + EPWM5_ISR, // 3.5 - ePWM5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_6PL != 0) + EPWM6_ISR, // 3.6 - ePWM6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_7PL != 0) + EPWM7_ISR, // 3.7 - ePWM7 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_8PL != 0) + EPWM8_ISR, // 3.8 - ePWM8 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 4 PIE Vectors: + // + #if (G4_1PL != 0) + ECAP1_ISR, // 4.1 - eCAP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_2PL != 0) + ECAP2_ISR, // 4.2 - eCAP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_3PL != 0) + ECAP3_ISR, // 4.3 - eCAP3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_4PL != 0) + ECAP4_ISR, // 4.4 - eCAP4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_5PL != 0) + ECAP5_ISR, // 4.5 - eCAP5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_6PL != 0) + ECAP6_ISR, // 4.6 - eCAP6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + PIE_RESERVED_ISR, // 4.7 - Reserved + PIE_RESERVED_ISR, // 4.8 - Reserved + + // + // Group 5 PIE Vectors: + // + #if (G5_1PL != 0) + EQEP1_ISR, // 5.1 - eQEP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G5_2PL != 0) + EQEP2_ISR, // 5.2 - eQEP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G5_3PL != 0) + EQEP3_ISR, // 5.3 - eQEP3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + PIE_RESERVED_ISR, // 5.4 - Reserved + PIE_RESERVED_ISR, // 5.5 - Reserved + PIE_RESERVED_ISR, // 5.6 - Reserved + PIE_RESERVED_ISR, // 5.7 - Reserved + PIE_RESERVED_ISR, // 5.8 - Reserved + + // + // Group 6 PIE Vectors: + // + #if (G6_1PL != 0) + SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_2PL != 0) + SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_3PL != 0) + SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_4PL != 0) + SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_5PL != 0) + MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_6PL != 0) + MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_7PL != 0) + MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_8PL != 0) + MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 7 PIE Vectors: + // + #if (G7_1PL != 0) + DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_2PL != 0) + DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_3PL != 0) + DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_4PL != 0) + DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_5PL != 0) + DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_6PL != 0) + DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + PIE_RESERVED_ISR, // 7.7 - Reserved + PIE_RESERVED_ISR, // 7.8 - Reserved + + // + // Group 8 PIE Vectors: + // + #if (G8_1PL != 0) + I2CA_ISR, // 8.1 - I2CA Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_2PL != 0) + I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_3PL != 0) + I2CB_ISR, // 8.3 - I2CB Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_4PL != 0) + I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_5PL != 0) + SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_6PL != 0) + SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_7PL != 0) + SCID_RX_ISR, // 8.7 - SCID Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_8PL != 0) + SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 9 PIE Vectors: + // + #if (G9_1PL != 0) + SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_2PL != 0) + SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_3PL != 0) + SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_4PL != 0) + SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_5PL != 0) + CANA0_ISR, // 9.5 - CANA Interrupt 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_6PL != 0) + CANA1_ISR, // 9.6 - CANA Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_7PL != 0) + CANB0_ISR, // 9.7 - CANB Interrupt 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_8PL != 0) + CANB1_ISR, // 9.8 - CANB Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 10 PIE Vectors + // + #if (G10_1PL != 0) + ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_2PL != 0) + ADCA2_ISR, // 10.2 - ADCA Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_3PL != 0) + ADCA3_ISR, // 10.3 - ADCA Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_4PL != 0) + ADCA4_ISR, // 10.4 - ADCA Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_5PL != 0) + ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_6PL != 0) + ADCB2_ISR, // 10.6 - ADCB Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_7PL != 0) + ADCB3_ISR, // 10.7 - ADCB Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_8PL != 0) + ADCB4_ISR, // 10.8 - ADCB Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 11 PIE Vectors + // + #if (G11_1PL != 0) + CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_2PL != 0) + CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_3PL != 0) + CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_4PL != 0) + CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_5PL != 0) + CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_6PL != 0) + CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_7PL != 0) + CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_8PL != 0) + CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 12 PIE Vectors + // + #if (G12_1PL != 0) + XINT3_ISR, // 12.1 - XINT3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_2PL != 0) + XINT4_ISR, // 12.2 - XINT4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_3PL != 0) + XINT5_ISR, // 12.3 - XINT5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 12.4 - Reserved + PIE_RESERVED_ISR, // 12.5 - Reserved + + #if (G12_6PL != 0) + VCU_ISR, // 12.6 - VCU Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_7PL != 0) + FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_8PL != 0) + FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 1.9 - Reserved + PIE_RESERVED_ISR, // 1.10 - Reserved + PIE_RESERVED_ISR, // 1.11 - Reserved + PIE_RESERVED_ISR, // 1.12 - Reserved + + #if (G1_13PL != 0) + IPC0_ISR, // 1.13 - IPC Interrupt 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_14PL != 0) + IPC1_ISR, // 1.14 - IPC Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_15PL != 0) + IPC2_ISR, // 1.15 - IPC Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_16PL != 0) + IPC3_ISR, // 1.16 - IPC Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_9PL != 0) + EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_10PL != 0) + EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_11PL != 0) + EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_12PL != 0) + EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 2.13 - Reserved + PIE_RESERVED_ISR, // 2.14 - Reserved + PIE_RESERVED_ISR, // 2.15 - Reserved + PIE_RESERVED_ISR, // 2.16 - Reserved + + #if (G3_9PL != 0) + EPWM9_ISR, // 3.9 - ePWM9 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_10PL != 0) + EPWM10_ISR, // 3.10 - ePWM10 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_11PL != 0) + EPWM11_ISR, // 3.11 - ePWM11 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_12PL != 0) + EPWM12_ISR, // 3.12 - ePWM12 Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 3.13 - Reserved + PIE_RESERVED_ISR, // 3.14 - Reserved + PIE_RESERVED_ISR, // 3.15 - Reserved + PIE_RESERVED_ISR, // 3.16 - Reserved + PIE_RESERVED_ISR, // 4.9 - Reserved + PIE_RESERVED_ISR, // 4.10 - Reserved + PIE_RESERVED_ISR, // 4.11 - Reserved + PIE_RESERVED_ISR, // 4.12 - Reserved + PIE_RESERVED_ISR, // 4.13 - Reserved + PIE_RESERVED_ISR, // 4.14 - Reserved + PIE_RESERVED_ISR, // 4.15 - Reserved + PIE_RESERVED_ISR, // 4.16 - Reserved + + #if (G5_9PL != 0) + SD1_ISR, // 5.9 - SD1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G5_10PL != 0) + SD2_ISR, // 5.10 - SD2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 5.11 - Reserved + PIE_RESERVED_ISR, // 5.12 - Reserved + PIE_RESERVED_ISR, // 5.13 - Reserved + PIE_RESERVED_ISR, // 5.14 - Reserved + PIE_RESERVED_ISR, // 5.15 - Reserved + PIE_RESERVED_ISR, // 5.16 - Reserved + + #if (G6_9PL != 0) + SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_10PL != 0) + SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 6.11 - Reserved + PIE_RESERVED_ISR, // 6.12 - Reserved + PIE_RESERVED_ISR, // 6.13 - Reserved + PIE_RESERVED_ISR, // 6.14 - Reserved + PIE_RESERVED_ISR, // 6.15 - Reserved + PIE_RESERVED_ISR, // 6.16 - Reserved + PIE_RESERVED_ISR, // 7.9 - Reserved + PIE_RESERVED_ISR, // 7.10 - Reserved + PIE_RESERVED_ISR, // 7.11 - Reserved + PIE_RESERVED_ISR, // 7.12 - Reserved + PIE_RESERVED_ISR, // 7.13 - Reserved + PIE_RESERVED_ISR, // 7.14 - Reserved + PIE_RESERVED_ISR, // 7.15 - Reserved + PIE_RESERVED_ISR, // 7.16 - Reserved + PIE_RESERVED_ISR, // 8.9 - Reserved + PIE_RESERVED_ISR, // 8.10 - Reserved + PIE_RESERVED_ISR, // 8.11 - Reserved + PIE_RESERVED_ISR, // 8.12 - Reserved + PIE_RESERVED_ISR, // 8.13 - Reserved + PIE_RESERVED_ISR, // 8.14 - Reserved +#ifdef CPU1 + + #if (G8_15PL != 0) + UPPA_ISR, // 8.15 - uPPA Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 8.16 - Reserved +#elif defined(CPU2) + PIE_RESERVED_ISR, // 8.15 - Reserved + PIE_RESERVED_ISR, // 8.16 - Reserved +#endif + PIE_RESERVED_ISR, // 9.9 - Reserved + PIE_RESERVED_ISR, // 9.10 - Reserved + PIE_RESERVED_ISR, // 9.11 - Reserved + PIE_RESERVED_ISR, // 9.12 - Reserved + PIE_RESERVED_ISR, // 9.13 - Reserved + PIE_RESERVED_ISR, // 9.14 - Reserved +#ifdef CPU1 + + #if (G9_15PL != 0) + USBA_ISR, // 9.15 - USBA Interrupt + #else + INT_NOTUSED_ISR, + #endif +#elif defined(CPU2) + PIE_RESERVED_ISR, // 9.15 - Reserved +#endif + PIE_RESERVED_ISR, // 9.16 - Reserved + + #if (G10_9PL != 0) + ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_10PL != 0) + ADCC2_ISR, // 10.10 - ADCC Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_11PL != 0) + ADCC3_ISR, // 10.11 - ADCC Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_12PL != 0) + ADCC4_ISR, // 10.12 - ADCC Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_13PL != 0) + ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_14PL != 0) + ADCD2_ISR, // 10.14 - ADCD Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_15PL != 0) + ADCD3_ISR, // 10.15 - ADCD Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_16PL != 0) + ADCD4_ISR, // 10.16 - ADCD Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 11.9 - Reserved + PIE_RESERVED_ISR, // 11.10 - Reserved + PIE_RESERVED_ISR, // 11.11 - Reserved + PIE_RESERVED_ISR, // 11.12 - Reserved + PIE_RESERVED_ISR, // 11.13 - Reserved + PIE_RESERVED_ISR, // 11.14 - Reserved + PIE_RESERVED_ISR, // 11.15 - Reserved + PIE_RESERVED_ISR, // 11.16 - Reserved + + #if (G12_9PL != 0) + EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_10PL != 0) + RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_11PL != 0) + FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_12PL != 0) + RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_13PL != 0) + SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_14PL != 0) + AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_15PL != 0) + CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_16PL != 0) + CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a known +// state. This function must be executed after boot time. +// +void +InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 221; i++) + { + *Dest++ = *Source++; + } + EDIS; +} + +// +// End of File +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Sci.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Sci.c new file mode 100644 index 00000000000..e21b934a5e3 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Sci.c @@ -0,0 +1,48 @@ +//########################################################################### +// +// FILE: F2837xD_Sci.c +// +// TITLE: F2837xD SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "F2837xD_device.h" // F2837xD Headerfile Include File +#include "F2837xD_Examples.h" // F2837xD Examples Include File + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Spi.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Spi.c new file mode 100644 index 00000000000..1a82751d7e0 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Spi.c @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: F2837xD_Spi.c +// +// TITLE: F2837xD SPI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Calculate BRR: 7-bit baud rate register value +// SPI CLK freq = 500 kHz +// LSPCLK freq = CPU freq / 4 (by default) +// BRR = (LSPCLK freq / SPI CLK freq) - 1 +// +#if CPU_FRQ_200MHZ +#define SPI_BRR ((200E6 / 4) / 500E3) - 1 +#endif + +#if CPU_FRQ_150MHZ +#define SPI_BRR ((150E6 / 4) / 500E3) - 1 +#endif + +#if CPU_FRQ_120MHZ +#define SPI_BRR ((120E6 / 4) / 500E3) - 1 +#endif + +// +// InitSPI - This function initializes the SPI to a known state +// +void InitSpi(void) +{ + // Initialize SPI-A + + // Set reset low before configuration changes + // Clock polarity (0 == rising, 1 == falling) + // 16-bit character + // Enable loop-back + SpiaRegs.SPICCR.bit.SPISWRESET = 0; + SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; + SpiaRegs.SPICCR.bit.SPICHAR = (16-1); + SpiaRegs.SPICCR.bit.SPILBK = 1; + + // Enable master (0 == slave, 1 == master) + // Enable transmission (Talk) + // Clock phase (0 == normal, 1 == delayed) + // SPI interrupts are disabled + SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; + SpiaRegs.SPICTL.bit.TALK = 1; + SpiaRegs.SPICTL.bit.CLK_PHASE = 0; + SpiaRegs.SPICTL.bit.SPIINTENA = 0; + + // Set the baud rate + SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR; + + // Set FREE bit + // Halting on a breakpoint will not halt the SPI + SpiaRegs.SPIPRI.bit.FREE = 1; + + // Release the SPI from reset + SpiaRegs.SPICCR.bit.SPISWRESET = 1; +} + +// +// InitSpiGpio - This function initializes GPIO pins to function as SPI pins. +// Each GPIO pin can be configured as a GPIO pin or up to 3 +// different peripheral functional pins. By default all pins come +// up as GPIO inputs after reset. +// +// Caution: +// For each SPI peripheral +// Only one GPIO pin should be enabled for SPISOMO operation. +// Only one GPIO pin should be enabled for SPISOMI operation. +// Only one GPIO pin should be enabled for SPICLK operation. +// Only one GPIO pin should be enabled for SPISTE operation. +// Comment out other unwanted lines. +// +void InitSpiGpio() +{ + InitSpiaGpio(); +} + +// +// InitSpiaGpio - Initialize SPIA GPIOs +// +void InitSpiaGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) +// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (SPISIMOA) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) +// GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (SPISOMIA) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) + + // + // Set qualification for selected pins to asynch only + // + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (SPISIMOA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (SPISOMIA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) + + // + //Configure SPI-A pins using GPIO regs + // + // This specifies which of the possible GPIO pins will be SPI functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA +// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // Configure GPIO5 as SPISIMOA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA +// GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as SPISOMIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA + + EDIS; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_SysCtrl.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_SysCtrl.c new file mode 100644 index 00000000000..0971cee2d56 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_SysCtrl.c @@ -0,0 +1,1276 @@ +//########################################################################### +// +// FILE: F2837xD_SysCtrl.c +// +// TITLE: F2837xD Device System Control Initialization & Support Functions. +// +// DESCRIPTION: +// +// Example initialization of system resources. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#ifdef __cplusplus +using std::memcpy; +#endif + +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 +#define TMR1SYSCLKCTR 0xF0000000 +#define TMR2INPCLKCTR 0x800 + +// +// Functions that will be run from RAM need to be assigned to a different +// section. This section will then be mapped to a load and run address using +// the linker cmd file. +// +// *IMPORTANT* +// +// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM +// FLASH TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM +// THROWING AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE. +// +#ifndef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); + #pragma CODE_SECTION(FlashOff, ".TI.ramfunc"); + #else + #pragma CODE_SECTION(InitFlash, "ramfuncs"); + #pragma CODE_SECTION(FlashOff, "ramfuncs"); + #endif + #endif +#endif + +// +// InitSysCtrl - Initialization of system resources. +// +void InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + +#ifdef _FLASH + // + // Copy time critical code and Flash setup code to RAM. This includes the + // following functions: InitFlash() + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart + // symbols are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + InitFlash(); +#endif + + // + // *IMPORTANT* + // + // The Device_cal function, which copies the ADC & oscillator calibration + // values from TI reserved OTP into the appropriate trim registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC and + // oscillators to function according to specification. The clocks to the + // ADC MUST be enabled before calling this function. + // + // See the device data manual and/or the ADC Reference Manual for more + // information. + // +#ifdef CPU1 + EALLOW; + + // + // Enable pull-ups on unbonded IOs as soon as possible to reduce power + // consumption. + // + GPIO_EnableUnbondedIOPullups(); + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + // + // Check if device is trimmed + // + if(*((Uint16 *)0x5D1B6) == 0x0000){ + // + // Device is not trimmed--apply static calibration values + // + AnalogSubsysRegs.ANAREFTRIMA.all = 31709; + AnalogSubsysRegs.ANAREFTRIMB.all = 31709; + AnalogSubsysRegs.ANAREFTRIMC.all = 31709; + AnalogSubsysRegs.ANAREFTRIMD.all = 31709; + } + + CpuSysRegs.PCLKCR13.bit.ADC_A = 0; + CpuSysRegs.PCLKCR13.bit.ADC_B = 0; + CpuSysRegs.PCLKCR13.bit.ADC_C = 0; + CpuSysRegs.PCLKCR13.bit.ADC_D = 0; + EDIS; + + // + // Initialize the PLL control: SYSPLLMULT and SYSCLKDIVSEL. + // + // Defined options to be passed as arguments to this function are defined + // in F2837xD_Examples.h. + // + // Note: The internal oscillator CANNOT be used as the PLL source if the + // PLLSYSCLK is configured to frequencies above 194 MHz. + // + // PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV) + // +#ifdef _LAUNCHXL_F28379D + InitSysPll(XTAL_OSC,IMULT_40,FMULT_0,PLLCLK_BY_2); +#else + InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2); +#endif // _LAUNCHXL_F28379D + +#endif // CPU1 + + // + // Turn on all peripherals + // + InitPeripheralClocks(); +} + +// +// InitPeripheralClocks - Initializes the clocks for the peripherals. +// +// Note: In order to reduce power consumption, turn off the clocks to any +// peripheral that is not specified for your part-number or is not used in the +// application +// +void InitPeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.bit.CLA1 = 1; + CpuSysRegs.PCLKCR0.bit.DMA = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR0.bit.HRPWM = 1; +#endif + + CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR1.bit.EMIF1 = 1; + CpuSysRegs.PCLKCR1.bit.EMIF2 = 1; +#endif + + CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM4 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM5 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM6 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM7 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM8 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM9 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM10 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM11 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM12 = 1; + + CpuSysRegs.PCLKCR3.bit.ECAP1 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP2 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP3 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP4 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP5 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP6 = 1; + + CpuSysRegs.PCLKCR4.bit.EQEP1 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP2 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP3 = 1; + + CpuSysRegs.PCLKCR6.bit.SD1 = 1; + CpuSysRegs.PCLKCR6.bit.SD2 = 1; + + CpuSysRegs.PCLKCR7.bit.SCI_A = 1; + CpuSysRegs.PCLKCR7.bit.SCI_B = 1; + CpuSysRegs.PCLKCR7.bit.SCI_C = 1; + CpuSysRegs.PCLKCR7.bit.SCI_D = 1; + + CpuSysRegs.PCLKCR8.bit.SPI_A = 1; + CpuSysRegs.PCLKCR8.bit.SPI_B = 1; + CpuSysRegs.PCLKCR8.bit.SPI_C = 1; + + CpuSysRegs.PCLKCR9.bit.I2C_A = 1; + CpuSysRegs.PCLKCR9.bit.I2C_B = 1; + + CpuSysRegs.PCLKCR10.bit.CAN_A = 1; + CpuSysRegs.PCLKCR10.bit.CAN_B = 1; + + CpuSysRegs.PCLKCR11.bit.McBSP_A = 1; + CpuSysRegs.PCLKCR11.bit.McBSP_B = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR11.bit.USB_A = 1; + + CpuSysRegs.PCLKCR12.bit.uPP_A = 1; +#endif + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS8 = 1; + + CpuSysRegs.PCLKCR16.bit.DAC_A = 1; + CpuSysRegs.PCLKCR16.bit.DAC_B = 1; + CpuSysRegs.PCLKCR16.bit.DAC_C = 1; + + EDIS; +} + +// +// DisablePeripheralClocks - Gates-off all peripheral clocks. +// +void DisablePeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.all = 0; + CpuSysRegs.PCLKCR1.all = 0; + CpuSysRegs.PCLKCR2.all = 0; + CpuSysRegs.PCLKCR3.all = 0; + CpuSysRegs.PCLKCR4.all = 0; + CpuSysRegs.PCLKCR6.all = 0; + CpuSysRegs.PCLKCR7.all = 0; + CpuSysRegs.PCLKCR8.all = 0; + CpuSysRegs.PCLKCR9.all = 0; + CpuSysRegs.PCLKCR10.all = 0; + CpuSysRegs.PCLKCR11.all = 0; + CpuSysRegs.PCLKCR12.all = 0; + CpuSysRegs.PCLKCR13.all = 0; + CpuSysRegs.PCLKCR14.all = 0; + CpuSysRegs.PCLKCR16.all = 0; + + EDIS; +} + +// +// InitFlash - This function initializes the Flash Control registers. +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. +// +#ifdef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(".TI.ramfunc"); + #else + #pragma CODE_SECTION("ramfuncs"); + #endif + #endif +#endif +void InitFlash(void) +{ + EALLOW; + + // + // The default value of VREADST is good enough for the flash to power up + // properly at the INTOSC frequency. Below VREADST configuration covers up + // to the max frequency possible for this device. This is required for + // proper flash wake up at the higher frequencies if users put it to sleep + // for power saving reason. + // + Flash0CtrlRegs.FBAC.bit.VREADST = 0x14; + + // + // At reset bank and pump are in sleep. A Flash access will power up the + // bank and pump automatically. + // + // After a Flash access, bank and pump go to low power mode (configurable + // in FBFALLBACK/FPAC1 registers) if there is no further access to flash. + // + // Power up Flash bank and pump. This also sets the fall back mode of + // flash and pump as active. + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1; + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3; + + // + // Disable Cache and prefetch mechanism before changing wait states + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0; + + // + // Set waitstates according to frequency + // + // *CAUTION* + // Minimum waitstates required for the flash operating at a given CPU rate + // must be characterized by TI. Refer to the datasheet for the latest + // information. + // + #if CPU_FRQ_200MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3; + #endif + + #if CPU_FRQ_150MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + #if CPU_FRQ_120MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + // + // Enable Cache and prefetch mechanism to improve performance of code + // executed from Flash. + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1; + + // + // At reset, ECC is enabled. If it is disabled by application software and + // if application again wants to enable ECC. + // + Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA; + + EDIS; + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + __asm(" RPT #7 || NOP"); +} + +// +// FlashOff - This function powers down the flash +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. Also you must seize the flash pump in +// order to power it down. +// +#ifdef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(".TI.ramfunc"); + #else + #pragma CODE_SECTION("ramfuncs"); + #endif + #endif +#endif +void FlashOff(void) +{ + EALLOW; + + // + // Set VREADST to the proper value for the flash banks to power up properly + // + Flash0CtrlRegs.FBAC.bit.VREADST = 0x14; + + // + // Power down bank + // + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0; + + // + // Power down pump + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0; + + EDIS; +} + +// +// SeizeFlashPump - Wait until the flash pump is available. Then take control +// of it using the flash pump Semaphore. +// +void SeizeFlashPump(void) +{ + EALLOW; + #ifdef CPU1 + while (FlashPumpSemaphoreRegs.PUMPREQUEST.bit.PUMP_OWNERSHIP != 0x2) + { + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x2; + } + #elif defined(CPU2) + while (FlashPumpSemaphoreRegs.PUMPREQUEST.bit.PUMP_OWNERSHIP != 0x1) + { + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x1; + } + #endif + EDIS; +} + +// +// ReleaseFlashPump - Release control of the flash pump using the flash pump +// semaphore. +// +void ReleaseFlashPump(void) +{ + EALLOW; + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x0; + EDIS; +} + +// +// ServiceDog - This function resets the watchdog timer. +// +// Enable this function for using ServiceDog in the application. +// +void ServiceDog(void) +{ + EALLOW; + WdRegs.WDKEY.bit.WDKEY = 0x0055; + WdRegs.WDKEY.bit.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void DisableDog(void) +{ + volatile Uint16 temp; + + // + // Grab the clock config first so we don't clobber it + // + EALLOW; + temp = WdRegs.WDCR.all & 0x0007; + WdRegs.WDCR.all = 0x0068 | temp; + EDIS; +} + +#ifdef CPU1 +// +// InitSysPll() +// This function initializes the PLL registers. +// Note: +// - The internal oscillator CANNOT be used as the PLL source if the +// PLLSYSCLK is configured to frequencies above 194 MHz. +// +// - This function uses the Watchdog as a monitor for the PLL. The user +// watchdog settings will be modified and restored upon completion. Function +// allows for a minimum re lock attempt for 5 tries. Re lock attempt is carried +// out if either SLIP condition occurs or SYSCLK to Input Clock ratio is off by 10% +// +// - This function uses the following resources to support PLL initialization: +// o Watchdog +// o CPU Timer 1 +// o CPU Timer 2 +// +void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) +{ + Uint16 SCSR, WDCR, WDWCR, intStatus, t1TCR, t1TPR, t1TPRH; + Uint16 t2TCR, t2TPR, t2TPRH, t2SRC, t2Prescale; + Uint32 t1PRD, t2PRD, ctr1; + float sysclkToInClkError, mult, div; + bool sysclkInvalidFreq=true; + + if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && + (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && + (fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) && + (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) + { + switch (clock_source) + { + case INT_OSC1: + SysIntOsc1Sel(); + break; + + case INT_OSC2: + SysIntOsc2Sel(); + break; + + case XTAL_OSC: + SysXtalOscSel(); + break; + } + } + + EALLOW; + if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || + fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT) + { + Uint16 i; + + // + // This bit is reset only by POR + // + if(DevCfgRegs.SYSDBGCTL.bit.BIT_0 == 1) + { + // + // The user can optionally insert handler code here. This will only + // be executed if a watchdog reset occurred after a failed system + // PLL initialization. See your device user's guide for more + // information. + // + // If the application has a watchdog reset handler, this bit should + // be checked to determine if the watchdog reset occurred because + // of the PLL. + // + // No action here will continue with retrying the PLL as normal. + // + // Failed PLL initialization is due to any of the following: + // - No PLL clock + // - SLIP condition + // - Wrong Frequency + // + } + + // + // Bypass PLL and set dividers to /1 + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + asm(" RPT #20 || NOP"); + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; + + // + // Lock the PLL five times. This helps ensure a successful start. + // Five is the minimum recommended number. The user can increase this + // number according to allotted system initialization time. + // + for(i = 0; i < 5; i++) + { + // + // Turn off PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Write multiplier, which automatically turns on the PLL + // + ClkCfgRegs.SYSPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the SYSPLL lock counter + // + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) + { + // + // Uncomment to service the watchdog + // + // ServiceDog(); + } + } + } + + // + // Set divider to produce slower output frequency to limit current increase + // + if(divsel != PLLCLK_BY_126) + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; + } + else + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + } + + // + // *CAUTION* + // It is recommended to use the following watchdog code to monitor the PLL + // startup sequence. If your application has already cleared the watchdog + // SCRS[WDOVERRIDE] bit this cannot be done. It is recommended not to clear + // this bit until after the PLL has been initiated. + // + + // + // Backup User Watchdog + // + SCSR = WdRegs.SCSR.all; + WDCR = WdRegs.WDCR.all; + WDWCR = WdRegs.WDWCR.all; + + // + // Disable windowed functionality, reset counter + // + EALLOW; + WdRegs.WDWCR.all = 0x0; + WdRegs.WDKEY.bit.WDKEY = 0x55; + WdRegs.WDKEY.bit.WDKEY = 0xAA; + + // + // Disable global interrupts + // + intStatus = __disable_interrupts(); + + // + // Configure for watchdog reset and to run at max frequency + // + WdRegs.SCSR.all = 0x0; + WdRegs.WDCR.all = 0x28; + + // + // This bit is reset only by power-on-reset (POR) and will not be cleared + // by a WD reset + // + DevCfgRegs.SYSDBGCTL.bit.BIT_0 = 1; + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // + // Delay to ensure system is clocking from PLL prior to clearing status bit + // + asm(" RPT #20 || NOP"); + + // + // Service watchdog + // + ServiceDog(); + + // + // Slip Bit Monitor and SYSCLK Frequency Check using timers + // Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer counts + // are off by +/- 10%. + // At a minimum, SYSCLK check is performed. Re lock attempt is carried out + // if SLIPS bit is set. This while loop is monitored by watchdog. + // In the event that the PLL does not successfully lock, the loop will be + // aborted by watchdog reset. + // + EALLOW; + while(sysclkInvalidFreq == true) + { + if(ClkCfgRegs.SYSPLLSTS.bit.SLIPS == 1) + { + // + // Bypass PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + asm(" RPT #20 || NOP"); + + // + // Turn off PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Write multipliers, which automatically turns on the PLL + // + ClkCfgRegs.SYSPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the SYSPLL lock counter to expire + // + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1); + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // + // Delay to ensure system is clocking from PLL + // + asm(" RPT #20 || NOP"); + } + + // + // Backup timer1 and timer2 settings + // + t1TCR = CpuTimer1Regs.TCR.all; + t1PRD = CpuTimer1Regs.PRD.all; + t1TPR = CpuTimer1Regs.TPR.all; + t1TPRH = CpuTimer1Regs.TPRH.all; + t2SRC = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL; + t2Prescale = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE; + t2TCR = CpuTimer2Regs.TCR.all; + t2PRD = CpuTimer2Regs.PRD.all; + t2TPR = CpuTimer2Regs.TPR.all; + t2TPRH = CpuTimer2Regs.TPRH.all; + + // + // Set up timers 1 and 2 + // Configure timer1 to count SYSCLK cycles + // + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer1Regs.PRD.all = TMR1SYSCLKCTR; // seed timer1 counter + CpuTimer1Regs.TPR.bit.TDDR = 0x0; // sysclock divider + CpuTimer1Regs.TCR.bit.TRB = 1; // reload timer with value in PRD + CpuTimer1Regs.TCR.bit.TIF = 1; // clear interrupt flag + CpuTimer1Regs.TCR.bit.TIE = 1; // enable interrupt + + // + // Configure timer2 to count Input clock cycles + // + switch(clock_source) + { + case INT_OSC1: + // Clk Src = INT_OSC1 + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x1; + break; + case INT_OSC2: + // Clk Src = INT_OSC2 + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x2; + break; + case XTAL_OSC: + // Clk Src = XTAL + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x3; + break; + + } + CpuTimer2Regs.TCR.bit.TIF = 1; // clear interrupt flag + CpuTimer2Regs.TCR.bit.TIE = 1; // enable interrupt + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + CpuTimer2Regs.PRD.all = TMR2INPCLKCTR; // seed timer2 counter + CpuTimer2Regs.TPR.bit.TDDR = 0x0; // sysclock divider + CpuTimer2Regs.TCR.bit.TRB = 1; // reload timer with value in PRD + + // + // Stop/Start timer counters + // + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + CpuTimer1Regs.TCR.bit.TRB = 1; // reload timer1 with value in PRD + CpuTimer2Regs.TCR.bit.TRB = 1; // reload timer2 with value in PRD + CpuTimer2Regs.TCR.bit.TIF = 1; // clear timer2 interrupt flag + CpuTimer2Regs.TCR.bit.TSS = 0; // start timer2 + CpuTimer1Regs.TCR.bit.TSS = 0; // start timer1 + + // + // Stop timers if either timer1 or timer2 counters overflow + // + while((CpuTimer2Regs.TCR.bit.TIF == 0) && (CpuTimer1Regs.TCR.bit.TIF == 0)); + + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + + // + // Calculate elapsed counts on timer1 + // + ctr1 = TMR1SYSCLKCTR - CpuTimer1Regs.TIM.all; + + // + // Restore timer settings + // + CpuTimer1Regs.TCR.all = t1TCR; + CpuTimer1Regs.PRD.all = t1PRD; + CpuTimer1Regs.TPR.all = t1TPR; + CpuTimer1Regs.TPRH.all = t1TPRH; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale; + CpuTimer2Regs.TCR.all = t2TCR; + CpuTimer2Regs.PRD.all = t2PRD; + CpuTimer2Regs.TPR.all = t2TPR; + CpuTimer2Regs.TPRH.all = t2TPRH; + + // + // Calculate Clock Error: + // Error = (mult/div) - (timer1 count/timer2 count) + // + mult = (float)(imult) + (float)(fmult)/4; + div = (float)((!ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV) ? 1 : (ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV << 1)); + + sysclkToInClkError = (mult/div) - ((float)ctr1/(float)TMR2INPCLKCTR); + + // + // sysclkInvalidFreq will be set to true if sysclkToInClkError is off by 10% + // + sysclkInvalidFreq = ((sysclkToInClkError > 0.10) || (sysclkToInClkError < -0.10)); + } + + // + // Clear bit + // + DevCfgRegs.SYSDBGCTL.bit.BIT_0 = 0; + + // + // Restore user watchdog, first resetting counter + // + WdRegs.WDKEY.bit.WDKEY = 0x55; + WdRegs.WDKEY.bit.WDKEY = 0xAA; + + WDCR |= 0x28; // Setup WD key--KEY bits always read 0 + WdRegs.WDCR.all = WDCR; + WdRegs.WDWCR.all = WDWCR; + WdRegs.SCSR.all = SCSR & 0xFFFE; // Mask write to bit 0 (W1toClr) + + // + // Restore state of ST1[INTM]. This was set by the __disable_interrupts() + // intrinsic previously. + // + if(!(intStatus & 0x1)) + { + EINT; + } + + // + // Restore state of ST1[DBGM]. This was set by the __disable_interrupts() + // intrinsic previously. + // + if(!(intStatus & 0x2)) + { + asm(" CLRC DBGM"); + } + + // + // 200 PLLSYSCLK delay to allow voltage regulator to stabilize prior + // to increasing entire system clock frequency. + // + asm(" RPT #200 || NOP"); + + // + // Set the divider to user value + // + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + + EDIS; +} +#endif // CPU1 + +// +// InitAuxPll - This function initializes the AUXPLL registers. +// +// Note: For this function to properly detect PLL startup, +// SYSCLK >= 2*AUXPLLCLK after the AUXPLL is selected as the clocking source. +// +// This function will use CPU Timer 2 to monitor a successful lock of the +// AUXPLL. +// +void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) +{ + Uint16 i; + Uint16 counter = 0; + Uint16 started = 0; + Uint16 t2TCR, t2TPR, t2TPRH, t2SRC, t2Prescale, attempts; + Uint32 t2PRD; + + if((clock_source == ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL) && + (imult == ClkCfgRegs.AUXPLLMULT.bit.IMULT) && + (fmult == ClkCfgRegs.AUXPLLMULT.bit.FMULT) && + (divsel == ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + switch (clock_source) + { + case INT_OSC2: + AuxIntOsc2Sel(); + break; + + case XTAL_OSC: + AuxXtalOscSel(); + break; + + case AUXCLKIN: + AuxAuxClkSel(); + break; + } + + // + // Backup Timer 2 settings + // + t2SRC = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL; + t2Prescale = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE; + t2TCR = CpuTimer2Regs.TCR.all; + t2PRD = CpuTimer2Regs.PRD.all; + t2TPR = CpuTimer2Regs.TPR.all; + t2TPRH = CpuTimer2Regs.TPRH.all; + + // + // Configure Timer 2 for AUXPLL as source in known configuration + // + EALLOW; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x6; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = 0x0; // Divide by 1 + + CpuTimer2Regs.TCR.bit.TSS = 1; // Stop timer + CpuTimer2Regs.PRD.all = 10; // Small PRD value to detect overflow + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + CpuTimer2Regs.TCR.bit.TIE = 0; // Disable timer interrupts + + // + // Set AUX Divide by 8 to ensure that AUXPLLCLK <= SYSCLK/2 while using + // Timer 2 + // + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = 0x3; + EDIS; + + while((counter < 5) && (started == 0)) + { + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; // Turn off AUXPLL + asm(" RPT #20 || NOP"); // Small delay for power down + + // + // Set integer and fractional multiplier, which automatically turns on + // the PLL + // + ClkCfgRegs.AUXPLLMULT.all = ((fmult << 8U) | imult); + + // + // Enable AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1; + EDIS; + + // + // Wait for the AUXPLL lock counter + // + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) + { + // + // Uncomment to service the watchdog + // + // ServiceDog(); + } + + // + // Enable AUXPLLCLK to be fed from AUX PLL + // + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + asm(" RPT #20 || NOP"); + + // + // CPU Timer 2 will now be setup to be clocked from AUXPLLCLK. This is + // used to test that the PLL has successfully started. + // + CpuTimer2Regs.TCR.bit.TRB = 1; // Reload period value + CpuTimer2Regs.TCR.bit.TSS = 0; // Start Timer + + // + // Check to see timer is counting properly + // + for(i = 0; i < 1000; i++) + { + // + // Check overflow flag + // + if(CpuTimer2Regs.TCR.bit.TIF) + { + // + // Clear overflow flag + // + CpuTimer2Regs.TCR.bit.TIF = 1; + + // + // Set flag to indicate PLL started and break out of for-loop + // + started = 1; + break; + } + } + + // + // Stop timer + // + CpuTimer2Regs.TCR.bit.TSS = 1; + counter++; + EDIS; + } + + if(started == 0) + { + // + // AUX PLL may not have started. Reset multiplier to 0 (bypass PLL). + // + EALLOW; + ClkCfgRegs.AUXPLLMULT.all = 0; + EDIS; + + // + // The user should put some handler code here based on how this + // condition should be handled in their application. + // + asm(" ESTOP0"); + } + + // + // Slip Bit Monitor + // Re-lock routine for SLIP condition + // + attempts = 0; + while(ClkCfgRegs.AUXPLLSTS.bit.SLIPS && (attempts < 10)) + { + EALLOW; + // + // Bypass AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; + asm(" RPT #20 || NOP"); + + // + // Turn off AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Set integer and fractional multiplier, which automatically turns + // on the PLL + // + ClkCfgRegs.AUXPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the AUXPLL lock counter + // + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1); + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + asm(" RPT #20 || NOP"); + + attempts++; + EDIS; + } + + // + // Set divider to desired value + // + EALLOW; + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = divsel; + + // + // Restore Timer 2 configuration + // + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale; + CpuTimer2Regs.TCR.all = t2TCR; + CpuTimer2Regs.PRD.all = t2PRD; + CpuTimer2Regs.TPR.all = t2TPR; + CpuTimer2Regs.TPRH.all = t2TPRH; + + // + // Reload period value + // + CpuTimer2Regs.TCR.bit.TRB = 1; + EDIS; +} + +// +// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with +// current password for the DSP. Returns 1 if unlock is successful. +// +Uint16 CsmUnlock(void) +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the + // DSP. + // + EALLOW; + DcsmZ1Regs.Z1_CSMKEY0 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY1 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY2 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY3 = 0xFFFFFFFF; + + DcsmZ2Regs.Z2_CSMKEY0 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY1 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY2 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY3 = 0xFFFFFFFF; + EDIS; + + return(0); +} + +// +// SysIntOsc1Sel - This function switches to Internal Oscillator 1. +// +void SysIntOsc1Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + EDIS; +} + +// +// SysIntOsc2Sel - This function switches to Internal oscillator 2. +// +void SysIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + EDIS; +} + +// +// SysXtalOscSel - This function switches to External CRYSTAL oscillator. +// +void SysXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} + +// +// AuxIntOsc2Sel - This function switches to Internal oscillator 2. +// +void AuxIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + EDIS; +} + +// +// AuxXtalOscSel - This function switches to External CRYSTAL oscillator. +// +void AuxXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} + +// +// AuxAUXCLKOscSel - This function switches to AUXCLKIN (from a GPIO). +// +void AuxAuxClkSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = XTAL + EDIS; +} + +// +// IDLE - Enter IDLE mode (single CPU). +// +void IDLE(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE; + EDIS; + asm(" IDLE"); +} + +// +// STANDBY - Enter STANDBY mode (single CPU). +// +void STANDBY(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_STANDBY; + EDIS; + asm(" IDLE"); +} + +// +// HALT - Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first. +// +void HALT(void) +{ +#if defined(CPU2) + IDLE(); +#elif defined(CPU1) + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_HALT; + EDIS; + + while(DevCfgRegs.LPMSTAT.bit.CPU2LPMSTAT != 0x1); + + EALLOW; + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + EDIS; + asm(" IDLE"); +#endif +} + +// +// HIB - Enter HIB mode (dual CPU). Puts CPU2 in STANDBY first. Alternately, +// CPU2 may be in reset. +void HIB(void) +{ +#if defined(CPU2) + STANDBY(); +#elif defined(CPU1) + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_HIB; + EDIS; + + while((DevCfgRegs.LPMSTAT.bit.CPU2LPMSTAT == 0x0) && + (DevCfgRegs.RSTSTAT.bit.CPU2RES == 1)); + + DisablePeripheralClocks(); + EALLOW; + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + EDIS; + asm(" IDLE"); +#endif +} + diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_TempSensorConv.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_TempSensorConv.c new file mode 100644 index 00000000000..ffc70fec073 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_TempSensorConv.c @@ -0,0 +1,153 @@ +//########################################################################### +// +// FILE: F2837xD_TempSensorConv.c +// +// TITLE: F2837xD Temperature Sensor Conversion Functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Defines +// +#define FP_SCALE 32768 //Scale factor for Q15 fixed point numbers (2^15) +#define FP_ROUND FP_SCALE/2 //Added to Q15 numbers before converting to + //integer to round the number. +#define KELVIN 273 // Amount to add to Q15 fixed point numbers + // to shift from Celsius to Kelvin + // (Converting guarantees number is + // positive, which makes rounding more + // efficient) +#define KELVIN_OFF FP_SCALE*KELVIN +#define getTempSlope() (*(int (*)(void))0x7036E)() //Slope of temperature sensor + //(deg. C / ADC code). + //Stored in fixed point Q15 + //format. +#define getTempOffset() (*(int (*)(void))0x70372)() //ADC code corresponding to + //temperature sensor output + //at 0 deg. C + +// +// Globals +// +float32 tempSensor_tempSlope; +float32 tempSensor_tempOffset; +float32 tempSensor_scaleFactor; + +// +// InitTempSensor - Initialize the temperature sensor by powering up the +// sensor, loading the calibration values from OTP to RAM, +// and recording the intended VREFHI voltage. +// Note: This function doesn't support VREFLO != 0.0V, +// but this could be implemented if desired. +// +void InitTempSensor(float32 vrefhi_voltage) +{ + EALLOW; + + // + //power up the the temperature sensor + // + AnalogSubsysRegs.TSNSCTL.bit.ENABLE = 1; + + // + //delay to allow the sensor to power up + // + DELAY_US(1000); + + EDIS; + + // + //need to remember VREFHI voltage so that sensor readings can be scaled + //to match 2.5V values used for calibration data. + // + tempSensor_scaleFactor = vrefhi_voltage; + + // + //check the device revision + // + if(DevCfgRegs.REVID >= 3) + { + // + //for production devices (Rev. C), pull the slope and offset from OTP + // + tempSensor_tempSlope = (int32)getTempSlope(); + tempSensor_tempOffset = getTempOffset(); + } + else + { + // + //for pre-production devices, use these static values for slope + //and offset + // + tempSensor_tempSlope = 5196; + tempSensor_tempOffset = 1788; + } +} + +// +// GetTemperatureC - This function uses the reference data stored in OTP to +// convert the raw temperature sensor reading into degrees C +// +int16 GetTemperatureC(int16 sensorSample) +{ + sensorSample = (int16)((tempSensor_scaleFactor/2.5)*(sensorSample)); + + return (((sensorSample - tempSensor_tempOffset)*tempSensor_tempSlope + + FP_ROUND + KELVIN_OFF)/FP_SCALE - KELVIN); +} + +// +// GetTemperatureK - This function uses the reference data stored in OTP to +// convert the raw temperature sensor reading into degrees K +// +int16 GetTemperatureK(int16 sensorSample) +{ + sensorSample = (int16)((2.5/tempSensor_scaleFactor)*(sensorSample)); + + return (((sensorSample - tempSensor_tempOffset)*tempSensor_tempSlope + + FP_ROUND + KELVIN_OFF)/FP_SCALE); +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_Upp.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_Upp.c new file mode 100644 index 00000000000..f0432c9c8d3 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_Upp.c @@ -0,0 +1,153 @@ +//########################################################################### +// +// FILE: F2837xD_Upp.c +// +// TITLE: F2837xD Upp Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitUpp1Gpio - Initialize UPP1 GPIOs +// +void InitUpp1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (uPP_WAIT) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (uPP_START) + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (uPP_ENA) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (uPP_D7) + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (uPP_D6) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (uPP_D5) + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 1; // Disable pull-up on GPIO16 (uPP_D4) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 1; // Disable pull-up on GPIO17 (uPP_D3) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; // Disable pull-up on GPIO18 (uPP_D2) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 1; // Disable pull-up on GPIO19 (uPP_D1) + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (uPP_D0) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (uPP_CLK) + + // + // Disable QUAL for selected pins (ASYNC Input) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Disable pull-up on GPIO10 (uPP_WAIT) + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Disable pull-up on GPIO11 (uPP_START) + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Disable pull-up on GPIO12 (uPP_ENA) + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Disable pull-up on GPIO13 (uPP_D7) + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Disable pull-up on GPIO14 (uPP_D6) + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Disable pull-up on GPIO15 (uPP_D5) + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Disable pull-up on GPIO16 (uPP_D4) + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Disable pull-up on GPIO17 (uPP_D3) + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Disable pull-up on GPIO18 (uPP_D2) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Disable pull-up on GPIO19 (uPP_D1) + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 3; // Disable pull-up on GPIO20 (uPP_D0) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Disable pull-up on GPIO21 (uPP_CLK) + + // + // Configure uPP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM1 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 3; // Configure GPIO10 as uPP_WAIT + GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 3; // Configure GPIO11 as uPP_START + GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 3; // Configure GPIO12 as uPP_ENA + GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 + GpioCtrlRegs.GPAGMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 + GpioCtrlRegs.GPAGMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 + GpioCtrlRegs.GPAGMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4 + GpioCtrlRegs.GPAGMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3 + GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2 + GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1 + GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0 + GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 3; // Configure GPIO21 as uPP_CLK + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 3; // Configure GPIO10 as uPP_WAIT + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as uPP_START + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // Configure GPIO12 as uPP_ENA + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4 + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3 + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2 + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1 + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0 + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 as uPP_CLK + + EDIS; +} + +// +// SoftResetUpp - Trigger an internal uPP reset +// +void SoftResetUpp(void) +{ + UppRegs.PERCTL.bit.SOFTRST = 1; // Issue uPP Internal Reset. + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + UppRegs.PERCTL.bit.SOFTRST = 0; // Release uPP Internal Reset. +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_can.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_can.c new file mode 100644 index 00000000000..3b3cb24beab --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_can.c @@ -0,0 +1,131 @@ +//########################################################################### +// +// FILE: F2837xD_can.c +// +// TITLE: F2837xD CAN Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitCAN - Initializes the CAN-A controller after reset. +// +void InitCAN(void) +{ + int16_t iMsg; + + // + // Place CAN controller in init state, regardless of previous state. This + // will put controller in idle, and allow the message object RAM to be + // programmed. + // + CanaRegs.CAN_CTL.bit.Init = 1; + CanaRegs.CAN_CTL.bit.SWR = 1; + + // + // Wait for busy bit to clear + // + while(CanaRegs.CAN_IF1CMD.bit.Busy) + { + } + + // + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid and is a "safe" condition to leave the message + // object. The same arb reg is used to program all the message objects. + // + CanaRegs.CAN_IF1CMD.bit.DIR = 1; + CanaRegs.CAN_IF1CMD.bit.Arb = 1; + CanaRegs.CAN_IF1CMD.bit.Control = 1; + + CanaRegs.CAN_IF1ARB.all = 0; + + CanaRegs.CAN_IF1MCTL.all = 0; + + CanaRegs.CAN_IF2CMD.bit.DIR = 1; + CanaRegs.CAN_IF2CMD.bit.Arb = 1; + CanaRegs.CAN_IF2CMD.bit.Control = 1; + + CanaRegs.CAN_IF2ARB.all = 0; + + CanaRegs.CAN_IF2MCTL.all = 0; + + // + // Loop through to program all 32 message objects + // + for(iMsg = 1; iMsg <= 32; iMsg+=2) + { + // + // Wait for busy bit to clear + // + while(CanaRegs.CAN_IF1CMD.bit.Busy) + { + } + + // + // Initiate programming the message object + // + CanaRegs.CAN_IF1CMD.bit.MSG_NUM = iMsg; + + // + // Wait for busy bit to clear + // + while(CanaRegs.CAN_IF2CMD.bit.Busy) + { + } + + // + // Initiate programming the message object + // + CanaRegs.CAN_IF2CMD.bit.MSG_NUM = iMsg + 1; + } + + // + // Acknowledge any pending status interrupts. + // + volatile uint32_t discardRead = CanaRegs.CAN_ES.all; + +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_sci_io.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_sci_io.c new file mode 100644 index 00000000000..28c676c18db --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_sci_io.c @@ -0,0 +1,185 @@ +//############################################################################# +// +// File: F2837xD_sci_io.c +// +// Description: Contains the various functions related to the serial +// communications interface (SCI) object +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include +#include +#include "F28x_Project.h" +#include "F2837xD_sci_io.h" + +// +// Globals +// +uint16_t deviceOpen = 0; + +// +// SCI_open - Initialize and setup SCI +// +int SCI_open(const char * path, unsigned flags, int llv_fd) +{ + if(deviceOpen) + { + return (-1); + } + else + { + EALLOW; + CpuSysRegs.PCLKCR7.bit.SCI_A = 1; + SciaRegs.SCIFFTX.all=0xE040; + SciaRegs.SCIFFRX.all=0x2044; + SciaRegs.SCIFFCT.all=0x0; + SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.TXINTENA =1; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + + SciaRegs.SCIHBAUD.bit.BAUD =0x0000; // 9600 baud @LSPCLK = 10MHz + //(40 MHz SYSCLK). + SciaRegs.SCILBAUD.bit.BAUD =0x0081; + + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset + EDIS; + + deviceOpen = 1; + return (1); + } +} + +// +// SCI_close - Set SCI to closed +// +int SCI_close(int dev_fd) +{ + if((dev_fd != 1) || (!deviceOpen)) + { + return (-1); + } + else + { + deviceOpen = 0; + return (0); + } +} + +// +// SCI_read - Read from the SCI RX buffer +// +int SCI_read(int dev_fd, char * buf, unsigned count) +{ + uint16_t readCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while((readCount < count) && SciaRegs.SCIRXST.bit.RXRDY) + { + *bufPtr = SciaRegs.SCIRXBUF.bit.SAR; + readCount++; + bufPtr++; + } + + return (readCount); +} + +// +// SCI_write - Write to the SCI TX buffer +// +int SCI_write(int dev_fd, char * buf, unsigned count) +{ + uint16_t writeCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while(writeCount < count) + { + while(SciaRegs.SCICTL2.bit.TXRDY != 1) + { + } + SciaRegs.SCITXBUF.bit.TXDT = *bufPtr; + writeCount++; + bufPtr++; + } + + return (writeCount); +} + +// +// SCI_lseek - Do nothing +// +off_t SCI_lseek(int dev_fd, off_t offset, int origin) +{ + return (0); +} + +// +// SCI_unlink - Do nothing +// +int SCI_unlink(const char * path) +{ + return (0); +} + +// +// SCI_rename - Do nothing +// +int SCI_rename(const char * old_name, const char * new_name) +{ + return (0); +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_sdfm_drivers.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_sdfm_drivers.c new file mode 100644 index 00000000000..4bbfdf58904 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_sdfm_drivers.c @@ -0,0 +1,554 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm_drivers.c +// +// TITLE: SDFM Driver functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F28x_Project.h" +#include "F2837xD_struct.h" +#include "F2837xD_sdfm_drivers.h" + +// +// Sdfm_configureInputCtrl - This function configures SDFM Input control unit. +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter (FILTER1,FILTER2, +// FILTER3,FILTER4) needs to be +// configured. +// mode - This parameter is used to select +// one of the modes mentioned above +// +// Input control unit can be configured in four different modes: +// MODE_0 : Modulator clock rate = Modulator data rate +// MODE_1 : Modulator clock rate = (Modulator data rate / 2) +// MODE_2 : Manchester encoded data (Modulator clock is encoded into data) +// MODE_3 : Modulator clock rate = (2 x Modulator data rate) +// +void Sdfm_configureInputCtrl(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 mode) +{ + EALLOW; + + switch (filterNumber) + { + case FILTER1: + (*SDFM[sdfmNumber]).SDCTLPARM1.bit.MOD = mode; + break; + + case FILTER2: + (*SDFM[sdfmNumber]).SDCTLPARM2.bit.MOD = mode; + break; + + case FILTER3: + (*SDFM[sdfmNumber]).SDCTLPARM3.bit.MOD = mode; + break; + + case FILTER4: + (*SDFM[sdfmNumber]).SDCTLPARM4.bit.MOD = mode; + break; + } + + EDIS; +} + +// +// Sdfm_configureComparator - This function configures SDFM Comparator unit. +// Comparator unit can be configured to monitor +// input conditions with a fast settling time. +// This module can be programmed to detect over and +// under value conditions. +// +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter (FILTER1,FILTER2, +// FILTER3,FILTER3) +// filterType - This parameter is used to select +// one of the filter type mentioned +// above (SINC1,SINC2,SINC3,SINCFAST) +// OSR - This parameter is used to +// configure oversampling ratio for +// comparator +// HLT - This parameter is used to +// configure to detect over value +// condition +// LLT - This parameter is used to +// configure to detect under value +// condition +// +void Sdfm_configureComparator(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 filterType, Uint16 OSR, Uint16 HLT, + Uint16 LLT) +{ + EALLOW; + + switch (filterNumber) + { + case FILTER1: //Filter 1 + + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM1.bit.CS1_CS0 = filterType; + + // + //Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH1.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL1.bit.LLT = LLT; + break; + + case FILTER2: //Filter 2 + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM2.bit.CS1_CS0 = filterType; + + // + //Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH2.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL2.bit.LLT = LLT; + break; + + case FILTER3: //Filter 3 + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM3.bit.CS1_CS0 = filterType; + + // + //Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH3.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL3.bit.LLT = LLT; + break; + + case FILTER4: //Filter 4 + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM4.bit.CS1_CS0 = filterType; + + // + //Configure Comparator OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH4.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL4.bit.LLT = LLT; + break; + } + + EDIS; +} + + +// +// SDFM_configureData_filter - This function configures SDFM Data filter unit +// +// SDFM Data filter unit can be configured in any +// of four different Sinc filter types: +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter(FILTER1,FILTER2, +// FILTER3,FILTER3) needs to be +// configured +// Filter_switch - This parameter is used to +// enable/disable a filter +// filterType - This parameter is used to select +// one of the filter type mentioned +// above (SINC1 / SINC2 / SINC3 / +// SINCFAST) +// OSR - This parameter is used to +// configure oversampling ratio +// for Data filter (Upto OSR_256) +// DR_switch - This parameter selects whether +// data is represented in 16 (or) +// 32 bits +// shift_bits - When user chooses 16 bit +// representation, this variable +// allows to right shift by +// specific number of bits +// +void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 Filter_switch, Uint16 filterType, + Uint16 OSR, Uint16 DR_switch, Uint16 shift_bits) +{ + EALLOW; + + switch(filterNumber) + { + + case FILTER1: //Filter 1 + (*SDFM[sdfmNumber]).SDDFPARM1.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + //DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM1.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM1.bit.SH = shift_bits; + } + + break; + + case FILTER2: //Filter 2 + (*SDFM[sdfmNumber]).SDDFPARM2.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM2.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM2.bit.SH = shift_bits; + } + + break; + + case FILTER3: //Filter 3 + (*SDFM[sdfmNumber]).SDDFPARM3.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM3.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM3.bit.SH = shift_bits; + } + + break; + + case FILTER4: //Filter 4 + (*SDFM[sdfmNumber]).SDDFPARM4.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM4.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM4.bit.SH = shift_bits; + } + + break; + } + + EDIS; +} + +// +// Sdfm_configureInterrupt - This function configures SDFM Interrupt unit. +// SDFM Interrupt unit can be configured to +// enable/disable different sources of SDFM +// interrupts which should trigger CPU interrupt. +// +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter(FILTER1,FILTER2, +// FILTER3,FILTER3) needs to be +// configured +// IEH_Switch - This parameter allows over value +// condition to trigger CPU interrupt +// IEL_Switch - This parameter allows under value +// condition to trigger CPU interrupt +// MFIE_Switch - This parameter allows modulator +// failure to trigger CPU interrupt +// AE_Switch - This parameter allows new filter +// data acknowledge interrupt signal +// to trigger CPU interrupt +// +void Sdfm_configureInterrupt(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 IEH_Switch, Uint16 IEL_Switch, + Uint16 MFIE_Switch, Uint16 AE_Switch) +{ + EALLOW; + + switch(filterNumber) + { + case FILTER1: //Filter 1 + (*SDFM[sdfmNumber]).SDCPARM1.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM1.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM1.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.AE = AE_Switch; + break; + + case FILTER2: //Filter 2 + (*SDFM[sdfmNumber]).SDCPARM2.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM2.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM2.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.AE = AE_Switch; + break; + + case FILTER3: //Filter 3 + (*SDFM[sdfmNumber]).SDCPARM3.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM3.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM3.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.AE = AE_Switch; + break; + + case FILTER4: //Filter 4 + (*SDFM[sdfmNumber]).SDCPARM4.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM4.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM4.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.AE = AE_Switch; + break; + } + + EDIS; +} + + +// +// SDFM_configExternalreset - This function configures SDFM module to +// enable/disable external filter reset from PWM +// +// sdfmNumber - This parameter should +// be used to select +// SDFM1 (or) SDFM2 +// filter1_Config_ext_reset - This parameter is used +// to enable/disable +// external PWM reset for +// filter1 +// filter2_Config_ext_reset - This parameter is used +// to enable/disable +// external PWM reset for +// filter2 +// filter3_Config_ext_reset - This parameter is used +// to enable / disable +// external PWM reset for +// filter3 +// filter4_Config_ext_reset - This parameter is used +// to enable / disable +// external PWM reset for +// filter4 +// +void Sdfm_configureExternalreset(Uint16 sdfmNumber, + Uint16 filter1_Config_ext_reset, + Uint16 filter2_Config_ext_reset, + Uint16 filter3_Config_ext_reset, + Uint16 filter4_Config_ext_reset) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.SDSYNCEN = filter1_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.SDSYNCEN = filter2_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.SDSYNCEN = filter3_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.SDSYNCEN = filter4_Config_ext_reset; + EDIS; +} + +// +// SDFM_enableMFE - This function enables Master filter bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_enableMFE(Uint16 sdfmNumber) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 1; //Master Filter bit is enabled + EDIS; +} + +// +// SDFM_disableMFE - This function disable Master filter bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void SDFM_disableMFE(Uint16 sdfmNumber) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 0; //Master Filter bit is disabled + EDIS; +} + +// +// SDFM_enableMIE - This function enable Master Interrupt bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_enableMIE(Uint16 sdfmNumber) +{ + EALLOW; + // + //Enable MIE (Master Interrupt Enable) bit + // + (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 1; + EDIS; +} + +// +// Sdfm_disableMIE - This function disable Master Interrupt bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_disableMIE(Uint16 sdfmNumber) +{ + + EALLOW; + // + //Disable MIE (Master Interrupt Enable) bit + // + (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 0; + EDIS; +} + +// +// Sdfm_readFlagRegister - This function helps user read SDFM flag +// register (SDIFLG) +// +Uint32 Sdfm_readFlagRegister(Uint16 sdfmNumber) +{ + return ((*SDFM[sdfmNumber]).SDIFLG.all); +} + +// +// Sdfm_clearFlagRegister - This function helps is used to clear +// SDIFLG register +// +void Sdfm_clearFlagRegister(Uint16 sdfmNumber,Uint32 sdfmReadFlagRegister) +{ + (*SDFM[sdfmNumber]).SDIFLGCLR.all = sdfmReadFlagRegister; +} + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_struct.c b/bsp/tms320f28379d/libraries/common/source/F2837xD_struct.c new file mode 100644 index 00000000000..1a306bd1d40 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_struct.c @@ -0,0 +1,100 @@ +//########################################################################### +// +// FILE: F2837xD_struct.c +// +// TITLE: F2837xD SDFM structure +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_struct.h" + +// +// Globals +// +#if defined(CPU1) +volatile struct ADC_REGS *ADC[MAX_ADC] = +{ 0, &AdcaRegs, &AdcbRegs, + &AdccRegs, &AdcdRegs }; +#endif + +volatile struct ECAP_REGS *ECAP[MAX_ECAP] = +{ 0, &ECap1Regs, &ECap2Regs, &ECap3Regs, + &ECap4Regs, &ECap5Regs, &ECap6Regs }; + +volatile struct EPWM_REGS *EPWM[MAX_EPWM] = +{ 0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, + &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, + &EPwm7Regs, &EPwm8Regs, &EPwm9Regs, + &EPwm10Regs, &EPwm11Regs, &EPwm12Regs }; + +volatile struct EQEP_REGS *EQEP[MAX_EQEP] = +{ 0, &EQep1Regs, &EQep2Regs, &EQep3Regs }; + +volatile struct I2C_REGS *I2C[MAX_I2C] = +{ 0, &I2caRegs }; + +volatile struct McBSP_REGS *MCBSP[MAX_MCBSP] = +{ 0, &McbspaRegs }; + +volatile struct SCI_REGS *SCI[MAX_SCI] = +{ 0, &SciaRegs }; + +volatile struct SPI_REGS *SPI[MAX_SPI] = +{ 0, &SpiaRegs, &SpibRegs, &SpicRegs }; + +volatile struct SDFM_REGS *SDFM[MAX_SDFM] = +{ 0, &Sdfm1Regs, &Sdfm2Regs}; + +#if defined(CPU1) +volatile Uint16 *TRIP_SEL[MAX_TRIPSEL] = +{ 0, &InputXbarRegs.INPUT1SELECT, &InputXbarRegs.INPUT2SELECT, + &InputXbarRegs.INPUT3SELECT, &InputXbarRegs.INPUT4SELECT, + &InputXbarRegs.INPUT5SELECT, &InputXbarRegs.INPUT6SELECT, + &InputXbarRegs.INPUT7SELECT, &InputXbarRegs.INPUT8SELECT, + &InputXbarRegs.INPUT9SELECT, &InputXbarRegs.INPUT10SELECT, + &InputXbarRegs.INPUT11SELECT, &InputXbarRegs.INPUT12SELECT, + &InputXbarRegs.INPUT13SELECT, &InputXbarRegs.INPUT14SELECT +}; +#endif + +// +// End of file +// diff --git a/bsp/tms320f28379d/libraries/common/source/F2837xD_usDelay.asm b/bsp/tms320f28379d/libraries/common/source/F2837xD_usDelay.asm new file mode 100644 index 00000000000..71d3606fd05 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/F2837xD_usDelay.asm @@ -0,0 +1,105 @@ +;//########################################################################### +;// +;// FILE: F2837xD_usDelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// To use this function: +;// 1 - update the CPU clock speed in the F2837xD_Examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the F2837xD_Device.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// extern void Delay(long LoopCount); +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// Or as follows (if count is less then 16-bits): +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;//########################################################################### +;// $TI Release: F2837xD Support Library v3.05.00.00 $ +;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +;// $Copyright: +;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + + .def _F28x_usDelay + + .cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro + %{ + %} + + .if __TI_COMPILER_VERSION__ + .if __TI_COMPILER_VERSION__ >= 15009000 + .sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer + .else + .sect "ramfuncs" ;;Used with compilers older than v15.9.0 + .endif + .endif + + .global __F28x_usDelay +_F28x_usDelay: + SUB ACC,#1 + BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +; + +;// +;// End of file +;// diff --git a/bsp/tms320f28379d/libraries/common/source/device.c b/bsp/tms320f28379d/libraries/common/source/device.c new file mode 100644 index 00000000000..171d3ac8f15 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/device.c @@ -0,0 +1,328 @@ +//############################################################################# +// +// FILE: device.c +// +// TITLE: Device setup for examples. +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "device.h" +#include "driverlib.h" +#ifdef __cplusplus +using std::memcpy; +#endif + +//***************************************************************************** +// +// Function to initialize the device. Primarily initializes system control to a +// known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +// and enabling the clocks to the peripherals. +// +//***************************************************************************** +void Device_init(void) +{ + // + // Disable the watchdog + // + SysCtl_disableWatchdog(); + +#ifdef _FLASH + // + // Copy time critical code and flash setup code to RAM. This includes the + // following functions: InitFlash(); + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols + // are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES); +#endif +#ifdef CPU1 + // + // Set up PLL control and clock dividers + // + SysCtl_setClock(DEVICE_SETCLOCK_CFG); + + // + // Make sure the LSPCLK divider is set to the default (divide by 4) + // + SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4); + + // + // These asserts will check that the #defines for the clock rates in + // device.h match the actual rates that have been configured. If they do + // not match, check that the calculations of DEVICE_SYSCLK_FREQ and + // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as + // expected if these are not correct. + // + ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ); + ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ); +#endif + // + // Turn on all peripherals + // + Device_enableAllPeripherals(); +} + +//***************************************************************************** +// +// Function to turn on all peripherals, enabling reads and writes to the +// peripherals' registers. +// +// Note that to reduce power, unused peripherals should be disabled. +// +//***************************************************************************** +void Device_enableAllPeripherals(void) +{ + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2); +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM); +#endif + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC); +} + +//***************************************************************************** +// +// Function to disable pin locks on GPIOs. +// +//***************************************************************************** +void Device_initGPIO(void) +{ + // + // Disable pin locks. + // + GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF); + + // + // Enable GPIO Pullups + // + Device_enableUnbondedGPIOPullups(); +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 176PTP package: +// GPIOs Grp Bits +// 95-132 C 31 +// D 31:0 +// E 4:0 +// 134-168 E 31:6 +// F 8:0 +// +//***************************************************************************** + +void Device_enableUnbondedGPIOPullupsFor176Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ package: +// GPIOs Grp Bits +// 0-1 A 1:0 +// 5-9 A 9:5 +// 22-40 A 31:22 +// B 8:0 +// 44-57 B 25:12 +// 67-68 C 4:3 +// 74-77 C 13:10 +// 79-83 C 19:15 +// 93-168 C 31:29 +// D 31:0 +// E 31:0 +// F 8:0 +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullupsFor100Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ or +// 176PTP package. +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullups(void) +{ + // + // bits 8-10 have pin count + // + uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + (uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + + /* + * 5 = 100 pin + * 6 = 176 pin + * 7 = 337 pin + */ + if(pinCount == 5) + { + Device_enableUnbondedGPIOPullupsFor100Pin(); + } + else if(pinCount == 6) + { + Device_enableUnbondedGPIOPullupsFor176Pin(); + } + else + { + // + // Do nothing - this is 337 pin package + // + } +} + +//***************************************************************************** +// +// Error handling function to be called when an ASSERT is violated +// +//***************************************************************************** +void __error__(char *filename, uint32_t line) +{ + // + // An ASSERT condition was evaluated as false. You can use the filename and + // line parameters to determine what went wrong. + // + ESTOP0; +} diff --git a/bsp/tms320f28379d/libraries/common/source/usb.c b/bsp/tms320f28379d/libraries/common/source/usb.c new file mode 100644 index 00000000000..db82fb7a399 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/usb.c @@ -0,0 +1,3972 @@ +//########################################################################### +// +// FILE: usb.c +// +// TITLE: Driver for the USB Interface. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + + +//***************************************************************************** +// +//! \addtogroup usb_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_usb.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" +#include "usb.h" + +//***************************************************************************** +// +// Amount to shift the RX interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#define USB_INTEP_RX_SHIFT 16 + +//***************************************************************************** +// +// Amount to shift the RX endpoint status sources by in the flags used in the +// calls. +// +//***************************************************************************** +#define USB_RX_EPSTATUS_SHIFT 16 + +//***************************************************************************** +// +// Converts from an endpoint specifier to the offset of the endpoint's +// control/status registers. +// +//***************************************************************************** +#define EP_OFFSET(Endpoint) (Endpoint - 0x10) + +//***************************************************************************** +// +// Sets one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// \param ui8Value is the value to write to the register. +// +// This function is used to access the indexed registers for each endpoint. +// The only registers that are indexed are the FIFO configuration registers, +// which are not used after configuration. +// +// \return None. +// +//***************************************************************************** +static void +_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size) +{ + uint32_t ui32Index; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || + (ui32Endpoint == 3)); + ASSERT((ui32Size == 1) || (ui32Size == 2)); + + // + // Save the old index in case it was in use. + // + ui32Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1) + { + // + // Set the value. + // + HWREGB(ui32Base + ui32IndexedReg) = ui32Value; + } + else + { + // + // Set the value. + // + HWREGH(ui32Base + ui32IndexedReg) = ui32Value; + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Index; +} + +//***************************************************************************** +// +// Reads one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// +// This function is used internally to access the indexed registers for each +// endpoint. The only registers that are indexed are the FIFO configuration +// registers, which are not used after configuration. +// +// \return The value in the register requested. +// +//***************************************************************************** +static uint32_t +_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Size) +{ + uint8_t ui8Index; + uint8_t ui8Value; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || + (ui32Endpoint == 3)); + ASSERT((ui32Size == 1) || (ui32Size == 2)); + + // + // Save the old index in case it was in use. + // + ui8Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1) + { + // + // Get the value. + // + ui8Value = HWREGB(ui32Base + ui32IndexedReg); + } + else + { + // + // Get the value. + // + ui8Value = HWREGH(ui32Base + ui32IndexedReg); + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui8Index; + + // + // Return the register's value. + // + return(ui8Value); +} + +//***************************************************************************** +// +//! Puts the USB bus in a suspended state. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! When used in host mode, this function puts the USB bus in the suspended +//! state. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostSuspend(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Send the suspend signaling to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND; +} + +//***************************************************************************** +// +//! Handles the USB bus reset condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies whether to start or stop signaling reset on the USB +//! bus. +//! +//! When this function is called with the \e bStart parameter set to \b true, +//! this function causes the start of a reset condition on the USB bus. +//! The caller must then delay at least 20ms before calling this function +//! again with the \e bStart parameter set to \b false. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostReset(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Send a reset signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET; + } +} + +//***************************************************************************** +// +//! Handles the USB bus resume condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if the USB controller is entering or leaving the +//! resume signaling state. +//! +//! When in device mode, this function brings the USB controller out of the +//! suspend state. This call must first be made with the \e bStart parameter +//! set to \b true to start resume signaling. The device application must +//! then delay at least 10ms but not more than 15ms before calling this +//! function with the \e bStart parameter set to \b false. +//! +//! When in host mode, this function signals devices to leave the suspend +//! state. This call must first be made with the \e bStart parameter set to +//! \b true to start resume signaling. The host application must then delay +//! at least 20ms before calling this function with the \e bStart parameter set +//! to \b false. This action causes the controller to complete the resume +//! signaling on the USB bus. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostResume(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Send a resume signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME; + } +} + +//***************************************************************************** +// +//! Returns the current speed of the USB device connected. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current speed of the USB bus in host mode. +//! +//! \b Example: Get the USB connection speed. +//! +//! \verbatim +//! // +//! // Get the connection speed of the device connected to the USB controller. +//! // +//! USBHostSpeedGet(USB0_BASE); +//! \endverbatim +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, +//! or \b USB_UNDEF_SPEED. +// +//***************************************************************************** +uint32_t +USBHostSpeedGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) + { + return(USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) + { + return(USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return(USB_UNDEF_SPEED); +} + +//***************************************************************************** +// +//! Disables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to disable. +//! +//! This function disables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to disable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS); + } + + // + // Disable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = 0; + } + + // + // Disable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = 0; + } +} + +//***************************************************************************** +// +//! Enables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to enable. +//! +//! This function enables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to enable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) |= ui32Flags; + } + + // + // Enable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF; + } + + // + // Enable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID; + } +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32IntStatusEP is a pointer to the variable which holds the +//! endpoint interrupt status from RXIS And TXIS. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +//! This is the value of USBIS. +// +//***************************************************************************** +uint32_t +USBIntStatus(uint32_t ui32Base, uint32_t *pui32IntStatusEP) +{ + uint32_t ui32Status = 0; + *pui32IntStatusEP = 0; + uint32_t usbis = 0; + uint32_t rxis = 0; + uint32_t txis = 0; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + // + // Do-While to make sure that all status registers are cleared before continuing. + // This eliminates the race condition which can cause the USB interrupt to stay high + // and never get triggered again. + // + do + { + // Get the general interrupt status. + usbis = (uint32_t)HWREGB(ui32Base + USB_O_IS); + // Get the transmit interrupt status. + txis = (uint32_t)HWREGH(ui32Base + USB_O_TXIS); + // Get the receive interrupt status. + rxis = (uint32_t)HWREGH(ui32Base + USB_O_RXIS); + + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + ui32Status |= usbis; + // Get the transmit interrupt status. + *pui32IntStatusEP |= txis; + // Get the receive interrupt status, these bits go into the second byte of + // the returned value. + *pui32IntStatusEP |= ((uint32_t)rxis << USB_INTEP_RX_SHIFT); + + } while(usbis != 0x0000 || txis != 0x0000 || rxis != 0x0000); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusControl(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ui32Status = HWREGB(ui32Base + USB_O_IS); + + //*ui32EPStatus = USBIntStatusEndpoint(ui32Base); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Disables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to disable. +//! +//! This function disables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to disable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_TXIE) &= + ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_RXIE) &= + ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Enables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to enable. +//! +//! This function enables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to enable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable any transmit endpoint interrupts. + // + HWREGH(ui32Base + USB_O_TXIE) |= + ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + + // + // Enable any receive endpoint interrupts. + // + HWREGH(ui32Base + USB_O_RXIE) |= + ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Returns the endpoint interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads endpoint interrupt status for a USB controller. This +//! call returns the current status for endpoint interrupts only, the control +//! interrupt status is retrieved by calling USBIntStatusControl(). The bit +//! values returned are compared against the \b USB_INTEP_* values. +//! These values are grouped into classes for \b USB_INTEP_HOST_* and +//! \b USB_INTEP_DEV_* values to handle both host and device modes with all +//! endpoints. +//! +//! \note This call clears the source of all of the endpoint interrupts. +//! +//! \return Returns the status of the endpoint interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusEndpoint(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Get the transmit interrupt status. + // + ui32Status = HWREGH(ui32Base + USB_O_TXIS); + ui32Status |= ((uint32_t)HWREGH(ui32Base + USB_O_RXIS) << USB_INTEP_RX_SHIFT); + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns the interrupt number for a given USB module. +//! +//! \param ui32Base is the base address of the USB module. +//! +//! This function returns the interrupt number for the USB module with the base +//! address passed in the \e ui32Base parameter. +//! +//! \return Returns the USB interrupt number or 0 if the interrupt does not +//! exist. +// +//***************************************************************************** +static uint32_t +_USBIntNumberGet(uint32_t ui32Base) +{ + return(INT_USB0); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param pfnHandler is a pointer to the function to be called when a USB +//! interrupt occurs. +//! +//! This function registers the handler to be called when a USB interrupt +//! occurs and enables the global USB interrupt in the interrupt controller. +//! The specific desired USB interrupts must be enabled via a separate call to +//! USBIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt sources via calls to USBIntStatusControl() and +//! USBIntStatusEndpoint(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + ui32Int = _USBIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the USB interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function unregisters the interrupt handler. This function also +//! disables the USB interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering or +//! unregistering interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + ui32Int = _USBIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Disable the USB interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Returns the current status of an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the status of a given endpoint. If any of these +//! status bits must be cleared, then the USBDevEndpointStatusClear() or the +//! USBHostEndpointStatusClear() functions must be called. +//! +//! The following are the status flags for host mode: +//! +//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. +//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. +//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. +//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN +//! endpoint in Isochronous mode. +//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN +//! endpoint. +//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. +//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. +//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT +//! request. +//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. +//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this +//! OUT endpoint. +//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. +//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not +//! completed. +//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the +//! specified timeout period. +//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on +//! endpoint zero. +//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an +//! IN transaction. +//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN +//! transaction. +//! +//! The following are the status flags for device mode: +//! +//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. +//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT +//! endpoint. +//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. +//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. +//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT +//! endpoint's FIFO. +//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. +//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. +//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no +//! data was ready. +//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. +//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not +//! completed. +//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End +//! condition was sent. +//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. +//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not +//! completed. +//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint +//! zero's OUT FIFO. +//! +//! \return The current status flags for the endpoint depending on mode. +// +//***************************************************************************** +uint32_t +USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the TX portion of the endpoint status. + // + ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1); + + // + // Get the RX portion of the endpoint status. + // + ui32Status |= + (((uint32_t)HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) << + USB_RX_EPSTATUS_SHIFT); + + // + // Return the endpoint status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Clear the specified flags for the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags; + } + else + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~ui32Flags; + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if(ui32Flags & USB_DEV_EP0_SETUP_END) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC; + } + + // + // Clear the Sent Stall status flag. + // + if(ui32Flags & USB_DEV_EP0_SENT_STALL) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // must be cleared. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Sets the value data toggle on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. +//! \param ui32Flags specifies whether to set the IN or OUT endpoint. +//! +//! This function is used to force the state of the data toggle in host mode. +//! If the value passed in the \e bDataToggle parameter is \b false, then the +//! data toggle is set to the DATA0 state, and if it is \b true it is set to +//! the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or +//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The +//! \e ui32Flags parameter is ignored for endpoint zero. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags) +{ + uint32_t ui32DataToggle; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // The data toggle defaults to DATA0. + // + ui32DataToggle = 0; + + // + // See if the data toggle must be set to DATA1. + // + if(bDataToggle) + { + // + // Select the data toggle bit based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32DataToggle = USB_CSRH0_DT; + } + else if(ui32Flags == USB_EP_HOST_IN) + { + ui32DataToggle = USB_RXCSRH1_DT; + } + else + { + ui32DataToggle = USB_TXCSRH1_DT; + } + } + + // + // Set the data toggle based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the write enable and the bit value for endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRH0) = + ((HWREGB(ui32Base + USB_O_CSRH0) & + ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (ui32DataToggle | USB_CSRH0_DTWE)); + } + else if(ui32Flags == USB_EP_HOST_IN) + { + // + // Set the Write enable and the bit value for an IN endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (ui32DataToggle | USB_RXCSRH1_DTWE)); + } + else + { + // + // Set the Write enable and the bit value for an OUT endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (ui32DataToggle | USB_TXCSRH1_DTWE)); + } +} + +//***************************************************************************** +// +//! Sets the data toggle on an endpoint to zero. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param ui32Flags specifies whether to access the IN or OUT endpoint. +//! +//! This function causes the USB controller to clear the data toggle for an +//! endpoint. This call is not valid for endpoint zero and can be made with +//! host or device controllers. +//! +//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive data toggle must be cleared. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Stalls the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to stall. +//! \param ui32Flags specifies whether to stall the IN or OUT endpoint. +//! +//! This function causes the endpoint number passed in to go into a stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is issued on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion +//! of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Determine how to stall this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_STALL; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_STALL; + } +} + +//***************************************************************************** +// +//! Clears the stall condition on the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint to remove the stall condition. +//! \param ui32Flags specifies whether to remove the stall condition from the +//! IN or the OUT portion of this endpoint. +//! +//! This function causes the endpoint number passed in to exit the stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is cleared on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT +//! portion of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); + + // + // Determine how to clear the stall on this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + // + // Clear the stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Connects the USB controller to the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevConnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN; +} + +//***************************************************************************** +// +//! Removes the USB controller from the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! remove the device from the USB bus. A call to USBDevConnect() is needed to +//! reconnect to the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevDisconnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Disable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN); +} + +//***************************************************************************** +// +//! Sets the address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Address is the address to use for a device. +//! +//! This function configures the device address on the USB bus. This address +//! was likely received via a SET ADDRESS command from the host controller. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Set the function address in the correct location. + // + HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address; +} + +//***************************************************************************** +// +//! Returns the current device address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current device address. This address was set +//! by a call to USBDevAddrSet(). +//! +//! \note This function must only be called in device mode. +//! +//! \return The current device address. +// +//***************************************************************************** +uint32_t +USBDevAddrGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Return the function address. + // + return(HWREGB(ui32Base + USB_O_FADDR)); +} + +//***************************************************************************** +// +//! Sets the base configuration for a host endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPayload is the maximum payload for this endpoint. +//! \param ui32NAKPollInterval is the either the NAK timeout limit or the +//! polling interval, depending on the type of endpoint. +//! \param ui32TargetEndpoint is the endpoint that the host endpoint is +//! targeting. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for the transmit or receive +//! portion of an endpoint in host mode. The \e ui32Flags parameter determines +//! some of the configuration while the other parameters provide the rest. The +//! \e ui32Flags parameter determines whether this is an IN endpoint +//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint +//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed +//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint +//! (\b USB_EP_SPEED_LOW). +//! +//! The \b USB_EP_MODE_ flags control the type of the endpoint. +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \e ui32NAKPollInterval parameter has different meanings based on the +//! \b USB_EP_MODE value and whether or not this call is being made for +//! endpoint zero or another endpoint. For endpoint zero or any Bulk +//! endpoints, this value always indicates the number of frames to allow a +//! device to NAK before considering it a timeout. If this endpoint is an +//! isochronous or interrupt endpoint, this value is the polling interval for +//! this endpoint. +//! +//! For interrupt endpoints, the polling interval is the number of frames +//! between interrupt IN requests to an endpoint and has a range of 1 to 255. +//! For isochronous endpoints this value represents a polling interval of +//! 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the +//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) +//! frames before issuing a time out. +//! +//! There are two special time out values that can be specified when setting +//! the \e ui32NAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is +//! the maximum value that can be passed in this variable. The other is +//! \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the +//! number of NAKs. +//! +//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the +//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit +//! is specified to cause the transmission of data on the USB bus to start +//! as soon as the number of bytes specified by \e ui32MaxPayload has been +//! written into the OUT FIFO for this endpoint. +//! +//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST +//! bit can be specified to trigger the request for more data once the FIFO has +//! been drained enough to fit \e ui32MaxPayload bytes. The +//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag +//! automatically once the data has been read from the FIFO. If this option is +//! not used, this flag must be manually cleared via a call to +//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear(). +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + ASSERT(ui32NAKPollInterval <= MAX_NAK_LIMIT); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval; + + // + // Set the transfer type information. + // + HWREGB(ui32Base + USB_O_TYPE0) = + ((ui32Flags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : + USB_TYPE0_SPEED_LOW); + } + else + { + // + // Start with the target endpoint. + // + ui32Register = ui32TargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if(ui32Flags & USB_EP_SPEED_FULL) + { + ui32Register |= USB_TXTYPE1_SPEED_FULL; + } + else + { + ui32Register |= USB_TXTYPE1_SPEED_LOW; + } + + // + // Set the protocol for the device using this endpoint. + // + switch(ui32Flags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ui32Register |= USB_TXTYPE1_PROTO_BULK; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ui32Register |= USB_TXTYPE1_PROTO_ISOC; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ui32Register |= USB_TXTYPE1_PROTO_INT; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ui32Register |= USB_TXTYPE1_PROTO_CTRL; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPayload; + + // + // Set the transmit control value to zero. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Write out the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + } + else + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPayload; + + // + // Set the receive control value to zero. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register |= USB_RXCSRH1_AUTOCL; + } + + // + // Allow auto generation of DMA requests. + // + if(ui32Flags & USB_EP_AUTO_REQUEST) + { + ui32Register |= USB_RXCSRH1_AUTORQ; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Write out the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + } + } +} + +//***************************************************************************** +// +//! Sets the configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPacketSize is the maximum packet size for this endpoint. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for an endpoint in device mode. +//! Endpoint zero does not have a dynamic configuration, so this function +//! must not be called for endpoint zero. The \e ui32Flags parameter +//! determines some of the configuration while the other parameters provide the +//! rest. +//! +//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint. +//! +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the +//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be +//! specified to cause the automatic transmission of data on the USB bus as +//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for +//! this endpoint. This option is commonly used with DMA as no interaction is +//! required to start the transmission of data. +//! +//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is +//! specified to trigger the request for more data once the FIFO has been +//! drained enough to receive \e ui32MaxPacketSize more bytes of data. Also +//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the +//! data packet ready flag automatically once the data has been read from the +//! FIFO. If this option is not used, this flag must be manually cleared via a +//! call to USBDevEndpointStatusClear(). Both of these settings can be used to +//! remove the need for extra calls when using the controller in DMA mode. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Set the maximum packet size. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_TXCSRH1_ISO; + } + + // + // Write the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) = + USB_TXCSRL1_CLRDT; + } + else + { + // + // Set the MaxPacketSize. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register = USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_RXCSRH1_ISO; + } + + // + // Write the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) = + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Gets the current configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32MaxPacketSize is a pointer which is written with the maximum +//! packet size for this endpoint. +//! \param pui32Flags is a pointer which is written with the current endpoint +//! settings. On entry to the function, this pointer must contain either +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT +//! endpoint is to be queried. +//! +//! This function returns the basic configuration for an endpoint in device +//! mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are +//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed +//! to USBDevEndpointConfigSet() for this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT(pui32MaxPacketSize && pui32Flags); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // Determine if a transmit or receive endpoint is being queried. + // + if(*pui32Flags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_TXMAXP1); + + // + // Get the current transmit control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_TXCSRH1); + + // + // Are we allowing auto setting of TxPktRdy when max packet size has + // been loaded into the FIFO? + // + if(ui32Register & USB_TXCSRH1_AUTOSET) + { + *pui32Flags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_TXCSRH1_DMAEN) + { + if(ui32Register & USB_TXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_TXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_RXMAXP1); + + // + // Get the current receive control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_RXCSRH1); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size max + // packet has been unloaded from the FIFO? + // + if(ui32Register & USB_RXCSRH1_AUTOCL) + { + *pui32Flags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_RXCSRH1_DMAEN) + { + if(ui32Register & USB_RXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_RXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } +} + +//***************************************************************************** +// +//! Sets the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32FIFOAddress is the starting address for the FIFO. +//! \param ui32FIFOSize is the size of the FIFO specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to set in the FIFO +//! configuration. +//! +//! This function configures the starting FIFO RAM address and size of the FIFO +//! for a given endpoint. Endpoint zero does not have a dynamically +//! configurable FIFO, so this function must not be called for endpoint zero. +//! The \e ui32FIFOSize parameter must be one of the values in the +//! \b USB_FIFO_SZ_ values. +//! +//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly +//! indicates the starting address in the USB controller's FIFO RAM. For +//! example, a value of 64 indicates that the FIFO starts 64 bytes into +//! the USB controller's FIFO memory. The \e ui32Flags value specifies whether +//! the endpoint's OUT or IN FIFO must be configured. If in host mode, use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use +//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOSZ, + ui32FIFOSize, 1); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOADD, + ui32FIFOAddress >> 3, 2); + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOSZ, + ui32FIFOSize, 1); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOADD, + ui32FIFOAddress >> 3, 2); + } +} + +//***************************************************************************** +// +//! Returns the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32FIFOAddress is the starting address for the FIFO. +//! \param pui32FIFOSize is the size of the FIFO as specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to retrieve from the FIFO +//! configuration. +//! +//! This function returns the starting address and size of the FIFO for a +//! given endpoint. Endpoint zero does not have a dynamically configurable +//! FIFO, so this function must not be called for endpoint zero. The +//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must +//! be read. If in host mode, the \e ui32Flags parameter must be +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the +//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or +//! \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Get the transmit FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_TXFIFOADD, + 2)) << 3; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_TXFIFOSZ, 1); + } + else + { + // + // Get the receive FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_RXFIFOADD, + 2)) << 3; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_RXFIFOSZ, 1); + } +} + +//***************************************************************************** +// +//! Configure the DMA settings for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Config specifies the configuration options for an endpoint. +//! +//! This function configures the DMA settings for a given endpoint without +//! changing other options that may already be configured. In order for the +//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be +//! called before starting the DMA transfer. The configuration +//! options are passed in the \e ui32Config parameter and can have the values +//! described below. +//! +//! One of the following values to specify direction: +//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with +//! DMA transfers from memory to the USB controller. +//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with +//! DMA transfers from the USB controller to memory. +//! +//! One of the following values: +//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for +//! transfers that do not span multiple packets or when interrupts are +//! required for each packet. +//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for +//! transfers that span multiple packets and do not require interrupts +//! between packets. +//! +//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: +//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers +//! to automatically be sent when a full packet is loaded into a FIFO. +//! This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go +//! out when the FIFO becomes full and the DMA has more data to send. +//! +//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: +//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA +//! transfers to automatically be acknowledged as they are received. This is +//! needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to +//! be received and acknowledged when the FIFO is emptied by the DMA +//! transfer. +//! +//! Values only used with \b USB_EP_HOST_IN: +//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA +//! transfers to automatically request a new IN transaction when the +//! previous transfer has emptied the FIFO. This is typically used in +//! conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers +//! can continue without interrupting the main processor. +//! +//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge +//! request and automatically generate a new IN request in host mode. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for receiving multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_1, USB_EP_HOST_IN | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_CLEAR | +//! USB_EP_AUTO_REQUEST); +//! \endverbatim +//! +//! \b Example: Set endpoint 2 transmit endpoint to automatically send each +//! packet in host mode when spanning multiple packets. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for transmitting multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_2, USB_EP_HOST_OUT | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_SET); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config) +{ + uint32_t ui32NewConfig; + + if(ui32Config & USB_EP_HOST_OUT) + { + // + // Clear mode and DMA enable. + // + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) & + ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_TXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_SET) + { + ui32NewConfig |= USB_TXCSRH1_AUTOSET; + } + + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + ui32NewConfig; + } + else + { + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) & + ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_RXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_CLEAR) + { + ui32NewConfig |= USB_RXCSRH1_AUTOCL; + } + if(ui32Config & USB_EP_AUTO_REQUEST) + { + ui32NewConfig |= USB_RXCSRH1_AUTORQ; + } + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + ui32NewConfig; + } +} + +//***************************************************************************** +// +//! Enable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction and what mode to use when +//! enabling DMA. +//! +//! This function enables DMA on a given endpoint and configures the mode +//! according to the values in the \e ui32Flags parameter. The \e ui32Flags +//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this +//! function is called the only DMA or error interrupts are generated by the +//! USB controller. +//! +//! \note If this function is called when an endpoint is configured in DMA +//! mode 0 the USB controller does not generate an interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // See if the transmit DMA is being enabled. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Enable DMA on the transmit endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |= + USB_TXCSRH1_DMAEN; + } + else + { + // + // Enable DMA on the receive endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |= + USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Disable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction to disable. +//! +//! This function disables DMA on a given endpoint to allow non-DMA USB +//! transactions to generate interrupts normally. The \e ui32Flags parameter +//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // If this was a request to disable DMA on the IN portion of the endpoint + // then handle it. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &= + ~USB_TXCSRH1_DMAEN; + } + else + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &= + ~USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Determine the number of bytes of data available in a given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the number of bytes of data currently available in +//! the FIFO for the given receive (OUT) endpoint. It may be used prior to +//! calling USBEndpointDataGet() to determine the size of buffer required to +//! hold the newly-received packet. +//! +//! \return This call returns the number of bytes available in a given endpoint +//! FIFO. +// +//***************************************************************************** +uint32_t +USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Is there a packet ready in the FIFO? + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + return(0); + } + + // + // Return the byte count in the FIFO. + // + return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint)); +} + +//***************************************************************************** +// +//! Retrieves data from the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used to return the data from +//! the FIFO. +//! \param pui32Size is initially the size of the buffer passed into this call +//! via the \e pui8Data parameter. It is set to the amount of data returned in +//! the buffer. +//! +//! This function returns the data from the FIFO for the given endpoint. +//! The \e pui32Size parameter indicates the size of the buffer passed in +//! the \e pui32Data parameter. The data in the \e pui32Size parameter is +//! changed to match the amount of data returned in the \e pui8Data parameter. +//! If a zero-byte packet is received, this call does not return an error but +//! instead just returns a zero in the \e pui32Size parameter. The only error +//! case occurs when there is no data packet available. +//! +//! \return This call returns 0, or -1 if no packet was received. +// +//***************************************************************************** +int32_t +USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size) +{ + uint32_t ui32Register, ui32ByteCount, ui32FIFO; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return(-1); + } + + // + // Get the byte count in the FIFO. + // + ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint); + + // + // Determine how many bytes are copied. + // + ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; + + // + // Return the number of bytes we are going to read. + // + *pui32Size = ui32ByteCount; + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Read the data out of the FIFO. + // + for(; ui32ByteCount > 0; ui32ByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pui8Data++ = HWREGB(ui32FIFO); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in device +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param bIsLastPacket indicates if this packet is the last one. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! The \e bIsLastPacket parameter is set to a \b true value if this is the +//! last in a series of data packets on endpoint zero. The \e bIsLastPacket +//! parameter is not used for endpoints other than endpoint zero. This call +//! can be used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Determine which endpoint is being acked. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) = + USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in host +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! This call is used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Clear RxPktRdy. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Puts data into the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used as the source for the +//! data to put into the FIFO. +//! \param ui32Size is the amount of data to put into the FIFO. +//! +//! This function puts the data from the \e pui8Data parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission, then +//! this call does not put any of the data into the FIFO and returns -1. Care +//! must be taken to not write more data than can fit into the FIFO +//! allocated by the call to USBFIFOConfigSet(). +//! +//! \return This call returns 0 on success, or -1 to indicate that the FIFO +//! is in use and cannot be written. +// +//***************************************************************************** +int32_t +USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size) +{ + uint32_t ui32FIFO; + uint8_t ui8TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui8TxPktRdy = USB_CSRL0_TXRDY; + } + else + { + ui8TxPktRdy = USB_TXCSRL1_TXRDY; + } + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy) + { + return(-1); + } + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Write the data to the FIFO. + // + for(; ui32Size > 0; ui32Size--) + { + HWREGB(ui32FIFO) = *pui8Data++; + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Starts the transfer of data from an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32TransType is set to indicate what type of data is being sent. +//! +//! This function starts the transfer of data from the FIFO for a given +//! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was +//! not enabled for the endpoint. Setting the \e ui32TransType parameter +//! allows the appropriate signaling on the USB bus for the type of transaction +//! being requested. The \e ui32TransType parameter must be one of the +//! following: +//! +//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a +//! sequence of IN transactions. +//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - \b USB_TRANS_STATUS for status results on endpoint zero. +//! +//! \return This call returns 0 on success, or -1 if a transmission is already +//! in progress. +// +//***************************************************************************** +int32_t +USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType) +{ + uint32_t ui32TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = ui32TransType & 0xff; + } + else + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = (ui32TransType >> 8) & 0xff; + } + + // + // Set TxPktRdy in order to send the data. + // + HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Forces a flush of an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies if the IN or OUT endpoint is accessed. +//! +//! This function forces the USB controller to flush out the data in the FIFO. +//! The function can be called with either host or device controllers and +//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if((HWREGB(ui32Base + USB_O_CSRL0) & + (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Make sure the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_TXCSRL1_TXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_FLUSH; + } + } + else + { + // + // Make sure that the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_RXCSRL1_RXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_FLUSH; + } + } + } +} + +//***************************************************************************** +// +//! Schedules a request for an IN transaction on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function schedules a request for an IN transaction. When the USB +//! device being communicated with responds with the data, the data can be +//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Set the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Clears a scheduled IN transaction for an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function clears a previously scheduled IN transaction if it is still +//! pending. This function is used to safely disable any scheduled IN +//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured +//! for communications with other devices. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Clear the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Issues a request for a status IN transaction on endpoint zero. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function is used to cause a request for a status IN transaction from +//! a device on endpoint zero. This function can only be used with endpoint +//! zero as that is the only control endpoint that supports this ability. This +//! function is used to complete the last phase of a control transaction to a +//! device and an interrupt is signaled when the status packet has been +//! received. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Set the request for a status IN transaction. + // + HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +//***************************************************************************** +// +//! Sets the functional address for the device that is connected to an +//! endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the functional address for the controller to use for +//! this endpoint. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the functional address for a device that is using +//! this endpoint for communication. This \e ui32Addr parameter is the address +//! of the target device that this endpoint is communicating with. The +//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive address is set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)) = ui32Addr; + } + else + { + // + // Set the receive address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)) = + ui32Addr; + } +} + +//***************************************************************************** +// +//! Gets the current functional device address for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current functional address that an endpoint is +//! using to communicate with a device. The \e ui32Flags parameter determines +//! if the IN or OUT endpoint's device address is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns the current function address being used by an endpoint. +// +//***************************************************************************** +uint32_t +USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1))); + } + else + { + // + // Return this endpoint's receive address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1))); + } +} + +//***************************************************************************** +// +//! Sets the hub address for the device that is connected to an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the hub address and port for the device using this +//! endpoint. The hub address must be defined in bits 0 through 6 with the +//! port number in bits 8 through 14. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the hub address for a device that is using this +//! endpoint for communication. The \e ui32Flags parameter determines if the +//! device address for the IN or the OUT endpoint is configured by this call +//! and sets the speed of the downstream device. Valid values are one of +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with +//! \b USB_EP_SPEED_LOW. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the hub transmit or receive address is being set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the hub transmit address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)) = ui32Addr; + } + else + { + // + // Set the hub receive address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)) = + ui32Addr; + } + + // + // Set the speed of communication for endpoint 0. This configuration is + // done here because it changes on a transaction-by-transaction basis for + // EP0. For other endpoints, this is set in USBHostEndpointConfig(). + // + if(ui32Endpoint == USB_EP_0) + { + if(ui32Flags & USB_EP_SPEED_FULL) + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; + } + else + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; + } + } +} + +//***************************************************************************** +// +//! Gets the current device hub address for this endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current hub address that an endpoint is using +//! to communicate with a device. The \e ui32Flags parameter determines if the +//! device address for the IN or OUT endpoint is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return This function returns the current hub address being used by an +//! endpoint. +// +//***************************************************************************** +uint32_t +USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the hub transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return the hub transmit address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1))); + } + else + { + // + // Return the hub receive address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1))); + } +} + +//***************************************************************************** +// +//! Sets the configuration for USB power fault. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies the configuration of the power fault. +//! +//! This function controls how the USB controller uses its external power +//! control pins (USBnPFLT and USBnEPEN). The flags specify the power +//! fault level sensitivity, the power fault action, and the power enable level +//! and source. +//! +//! One of the following can be selected as the power fault level sensitivity: +//! +//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin +//! being driven low. +//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin +//! being driven high. +//! +//! One of the following can be selected as the power fault action: +//! +//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault +//! detected. +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a +//! power fault. +//! +//! One of the following can be selected as the power enable level and source: +//! +//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller +//! when USBHostPwrEnable() is called. +//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB +//! controller when USBHostPwrEnable() is +//! called. +//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller +//! automatically if USBOTGSessionRequest() has +//! enabled a session. +//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB +//! controller automatically if +//! USBOTGSessionRequest() has enabled a +//! session. +//! +//! On devices that support the VBUS glitch filter, the +//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS +//! level caused by high power consumption. This feature is mainly used to +//! avoid causing VBUS errors caused by devices with high in-rush current. +//! +//! \note This function must only be called on microcontrollers that support +//! host mode or OTG operation. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | + USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | + USB_EPC_EPEN_M)) == 0); + + // + // If requested, enable VBUS droop detection on parts that support this + // feature. + // + HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16; + + // + // Set the power fault configuration as specified. This configuration + // does not change whether fault detection is enabled or not. + // + HWREGH(ui32Base + USB_O_EPC) = + (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) & + ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | + USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); +} + +//***************************************************************************** +// +//! Enables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables power fault detection in the USB controller. If the +//! USBnPFLT pin is not in use, this function must not be used. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Disables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables power fault detection in the USB controller. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Enables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables the USBnEPEN signal, which enables an external power +//! supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Disables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables the USBnEPEN signal, which disables an external +//! power supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Disable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Get the current frame number. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the last frame number received. +//! +//! \return The last frame number received. +// +//***************************************************************************** +uint32_t +USBFrameNumberGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Return the most recent frame number. + // + return(HWREGH(ui32Base + USB_O_FRAME)); +} + +//***************************************************************************** +// +//! Starts or ends a session. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if this call starts or ends a session. +//! +//! This function is used in OTG mode to start a session request or end a +//! session. If the \e bStart parameter is set to \b true, then this function +//! starts a session and if it is \b false it ends a session. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGSessionRequest(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Start or end the session as directed. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; + } + else + { + HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; + } +} + +//***************************************************************************** +// +//! Returns the absolute FIFO address for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! +//! This function returns the actual physical address of the FIFO. This +//! address is needed when the USB is going to be used with the uDMA +//! controller and the source or destination address must be set to the +//! physical FIFO address for a given endpoint. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Return the FIFO address for this endpoint. + // + return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2)); +} + +//***************************************************************************** +// +//! Returns the current operating mode of the controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current operating mode on USB controllers with +//! OTG or Dual mode functionality. +//! +//! For OTG controllers: +//! +//! The function returns one of the following values on OTG controllers: +//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE. +//! +//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode +//! on the B-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode +//! on the B-side of the cable. If an OTG session request is started with no +//! cable in place, this mode is the default. +//! +//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to +//! determine its role in the system. +//! +//! For Dual Mode controllers: +//! +//! The function returns one of the following values: +//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +//! +//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. +//! +//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. +//! +//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as +//! either a host or device. +//! +//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +// +//***************************************************************************** +uint32_t +USBModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return(HWREGB(ui32Base + USB_O_DEVCTL) & + (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | + USB_DEVCTL_VBUS_M)); +} + +//***************************************************************************** +// +//! Sets the DMA channel to use for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! \param ui32Channel specifies which DMA channel to use for which endpoint. +//! +//! This function is used to configure which DMA channel to use with a given +//! endpoint. Receive DMA channels can only be used with receive endpoints +//! and transmit DMA channels can only be used with transmit endpoints. As a +//! result, the 3 receive and 3 transmit DMA channels can be mapped to any +//! endpoint other than 0. The values that are passed into the +//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. +//! +//! \note This function only has an effect on microcontrollers that have the +//! ability to change the DMA channel for an endpoint. Calling this function +//! on other devices has no effect. +//! +//! \return None. +//! +//***************************************************************************** +void +USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel) +{ + uint32_t ui32Mask; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); +// ASSERT(ui32Channel <= UDMA_CHANNEL_USBEP3TX); + + // + // The input select mask must be shifted into the correct position + // based on the channel. + // + ui32Mask = (uint32_t)0xf << (ui32Channel * 4); + + // + // Clear out the current selection for the channel. + // + ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask); + + // + // The input select is now shifted into the correct position based on the + // channel. + // + ui32Mask |= ((uint32_t)USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4); + + // + // Write the value out to the register. + // + HWREG(ui32Base + USB_O_DMASEL) = ui32Mask; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to host. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to host mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of host mode. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to device mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Set the USB controller mode to device. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to OTG. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to OTG mode. This +//! function is only valid on microcontrollers that have the OTG capabilities. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Disable the override of the USB controller mode when running on an OTG + // device. + // + HWREGB(ui32Base + USB_O_GPCS) = 0; +} + +//***************************************************************************** +// +//! Powers off the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers off the USB PHY, reducing the current consuption +//! of the device. While in the powered-off state, the USB controller is +//! unable to operate. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOff(uint32_t ui32Base) +{ + // + // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Powers on the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers on the USB PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function must +//! only be called if USBPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOn(uint32_t ui32Base) +{ + // + // Clear the PWRDNPHY bit in the PHY, putting it into normal operating + // mode. + // + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Sets the number of packets to request when transferring multiple bulk +//! packets. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint index to target for this write. +//! \param ui32Count is the number of packets to request. +//! +//! This function sets the number of consecutive bulk packets to request +//! when transferring multiple bulk packets with DMA. +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count) +{ + HWREG(ui32Base + USB_O_RQPKTCOUNT1 + + (0x4 * (USBEPToIndex(ui32Endpoint) - 1))) = ui32Count; +} + +//***************************************************************************** +// +//! Returns the number of USB endpoint pairs on the device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the number of endpoint pairs supported by the USB +//! controller corresponding to the passed base address. The value returned is +//! the number of IN or OUT endpoints available and does not include endpoint 0 +//! (the control endpoint). For example, if 15 is returned, there are 15 IN +//! and 15 OUT endpoints available in addition to endpoint 0. +//! +//! \return Returns the number of IN or OUT endpoints available. +// +//***************************************************************************** +uint32_t +USBNumEndpointsGet(uint32_t ui32Base) +{ + // + // Read the number of endpoints from the hardware. The number of TX and + // RX endpoints are always the same. + // + return(15); +} + diff --git a/bsp/tms320f28379d/libraries/common/source/usb_hal.c b/bsp/tms320f28379d/libraries/common/source/usb_hal.c new file mode 100644 index 00000000000..f73ff48a866 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/source/usb_hal.c @@ -0,0 +1,163 @@ +//########################################################################### +// +// FILE: usb_hal.c +// +// TITLE: Wrapper for interrupt functions and USB support pins. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_usb.h" +#include "usb_hal.h" +#include "usb.h" +#include "include/usblib.h" +#include "include/usblibpriv.h" +#include "include/device/usbdevice.h" +#include "include/host/usbhost.h" +#include "include/host/usbhostpriv.h" +#include "include/usblibpriv.h" + +//***************************************************************************** +// +//! \addtogroup c2000_specific +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Enables USB related GPIOs to perform their USB function. +// +//***************************************************************************** +void USBGPIOEnable(void) +{ + EALLOW; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 1; + GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 1; + + //VBUS + GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0; + //ID + GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0; + + GpioCtrlRegs.GPDGMUX2.bit.GPIO120 = 3; + GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 3; + GpioCtrlRegs.GPDGMUX2.bit.GPIO121 = 3; + GpioCtrlRegs.GPDMUX2.bit.GPIO121 = 3; + EDIS; +} + +//***************************************************************************** +// +//! Disables USB related GPIOs from performing their USB function. +// +//***************************************************************************** +void USBGPIODisable(void) +{ + EALLOW; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 0; + GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 0; + + GpioCtrlRegs.GPDGMUX2.bit.GPIO120 = 0; + GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 0; + GpioCtrlRegs.GPDGMUX2.bit.GPIO121 = 0; + GpioCtrlRegs.GPDMUX2.bit.GPIO121 = 0; + EDIS; +} + + +//***************************************************************************** +// +//! Wrapper function to implement mS based delay for USB functions +// +//***************************************************************************** +void USBDelay(uint32_t ui32Delay) +{ + DELAY_US(ui32Delay*1000); +} + +//***************************************************************************** +// +//! Device interrupt service routine wrapper to make ISR compatible with +//! C2000 PIE controller. +// +//***************************************************************************** + +__interrupt void +f28x_USB0DeviceIntHandler(void) +{ + USB0DeviceIntHandler(); + PieCtrlRegs.PIEACK.all |= 0x0100; +} +//***************************************************************************** +// +//! Host interrupt service routine wrapper to make ISR compatible with +//! C2000 PIE controller. +// +//***************************************************************************** +__interrupt void +f28x_USB0HostIntHandler(void) +{ + USB0HostIntHandler(); + PieCtrlRegs.PIEACK.all |= 0x0100; +} + +//***************************************************************************** +// +//! Dual mode interrupt service routine wrapper to make ISR compatible with +//! C2000 PIE controller. +// +//***************************************************************************** +__interrupt void +f28x_USB0DualModeIntHandler(void) +{ + USB0DualModeIntHandler(); + PieCtrlRegs.PIEACK.all |= 0x0100; +} + +//***************************************************************************** +// +// Close the c2000_specific Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28377D.ccxml b/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28377D.ccxml new file mode 100644 index 00000000000..79dd5cc44ec --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28377D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28379D.ccxml b/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28379D.ccxml new file mode 100644 index 00000000000..bd5fa498938 --- /dev/null +++ b/bsp/tms320f28379d/libraries/common/targetConfigs/TMS320F28379D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd new file mode 100644 index 00000000000..2f913258671 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd @@ -0,0 +1,287 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CLB_XBAR : origin = 0x007A40, length = 0x000040 + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + EPWM_XBAR : origin = 0x007A00, length = 0x000040 + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + + OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + ROMPREFETCH : origin = 0x05E608, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + EMIF2CONFIG : origin = 0x05F4A0, length = 0x000020 /* Emif-2 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + ROMWAITSTATE : origin = 0x05F540, length = 0x000002 /* ROM Config registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + + UPP : origin = 0x006200, length = 0x000100 /* uPP registers */ + + DEV_CFG : origin = 0x05D000, length = 0x000180 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + INPUT_XBAR : origin = 0x007900, length = 0x000020 + XBAR : origin = 0x007920, length = 0x000020 + SYNC_SOC : origin = 0x007940, length = 0x000010 + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile : TYPE=DSECT + GROUP + { + EmuBModeVar : TYPE=DSECT + EmuBootPinsVar : TYPE=DSECT + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + ClbXbarRegsFile : > CLB_XBAR PAGE = 1 + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + OutputXbarRegsFile : > OUTPUT_XBAR PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + InputXbarRegsFile : > INPUT_XBAR PAGE = 1 + XbarRegsFile : > XBAR PAGE = 1 + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + RomPrefetchRegsFile : > ROMPREFETCH, PAGE = 1 + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + Emif2ConfigRegsFile : > EMIF2CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + RomWaitStateRegsFile : > ROMWAITSTATE, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + UppRegsFile : > UPP, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + DevCfgRegsFile : > DEV_CFG, PAGE = 1 + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + SyncSocRegsFile : > SYNC_SOC, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd new file mode 100644 index 00000000000..189250ad3bc --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd @@ -0,0 +1,255 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + + DEV_CFG : origin = 0x05D000, length = 0x000200 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile : TYPE=DSECT + GROUP + { + EmuBModeVar : TYPE=DSECT + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + DevCfgRegsFile : > DEV_CFG, PAGE = 1 + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd new file mode 100644 index 00000000000..c125c94918c --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd @@ -0,0 +1,287 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CLB_XBAR : origin = 0x007A40, length = 0x000040 + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + EPWM_XBAR : origin = 0x007A00, length = 0x000040 + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + + OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + ROMPREFETCH : origin = 0x05E608, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + EMIF2CONFIG : origin = 0x05F4A0, length = 0x000020 /* Emif-2 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + ROMWAITSTATE : origin = 0x05F540, length = 0x000002 /* ROM Config registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + + UPP : origin = 0x006200, length = 0x000100 /* uPP registers */ + + DEV_CFG : origin = 0x05D000, length = 0x000180 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + INPUT_XBAR : origin = 0x007900, length = 0x000020 + XBAR : origin = 0x007920, length = 0x000020 + SYNC_SOC : origin = 0x007940, length = 0x000010 + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile + GROUP + { + EmuBModeVar + EmuBootPinsVar + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + ClbXbarRegsFile : > CLB_XBAR PAGE = 1 + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + OutputXbarRegsFile : > OUTPUT_XBAR PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + InputXbarRegsFile : > INPUT_XBAR PAGE = 1 + XbarRegsFile : > XBAR PAGE = 1 + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + RomPrefetchRegsFile : > ROMPREFETCH, PAGE = 1 + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + Emif2ConfigRegsFile : > EMIF2CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + RomWaitStateRegsFile : > ROMWAITSTATE, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + UppRegsFile : > UPP, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + DevCfgRegsFile : > DEV_CFG, PAGE = 1 + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + SyncSocRegsFile : > SYNC_SOC, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd new file mode 100644 index 00000000000..af9414a90de --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd @@ -0,0 +1,251 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile + GROUP + { + EmuBModeVar + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_adc.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_adc.h new file mode 100644 index 00000000000..cdcee353fb6 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_adc.h @@ -0,0 +1,1067 @@ +//########################################################################### +// +// FILE: F2837xD_adc.h +// +// TITLE: ADC Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_ADC_H__ +#define __F2837xD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ADC Individual Register Bit Definitions: + +struct ADCCTL1_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 INTPULSEPOS:1; // 2 ADC Interrupt Pulse Position + Uint16 rsvd2:4; // 6:3 Reserved + Uint16 ADCPWDNZ:1; // 7 ADC Power Down + Uint16 ADCBSYCHN:4; // 11:8 ADC Busy Channel + Uint16 rsvd3:1; // 12 Reserved + Uint16 ADCBSY:1; // 13 ADC Busy + Uint16 rsvd4:2; // 15:14 Reserved +}; + +union ADCCTL1_REG { + Uint16 all; + struct ADCCTL1_BITS bit; +}; + +struct ADCCTL2_BITS { // bits description + Uint16 PRESCALE:4; // 3:0 ADC Clock Prescaler + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 RESOLUTION:1; // 6 SOC Conversion Resolution + Uint16 SIGNALMODE:1; // 7 SOC Signaling Mode + Uint16 rsvd2:5; // 12:8 Reserved + Uint16 rsvd3:3; // 15:13 Reserved +}; + +union ADCCTL2_REG { + Uint16 all; + struct ADCCTL2_BITS bit; +}; + +struct ADCBURSTCTL_BITS { // bits description + Uint16 BURSTTRIGSEL:6; // 5:0 SOC Burst Trigger Source Select + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 BURSTSIZE:4; // 11:8 SOC Burst Size Select + Uint16 rsvd2:3; // 14:12 Reserved + Uint16 BURSTEN:1; // 15 SOC Burst Mode Enable +}; + +union ADCBURSTCTL_REG { + Uint16 all; + struct ADCBURSTCTL_BITS bit; +}; + +struct ADCINTFLG_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTFLG_REG { + Uint16 all; + struct ADCINTFLG_BITS bit; +}; + +struct ADCINTFLGCLR_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Clear + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Clear + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Clear + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Clear + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTFLGCLR_REG { + Uint16 all; + struct ADCINTFLGCLR_BITS bit; +}; + +struct ADCINTOVF_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Flags + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Flags + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Flags + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Flags + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTOVF_REG { + Uint16 all; + struct ADCINTOVF_BITS bit; +}; + +struct ADCINTOVFCLR_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Clear Bits + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Clear Bits + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Clear Bits + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Clear Bits + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTOVFCLR_REG { + Uint16 all; + struct ADCINTOVFCLR_BITS bit; +}; + +struct ADCINTSEL1N2_BITS { // bits description + Uint16 INT1SEL:4; // 3:0 ADCINT1 EOC Source Select + Uint16 rsvd1:1; // 4 Reserved + Uint16 INT1E:1; // 5 ADCINT1 Interrupt Enable + Uint16 INT1CONT:1; // 6 ADCINT1 Continuous Mode Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 INT2SEL:4; // 11:8 ADCINT2 EOC Source Select + Uint16 rsvd3:1; // 12 Reserved + Uint16 INT2E:1; // 13 ADCINT2 Interrupt Enable + Uint16 INT2CONT:1; // 14 ADCINT2 Continuous Mode Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCINTSEL1N2_REG { + Uint16 all; + struct ADCINTSEL1N2_BITS bit; +}; + +struct ADCINTSEL3N4_BITS { // bits description + Uint16 INT3SEL:4; // 3:0 ADCINT3 EOC Source Select + Uint16 rsvd1:1; // 4 Reserved + Uint16 INT3E:1; // 5 ADCINT3 Interrupt Enable + Uint16 INT3CONT:1; // 6 ADCINT3 Continuous Mode Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 INT4SEL:4; // 11:8 ADCINT4 EOC Source Select + Uint16 rsvd3:1; // 12 Reserved + Uint16 INT4E:1; // 13 ADCINT4 Interrupt Enable + Uint16 INT4CONT:1; // 14 ADCINT4 Continuous Mode Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCINTSEL3N4_REG { + Uint16 all; + struct ADCINTSEL3N4_BITS bit; +}; + +struct ADCSOCPRICTL_BITS { // bits description + Uint16 SOCPRIORITY:5; // 4:0 SOC Priority + Uint16 RRPOINTER:5; // 9:5 Round Robin Pointer + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCSOCPRICTL_REG { + Uint16 all; + struct ADCSOCPRICTL_BITS bit; +}; + +struct ADCINTSOCSEL1_BITS { // bits description + Uint16 SOC0:2; // 1:0 SOC0 ADC Interrupt Trigger Select + Uint16 SOC1:2; // 3:2 SOC1 ADC Interrupt Trigger Select + Uint16 SOC2:2; // 5:4 SOC2 ADC Interrupt Trigger Select + Uint16 SOC3:2; // 7:6 SOC3 ADC Interrupt Trigger Select + Uint16 SOC4:2; // 9:8 SOC4 ADC Interrupt Trigger Select + Uint16 SOC5:2; // 11:10 SOC5 ADC Interrupt Trigger Select + Uint16 SOC6:2; // 13:12 SOC6 ADC Interrupt Trigger Select + Uint16 SOC7:2; // 15:14 SOC7 ADC Interrupt Trigger Select +}; + +union ADCINTSOCSEL1_REG { + Uint16 all; + struct ADCINTSOCSEL1_BITS bit; +}; + +struct ADCINTSOCSEL2_BITS { // bits description + Uint16 SOC8:2; // 1:0 SOC8 ADC Interrupt Trigger Select + Uint16 SOC9:2; // 3:2 SOC9 ADC Interrupt Trigger Select + Uint16 SOC10:2; // 5:4 SOC10 ADC Interrupt Trigger Select + Uint16 SOC11:2; // 7:6 SOC11 ADC Interrupt Trigger Select + Uint16 SOC12:2; // 9:8 SOC12 ADC Interrupt Trigger Select + Uint16 SOC13:2; // 11:10 SOC13 ADC Interrupt Trigger Select + Uint16 SOC14:2; // 13:12 SOC14 ADC Interrupt Trigger Select + Uint16 SOC15:2; // 15:14 SOC15 ADC Interrupt Trigger Select +}; + +union ADCINTSOCSEL2_REG { + Uint16 all; + struct ADCINTSOCSEL2_BITS bit; +}; + +struct ADCSOCFLG1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Start of Conversion Flag + Uint16 SOC1:1; // 1 SOC1 Start of Conversion Flag + Uint16 SOC2:1; // 2 SOC2 Start of Conversion Flag + Uint16 SOC3:1; // 3 SOC3 Start of Conversion Flag + Uint16 SOC4:1; // 4 SOC4 Start of Conversion Flag + Uint16 SOC5:1; // 5 SOC5 Start of Conversion Flag + Uint16 SOC6:1; // 6 SOC6 Start of Conversion Flag + Uint16 SOC7:1; // 7 SOC7 Start of Conversion Flag + Uint16 SOC8:1; // 8 SOC8 Start of Conversion Flag + Uint16 SOC9:1; // 9 SOC9 Start of Conversion Flag + Uint16 SOC10:1; // 10 SOC10 Start of Conversion Flag + Uint16 SOC11:1; // 11 SOC11 Start of Conversion Flag + Uint16 SOC12:1; // 12 SOC12 Start of Conversion Flag + Uint16 SOC13:1; // 13 SOC13 Start of Conversion Flag + Uint16 SOC14:1; // 14 SOC14 Start of Conversion Flag + Uint16 SOC15:1; // 15 SOC15 Start of Conversion Flag +}; + +union ADCSOCFLG1_REG { + Uint16 all; + struct ADCSOCFLG1_BITS bit; +}; + +struct ADCSOCFRC1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Force Start of Conversion Bit + Uint16 SOC1:1; // 1 SOC1 Force Start of Conversion Bit + Uint16 SOC2:1; // 2 SOC2 Force Start of Conversion Bit + Uint16 SOC3:1; // 3 SOC3 Force Start of Conversion Bit + Uint16 SOC4:1; // 4 SOC4 Force Start of Conversion Bit + Uint16 SOC5:1; // 5 SOC5 Force Start of Conversion Bit + Uint16 SOC6:1; // 6 SOC6 Force Start of Conversion Bit + Uint16 SOC7:1; // 7 SOC7 Force Start of Conversion Bit + Uint16 SOC8:1; // 8 SOC8 Force Start of Conversion Bit + Uint16 SOC9:1; // 9 SOC9 Force Start of Conversion Bit + Uint16 SOC10:1; // 10 SOC10 Force Start of Conversion Bit + Uint16 SOC11:1; // 11 SOC11 Force Start of Conversion Bit + Uint16 SOC12:1; // 12 SOC12 Force Start of Conversion Bit + Uint16 SOC13:1; // 13 SOC13 Force Start of Conversion Bit + Uint16 SOC14:1; // 14 SOC14 Force Start of Conversion Bit + Uint16 SOC15:1; // 15 SOC15 Force Start of Conversion Bit +}; + +union ADCSOCFRC1_REG { + Uint16 all; + struct ADCSOCFRC1_BITS bit; +}; + +struct ADCSOCOVF1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Start of Conversion Overflow Flag + Uint16 SOC1:1; // 1 SOC1 Start of Conversion Overflow Flag + Uint16 SOC2:1; // 2 SOC2 Start of Conversion Overflow Flag + Uint16 SOC3:1; // 3 SOC3 Start of Conversion Overflow Flag + Uint16 SOC4:1; // 4 SOC4 Start of Conversion Overflow Flag + Uint16 SOC5:1; // 5 SOC5 Start of Conversion Overflow Flag + Uint16 SOC6:1; // 6 SOC6 Start of Conversion Overflow Flag + Uint16 SOC7:1; // 7 SOC7 Start of Conversion Overflow Flag + Uint16 SOC8:1; // 8 SOC8 Start of Conversion Overflow Flag + Uint16 SOC9:1; // 9 SOC9 Start of Conversion Overflow Flag + Uint16 SOC10:1; // 10 SOC10 Start of Conversion Overflow Flag + Uint16 SOC11:1; // 11 SOC11 Start of Conversion Overflow Flag + Uint16 SOC12:1; // 12 SOC12 Start of Conversion Overflow Flag + Uint16 SOC13:1; // 13 SOC13 Start of Conversion Overflow Flag + Uint16 SOC14:1; // 14 SOC14 Start of Conversion Overflow Flag + Uint16 SOC15:1; // 15 SOC15 Start of Conversion Overflow Flag +}; + +union ADCSOCOVF1_REG { + Uint16 all; + struct ADCSOCOVF1_BITS bit; +}; + +struct ADCSOCOVFCLR1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Clear Start of Conversion Overflow Bit + Uint16 SOC1:1; // 1 SOC1 Clear Start of Conversion Overflow Bit + Uint16 SOC2:1; // 2 SOC2 Clear Start of Conversion Overflow Bit + Uint16 SOC3:1; // 3 SOC3 Clear Start of Conversion Overflow Bit + Uint16 SOC4:1; // 4 SOC4 Clear Start of Conversion Overflow Bit + Uint16 SOC5:1; // 5 SOC5 Clear Start of Conversion Overflow Bit + Uint16 SOC6:1; // 6 SOC6 Clear Start of Conversion Overflow Bit + Uint16 SOC7:1; // 7 SOC7 Clear Start of Conversion Overflow Bit + Uint16 SOC8:1; // 8 SOC8 Clear Start of Conversion Overflow Bit + Uint16 SOC9:1; // 9 SOC9 Clear Start of Conversion Overflow Bit + Uint16 SOC10:1; // 10 SOC10 Clear Start of Conversion Overflow Bit + Uint16 SOC11:1; // 11 SOC11 Clear Start of Conversion Overflow Bit + Uint16 SOC12:1; // 12 SOC12 Clear Start of Conversion Overflow Bit + Uint16 SOC13:1; // 13 SOC13 Clear Start of Conversion Overflow Bit + Uint16 SOC14:1; // 14 SOC14 Clear Start of Conversion Overflow Bit + Uint16 SOC15:1; // 15 SOC15 Clear Start of Conversion Overflow Bit +}; + +union ADCSOCOVFCLR1_REG { + Uint16 all; + struct ADCSOCOVFCLR1_BITS bit; +}; + +struct ADCSOC0CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC0 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC0 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC0 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC0CTL_REG { + Uint32 all; + struct ADCSOC0CTL_BITS bit; +}; + +struct ADCSOC1CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC1 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC1 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC1 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC1CTL_REG { + Uint32 all; + struct ADCSOC1CTL_BITS bit; +}; + +struct ADCSOC2CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC2 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC2 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC2 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC2CTL_REG { + Uint32 all; + struct ADCSOC2CTL_BITS bit; +}; + +struct ADCSOC3CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC3 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC3 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC3 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC3CTL_REG { + Uint32 all; + struct ADCSOC3CTL_BITS bit; +}; + +struct ADCSOC4CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC4 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC4 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC4 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC4CTL_REG { + Uint32 all; + struct ADCSOC4CTL_BITS bit; +}; + +struct ADCSOC5CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC5 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC5 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC5 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC5CTL_REG { + Uint32 all; + struct ADCSOC5CTL_BITS bit; +}; + +struct ADCSOC6CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC6 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC6 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC6 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC6CTL_REG { + Uint32 all; + struct ADCSOC6CTL_BITS bit; +}; + +struct ADCSOC7CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC7 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC7 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC7 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC7CTL_REG { + Uint32 all; + struct ADCSOC7CTL_BITS bit; +}; + +struct ADCSOC8CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC8 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC8 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC8 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC8CTL_REG { + Uint32 all; + struct ADCSOC8CTL_BITS bit; +}; + +struct ADCSOC9CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC9 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC9 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC9 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC9CTL_REG { + Uint32 all; + struct ADCSOC9CTL_BITS bit; +}; + +struct ADCSOC10CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC10 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC10 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC10 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC10CTL_REG { + Uint32 all; + struct ADCSOC10CTL_BITS bit; +}; + +struct ADCSOC11CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC11 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC11 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC11 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC11CTL_REG { + Uint32 all; + struct ADCSOC11CTL_BITS bit; +}; + +struct ADCSOC12CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC12 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC12 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC12 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC12CTL_REG { + Uint32 all; + struct ADCSOC12CTL_BITS bit; +}; + +struct ADCSOC13CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC13 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC13 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC13 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC13CTL_REG { + Uint32 all; + struct ADCSOC13CTL_BITS bit; +}; + +struct ADCSOC14CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC14 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC14 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC14 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC14CTL_REG { + Uint32 all; + struct ADCSOC14CTL_BITS bit; +}; + +struct ADCSOC15CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC15 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC15 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC15 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC15CTL_REG { + Uint32 all; + struct ADCSOC15CTL_BITS bit; +}; + +struct ADCEVTSTAT_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Flag + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Flag + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Flag + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Flag + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Flag + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Flag + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Flag + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Flag + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Flag + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Flag + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Flag + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Flag + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTSTAT_REG { + Uint16 all; + struct ADCEVTSTAT_BITS bit; +}; + +struct ADCEVTCLR_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Clear + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Clear + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Clear + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Clear + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Clear + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Clear + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Clear + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Clear + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Clear + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Clear + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Clear + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Clear + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTCLR_REG { + Uint16 all; + struct ADCEVTCLR_BITS bit; +}; + +struct ADCEVTSEL_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Event Enable + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Event Enable + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Event Enable + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Event Enable + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Event Enable + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Event Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Event Enable + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Event Enable + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Event Enable + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Event Enable + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Event Enable + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Event Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTSEL_REG { + Uint16 all; + struct ADCEVTSEL_BITS bit; +}; + +struct ADCEVTINTSEL_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Interrupt Enable + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Interrupt Enable + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Interrupt Enable + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Interrupt Enable + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Interrupt Enable + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Interrupt Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Interrupt Enable + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Interrupt Enable + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Interrupt Enable + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Interrupt Enable + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Interrupt Enable + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Interrupt Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTINTSEL_REG { + Uint16 all; + struct ADCEVTINTSEL_BITS bit; +}; + +struct ADCCOUNTER_BITS { // bits description + Uint16 FREECOUNT:12; // 11:0 ADC Free Running Counter Value + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCCOUNTER_REG { + Uint16 all; + struct ADCCOUNTER_BITS bit; +}; + +struct ADCREV_BITS { // bits description + Uint16 TYPE:8; // 7:0 ADC Type + Uint16 REV:8; // 15:8 ADC Revision +}; + +union ADCREV_REG { + Uint16 all; + struct ADCREV_BITS bit; +}; + +struct ADCOFFTRIM_BITS { // bits description + Uint16 OFFTRIM:8; // 7:0 ADC Offset Trim + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ADCOFFTRIM_REG { + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADCPPB1CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 1 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 1 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB1CONFIG_REG { + Uint16 all; + struct ADCPPB1CONFIG_BITS bit; +}; + +struct ADCPPB1STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 1 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB1STAMP_REG { + Uint16 all; + struct ADCPPB1STAMP_BITS bit; +}; + +struct ADCPPB1OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB1OFFCAL_REG { + Uint16 all; + struct ADCPPB1OFFCAL_BITS bit; +}; + +struct ADCPPB1TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 1 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB1TRIPHI_REG { + Uint32 all; + struct ADCPPB1TRIPHI_BITS bit; +}; + +struct ADCPPB1TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 1 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 1 Request Time Stamp +}; + +union ADCPPB1TRIPLO_REG { + Uint32 all; + struct ADCPPB1TRIPLO_BITS bit; +}; + +struct ADCPPB2CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 2 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 2 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB2CONFIG_REG { + Uint16 all; + struct ADCPPB2CONFIG_BITS bit; +}; + +struct ADCPPB2STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 2 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB2STAMP_REG { + Uint16 all; + struct ADCPPB2STAMP_BITS bit; +}; + +struct ADCPPB2OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB2OFFCAL_REG { + Uint16 all; + struct ADCPPB2OFFCAL_BITS bit; +}; + +struct ADCPPB2TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 2 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB2TRIPHI_REG { + Uint32 all; + struct ADCPPB2TRIPHI_BITS bit; +}; + +struct ADCPPB2TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 2 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 2 Request Time Stamp +}; + +union ADCPPB2TRIPLO_REG { + Uint32 all; + struct ADCPPB2TRIPLO_BITS bit; +}; + +struct ADCPPB3CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 3 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 3 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB3CONFIG_REG { + Uint16 all; + struct ADCPPB3CONFIG_BITS bit; +}; + +struct ADCPPB3STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 3 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB3STAMP_REG { + Uint16 all; + struct ADCPPB3STAMP_BITS bit; +}; + +struct ADCPPB3OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB3OFFCAL_REG { + Uint16 all; + struct ADCPPB3OFFCAL_BITS bit; +}; + +struct ADCPPB3TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 3 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB3TRIPHI_REG { + Uint32 all; + struct ADCPPB3TRIPHI_BITS bit; +}; + +struct ADCPPB3TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 3 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 3 Request Time Stamp +}; + +union ADCPPB3TRIPLO_REG { + Uint32 all; + struct ADCPPB3TRIPLO_BITS bit; +}; + +struct ADCPPB4CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 4 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 4 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB4CONFIG_REG { + Uint16 all; + struct ADCPPB4CONFIG_BITS bit; +}; + +struct ADCPPB4STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 4 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB4STAMP_REG { + Uint16 all; + struct ADCPPB4STAMP_BITS bit; +}; + +struct ADCPPB4OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB4OFFCAL_REG { + Uint16 all; + struct ADCPPB4OFFCAL_BITS bit; +}; + +struct ADCPPB4TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 4 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB4TRIPHI_REG { + Uint32 all; + struct ADCPPB4TRIPHI_BITS bit; +}; + +struct ADCPPB4TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 4 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 4 Request Time Stamp +}; + +union ADCPPB4TRIPLO_REG { + Uint32 all; + struct ADCPPB4TRIPLO_BITS bit; +}; + +struct ADC_REGS { + union ADCCTL1_REG ADCCTL1; // ADC Control 1 Register + union ADCCTL2_REG ADCCTL2; // ADC Control 2 Register + union ADCBURSTCTL_REG ADCBURSTCTL; // ADC Burst Control Register + union ADCINTFLG_REG ADCINTFLG; // ADC Interrupt Flag Register + union ADCINTFLGCLR_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear Register + union ADCINTOVF_REG ADCINTOVF; // ADC Interrupt Overflow Register + union ADCINTOVFCLR_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear Register + union ADCINTSEL1N2_REG ADCINTSEL1N2; // ADC Interrupt 1 and 2 Selection Register + union ADCINTSEL3N4_REG ADCINTSEL3N4; // ADC Interrupt 3 and 4 Selection Register + union ADCSOCPRICTL_REG ADCSOCPRICTL; // ADC SOC Priority Control Register + union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 Register + union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 Register + union ADCSOCFLG1_REG ADCSOCFLG1; // ADC SOC Flag 1 Register + union ADCSOCFRC1_REG ADCSOCFRC1; // ADC SOC Force 1 Register + union ADCSOCOVF1_REG ADCSOCOVF1; // ADC SOC Overflow 1 Register + union ADCSOCOVFCLR1_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 Register + union ADCSOC0CTL_REG ADCSOC0CTL; // ADC SOC0 Control Register + union ADCSOC1CTL_REG ADCSOC1CTL; // ADC SOC1 Control Register + union ADCSOC2CTL_REG ADCSOC2CTL; // ADC SOC2 Control Register + union ADCSOC3CTL_REG ADCSOC3CTL; // ADC SOC3 Control Register + union ADCSOC4CTL_REG ADCSOC4CTL; // ADC SOC4 Control Register + union ADCSOC5CTL_REG ADCSOC5CTL; // ADC SOC5 Control Register + union ADCSOC6CTL_REG ADCSOC6CTL; // ADC SOC6 Control Register + union ADCSOC7CTL_REG ADCSOC7CTL; // ADC SOC7 Control Register + union ADCSOC8CTL_REG ADCSOC8CTL; // ADC SOC8 Control Register + union ADCSOC9CTL_REG ADCSOC9CTL; // ADC SOC9 Control Register + union ADCSOC10CTL_REG ADCSOC10CTL; // ADC SOC10 Control Register + union ADCSOC11CTL_REG ADCSOC11CTL; // ADC SOC11 Control Register + union ADCSOC12CTL_REG ADCSOC12CTL; // ADC SOC12 Control Register + union ADCSOC13CTL_REG ADCSOC13CTL; // ADC SOC13 Control Register + union ADCSOC14CTL_REG ADCSOC14CTL; // ADC SOC14 Control Register + union ADCSOC15CTL_REG ADCSOC15CTL; // ADC SOC15 Control Register + union ADCEVTSTAT_REG ADCEVTSTAT; // ADC Event Status Register + Uint16 rsvd1; // Reserved + union ADCEVTCLR_REG ADCEVTCLR; // ADC Event Clear Register + Uint16 rsvd2; // Reserved + union ADCEVTSEL_REG ADCEVTSEL; // ADC Event Selection Register + Uint16 rsvd3; // Reserved + union ADCEVTINTSEL_REG ADCEVTINTSEL; // ADC Event Interrupt Selection Register + Uint16 rsvd4[2]; // Reserved + union ADCCOUNTER_REG ADCCOUNTER; // ADC Counter Register + union ADCREV_REG ADCREV; // ADC Revision Register + union ADCOFFTRIM_REG ADCOFFTRIM; // ADC Offset Trim Register + Uint16 rsvd5[4]; // Reserved + union ADCPPB1CONFIG_REG ADCPPB1CONFIG; // ADC PPB1 Config Register + union ADCPPB1STAMP_REG ADCPPB1STAMP; // ADC PPB1 Sample Delay Time Stamp Register + union ADCPPB1OFFCAL_REG ADCPPB1OFFCAL; // ADC PPB1 Offset Calibration Register + Uint16 ADCPPB1OFFREF; // ADC PPB1 Offset Reference Register + union ADCPPB1TRIPHI_REG ADCPPB1TRIPHI; // ADC PPB1 Trip High Register + union ADCPPB1TRIPLO_REG ADCPPB1TRIPLO; // ADC PPB1 Trip Low/Trigger Time Stamp Register + union ADCPPB2CONFIG_REG ADCPPB2CONFIG; // ADC PPB2 Config Register + union ADCPPB2STAMP_REG ADCPPB2STAMP; // ADC PPB2 Sample Delay Time Stamp Register + union ADCPPB2OFFCAL_REG ADCPPB2OFFCAL; // ADC PPB2 Offset Calibration Register + Uint16 ADCPPB2OFFREF; // ADC PPB2 Offset Reference Register + union ADCPPB2TRIPHI_REG ADCPPB2TRIPHI; // ADC PPB2 Trip High Register + union ADCPPB2TRIPLO_REG ADCPPB2TRIPLO; // ADC PPB2 Trip Low/Trigger Time Stamp Register + union ADCPPB3CONFIG_REG ADCPPB3CONFIG; // ADC PPB3 Config Register + union ADCPPB3STAMP_REG ADCPPB3STAMP; // ADC PPB3 Sample Delay Time Stamp Register + union ADCPPB3OFFCAL_REG ADCPPB3OFFCAL; // ADC PPB3 Offset Calibration Register + Uint16 ADCPPB3OFFREF; // ADC PPB3 Offset Reference Register + union ADCPPB3TRIPHI_REG ADCPPB3TRIPHI; // ADC PPB3 Trip High Register + union ADCPPB3TRIPLO_REG ADCPPB3TRIPLO; // ADC PPB3 Trip Low/Trigger Time Stamp Register + union ADCPPB4CONFIG_REG ADCPPB4CONFIG; // ADC PPB4 Config Register + union ADCPPB4STAMP_REG ADCPPB4STAMP; // ADC PPB4 Sample Delay Time Stamp Register + union ADCPPB4OFFCAL_REG ADCPPB4OFFCAL; // ADC PPB4 Offset Calibration Register + Uint16 ADCPPB4OFFREF; // ADC PPB4 Offset Reference Register + union ADCPPB4TRIPHI_REG ADCPPB4TRIPHI; // ADC PPB4 Trip High Register + union ADCPPB4TRIPLO_REG ADCPPB4TRIPLO; // ADC PPB4 Trip Low/Trigger Time Stamp Register + Uint16 rsvd6[16]; // Reserved + Uint32 ADCINLTRIM1; // ADC Linearity Trim 1 Register + Uint32 ADCINLTRIM2; // ADC Linearity Trim 2 Register + Uint32 ADCINLTRIM3; // ADC Linearity Trim 3 Register + Uint32 ADCINLTRIM4; // ADC Linearity Trim 4 Register + Uint32 ADCINLTRIM5; // ADC Linearity Trim 5 Register + Uint32 ADCINLTRIM6; // ADC Linearity Trim 6 Register + Uint16 rsvd7[4]; // Reserved +}; + +struct ADCPPB1RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB1RESULT_REG { + Uint32 all; + struct ADCPPB1RESULT_BITS bit; +}; + +struct ADCPPB2RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB2RESULT_REG { + Uint32 all; + struct ADCPPB2RESULT_BITS bit; +}; + +struct ADCPPB3RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB3RESULT_REG { + Uint32 all; + struct ADCPPB3RESULT_BITS bit; +}; + +struct ADCPPB4RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB4RESULT_REG { + Uint32 all; + struct ADCPPB4RESULT_BITS bit; +}; + +struct ADC_RESULT_REGS { + Uint16 ADCRESULT0; // ADC Result 0 Register + Uint16 ADCRESULT1; // ADC Result 1 Register + Uint16 ADCRESULT2; // ADC Result 2 Register + Uint16 ADCRESULT3; // ADC Result 3 Register + Uint16 ADCRESULT4; // ADC Result 4 Register + Uint16 ADCRESULT5; // ADC Result 5 Register + Uint16 ADCRESULT6; // ADC Result 6 Register + Uint16 ADCRESULT7; // ADC Result 7 Register + Uint16 ADCRESULT8; // ADC Result 8 Register + Uint16 ADCRESULT9; // ADC Result 9 Register + Uint16 ADCRESULT10; // ADC Result 10 Register + Uint16 ADCRESULT11; // ADC Result 11 Register + Uint16 ADCRESULT12; // ADC Result 12 Register + Uint16 ADCRESULT13; // ADC Result 13 Register + Uint16 ADCRESULT14; // ADC Result 14 Register + Uint16 ADCRESULT15; // ADC Result 15 Register + union ADCPPB1RESULT_REG ADCPPB1RESULT; // ADC Post Processing Block 1 Result Register + union ADCPPB2RESULT_REG ADCPPB2RESULT; // ADC Post Processing Block 2 Result Register + union ADCPPB3RESULT_REG ADCPPB3RESULT; // ADC Post Processing Block 3 Result Register + union ADCPPB4RESULT_REG ADCPPB4RESULT; // ADC Post Processing Block 4 Result Register +}; + +//--------------------------------------------------------------------------- +// ADC External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ADC_RESULT_REGS AdcaResultRegs; +extern volatile struct ADC_RESULT_REGS AdcbResultRegs; +extern volatile struct ADC_RESULT_REGS AdccResultRegs; +extern volatile struct ADC_RESULT_REGS AdcdResultRegs; +extern volatile struct ADC_REGS AdcaRegs; +extern volatile struct ADC_REGS AdcbRegs; +extern volatile struct ADC_REGS AdccRegs; +extern volatile struct ADC_REGS AdcdRegs; +#endif +#ifdef CPU2 +extern volatile struct ADC_RESULT_REGS AdcaResultRegs; +extern volatile struct ADC_RESULT_REGS AdcbResultRegs; +extern volatile struct ADC_RESULT_REGS AdccResultRegs; +extern volatile struct ADC_RESULT_REGS AdcdResultRegs; +extern volatile struct ADC_REGS AdcaRegs; +extern volatile struct ADC_REGS AdcbRegs; +extern volatile struct ADC_REGS AdccRegs; +extern volatile struct ADC_REGS AdcdRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_analogsubsys.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_analogsubsys.h new file mode 100644 index 00000000000..b116e47d77f --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_analogsubsys.h @@ -0,0 +1,199 @@ +//########################################################################### +// +// FILE: F2837xD_analogsubsys.h +// +// TITLE: ANALOGSUBSYS Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_ANALOGSUBSYS_H__ +#define __F2837xD_ANALOGSUBSYS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ANALOGSUBSYS Individual Register Bit Definitions: + +struct INTOSC1TRIM_BITS { // bits description + Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:8; // 23:16 Reserved + Uint16 rsvd3:8; // 31:24 Reserved +}; + +union INTOSC1TRIM_REG { + Uint32 all; + struct INTOSC1TRIM_BITS bit; +}; + +struct INTOSC2TRIM_BITS { // bits description + Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:8; // 23:16 Reserved + Uint16 rsvd3:8; // 31:24 Reserved +}; + +union INTOSC2TRIM_REG { + Uint32 all; + struct INTOSC2TRIM_BITS bit; +}; + +struct TSNSCTL_BITS { // bits description + Uint16 ENABLE:1; // 0 Temperature Sensor Enable + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union TSNSCTL_REG { + Uint16 all; + struct TSNSCTL_BITS bit; +}; + +struct LOCK_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 TSNSCTL:1; // 3 Temperature Sensor Control Register Lock + Uint16 rsvd4:1; // 4 Reserved + Uint16 rsvd5:1; // 5 Reserved + Uint16 rsvd6:1; // 6 Reserved + Uint32 rsvd7:12; // 18:7 Reserved + Uint16 rsvd8:1; // 19 Reserved + Uint16 rsvd9:1; // 20 Reserved + Uint16 rsvd10:1; // 21 Reserved + Uint16 rsvd11:1; // 22 Reserved + Uint16 rsvd12:1; // 23 Reserved + Uint16 rsvd13:1; // 24 Reserved + Uint16 rsvd14:1; // 25 Reserved + Uint16 rsvd15:1; // 26 Reserved + Uint16 rsvd16:1; // 27 Reserved + Uint16 rsvd17:1; // 28 Reserved + Uint16 rsvd18:1; // 29 Reserved + Uint16 rsvd19:1; // 30 Reserved + Uint16 rsvd20:1; // 31 Reserved +}; + +union LOCK_REG { + Uint32 all; + struct LOCK_BITS bit; +}; + +struct ANAREFTRIMA_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMA_REG { + Uint32 all; + struct ANAREFTRIMA_BITS bit; +}; + +struct ANAREFTRIMB_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMB_REG { + Uint32 all; + struct ANAREFTRIMB_BITS bit; +}; + +struct ANAREFTRIMC_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMC_REG { + Uint32 all; + struct ANAREFTRIMC_BITS bit; +}; + +struct ANAREFTRIMD_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMD_REG { + Uint32 all; + struct ANAREFTRIMD_BITS bit; +}; + +struct ANALOG_SUBSYS_REGS { + Uint16 rsvd1[32]; // Reserved + union INTOSC1TRIM_REG INTOSC1TRIM; // Internal Oscillator 1 Trim Register + union INTOSC2TRIM_REG INTOSC2TRIM; // Internal Oscillator 2 Trim Register + Uint16 rsvd2[2]; // Reserved + union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register + Uint16 rsvd3[7]; // Reserved + union LOCK_REG LOCK; // Lock Register + Uint16 rsvd4[6]; // Reserved + union ANAREFTRIMA_REG ANAREFTRIMA; // Analog Reference Trim A Register + union ANAREFTRIMB_REG ANAREFTRIMB; // Analog Reference Trim B Register + union ANAREFTRIMC_REG ANAREFTRIMC; // Analog Reference Trim C Register + union ANAREFTRIMD_REG ANAREFTRIMD; // Analog Reference Trim D Register + Uint16 rsvd5[10]; // Reserved +}; + +//--------------------------------------------------------------------------- +// ANALOGSUBSYS External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_can.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_can.h new file mode 100644 index 00000000000..ad625e4554a --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_can.h @@ -0,0 +1,612 @@ +//########################################################################### +// +// FILE: F2837xD_can.h +// +// TITLE: CAN Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CAN_H__ +#define __F2837xD_CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CAN Individual Register Bit Definitions: + +struct CAN_CTL_BITS { // bits description + bp_16 Init:1; // 0 Initialization + bp_16 IE0:1; // 1 Interrupt line 0 Enable + bp_16 SIE:1; // 2 Status Change Interrupt Enable + bp_16 EIE:1; // 3 Error Interrupt Enable + bp_16 rsvd1:1; // 4 Reserved + bp_16 DAR:1; // 5 Disable Automatic Retransmission + bp_16 CCE:1; // 6 Configuration Change Enable + bp_16 Test:1; // 7 Test Mode Enable + bp_16 IDS:1; // 8 Interruption Debug Support Enable + bp_16 ABO:1; // 9 Auto-Bus-On Enable + bp_16 PMD:4; // 13:10 Parity on/off + bp_16 rsvd2:1; // 14 Reserved + bp_16 SWR:1; // 15 SW Reset Enable + bp_32 INITDBG:1; // 16 Debug Mode Status + bp_32 IE1:1; // 17 Interrupt line 1 Enable Disabled + bp_32 rsvd3:1; // 18 Reserved + bp_32 rsvd4:1; // 19 Reserved + bp_32 rsvd5:1; // 20 Reserved + bp_32 rsvd6:3; // 23:21 Reserved + bp_32 rsvd7:1; // 24 Reserved + bp_32 rsvd8:1; // 25 Reserved + bp_32 rsvd9:6; // 31:26 Reserved +}; + +union CAN_CTL_REG { + bp_32 all; + struct CAN_CTL_BITS bit; +}; + +struct CAN_ES_BITS { // bits description + bp_16 LEC:3; // 2:0 Last Error Code + bp_16 TxOk:1; // 3 Transmission status + bp_16 RxOk:1; // 4 Reception status + bp_16 EPass:1; // 5 Error Passive State + bp_16 EWarn:1; // 6 Warning State + bp_16 BOff:1; // 7 Bus-Off State + bp_16 PER:1; // 8 Parity Error Detected + bp_16 rsvd1:1; // 9 Reserved + bp_16 rsvd2:1; // 10 Reserved + bp_16 rsvd3:5; // 15:11 Reserved + bp_32 rsvd4:16; // 31:16 Reserved +}; + +union CAN_ES_REG { + bp_32 all; + struct CAN_ES_BITS bit; +}; + +struct CAN_ERRC_BITS { // bits description + bp_16 TEC:8; // 7:0 Transmit Error Counter + bp_16 REC:7; // 14:8 Receive Error Counter + bp_16 RP:1; // 15 Receive Error Passive + bp_32 rsvd1:16; // 31:16 Reserved +}; + +union CAN_ERRC_REG { + bp_32 all; + struct CAN_ERRC_BITS bit; +}; + +struct CAN_BTR_BITS { // bits description + bp_16 BRP:6; // 5:0 Baud Rate Prescaler + bp_16 SJW:2; // 7:6 Synchronization Jump Width + bp_16 TSEG1:4; // 11:8 Time segment + bp_16 TSEG2:3; // 14:12 Time segment + bp_16 rsvd1:1; // 15 Reserved + bp_32 BRPE:4; // 19:16 Baud Rate Prescaler Extension + bp_32 rsvd2:12; // 31:20 Reserved +}; + +union CAN_BTR_REG { + bp_32 all; + struct CAN_BTR_BITS bit; +}; + +struct CAN_INT_BITS { // bits description + bp_16 INT0ID:16; // 15:0 Interrupt Identifier + bp_32 INT1ID:8; // 23:16 Interrupt 1 Identifier + bp_32 rsvd1:8; // 31:24 Reserved +}; + +union CAN_INT_REG { + bp_32 all; + struct CAN_INT_BITS bit; +}; + +struct CAN_TEST_BITS { // bits description + bp_16 rsvd1:3; // 2:0 Reserved + bp_16 SILENT:1; // 3 Silent Mode + bp_16 LBACK:1; // 4 Loopback Mode + bp_16 TX:2; // 6:5 CANTX Pin Control + bp_16 RX:1; // 7 CANRX Pin Status + bp_16 EXL:1; // 8 External Loopback Mode + bp_16 RDA:1; // 9 RAM Direct Access Enable: + bp_16 rsvd2:6; // 15:10 Reserved + bp_32 rsvd3:16; // 31:16 Reserved +}; + +union CAN_TEST_REG { + bp_32 all; + struct CAN_TEST_BITS bit; +}; + +struct CAN_PERR_BITS { // bits description + bp_16 MSG_NUM:8; // 7:0 Message Number + bp_16 WORD_NUM:3; // 10:8 Word Number + bp_16 rsvd1:5; // 15:11 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_PERR_REG { + bp_32 all; + struct CAN_PERR_BITS bit; +}; + +struct CAN_RAM_INIT_BITS { // bits description + bp_16 KEY0:1; // 0 KEY0 + bp_16 KEY1:1; // 1 KEY1 + bp_16 KEY2:1; // 2 KEY2 + bp_16 KEY3:1; // 3 KEY3 + bp_16 CAN_RAM_INIT:1; // 4 Initialize CAN Mailbox RAM + bp_16 RAM_INIT_DONE:1; // 5 CAN RAM initialization complete + bp_16 rsvd1:10; // 15:6 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_RAM_INIT_REG { + bp_32 all; + struct CAN_RAM_INIT_BITS bit; +}; + +struct CAN_GLB_INT_EN_BITS { // bits description + bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for CAN INT0 + bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for CAN INT1 + bp_16 rsvd1:14; // 15:2 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_GLB_INT_EN_REG { + bp_32 all; + struct CAN_GLB_INT_EN_BITS bit; +}; + +struct CAN_GLB_INT_FLG_BITS { // bits description + bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for CAN INT0 + bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for CAN INT1 + bp_16 rsvd1:14; // 15:2 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_GLB_INT_FLG_REG { + bp_32 all; + struct CAN_GLB_INT_FLG_BITS bit; +}; + +struct CAN_GLB_INT_CLR_BITS { // bits description + bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for CAN INT0 + bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for CAN INT1 + bp_16 rsvd1:14; // 15:2 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_GLB_INT_CLR_REG { + bp_32 all; + struct CAN_GLB_INT_CLR_BITS bit; +}; + +struct CAN_TXRQ_X_BITS { // bits description + bp_16 TxRqstReg1:2; // 1:0 Transmit Request Register 1 + bp_16 TxRqstReg2:2; // 3:2 Transmit Request Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_TXRQ_X_REG { + bp_32 all; + struct CAN_TXRQ_X_BITS bit; +}; + +struct CAN_NDAT_X_BITS { // bits description + bp_16 NewDatReg1:2; // 1:0 New Data Register 1 + bp_16 NewDatReg2:2; // 3:2 New Data Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_NDAT_X_REG { + bp_32 all; + struct CAN_NDAT_X_BITS bit; +}; + +struct CAN_IPEN_X_BITS { // bits description + bp_16 IntPndReg1:2; // 1:0 Interrupt Pending Register 1 + bp_16 IntPndReg2:2; // 3:2 Interrupt Pending Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IPEN_X_REG { + bp_32 all; + struct CAN_IPEN_X_BITS bit; +}; + +struct CAN_MVAL_X_BITS { // bits description + bp_16 MsgValReg1:2; // 1:0 Message Valid Register 1 + bp_16 MsgValReg2:2; // 3:2 Message Valid Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_MVAL_X_REG { + bp_32 all; + struct CAN_MVAL_X_BITS bit; +}; + +struct CAN_IF1CMD_BITS { // bits description + bp_16 MSG_NUM:8; // 7:0 Message Number + bp_16 rsvd1:6; // 13:8 Reserved + bp_16 rsvd2:1; // 14 Reserved + bp_16 Busy:1; // 15 Busy Flag + bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 + bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 + bp_32 TXRQST:1; // 18 Access Transmission Request Bit + bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit + bp_32 Control:1; // 20 Access Control Bits + bp_32 Arb:1; // 21 Access Arbitration Bits + bp_32 Mask:1; // 22 Access Mask Bits + bp_32 DIR:1; // 23 Write/Read Direction + bp_32 rsvd3:8; // 31:24 Reserved +}; + +union CAN_IF1CMD_REG { + bp_32 all; + struct CAN_IF1CMD_BITS bit; +}; + +struct CAN_IF1MSK_BITS { // bits description + bp_32 Msk:29; // 28:0 Identifier Mask + bp_32 rsvd1:1; // 29 Reserved + bp_32 MDir:1; // 30 Mask Message Direction + bp_32 MXtd:1; // 31 Mask Extended Identifier +}; + +union CAN_IF1MSK_REG { + bp_32 all; + struct CAN_IF1MSK_BITS bit; +}; + +struct CAN_IF1ARB_BITS { // bits description + bp_32 ID:29; // 28:0 ` + bp_32 Dir:1; // 29 Message Direction + bp_32 Xtd:1; // 30 Extended Identifier + bp_32 MsgVal:1; // 31 Message Valid +}; + +union CAN_IF1ARB_REG { + bp_32 all; + struct CAN_IF1ARB_BITS bit; +}; + +struct CAN_IF1MCTL_BITS { // bits description + bp_16 DLC:4; // 3:0 Data length code + bp_16 rsvd1:3; // 6:4 Reserved + bp_16 EoB:1; // 7 End of Block + bp_16 TxRqst:1; // 8 Transmit Request + bp_16 RmtEn:1; // 9 Remote Enable + bp_16 RxIE:1; // 10 Receive Interrupt Enable + bp_16 TxIE:1; // 11 Transmit Interrupt Enable + bp_16 UMask:1; // 12 Use Acceptance Mask + bp_16 IntPnd:1; // 13 Interrupt Pending + bp_16 MsgLst:1; // 14 Message Lost + bp_16 NewDat:1; // 15 New Data + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IF1MCTL_REG { + bp_32 all; + struct CAN_IF1MCTL_BITS bit; +}; + +struct CAN_IF1DATA_BITS { // bits description + bp_16 Data_0:8; // 7:0 Data Byte 0 + bp_16 Data_1:8; // 15:8 Data Byte 1 + bp_32 Data_2:8; // 23:16 Data Byte 2 + bp_32 Data_3:8; // 31:24 Data Byte 3 +}; + +union CAN_IF1DATA_REG { + bp_32 all; + struct CAN_IF1DATA_BITS bit; +}; + +struct CAN_IF1DATB_BITS { // bits description + bp_16 Data_4:8; // 7:0 Data Byte 4 + bp_16 Data_5:8; // 15:8 Data Byte 5 + bp_32 Data_6:8; // 23:16 Data Byte 6 + bp_32 Data_7:8; // 31:24 Data Byte 7 +}; + +union CAN_IF1DATB_REG { + bp_32 all; + struct CAN_IF1DATB_BITS bit; +}; + +struct CAN_IF2CMD_BITS { // bits description + bp_16 MSG_NUM:8; // 7:0 Message Number + bp_16 rsvd1:6; // 13:8 Reserved + bp_16 rsvd2:1; // 14 Reserved + bp_16 Busy:1; // 15 Busy Flag + bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 + bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 + bp_32 TxRqst:1; // 18 Access Transmission Request Bit + bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit + bp_32 Control:1; // 20 Access Control Bits + bp_32 Arb:1; // 21 Access Arbitration Bits + bp_32 Mask:1; // 22 Access Mask Bits + bp_32 DIR:1; // 23 Write/Read Direction + bp_32 rsvd3:8; // 31:24 Reserved +}; + +union CAN_IF2CMD_REG { + bp_32 all; + struct CAN_IF2CMD_BITS bit; +}; + +struct CAN_IF2MSK_BITS { // bits description + bp_32 Msk:29; // 28:0 Identifier Mask + bp_32 rsvd1:1; // 29 Reserved + bp_32 MDir:1; // 30 Mask Message Direction + bp_32 MXtd:1; // 31 Mask Extended Identifier +}; + +union CAN_IF2MSK_REG { + bp_32 all; + struct CAN_IF2MSK_BITS bit; +}; + +struct CAN_IF2ARB_BITS { // bits description + bp_32 ID:29; // 28:0 Message Identifier + bp_32 Dir:1; // 29 Message Direction + bp_32 Xtd:1; // 30 Extended Identifier + bp_32 MsgVal:1; // 31 Message Valid +}; + +union CAN_IF2ARB_REG { + bp_32 all; + struct CAN_IF2ARB_BITS bit; +}; + +struct CAN_IF2MCTL_BITS { // bits description + bp_16 DLC:4; // 3:0 Data length code + bp_16 rsvd1:3; // 6:4 Reserved + bp_16 EoB:1; // 7 End of Block + bp_16 TxRqst:1; // 8 Transmit Request + bp_16 RmtEn:1; // 9 Remote Enable + bp_16 RxIE:1; // 10 Receive Interrupt Enable + bp_16 TxIE:1; // 11 Transmit Interrupt Enable + bp_16 UMask:1; // 12 Use Acceptance Mask + bp_16 IntPnd:1; // 13 Interrupt Pending + bp_16 MsgLst:1; // 14 Message Lost + bp_16 NewDat:1; // 15 New Data + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IF2MCTL_REG { + bp_32 all; + struct CAN_IF2MCTL_BITS bit; +}; + +struct CAN_IF2DATA_BITS { // bits description + bp_16 Data_0:8; // 7:0 Data Byte 0 + bp_16 Data_1:8; // 15:8 Data Byte 1 + bp_32 Data_2:8; // 23:16 Data Byte 2 + bp_32 Data_3:8; // 31:24 Data Byte 3 +}; + +union CAN_IF2DATA_REG { + bp_32 all; + struct CAN_IF2DATA_BITS bit; +}; + +struct CAN_IF2DATB_BITS { // bits description + bp_16 Data_4:8; // 7:0 Data Byte 4 + bp_16 Data_5:8; // 15:8 Data Byte 5 + bp_32 Data_6:8; // 23:16 Data Byte 6 + bp_32 Data_7:8; // 31:24 Data Byte 7 +}; + +union CAN_IF2DATB_REG { + bp_32 all; + struct CAN_IF2DATB_BITS bit; +}; + +struct CAN_IF3OBS_BITS { // bits description + bp_16 Mask:1; // 0 Mask data read observation + bp_16 Arb:1; // 1 Arbitration data read observation + bp_16 Ctrl:1; // 2 Ctrl read observation + bp_16 Data_A:1; // 3 Data A read observation + bp_16 Data_B:1; // 4 Data B read observation + bp_16 rsvd1:3; // 7:5 Reserved + bp_16 IF3SM:1; // 8 IF3 Status of Mask data read access + bp_16 IF3SA:1; // 9 IF3 Status of Arbitration data read access + bp_16 IF3SC:1; // 10 IF3 Status of Control bits read access + bp_16 IF3SDA:1; // 11 IF3 Status of Data A read access + bp_16 IF3SDB:1; // 12 IF3 Status of Data B read access + bp_16 rsvd2:2; // 14:13 Reserved + bp_16 IF3Upd:1; // 15 IF3 Update Data + bp_32 rsvd3:16; // 31:16 Reserved +}; + +union CAN_IF3OBS_REG { + bp_32 all; + struct CAN_IF3OBS_BITS bit; +}; + +struct CAN_IF3MSK_BITS { // bits description + bp_32 Msk:29; // 28:0 Mask + bp_32 rsvd1:1; // 29 Reserved + bp_32 MDir:1; // 30 Mask Message Direction + bp_32 MXtd:1; // 31 Mask Extended Identifier +}; + +union CAN_IF3MSK_REG { + bp_32 all; + struct CAN_IF3MSK_BITS bit; +}; + +struct CAN_IF3ARB_BITS { // bits description + bp_32 ID:29; // 28:0 Message Identifier + bp_32 Dir:1; // 29 Message Direction + bp_32 Xtd:1; // 30 Extended Identifier + bp_32 MsgVal:1; // 31 Message Valid +}; + +union CAN_IF3ARB_REG { + bp_32 all; + struct CAN_IF3ARB_BITS bit; +}; + +struct CAN_IF3MCTL_BITS { // bits description + bp_16 DLC:4; // 3:0 Data length code + bp_16 rsvd1:3; // 6:4 Reserved + bp_16 EoB:1; // 7 End of Block + bp_16 TxRqst:1; // 8 Transmit Request + bp_16 RmtEn:1; // 9 Remote Enable + bp_16 RxIE:1; // 10 Receive Interrupt Enable + bp_16 TxIE:1; // 11 Transmit Interrupt Enable + bp_16 UMask:1; // 12 Use Acceptance Mask + bp_16 IntPnd:1; // 13 Interrupt Pending + bp_16 MsgLst:1; // 14 Message Lost + bp_16 NewDat:1; // 15 New Data + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IF3MCTL_REG { + bp_32 all; + struct CAN_IF3MCTL_BITS bit; +}; + +struct CAN_IF3DATA_BITS { // bits description + bp_16 Data_0:8; // 7:0 Data Byte 0 + bp_16 Data_1:8; // 15:8 Data Byte 1 + bp_32 Data_2:8; // 23:16 Data Byte 2 + bp_32 Data_3:8; // 31:24 Data Byte 3 +}; + +union CAN_IF3DATA_REG { + bp_32 all; + struct CAN_IF3DATA_BITS bit; +}; + +struct CAN_IF3DATB_BITS { // bits description + bp_16 Data_4:8; // 7:0 Data Byte 4 + bp_16 Data_5:8; // 15:8 Data Byte 5 + bp_32 Data_6:8; // 23:16 Data Byte 6 + bp_32 Data_7:8; // 31:24 Data Byte 7 +}; + +union CAN_IF3DATB_REG { + bp_32 all; + struct CAN_IF3DATB_BITS bit; +}; + +struct CAN_REGS { + union CAN_CTL_REG CAN_CTL; // CAN Control Register + union CAN_ES_REG CAN_ES; // Error and Status Register + union CAN_ERRC_REG CAN_ERRC; // Error Counter Register + union CAN_BTR_REG CAN_BTR; // Bit Timing Register + union CAN_INT_REG CAN_INT; // Interrupt Register + union CAN_TEST_REG CAN_TEST; // Test Register + uint32_t rsvd1[2]; // Reserved + union CAN_PERR_REG CAN_PERR; // CAN Parity Error Code Register + uint32_t rsvd2[16]; // Reserved + union CAN_RAM_INIT_REG CAN_RAM_INIT; // CAN RAM Initialization Register + uint32_t rsvd3[6]; // Reserved + union CAN_GLB_INT_EN_REG CAN_GLB_INT_EN; // CAN Global Interrupt Enable Register + union CAN_GLB_INT_FLG_REG CAN_GLB_INT_FLG; // CAN Global Interrupt Flag Register + union CAN_GLB_INT_CLR_REG CAN_GLB_INT_CLR; // CAN Global Interrupt Clear Register + uint32_t rsvd4[18]; // Reserved + bp_32 CAN_ABOTR; // Auto-Bus-On Time Register + union CAN_TXRQ_X_REG CAN_TXRQ_X; // CAN Transmission Request Register + bp_32 CAN_TXRQ_21; // CAN Transmission Request 2_1 Register + uint32_t rsvd5[6]; // Reserved + union CAN_NDAT_X_REG CAN_NDAT_X; // CAN New Data Register + bp_32 CAN_NDAT_21; // CAN New Data 2_1 Register + uint32_t rsvd6[6]; // Reserved + union CAN_IPEN_X_REG CAN_IPEN_X; // CAN Interrupt Pending Register + bp_32 CAN_IPEN_21; // CAN Interrupt Pending 2_1 Register + uint32_t rsvd7[6]; // Reserved + union CAN_MVAL_X_REG CAN_MVAL_X; // CAN Message Valid Register + bp_32 CAN_MVAL_21; // CAN Message Valid 2_1 Register + uint32_t rsvd8[8]; // Reserved + bp_32 CAN_IP_MUX21; // CAN Interrupt Multiplexer 2_1 Register + uint32_t rsvd9[18]; // Reserved + union CAN_IF1CMD_REG CAN_IF1CMD; // IF1 Command Register + union CAN_IF1MSK_REG CAN_IF1MSK; // IF1 Mask Register + union CAN_IF1ARB_REG CAN_IF1ARB; // IF1 Arbitration Register + union CAN_IF1MCTL_REG CAN_IF1MCTL; // IF1 Message Control Register + union CAN_IF1DATA_REG CAN_IF1DATA; // IF1 Data A Register + union CAN_IF1DATB_REG CAN_IF1DATB; // IF1 Data B Register + uint32_t rsvd10[4]; // Reserved + union CAN_IF2CMD_REG CAN_IF2CMD; // IF2 Command Register + union CAN_IF2MSK_REG CAN_IF2MSK; // IF2 Mask Register + union CAN_IF2ARB_REG CAN_IF2ARB; // IF2 Arbitration Register + union CAN_IF2MCTL_REG CAN_IF2MCTL; // IF2 Message Control Register + union CAN_IF2DATA_REG CAN_IF2DATA; // IF2 Data A Register + union CAN_IF2DATB_REG CAN_IF2DATB; // IF2 Data B Register + uint32_t rsvd11[4]; // Reserved + union CAN_IF3OBS_REG CAN_IF3OBS; // IF3 Observation Register + union CAN_IF3MSK_REG CAN_IF3MSK; // IF3 Mask Register + union CAN_IF3ARB_REG CAN_IF3ARB; // IF3 Arbitration Register + union CAN_IF3MCTL_REG CAN_IF3MCTL; // IF3 Message Control Register + union CAN_IF3DATA_REG CAN_IF3DATA; // IF3 Data A Register + union CAN_IF3DATB_REG CAN_IF3DATB; // IF3 Data B Register + uint32_t rsvd12[4]; // Reserved + bp_32 CAN_IF3UPD; // IF3 Update Enable Register +}; + +//--------------------------------------------------------------------------- +// CAN External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CAN_REGS CanaRegs; +extern volatile struct CAN_REGS CanbRegs; +#endif +#ifdef CPU2 +extern volatile struct CAN_REGS CanaRegs; +extern volatile struct CAN_REGS CanbRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_cla.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cla.h new file mode 100644 index 00000000000..683333074c0 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cla.h @@ -0,0 +1,305 @@ +//########################################################################### +// +// FILE: F2837xD_cla.h +// +// TITLE: CLA Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CLA_H__ +#define __F2837xD_CLA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CLA Individual Register Bit Definitions: + +struct MCTL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset + Uint16 SOFTRESET:1; // 1 Soft Reset + Uint16 IACKE:1; // 2 IACK enable + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union MCTL_REG { + Uint16 all; + struct MCTL_BITS bit; +}; + +struct MIFR_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Flag + Uint16 INT2:1; // 1 Task 2 Interrupt Flag + Uint16 INT3:1; // 2 Task 3 Interrupt Flag + Uint16 INT4:1; // 3 Task 4 Interrupt Flag + Uint16 INT5:1; // 4 Task 5 Interrupt Flag + Uint16 INT6:1; // 5 Task 6 Interrupt Flag + Uint16 INT7:1; // 6 Task 7 Interrupt Flag + Uint16 INT8:1; // 7 Task 8 Interrupt Flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIFR_REG { + Uint16 all; + struct MIFR_BITS bit; +}; + +struct MIOVF_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag + Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag + Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag + Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag + Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag + Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag + Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag + Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIOVF_REG { + Uint16 all; + struct MIOVF_BITS bit; +}; + +struct MIFRC_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Force + Uint16 INT2:1; // 1 Task 2 Interrupt Force + Uint16 INT3:1; // 2 Task 3 Interrupt Force + Uint16 INT4:1; // 3 Task 4 Interrupt Force + Uint16 INT5:1; // 4 Task 5 Interrupt Force + Uint16 INT6:1; // 5 Task 6 Interrupt Force + Uint16 INT7:1; // 6 Task 7 Interrupt Force + Uint16 INT8:1; // 7 Task 8 Interrupt Force + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIFRC_REG { + Uint16 all; + struct MIFRC_BITS bit; +}; + +struct MICLR_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear + Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear + Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear + Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear + Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear + Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear + Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear + Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MICLR_REG { + Uint16 all; + struct MICLR_BITS bit; +}; + +struct MICLROVF_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear + Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear + Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear + Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear + Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear + Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear + Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear + Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MICLROVF_REG { + Uint16 all; + struct MICLROVF_BITS bit; +}; + +struct MIER_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Enable + Uint16 INT2:1; // 1 Task 2 Interrupt Enable + Uint16 INT3:1; // 2 Task 3 Interrupt Enable + Uint16 INT4:1; // 3 Task 4 Interrupt Enable + Uint16 INT5:1; // 4 Task 5 Interrupt Enable + Uint16 INT6:1; // 5 Task 6 Interrupt Enable + Uint16 INT7:1; // 6 Task 7 Interrupt Enable + Uint16 INT8:1; // 7 Task 8 Interrupt Enable + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIER_REG { + Uint16 all; + struct MIER_BITS bit; +}; + +struct MIRUN_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Run Status + Uint16 INT2:1; // 1 Task 2 Run Status + Uint16 INT3:1; // 2 Task 3 Run Status + Uint16 INT4:1; // 3 Task 4 Run Status + Uint16 INT5:1; // 4 Task 5 Run Status + Uint16 INT6:1; // 5 Task 6 Run Status + Uint16 INT7:1; // 6 Task 7 Run Status + Uint16 INT8:1; // 7 Task 8 Run Status + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIRUN_REG { + Uint16 all; + struct MIRUN_BITS bit; +}; + +struct _MSTF_BITS { // bits description + Uint16 LVF:1; // 0 Latched Overflow Flag + Uint16 LUF:1; // 1 Latched Underflow Flag + Uint16 NF:1; // 2 Negative Float Flag + Uint16 ZF:1; // 3 Zero Float Flag + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 TF:1; // 6 Test Flag + Uint16 rsvd2:2; // 8:7 Reserved + Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode + Uint16 rsvd3:1; // 10 Reserved + Uint16 MEALLOW:1; // 11 MEALLOW Status + Uint32 _RPC:16; // 27:12 Return PC + Uint16 rsvd4:4; // 31:28 Reserved +}; + +union _MSTF_REG { + Uint32 all; + struct _MSTF_BITS bit; +}; + +union MR_REG { + Uint32 i32; + float f32; +}; + +struct CLA_REGS { + Uint16 MVECT1; // Task Interrupt Vector + Uint16 MVECT2; // Task Interrupt Vector + Uint16 MVECT3; // Task Interrupt Vector + Uint16 MVECT4; // Task Interrupt Vector + Uint16 MVECT5; // Task Interrupt Vector + Uint16 MVECT6; // Task Interrupt Vector + Uint16 MVECT7; // Task Interrupt Vector + Uint16 MVECT8; // Task Interrupt Vector + Uint16 rsvd1[8]; // Reserved + union MCTL_REG MCTL; // Control Register + Uint16 rsvd2[15]; // Reserved + union MIFR_REG MIFR; // Interrupt Flag Register + union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register + union MIFRC_REG MIFRC; // Interrupt Force Register + union MICLR_REG MICLR; // Interrupt Flag Clear Register + union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register + union MIER_REG MIER; // Interrupt Enable Register + union MIRUN_REG MIRUN; // Interrupt Run Status Register + Uint16 rsvd3; // Reserved + Uint16 _MPC; // CLA Program Counter + Uint16 rsvd4; // Reserved + Uint16 _MAR0; // CLA Auxiliary Register 0 + Uint16 _MAR1; // CLA Auxiliary Register 1 + Uint16 rsvd5[2]; // Reserved + union _MSTF_REG _MSTF; // CLA Floating-Point Status Register + union MR_REG _MR0; // CLA Floating-Point Result Register 0 + Uint16 rsvd6[2]; // Reserved + union MR_REG _MR1; // CLA Floating-Point Result Register 1 + Uint16 rsvd7[2]; // Reserved + union MR_REG _MR2; // CLA Floating-Point Result Register 2 + Uint16 rsvd8[2]; // Reserved + union MR_REG _MR3; // CLA Floating-Point Result Register 3 +}; + +struct SOFTINTEN_BITS { // bits description + Uint16 TASK1:1; // 0 Task 1 Software Interrupt Enable + Uint16 TASK2:1; // 1 Task 2 Software Interrupt Enable + Uint16 TASK3:1; // 2 Task 3 Software Interrupt Enable + Uint16 TASK4:1; // 3 Task 4 Software Interrupt Enable + Uint16 TASK5:1; // 4 Task 5 Software Interrupt Enable + Uint16 TASK6:1; // 5 Task 6 Software Interrupt Enable + Uint16 TASK7:1; // 6 Task 7 Software Interrupt Enable + Uint16 TASK8:1; // 7 Task 8 Software Interrupt Enable + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTINTEN_REG { + Uint32 all; + struct SOFTINTEN_BITS bit; +}; + +struct SOFTINTFRC_BITS { // bits description + Uint16 TASK1:1; // 0 Task 1 Software Interrupt Force + Uint16 TASK2:1; // 1 Task 2 Software Interrupt Force + Uint16 TASK3:1; // 2 Task 3 Software Interrupt Force + Uint16 TASK4:1; // 3 Task 4 Software Interrupt Force + Uint16 TASK5:1; // 4 Task 5 Software Interrupt Force + Uint16 TASK6:1; // 5 Task 6 Software Interrupt Force + Uint16 TASK7:1; // 6 Task 7 Software Interrupt Force + Uint16 TASK8:1; // 7 Task 8 Software Interrupt Force + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTINTFRC_REG { + Uint32 all; + struct SOFTINTFRC_BITS bit; +}; + +struct CLA_SOFTINT_REGS { + union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register + union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register +}; + +//--------------------------------------------------------------------------- +// CLA External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; +extern volatile struct CLA_REGS Cla1Regs; +#endif +#ifdef CPU2 +extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; +extern volatile struct CLA_REGS Cla1Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_cmpss.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cmpss.h new file mode 100644 index 00000000000..51b595b01c1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cmpss.h @@ -0,0 +1,310 @@ +//########################################################################### +// +// FILE: F2837xD_cmpss.h +// +// TITLE: CMPSS Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CMPSS_H__ +#define __F2837xD_CMPSS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CMPSS Individual Register Bit Definitions: + +struct COMPCTL_BITS { // bits description + Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select + Uint16 COMPHINV:1; // 1 High Comparator Invert Select + Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select + Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select + Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable + Uint16 rsvd1:1; // 7 Reserved + Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select + Uint16 COMPLINV:1; // 9 Low Comparator Invert Select + Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select + Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select + Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable + Uint16 COMPDACE:1; // 15 Comparator/DAC Enable +}; + +union COMPCTL_REG { + Uint16 all; + struct COMPCTL_BITS bit; +}; + +struct COMPHYSCTL_BITS { // bits description + Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union COMPHYSCTL_REG { + Uint16 all; + struct COMPHYSCTL_BITS bit; +}; + +struct COMPSTS_BITS { // bits description + Uint16 COMPHSTS:1; // 0 High Comparator Status + Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 COMPLSTS:1; // 8 Low Comparator Status + Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status + Uint16 rsvd2:6; // 15:10 Reserved +}; + +union COMPSTS_REG { + Uint16 all; + struct COMPSTS_BITS bit; +}; + +struct COMPSTSCLR_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear + Uint16 HSYNCCLREN:1; // 2 High Comparator PWMSYNC Clear Enable + Uint16 rsvd2:6; // 8:3 Reserved + Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear + Uint16 LSYNCCLREN:1; // 10 Low Comparator PWMSYNC Clear Enable + Uint16 rsvd3:5; // 15:11 Reserved +}; + +union COMPSTSCLR_REG { + Uint16 all; + struct COMPSTSCLR_BITS bit; +}; + +struct COMPDACCTL_BITS { // bits description + Uint16 DACSOURCE:1; // 0 DAC Source Control + Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control + Uint16 SELREF:1; // 5 DAC Reference Select + Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select + Uint16 SWLOADSEL:1; // 7 Software Load Select + Uint16 rsvd1:6; // 13:8 Reserved + Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits +}; + +union COMPDACCTL_REG { + Uint16 all; + struct COMPDACCTL_BITS bit; +}; + +struct DACHVALS_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACHVALS_REG { + Uint16 all; + struct DACHVALS_BITS bit; +}; + +struct DACHVALA_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACHVALA_REG { + Uint16 all; + struct DACHVALA_BITS bit; +}; + +struct DACLVALS_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACLVALS_REG { + Uint16 all; + struct DACLVALS_BITS bit; +}; + +struct DACLVALA_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACLVALA_REG { + Uint16 all; + struct DACLVALA_BITS bit; +}; + +struct RAMPDLYA_BITS { // bits description + Uint16 DELAY:13; // 12:0 Ramp Delay Value + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union RAMPDLYA_REG { + Uint16 all; + struct RAMPDLYA_BITS bit; +}; + +struct RAMPDLYS_BITS { // bits description + Uint16 DELAY:13; // 12:0 Ramp Delay Value + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union RAMPDLYS_REG { + Uint16 all; + struct RAMPDLYS_BITS bit; +}; + +struct CTRIPLFILCTL_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 SAMPWIN:5; // 8:4 Sample Window + Uint16 THRESH:5; // 13:9 Majority Voting Threshold + Uint16 rsvd2:1; // 14 Reserved + Uint16 FILINIT:1; // 15 Filter Initialization Bit +}; + +union CTRIPLFILCTL_REG { + Uint16 all; + struct CTRIPLFILCTL_BITS bit; +}; + +struct CTRIPLFILCLKCTL_BITS { // bits description + Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union CTRIPLFILCLKCTL_REG { + Uint16 all; + struct CTRIPLFILCLKCTL_BITS bit; +}; + +struct CTRIPHFILCTL_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 SAMPWIN:5; // 8:4 Sample Window + Uint16 THRESH:5; // 13:9 Majority Voting Threshold + Uint16 rsvd2:1; // 14 Reserved + Uint16 FILINIT:1; // 15 Filter Initialization Bit +}; + +union CTRIPHFILCTL_REG { + Uint16 all; + struct CTRIPHFILCTL_BITS bit; +}; + +struct CTRIPHFILCLKCTL_BITS { // bits description + Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union CTRIPHFILCLKCTL_REG { + Uint16 all; + struct CTRIPHFILCLKCTL_BITS bit; +}; + +struct COMPLOCK_BITS { // bits description + Uint16 COMPCTL:1; // 0 COMPCTL Lock + Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock + Uint16 DACCTL:1; // 2 DACCTL Lock + Uint16 CTRIP:1; // 3 CTRIP Lock + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:11; // 15:5 Reserved +}; + +union COMPLOCK_REG { + Uint16 all; + struct COMPLOCK_BITS bit; +}; + +struct CMPSS_REGS { + union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register + union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register + union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register + union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register + union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register + Uint16 rsvd1; // Reserved + union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register + union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register + Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register + Uint16 rsvd2; // Reserved + Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register + Uint16 rsvd3; // Reserved + Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register + Uint16 rsvd4; // Reserved + Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register + Uint16 rsvd5; // Reserved + Uint16 RAMPSTS; // CMPSS Ramp Status Register + Uint16 rsvd6; // Reserved + union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register + union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register + union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register + union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register + union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register + union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register + union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register + union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register + union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register + Uint16 rsvd7[5]; // Reserved +}; + +//--------------------------------------------------------------------------- +// CMPSS External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CMPSS_REGS Cmpss1Regs; +extern volatile struct CMPSS_REGS Cmpss2Regs; +extern volatile struct CMPSS_REGS Cmpss3Regs; +extern volatile struct CMPSS_REGS Cmpss4Regs; +extern volatile struct CMPSS_REGS Cmpss5Regs; +extern volatile struct CMPSS_REGS Cmpss6Regs; +extern volatile struct CMPSS_REGS Cmpss7Regs; +extern volatile struct CMPSS_REGS Cmpss8Regs; +#endif +#ifdef CPU2 +extern volatile struct CMPSS_REGS Cmpss1Regs; +extern volatile struct CMPSS_REGS Cmpss2Regs; +extern volatile struct CMPSS_REGS Cmpss3Regs; +extern volatile struct CMPSS_REGS Cmpss4Regs; +extern volatile struct CMPSS_REGS Cmpss5Regs; +extern volatile struct CMPSS_REGS Cmpss6Regs; +extern volatile struct CMPSS_REGS Cmpss7Regs; +extern volatile struct CMPSS_REGS Cmpss8Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_cputimer.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cputimer.h new file mode 100644 index 00000000000..f822f516e5c --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_cputimer.h @@ -0,0 +1,141 @@ +//########################################################################### +// +// FILE: F2837xD_cputimer.h +// +// TITLE: CPUTIMER Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CPUTIMER_H__ +#define __F2837xD_CPUTIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CPUTIMER Individual Register Bit Definitions: + +struct TIM_BITS { // bits description + Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers + Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High +}; + +union TIM_REG { + Uint32 all; + struct TIM_BITS bit; +}; + +struct PRD_BITS { // bits description + Uint16 LSW:16; // 15:0 CPU-Timer Period Registers + Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High +}; + +union PRD_REG { + Uint32 all; + struct PRD_BITS bit; +}; + +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 TSS:1; // 4 CPU-Timer stop status bit. + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 Reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 Emulation modes + Uint16 rsvd3:2; // 13:12 Reserved + Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable. + Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag. +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down. + Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter. +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down. + Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter. +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +struct CPUTIMER_REGS { + union TIM_REG TIM; // CPU-Timer, Counter Register + union PRD_REG PRD; // CPU-Timer, Period Register + union TCR_REG TCR; // CPU-Timer, Control Register + Uint16 rsvd1; // Reserved + union TPR_REG TPR; // CPU-Timer, Prescale Register + union TPRH_REG TPRH; // CPU-Timer, Prescale Register High +}; + +//--------------------------------------------------------------------------- +// CPUTIMER External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; +#endif +#ifdef CPU2 +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_dac.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dac.h new file mode 100644 index 00000000000..6594bf23348 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dac.h @@ -0,0 +1,163 @@ +//########################################################################### +// +// FILE: F2837xD_dac.h +// +// TITLE: DAC Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_DAC_H__ +#define __F2837xD_DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// DAC Individual Register Bit Definitions: + +struct DACREV_BITS { // bits description + Uint16 REV:8; // 7:0 DAC Revision Register + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union DACREV_REG { + Uint16 all; + struct DACREV_BITS bit; +}; + +struct DACCTL_BITS { // bits description + Uint16 DACREFSEL:1; // 0 DAC Reference Select + Uint16 rsvd1:1; // 1 Reserved + Uint16 LOADMODE:1; // 2 DACVALA Load Mode + Uint16 rsvd2:1; // 3 Reserved + Uint16 SYNCSEL:4; // 7:4 DAC PWMSYNC Select + Uint16 rsvd3:8; // 15:8 Reserved +}; + +union DACCTL_REG { + Uint16 all; + struct DACCTL_BITS bit; +}; + +struct DACVALA_BITS { // bits description + Uint16 DACVALA:12; // 11:0 DAC Active Output Code + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACVALA_REG { + Uint16 all; + struct DACVALA_BITS bit; +}; + +struct DACVALS_BITS { // bits description + Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACVALS_REG { + Uint16 all; + struct DACVALS_BITS bit; +}; + +struct DACOUTEN_BITS { // bits description + Uint16 DACOUTEN:1; // 0 DAC Output Code + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union DACOUTEN_REG { + Uint16 all; + struct DACOUTEN_BITS bit; +}; + +struct DACLOCK_BITS { // bits description + Uint16 DACCTL:1; // 0 DAC Control Register Lock + Uint16 DACVAL:1; // 1 DAC Value Register Lock + Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union DACLOCK_REG { + Uint16 all; + struct DACLOCK_BITS bit; +}; + +struct DACTRIM_BITS { // bits description + Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim + Uint16 rsvd1:4; // 11:8 Reserved + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union DACTRIM_REG { + Uint16 all; + struct DACTRIM_BITS bit; +}; + +struct DAC_REGS { + union DACREV_REG DACREV; // DAC Revision Register + union DACCTL_REG DACCTL; // DAC Control Register + union DACVALA_REG DACVALA; // DAC Value Register - Active + union DACVALS_REG DACVALS; // DAC Value Register - Shadow + union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register + union DACLOCK_REG DACLOCK; // DAC Lock Register + union DACTRIM_REG DACTRIM; // DAC Trim Register + Uint16 rsvd1; // Reserved +}; + +//--------------------------------------------------------------------------- +// DAC External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct DAC_REGS DacaRegs; +extern volatile struct DAC_REGS DacbRegs; +extern volatile struct DAC_REGS DaccRegs; +#endif +#ifdef CPU2 +extern volatile struct DAC_REGS DacaRegs; +extern volatile struct DAC_REGS DacbRegs; +extern volatile struct DAC_REGS DaccRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_dcsm.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dcsm.h new file mode 100644 index 00000000000..4ea33d6843e --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dcsm.h @@ -0,0 +1,449 @@ +//########################################################################### +// +// FILE: F2837xD_dcsm.h +// +// TITLE: DCSM Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_DCSM_H__ +#define __F2837xD_DCSM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// DCSM Individual Register Bit Definitions: + +struct Z1_LINKPOINTER_BITS { // bits description + Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer. + Uint16 rsvd1:3; // 31:29 Reserved +}; + +union Z1_LINKPOINTER_REG { + Uint32 all; + struct Z1_LINKPOINTER_BITS bit; +}; + +struct Z1_OTPSECLOCK_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock. + Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock. + Uint16 rsvd2:4; // 15:12 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z1_OTPSECLOCK_REG { + Uint32 all; + struct Z1_OTPSECLOCK_BITS bit; +}; + +struct Z1_BOOTCTRL_BITS { // bits description + Uint16 KEY:8; // 7:0 OTP Boot Key + Uint16 BMODE:8; // 15:8 OTP Boot Mode + Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping + Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping +}; + +union Z1_BOOTCTRL_REG { + Uint32 all; + struct Z1_BOOTCTRL_BITS bit; +}; + +struct Z1_CR_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros + Uint16 ALLONE:1; // 4 CSMPSWD All Ones + Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY + Uint16 ARMED:1; // 6 CSM Armed + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:7; // 14:8 Reserved + Uint16 FORCESEC:1; // 15 Force Secure +}; + +union Z1_CR_REG { + Uint16 all; + struct Z1_CR_BITS bit; +}; + +struct Z1_GRABSECTR_BITS { // bits description + Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A + Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B + Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C + Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D + Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E + Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F + Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G + Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H + Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I + Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J + Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K + Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L + Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M + Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N + Uint16 rsvd1:2; // 29:28 Reserved + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z1_GRABSECTR_REG { + Uint32 all; + struct Z1_GRABSECTR_BITS bit; +}; + +struct Z1_GRABRAMR_BITS { // bits description + Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 + Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 + Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 + Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 + Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 + Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 + Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0 + Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1 + Uint16 rsvd1:12; // 27:16 Reserved + Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1 + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z1_GRABRAMR_REG { + Uint32 all; + struct Z1_GRABRAMR_BITS bit; +}; + +struct Z1_EXEONLYSECTR_BITS { // bits description + Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A + Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B + Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C + Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D + Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E + Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F + Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G + Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H + Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I + Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J + Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K + Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L + Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M + Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N + Uint16 rsvd1:1; // 14 Reserved + Uint16 rsvd2:1; // 15 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z1_EXEONLYSECTR_REG { + Uint32 all; + struct Z1_EXEONLYSECTR_BITS bit; +}; + +struct Z1_EXEONLYRAMR_BITS { // bits description + Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 + Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 + Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 + Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 + Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 + Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 + Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0 + Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1 + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union Z1_EXEONLYRAMR_REG { + Uint32 all; + struct Z1_EXEONLYRAMR_BITS bit; +}; + +struct DCSM_Z1_REGS { + union Z1_LINKPOINTER_REG Z1_LINKPOINTER; // Zone 1 Link Pointer + union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure JTAG lock + union Z1_BOOTCTRL_REG Z1_BOOTCTRL; // Boot Mode + Uint32 Z1_LINKPOINTERERR; // Link Pointer Error + Uint16 rsvd1[8]; // Reserved + Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0 + Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1 + Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2 + Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3 + Uint16 rsvd2; // Reserved + union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register + union Z1_GRABSECTR_REG Z1_GRABSECTR; // Zone 1 Grab Flash Sectors Register + union Z1_GRABRAMR_REG Z1_GRABRAMR; // Zone 1 Grab RAM Blocks Register + union Z1_EXEONLYSECTR_REG Z1_EXEONLYSECTR; // Zone 1 Flash Execute_Only Sector Register + union Z1_EXEONLYRAMR_REG Z1_EXEONLYRAMR; // Zone 1 RAM Execute_Only Block Register + Uint16 rsvd3; // Reserved +}; + +struct Z2_LINKPOINTER_BITS { // bits description + Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer. + Uint16 rsvd1:3; // 31:29 Reserved +}; + +union Z2_LINKPOINTER_REG { + Uint32 all; + struct Z2_LINKPOINTER_BITS bit; +}; + +struct Z2_OTPSECLOCK_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock. + Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock. + Uint16 rsvd2:4; // 15:12 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z2_OTPSECLOCK_REG { + Uint32 all; + struct Z2_OTPSECLOCK_BITS bit; +}; + +struct Z2_BOOTCTRL_BITS { // bits description + Uint16 KEY:8; // 7:0 OTP Boot Key + Uint16 BMODE:8; // 15:8 OTP Boot Mode + Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping + Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping +}; + +union Z2_BOOTCTRL_REG { + Uint32 all; + struct Z2_BOOTCTRL_BITS bit; +}; + +struct Z2_CR_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros + Uint16 ALLONE:1; // 4 CSMPSWD All Ones + Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY + Uint16 ARMED:1; // 6 CSM Armed + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:7; // 14:8 Reserved + Uint16 FORCESEC:1; // 15 Force Secure +}; + +union Z2_CR_REG { + Uint16 all; + struct Z2_CR_BITS bit; +}; + +struct Z2_GRABSECTR_BITS { // bits description + Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A + Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B + Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C + Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D + Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E + Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F + Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G + Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H + Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I + Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J + Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K + Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L + Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M + Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N + Uint16 rsvd1:2; // 29:28 Reserved + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z2_GRABSECTR_REG { + Uint32 all; + struct Z2_GRABSECTR_BITS bit; +}; + +struct Z2_GRABRAMR_BITS { // bits description + Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 + Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 + Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 + Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 + Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 + Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 + Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0 + Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1 + Uint16 rsvd1:12; // 27:16 Reserved + Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1 + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z2_GRABRAMR_REG { + Uint32 all; + struct Z2_GRABRAMR_BITS bit; +}; + +struct Z2_EXEONLYSECTR_BITS { // bits description + Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A + Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B + Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C + Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D + Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E + Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F + Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G + Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H + Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I + Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J + Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K + Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L + Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M + Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N + Uint16 rsvd1:1; // 14 Reserved + Uint16 rsvd2:1; // 15 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z2_EXEONLYSECTR_REG { + Uint32 all; + struct Z2_EXEONLYSECTR_BITS bit; +}; + +struct Z2_EXEONLYRAMR_BITS { // bits description + Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 + Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 + Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 + Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 + Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 + Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 + Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0 + Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1 + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union Z2_EXEONLYRAMR_REG { + Uint32 all; + struct Z2_EXEONLYRAMR_BITS bit; +}; + +struct DCSM_Z2_REGS { + union Z2_LINKPOINTER_REG Z2_LINKPOINTER; // Zone 2 Link Pointer + union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure JTAG lock + union Z2_BOOTCTRL_REG Z2_BOOTCTRL; // Boot Mode + Uint32 Z2_LINKPOINTERERR; // Link Pointer Error + Uint16 rsvd1[8]; // Reserved + Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0 + Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1 + Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2 + Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3 + Uint16 rsvd2; // Reserved + union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register + union Z2_GRABSECTR_REG Z2_GRABSECTR; // Zone 2 Grab Flash Sectors Register + union Z2_GRABRAMR_REG Z2_GRABRAMR; // Zone 2 Grab RAM Blocks Register + union Z2_EXEONLYSECTR_REG Z2_EXEONLYSECTR; // Zone 2 Flash Execute_Only Sector Register + union Z2_EXEONLYRAMR_REG Z2_EXEONLYRAMR; // Zone 2 RAM Execute_Only Block Register + Uint16 rsvd3; // Reserved +}; + +struct FLSEM_BITS { // bits description + Uint16 SEM:2; // 1:0 Flash Semaphore Bit + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 KEY:8; // 15:8 Semaphore Key + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FLSEM_REG { + Uint32 all; + struct FLSEM_BITS bit; +}; + +struct SECTSTAT_BITS { // bits description + Uint16 STATUS_SECTA:2; // 1:0 Zone Status Flash Sector A + Uint16 STATUS_SECTB:2; // 3:2 Zone Status Flash Sector B + Uint16 STATUS_SECTC:2; // 5:4 Zone Status Flash Sector C + Uint16 STATUS_SECTD:2; // 7:6 Zone Status Flash Sector D + Uint16 STATUS_SECTE:2; // 9:8 Zone Status Flash Sector E + Uint16 STATUS_SECTF:2; // 11:10 Zone Status Flash Sector F + Uint16 STATUS_SECTG:2; // 13:12 Zone Status Flash Sector G + Uint16 STATUS_SECTH:2; // 15:14 Zone Status Flash Sector H + Uint16 STATUS_SECTI:2; // 17:16 Zone Status Flash Sector I + Uint16 STATUS_SECTJ:2; // 19:18 Zone Status Flash Sector J + Uint16 STATUS_SECTK:2; // 21:20 Zone Status Flash Sector K + Uint16 STATUS_SECTL:2; // 23:22 Zone Status Flash Sector L + Uint16 STATUS_SECTM:2; // 25:24 Zone Status Flash Sector M + Uint16 STATUS_SECTN:2; // 27:26 Zone Status Flash Sector N + Uint16 rsvd1:2; // 29:28 Reserved + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union SECTSTAT_REG { + Uint32 all; + struct SECTSTAT_BITS bit; +}; + +struct RAMSTAT_BITS { // bits description + Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM LS0 + Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM LS1 + Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM LS2 + Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM LS3 + Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM LS4 + Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM LS5 + Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM D0 + Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM D1 + Uint16 rsvd1:12; // 27:16 Reserved + Uint16 STATUS_CLA1:2; // 29:28 Zone Status CLA1 + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union RAMSTAT_REG { + Uint32 all; + struct RAMSTAT_BITS bit; +}; + +struct DCSM_COMMON_REGS { + union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register + union SECTSTAT_REG SECTSTAT; // Sectors Status Register + union RAMSTAT_REG RAMSTAT; // RAM Status Register + Uint16 rsvd1[2]; // Reserved +}; + +//--------------------------------------------------------------------------- +// DCSM External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct DCSM_Z1_REGS DcsmZ1Regs; +extern volatile struct DCSM_Z2_REGS DcsmZ2Regs; +extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; +#endif +#ifdef CPU2 +extern volatile struct DCSM_Z1_REGS DcsmZ1Regs; +extern volatile struct DCSM_Z2_REGS DcsmZ2Regs; +extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_device.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_device.h new file mode 100644 index 00000000000..58aee28ebbe --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_device.h @@ -0,0 +1,345 @@ +//########################################################################### +// +// FILE: F2837xD_device.h +// +// TITLE: F2837xD Device Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_DEVICE_H +#define F2837xD_DEVICE_H + +#if (!defined(CPU1) && !defined(CPU2)) +#error "You must define CPU1 or CPU2 in your project properties. Otherwise, the offsets in your header files will be inaccurate." +#endif + +#if (defined(CPU1) && defined(CPU2)) +#error "You have defined both CPU1 and CPU2 in your project properties. Only a single CPU should be defined." +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define TARGET 1 + +// +// User To Select Target Device: +// +#define F28_2837xD TARGET + +// +// Common CPU Definitions: +// +extern __cregister volatile unsigned int IFR; +extern __cregister volatile unsigned int IER; + +#define EINT __asm(" clrc INTM") +#define DINT __asm(" setc INTM") +#define ERTM __asm(" clrc DBGM") +#define DRTM __asm(" setc DBGM") +#ifndef EALLOW +#define EALLOW __asm(" EALLOW") +#endif +#ifndef EDIS +#define EDIS __asm(" EDIS") +#endif +#define ESTOP0 __asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#ifndef C28X_BIT0 +#define C28X_BIT0 0x00000001 +#endif + +#ifndef C28X_BIT1 +#define C28X_BIT1 0x00000002 +#endif + +#ifndef C28X_BIT2 +#define C28X_BIT2 0x00000004 +#endif + +#ifndef C28X_BIT3 +#define C28X_BIT3 0x00000008 +#endif + +#ifndef C28X_BIT4 +#define C28X_BIT4 0x00000010 +#endif + +#ifndef C28X_BIT5 +#define C28X_BIT5 0x00000020 +#endif + +#ifndef C28X_BIT6 +#define C28X_BIT6 0x00000040 +#endif + +#ifndef C28X_BIT7 +#define C28X_BIT7 0x00000080 +#endif + +#ifndef C28X_BIT8 +#define C28X_BIT8 0x00000100 +#endif + +#ifndef C28X_BIT9 +#define C28X_BIT9 0x00000200 +#endif + +#ifndef C28X_BIT10 +#define C28X_BIT10 0x00000400 +#endif + +#ifndef C28X_BIT11 +#define C28X_BIT11 0x00000800 +#endif + +#ifndef C28X_BIT12 +#define C28X_BIT12 0x00001000 +#endif + +#ifndef C28X_BIT13 +#define C28X_BIT13 0x00002000 +#endif + +#ifndef C28X_BIT14 +#define C28X_BIT14 0x00004000 +#endif + +#ifndef C28X_BIT15 +#define C28X_BIT15 0x00008000 +#endif + +#ifndef C28X_BIT16 +#define C28X_BIT16 0x00010000 +#endif + +#ifndef C28X_BIT17 +#define C28X_BIT17 0x00020000 +#endif + +#ifndef C28X_BIT18 +#define C28X_BIT18 0x00040000 +#endif + +#ifndef C28X_BIT19 +#define C28X_BIT19 0x00080000 +#endif + +#ifndef C28X_BIT20 +#define C28X_BIT20 0x00100000 +#endif + +#ifndef C28X_BIT21 +#define C28X_BIT21 0x00200000 +#endif + +#ifndef C28X_BIT22 +#define C28X_BIT22 0x00400000 +#endif + +#ifndef C28X_BIT23 +#define C28X_BIT23 0x00800000 +#endif + +#ifndef C28X_BIT24 +#define C28X_BIT24 0x01000000 +#endif + +#ifndef C28X_BIT25 +#define C28X_BIT25 0x02000000 +#endif + +#ifndef C28X_BIT26 +#define C28X_BIT26 0x04000000 +#endif + +#ifndef C28X_BIT27 +#define C28X_BIT27 0x08000000 +#endif + +#ifndef C28X_BIT28 +#define C28X_BIT28 0x10000000 +#endif + +#ifndef C28X_BIT29 +#define C28X_BIT29 0x20000000 +#endif + +#ifndef C28X_BIT30 +#define C28X_BIT30 0x40000000 +#endif + +#ifndef C28X_BIT31 +#define C28X_BIT31 0x80000000 +#endif + +// +// For Portability, User Is Recommended To Use the C99 Standard integer types +// +#if !defined(__TMS320C28XX_CLA__) +#include +#include +#endif //__TMS320C28XX_CLA__ +#include +#include +#include + +// +// C++ Bool Compatibility +// +#if defined(__cplusplus) +typedef bool _Bool; +#endif + +// +// C99 defines boolean type to be _Bool, but this doesn't match the format of +// the other standard integer types. bool_t has been defined to fill this gap. +// +typedef _Bool bool_t; + +// +//used for a bool function return status +// +typedef _Bool status_t; + +#ifndef SUCCESS +#define SUCCESS true +#endif + +#ifndef FAIL +#define FAIL false +#endif + +// +// The following data types are included for compatibility with legacy code, +// they are not recommended for use in new software. Please use the C99 +// types included above +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// The following data types are for use with byte addressable peripherals. +// See compiler documentation on the byte_peripheral type attribute. +// +#ifndef __TMS320C28XX_CLA__ +#if __TI_COMPILER_VERSION__ >= 16006000 +typedef unsigned int bp_16 __attribute__((byte_peripheral)); +typedef unsigned long bp_32 __attribute__((byte_peripheral)); +#endif +#endif + +// +// Include All Peripheral Header Files: +// +#include "F2837xD_adc.h" +#include "F2837xD_analogsubsys.h" +#include "F2837xD_cla.h" +#include "F2837xD_cmpss.h" +#include "F2837xD_cputimer.h" +#include "F2837xD_dac.h" +#include "F2837xD_dcsm.h" +#include "F2837xD_dma.h" +#include "F2837xD_ecap.h" +#include "F2837xD_emif.h" +#include "F2837xD_epwm.h" // Enhanced PWM +#include "F2837xD_epwm_xbar.h" +#include "F2837xD_eqep.h" +#include "F2837xD_flash.h" +#include "F2837xD_gpio.h" // General Purpose I/O Registers +#include "F2837xD_i2c.h" +#include "F2837xD_input_xbar.h" +#include "F2837xD_ipc.h" +#include "F2837xD_mcbsp.h" +#include "F2837xD_memconfig.h" +#include "F2837xD_nmiintrupt.h" // NMI Interrupt Registers +#include "F2837xD_output_xbar.h" +#include "F2837xD_piectrl.h" // PIE Control Registers +#include "F2837xD_pievect.h" +#include "F2837xD_sci.h" +#include "F2837xD_sdfm.h" +#include "F2837xD_spi.h" +#include "F2837xD_sysctrl.h" // System Control/Power Modes +#include "F2837xD_upp.h" +#include "F2837xD_xbar.h" +#include "F2837xD_xint.h" // External Interrupts + +// +// byte_peripheral attribute is only supported on the C28 +// +#ifndef __TMS320C28XX_CLA__ +#if __TI_COMPILER_VERSION__ >= 16006000 +#include "F2837xD_can.h" +#endif +#endif + +#ifdef __cplusplus +} +#endif // extern "C" + +#endif // end of F2837xD_DEVICE_H definition + +// +// End of file. +// diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_dma.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dma.h new file mode 100644 index 00000000000..3de5b3ca0fd --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_dma.h @@ -0,0 +1,214 @@ +//########################################################################### +// +// FILE: F2837xD_dma.h +// +// TITLE: DMA Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_DMA_H__ +#define __F2837xD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// DMA Individual Register Bit Definitions: + +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select + Uint16 rsvd1:2; // 6:5 Reserved + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode + Uint16 ONESHOT:1; // 10 One Shot Mode Bit + Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit + Uint16 rsvd2:2; // 13:12 Reserved + Uint16 DATASIZE:1; // 14 Data Size Mode Bit + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit + Uint16 HALT:1; // 1 Halt Bit + Uint16 SOFTRESET:1; // 2 Soft Reset Bit + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit + Uint16 rsvd2:2; // 6:5 Reserved + Uint16 ERRCLR:1; // 7 Error Clear Bit + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit + Uint16 SYNCFLG:1; // 9 Sync Flag Bit + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit + Uint16 BURSTSTS:1; // 12 Burst Status Bit + Uint16 RUNSTS:1; // 13 Run Status Bit + Uint16 OVRFLG:1; // 14 Overflow Flag Bit + Uint16 rsvd1:1; // 15 Reserved +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit + Uint16 rsvd1:14; // 15:2 Reserved +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 Reserved + Uint16 FREE:1; // 15 Debug Mode Bit +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits + Uint16 rsvd1:1; // 3 Reserved + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size + Uint16 rsvd1:11; // 15:5 Reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count + Uint16 rsvd1:11; // 15:5 Reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + int16 SRC_BURST_STEP; // Source Burst Step Register + int16 DST_BURST_STEP; // Destination Burst Step Register + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + int16 SRC_TRANSFER_STEP; // Source Transfer Step Register + int16 DST_TRANSFER_STEP; // Destination Transfer Step Register + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register + Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register + int16 DST_WRAP_STEP; // Destination Wrap Step Register + Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register + Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register + Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register + Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register + Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register + Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register + Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register + Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register +}; + +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // Reserved + Uint16 rsvd1; // Reserved + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // Reserved + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // Reserved + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +//--------------------------------------------------------------------------- +// DMA External References & Function Declarations: +// +extern volatile struct DMA_REGS DmaRegs; +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_ecap.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_ecap.h new file mode 100644 index 00000000000..1fdeb15ec32 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_ecap.h @@ -0,0 +1,203 @@ +//########################################################################### +// +// FILE: F2837xD_ecap.h +// +// TITLE: ECAP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_ECAP_H__ +#define __F2837xD_ECAP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ECAP Individual Register Bit Definitions: + +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECCLR_BITS { // bits description + Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear + Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear + Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear + Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear + Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear + Uint16 CTROVF:1; // 5 Counter Overflow Status Clear + Uint16 CTR_PRD:1; // 6 Period Equal Status Clear + Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ECCLR_REG { + Uint16 all; + struct ECCLR_BITS bit; +}; + +struct ECFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt + Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt + Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt + Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt + Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt + Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt + Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union ECFRC_REG { + Uint16 all; + struct ECFRC_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time-Stamp Counter + Uint32 CTRPHS; // Counter Phase Offset Value Register + Uint32 CAP1; // Capture 1 Register + Uint32 CAP2; // Capture 2 Register + Uint32 CAP3; // Capture 3 Register + Uint32 CAP4; // Capture 4 Register + Uint16 rsvd1[8]; // Reserved + union ECCTL1_REG ECCTL1; // Capture Control Register 1 + union ECCTL2_REG ECCTL2; // Capture Control Register 2 + union ECEINT_REG ECEINT; // Capture Interrupt Enable Register + union ECFLG_REG ECFLG; // Capture Interrupt Flag Register + union ECCLR_REG ECCLR; // Capture Interrupt Clear Register + union ECFRC_REG ECFRC; // Capture Interrupt Force Register + Uint16 rsvd2[6]; // Reserved +}; + +//--------------------------------------------------------------------------- +// ECAP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; +#endif +#ifdef CPU2 +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_emif.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_emif.h new file mode 100644 index 00000000000..c3246b567c0 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_emif.h @@ -0,0 +1,302 @@ +//########################################################################### +// +// FILE: F2837xD_emif.h +// +// TITLE: EMIF Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EMIF_H__ +#define __F2837xD_EMIF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EMIF Individual Register Bit Definitions: + +struct RCSR_BITS { // bits description + Uint16 MINOR_REVISION:8; // 7:0 Minor Revision. + Uint16 MAJOR_REVISION:8; // 15:8 Major Revision. + Uint16 MODULE_ID:14; // 29:16 EMIF module ID. + Uint16 FR:1; // 30 EMIF is running in full rate or half rate. + Uint16 BE:1; // 31 EMIF endian mode. +}; + +union RCSR_REG { + Uint32 all; + struct RCSR_BITS bit; +}; + +struct ASYNC_WCCR_BITS { // bits description + Uint16 MAX_EXT_WAIT:8; // 7:0 Maximum Extended Wait cycles. + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:2; // 17:16 Reserved + Uint16 rsvd3:2; // 19:18 Reserved + Uint16 rsvd4:2; // 21:20 Reserved + Uint16 rsvd5:2; // 23:22 Reserved + Uint16 rsvd6:4; // 27:24 Reserved + Uint16 WP0:1; // 28 Polarity for EMxWAIT. + Uint16 rsvd7:1; // 29 Reserved + Uint16 rsvd8:1; // 30 Reserved + Uint16 rsvd9:1; // 31 Reserved +}; + +union ASYNC_WCCR_REG { + Uint32 all; + struct ASYNC_WCCR_BITS bit; +}; + +struct SDRAM_CR_BITS { // bits description + Uint16 PAGESIGE:3; // 2:0 Page Size. + Uint16 rsvd1:1; // 3 Reserved + Uint16 IBANK:3; // 6:4 Internal Bank setup of SDRAM devices. + Uint16 rsvd2:1; // 7 Reserved + Uint16 BIT_11_9_LOCK:1; // 8 Bits 11 to 9 are writable only if this bit is set. + Uint16 CL:3; // 11:9 CAS Latency. + Uint16 rsvd3:1; // 12 Reserved + Uint16 rsvd4:1; // 13 Reserved + Uint16 NM:1; // 14 Narrow Mode. + Uint16 rsvd5:1; // 15 Reserved + Uint16 rsvd6:1; // 16 Reserved + Uint16 rsvd7:2; // 18:17 Reserved + Uint16 rsvd8:1; // 19 Reserved + Uint16 rsvd9:3; // 22:20 Reserved + Uint16 rsvd10:3; // 25:23 Reserved + Uint16 rsvd11:3; // 28:26 Reserved + Uint16 PDWR:1; // 29 Perform refreshes during Power Down. + Uint16 PD:1; // 30 Power Down. + Uint16 SR:1; // 31 Self Refresh. +}; + +union SDRAM_CR_REG { + Uint32 all; + struct SDRAM_CR_BITS bit; +}; + +struct SDRAM_RCR_BITS { // bits description + Uint16 REFRESH_RATE:13; // 12:0 Refresh Rate. + Uint16 rsvd1:3; // 15:13 Reserved + Uint16 rsvd2:3; // 18:16 Reserved + Uint16 rsvd3:13; // 31:19 Reserved +}; + +union SDRAM_RCR_REG { + Uint32 all; + struct SDRAM_RCR_BITS bit; +}; + +struct ASYNC_CS2_CR_BITS { // bits description + Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. + Uint16 TA:2; // 3:2 Turn Around cycles. + Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. + Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. + Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. + Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. + Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. + Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. + Uint16 EW:1; // 30 Extend Wait mode. + Uint16 SS:1; // 31 Select Strobe mode. +}; + +union ASYNC_CS2_CR_REG { + Uint32 all; + struct ASYNC_CS2_CR_BITS bit; +}; + +struct ASYNC_CS3_CR_BITS { // bits description + Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. + Uint16 TA:2; // 3:2 Turn Around cycles. + Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. + Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. + Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. + Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. + Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. + Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. + Uint16 EW:1; // 30 Extend Wait mode. + Uint16 SS:1; // 31 Select Strobe mode. +}; + +union ASYNC_CS3_CR_REG { + Uint32 all; + struct ASYNC_CS3_CR_BITS bit; +}; + +struct ASYNC_CS4_CR_BITS { // bits description + Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. + Uint16 TA:2; // 3:2 Turn Around cycles. + Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. + Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. + Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. + Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. + Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. + Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. + Uint16 EW:1; // 30 Extend Wait mode. + Uint16 SS:1; // 31 Select Strobe mode. +}; + +union ASYNC_CS4_CR_REG { + Uint32 all; + struct ASYNC_CS4_CR_BITS bit; +}; + +struct SDRAM_TR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 T_RRD:3; // 6:4 Activate to Activate timing for different bank. + Uint16 rsvd2:1; // 7 Reserved + Uint16 T_RC:4; // 11:8 Activate to Activate timing . + Uint16 T_RAS:4; // 15:12 Activate to Precharge timing. + Uint16 T_WR:3; // 18:16 Last Write to Precharge timing. + Uint16 rsvd3:1; // 19 Reserved + Uint16 T_RCD:3; // 22:20 Activate to Read/Write timing. + Uint16 rsvd4:1; // 23 Reserved + Uint16 T_RP:3; // 26:24 Precharge to Activate/Refresh timing. + Uint16 T_RFC:5; // 31:27 Refresh/Load Mode to Refresh/Activate timing +}; + +union SDRAM_TR_REG { + Uint32 all; + struct SDRAM_TR_BITS bit; +}; + +struct SDR_EXT_TMNG_BITS { // bits description + Uint16 T_XS:5; // 4:0 Self Refresh exit to new command timing. + Uint16 rsvd1:11; // 15:5 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SDR_EXT_TMNG_REG { + Uint32 all; + struct SDR_EXT_TMNG_BITS bit; +}; + +struct INT_RAW_BITS { // bits description + Uint16 AT:1; // 0 Asynchronous Timeout. + Uint16 LT:1; // 1 Line Trap. + Uint16 WR:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_RAW_REG { + Uint32 all; + struct INT_RAW_BITS bit; +}; + +struct INT_MSK_BITS { // bits description + Uint16 AT_MASKED:1; // 0 Asynchronous Timeout. + Uint16 LT_MASKED:1; // 1 Line Trap. + Uint16 WR_MASKED:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_MSK_REG { + Uint32 all; + struct INT_MSK_BITS bit; +}; + +struct INT_MSK_SET_BITS { // bits description + Uint16 AT_MASK_SET:1; // 0 Asynchronous Timeout. + Uint16 LT_MASK_SET:1; // 1 Line Trap. + Uint16 WR_MASK_SET:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_MSK_SET_REG { + Uint32 all; + struct INT_MSK_SET_BITS bit; +}; + +struct INT_MSK_CLR_BITS { // bits description + Uint16 AT_MASK_CLR:1; // 0 Asynchronous Timeout. + Uint16 LT_MASK_CLR:1; // 1 Line Trap. + Uint16 WR_MASK_CLR:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_MSK_CLR_REG { + Uint32 all; + struct INT_MSK_CLR_BITS bit; +}; + +struct EMIF_REGS { + union RCSR_REG RCSR; // Revision Code and Status Register + union ASYNC_WCCR_REG ASYNC_WCCR; // Async Wait Cycle Config Register + union SDRAM_CR_REG SDRAM_CR; // SDRAM (EMxCS0n) Config Register + union SDRAM_RCR_REG SDRAM_RCR; // SDRAM Refresh Control Register + union ASYNC_CS2_CR_REG ASYNC_CS2_CR; // Async 1 (EMxCS2n) Config Register + union ASYNC_CS3_CR_REG ASYNC_CS3_CR; // Async 2 (EMxCS3n) Config Register + union ASYNC_CS4_CR_REG ASYNC_CS4_CR; // Async 3 (EMxCS4n) Config Register + Uint16 rsvd1[2]; // Reserved + union SDRAM_TR_REG SDRAM_TR; // SDRAM Timing Register + Uint16 rsvd2[6]; // Reserved + Uint32 TOTAL_SDRAM_AR; // Total SDRAM Accesses Register + Uint32 TOTAL_SDRAM_ACTR; // Total SDRAM Activate Register + Uint16 rsvd3[2]; // Reserved + union SDR_EXT_TMNG_REG SDR_EXT_TMNG; // SDRAM SR/PD Exit Timing Register + union INT_RAW_REG INT_RAW; // Interrupt Raw Register + union INT_MSK_REG INT_MSK; // Interrupt Masked Register + union INT_MSK_SET_REG INT_MSK_SET; // Interrupt Mask Set Register + union INT_MSK_CLR_REG INT_MSK_CLR; // Interrupt Mask Clear Register + Uint16 rsvd4[72]; // Reserved +}; + +//--------------------------------------------------------------------------- +// EMIF External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EMIF_REGS Emif1Regs; +extern volatile struct EMIF_REGS Emif2Regs; +#endif +#ifdef CPU2 +extern volatile struct EMIF_REGS Emif1Regs; +extern volatile struct EMIF_REGS Emif2Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm.h new file mode 100644 index 00000000000..bd784afd49e --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm.h @@ -0,0 +1,1240 @@ +//########################################################################### +// +// FILE: F2837xD_epwm.h +// +// TITLE: EPWM Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EPWM_H__ +#define __F2837xD_EPWM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EPWM Individual Register Bit Definitions: + +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase Load Enable + Uint16 PRDLD:1; // 3 Active Period Load + Uint16 SYNCOSEL:2; // 5:4 Sync Output Select + Uint16 SWFSYNC:1; // 6 Software Force Sync Pulse + Uint16 HSPCLKDIV:3; // 9:7 High Speed TBCLK Pre-scaler + Uint16 CLKDIV:3; // 12:10 Time Base Clock Pre-scaler + Uint16 PHSDIR:1; // 13 Phase Direction Bit + Uint16 FREE_SOFT:2; // 15:14 Emulation Mode Bits +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +struct TBCTL2_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 rsvd2:1; // 5 Reserved + Uint16 OSHTSYNCMODE:1; // 6 One shot sync mode + Uint16 OSHTSYNC:1; // 7 One shot sync + Uint16 rsvd3:4; // 11:8 Reserved + Uint16 SYNCOSELX:2; // 13:12 Syncout selection + Uint16 PRDLDSYNC:2; // 15:14 PRD Shadow to Active Load on SYNC Event +}; + +union TBCTL2_REG { + Uint16 all; + struct TBCTL2_BITS bit; +}; + +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter Direction Status + Uint16 SYNCI:1; // 1 External Input Sync Status + Uint16 CTRMAX:1; // 2 Counter Max Latched Status + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 1:0 Active Compare A Load + Uint16 LOADBMODE:2; // 3:2 Active Compare B Load + Uint16 SHDWAMODE:1; // 4 Compare A Register Block Operating Mode + Uint16 rsvd1:1; // 5 Reserved + Uint16 SHDWBMODE:1; // 6 Compare B Register Block Operating Mode + Uint16 rsvd2:1; // 7 Reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow Register Full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow Register Full Status + Uint16 LOADASYNC:2; // 11:10 Active Compare A Load on SYNC + Uint16 LOADBSYNC:2; // 13:12 Active Compare B Load on SYNC + Uint16 rsvd3:2; // 15:14 Reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +struct CMPCTL2_BITS { // bits description + Uint16 LOADCMODE:2; // 1:0 Active Compare C Load + Uint16 LOADDMODE:2; // 3:2 Active Compare D load + Uint16 SHDWCMODE:1; // 4 Compare C Block Operating Mode + Uint16 rsvd1:1; // 5 Reserved + Uint16 SHDWDMODE:1; // 6 Compare D Block Operating Mode + Uint16 rsvd2:3; // 9:7 Reserved + Uint16 LOADCSYNC:2; // 11:10 Active Compare C Load on SYNC + Uint16 LOADDSYNC:2; // 13:12 Active Compare D Load on SYNC + Uint16 rsvd3:2; // 15:14 Reserved +}; + +union CMPCTL2_REG { + Uint16 all; + struct CMPCTL2_BITS bit; +}; + +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 LOADREDMODE:2; // 7:6 Active DBRED Load Mode + Uint16 LOADFEDMODE:2; // 9:8 Active DBFED Load Mode + Uint16 SHDWDBREDMODE:1; // 10 DBRED Block Operating Mode + Uint16 SHDWDBFEDMODE:1; // 11 DBFED Block Operating Mode + Uint16 OUTSWAP:2; // 13:12 Dead Band Output Swap Control + Uint16 DEDB_MODE:1; // 14 Dead Band Dual-Edge B Mode Control + Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +struct DBCTL2_BITS { // bits description + Uint16 LOADDBCTLMODE:2; // 1:0 DBCTL Load from Shadow Mode Select + Uint16 SHDWDBCTLMODE:1; // 2 DBCTL Load mode Select + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union DBCTL2_REG { + Uint16 all; + struct DBCTL2_BITS bit; +}; + +struct AQCTL_BITS { // bits description + Uint16 LDAQAMODE:2; // 1:0 Action Qualifier A Load Select + Uint16 LDAQBMODE:2; // 3:2 Action Qualifier B Load Select + Uint16 SHDWAQAMODE:1; // 4 Action Qualifer A Operating Mode + Uint16 rsvd1:1; // 5 Reserved + Uint16 SHDWAQBMODE:1; // 6 Action Qualifier B Operating Mode + Uint16 rsvd2:1; // 7 Reserved + Uint16 LDAQASYNC:2; // 9:8 AQCTLA Register Load on SYNC + Uint16 LDAQBSYNC:2; // 11:10 AQCTLB Register Load on SYNC + Uint16 rsvd3:4; // 15:12 Reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +struct AQTSRCSEL_BITS { // bits description + Uint16 T1SEL:4; // 3:0 T1 Event Source Select Bits + Uint16 T2SEL:4; // 7:4 T2 Event Source Select Bits + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQTSRCSEL_REG { + Uint16 all; + struct AQTSRCSEL_BITS bit; +}; + +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct VCAPCTL_BITS { // bits description + Uint16 VCAPE:1; // 0 Valley Capture mode + Uint16 VCAPSTART:1; // 1 Valley Capture Start + Uint16 TRIGSEL:3; // 4:2 Capture Trigger Select + Uint16 rsvd1:2; // 6:5 Reserved + Uint16 VDELAYDIV:3; // 9:7 Valley Delay Mode Divide Enable + Uint16 EDGEFILTDLYSEL:1; // 10 Valley Switching Mode Delay Select + Uint16 rsvd2:5; // 15:11 Reserved +}; + +union VCAPCTL_REG { + Uint16 all; + struct VCAPCTL_BITS bit; +}; + +struct VCNTCFG_BITS { // bits description + Uint16 STARTEDGE:4; // 3:0 Counter Start Edge Selection + Uint16 rsvd1:3; // 6:4 Reserved + Uint16 STARTEDGESTS:1; // 7 Start Edge Status Bit + Uint16 STOPEDGE:4; // 11:8 Counter Start Edge Selection + Uint16 rsvd2:3; // 14:12 Reserved + Uint16 STOPEDGESTS:1; // 15 Stop Edge Status Bit +}; + +union VCNTCFG_REG { + Uint16 all; + struct VCNTCFG_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 ePWMxA Edge Mode Select Bits + Uint16 CTLMODE:1; // 2 ePWMxA Control Mode Select Bits + Uint16 HRLOAD:2; // 4:3 ePWMxA Shadow Mode Select Bits + Uint16 SELOUTB:1; // 5 EPWMB Output Selection Bit + Uint16 AUTOCONV:1; // 6 Autoconversion Bit + Uint16 SWAPAB:1; // 7 Swap EPWMA and EPWMB Outputs Bit + Uint16 EDGMODEB:2; // 9:8 ePWMxB Edge Mode Select Bits + Uint16 CTLMODEB:1; // 10 ePWMxB Control Mode Select Bits + Uint16 HRLOADB:2; // 12:11 ePWMxB Shadow Mode Select Bits + Uint16 rsvd1:1; // 13 Reserved + Uint16 rsvd2:2; // 15:14 Reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct HRPWR_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 rsvd2:1; // 2 Reserved + Uint16 rsvd3:1; // 3 Reserved + Uint16 rsvd4:1; // 4 Reserved + Uint16 rsvd5:1; // 5 Reserved + Uint16 rsvd6:4; // 9:6 Reserved + Uint16 rsvd7:5; // 14:10 Reserved + Uint16 CALPWRON:1; // 15 Calibration Power On +}; + +union HRPWR_REG { + Uint16 all; + struct HRPWR_BITS bit; +}; + +struct HRMSTEP_BITS { // bits description + Uint16 HRMSTEP:8; // 7:0 High Resolution Micro Step Value + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union HRMSTEP_REG { + Uint16 all; + struct HRMSTEP_BITS bit; +}; + +struct HRCNFG2_BITS { // bits description + Uint16 EDGMODEDB:2; // 1:0 Dead-Band Edge-Mode Select Bits + Uint16 CTLMODEDBRED:2; // 3:2 DBRED Control Mode Select Bits + Uint16 CTLMODEDBFED:2; // 5:4 DBFED Control Mode Select Bits + Uint16 rsvd1:8; // 13:6 Reserved + Uint16 rsvd2:1; // 14 Reserved + Uint16 rsvd3:1; // 15 Reserved +}; + +union HRCNFG2_REG { + Uint16 all; + struct HRCNFG2_BITS bit; +}; + +struct HRPCTL_BITS { // bits description + Uint16 HRPE:1; // 0 High Resolution Period Enable + Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select + Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable + Uint16 rsvd1:1; // 3 Reserved + Uint16 PWMSYNCSELX:3; // 6:4 PWMSYNCX Source Select Bit: + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union HRPCTL_REG { + Uint16 all; + struct HRPCTL_BITS bit; +}; + +struct TRREM_BITS { // bits description + Uint16 TRREM:11; // 10:0 Translator Remainder Bits + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union TRREM_REG { + Uint16 all; + struct TRREM_BITS bit; +}; + +struct GLDCTL_BITS { // bits description + Uint16 GLD:1; // 0 Global Shadow to Active load event control + Uint16 GLDMODE:4; // 4:1 Shadow to Active Global Load Pulse Selection + Uint16 OSHTMODE:1; // 5 One Shot Load mode control bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 GLDPRD:3; // 9:7 Global Reload Strobe Period Select Register + Uint16 GLDCNT:3; // 12:10 Global Reload Strobe Counter Register + Uint16 rsvd2:3; // 15:13 Reserved +}; + +union GLDCTL_REG { + Uint16 all; + struct GLDCTL_BITS bit; +}; + +struct GLDCFG_BITS { // bits description + Uint16 TBPRD_TBPRDHR:1; // 0 Global load event configuration for TBPRD:TBPRDHR + Uint16 CMPA_CMPAHR:1; // 1 Global load event configuration for CMPA:CMPAHR + Uint16 CMPB_CMPBHR:1; // 2 Global load event configuration for CMPB:CMPBHR + Uint16 CMPC:1; // 3 Global load event configuration for CMPC + Uint16 CMPD:1; // 4 Global load event configuration for CMPD + Uint16 DBRED_DBREDHR:1; // 5 Global load event configuration for DBRED:DBREDHR + Uint16 DBFED_DBFEDHR:1; // 6 Global load event configuration for DBFED:DBFEDHR + Uint16 DBCTL:1; // 7 Global load event configuration for DBCTL + Uint16 AQCTLA_AQCTLA2:1; // 8 Global load event configuration for AQCTLA/A2 + Uint16 AQCTLB_AQCTLB2:1; // 9 Global load event configuration for AQCTLB/B2 + Uint16 AQCSFRC:1; // 10 Global load event configuration for AQCSFRC + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union GLDCFG_REG { + Uint16 all; + struct GLDCFG_BITS bit; +}; + +struct EPWMXLINK_BITS { // bits description + Uint16 TBPRDLINK:4; // 3:0 TBPRD:TBPRDHR Link + Uint16 CMPALINK:4; // 7:4 CMPA:CMPAHR Link + Uint16 CMPBLINK:4; // 11:8 CMPB:CMPBHR Link + Uint16 CMPCLINK:4; // 15:12 CMPC Link + Uint16 CMPDLINK:4; // 19:16 CMPD Link + Uint16 rsvd1:8; // 27:20 Reserved + Uint16 GLDCTL2LINK:4; // 31:28 GLDCTL2 Link +}; + +union EPWMXLINK_REG { + Uint32 all; + struct EPWMXLINK_BITS bit; +}; + +struct EPWMREV_BITS { // bits description + Uint16 REV:8; // 7:0 EPWM Silicon Revision bits + Uint16 TYPE:8; // 15:8 EPWM Type Bits +}; + +union EPWMREV_REG { + Uint16 all; + struct EPWMREV_BITS bit; +}; + +struct AQCTLA_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A Up + Uint16 CAD:2; // 7:6 Action Counter = Compare A Down + Uint16 CBU:2; // 9:8 Action Counter = Compare B Up + Uint16 CBD:2; // 11:10 Action Counter = Compare B Down + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union AQCTLA_REG { + Uint16 all; + struct AQCTLA_BITS bit; +}; + +struct AQCTLA2_BITS { // bits description + Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count + Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count + Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count + Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQCTLA2_REG { + Uint16 all; + struct AQCTLA2_BITS bit; +}; + +struct AQCTLB_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A Up + Uint16 CAD:2; // 7:6 Action Counter = Compare A Down + Uint16 CBU:2; // 9:8 Action Counter = Compare B Up + Uint16 CBD:2; // 11:10 Action Counter = Compare B Down + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union AQCTLB_REG { + Uint16 all; + struct AQCTLB_BITS bit; +}; + +struct AQCTLB2_BITS { // bits description + Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count + Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count + Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count + Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQCTLB2_REG { + Uint16 all; + struct AQCTLB2_BITS bit; +}; + +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A Invoked + Uint16 OTSFA:1; // 2 One-time SW Force A Output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B Invoked + Uint16 OTSFB:1; // 5 One-time SW Force A Output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow Options + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +struct DBREDHR_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:7; // 7:1 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 DBREDHR:7; // 15:9 DBREDHR High Resolution Bits +}; + +union DBREDHR_REG { + Uint16 all; + struct DBREDHR_BITS bit; +}; + +struct DBRED_BITS { // bits description + Uint16 DBRED:14; // 13:0 Rising edge delay value + Uint16 rsvd1:2; // 15:14 Reserved +}; + +union DBRED_REG { + Uint16 all; + struct DBRED_BITS bit; +}; + +struct DBFEDHR_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:7; // 7:1 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 DBFEDHR:7; // 15:9 DBFEDHR High Resolution Bits +}; + +union DBFEDHR_REG { + Uint16 all; + struct DBFEDHR_BITS bit; +}; + +struct DBFED_BITS { // bits description + Uint16 DBFED:14; // 13:0 Falling edge delay value + Uint16 rsvd1:2; // 15:14 Reserved +}; + +union DBFED_REG { + Uint16 all; + struct DBFED_BITS bit; +}; + +struct TBPHS_BITS { // bits description + Uint16 TBPHSHR:16; // 15:0 Extension Register for HRPWM Phase (8-bits) + Uint16 TBPHS:16; // 31:16 Phase Offset Register +}; + +union TBPHS_REG { + Uint32 all; + struct TBPHS_BITS bit; +}; + +struct CMPA_BITS { // bits description + Uint16 CMPAHR:16; // 15:0 Compare A HRPWM Extension Register + Uint16 CMPA:16; // 31:16 Compare A Register +}; + +union CMPA_REG { + Uint32 all; + struct CMPA_BITS bit; +}; + +struct CMPB_BITS { // bits description + Uint16 CMPBHR:16; // 15:0 Compare B High Resolution Bits + Uint16 CMPB:16; // 31:16 Compare B Register +}; + +union CMPB_REG { + Uint32 all; + struct CMPB_BITS bit; +}; + +struct GLDCTL2_BITS { // bits description + Uint16 OSHTLD:1; // 0 Enable reload event in one shot mode + Uint16 GFRCLD:1; // 1 Force reload event in one shot mode + Uint16 rsvd1:14; // 15:2 Reserved +}; + +union GLDCTL2_REG { + Uint16 all; + struct GLDCTL2_BITS bit; +}; + +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 DCAEVT2:1; // 6 DCAEVT2 CBC select + Uint16 DCBEVT2:1; // 7 DCBEVT2 CBC select + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 DCAEVT1:1; // 14 One-shot DCAEVT1 select + Uint16 DCBEVT1:1; // 15 One-shot DCBEVT1 select +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +struct TZDCSEL_BITS { // bits description + Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 + Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 + Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 + Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZDCSEL_REG { + Uint16 all; + struct TZDCSEL_BITS bit; +}; + +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 + Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 + Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 + Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +struct TZCTL2_BITS { // bits description + Uint16 TZAU:3; // 2:0 Trip Action On EPWMxA while Count direction is UP + Uint16 TZAD:3; // 5:3 Trip Action On EPWMxA while Count direction is DOWN + Uint16 TZBU:3; // 8:6 Trip Action On EPWMxB while Count direction is UP + Uint16 TZBD:3; // 11:9 Trip Action On EPWMxB while Count direction is DOWN + Uint16 rsvd1:3; // 14:12 Reserved + Uint16 ETZE:1; // 15 TZCTL2 Enable +}; + +union TZCTL2_REG { + Uint16 all; + struct TZCTL2_BITS bit; +}; + +struct TZCTLDCA_BITS { // bits description + Uint16 DCAEVT1U:3; // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP + Uint16 DCAEVT1D:3; // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN + Uint16 DCAEVT2U:3; // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP + Uint16 DCAEVT2D:3; // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZCTLDCA_REG { + Uint16 all; + struct TZCTLDCA_BITS bit; +}; + +struct TZCTLDCB_BITS { // bits description + Uint16 DCBEVT1U:3; // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP + Uint16 DCBEVT1D:3; // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN + Uint16 DCBEVT2U:3; // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP + Uint16 DCBEVT2D:3; // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZCTLDCB_REG { + Uint16 all; + struct TZCTLDCB_BITS bit; +}; + +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Int Enable + Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Int Enable + Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Int Enable + Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Int Enable + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Int Status Flag + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Flag + Uint16 OST:1; // 2 Trip Zones One Shot Flag + Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Flag + Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Flag + Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Flag + Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Flag + Uint16 rsvd1:9; // 15:7 Reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +struct TZCBCFLG_BITS { // bits description + Uint16 CBC1:1; // 0 Latched Status Flag for CBC1 Trip Latch + Uint16 CBC2:1; // 1 Latched Status Flag for CBC2 Trip Latch + Uint16 CBC3:1; // 2 Latched Status Flag for CBC3 Trip Latch + Uint16 CBC4:1; // 3 Latched Status Flag for CBC4 Trip Latch + Uint16 CBC5:1; // 4 Latched Status Flag for CBC5 Trip Latch + Uint16 CBC6:1; // 5 Latched Status Flag for CBC6 Trip Latch + Uint16 DCAEVT2:1; // 6 Latched Status Flag for Digital Compare Output A Event 2 + Uint16 DCBEVT2:1; // 7 Latched Status Flag for Digital Compare Output B Event 2 + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZCBCFLG_REG { + Uint16 all; + struct TZCBCFLG_BITS bit; +}; + +struct TZOSTFLG_BITS { // bits description + Uint16 OST1:1; // 0 Latched Status Flag for OST1 Trip Latch + Uint16 OST2:1; // 1 Latched Status Flag for OST2 Trip Latch + Uint16 OST3:1; // 2 Latched Status Flag for OST3 Trip Latch + Uint16 OST4:1; // 3 Latched Status Flag for OST4 Trip Latch + Uint16 OST5:1; // 4 Latched Status Flag for OST5 Trip Latch + Uint16 OST6:1; // 5 Latched Status Flag for OST6 Trip Latch + Uint16 DCAEVT1:1; // 6 Latched Status Flag for Digital Compare Output A Event 1 + Uint16 DCBEVT1:1; // 7 Latched Status Flag for Digital Compare Output B Event 1 + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZOSTFLG_REG { + Uint16 all; + struct TZOSTFLG_BITS bit; +}; + +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global Interrupt Clear Flag + Uint16 CBC:1; // 1 Cycle-By-Cycle Flag Clear + Uint16 OST:1; // 2 One-Shot Flag Clear + Uint16 DCAEVT1:1; // 3 DCAVET1 Flag Clear + Uint16 DCAEVT2:1; // 4 DCAEVT2 Flag Clear + Uint16 DCBEVT1:1; // 5 DCBEVT1 Flag Clear + Uint16 DCBEVT2:1; // 6 DCBEVT2 Flag Clear + Uint16 rsvd1:7; // 13:7 Reserved + Uint16 CBCPULSE:2; // 15:14 Clear Pulse for CBC Trip Latch +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +struct TZCBCCLR_BITS { // bits description + Uint16 CBC1:1; // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch + Uint16 CBC2:1; // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch + Uint16 CBC3:1; // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch + Uint16 CBC4:1; // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch + Uint16 CBC5:1; // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch + Uint16 CBC6:1; // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch + Uint16 DCAEVT2:1; // 6 Clear Flag forDCAEVT2 selected for CBC + Uint16 DCBEVT2:1; // 7 Clear Flag for DCBEVT2 selected for CBC + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZCBCCLR_REG { + Uint16 all; + struct TZCBCCLR_BITS bit; +}; + +struct TZOSTCLR_BITS { // bits description + Uint16 OST1:1; // 0 Clear Flag for Oneshot (OST1) Trip Latch + Uint16 OST2:1; // 1 Clear Flag for Oneshot (OST2) Trip Latch + Uint16 OST3:1; // 2 Clear Flag for Oneshot (OST3) Trip Latch + Uint16 OST4:1; // 3 Clear Flag for Oneshot (OST4) Trip Latch + Uint16 OST5:1; // 4 Clear Flag for Oneshot (OST5) Trip Latch + Uint16 OST6:1; // 5 Clear Flag for Oneshot (OST6) Trip Latch + Uint16 DCAEVT1:1; // 6 Clear Flag for DCAEVT1 selected for OST + Uint16 DCBEVT1:1; // 7 Clear Flag for DCBEVT1 selected for OST + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZOSTCLR_REG { + Uint16 all; + struct TZOSTCLR_BITS bit; +}; + +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CBC:1; // 1 Force Trip Zones Cycle By Cycle Event + Uint16 OST:1; // 2 Force Trip Zones One Shot Event + Uint16 DCAEVT1:1; // 3 Force Digital Compare A Event 1 + Uint16 DCAEVT2:1; // 4 Force Digital Compare A Event 2 + Uint16 DCBEVT1:1; // 5 Force Digital Compare B Event 1 + Uint16 DCBEVT2:1; // 6 Force Digital Compare B Event 2 + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 SOCASELCMP:1; // 4 EPWMxSOCA Compare Select + Uint16 SOCBSELCMP:1; // 5 EPWMxSOCB Compare Select + Uint16 INTSELCMP:1; // 6 EPWMxINT Compare Select + Uint16 rsvd1:1; // 7 Reserved + Uint16 SOCASEL:3; // 10:8 Start of Conversion A Select + Uint16 SOCAEN:1; // 11 Start of Conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of Conversion B Select + Uint16 SOCBEN:1; // 15 Start of Conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 INTPSSEL:1; // 4 EPWMxINTn Pre-Scale Selection Bits + Uint16 SOCPSSEL:1; // 5 EPWMxSOC A/B Pre-Scale Selection Bits + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 Reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 Reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 Reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +struct ETINTPS_BITS { // bits description + Uint16 INTPRD2:4; // 3:0 EPWMxINTn Period Select + Uint16 INTCNT2:4; // 7:4 EPWMxINTn Counter Register + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ETINTPS_REG { + Uint16 all; + struct ETINTPS_BITS bit; +}; + +struct ETSOCPS_BITS { // bits description + Uint16 SOCAPRD2:4; // 3:0 EPWMxSOCA Period Select + Uint16 SOCACNT2:4; // 7:4 EPWMxSOCA Counter Register + Uint16 SOCBPRD2:4; // 11:8 EPWMxSOCB Period Select + Uint16 SOCBCNT2:4; // 15:12 EPWMxSOCB Counter Register +}; + +union ETSOCPS_REG { + Uint16 all; + struct ETSOCPS_BITS bit; +}; + +struct ETCNTINITCTL_BITS { // bits description + Uint16 rsvd1:10; // 9:0 Reserved + Uint16 INTINITFRC:1; // 10 EPWMxINT Counter Initialization Force + Uint16 SOCAINITFRC:1; // 11 EPWMxSOCA Counter Initialization Force + Uint16 SOCBINITFRC:1; // 12 EPWMxSOCB Counter Initialization Force + Uint16 INTINITEN:1; // 13 EPWMxINT Counter Initialization Enable + Uint16 SOCAINITEN:1; // 14 EPWMxSOCA Counter Initialization Enable + Uint16 SOCBINITEN:1; // 15 EPWMxSOCB Counter Initialization Enable +}; + +union ETCNTINITCTL_REG { + Uint16 all; + struct ETCNTINITCTL_BITS bit; +}; + +struct ETCNTINIT_BITS { // bits description + Uint16 INTINIT:4; // 3:0 EPWMxINT Counter Initialization Bits + Uint16 SOCAINIT:4; // 7:4 EPWMxSOCA Counter Initialization Bits + Uint16 SOCBINIT:4; // 11:8 EPWMxSOCB Counter Initialization Bits + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ETCNTINIT_REG { + Uint16 all; + struct ETCNTINIT_BITS bit; +}; + +struct DCTRIPSEL_BITS { // bits description + Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High COMP Input Select + Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low COMP Input Select + Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High COMP Input Select + Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low COMP Input Select +}; + +union DCTRIPSEL_REG { + Uint16 all; + struct DCTRIPSEL_BITS bit; +}; + +struct DCACTL_BITS { // bits description + Uint16 EVT1SRCSEL:1; // 0 DCAEVT1 Source Signal + Uint16 EVT1FRCSYNCSEL:1; // 1 DCAEVT1 Force Sync Signal + Uint16 EVT1SOCE:1; // 2 DCAEVT1 SOC Enable + Uint16 EVT1SYNCE:1; // 3 DCAEVT1 SYNC Enable + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:2; // 6:5 Reserved + Uint16 rsvd3:1; // 7 Reserved + Uint16 EVT2SRCSEL:1; // 8 DCAEVT2 Source Signal + Uint16 EVT2FRCSYNCSEL:1; // 9 DCAEVT2 Force Sync Signal + Uint16 rsvd4:2; // 11:10 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:2; // 14:13 Reserved + Uint16 rsvd7:1; // 15 Reserved +}; + +union DCACTL_REG { + Uint16 all; + struct DCACTL_BITS bit; +}; + +struct DCBCTL_BITS { // bits description + Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal + Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Sync Signal + Uint16 EVT1SOCE:1; // 2 DCBEVT1 SOC Enable + Uint16 EVT1SYNCE:1; // 3 DCBEVT1 SYNC Enable + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:2; // 6:5 Reserved + Uint16 rsvd3:1; // 7 Reserved + Uint16 EVT2SRCSEL:1; // 8 DCBEVT2 Source Signal + Uint16 EVT2FRCSYNCSEL:1; // 9 DCBEVT2 Force Sync Signal + Uint16 rsvd4:2; // 11:10 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:2; // 14:13 Reserved + Uint16 rsvd7:1; // 15 Reserved +}; + +union DCBCTL_REG { + Uint16 all; + struct DCBCTL_BITS bit; +}; + +struct DCFCTL_BITS { // bits description + Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select + Uint16 BLANKE:1; // 2 Blanking Enable/Disable + Uint16 BLANKINV:1; // 3 Blanking Window Inversion + Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment + Uint16 EDGEFILTSEL:1; // 6 Edge Filter Select + Uint16 rsvd1:1; // 7 Reserved + Uint16 EDGEMODE:2; // 9:8 Edge Mode + Uint16 EDGECOUNT:3; // 12:10 Edge Count + Uint16 EDGESTATUS:3; // 15:13 Edge Status +}; + +union DCFCTL_REG { + Uint16 all; + struct DCFCTL_BITS bit; +}; + +struct DCCAPCTL_BITS { // bits description + Uint16 CAPE:1; // 0 Counter Capture Enable + Uint16 SHDWMODE:1; // 1 Counter Capture Mode + Uint16 rsvd1:11; // 12:2 Reserved + Uint16 CAPSTS:1; // 13 Latched Status Flag for Capture Event + Uint16 CAPCLR:1; // 14 DC Capture Latched Status Clear Flag + Uint16 CAPMODE:1; // 15 Counter Capture Mode +}; + +union DCCAPCTL_REG { + Uint16 all; + struct DCCAPCTL_BITS bit; +}; + +struct DCAHTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAH Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAH Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAH Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAH Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAH Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAH Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAH Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAH Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAH Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAH Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAH Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAH Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAH Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAH Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCAHTRIPSEL_REG { + Uint16 all; + struct DCAHTRIPSEL_BITS bit; +}; + +struct DCALTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAL Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAL Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAL Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAL Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAL Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAL Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAL Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAL Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAL Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAL Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAL Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAL Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAL Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAL Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCALTRIPSEL_REG { + Uint16 all; + struct DCALTRIPSEL_BITS bit; +}; + +struct DCBHTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBH Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBH Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBH Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBH Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBH Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBH Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBH Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBH Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBH Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBH Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBH Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBH Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBH Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBH Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCBHTRIPSEL_REG { + Uint16 all; + struct DCBHTRIPSEL_BITS bit; +}; + +struct DCBLTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBL Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBL Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBL Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBL Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBL Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBL Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBL Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBL Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBL Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBL Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBL Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBL Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBL Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBL Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCBLTRIPSEL_REG { + Uint16 all; + struct DCBLTRIPSEL_BITS bit; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // Time Base Control Register + union TBCTL2_REG TBCTL2; // Time Base Control Register 2 + Uint16 rsvd1[2]; // Reserved + Uint16 TBCTR; // Time Base Counter Register + union TBSTS_REG TBSTS; // Time Base Status Register + Uint16 rsvd2[2]; // Reserved + union CMPCTL_REG CMPCTL; // Counter Compare Control Register + union CMPCTL2_REG CMPCTL2; // Counter Compare Control Register 2 + Uint16 rsvd3[2]; // Reserved + union DBCTL_REG DBCTL; // Dead-Band Generator Control Register + union DBCTL2_REG DBCTL2; // Dead-Band Generator Control Register 2 + Uint16 rsvd4[2]; // Reserved + union AQCTL_REG AQCTL; // Action Qualifier Control Register + union AQTSRCSEL_REG AQTSRCSEL; // Action Qualifier Trigger Event Source Select Register + Uint16 rsvd5[2]; // Reserved + union PCCTL_REG PCCTL; // PWM Chopper Control Register + Uint16 rsvd6[3]; // Reserved + union VCAPCTL_REG VCAPCTL; // Valley Capture Control Register + union VCNTCFG_REG VCNTCFG; // Valley Counter Config Register + Uint16 rsvd7[6]; // Reserved + union HRCNFG_REG HRCNFG; // HRPWM Configuration Register + union HRPWR_REG HRPWR; // HRPWM Power Register + Uint16 rsvd8[4]; // Reserved + union HRMSTEP_REG HRMSTEP; // HRPWM MEP Step Register + union HRCNFG2_REG HRCNFG2; // HRPWM Configuration 2 Register + Uint16 rsvd9[5]; // Reserved + union HRPCTL_REG HRPCTL; // High Resolution Period Control Register + union TRREM_REG TRREM; // Translator High Resolution Remainder Register + Uint16 rsvd10[5]; // Reserved + union GLDCTL_REG GLDCTL; // Global PWM Load Control Register + union GLDCFG_REG GLDCFG; // Global PWM Load Config Register + Uint16 rsvd11[2]; // Reserved + union EPWMXLINK_REG EPWMXLINK; // EPWMx Link Register + Uint16 rsvd12[4]; // Reserved + union EPWMREV_REG EPWMREV; // EPWM Revision Register + Uint16 rsvd13; // Reserved + union AQCTLA_REG AQCTLA; // Action Qualifier Control Register For Output A + union AQCTLA2_REG AQCTLA2; // Additional Action Qualifier Control Register For Output A + union AQCTLB_REG AQCTLB; // Action Qualifier Control Register For Output B + union AQCTLB2_REG AQCTLB2; // Additional Action Qualifier Control Register For Output B + Uint16 rsvd14[3]; // Reserved + union AQSFRC_REG AQSFRC; // Action Qualifier Software Force Register + Uint16 rsvd15; // Reserved + union AQCSFRC_REG AQCSFRC; // Action Qualifier Continuous S/W Force Register + Uint16 rsvd16[6]; // Reserved + union DBREDHR_REG DBREDHR; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register + union DBRED_REG DBRED; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register + union DBFEDHR_REG DBFEDHR; // Dead-Band Generator Falling Edge Delay High Resolution Register + union DBFED_REG DBFED; // Dead-Band Generator Falling Edge Delay Count Register + Uint16 rsvd17[12]; // Reserved + union TBPHS_REG TBPHS; // Time Base Phase High + Uint16 TBPRDHR; // Time Base Period High Resolution Register + Uint16 TBPRD; // Time Base Period Register + Uint16 rsvd18[6]; // Reserved + union CMPA_REG CMPA; // Counter Compare A Register + union CMPB_REG CMPB; // Compare B Register + Uint16 rsvd19; // Reserved + Uint16 CMPC; // Counter Compare C Register + Uint16 rsvd20; // Reserved + Uint16 CMPD; // Counter Compare D Register + Uint16 rsvd21[2]; // Reserved + union GLDCTL2_REG GLDCTL2; // Global PWM Load Control Register 2 + Uint16 rsvd22[2]; // Reserved + Uint16 SWVDELVAL; // Software Valley Mode Delay Register + Uint16 rsvd23[8]; // Reserved + union TZSEL_REG TZSEL; // Trip Zone Select Register + Uint16 rsvd24; // Reserved + union TZDCSEL_REG TZDCSEL; // Trip Zone Digital Comparator Select Register + Uint16 rsvd25; // Reserved + union TZCTL_REG TZCTL; // Trip Zone Control Register + union TZCTL2_REG TZCTL2; // Additional Trip Zone Control Register + union TZCTLDCA_REG TZCTLDCA; // Trip Zone Control Register Digital Compare A + union TZCTLDCB_REG TZCTLDCB; // Trip Zone Control Register Digital Compare B + Uint16 rsvd26[5]; // Reserved + union TZEINT_REG TZEINT; // Trip Zone Enable Interrupt Register + Uint16 rsvd27[5]; // Reserved + union TZFLG_REG TZFLG; // Trip Zone Flag Register + union TZCBCFLG_REG TZCBCFLG; // Trip Zone CBC Flag Register + union TZOSTFLG_REG TZOSTFLG; // Trip Zone OST Flag Register + Uint16 rsvd28; // Reserved + union TZCLR_REG TZCLR; // Trip Zone Clear Register + union TZCBCCLR_REG TZCBCCLR; // Trip Zone CBC Clear Register + union TZOSTCLR_REG TZOSTCLR; // Trip Zone OST Clear Register + Uint16 rsvd29; // Reserved + union TZFRC_REG TZFRC; // Trip Zone Force Register + Uint16 rsvd30[8]; // Reserved + union ETSEL_REG ETSEL; // Event Trigger Selection Register + Uint16 rsvd31; // Reserved + union ETPS_REG ETPS; // Event Trigger Pre-Scale Register + Uint16 rsvd32; // Reserved + union ETFLG_REG ETFLG; // Event Trigger Flag Register + Uint16 rsvd33; // Reserved + union ETCLR_REG ETCLR; // Event Trigger Clear Register + Uint16 rsvd34; // Reserved + union ETFRC_REG ETFRC; // Event Trigger Force Register + Uint16 rsvd35; // Reserved + union ETINTPS_REG ETINTPS; // Event-Trigger Interrupt Pre-Scale Register + Uint16 rsvd36; // Reserved + union ETSOCPS_REG ETSOCPS; // Event-Trigger SOC Pre-Scale Register + Uint16 rsvd37; // Reserved + union ETCNTINITCTL_REG ETCNTINITCTL; // Event-Trigger Counter Initialization Control Register + Uint16 rsvd38; // Reserved + union ETCNTINIT_REG ETCNTINIT; // Event-Trigger Counter Initialization Register + Uint16 rsvd39[11]; // Reserved + union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select Register + Uint16 rsvd40[2]; // Reserved + union DCACTL_REG DCACTL; // Digital Compare A Control Register + union DCBCTL_REG DCBCTL; // Digital Compare B Control Register + Uint16 rsvd41[2]; // Reserved + union DCFCTL_REG DCFCTL; // Digital Compare Filter Control Register + union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control Register + Uint16 DCFOFFSET; // Digital Compare Filter Offset Register + Uint16 DCFOFFSETCNT; // Digital Compare Filter Offset Counter Register + Uint16 DCFWINDOW; // Digital Compare Filter Window Register + Uint16 DCFWINDOWCNT; // Digital Compare Filter Window Counter Register + Uint16 rsvd42[2]; // Reserved + Uint16 DCCAP; // Digital Compare Counter Capture Register + Uint16 rsvd43[2]; // Reserved + union DCAHTRIPSEL_REG DCAHTRIPSEL; // Digital Compare AH Trip Select + union DCALTRIPSEL_REG DCALTRIPSEL; // Digital Compare AL Trip Select + union DCBHTRIPSEL_REG DCBHTRIPSEL; // Digital Compare BH Trip Select + union DCBLTRIPSEL_REG DCBLTRIPSEL; // Digital Compare BL Trip Select + Uint16 rsvd44[39]; // Reserved + Uint16 HWVDELVAL; // Hardware Valley Mode Delay Register + Uint16 VCNTVAL; // Hardware Valley Counter Register + Uint16 rsvd45; // Reserved +}; + +//--------------------------------------------------------------------------- +// EPWM External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; +extern volatile struct EPWM_REGS EPwm7Regs; +extern volatile struct EPWM_REGS EPwm8Regs; +extern volatile struct EPWM_REGS EPwm9Regs; +extern volatile struct EPWM_REGS EPwm10Regs; +extern volatile struct EPWM_REGS EPwm11Regs; +extern volatile struct EPWM_REGS EPwm12Regs; +#endif +#ifdef CPU2 +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; +extern volatile struct EPWM_REGS EPwm7Regs; +extern volatile struct EPWM_REGS EPwm8Regs; +extern volatile struct EPWM_REGS EPwm9Regs; +extern volatile struct EPWM_REGS EPwm10Regs; +extern volatile struct EPWM_REGS EPwm11Regs; +extern volatile struct EPWM_REGS EPwm12Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm_xbar.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm_xbar.h new file mode 100644 index 00000000000..47f85e18fe0 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_epwm_xbar.h @@ -0,0 +1,832 @@ +//########################################################################### +// +// FILE: F2837xD_epwm_xbar.h +// +// TITLE: EPWM_XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EPWM_XBAR_H__ +#define __F2837xD_EPWM_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EPWM_XBAR Individual Register Bit Definitions: + +struct TRIP4MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR +}; + +union TRIP4MUX0TO15CFG_REG { + Uint32 all; + struct TRIP4MUX0TO15CFG_BITS bit; +}; + +struct TRIP4MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR +}; + +union TRIP4MUX16TO31CFG_REG { + Uint32 all; + struct TRIP4MUX16TO31CFG_BITS bit; +}; + +struct TRIP5MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR +}; + +union TRIP5MUX0TO15CFG_REG { + Uint32 all; + struct TRIP5MUX0TO15CFG_BITS bit; +}; + +struct TRIP5MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR +}; + +union TRIP5MUX16TO31CFG_REG { + Uint32 all; + struct TRIP5MUX16TO31CFG_BITS bit; +}; + +struct TRIP7MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR +}; + +union TRIP7MUX0TO15CFG_REG { + Uint32 all; + struct TRIP7MUX0TO15CFG_BITS bit; +}; + +struct TRIP7MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR +}; + +union TRIP7MUX16TO31CFG_REG { + Uint32 all; + struct TRIP7MUX16TO31CFG_BITS bit; +}; + +struct TRIP8MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR +}; + +union TRIP8MUX0TO15CFG_REG { + Uint32 all; + struct TRIP8MUX0TO15CFG_BITS bit; +}; + +struct TRIP8MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR +}; + +union TRIP8MUX16TO31CFG_REG { + Uint32 all; + struct TRIP8MUX16TO31CFG_BITS bit; +}; + +struct TRIP9MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR +}; + +union TRIP9MUX0TO15CFG_REG { + Uint32 all; + struct TRIP9MUX0TO15CFG_BITS bit; +}; + +struct TRIP9MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR +}; + +union TRIP9MUX16TO31CFG_REG { + Uint32 all; + struct TRIP9MUX16TO31CFG_BITS bit; +}; + +struct TRIP10MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR +}; + +union TRIP10MUX0TO15CFG_REG { + Uint32 all; + struct TRIP10MUX0TO15CFG_BITS bit; +}; + +struct TRIP10MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR +}; + +union TRIP10MUX16TO31CFG_REG { + Uint32 all; + struct TRIP10MUX16TO31CFG_BITS bit; +}; + +struct TRIP11MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR +}; + +union TRIP11MUX0TO15CFG_REG { + Uint32 all; + struct TRIP11MUX0TO15CFG_BITS bit; +}; + +struct TRIP11MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR +}; + +union TRIP11MUX16TO31CFG_REG { + Uint32 all; + struct TRIP11MUX16TO31CFG_BITS bit; +}; + +struct TRIP12MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR +}; + +union TRIP12MUX0TO15CFG_REG { + Uint32 all; + struct TRIP12MUX0TO15CFG_BITS bit; +}; + +struct TRIP12MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR +}; + +union TRIP12MUX16TO31CFG_REG { + Uint32 all; + struct TRIP12MUX16TO31CFG_BITS bit; +}; + +struct TRIP4MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR +}; + +union TRIP4MUXENABLE_REG { + Uint32 all; + struct TRIP4MUXENABLE_BITS bit; +}; + +struct TRIP5MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR +}; + +union TRIP5MUXENABLE_REG { + Uint32 all; + struct TRIP5MUXENABLE_BITS bit; +}; + +struct TRIP7MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR +}; + +union TRIP7MUXENABLE_REG { + Uint32 all; + struct TRIP7MUXENABLE_BITS bit; +}; + +struct TRIP8MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR +}; + +union TRIP8MUXENABLE_REG { + Uint32 all; + struct TRIP8MUXENABLE_BITS bit; +}; + +struct TRIP9MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR +}; + +union TRIP9MUXENABLE_REG { + Uint32 all; + struct TRIP9MUXENABLE_BITS bit; +}; + +struct TRIP10MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR +}; + +union TRIP10MUXENABLE_REG { + Uint32 all; + struct TRIP10MUXENABLE_BITS bit; +}; + +struct TRIP11MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR +}; + +union TRIP11MUXENABLE_REG { + Uint32 all; + struct TRIP11MUXENABLE_BITS bit; +}; + +struct TRIP12MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR +}; + +union TRIP12MUXENABLE_REG { + Uint32 all; + struct TRIP12MUXENABLE_BITS bit; +}; + +struct TRIPOUTINV_BITS { // bits description + Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR + Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR + Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR + Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR + Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR + Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR + Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR + Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union TRIPOUTINV_REG { + Uint32 all; + struct TRIPOUTINV_BITS bit; +}; + +struct TRIPLOCK_BITS { // bits description + Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 KEY:16; // 31:16 Write protection KEY +}; + +union TRIPLOCK_REG { + Uint32 all; + struct TRIPLOCK_BITS bit; +}; + +struct EPWM_XBAR_REGS { + union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4 + union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4 + union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5 + union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5 + union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7 + union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7 + union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8 + union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8 + union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9 + union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9 + union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10 + union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10 + union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11 + union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11 + union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12 + union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12 + union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4 + union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5 + union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7 + union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8 + union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9 + union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10 + union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11 + union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12 + Uint16 rsvd1[8]; // Reserved + union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register + Uint16 rsvd2[4]; // Reserved + union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register +}; + +//--------------------------------------------------------------------------- +// EPWM_XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_eqep.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_eqep.h new file mode 100644 index 00000000000..f37da095a97 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_eqep.h @@ -0,0 +1,267 @@ +//########################################################################### +// +// FILE: F2837xD_eqep.h +// +// TITLE: EQEP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EQEP_H__ +#define __F2837xD_EQEP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EQEP Individual Register Bit Definitions: + +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter + Uint16 XCR:1; // 11 External Clock Rate + Uint16 SPSEL:1; // 12 Sync output pin selection + Uint16 SOEN:1; // 13 Sync output-enable + Uint16 QSRC:2; // 15:14 Position-counter source selection +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature postotion counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Postion counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position event prescaler + Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler + Uint16 rsvd1:8; // 14:7 Reserved + Uint16 CEN:1; // 15 Enable eQEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare of shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error interrupt enable + Uint16 QPE:1; // 2 Quadrature phase error interrupt enable + Uint16 QDC:1; // 3 Quadrature direction change interrupt enable + Uint16 WTO:1; // 4 Watchdog time out interrupt enable + Uint16 PCU:1; // 5 Position counter underflow interrupt enable + Uint16 PCO:1; // 6 Position counter overflow interrupt enable + Uint16 PCR:1; // 7 Position-compare ready interrupt enable + Uint16 PCM:1; // 8 Position-compare match interrupt enable + Uint16 SEL:1; // 9 Strobe event latch interrupt enable + Uint16 IEL:1; // 10 Index event latch interrupt enable + Uint16 UTO:1; // 11 Unit time out interrupt enable + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt status flag + Uint16 PCE:1; // 1 Position counter error interrupt flag + Uint16 PHE:1; // 2 Quadrature phase error interrupt flag + Uint16 QDC:1; // 3 Quadrature direction change interrupt flag + Uint16 WTO:1; // 4 Watchdog timeout interrupt flag + Uint16 PCU:1; // 5 Position counter underflow interrupt flag + Uint16 PCO:1; // 6 Position counter overflow interrupt flag + Uint16 PCR:1; // 7 Position-compare ready interrupt flag + Uint16 PCM:1; // 8 eQEP compare match event interrupt flag + Uint16 SEL:1; // 9 Strobe event latch interrupt flag + Uint16 IEL:1; // 10 Index event latch interrupt flag + Uint16 UTO:1; // 11 Unit time out interrupt flag + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +struct QCLR_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt clear flag + Uint16 PCE:1; // 1 Clear position counter error interrupt flag + Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag + Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag + Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag + Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag + Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag + Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag + Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag + Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag + Uint16 IEL:1; // 10 Clear index event latch interrupt flag + Uint16 UTO:1; // 11 Clear unit time out interrupt flag + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union QCLR_REG { + Uint16 all; + struct QCLR_BITS bit; +}; + +struct QFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 PCE:1; // 1 Force position counter error interrupt + Uint16 PHE:1; // 2 Force quadrature phase error interrupt + Uint16 QDC:1; // 3 Force quadrature direction change interrupt + Uint16 WTO:1; // 4 Force watchdog time out interrupt + Uint16 PCU:1; // 5 Force position counter underflow interrupt + Uint16 PCO:1; // 6 Force position counter overflow interrupt + Uint16 PCR:1; // 7 Force position-compare ready interrupt + Uint16 PCM:1; // 8 Force position-compare match interrupt + Uint16 SEL:1; // 9 Force strobe event latch interrupt + Uint16 IEL:1; // 10 Force index event latch interrupt + Uint16 UTO:1; // 11 Force unit time out interrupt + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error flag. + Uint16 FIMF:1; // 1 First index marker flag + Uint16 CDEF:1; // 2 Capture direction error flag + Uint16 COEF:1; // 3 Capture overflow error flag + Uint16 QDLF:1; // 4 eQEP direction latch flag + Uint16 QDF:1; // 5 Quadrature direction flag + Uint16 FIDF:1; // 6 The first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position Counter + Uint32 QPOSINIT; // Position Counter Init + Uint32 QPOSMAX; // Maximum Position Count + Uint32 QPOSCMP; // Position Compare + Uint32 QPOSILAT; // Index Position Latch + Uint32 QPOSSLAT; // Strobe Position Latch + Uint32 QPOSLAT; // Position Latch + Uint32 QUTMR; // QEP Unit Timer + Uint32 QUPRD; // QEP Unit Period + Uint16 QWDTMR; // QEP Watchdog Timer + Uint16 QWDPRD; // QEP Watchdog Period + union QDECCTL_REG QDECCTL; // Quadrature Decoder Control + union QEPCTL_REG QEPCTL; // QEP Control + union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control + union QPOSCTL_REG QPOSCTL; // Position Compare Control + union QEINT_REG QEINT; // QEP Interrupt Control + union QFLG_REG QFLG; // QEP Interrupt Flag + union QCLR_REG QCLR; // QEP Interrupt Clear + union QFRC_REG QFRC; // QEP Interrupt Force + union QEPSTS_REG QEPSTS; // QEP Status + Uint16 QCTMR; // QEP Capture Timer + Uint16 QCPRD; // QEP Capture Period + Uint16 QCTMRLAT; // QEP Capture Latch + Uint16 QCPRDLAT; // QEP Capture Period Latch + Uint16 rsvd1; // Reserved +}; + +//--------------------------------------------------------------------------- +// EQEP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; +extern volatile struct EQEP_REGS EQep3Regs; +#endif +#ifdef CPU2 +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; +extern volatile struct EQEP_REGS EQep3Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_flash.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_flash.h new file mode 100644 index 00000000000..2882c6a96d3 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_flash.h @@ -0,0 +1,376 @@ +//########################################################################### +// +// FILE: F2837xD_flash.h +// +// TITLE: FLASH Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_FLASH_H__ +#define __F2837xD_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// FLASH Individual Register Bit Definitions: + +struct FRDCNTL_BITS { // bits description + Uint16 rsvd1:8; // 7:0 Reserved + Uint16 RWAIT:4; // 11:8 Random Read Waitstate + Uint16 rsvd2:4; // 15:12 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union FRDCNTL_REG { + Uint32 all; + struct FRDCNTL_BITS bit; +}; + +struct FBAC_BITS { // bits description + Uint16 VREADST:8; // 7:0 VREAD Setup Time Count + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FBAC_REG { + Uint32 all; + struct FBAC_BITS bit; +}; + +struct FBFALLBACK_BITS { // bits description + Uint16 BNKPWR0:2; // 1:0 Bank Power Mode + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FBFALLBACK_REG { + Uint32 all; + struct FBFALLBACK_BITS bit; +}; + +struct FBPRDY_BITS { // bits description + Uint16 BANKRDY:1; // 0 Flash Bank Active Power State + Uint16 rsvd1:14; // 14:1 Reserved + Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FBPRDY_REG { + Uint32 all; + struct FBPRDY_BITS bit; +}; + +struct FPAC1_BITS { // bits description + Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count + Uint16 rsvd2:4; // 31:28 Reserved +}; + +union FPAC1_REG { + Uint32 all; + struct FPAC1_BITS bit; +}; + +struct FMSTAT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status + Uint16 CSTAT:1; // 4 Command Fail Status + Uint16 INVDAT:1; // 5 Invalid Data + Uint16 PGM:1; // 6 Program Operation Status + Uint16 ERS:1; // 7 Erase Operation Status + Uint16 BUSY:1; // 8 Busy Bit + Uint16 rsvd4:1; // 9 Reserved + Uint16 EV:1; // 10 Erase Verify Status + Uint16 rsvd5:1; // 11 Reserved + Uint16 PGV:1; // 12 Programming Verify Status + Uint16 rsvd6:1; // 13 Reserved + Uint16 rsvd7:1; // 14 Reserved + Uint16 rsvd8:1; // 15 Reserved + Uint16 rsvd9:1; // 16 Reserved + Uint16 rsvd10:1; // 17 Reserved + Uint16 rsvd11:14; // 31:18 Reserved +}; + +union FMSTAT_REG { + Uint32 all; + struct FMSTAT_BITS bit; +}; + +struct FRD_INTF_CTRL_BITS { // bits description + Uint16 PREFETCH_EN:1; // 0 Prefetch Enable + Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FRD_INTF_CTRL_REG { + Uint32 all; + struct FRD_INTF_CTRL_BITS bit; +}; + +struct FLASH_CTRL_REGS { + union FRDCNTL_REG FRDCNTL; // Flash Read Control Register + Uint16 rsvd1[28]; // Reserved + union FBAC_REG FBAC; // Flash Bank Access Control Register + union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register + union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register + union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 + Uint16 rsvd2[4]; // Reserved + union FMSTAT_REG FMSTAT; // Flash Module Status Register + Uint16 rsvd3[340]; // Reserved + union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register +}; + +struct ECC_ENABLE_BITS { // bits description + Uint16 ENABLE:4; // 3:0 Enable ECC + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ECC_ENABLE_REG { + Uint32 all; + struct ECC_ENABLE_BITS bit; +}; + +struct ERR_STATUS_BITS { // bits description + Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 + Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 + Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 + Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 + Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred + Uint16 rsvd2:13; // 31:19 Reserved +}; + +union ERR_STATUS_REG { + Uint32 all; + struct ERR_STATUS_BITS bit; +}; + +struct ERR_POS_BITS { // bits description + Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits + Uint16 rsvd2:7; // 15:9 Reserved + Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits + Uint16 rsvd4:7; // 31:25 Reserved +}; + +union ERR_POS_REG { + Uint32 all; + struct ERR_POS_BITS bit; +}; + +struct ERR_STATUS_CLR_BITS { // bits description + Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear + Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear + Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear + Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear + Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear + Uint16 rsvd2:13; // 31:19 Reserved +}; + +union ERR_STATUS_CLR_REG { + Uint32 all; + struct ERR_STATUS_CLR_BITS bit; +}; + +struct ERR_CNT_BITS { // bits description + Uint16 ERR_CNT:16; // 15:0 Error counter + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union ERR_CNT_REG { + Uint32 all; + struct ERR_CNT_BITS bit; +}; + +struct ERR_THRESHOLD_BITS { // bits description + Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union ERR_THRESHOLD_REG { + Uint32 all; + struct ERR_THRESHOLD_BITS bit; +}; + +struct ERR_INTFLG_BITS { // bits description + Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag + Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ERR_INTFLG_REG { + Uint32 all; + struct ERR_INTFLG_BITS bit; +}; + +struct ERR_INTCLR_BITS { // bits description + Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear + Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ERR_INTCLR_REG { + Uint32 all; + struct ERR_INTCLR_BITS bit; +}; + +struct FADDR_TEST_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 ADDRL:13; // 15:3 ECC Address Low + Uint16 ADDRH:6; // 21:16 ECC Address High + Uint16 rsvd2:10; // 31:22 Reserved +}; + +union FADDR_TEST_REG { + Uint32 all; + struct FADDR_TEST_BITS bit; +}; + +struct FECC_TEST_BITS { // bits description + Uint16 ECC:8; // 7:0 ECC Control Bits + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FECC_TEST_REG { + Uint32 all; + struct FECC_TEST_BITS bit; +}; + +struct FECC_CTRL_BITS { // bits description + Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic + Uint16 ECC_SELECT:1; // 1 ECC Bit Select + Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FECC_CTRL_REG { + Uint32 all; + struct FECC_CTRL_BITS bit; +}; + +struct FECC_STATUS_BITS { // bits description + Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error + Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error + Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error + Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error + Uint16 rsvd1:7; // 15:9 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FECC_STATUS_REG { + Uint32 all; + struct FECC_STATUS_BITS bit; +}; + +struct FLASH_ECC_REGS { + union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable + Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low + Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High + Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low + Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High + union ERR_STATUS_REG ERR_STATUS; // Error Status + union ERR_POS_REG ERR_POS; // Error Position + union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear + union ERR_CNT_REG ERR_CNT; // Error Control + union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold + union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag + union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear + Uint32 FDATAH_TEST; // Data High Test + Uint32 FDATAL_TEST; // Data Low Test + union FADDR_TEST_REG FADDR_TEST; // ECC Test Address + union FECC_TEST_REG FECC_TEST; // ECC Test Address + union FECC_CTRL_REG FECC_CTRL; // ECC Control + Uint32 FOUTH_TEST; // Test Data Out High + Uint32 FOUTL_TEST; // Test Data Out Low + union FECC_STATUS_REG FECC_STATUS; // ECC Status +}; + +struct PUMPREQUEST_BITS { // bits description + Uint16 PUMP_OWNERSHIP:2; // 1:0 Flash Pump Request Semaphore between CPU1 and CPU2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register +}; + +union PUMPREQUEST_REG { + Uint32 all; + struct PUMPREQUEST_BITS bit; +}; + +struct FLASH_PUMP_SEMAPHORE_REGS { + union PUMPREQUEST_REG PUMPREQUEST; // Flash programming semaphore PUMP request register +}; + +//--------------------------------------------------------------------------- +// FLASH External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; +extern volatile struct FLASH_ECC_REGS Flash0EccRegs; +#endif +#ifdef CPU2 +extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; +extern volatile struct FLASH_ECC_REGS Flash0EccRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_gpio.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_gpio.h new file mode 100644 index 00000000000..7aeb219836a --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_gpio.h @@ -0,0 +1,3882 @@ +//########################################################################### +// +// FILE: F2837xD_gpio.h +// +// TITLE: GPIO Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_GPIO_H__ +#define __F2837xD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// GPIO Individual Register Bit Definitions: + +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO0 to GPIO7 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO8 to GPIO15 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO16 to GPIO23 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO24 to GPIO31 +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +struct GPAQSEL1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 Select input qualification type for GPIO0 + Uint16 GPIO1:2; // 3:2 Select input qualification type for GPIO1 + Uint16 GPIO2:2; // 5:4 Select input qualification type for GPIO2 + Uint16 GPIO3:2; // 7:6 Select input qualification type for GPIO3 + Uint16 GPIO4:2; // 9:8 Select input qualification type for GPIO4 + Uint16 GPIO5:2; // 11:10 Select input qualification type for GPIO5 + Uint16 GPIO6:2; // 13:12 Select input qualification type for GPIO6 + Uint16 GPIO7:2; // 15:14 Select input qualification type for GPIO7 + Uint16 GPIO8:2; // 17:16 Select input qualification type for GPIO8 + Uint16 GPIO9:2; // 19:18 Select input qualification type for GPIO9 + Uint16 GPIO10:2; // 21:20 Select input qualification type for GPIO10 + Uint16 GPIO11:2; // 23:22 Select input qualification type for GPIO11 + Uint16 GPIO12:2; // 25:24 Select input qualification type for GPIO12 + Uint16 GPIO13:2; // 27:26 Select input qualification type for GPIO13 + Uint16 GPIO14:2; // 29:28 Select input qualification type for GPIO14 + Uint16 GPIO15:2; // 31:30 Select input qualification type for GPIO15 +}; + +union GPAQSEL1_REG { + Uint32 all; + struct GPAQSEL1_BITS bit; +}; + +struct GPAQSEL2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 Select input qualification type for GPIO16 + Uint16 GPIO17:2; // 3:2 Select input qualification type for GPIO17 + Uint16 GPIO18:2; // 5:4 Select input qualification type for GPIO18 + Uint16 GPIO19:2; // 7:6 Select input qualification type for GPIO19 + Uint16 GPIO20:2; // 9:8 Select input qualification type for GPIO20 + Uint16 GPIO21:2; // 11:10 Select input qualification type for GPIO21 + Uint16 GPIO22:2; // 13:12 Select input qualification type for GPIO22 + Uint16 GPIO23:2; // 15:14 Select input qualification type for GPIO23 + Uint16 GPIO24:2; // 17:16 Select input qualification type for GPIO24 + Uint16 GPIO25:2; // 19:18 Select input qualification type for GPIO25 + Uint16 GPIO26:2; // 21:20 Select input qualification type for GPIO26 + Uint16 GPIO27:2; // 23:22 Select input qualification type for GPIO27 + Uint16 GPIO28:2; // 25:24 Select input qualification type for GPIO28 + Uint16 GPIO29:2; // 27:26 Select input qualification type for GPIO29 + Uint16 GPIO30:2; // 29:28 Select input qualification type for GPIO30 + Uint16 GPIO31:2; // 31:30 Select input qualification type for GPIO31 +}; + +union GPAQSEL2_REG { + Uint32 all; + struct GPAQSEL2_BITS bit; +}; + +struct GPAMUX1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 + Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 + Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 + Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 + Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 + Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 + Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 + Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 + Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 + Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 + Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 + Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 + Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 + Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 + Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 + Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 +}; + +union GPAMUX1_REG { + Uint32 all; + struct GPAMUX1_BITS bit; +}; + +struct GPAMUX2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 + Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 + Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 + Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 + Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 + Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 + Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 + Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 + Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 + Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 + Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 + Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 + Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 + Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 + Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 + Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 +}; + +union GPAMUX2_REG { + Uint32 all; + struct GPAMUX2_BITS bit; +}; + +struct GPADIR_BITS { // bits description + Uint16 GPIO0:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO1:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO2:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO3:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO4:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO5:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO6:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO7:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO8:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO9:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO10:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO11:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO12:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO13:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO14:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO15:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO16:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO17:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO18:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO19:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO20:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO21:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO22:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO23:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO24:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO25:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO26:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO27:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO28:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO29:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO30:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO31:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPADIR_REG { + Uint32 all; + struct GPADIR_BITS bit; +}; + +struct GPAPUD_BITS { // bits description + Uint16 GPIO0:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO1:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO2:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO3:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO4:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO5:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO6:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO7:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO8:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO9:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO10:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO11:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO12:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO13:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO14:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO15:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO16:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO17:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO18:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO19:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO20:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO21:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO22:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO23:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO24:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO25:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO26:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO27:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO28:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO29:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO30:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO31:1; // 31 Pull-Up Disable control for this pin +}; + +union GPAPUD_REG { + Uint32 all; + struct GPAPUD_BITS bit; +}; + +struct GPAINV_BITS { // bits description + Uint16 GPIO0:1; // 0 Input inversion control for this pin + Uint16 GPIO1:1; // 1 Input inversion control for this pin + Uint16 GPIO2:1; // 2 Input inversion control for this pin + Uint16 GPIO3:1; // 3 Input inversion control for this pin + Uint16 GPIO4:1; // 4 Input inversion control for this pin + Uint16 GPIO5:1; // 5 Input inversion control for this pin + Uint16 GPIO6:1; // 6 Input inversion control for this pin + Uint16 GPIO7:1; // 7 Input inversion control for this pin + Uint16 GPIO8:1; // 8 Input inversion control for this pin + Uint16 GPIO9:1; // 9 Input inversion control for this pin + Uint16 GPIO10:1; // 10 Input inversion control for this pin + Uint16 GPIO11:1; // 11 Input inversion control for this pin + Uint16 GPIO12:1; // 12 Input inversion control for this pin + Uint16 GPIO13:1; // 13 Input inversion control for this pin + Uint16 GPIO14:1; // 14 Input inversion control for this pin + Uint16 GPIO15:1; // 15 Input inversion control for this pin + Uint16 GPIO16:1; // 16 Input inversion control for this pin + Uint16 GPIO17:1; // 17 Input inversion control for this pin + Uint16 GPIO18:1; // 18 Input inversion control for this pin + Uint16 GPIO19:1; // 19 Input inversion control for this pin + Uint16 GPIO20:1; // 20 Input inversion control for this pin + Uint16 GPIO21:1; // 21 Input inversion control for this pin + Uint16 GPIO22:1; // 22 Input inversion control for this pin + Uint16 GPIO23:1; // 23 Input inversion control for this pin + Uint16 GPIO24:1; // 24 Input inversion control for this pin + Uint16 GPIO25:1; // 25 Input inversion control for this pin + Uint16 GPIO26:1; // 26 Input inversion control for this pin + Uint16 GPIO27:1; // 27 Input inversion control for this pin + Uint16 GPIO28:1; // 28 Input inversion control for this pin + Uint16 GPIO29:1; // 29 Input inversion control for this pin + Uint16 GPIO30:1; // 30 Input inversion control for this pin + Uint16 GPIO31:1; // 31 Input inversion control for this pin +}; + +union GPAINV_REG { + Uint32 all; + struct GPAINV_BITS bit; +}; + +struct GPAODR_BITS { // bits description + Uint16 GPIO0:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO1:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO2:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO3:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO4:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO5:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO6:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO7:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO8:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO9:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO10:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO11:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO12:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO13:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO14:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO15:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO16:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO17:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO18:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO19:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO20:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO21:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO22:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO23:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO24:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO25:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO26:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO27:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO28:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO29:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO30:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO31:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPAODR_REG { + Uint32 all; + struct GPAODR_BITS bit; +}; + +struct GPAGMUX1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 + Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 + Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 + Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 + Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 + Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 + Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 + Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 + Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 + Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 + Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 + Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 + Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 + Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 + Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 + Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 +}; + +union GPAGMUX1_REG { + Uint32 all; + struct GPAGMUX1_BITS bit; +}; + +struct GPAGMUX2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 + Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 + Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 + Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 + Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 + Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 + Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 + Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 + Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 + Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 + Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 + Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 + Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 + Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 + Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 + Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 +}; + +union GPAGMUX2_REG { + Uint32 all; + struct GPAGMUX2_BITS bit; +}; + +struct GPACSEL1_BITS { // bits description + Uint16 GPIO0:4; // 3:0 GPIO0 Master CPU Select + Uint16 GPIO1:4; // 7:4 GPIO1 Master CPU Select + Uint16 GPIO2:4; // 11:8 GPIO2 Master CPU Select + Uint16 GPIO3:4; // 15:12 GPIO3 Master CPU Select + Uint16 GPIO4:4; // 19:16 GPIO4 Master CPU Select + Uint16 GPIO5:4; // 23:20 GPIO5 Master CPU Select + Uint16 GPIO6:4; // 27:24 GPIO6 Master CPU Select + Uint16 GPIO7:4; // 31:28 GPIO7 Master CPU Select +}; + +union GPACSEL1_REG { + Uint32 all; + struct GPACSEL1_BITS bit; +}; + +struct GPACSEL2_BITS { // bits description + Uint16 GPIO8:4; // 3:0 GPIO8 Master CPU Select + Uint16 GPIO9:4; // 7:4 GPIO9 Master CPU Select + Uint16 GPIO10:4; // 11:8 GPIO10 Master CPU Select + Uint16 GPIO11:4; // 15:12 GPIO11 Master CPU Select + Uint16 GPIO12:4; // 19:16 GPIO12 Master CPU Select + Uint16 GPIO13:4; // 23:20 GPIO13 Master CPU Select + Uint16 GPIO14:4; // 27:24 GPIO14 Master CPU Select + Uint16 GPIO15:4; // 31:28 GPIO15 Master CPU Select +}; + +union GPACSEL2_REG { + Uint32 all; + struct GPACSEL2_BITS bit; +}; + +struct GPACSEL3_BITS { // bits description + Uint16 GPIO16:4; // 3:0 GPIO16 Master CPU Select + Uint16 GPIO17:4; // 7:4 GPIO17 Master CPU Select + Uint16 GPIO18:4; // 11:8 GPIO18 Master CPU Select + Uint16 GPIO19:4; // 15:12 GPIO19 Master CPU Select + Uint16 GPIO20:4; // 19:16 GPIO20 Master CPU Select + Uint16 GPIO21:4; // 23:20 GPIO21 Master CPU Select + Uint16 GPIO22:4; // 27:24 GPIO22 Master CPU Select + Uint16 GPIO23:4; // 31:28 GPIO23 Master CPU Select +}; + +union GPACSEL3_REG { + Uint32 all; + struct GPACSEL3_BITS bit; +}; + +struct GPACSEL4_BITS { // bits description + Uint16 GPIO24:4; // 3:0 GPIO24 Master CPU Select + Uint16 GPIO25:4; // 7:4 GPIO25 Master CPU Select + Uint16 GPIO26:4; // 11:8 GPIO26 Master CPU Select + Uint16 GPIO27:4; // 15:12 GPIO27 Master CPU Select + Uint16 GPIO28:4; // 19:16 GPIO28 Master CPU Select + Uint16 GPIO29:4; // 23:20 GPIO29 Master CPU Select + Uint16 GPIO30:4; // 27:24 GPIO30 Master CPU Select + Uint16 GPIO31:4; // 31:28 GPIO31 Master CPU Select +}; + +union GPACSEL4_REG { + Uint32 all; + struct GPACSEL4_BITS bit; +}; + +struct GPALOCK_BITS { // bits description + Uint16 GPIO0:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO1:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO2:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO3:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO4:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO5:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO6:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO7:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO8:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO9:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO10:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO11:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO12:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO13:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO14:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO15:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO16:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO17:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO18:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO19:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO20:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO21:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO22:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO23:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO24:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO25:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO26:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO27:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO28:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO29:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO30:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO31:1; // 31 Configuration Lock bit for this pin +}; + +union GPALOCK_REG { + Uint32 all; + struct GPALOCK_BITS bit; +}; + +struct GPACR_BITS { // bits description + Uint16 GPIO0:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO1:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO2:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO3:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO4:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO5:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO6:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO7:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO8:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO9:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO10:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO11:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO12:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO13:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO14:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO15:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO16:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO17:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO18:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO19:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO20:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO21:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO22:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO23:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO24:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO25:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO26:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO27:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO28:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO29:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO30:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO31:1; // 31 Configuration lock commit bit for this pin +}; + +union GPACR_REG { + Uint32 all; + struct GPACR_BITS bit; +}; + +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO32 to GPIO39 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO40 to GPIO47 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO48 to GPIO55 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO56 to GPIO63 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +struct GPBQSEL1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 Select input qualification type for GPIO32 + Uint16 GPIO33:2; // 3:2 Select input qualification type for GPIO33 + Uint16 GPIO34:2; // 5:4 Select input qualification type for GPIO34 + Uint16 GPIO35:2; // 7:6 Select input qualification type for GPIO35 + Uint16 GPIO36:2; // 9:8 Select input qualification type for GPIO36 + Uint16 GPIO37:2; // 11:10 Select input qualification type for GPIO37 + Uint16 GPIO38:2; // 13:12 Select input qualification type for GPIO38 + Uint16 GPIO39:2; // 15:14 Select input qualification type for GPIO39 + Uint16 GPIO40:2; // 17:16 Select input qualification type for GPIO40 + Uint16 GPIO41:2; // 19:18 Select input qualification type for GPIO41 + Uint16 GPIO42:2; // 21:20 Select input qualification type for GPIO42 + Uint16 GPIO43:2; // 23:22 Select input qualification type for GPIO43 + Uint16 GPIO44:2; // 25:24 Select input qualification type for GPIO44 + Uint16 GPIO45:2; // 27:26 Select input qualification type for GPIO45 + Uint16 GPIO46:2; // 29:28 Select input qualification type for GPIO46 + Uint16 GPIO47:2; // 31:30 Select input qualification type for GPIO47 +}; + +union GPBQSEL1_REG { + Uint32 all; + struct GPBQSEL1_BITS bit; +}; + +struct GPBQSEL2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 Select input qualification type for GPIO48 + Uint16 GPIO49:2; // 3:2 Select input qualification type for GPIO49 + Uint16 GPIO50:2; // 5:4 Select input qualification type for GPIO50 + Uint16 GPIO51:2; // 7:6 Select input qualification type for GPIO51 + Uint16 GPIO52:2; // 9:8 Select input qualification type for GPIO52 + Uint16 GPIO53:2; // 11:10 Select input qualification type for GPIO53 + Uint16 GPIO54:2; // 13:12 Select input qualification type for GPIO54 + Uint16 GPIO55:2; // 15:14 Select input qualification type for GPIO55 + Uint16 GPIO56:2; // 17:16 Select input qualification type for GPIO56 + Uint16 GPIO57:2; // 19:18 Select input qualification type for GPIO57 + Uint16 GPIO58:2; // 21:20 Select input qualification type for GPIO58 + Uint16 GPIO59:2; // 23:22 Select input qualification type for GPIO59 + Uint16 GPIO60:2; // 25:24 Select input qualification type for GPIO60 + Uint16 GPIO61:2; // 27:26 Select input qualification type for GPIO61 + Uint16 GPIO62:2; // 29:28 Select input qualification type for GPIO62 + Uint16 GPIO63:2; // 31:30 Select input qualification type for GPIO63 +}; + +union GPBQSEL2_REG { + Uint32 all; + struct GPBQSEL2_BITS bit; +}; + +struct GPBMUX1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 + Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 + Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 + Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 + Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 + Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 + Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 + Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 + Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 + Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 + Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 + Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 + Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 + Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 + Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 + Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 +}; + +union GPBMUX1_REG { + Uint32 all; + struct GPBMUX1_BITS bit; +}; + +struct GPBMUX2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 + Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 + Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 + Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 + Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 + Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 + Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 + Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 + Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 + Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 + Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 + Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 + Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 + Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 + Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 + Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 +}; + +union GPBMUX2_REG { + Uint32 all; + struct GPBMUX2_BITS bit; +}; + +struct GPBDIR_BITS { // bits description + Uint16 GPIO32:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO33:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO34:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO35:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO36:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO37:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO38:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO39:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO40:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO41:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO42:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO43:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO44:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO45:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO46:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO47:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO48:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO49:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO50:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO51:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO52:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO53:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO54:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO55:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO56:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO57:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO58:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO59:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO60:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO61:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO62:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO63:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPBDIR_REG { + Uint32 all; + struct GPBDIR_BITS bit; +}; + +struct GPBPUD_BITS { // bits description + Uint16 GPIO32:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO33:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO34:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO35:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO36:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO37:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO38:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO39:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO40:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO41:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO42:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO43:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO44:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO45:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO46:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO47:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO48:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO49:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO50:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO51:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO52:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO53:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO54:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO55:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO56:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO57:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO58:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO59:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO60:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO61:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO62:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO63:1; // 31 Pull-Up Disable control for this pin +}; + +union GPBPUD_REG { + Uint32 all; + struct GPBPUD_BITS bit; +}; + +struct GPBINV_BITS { // bits description + Uint16 GPIO32:1; // 0 Input inversion control for this pin + Uint16 GPIO33:1; // 1 Input inversion control for this pin + Uint16 GPIO34:1; // 2 Input inversion control for this pin + Uint16 GPIO35:1; // 3 Input inversion control for this pin + Uint16 GPIO36:1; // 4 Input inversion control for this pin + Uint16 GPIO37:1; // 5 Input inversion control for this pin + Uint16 GPIO38:1; // 6 Input inversion control for this pin + Uint16 GPIO39:1; // 7 Input inversion control for this pin + Uint16 GPIO40:1; // 8 Input inversion control for this pin + Uint16 GPIO41:1; // 9 Input inversion control for this pin + Uint16 GPIO42:1; // 10 Input inversion control for this pin + Uint16 GPIO43:1; // 11 Input inversion control for this pin + Uint16 GPIO44:1; // 12 Input inversion control for this pin + Uint16 GPIO45:1; // 13 Input inversion control for this pin + Uint16 GPIO46:1; // 14 Input inversion control for this pin + Uint16 GPIO47:1; // 15 Input inversion control for this pin + Uint16 GPIO48:1; // 16 Input inversion control for this pin + Uint16 GPIO49:1; // 17 Input inversion control for this pin + Uint16 GPIO50:1; // 18 Input inversion control for this pin + Uint16 GPIO51:1; // 19 Input inversion control for this pin + Uint16 GPIO52:1; // 20 Input inversion control for this pin + Uint16 GPIO53:1; // 21 Input inversion control for this pin + Uint16 GPIO54:1; // 22 Input inversion control for this pin + Uint16 GPIO55:1; // 23 Input inversion control for this pin + Uint16 GPIO56:1; // 24 Input inversion control for this pin + Uint16 GPIO57:1; // 25 Input inversion control for this pin + Uint16 GPIO58:1; // 26 Input inversion control for this pin + Uint16 GPIO59:1; // 27 Input inversion control for this pin + Uint16 GPIO60:1; // 28 Input inversion control for this pin + Uint16 GPIO61:1; // 29 Input inversion control for this pin + Uint16 GPIO62:1; // 30 Input inversion control for this pin + Uint16 GPIO63:1; // 31 Input inversion control for this pin +}; + +union GPBINV_REG { + Uint32 all; + struct GPBINV_BITS bit; +}; + +struct GPBODR_BITS { // bits description + Uint16 GPIO32:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO33:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO34:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO35:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO36:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO37:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO38:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO39:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO40:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO41:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO42:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO43:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO44:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO45:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO46:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO47:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO48:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO49:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO50:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO51:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO52:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO53:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO54:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO55:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO56:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO57:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO58:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO59:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO60:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO61:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO62:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO63:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPBODR_REG { + Uint32 all; + struct GPBODR_BITS bit; +}; + +struct GPBAMSEL_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:1; // 4 Reserved + Uint16 rsvd6:1; // 5 Reserved + Uint16 rsvd7:1; // 6 Reserved + Uint16 rsvd8:1; // 7 Reserved + Uint16 rsvd9:1; // 8 Reserved + Uint16 rsvd10:1; // 9 Reserved + Uint16 GPIO42:1; // 10 Analog Mode select for this pin + Uint16 GPIO43:1; // 11 Analog Mode select for this pin + Uint16 rsvd11:1; // 12 Reserved + Uint16 rsvd12:1; // 13 Reserved + Uint16 rsvd13:1; // 14 Reserved + Uint16 rsvd14:1; // 15 Reserved + Uint16 rsvd15:1; // 16 Reserved + Uint16 rsvd16:1; // 17 Reserved + Uint16 rsvd17:1; // 18 Reserved + Uint16 rsvd18:1; // 19 Reserved + Uint16 rsvd19:1; // 20 Reserved + Uint16 rsvd20:1; // 21 Reserved + Uint16 rsvd21:1; // 22 Reserved + Uint16 rsvd22:1; // 23 Reserved + Uint16 rsvd23:1; // 24 Reserved + Uint16 rsvd24:1; // 25 Reserved + Uint16 rsvd25:1; // 26 Reserved + Uint16 rsvd26:1; // 27 Reserved + Uint16 rsvd27:1; // 28 Reserved + Uint16 rsvd28:1; // 29 Reserved + Uint16 rsvd29:1; // 30 Reserved + Uint16 rsvd30:1; // 31 Reserved +}; + +union GPBAMSEL_REG { + Uint32 all; + struct GPBAMSEL_BITS bit; +}; + +struct GPBGMUX1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 + Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 + Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 + Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 + Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 + Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 + Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 + Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 + Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 + Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 + Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 + Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 + Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 + Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 + Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 + Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 +}; + +union GPBGMUX1_REG { + Uint32 all; + struct GPBGMUX1_BITS bit; +}; + +struct GPBGMUX2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 + Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 + Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 + Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 + Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 + Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 + Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 + Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 + Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 + Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 + Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 + Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 + Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 + Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 + Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 + Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 +}; + +union GPBGMUX2_REG { + Uint32 all; + struct GPBGMUX2_BITS bit; +}; + +struct GPBCSEL1_BITS { // bits description + Uint16 GPIO32:4; // 3:0 GPIO32 Master CPU Select + Uint16 GPIO33:4; // 7:4 GPIO33 Master CPU Select + Uint16 GPIO34:4; // 11:8 GPIO34 Master CPU Select + Uint16 GPIO35:4; // 15:12 GPIO35 Master CPU Select + Uint16 GPIO36:4; // 19:16 GPIO36 Master CPU Select + Uint16 GPIO37:4; // 23:20 GPIO37 Master CPU Select + Uint16 GPIO38:4; // 27:24 GPIO38 Master CPU Select + Uint16 GPIO39:4; // 31:28 GPIO39 Master CPU Select +}; + +union GPBCSEL1_REG { + Uint32 all; + struct GPBCSEL1_BITS bit; +}; + +struct GPBCSEL2_BITS { // bits description + Uint16 GPIO40:4; // 3:0 GPIO40 Master CPU Select + Uint16 GPIO41:4; // 7:4 GPIO41 Master CPU Select + Uint16 GPIO42:4; // 11:8 GPIO42 Master CPU Select + Uint16 GPIO43:4; // 15:12 GPIO43 Master CPU Select + Uint16 GPIO44:4; // 19:16 GPIO44 Master CPU Select + Uint16 GPIO45:4; // 23:20 GPIO45 Master CPU Select + Uint16 GPIO46:4; // 27:24 GPIO46 Master CPU Select + Uint16 GPIO47:4; // 31:28 GPIO47 Master CPU Select +}; + +union GPBCSEL2_REG { + Uint32 all; + struct GPBCSEL2_BITS bit; +}; + +struct GPBCSEL3_BITS { // bits description + Uint16 GPIO48:4; // 3:0 GPIO48 Master CPU Select + Uint16 GPIO49:4; // 7:4 GPIO49 Master CPU Select + Uint16 GPIO50:4; // 11:8 GPIO50 Master CPU Select + Uint16 GPIO51:4; // 15:12 GPIO51 Master CPU Select + Uint16 GPIO52:4; // 19:16 GPIO52 Master CPU Select + Uint16 GPIO53:4; // 23:20 GPIO53 Master CPU Select + Uint16 GPIO54:4; // 27:24 GPIO54 Master CPU Select + Uint16 GPIO55:4; // 31:28 GPIO55 Master CPU Select +}; + +union GPBCSEL3_REG { + Uint32 all; + struct GPBCSEL3_BITS bit; +}; + +struct GPBCSEL4_BITS { // bits description + Uint16 GPIO56:4; // 3:0 GPIO56 Master CPU Select + Uint16 GPIO57:4; // 7:4 GPIO57 Master CPU Select + Uint16 GPIO58:4; // 11:8 GPIO58 Master CPU Select + Uint16 GPIO59:4; // 15:12 GPIO59 Master CPU Select + Uint16 GPIO60:4; // 19:16 GPIO60 Master CPU Select + Uint16 GPIO61:4; // 23:20 GPIO61 Master CPU Select + Uint16 GPIO62:4; // 27:24 GPIO62 Master CPU Select + Uint16 GPIO63:4; // 31:28 GPIO63 Master CPU Select +}; + +union GPBCSEL4_REG { + Uint32 all; + struct GPBCSEL4_BITS bit; +}; + +struct GPBLOCK_BITS { // bits description + Uint16 GPIO32:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO33:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO34:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO35:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO36:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO37:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO38:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO39:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO40:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO41:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO42:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO43:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO44:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO45:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO46:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO47:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO48:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO49:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO50:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO51:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO52:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO53:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO54:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO55:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO56:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO57:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO58:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO59:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO60:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO61:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO62:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO63:1; // 31 Configuration Lock bit for this pin +}; + +union GPBLOCK_REG { + Uint32 all; + struct GPBLOCK_BITS bit; +}; + +struct GPBCR_BITS { // bits description + Uint16 GPIO32:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO33:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO34:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO35:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO36:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO37:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO38:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO39:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO40:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO41:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO42:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO43:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO44:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO45:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO46:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO47:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO48:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO49:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO50:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO51:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO52:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO53:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO54:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO55:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO56:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO57:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO58:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO59:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO60:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO61:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO62:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO63:1; // 31 Configuration lock commit bit for this pin +}; + +union GPBCR_REG { + Uint32 all; + struct GPBCR_BITS bit; +}; + +struct GPCCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO64 to GPIO71 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO72 to GPIO79 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO80 to GPIO87 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO88 to GPIO95 +}; + +union GPCCTRL_REG { + Uint32 all; + struct GPCCTRL_BITS bit; +}; + +struct GPCQSEL1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 Select input qualification type for GPIO64 + Uint16 GPIO65:2; // 3:2 Select input qualification type for GPIO65 + Uint16 GPIO66:2; // 5:4 Select input qualification type for GPIO66 + Uint16 GPIO67:2; // 7:6 Select input qualification type for GPIO67 + Uint16 GPIO68:2; // 9:8 Select input qualification type for GPIO68 + Uint16 GPIO69:2; // 11:10 Select input qualification type for GPIO69 + Uint16 GPIO70:2; // 13:12 Select input qualification type for GPIO70 + Uint16 GPIO71:2; // 15:14 Select input qualification type for GPIO71 + Uint16 GPIO72:2; // 17:16 Select input qualification type for GPIO72 + Uint16 GPIO73:2; // 19:18 Select input qualification type for GPIO73 + Uint16 GPIO74:2; // 21:20 Select input qualification type for GPIO74 + Uint16 GPIO75:2; // 23:22 Select input qualification type for GPIO75 + Uint16 GPIO76:2; // 25:24 Select input qualification type for GPIO76 + Uint16 GPIO77:2; // 27:26 Select input qualification type for GPIO77 + Uint16 GPIO78:2; // 29:28 Select input qualification type for GPIO78 + Uint16 GPIO79:2; // 31:30 Select input qualification type for GPIO79 +}; + +union GPCQSEL1_REG { + Uint32 all; + struct GPCQSEL1_BITS bit; +}; + +struct GPCQSEL2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 Select input qualification type for GPIO80 + Uint16 GPIO81:2; // 3:2 Select input qualification type for GPIO81 + Uint16 GPIO82:2; // 5:4 Select input qualification type for GPIO82 + Uint16 GPIO83:2; // 7:6 Select input qualification type for GPIO83 + Uint16 GPIO84:2; // 9:8 Select input qualification type for GPIO84 + Uint16 GPIO85:2; // 11:10 Select input qualification type for GPIO85 + Uint16 GPIO86:2; // 13:12 Select input qualification type for GPIO86 + Uint16 GPIO87:2; // 15:14 Select input qualification type for GPIO87 + Uint16 GPIO88:2; // 17:16 Select input qualification type for GPIO88 + Uint16 GPIO89:2; // 19:18 Select input qualification type for GPIO89 + Uint16 GPIO90:2; // 21:20 Select input qualification type for GPIO90 + Uint16 GPIO91:2; // 23:22 Select input qualification type for GPIO91 + Uint16 GPIO92:2; // 25:24 Select input qualification type for GPIO92 + Uint16 GPIO93:2; // 27:26 Select input qualification type for GPIO93 + Uint16 GPIO94:2; // 29:28 Select input qualification type for GPIO94 + Uint16 GPIO95:2; // 31:30 Select input qualification type for GPIO95 +}; + +union GPCQSEL2_REG { + Uint32 all; + struct GPCQSEL2_BITS bit; +}; + +struct GPCMUX1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 + Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 + Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 + Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 + Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 + Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 + Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 + Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 + Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 + Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 + Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 + Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 + Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 + Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 + Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 + Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 +}; + +union GPCMUX1_REG { + Uint32 all; + struct GPCMUX1_BITS bit; +}; + +struct GPCMUX2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 + Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 + Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 + Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 + Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 + Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 + Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 + Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 + Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 + Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 + Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 + Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 + Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 + Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 + Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 + Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 +}; + +union GPCMUX2_REG { + Uint32 all; + struct GPCMUX2_BITS bit; +}; + +struct GPCDIR_BITS { // bits description + Uint16 GPIO64:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO65:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO66:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO67:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO68:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO69:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO70:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO71:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO72:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO73:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO74:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO75:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO76:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO77:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO78:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO79:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO80:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO81:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO82:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO83:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO84:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO85:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO86:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO87:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO88:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO89:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO90:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO91:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO92:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO93:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO94:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO95:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPCDIR_REG { + Uint32 all; + struct GPCDIR_BITS bit; +}; + +struct GPCPUD_BITS { // bits description + Uint16 GPIO64:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO65:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO66:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO67:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO68:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO69:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO70:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO71:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO72:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO73:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO74:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO75:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO76:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO77:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO78:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO79:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO80:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO81:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO82:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO83:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO84:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO85:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO86:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO87:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO88:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO89:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO90:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO91:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO92:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO93:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO94:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO95:1; // 31 Pull-Up Disable control for this pin +}; + +union GPCPUD_REG { + Uint32 all; + struct GPCPUD_BITS bit; +}; + +struct GPCINV_BITS { // bits description + Uint16 GPIO64:1; // 0 Input inversion control for this pin + Uint16 GPIO65:1; // 1 Input inversion control for this pin + Uint16 GPIO66:1; // 2 Input inversion control for this pin + Uint16 GPIO67:1; // 3 Input inversion control for this pin + Uint16 GPIO68:1; // 4 Input inversion control for this pin + Uint16 GPIO69:1; // 5 Input inversion control for this pin + Uint16 GPIO70:1; // 6 Input inversion control for this pin + Uint16 GPIO71:1; // 7 Input inversion control for this pin + Uint16 GPIO72:1; // 8 Input inversion control for this pin + Uint16 GPIO73:1; // 9 Input inversion control for this pin + Uint16 GPIO74:1; // 10 Input inversion control for this pin + Uint16 GPIO75:1; // 11 Input inversion control for this pin + Uint16 GPIO76:1; // 12 Input inversion control for this pin + Uint16 GPIO77:1; // 13 Input inversion control for this pin + Uint16 GPIO78:1; // 14 Input inversion control for this pin + Uint16 GPIO79:1; // 15 Input inversion control for this pin + Uint16 GPIO80:1; // 16 Input inversion control for this pin + Uint16 GPIO81:1; // 17 Input inversion control for this pin + Uint16 GPIO82:1; // 18 Input inversion control for this pin + Uint16 GPIO83:1; // 19 Input inversion control for this pin + Uint16 GPIO84:1; // 20 Input inversion control for this pin + Uint16 GPIO85:1; // 21 Input inversion control for this pin + Uint16 GPIO86:1; // 22 Input inversion control for this pin + Uint16 GPIO87:1; // 23 Input inversion control for this pin + Uint16 GPIO88:1; // 24 Input inversion control for this pin + Uint16 GPIO89:1; // 25 Input inversion control for this pin + Uint16 GPIO90:1; // 26 Input inversion control for this pin + Uint16 GPIO91:1; // 27 Input inversion control for this pin + Uint16 GPIO92:1; // 28 Input inversion control for this pin + Uint16 GPIO93:1; // 29 Input inversion control for this pin + Uint16 GPIO94:1; // 30 Input inversion control for this pin + Uint16 GPIO95:1; // 31 Input inversion control for this pin +}; + +union GPCINV_REG { + Uint32 all; + struct GPCINV_BITS bit; +}; + +struct GPCODR_BITS { // bits description + Uint16 GPIO64:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO65:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO66:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO67:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO68:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO69:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO70:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO71:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO72:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO73:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO74:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO75:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO76:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO77:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO78:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO79:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO80:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO81:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO82:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO83:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO84:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO85:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO86:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO87:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO88:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO89:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO90:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO91:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO92:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO93:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO94:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO95:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPCODR_REG { + Uint32 all; + struct GPCODR_BITS bit; +}; + +struct GPCGMUX1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 + Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 + Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 + Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 + Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 + Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 + Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 + Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 + Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 + Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 + Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 + Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 + Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 + Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 + Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 + Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 +}; + +union GPCGMUX1_REG { + Uint32 all; + struct GPCGMUX1_BITS bit; +}; + +struct GPCGMUX2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 + Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 + Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 + Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 + Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 + Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 + Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 + Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 + Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 + Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 + Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 + Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 + Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 + Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 + Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 + Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 +}; + +union GPCGMUX2_REG { + Uint32 all; + struct GPCGMUX2_BITS bit; +}; + +struct GPCCSEL1_BITS { // bits description + Uint16 GPIO64:4; // 3:0 GPIO64 Master CPU Select + Uint16 GPIO65:4; // 7:4 GPIO65 Master CPU Select + Uint16 GPIO66:4; // 11:8 GPIO66 Master CPU Select + Uint16 GPIO67:4; // 15:12 GPIO67 Master CPU Select + Uint16 GPIO68:4; // 19:16 GPIO68 Master CPU Select + Uint16 GPIO69:4; // 23:20 GPIO69 Master CPU Select + Uint16 GPIO70:4; // 27:24 GPIO70 Master CPU Select + Uint16 GPIO71:4; // 31:28 GPIO71 Master CPU Select +}; + +union GPCCSEL1_REG { + Uint32 all; + struct GPCCSEL1_BITS bit; +}; + +struct GPCCSEL2_BITS { // bits description + Uint16 GPIO72:4; // 3:0 GPIO72 Master CPU Select + Uint16 GPIO73:4; // 7:4 GPIO73 Master CPU Select + Uint16 GPIO74:4; // 11:8 GPIO74 Master CPU Select + Uint16 GPIO75:4; // 15:12 GPIO75 Master CPU Select + Uint16 GPIO76:4; // 19:16 GPIO76 Master CPU Select + Uint16 GPIO77:4; // 23:20 GPIO77 Master CPU Select + Uint16 GPIO78:4; // 27:24 GPIO78 Master CPU Select + Uint16 GPIO79:4; // 31:28 GPIO79 Master CPU Select +}; + +union GPCCSEL2_REG { + Uint32 all; + struct GPCCSEL2_BITS bit; +}; + +struct GPCCSEL3_BITS { // bits description + Uint16 GPIO80:4; // 3:0 GPIO80 Master CPU Select + Uint16 GPIO81:4; // 7:4 GPIO81 Master CPU Select + Uint16 GPIO82:4; // 11:8 GPIO82 Master CPU Select + Uint16 GPIO83:4; // 15:12 GPIO83 Master CPU Select + Uint16 GPIO84:4; // 19:16 GPIO84 Master CPU Select + Uint16 GPIO85:4; // 23:20 GPIO85 Master CPU Select + Uint16 GPIO86:4; // 27:24 GPIO86 Master CPU Select + Uint16 GPIO87:4; // 31:28 GPIO87 Master CPU Select +}; + +union GPCCSEL3_REG { + Uint32 all; + struct GPCCSEL3_BITS bit; +}; + +struct GPCCSEL4_BITS { // bits description + Uint16 GPIO88:4; // 3:0 GPIO88 Master CPU Select + Uint16 GPIO89:4; // 7:4 GPIO89 Master CPU Select + Uint16 GPIO90:4; // 11:8 GPIO90 Master CPU Select + Uint16 GPIO91:4; // 15:12 GPIO91 Master CPU Select + Uint16 GPIO92:4; // 19:16 GPIO92 Master CPU Select + Uint16 GPIO93:4; // 23:20 GPIO93 Master CPU Select + Uint16 GPIO94:4; // 27:24 GPIO94 Master CPU Select + Uint16 GPIO95:4; // 31:28 GPIO95 Master CPU Select +}; + +union GPCCSEL4_REG { + Uint32 all; + struct GPCCSEL4_BITS bit; +}; + +struct GPCLOCK_BITS { // bits description + Uint16 GPIO64:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO65:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO66:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO67:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO68:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO69:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO70:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO71:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO72:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO73:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO74:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO75:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO76:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO77:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO78:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO79:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO80:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO81:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO82:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO83:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO84:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO85:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO86:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO87:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO88:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO89:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO90:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO91:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO92:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO93:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO94:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO95:1; // 31 Configuration Lock bit for this pin +}; + +union GPCLOCK_REG { + Uint32 all; + struct GPCLOCK_BITS bit; +}; + +struct GPCCR_BITS { // bits description + Uint16 GPIO64:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO65:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO66:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO67:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO68:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO69:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO70:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO71:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO72:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO73:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO74:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO75:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO76:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO77:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO78:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO79:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO80:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO81:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO82:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO83:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO84:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO85:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO86:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO87:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO88:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO89:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO90:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO91:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO92:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO93:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO94:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO95:1; // 31 Configuration lock commit bit for this pin +}; + +union GPCCR_REG { + Uint32 all; + struct GPCCR_BITS bit; +}; + +struct GPDCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO96 to GPIO103 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO104 to GPIO111 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO112 to GPIO119 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO120 to GPIO127 +}; + +union GPDCTRL_REG { + Uint32 all; + struct GPDCTRL_BITS bit; +}; + +struct GPDQSEL1_BITS { // bits description + Uint16 GPIO96:2; // 1:0 Select input qualification type for GPIO96 + Uint16 GPIO97:2; // 3:2 Select input qualification type for GPIO97 + Uint16 GPIO98:2; // 5:4 Select input qualification type for GPIO98 + Uint16 GPIO99:2; // 7:6 Select input qualification type for GPIO99 + Uint16 GPIO100:2; // 9:8 Select input qualification type for GPIO100 + Uint16 GPIO101:2; // 11:10 Select input qualification type for GPIO101 + Uint16 GPIO102:2; // 13:12 Select input qualification type for GPIO102 + Uint16 GPIO103:2; // 15:14 Select input qualification type for GPIO103 + Uint16 GPIO104:2; // 17:16 Select input qualification type for GPIO104 + Uint16 GPIO105:2; // 19:18 Select input qualification type for GPIO105 + Uint16 GPIO106:2; // 21:20 Select input qualification type for GPIO106 + Uint16 GPIO107:2; // 23:22 Select input qualification type for GPIO107 + Uint16 GPIO108:2; // 25:24 Select input qualification type for GPIO108 + Uint16 GPIO109:2; // 27:26 Select input qualification type for GPIO109 + Uint16 GPIO110:2; // 29:28 Select input qualification type for GPIO110 + Uint16 GPIO111:2; // 31:30 Select input qualification type for GPIO111 +}; + +union GPDQSEL1_REG { + Uint32 all; + struct GPDQSEL1_BITS bit; +}; + +struct GPDQSEL2_BITS { // bits description + Uint16 GPIO112:2; // 1:0 Select input qualification type for GPIO112 + Uint16 GPIO113:2; // 3:2 Select input qualification type for GPIO113 + Uint16 GPIO114:2; // 5:4 Select input qualification type for GPIO114 + Uint16 GPIO115:2; // 7:6 Select input qualification type for GPIO115 + Uint16 GPIO116:2; // 9:8 Select input qualification type for GPIO116 + Uint16 GPIO117:2; // 11:10 Select input qualification type for GPIO117 + Uint16 GPIO118:2; // 13:12 Select input qualification type for GPIO118 + Uint16 GPIO119:2; // 15:14 Select input qualification type for GPIO119 + Uint16 GPIO120:2; // 17:16 Select input qualification type for GPIO120 + Uint16 GPIO121:2; // 19:18 Select input qualification type for GPIO121 + Uint16 GPIO122:2; // 21:20 Select input qualification type for GPIO122 + Uint16 GPIO123:2; // 23:22 Select input qualification type for GPIO123 + Uint16 GPIO124:2; // 25:24 Select input qualification type for GPIO124 + Uint16 GPIO125:2; // 27:26 Select input qualification type for GPIO125 + Uint16 GPIO126:2; // 29:28 Select input qualification type for GPIO126 + Uint16 GPIO127:2; // 31:30 Select input qualification type for GPIO127 +}; + +union GPDQSEL2_REG { + Uint32 all; + struct GPDQSEL2_BITS bit; +}; + +struct GPDMUX1_BITS { // bits description + Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 + Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 + Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 + Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 + Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 + Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 + Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 + Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 + Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 + Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 + Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 + Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 + Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 + Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 + Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 + Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 +}; + +union GPDMUX1_REG { + Uint32 all; + struct GPDMUX1_BITS bit; +}; + +struct GPDMUX2_BITS { // bits description + Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 + Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 + Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 + Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 + Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 + Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 + Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 + Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 + Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 + Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 + Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 + Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 + Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 + Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 + Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 + Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 +}; + +union GPDMUX2_REG { + Uint32 all; + struct GPDMUX2_BITS bit; +}; + +struct GPDDIR_BITS { // bits description + Uint16 GPIO96:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO97:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO98:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO99:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO100:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO101:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO102:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO103:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO104:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO105:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO106:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO107:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO108:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO109:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO110:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO111:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO112:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO113:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO114:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO115:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO116:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO117:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO118:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO119:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO120:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO121:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO122:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO123:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO124:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO125:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO126:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO127:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPDDIR_REG { + Uint32 all; + struct GPDDIR_BITS bit; +}; + +struct GPDPUD_BITS { // bits description + Uint16 GPIO96:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO97:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO98:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO99:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO100:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO101:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO102:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO103:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO104:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO105:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO106:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO107:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO108:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO109:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO110:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO111:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO112:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO113:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO114:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO115:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO116:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO117:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO118:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO119:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO120:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO121:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO122:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO123:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO124:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO125:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO126:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO127:1; // 31 Pull-Up Disable control for this pin +}; + +union GPDPUD_REG { + Uint32 all; + struct GPDPUD_BITS bit; +}; + +struct GPDINV_BITS { // bits description + Uint16 GPIO96:1; // 0 Input inversion control for this pin + Uint16 GPIO97:1; // 1 Input inversion control for this pin + Uint16 GPIO98:1; // 2 Input inversion control for this pin + Uint16 GPIO99:1; // 3 Input inversion control for this pin + Uint16 GPIO100:1; // 4 Input inversion control for this pin + Uint16 GPIO101:1; // 5 Input inversion control for this pin + Uint16 GPIO102:1; // 6 Input inversion control for this pin + Uint16 GPIO103:1; // 7 Input inversion control for this pin + Uint16 GPIO104:1; // 8 Input inversion control for this pin + Uint16 GPIO105:1; // 9 Input inversion control for this pin + Uint16 GPIO106:1; // 10 Input inversion control for this pin + Uint16 GPIO107:1; // 11 Input inversion control for this pin + Uint16 GPIO108:1; // 12 Input inversion control for this pin + Uint16 GPIO109:1; // 13 Input inversion control for this pin + Uint16 GPIO110:1; // 14 Input inversion control for this pin + Uint16 GPIO111:1; // 15 Input inversion control for this pin + Uint16 GPIO112:1; // 16 Input inversion control for this pin + Uint16 GPIO113:1; // 17 Input inversion control for this pin + Uint16 GPIO114:1; // 18 Input inversion control for this pin + Uint16 GPIO115:1; // 19 Input inversion control for this pin + Uint16 GPIO116:1; // 20 Input inversion control for this pin + Uint16 GPIO117:1; // 21 Input inversion control for this pin + Uint16 GPIO118:1; // 22 Input inversion control for this pin + Uint16 GPIO119:1; // 23 Input inversion control for this pin + Uint16 GPIO120:1; // 24 Input inversion control for this pin + Uint16 GPIO121:1; // 25 Input inversion control for this pin + Uint16 GPIO122:1; // 26 Input inversion control for this pin + Uint16 GPIO123:1; // 27 Input inversion control for this pin + Uint16 GPIO124:1; // 28 Input inversion control for this pin + Uint16 GPIO125:1; // 29 Input inversion control for this pin + Uint16 GPIO126:1; // 30 Input inversion control for this pin + Uint16 GPIO127:1; // 31 Input inversion control for this pin +}; + +union GPDINV_REG { + Uint32 all; + struct GPDINV_BITS bit; +}; + +struct GPDODR_BITS { // bits description + Uint16 GPIO96:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO97:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO98:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO99:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO100:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO101:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO102:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO103:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO104:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO105:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO106:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO107:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO108:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO109:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO110:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO111:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO112:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO113:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO114:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO115:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO116:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO117:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO118:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO119:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO120:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO121:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO122:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO123:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO124:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO125:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO126:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO127:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPDODR_REG { + Uint32 all; + struct GPDODR_BITS bit; +}; + +struct GPDGMUX1_BITS { // bits description + Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 + Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 + Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 + Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 + Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 + Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 + Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 + Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 + Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 + Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 + Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 + Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 + Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 + Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 + Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 + Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 +}; + +union GPDGMUX1_REG { + Uint32 all; + struct GPDGMUX1_BITS bit; +}; + +struct GPDGMUX2_BITS { // bits description + Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 + Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 + Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 + Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 + Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 + Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 + Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 + Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 + Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 + Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 + Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 + Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 + Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 + Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 + Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 + Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 +}; + +union GPDGMUX2_REG { + Uint32 all; + struct GPDGMUX2_BITS bit; +}; + +struct GPDCSEL1_BITS { // bits description + Uint16 GPIO96:4; // 3:0 GPIO96 Master CPU Select + Uint16 GPIO97:4; // 7:4 GPIO97 Master CPU Select + Uint16 GPIO98:4; // 11:8 GPIO98 Master CPU Select + Uint16 GPIO99:4; // 15:12 GPIO99 Master CPU Select + Uint16 GPIO100:4; // 19:16 GPIO100 Master CPU Select + Uint16 GPIO101:4; // 23:20 GPIO101 Master CPU Select + Uint16 GPIO102:4; // 27:24 GPIO102 Master CPU Select + Uint16 GPIO103:4; // 31:28 GPIO103 Master CPU Select +}; + +union GPDCSEL1_REG { + Uint32 all; + struct GPDCSEL1_BITS bit; +}; + +struct GPDCSEL2_BITS { // bits description + Uint16 GPIO104:4; // 3:0 GPIO104 Master CPU Select + Uint16 GPIO105:4; // 7:4 GPIO105 Master CPU Select + Uint16 GPIO106:4; // 11:8 GPIO106 Master CPU Select + Uint16 GPIO107:4; // 15:12 GPIO107 Master CPU Select + Uint16 GPIO108:4; // 19:16 GPIO108 Master CPU Select + Uint16 GPIO109:4; // 23:20 GPIO109 Master CPU Select + Uint16 GPIO110:4; // 27:24 GPIO110 Master CPU Select + Uint16 GPIO111:4; // 31:28 GPIO111 Master CPU Select +}; + +union GPDCSEL2_REG { + Uint32 all; + struct GPDCSEL2_BITS bit; +}; + +struct GPDCSEL3_BITS { // bits description + Uint16 GPIO112:4; // 3:0 GPIO112 Master CPU Select + Uint16 GPIO113:4; // 7:4 GPIO113 Master CPU Select + Uint16 GPIO114:4; // 11:8 GPIO114 Master CPU Select + Uint16 GPIO115:4; // 15:12 GPIO115 Master CPU Select + Uint16 GPIO116:4; // 19:16 GPIO116 Master CPU Select + Uint16 GPIO117:4; // 23:20 GPIO117 Master CPU Select + Uint16 GPIO118:4; // 27:24 GPIO118 Master CPU Select + Uint16 GPIO119:4; // 31:28 GPIO119 Master CPU Select +}; + +union GPDCSEL3_REG { + Uint32 all; + struct GPDCSEL3_BITS bit; +}; + +struct GPDCSEL4_BITS { // bits description + Uint16 GPIO120:4; // 3:0 GPIO120 Master CPU Select + Uint16 GPIO121:4; // 7:4 GPIO121 Master CPU Select + Uint16 GPIO122:4; // 11:8 GPIO122 Master CPU Select + Uint16 GPIO123:4; // 15:12 GPIO123 Master CPU Select + Uint16 GPIO124:4; // 19:16 GPIO124 Master CPU Select + Uint16 GPIO125:4; // 23:20 GPIO125 Master CPU Select + Uint16 GPIO126:4; // 27:24 GPIO126 Master CPU Select + Uint16 GPIO127:4; // 31:28 GPIO127 Master CPU Select +}; + +union GPDCSEL4_REG { + Uint32 all; + struct GPDCSEL4_BITS bit; +}; + +struct GPDLOCK_BITS { // bits description + Uint16 GPIO96:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO97:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO98:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO99:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO100:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO101:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO102:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO103:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO104:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO105:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO106:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO107:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO108:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO109:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO110:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO111:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO112:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO113:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO114:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO115:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO116:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO117:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO118:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO119:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO120:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO121:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO122:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO123:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO124:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO125:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO126:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO127:1; // 31 Configuration Lock bit for this pin +}; + +union GPDLOCK_REG { + Uint32 all; + struct GPDLOCK_BITS bit; +}; + +struct GPDCR_BITS { // bits description + Uint16 GPIO96:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO97:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO98:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO99:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO100:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO101:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO102:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO103:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO104:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO105:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO106:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO107:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO108:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO109:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO110:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO111:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO112:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO113:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO114:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO115:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO116:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO117:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO118:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO119:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO120:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO121:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO122:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO123:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO124:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO125:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO126:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO127:1; // 31 Configuration lock commit bit for this pin +}; + +union GPDCR_REG { + Uint32 all; + struct GPDCR_BITS bit; +}; + +struct GPECTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO128 to GPIO135 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO136 to GPIO143 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO144 to GPIO151 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO152 to GPIO159 +}; + +union GPECTRL_REG { + Uint32 all; + struct GPECTRL_BITS bit; +}; + +struct GPEQSEL1_BITS { // bits description + Uint16 GPIO128:2; // 1:0 Select input qualification type for GPIO128 + Uint16 GPIO129:2; // 3:2 Select input qualification type for GPIO129 + Uint16 GPIO130:2; // 5:4 Select input qualification type for GPIO130 + Uint16 GPIO131:2; // 7:6 Select input qualification type for GPIO131 + Uint16 GPIO132:2; // 9:8 Select input qualification type for GPIO132 + Uint16 GPIO133:2; // 11:10 Select input qualification type for GPIO133 + Uint16 GPIO134:2; // 13:12 Select input qualification type for GPIO134 + Uint16 GPIO135:2; // 15:14 Select input qualification type for GPIO135 + Uint16 GPIO136:2; // 17:16 Select input qualification type for GPIO136 + Uint16 GPIO137:2; // 19:18 Select input qualification type for GPIO137 + Uint16 GPIO138:2; // 21:20 Select input qualification type for GPIO138 + Uint16 GPIO139:2; // 23:22 Select input qualification type for GPIO139 + Uint16 GPIO140:2; // 25:24 Select input qualification type for GPIO140 + Uint16 GPIO141:2; // 27:26 Select input qualification type for GPIO141 + Uint16 GPIO142:2; // 29:28 Select input qualification type for GPIO142 + Uint16 GPIO143:2; // 31:30 Select input qualification type for GPIO143 +}; + +union GPEQSEL1_REG { + Uint32 all; + struct GPEQSEL1_BITS bit; +}; + +struct GPEQSEL2_BITS { // bits description + Uint16 GPIO144:2; // 1:0 Select input qualification type for GPIO144 + Uint16 GPIO145:2; // 3:2 Select input qualification type for GPIO145 + Uint16 GPIO146:2; // 5:4 Select input qualification type for GPIO146 + Uint16 GPIO147:2; // 7:6 Select input qualification type for GPIO147 + Uint16 GPIO148:2; // 9:8 Select input qualification type for GPIO148 + Uint16 GPIO149:2; // 11:10 Select input qualification type for GPIO149 + Uint16 GPIO150:2; // 13:12 Select input qualification type for GPIO150 + Uint16 GPIO151:2; // 15:14 Select input qualification type for GPIO151 + Uint16 GPIO152:2; // 17:16 Select input qualification type for GPIO152 + Uint16 GPIO153:2; // 19:18 Select input qualification type for GPIO153 + Uint16 GPIO154:2; // 21:20 Select input qualification type for GPIO154 + Uint16 GPIO155:2; // 23:22 Select input qualification type for GPIO155 + Uint16 GPIO156:2; // 25:24 Select input qualification type for GPIO156 + Uint16 GPIO157:2; // 27:26 Select input qualification type for GPIO157 + Uint16 GPIO158:2; // 29:28 Select input qualification type for GPIO158 + Uint16 GPIO159:2; // 31:30 Select input qualification type for GPIO159 +}; + +union GPEQSEL2_REG { + Uint32 all; + struct GPEQSEL2_BITS bit; +}; + +struct GPEMUX1_BITS { // bits description + Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 + Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 + Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 + Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 + Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 + Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 + Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 + Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 + Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 + Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 + Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 + Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 + Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 + Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 + Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 + Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 +}; + +union GPEMUX1_REG { + Uint32 all; + struct GPEMUX1_BITS bit; +}; + +struct GPEMUX2_BITS { // bits description + Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 + Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 + Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 + Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 + Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 + Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 + Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 + Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 + Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 + Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 + Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 + Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 + Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 + Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 + Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 + Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 +}; + +union GPEMUX2_REG { + Uint32 all; + struct GPEMUX2_BITS bit; +}; + +struct GPEDIR_BITS { // bits description + Uint16 GPIO128:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO129:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO130:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO131:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO132:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO133:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO134:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO135:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO136:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO137:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO138:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO139:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO140:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO141:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO142:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO143:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO144:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO145:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO146:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO147:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO148:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO149:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO150:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO151:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO152:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO153:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO154:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO155:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO156:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO157:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO158:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO159:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPEDIR_REG { + Uint32 all; + struct GPEDIR_BITS bit; +}; + +struct GPEPUD_BITS { // bits description + Uint16 GPIO128:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO129:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO130:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO131:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO132:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO133:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO134:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO135:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO136:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO137:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO138:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO139:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO140:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO141:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO142:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO143:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO144:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO145:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO146:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO147:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO148:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO149:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO150:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO151:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO152:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO153:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO154:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO155:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO156:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO157:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO158:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO159:1; // 31 Pull-Up Disable control for this pin +}; + +union GPEPUD_REG { + Uint32 all; + struct GPEPUD_BITS bit; +}; + +struct GPEINV_BITS { // bits description + Uint16 GPIO128:1; // 0 Input inversion control for this pin + Uint16 GPIO129:1; // 1 Input inversion control for this pin + Uint16 GPIO130:1; // 2 Input inversion control for this pin + Uint16 GPIO131:1; // 3 Input inversion control for this pin + Uint16 GPIO132:1; // 4 Input inversion control for this pin + Uint16 GPIO133:1; // 5 Input inversion control for this pin + Uint16 GPIO134:1; // 6 Input inversion control for this pin + Uint16 GPIO135:1; // 7 Input inversion control for this pin + Uint16 GPIO136:1; // 8 Input inversion control for this pin + Uint16 GPIO137:1; // 9 Input inversion control for this pin + Uint16 GPIO138:1; // 10 Input inversion control for this pin + Uint16 GPIO139:1; // 11 Input inversion control for this pin + Uint16 GPIO140:1; // 12 Input inversion control for this pin + Uint16 GPIO141:1; // 13 Input inversion control for this pin + Uint16 GPIO142:1; // 14 Input inversion control for this pin + Uint16 GPIO143:1; // 15 Input inversion control for this pin + Uint16 GPIO144:1; // 16 Input inversion control for this pin + Uint16 GPIO145:1; // 17 Input inversion control for this pin + Uint16 GPIO146:1; // 18 Input inversion control for this pin + Uint16 GPIO147:1; // 19 Input inversion control for this pin + Uint16 GPIO148:1; // 20 Input inversion control for this pin + Uint16 GPIO149:1; // 21 Input inversion control for this pin + Uint16 GPIO150:1; // 22 Input inversion control for this pin + Uint16 GPIO151:1; // 23 Input inversion control for this pin + Uint16 GPIO152:1; // 24 Input inversion control for this pin + Uint16 GPIO153:1; // 25 Input inversion control for this pin + Uint16 GPIO154:1; // 26 Input inversion control for this pin + Uint16 GPIO155:1; // 27 Input inversion control for this pin + Uint16 GPIO156:1; // 28 Input inversion control for this pin + Uint16 GPIO157:1; // 29 Input inversion control for this pin + Uint16 GPIO158:1; // 30 Input inversion control for this pin + Uint16 GPIO159:1; // 31 Input inversion control for this pin +}; + +union GPEINV_REG { + Uint32 all; + struct GPEINV_BITS bit; +}; + +struct GPEODR_BITS { // bits description + Uint16 GPIO128:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO129:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO130:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO131:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO132:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO133:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO134:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO135:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO136:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO137:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO138:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO139:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO140:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO141:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO142:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO143:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO144:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO145:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO146:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO147:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO148:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO149:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO150:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO151:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO152:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO153:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO154:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO155:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO156:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO157:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO158:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO159:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPEODR_REG { + Uint32 all; + struct GPEODR_BITS bit; +}; + +struct GPEGMUX1_BITS { // bits description + Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 + Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 + Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 + Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 + Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 + Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 + Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 + Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 + Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 + Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 + Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 + Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 + Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 + Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 + Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 + Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 +}; + +union GPEGMUX1_REG { + Uint32 all; + struct GPEGMUX1_BITS bit; +}; + +struct GPEGMUX2_BITS { // bits description + Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 + Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 + Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 + Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 + Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 + Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 + Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 + Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 + Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 + Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 + Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 + Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 + Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 + Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 + Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 + Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 +}; + +union GPEGMUX2_REG { + Uint32 all; + struct GPEGMUX2_BITS bit; +}; + +struct GPECSEL1_BITS { // bits description + Uint16 GPIO128:4; // 3:0 GPIO128 Master CPU Select + Uint16 GPIO129:4; // 7:4 GPIO129 Master CPU Select + Uint16 GPIO130:4; // 11:8 GPIO130 Master CPU Select + Uint16 GPIO131:4; // 15:12 GPIO131 Master CPU Select + Uint16 GPIO132:4; // 19:16 GPIO132 Master CPU Select + Uint16 GPIO133:4; // 23:20 GPIO133 Master CPU Select + Uint16 GPIO134:4; // 27:24 GPIO134 Master CPU Select + Uint16 GPIO135:4; // 31:28 GPIO135 Master CPU Select +}; + +union GPECSEL1_REG { + Uint32 all; + struct GPECSEL1_BITS bit; +}; + +struct GPECSEL2_BITS { // bits description + Uint16 GPIO136:4; // 3:0 GPIO136 Master CPU Select + Uint16 GPIO137:4; // 7:4 GPIO137 Master CPU Select + Uint16 GPIO138:4; // 11:8 GPIO138 Master CPU Select + Uint16 GPIO139:4; // 15:12 GPIO139 Master CPU Select + Uint16 GPIO140:4; // 19:16 GPIO140 Master CPU Select + Uint16 GPIO141:4; // 23:20 GPIO141 Master CPU Select + Uint16 GPIO142:4; // 27:24 GPIO142 Master CPU Select + Uint16 GPIO143:4; // 31:28 GPIO143 Master CPU Select +}; + +union GPECSEL2_REG { + Uint32 all; + struct GPECSEL2_BITS bit; +}; + +struct GPECSEL3_BITS { // bits description + Uint16 GPIO144:4; // 3:0 GPIO144 Master CPU Select + Uint16 GPIO145:4; // 7:4 GPIO145 Master CPU Select + Uint16 GPIO146:4; // 11:8 GPIO146 Master CPU Select + Uint16 GPIO147:4; // 15:12 GPIO147 Master CPU Select + Uint16 GPIO148:4; // 19:16 GPIO148 Master CPU Select + Uint16 GPIO149:4; // 23:20 GPIO149 Master CPU Select + Uint16 GPIO150:4; // 27:24 GPIO150 Master CPU Select + Uint16 GPIO151:4; // 31:28 GPIO151 Master CPU Select +}; + +union GPECSEL3_REG { + Uint32 all; + struct GPECSEL3_BITS bit; +}; + +struct GPECSEL4_BITS { // bits description + Uint16 GPIO152:4; // 3:0 GPIO152 Master CPU Select + Uint16 GPIO153:4; // 7:4 GPIO153 Master CPU Select + Uint16 GPIO154:4; // 11:8 GPIO154 Master CPU Select + Uint16 GPIO155:4; // 15:12 GPIO155 Master CPU Select + Uint16 GPIO156:4; // 19:16 GPIO156 Master CPU Select + Uint16 GPIO157:4; // 23:20 GPIO157 Master CPU Select + Uint16 GPIO158:4; // 27:24 GPIO158 Master CPU Select + Uint16 GPIO159:4; // 31:28 GPIO159 Master CPU Select +}; + +union GPECSEL4_REG { + Uint32 all; + struct GPECSEL4_BITS bit; +}; + +struct GPELOCK_BITS { // bits description + Uint16 GPIO128:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO129:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO130:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO131:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO132:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO133:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO134:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO135:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO136:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO137:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO138:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO139:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO140:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO141:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO142:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO143:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO144:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO145:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO146:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO147:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO148:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO149:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO150:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO151:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO152:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO153:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO154:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO155:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO156:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO157:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO158:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO159:1; // 31 Configuration Lock bit for this pin +}; + +union GPELOCK_REG { + Uint32 all; + struct GPELOCK_BITS bit; +}; + +struct GPECR_BITS { // bits description + Uint16 GPIO128:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO129:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO130:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO131:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO132:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO133:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO134:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO135:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO136:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO137:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO138:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO139:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO140:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO141:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO142:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO143:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO144:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO145:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO146:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO147:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO148:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO149:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO150:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO151:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO152:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO153:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO154:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO155:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO156:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO157:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO158:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO159:1; // 31 Configuration lock commit bit for this pin +}; + +union GPECR_REG { + Uint32 all; + struct GPECR_BITS bit; +}; + +struct GPFCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO160 to GPIO167 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO168 + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union GPFCTRL_REG { + Uint32 all; + struct GPFCTRL_BITS bit; +}; + +struct GPFQSEL1_BITS { // bits description + Uint16 GPIO160:2; // 1:0 Select input qualification type for GPIO160 + Uint16 GPIO161:2; // 3:2 Select input qualification type for GPIO161 + Uint16 GPIO162:2; // 5:4 Select input qualification type for GPIO162 + Uint16 GPIO163:2; // 7:6 Select input qualification type for GPIO163 + Uint16 GPIO164:2; // 9:8 Select input qualification type for GPIO164 + Uint16 GPIO165:2; // 11:10 Select input qualification type for GPIO165 + Uint16 GPIO166:2; // 13:12 Select input qualification type for GPIO166 + Uint16 GPIO167:2; // 15:14 Select input qualification type for GPIO167 + Uint16 GPIO168:2; // 17:16 Select input qualification type for GPIO168 + Uint16 rsvd1:2; // 19:18 Reserved + Uint16 rsvd2:2; // 21:20 Reserved + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:2; // 27:26 Reserved + Uint16 rsvd6:2; // 29:28 Reserved + Uint16 rsvd7:2; // 31:30 Reserved +}; + +union GPFQSEL1_REG { + Uint32 all; + struct GPFQSEL1_BITS bit; +}; + +struct GPFMUX1_BITS { // bits description + Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 + Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 + Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 + Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 + Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 + Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 + Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 + Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 + Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 + Uint16 rsvd1:2; // 19:18 Reserved + Uint16 rsvd2:2; // 21:20 Reserved + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:2; // 27:26 Reserved + Uint16 rsvd6:2; // 29:28 Reserved + Uint16 rsvd7:2; // 31:30 Reserved +}; + +union GPFMUX1_REG { + Uint32 all; + struct GPFMUX1_BITS bit; +}; + +struct GPFDIR_BITS { // bits description + Uint16 GPIO160:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO161:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO162:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO163:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO164:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO165:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO166:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO167:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO168:1; // 8 Defines direction for this pin in GPIO mode + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFDIR_REG { + Uint32 all; + struct GPFDIR_BITS bit; +}; + +struct GPFPUD_BITS { // bits description + Uint16 GPIO160:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO161:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO162:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO163:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO164:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO165:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO166:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO167:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO168:1; // 8 Pull-Up Disable control for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFPUD_REG { + Uint32 all; + struct GPFPUD_BITS bit; +}; + +struct GPFINV_BITS { // bits description + Uint16 GPIO160:1; // 0 Input inversion control for this pin + Uint16 GPIO161:1; // 1 Input inversion control for this pin + Uint16 GPIO162:1; // 2 Input inversion control for this pin + Uint16 GPIO163:1; // 3 Input inversion control for this pin + Uint16 GPIO164:1; // 4 Input inversion control for this pin + Uint16 GPIO165:1; // 5 Input inversion control for this pin + Uint16 GPIO166:1; // 6 Input inversion control for this pin + Uint16 GPIO167:1; // 7 Input inversion control for this pin + Uint16 GPIO168:1; // 8 Input inversion control for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFINV_REG { + Uint32 all; + struct GPFINV_BITS bit; +}; + +struct GPFODR_BITS { // bits description + Uint16 GPIO160:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO161:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO162:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO163:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO164:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO165:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO166:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO167:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO168:1; // 8 Outpout Open-Drain control for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFODR_REG { + Uint32 all; + struct GPFODR_BITS bit; +}; + +struct GPFGMUX1_BITS { // bits description + Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 + Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 + Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 + Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 + Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 + Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 + Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 + Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 + Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 + Uint16 rsvd1:2; // 19:18 Reserved + Uint16 rsvd2:2; // 21:20 Reserved + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:2; // 27:26 Reserved + Uint16 rsvd6:2; // 29:28 Reserved + Uint16 rsvd7:2; // 31:30 Reserved +}; + +union GPFGMUX1_REG { + Uint32 all; + struct GPFGMUX1_BITS bit; +}; + +struct GPFCSEL1_BITS { // bits description + Uint16 GPIO160:4; // 3:0 GPIO160 Master CPU Select + Uint16 GPIO161:4; // 7:4 GPIO161 Master CPU Select + Uint16 GPIO162:4; // 11:8 GPIO162 Master CPU Select + Uint16 GPIO163:4; // 15:12 GPIO163 Master CPU Select + Uint16 GPIO164:4; // 19:16 GPIO164 Master CPU Select + Uint16 GPIO165:4; // 23:20 GPIO165 Master CPU Select + Uint16 GPIO166:4; // 27:24 GPIO166 Master CPU Select + Uint16 GPIO167:4; // 31:28 GPIO167 Master CPU Select +}; + +union GPFCSEL1_REG { + Uint32 all; + struct GPFCSEL1_BITS bit; +}; + +struct GPFCSEL2_BITS { // bits description + Uint16 GPIO168:4; // 3:0 GPIO168 Master CPU Select + Uint16 rsvd1:4; // 7:4 Reserved + Uint16 rsvd2:4; // 11:8 Reserved + Uint16 rsvd3:4; // 15:12 Reserved + Uint16 rsvd4:4; // 19:16 Reserved + Uint16 rsvd5:4; // 23:20 Reserved + Uint16 rsvd6:4; // 27:24 Reserved + Uint16 rsvd7:4; // 31:28 Reserved +}; + +union GPFCSEL2_REG { + Uint32 all; + struct GPFCSEL2_BITS bit; +}; + +struct GPFLOCK_BITS { // bits description + Uint16 GPIO160:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO161:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO162:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO163:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO164:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO165:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO166:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO167:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO168:1; // 8 Configuration Lock bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFLOCK_REG { + Uint32 all; + struct GPFLOCK_BITS bit; +}; + +struct GPFCR_BITS { // bits description + Uint16 GPIO160:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO161:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO162:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO163:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO164:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO165:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO166:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO167:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO168:1; // 8 Configuration lock commit bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFCR_REG { + Uint32 all; + struct GPFCR_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Qualification Sampling Period Control (GPIO0 to 31) + union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + union GPAMUX1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) + union GPAMUX2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) + union GPADIR_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + union GPAPUD_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) + Uint16 rsvd1[2]; // Reserved + union GPAINV_REG GPAINV; // GPIO A Input Polarity Invert Registers (GPIO0 to 31) + union GPAODR_REG GPAODR; // GPIO A Open Drain Output Register (GPIO0 to GPIO31) + Uint16 rsvd2[12]; // Reserved + union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to 15) + union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to 31) + Uint16 rsvd3[4]; // Reserved + union GPACSEL1_REG GPACSEL1; // GPIO A Core Select Register (GPIO0 to 7) + union GPACSEL2_REG GPACSEL2; // GPIO A Core Select Register (GPIO8 to 15) + union GPACSEL3_REG GPACSEL3; // GPIO A Core Select Register (GPIO16 to 23) + union GPACSEL4_REG GPACSEL4; // GPIO A Core Select Register (GPIO24 to 31) + Uint16 rsvd4[12]; // Reserved + union GPALOCK_REG GPALOCK; // GPIO A Lock Configuration Register (GPIO0 to 31) + union GPACR_REG GPACR; // GPIO A Lock Commit Register (GPIO0 to 31) + union GPBCTRL_REG GPBCTRL; // GPIO B Qualification Sampling Period Control (GPIO32 to 63) + union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + union GPBMUX1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPBMUX2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDIR_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + union GPBPUD_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) + Uint16 rsvd5[2]; // Reserved + union GPBINV_REG GPBINV; // GPIO B Input Polarity Invert Registers (GPIO32 to 63) + union GPBODR_REG GPBODR; // GPIO B Open Drain Output Register (GPIO32 to GPIO63) + union GPBAMSEL_REG GPBAMSEL; // GPIO B Analog Mode Select register (GPIO32 to GPIO63) + Uint16 rsvd6[10]; // Reserved + union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to 47) + union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to 63) + Uint16 rsvd7[4]; // Reserved + union GPBCSEL1_REG GPBCSEL1; // GPIO B Core Select Register (GPIO32 to 39) + union GPBCSEL2_REG GPBCSEL2; // GPIO B Core Select Register (GPIO40 to 47) + union GPBCSEL3_REG GPBCSEL3; // GPIO B Core Select Register (GPIO48 to 55) + union GPBCSEL4_REG GPBCSEL4; // GPIO B Core Select Register (GPIO56 to 63) + Uint16 rsvd8[12]; // Reserved + union GPBLOCK_REG GPBLOCK; // GPIO B Lock Configuration Register (GPIO32 to 63) + union GPBCR_REG GPBCR; // GPIO B Lock Commit Register (GPIO32 to 63) + union GPCCTRL_REG GPCCTRL; // GPIO C Qualification Sampling Period Control (GPIO64 to 95) + union GPCQSEL1_REG GPCQSEL1; // GPIO C Qualifier Select 1 Register (GPIO64 to 79) + union GPCQSEL2_REG GPCQSEL2; // GPIO C Qualifier Select 2 Register (GPIO80 to 95) + union GPCMUX1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPCMUX2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDIR_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + union GPCPUD_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95) + Uint16 rsvd9[2]; // Reserved + union GPCINV_REG GPCINV; // GPIO C Input Polarity Invert Registers (GPIO64 to 95) + union GPCODR_REG GPCODR; // GPIO C Open Drain Output Register (GPIO64 to GPIO95) + Uint16 rsvd10[12]; // Reserved + union GPCGMUX1_REG GPCGMUX1; // GPIO C Peripheral Group Mux (GPIO64 to 79) + union GPCGMUX2_REG GPCGMUX2; // GPIO C Peripheral Group Mux (GPIO80 to 95) + Uint16 rsvd11[4]; // Reserved + union GPCCSEL1_REG GPCCSEL1; // GPIO C Core Select Register (GPIO64 to 71) + union GPCCSEL2_REG GPCCSEL2; // GPIO C Core Select Register (GPIO72 to 79) + union GPCCSEL3_REG GPCCSEL3; // GPIO C Core Select Register (GPIO80 to 87) + union GPCCSEL4_REG GPCCSEL4; // GPIO C Core Select Register (GPIO88 to 95) + Uint16 rsvd12[12]; // Reserved + union GPCLOCK_REG GPCLOCK; // GPIO C Lock Configuration Register (GPIO64 to 95) + union GPCCR_REG GPCCR; // GPIO C Lock Commit Register (GPIO64 to 95) + union GPDCTRL_REG GPDCTRL; // GPIO D Qualification Sampling Period Control (GPIO96 to 127) + union GPDQSEL1_REG GPDQSEL1; // GPIO D Qualifier Select 1 Register (GPIO96 to 111) + union GPDQSEL2_REG GPDQSEL2; // GPIO D Qualifier Select 2 Register (GPIO112 to 127) + union GPDMUX1_REG GPDMUX1; // GPIO D Mux 1 Register (GPIO96 to 111) + union GPDMUX2_REG GPDMUX2; // GPIO D Mux 2 Register (GPIO112 to 127) + union GPDDIR_REG GPDDIR; // GPIO D Direction Register (GPIO96 to 127) + union GPDPUD_REG GPDPUD; // GPIO D Pull Up Disable Register (GPIO96 to 127) + Uint16 rsvd13[2]; // Reserved + union GPDINV_REG GPDINV; // GPIO D Input Polarity Invert Registers (GPIO96 to 127) + union GPDODR_REG GPDODR; // GPIO D Open Drain Output Register (GPIO96 to GPIO127) + Uint16 rsvd14[12]; // Reserved + union GPDGMUX1_REG GPDGMUX1; // GPIO D Peripheral Group Mux (GPIO96 to 111) + union GPDGMUX2_REG GPDGMUX2; // GPIO D Peripheral Group Mux (GPIO112 to 127) + Uint16 rsvd15[4]; // Reserved + union GPDCSEL1_REG GPDCSEL1; // GPIO D Core Select Register (GPIO96 to 103) + union GPDCSEL2_REG GPDCSEL2; // GPIO D Core Select Register (GPIO104 to 111) + union GPDCSEL3_REG GPDCSEL3; // GPIO D Core Select Register (GPIO112 to 119) + union GPDCSEL4_REG GPDCSEL4; // GPIO D Core Select Register (GPIO120 to 127) + Uint16 rsvd16[12]; // Reserved + union GPDLOCK_REG GPDLOCK; // GPIO D Lock Configuration Register (GPIO96 to 127) + union GPDCR_REG GPDCR; // GPIO D Lock Commit Register (GPIO96 to 127) + union GPECTRL_REG GPECTRL; // GPIO E Qualification Sampling Period Control (GPIO128 to 159) + union GPEQSEL1_REG GPEQSEL1; // GPIO E Qualifier Select 1 Register (GPIO128 to 143) + union GPEQSEL2_REG GPEQSEL2; // GPIO E Qualifier Select 2 Register (GPIO144 to 159) + union GPEMUX1_REG GPEMUX1; // GPIO E Mux 1 Register (GPIO128 to 143) + union GPEMUX2_REG GPEMUX2; // GPIO E Mux 2 Register (GPIO144 to 159) + union GPEDIR_REG GPEDIR; // GPIO E Direction Register (GPIO128 to 159) + union GPEPUD_REG GPEPUD; // GPIO E Pull Up Disable Register (GPIO128 to 159) + Uint16 rsvd17[2]; // Reserved + union GPEINV_REG GPEINV; // GPIO E Input Polarity Invert Registers (GPIO128 to 159) + union GPEODR_REG GPEODR; // GPIO E Open Drain Output Register (GPIO128 to GPIO159) + Uint16 rsvd18[12]; // Reserved + union GPEGMUX1_REG GPEGMUX1; // GPIO E Peripheral Group Mux (GPIO128 to 143) + union GPEGMUX2_REG GPEGMUX2; // GPIO E Peripheral Group Mux (GPIO144 to 159) + Uint16 rsvd19[4]; // Reserved + union GPECSEL1_REG GPECSEL1; // GPIO E Core Select Register (GPIO128 to 135) + union GPECSEL2_REG GPECSEL2; // GPIO E Core Select Register (GPIO136 to 143) + union GPECSEL3_REG GPECSEL3; // GPIO E Core Select Register (GPIO144 to 151) + union GPECSEL4_REG GPECSEL4; // GPIO E Core Select Register (GPIO152 to 159) + Uint16 rsvd20[12]; // Reserved + union GPELOCK_REG GPELOCK; // GPIO E Lock Configuration Register (GPIO128 to 159) + union GPECR_REG GPECR; // GPIO E Lock Commit Register (GPIO128 to 159) + union GPFCTRL_REG GPFCTRL; // GPIO F Qualification Sampling Period Control (GPIO160 to 168) + union GPFQSEL1_REG GPFQSEL1; // GPIO F Qualifier Select 1 Register (GPIO160 to 168) + Uint16 rsvd21[2]; // Reserved + union GPFMUX1_REG GPFMUX1; // GPIO F Mux 1 Register (GPIO160 to 168) + Uint16 rsvd22[2]; // Reserved + union GPFDIR_REG GPFDIR; // GPIO F Direction Register (GPIO160 to 168) + union GPFPUD_REG GPFPUD; // GPIO F Pull Up Disable Register (GPIO160 to 168) + Uint16 rsvd23[2]; // Reserved + union GPFINV_REG GPFINV; // GPIO F Input Polarity Invert Registers (GPIO160 to 168) + union GPFODR_REG GPFODR; // GPIO F Open Drain Output Register (GPIO160 to GPIO168) + Uint16 rsvd24[12]; // Reserved + union GPFGMUX1_REG GPFGMUX1; // GPIO F Peripheral Group Mux (GPIO160 to 168) + Uint16 rsvd25[6]; // Reserved + union GPFCSEL1_REG GPFCSEL1; // GPIO F Core Select Register (GPIO160 to 167) + union GPFCSEL2_REG GPFCSEL2; // GPIO F Core Select Register (GPIO168) + Uint16 rsvd26[16]; // Reserved + union GPFLOCK_REG GPFLOCK; // GPIO F Lock Configuration Register (GPIO160 to 168) + union GPFCR_REG GPFCR; // GPIO F Lock Commit Register (GPIO160 to 168) +}; + +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 Data Register for this pin + Uint16 GPIO1:1; // 1 Data Register for this pin + Uint16 GPIO2:1; // 2 Data Register for this pin + Uint16 GPIO3:1; // 3 Data Register for this pin + Uint16 GPIO4:1; // 4 Data Register for this pin + Uint16 GPIO5:1; // 5 Data Register for this pin + Uint16 GPIO6:1; // 6 Data Register for this pin + Uint16 GPIO7:1; // 7 Data Register for this pin + Uint16 GPIO8:1; // 8 Data Register for this pin + Uint16 GPIO9:1; // 9 Data Register for this pin + Uint16 GPIO10:1; // 10 Data Register for this pin + Uint16 GPIO11:1; // 11 Data Register for this pin + Uint16 GPIO12:1; // 12 Data Register for this pin + Uint16 GPIO13:1; // 13 Data Register for this pin + Uint16 GPIO14:1; // 14 Data Register for this pin + Uint16 GPIO15:1; // 15 Data Register for this pin + Uint16 GPIO16:1; // 16 Data Register for this pin + Uint16 GPIO17:1; // 17 Data Register for this pin + Uint16 GPIO18:1; // 18 Data Register for this pin + Uint16 GPIO19:1; // 19 Data Register for this pin + Uint16 GPIO20:1; // 20 Data Register for this pin + Uint16 GPIO21:1; // 21 Data Register for this pin + Uint16 GPIO22:1; // 22 Data Register for this pin + Uint16 GPIO23:1; // 23 Data Register for this pin + Uint16 GPIO24:1; // 24 Data Register for this pin + Uint16 GPIO25:1; // 25 Data Register for this pin + Uint16 GPIO26:1; // 26 Data Register for this pin + Uint16 GPIO27:1; // 27 Data Register for this pin + Uint16 GPIO28:1; // 28 Data Register for this pin + Uint16 GPIO29:1; // 29 Data Register for this pin + Uint16 GPIO30:1; // 30 Data Register for this pin + Uint16 GPIO31:1; // 31 Data Register for this pin +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +struct GPASET_BITS { // bits description + Uint16 GPIO0:1; // 0 Output Set bit for this pin + Uint16 GPIO1:1; // 1 Output Set bit for this pin + Uint16 GPIO2:1; // 2 Output Set bit for this pin + Uint16 GPIO3:1; // 3 Output Set bit for this pin + Uint16 GPIO4:1; // 4 Output Set bit for this pin + Uint16 GPIO5:1; // 5 Output Set bit for this pin + Uint16 GPIO6:1; // 6 Output Set bit for this pin + Uint16 GPIO7:1; // 7 Output Set bit for this pin + Uint16 GPIO8:1; // 8 Output Set bit for this pin + Uint16 GPIO9:1; // 9 Output Set bit for this pin + Uint16 GPIO10:1; // 10 Output Set bit for this pin + Uint16 GPIO11:1; // 11 Output Set bit for this pin + Uint16 GPIO12:1; // 12 Output Set bit for this pin + Uint16 GPIO13:1; // 13 Output Set bit for this pin + Uint16 GPIO14:1; // 14 Output Set bit for this pin + Uint16 GPIO15:1; // 15 Output Set bit for this pin + Uint16 GPIO16:1; // 16 Output Set bit for this pin + Uint16 GPIO17:1; // 17 Output Set bit for this pin + Uint16 GPIO18:1; // 18 Output Set bit for this pin + Uint16 GPIO19:1; // 19 Output Set bit for this pin + Uint16 GPIO20:1; // 20 Output Set bit for this pin + Uint16 GPIO21:1; // 21 Output Set bit for this pin + Uint16 GPIO22:1; // 22 Output Set bit for this pin + Uint16 GPIO23:1; // 23 Output Set bit for this pin + Uint16 GPIO24:1; // 24 Output Set bit for this pin + Uint16 GPIO25:1; // 25 Output Set bit for this pin + Uint16 GPIO26:1; // 26 Output Set bit for this pin + Uint16 GPIO27:1; // 27 Output Set bit for this pin + Uint16 GPIO28:1; // 28 Output Set bit for this pin + Uint16 GPIO29:1; // 29 Output Set bit for this pin + Uint16 GPIO30:1; // 30 Output Set bit for this pin + Uint16 GPIO31:1; // 31 Output Set bit for this pin +}; + +union GPASET_REG { + Uint32 all; + struct GPASET_BITS bit; +}; + +struct GPACLEAR_BITS { // bits description + Uint16 GPIO0:1; // 0 Output Clear bit for this pin + Uint16 GPIO1:1; // 1 Output Clear bit for this pin + Uint16 GPIO2:1; // 2 Output Clear bit for this pin + Uint16 GPIO3:1; // 3 Output Clear bit for this pin + Uint16 GPIO4:1; // 4 Output Clear bit for this pin + Uint16 GPIO5:1; // 5 Output Clear bit for this pin + Uint16 GPIO6:1; // 6 Output Clear bit for this pin + Uint16 GPIO7:1; // 7 Output Clear bit for this pin + Uint16 GPIO8:1; // 8 Output Clear bit for this pin + Uint16 GPIO9:1; // 9 Output Clear bit for this pin + Uint16 GPIO10:1; // 10 Output Clear bit for this pin + Uint16 GPIO11:1; // 11 Output Clear bit for this pin + Uint16 GPIO12:1; // 12 Output Clear bit for this pin + Uint16 GPIO13:1; // 13 Output Clear bit for this pin + Uint16 GPIO14:1; // 14 Output Clear bit for this pin + Uint16 GPIO15:1; // 15 Output Clear bit for this pin + Uint16 GPIO16:1; // 16 Output Clear bit for this pin + Uint16 GPIO17:1; // 17 Output Clear bit for this pin + Uint16 GPIO18:1; // 18 Output Clear bit for this pin + Uint16 GPIO19:1; // 19 Output Clear bit for this pin + Uint16 GPIO20:1; // 20 Output Clear bit for this pin + Uint16 GPIO21:1; // 21 Output Clear bit for this pin + Uint16 GPIO22:1; // 22 Output Clear bit for this pin + Uint16 GPIO23:1; // 23 Output Clear bit for this pin + Uint16 GPIO24:1; // 24 Output Clear bit for this pin + Uint16 GPIO25:1; // 25 Output Clear bit for this pin + Uint16 GPIO26:1; // 26 Output Clear bit for this pin + Uint16 GPIO27:1; // 27 Output Clear bit for this pin + Uint16 GPIO28:1; // 28 Output Clear bit for this pin + Uint16 GPIO29:1; // 29 Output Clear bit for this pin + Uint16 GPIO30:1; // 30 Output Clear bit for this pin + Uint16 GPIO31:1; // 31 Output Clear bit for this pin +}; + +union GPACLEAR_REG { + Uint32 all; + struct GPACLEAR_BITS bit; +}; + +struct GPATOGGLE_BITS { // bits description + Uint16 GPIO0:1; // 0 Output Toggle bit for this pin + Uint16 GPIO1:1; // 1 Output Toggle bit for this pin + Uint16 GPIO2:1; // 2 Output Toggle bit for this pin + Uint16 GPIO3:1; // 3 Output Toggle bit for this pin + Uint16 GPIO4:1; // 4 Output Toggle bit for this pin + Uint16 GPIO5:1; // 5 Output Toggle bit for this pin + Uint16 GPIO6:1; // 6 Output Toggle bit for this pin + Uint16 GPIO7:1; // 7 Output Toggle bit for this pin + Uint16 GPIO8:1; // 8 Output Toggle bit for this pin + Uint16 GPIO9:1; // 9 Output Toggle bit for this pin + Uint16 GPIO10:1; // 10 Output Toggle bit for this pin + Uint16 GPIO11:1; // 11 Output Toggle bit for this pin + Uint16 GPIO12:1; // 12 Output Toggle bit for this pin + Uint16 GPIO13:1; // 13 Output Toggle bit for this pin + Uint16 GPIO14:1; // 14 Output Toggle bit for this pin + Uint16 GPIO15:1; // 15 Output Toggle bit for this pin + Uint16 GPIO16:1; // 16 Output Toggle bit for this pin + Uint16 GPIO17:1; // 17 Output Toggle bit for this pin + Uint16 GPIO18:1; // 18 Output Toggle bit for this pin + Uint16 GPIO19:1; // 19 Output Toggle bit for this pin + Uint16 GPIO20:1; // 20 Output Toggle bit for this pin + Uint16 GPIO21:1; // 21 Output Toggle bit for this pin + Uint16 GPIO22:1; // 22 Output Toggle bit for this pin + Uint16 GPIO23:1; // 23 Output Toggle bit for this pin + Uint16 GPIO24:1; // 24 Output Toggle bit for this pin + Uint16 GPIO25:1; // 25 Output Toggle bit for this pin + Uint16 GPIO26:1; // 26 Output Toggle bit for this pin + Uint16 GPIO27:1; // 27 Output Toggle bit for this pin + Uint16 GPIO28:1; // 28 Output Toggle bit for this pin + Uint16 GPIO29:1; // 29 Output Toggle bit for this pin + Uint16 GPIO30:1; // 30 Output Toggle bit for this pin + Uint16 GPIO31:1; // 31 Output Toggle bit for this pin +}; + +union GPATOGGLE_REG { + Uint32 all; + struct GPATOGGLE_BITS bit; +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 Data Register for this pin + Uint16 GPIO33:1; // 1 Data Register for this pin + Uint16 GPIO34:1; // 2 Data Register for this pin + Uint16 GPIO35:1; // 3 Data Register for this pin + Uint16 GPIO36:1; // 4 Data Register for this pin + Uint16 GPIO37:1; // 5 Data Register for this pin + Uint16 GPIO38:1; // 6 Data Register for this pin + Uint16 GPIO39:1; // 7 Data Register for this pin + Uint16 GPIO40:1; // 8 Data Register for this pin + Uint16 GPIO41:1; // 9 Data Register for this pin + Uint16 GPIO42:1; // 10 Data Register for this pin + Uint16 GPIO43:1; // 11 Data Register for this pin + Uint16 GPIO44:1; // 12 Data Register for this pin + Uint16 GPIO45:1; // 13 Data Register for this pin + Uint16 GPIO46:1; // 14 Data Register for this pin + Uint16 GPIO47:1; // 15 Data Register for this pin + Uint16 GPIO48:1; // 16 Data Register for this pin + Uint16 GPIO49:1; // 17 Data Register for this pin + Uint16 GPIO50:1; // 18 Data Register for this pin + Uint16 GPIO51:1; // 19 Data Register for this pin + Uint16 GPIO52:1; // 20 Data Register for this pin + Uint16 GPIO53:1; // 21 Data Register for this pin + Uint16 GPIO54:1; // 22 Data Register for this pin + Uint16 GPIO55:1; // 23 Data Register for this pin + Uint16 GPIO56:1; // 24 Data Register for this pin + Uint16 GPIO57:1; // 25 Data Register for this pin + Uint16 GPIO58:1; // 26 Data Register for this pin + Uint16 GPIO59:1; // 27 Data Register for this pin + Uint16 GPIO60:1; // 28 Data Register for this pin + Uint16 GPIO61:1; // 29 Data Register for this pin + Uint16 GPIO62:1; // 30 Data Register for this pin + Uint16 GPIO63:1; // 31 Data Register for this pin +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +struct GPBSET_BITS { // bits description + Uint16 GPIO32:1; // 0 Output Set bit for this pin + Uint16 GPIO33:1; // 1 Output Set bit for this pin + Uint16 GPIO34:1; // 2 Output Set bit for this pin + Uint16 GPIO35:1; // 3 Output Set bit for this pin + Uint16 GPIO36:1; // 4 Output Set bit for this pin + Uint16 GPIO37:1; // 5 Output Set bit for this pin + Uint16 GPIO38:1; // 6 Output Set bit for this pin + Uint16 GPIO39:1; // 7 Output Set bit for this pin + Uint16 GPIO40:1; // 8 Output Set bit for this pin + Uint16 GPIO41:1; // 9 Output Set bit for this pin + Uint16 GPIO42:1; // 10 Output Set bit for this pin + Uint16 GPIO43:1; // 11 Output Set bit for this pin + Uint16 GPIO44:1; // 12 Output Set bit for this pin + Uint16 GPIO45:1; // 13 Output Set bit for this pin + Uint16 GPIO46:1; // 14 Output Set bit for this pin + Uint16 GPIO47:1; // 15 Output Set bit for this pin + Uint16 GPIO48:1; // 16 Output Set bit for this pin + Uint16 GPIO49:1; // 17 Output Set bit for this pin + Uint16 GPIO50:1; // 18 Output Set bit for this pin + Uint16 GPIO51:1; // 19 Output Set bit for this pin + Uint16 GPIO52:1; // 20 Output Set bit for this pin + Uint16 GPIO53:1; // 21 Output Set bit for this pin + Uint16 GPIO54:1; // 22 Output Set bit for this pin + Uint16 GPIO55:1; // 23 Output Set bit for this pin + Uint16 GPIO56:1; // 24 Output Set bit for this pin + Uint16 GPIO57:1; // 25 Output Set bit for this pin + Uint16 GPIO58:1; // 26 Output Set bit for this pin + Uint16 GPIO59:1; // 27 Output Set bit for this pin + Uint16 GPIO60:1; // 28 Output Set bit for this pin + Uint16 GPIO61:1; // 29 Output Set bit for this pin + Uint16 GPIO62:1; // 30 Output Set bit for this pin + Uint16 GPIO63:1; // 31 Output Set bit for this pin +}; + +union GPBSET_REG { + Uint32 all; + struct GPBSET_BITS bit; +}; + +struct GPBCLEAR_BITS { // bits description + Uint16 GPIO32:1; // 0 Output Clear bit for this pin + Uint16 GPIO33:1; // 1 Output Clear bit for this pin + Uint16 GPIO34:1; // 2 Output Clear bit for this pin + Uint16 GPIO35:1; // 3 Output Clear bit for this pin + Uint16 GPIO36:1; // 4 Output Clear bit for this pin + Uint16 GPIO37:1; // 5 Output Clear bit for this pin + Uint16 GPIO38:1; // 6 Output Clear bit for this pin + Uint16 GPIO39:1; // 7 Output Clear bit for this pin + Uint16 GPIO40:1; // 8 Output Clear bit for this pin + Uint16 GPIO41:1; // 9 Output Clear bit for this pin + Uint16 GPIO42:1; // 10 Output Clear bit for this pin + Uint16 GPIO43:1; // 11 Output Clear bit for this pin + Uint16 GPIO44:1; // 12 Output Clear bit for this pin + Uint16 GPIO45:1; // 13 Output Clear bit for this pin + Uint16 GPIO46:1; // 14 Output Clear bit for this pin + Uint16 GPIO47:1; // 15 Output Clear bit for this pin + Uint16 GPIO48:1; // 16 Output Clear bit for this pin + Uint16 GPIO49:1; // 17 Output Clear bit for this pin + Uint16 GPIO50:1; // 18 Output Clear bit for this pin + Uint16 GPIO51:1; // 19 Output Clear bit for this pin + Uint16 GPIO52:1; // 20 Output Clear bit for this pin + Uint16 GPIO53:1; // 21 Output Clear bit for this pin + Uint16 GPIO54:1; // 22 Output Clear bit for this pin + Uint16 GPIO55:1; // 23 Output Clear bit for this pin + Uint16 GPIO56:1; // 24 Output Clear bit for this pin + Uint16 GPIO57:1; // 25 Output Clear bit for this pin + Uint16 GPIO58:1; // 26 Output Clear bit for this pin + Uint16 GPIO59:1; // 27 Output Clear bit for this pin + Uint16 GPIO60:1; // 28 Output Clear bit for this pin + Uint16 GPIO61:1; // 29 Output Clear bit for this pin + Uint16 GPIO62:1; // 30 Output Clear bit for this pin + Uint16 GPIO63:1; // 31 Output Clear bit for this pin +}; + +union GPBCLEAR_REG { + Uint32 all; + struct GPBCLEAR_BITS bit; +}; + +struct GPBTOGGLE_BITS { // bits description + Uint16 GPIO32:1; // 0 Output Toggle bit for this pin + Uint16 GPIO33:1; // 1 Output Toggle bit for this pin + Uint16 GPIO34:1; // 2 Output Toggle bit for this pin + Uint16 GPIO35:1; // 3 Output Toggle bit for this pin + Uint16 GPIO36:1; // 4 Output Toggle bit for this pin + Uint16 GPIO37:1; // 5 Output Toggle bit for this pin + Uint16 GPIO38:1; // 6 Output Toggle bit for this pin + Uint16 GPIO39:1; // 7 Output Toggle bit for this pin + Uint16 GPIO40:1; // 8 Output Toggle bit for this pin + Uint16 GPIO41:1; // 9 Output Toggle bit for this pin + Uint16 GPIO42:1; // 10 Output Toggle bit for this pin + Uint16 GPIO43:1; // 11 Output Toggle bit for this pin + Uint16 GPIO44:1; // 12 Output Toggle bit for this pin + Uint16 GPIO45:1; // 13 Output Toggle bit for this pin + Uint16 GPIO46:1; // 14 Output Toggle bit for this pin + Uint16 GPIO47:1; // 15 Output Toggle bit for this pin + Uint16 GPIO48:1; // 16 Output Toggle bit for this pin + Uint16 GPIO49:1; // 17 Output Toggle bit for this pin + Uint16 GPIO50:1; // 18 Output Toggle bit for this pin + Uint16 GPIO51:1; // 19 Output Toggle bit for this pin + Uint16 GPIO52:1; // 20 Output Toggle bit for this pin + Uint16 GPIO53:1; // 21 Output Toggle bit for this pin + Uint16 GPIO54:1; // 22 Output Toggle bit for this pin + Uint16 GPIO55:1; // 23 Output Toggle bit for this pin + Uint16 GPIO56:1; // 24 Output Toggle bit for this pin + Uint16 GPIO57:1; // 25 Output Toggle bit for this pin + Uint16 GPIO58:1; // 26 Output Toggle bit for this pin + Uint16 GPIO59:1; // 27 Output Toggle bit for this pin + Uint16 GPIO60:1; // 28 Output Toggle bit for this pin + Uint16 GPIO61:1; // 29 Output Toggle bit for this pin + Uint16 GPIO62:1; // 30 Output Toggle bit for this pin + Uint16 GPIO63:1; // 31 Output Toggle bit for this pin +}; + +union GPBTOGGLE_REG { + Uint32 all; + struct GPBTOGGLE_BITS bit; +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 Data Register for this pin + Uint16 GPIO65:1; // 1 Data Register for this pin + Uint16 GPIO66:1; // 2 Data Register for this pin + Uint16 GPIO67:1; // 3 Data Register for this pin + Uint16 GPIO68:1; // 4 Data Register for this pin + Uint16 GPIO69:1; // 5 Data Register for this pin + Uint16 GPIO70:1; // 6 Data Register for this pin + Uint16 GPIO71:1; // 7 Data Register for this pin + Uint16 GPIO72:1; // 8 Data Register for this pin + Uint16 GPIO73:1; // 9 Data Register for this pin + Uint16 GPIO74:1; // 10 Data Register for this pin + Uint16 GPIO75:1; // 11 Data Register for this pin + Uint16 GPIO76:1; // 12 Data Register for this pin + Uint16 GPIO77:1; // 13 Data Register for this pin + Uint16 GPIO78:1; // 14 Data Register for this pin + Uint16 GPIO79:1; // 15 Data Register for this pin + Uint16 GPIO80:1; // 16 Data Register for this pin + Uint16 GPIO81:1; // 17 Data Register for this pin + Uint16 GPIO82:1; // 18 Data Register for this pin + Uint16 GPIO83:1; // 19 Data Register for this pin + Uint16 GPIO84:1; // 20 Data Register for this pin + Uint16 GPIO85:1; // 21 Data Register for this pin + Uint16 GPIO86:1; // 22 Data Register for this pin + Uint16 GPIO87:1; // 23 Data Register for this pin + Uint16 GPIO88:1; // 24 Data Register for this pin + Uint16 GPIO89:1; // 25 Data Register for this pin + Uint16 GPIO90:1; // 26 Data Register for this pin + Uint16 GPIO91:1; // 27 Data Register for this pin + Uint16 GPIO92:1; // 28 Data Register for this pin + Uint16 GPIO93:1; // 29 Data Register for this pin + Uint16 GPIO94:1; // 30 Data Register for this pin + Uint16 GPIO95:1; // 31 Data Register for this pin +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +struct GPCSET_BITS { // bits description + Uint16 GPIO64:1; // 0 Output Set bit for this pin + Uint16 GPIO65:1; // 1 Output Set bit for this pin + Uint16 GPIO66:1; // 2 Output Set bit for this pin + Uint16 GPIO67:1; // 3 Output Set bit for this pin + Uint16 GPIO68:1; // 4 Output Set bit for this pin + Uint16 GPIO69:1; // 5 Output Set bit for this pin + Uint16 GPIO70:1; // 6 Output Set bit for this pin + Uint16 GPIO71:1; // 7 Output Set bit for this pin + Uint16 GPIO72:1; // 8 Output Set bit for this pin + Uint16 GPIO73:1; // 9 Output Set bit for this pin + Uint16 GPIO74:1; // 10 Output Set bit for this pin + Uint16 GPIO75:1; // 11 Output Set bit for this pin + Uint16 GPIO76:1; // 12 Output Set bit for this pin + Uint16 GPIO77:1; // 13 Output Set bit for this pin + Uint16 GPIO78:1; // 14 Output Set bit for this pin + Uint16 GPIO79:1; // 15 Output Set bit for this pin + Uint16 GPIO80:1; // 16 Output Set bit for this pin + Uint16 GPIO81:1; // 17 Output Set bit for this pin + Uint16 GPIO82:1; // 18 Output Set bit for this pin + Uint16 GPIO83:1; // 19 Output Set bit for this pin + Uint16 GPIO84:1; // 20 Output Set bit for this pin + Uint16 GPIO85:1; // 21 Output Set bit for this pin + Uint16 GPIO86:1; // 22 Output Set bit for this pin + Uint16 GPIO87:1; // 23 Output Set bit for this pin + Uint16 GPIO88:1; // 24 Output Set bit for this pin + Uint16 GPIO89:1; // 25 Output Set bit for this pin + Uint16 GPIO90:1; // 26 Output Set bit for this pin + Uint16 GPIO91:1; // 27 Output Set bit for this pin + Uint16 GPIO92:1; // 28 Output Set bit for this pin + Uint16 GPIO93:1; // 29 Output Set bit for this pin + Uint16 GPIO94:1; // 30 Output Set bit for this pin + Uint16 GPIO95:1; // 31 Output Set bit for this pin +}; + +union GPCSET_REG { + Uint32 all; + struct GPCSET_BITS bit; +}; + +struct GPCCLEAR_BITS { // bits description + Uint16 GPIO64:1; // 0 Output Clear bit for this pin + Uint16 GPIO65:1; // 1 Output Clear bit for this pin + Uint16 GPIO66:1; // 2 Output Clear bit for this pin + Uint16 GPIO67:1; // 3 Output Clear bit for this pin + Uint16 GPIO68:1; // 4 Output Clear bit for this pin + Uint16 GPIO69:1; // 5 Output Clear bit for this pin + Uint16 GPIO70:1; // 6 Output Clear bit for this pin + Uint16 GPIO71:1; // 7 Output Clear bit for this pin + Uint16 GPIO72:1; // 8 Output Clear bit for this pin + Uint16 GPIO73:1; // 9 Output Clear bit for this pin + Uint16 GPIO74:1; // 10 Output Clear bit for this pin + Uint16 GPIO75:1; // 11 Output Clear bit for this pin + Uint16 GPIO76:1; // 12 Output Clear bit for this pin + Uint16 GPIO77:1; // 13 Output Clear bit for this pin + Uint16 GPIO78:1; // 14 Output Clear bit for this pin + Uint16 GPIO79:1; // 15 Output Clear bit for this pin + Uint16 GPIO80:1; // 16 Output Clear bit for this pin + Uint16 GPIO81:1; // 17 Output Clear bit for this pin + Uint16 GPIO82:1; // 18 Output Clear bit for this pin + Uint16 GPIO83:1; // 19 Output Clear bit for this pin + Uint16 GPIO84:1; // 20 Output Clear bit for this pin + Uint16 GPIO85:1; // 21 Output Clear bit for this pin + Uint16 GPIO86:1; // 22 Output Clear bit for this pin + Uint16 GPIO87:1; // 23 Output Clear bit for this pin + Uint16 GPIO88:1; // 24 Output Clear bit for this pin + Uint16 GPIO89:1; // 25 Output Clear bit for this pin + Uint16 GPIO90:1; // 26 Output Clear bit for this pin + Uint16 GPIO91:1; // 27 Output Clear bit for this pin + Uint16 GPIO92:1; // 28 Output Clear bit for this pin + Uint16 GPIO93:1; // 29 Output Clear bit for this pin + Uint16 GPIO94:1; // 30 Output Clear bit for this pin + Uint16 GPIO95:1; // 31 Output Clear bit for this pin +}; + +union GPCCLEAR_REG { + Uint32 all; + struct GPCCLEAR_BITS bit; +}; + +struct GPCTOGGLE_BITS { // bits description + Uint16 GPIO64:1; // 0 Output Toggle bit for this pin + Uint16 GPIO65:1; // 1 Output Toggle bit for this pin + Uint16 GPIO66:1; // 2 Output Toggle bit for this pin + Uint16 GPIO67:1; // 3 Output Toggle bit for this pin + Uint16 GPIO68:1; // 4 Output Toggle bit for this pin + Uint16 GPIO69:1; // 5 Output Toggle bit for this pin + Uint16 GPIO70:1; // 6 Output Toggle bit for this pin + Uint16 GPIO71:1; // 7 Output Toggle bit for this pin + Uint16 GPIO72:1; // 8 Output Toggle bit for this pin + Uint16 GPIO73:1; // 9 Output Toggle bit for this pin + Uint16 GPIO74:1; // 10 Output Toggle bit for this pin + Uint16 GPIO75:1; // 11 Output Toggle bit for this pin + Uint16 GPIO76:1; // 12 Output Toggle bit for this pin + Uint16 GPIO77:1; // 13 Output Toggle bit for this pin + Uint16 GPIO78:1; // 14 Output Toggle bit for this pin + Uint16 GPIO79:1; // 15 Output Toggle bit for this pin + Uint16 GPIO80:1; // 16 Output Toggle bit for this pin + Uint16 GPIO81:1; // 17 Output Toggle bit for this pin + Uint16 GPIO82:1; // 18 Output Toggle bit for this pin + Uint16 GPIO83:1; // 19 Output Toggle bit for this pin + Uint16 GPIO84:1; // 20 Output Toggle bit for this pin + Uint16 GPIO85:1; // 21 Output Toggle bit for this pin + Uint16 GPIO86:1; // 22 Output Toggle bit for this pin + Uint16 GPIO87:1; // 23 Output Toggle bit for this pin + Uint16 GPIO88:1; // 24 Output Toggle bit for this pin + Uint16 GPIO89:1; // 25 Output Toggle bit for this pin + Uint16 GPIO90:1; // 26 Output Toggle bit for this pin + Uint16 GPIO91:1; // 27 Output Toggle bit for this pin + Uint16 GPIO92:1; // 28 Output Toggle bit for this pin + Uint16 GPIO93:1; // 29 Output Toggle bit for this pin + Uint16 GPIO94:1; // 30 Output Toggle bit for this pin + Uint16 GPIO95:1; // 31 Output Toggle bit for this pin +}; + +union GPCTOGGLE_REG { + Uint32 all; + struct GPCTOGGLE_BITS bit; +}; + +struct GPDDAT_BITS { // bits description + Uint16 GPIO96:1; // 0 Data Register for this pin + Uint16 GPIO97:1; // 1 Data Register for this pin + Uint16 GPIO98:1; // 2 Data Register for this pin + Uint16 GPIO99:1; // 3 Data Register for this pin + Uint16 GPIO100:1; // 4 Data Register for this pin + Uint16 GPIO101:1; // 5 Data Register for this pin + Uint16 GPIO102:1; // 6 Data Register for this pin + Uint16 GPIO103:1; // 7 Data Register for this pin + Uint16 GPIO104:1; // 8 Data Register for this pin + Uint16 GPIO105:1; // 9 Data Register for this pin + Uint16 GPIO106:1; // 10 Data Register for this pin + Uint16 GPIO107:1; // 11 Data Register for this pin + Uint16 GPIO108:1; // 12 Data Register for this pin + Uint16 GPIO109:1; // 13 Data Register for this pin + Uint16 GPIO110:1; // 14 Data Register for this pin + Uint16 GPIO111:1; // 15 Data Register for this pin + Uint16 GPIO112:1; // 16 Data Register for this pin + Uint16 GPIO113:1; // 17 Data Register for this pin + Uint16 GPIO114:1; // 18 Data Register for this pin + Uint16 GPIO115:1; // 19 Data Register for this pin + Uint16 GPIO116:1; // 20 Data Register for this pin + Uint16 GPIO117:1; // 21 Data Register for this pin + Uint16 GPIO118:1; // 22 Data Register for this pin + Uint16 GPIO119:1; // 23 Data Register for this pin + Uint16 GPIO120:1; // 24 Data Register for this pin + Uint16 GPIO121:1; // 25 Data Register for this pin + Uint16 GPIO122:1; // 26 Data Register for this pin + Uint16 GPIO123:1; // 27 Data Register for this pin + Uint16 GPIO124:1; // 28 Data Register for this pin + Uint16 GPIO125:1; // 29 Data Register for this pin + Uint16 GPIO126:1; // 30 Data Register for this pin + Uint16 GPIO127:1; // 31 Data Register for this pin +}; + +union GPDDAT_REG { + Uint32 all; + struct GPDDAT_BITS bit; +}; + +struct GPDSET_BITS { // bits description + Uint16 GPIO96:1; // 0 Output Set bit for this pin + Uint16 GPIO97:1; // 1 Output Set bit for this pin + Uint16 GPIO98:1; // 2 Output Set bit for this pin + Uint16 GPIO99:1; // 3 Output Set bit for this pin + Uint16 GPIO100:1; // 4 Output Set bit for this pin + Uint16 GPIO101:1; // 5 Output Set bit for this pin + Uint16 GPIO102:1; // 6 Output Set bit for this pin + Uint16 GPIO103:1; // 7 Output Set bit for this pin + Uint16 GPIO104:1; // 8 Output Set bit for this pin + Uint16 GPIO105:1; // 9 Output Set bit for this pin + Uint16 GPIO106:1; // 10 Output Set bit for this pin + Uint16 GPIO107:1; // 11 Output Set bit for this pin + Uint16 GPIO108:1; // 12 Output Set bit for this pin + Uint16 GPIO109:1; // 13 Output Set bit for this pin + Uint16 GPIO110:1; // 14 Output Set bit for this pin + Uint16 GPIO111:1; // 15 Output Set bit for this pin + Uint16 GPIO112:1; // 16 Output Set bit for this pin + Uint16 GPIO113:1; // 17 Output Set bit for this pin + Uint16 GPIO114:1; // 18 Output Set bit for this pin + Uint16 GPIO115:1; // 19 Output Set bit for this pin + Uint16 GPIO116:1; // 20 Output Set bit for this pin + Uint16 GPIO117:1; // 21 Output Set bit for this pin + Uint16 GPIO118:1; // 22 Output Set bit for this pin + Uint16 GPIO119:1; // 23 Output Set bit for this pin + Uint16 GPIO120:1; // 24 Output Set bit for this pin + Uint16 GPIO121:1; // 25 Output Set bit for this pin + Uint16 GPIO122:1; // 26 Output Set bit for this pin + Uint16 GPIO123:1; // 27 Output Set bit for this pin + Uint16 GPIO124:1; // 28 Output Set bit for this pin + Uint16 GPIO125:1; // 29 Output Set bit for this pin + Uint16 GPIO126:1; // 30 Output Set bit for this pin + Uint16 GPIO127:1; // 31 Output Set bit for this pin +}; + +union GPDSET_REG { + Uint32 all; + struct GPDSET_BITS bit; +}; + +struct GPDCLEAR_BITS { // bits description + Uint16 GPIO96:1; // 0 Output Clear bit for this pin + Uint16 GPIO97:1; // 1 Output Clear bit for this pin + Uint16 GPIO98:1; // 2 Output Clear bit for this pin + Uint16 GPIO99:1; // 3 Output Clear bit for this pin + Uint16 GPIO100:1; // 4 Output Clear bit for this pin + Uint16 GPIO101:1; // 5 Output Clear bit for this pin + Uint16 GPIO102:1; // 6 Output Clear bit for this pin + Uint16 GPIO103:1; // 7 Output Clear bit for this pin + Uint16 GPIO104:1; // 8 Output Clear bit for this pin + Uint16 GPIO105:1; // 9 Output Clear bit for this pin + Uint16 GPIO106:1; // 10 Output Clear bit for this pin + Uint16 GPIO107:1; // 11 Output Clear bit for this pin + Uint16 GPIO108:1; // 12 Output Clear bit for this pin + Uint16 GPIO109:1; // 13 Output Clear bit for this pin + Uint16 GPIO110:1; // 14 Output Clear bit for this pin + Uint16 GPIO111:1; // 15 Output Clear bit for this pin + Uint16 GPIO112:1; // 16 Output Clear bit for this pin + Uint16 GPIO113:1; // 17 Output Clear bit for this pin + Uint16 GPIO114:1; // 18 Output Clear bit for this pin + Uint16 GPIO115:1; // 19 Output Clear bit for this pin + Uint16 GPIO116:1; // 20 Output Clear bit for this pin + Uint16 GPIO117:1; // 21 Output Clear bit for this pin + Uint16 GPIO118:1; // 22 Output Clear bit for this pin + Uint16 GPIO119:1; // 23 Output Clear bit for this pin + Uint16 GPIO120:1; // 24 Output Clear bit for this pin + Uint16 GPIO121:1; // 25 Output Clear bit for this pin + Uint16 GPIO122:1; // 26 Output Clear bit for this pin + Uint16 GPIO123:1; // 27 Output Clear bit for this pin + Uint16 GPIO124:1; // 28 Output Clear bit for this pin + Uint16 GPIO125:1; // 29 Output Clear bit for this pin + Uint16 GPIO126:1; // 30 Output Clear bit for this pin + Uint16 GPIO127:1; // 31 Output Clear bit for this pin +}; + +union GPDCLEAR_REG { + Uint32 all; + struct GPDCLEAR_BITS bit; +}; + +struct GPDTOGGLE_BITS { // bits description + Uint16 GPIO96:1; // 0 Output Toggle bit for this pin + Uint16 GPIO97:1; // 1 Output Toggle bit for this pin + Uint16 GPIO98:1; // 2 Output Toggle bit for this pin + Uint16 GPIO99:1; // 3 Output Toggle bit for this pin + Uint16 GPIO100:1; // 4 Output Toggle bit for this pin + Uint16 GPIO101:1; // 5 Output Toggle bit for this pin + Uint16 GPIO102:1; // 6 Output Toggle bit for this pin + Uint16 GPIO103:1; // 7 Output Toggle bit for this pin + Uint16 GPIO104:1; // 8 Output Toggle bit for this pin + Uint16 GPIO105:1; // 9 Output Toggle bit for this pin + Uint16 GPIO106:1; // 10 Output Toggle bit for this pin + Uint16 GPIO107:1; // 11 Output Toggle bit for this pin + Uint16 GPIO108:1; // 12 Output Toggle bit for this pin + Uint16 GPIO109:1; // 13 Output Toggle bit for this pin + Uint16 GPIO110:1; // 14 Output Toggle bit for this pin + Uint16 GPIO111:1; // 15 Output Toggle bit for this pin + Uint16 GPIO112:1; // 16 Output Toggle bit for this pin + Uint16 GPIO113:1; // 17 Output Toggle bit for this pin + Uint16 GPIO114:1; // 18 Output Toggle bit for this pin + Uint16 GPIO115:1; // 19 Output Toggle bit for this pin + Uint16 GPIO116:1; // 20 Output Toggle bit for this pin + Uint16 GPIO117:1; // 21 Output Toggle bit for this pin + Uint16 GPIO118:1; // 22 Output Toggle bit for this pin + Uint16 GPIO119:1; // 23 Output Toggle bit for this pin + Uint16 GPIO120:1; // 24 Output Toggle bit for this pin + Uint16 GPIO121:1; // 25 Output Toggle bit for this pin + Uint16 GPIO122:1; // 26 Output Toggle bit for this pin + Uint16 GPIO123:1; // 27 Output Toggle bit for this pin + Uint16 GPIO124:1; // 28 Output Toggle bit for this pin + Uint16 GPIO125:1; // 29 Output Toggle bit for this pin + Uint16 GPIO126:1; // 30 Output Toggle bit for this pin + Uint16 GPIO127:1; // 31 Output Toggle bit for this pin +}; + +union GPDTOGGLE_REG { + Uint32 all; + struct GPDTOGGLE_BITS bit; +}; + +struct GPEDAT_BITS { // bits description + Uint16 GPIO128:1; // 0 Data Register for this pin + Uint16 GPIO129:1; // 1 Data Register for this pin + Uint16 GPIO130:1; // 2 Data Register for this pin + Uint16 GPIO131:1; // 3 Data Register for this pin + Uint16 GPIO132:1; // 4 Data Register for this pin + Uint16 GPIO133:1; // 5 Data Register for this pin + Uint16 GPIO134:1; // 6 Data Register for this pin + Uint16 GPIO135:1; // 7 Data Register for this pin + Uint16 GPIO136:1; // 8 Data Register for this pin + Uint16 GPIO137:1; // 9 Data Register for this pin + Uint16 GPIO138:1; // 10 Data Register for this pin + Uint16 GPIO139:1; // 11 Data Register for this pin + Uint16 GPIO140:1; // 12 Data Register for this pin + Uint16 GPIO141:1; // 13 Data Register for this pin + Uint16 GPIO142:1; // 14 Data Register for this pin + Uint16 GPIO143:1; // 15 Data Register for this pin + Uint16 GPIO144:1; // 16 Data Register for this pin + Uint16 GPIO145:1; // 17 Data Register for this pin + Uint16 GPIO146:1; // 18 Data Register for this pin + Uint16 GPIO147:1; // 19 Data Register for this pin + Uint16 GPIO148:1; // 20 Data Register for this pin + Uint16 GPIO149:1; // 21 Data Register for this pin + Uint16 GPIO150:1; // 22 Data Register for this pin + Uint16 GPIO151:1; // 23 Data Register for this pin + Uint16 GPIO152:1; // 24 Data Register for this pin + Uint16 GPIO153:1; // 25 Data Register for this pin + Uint16 GPIO154:1; // 26 Data Register for this pin + Uint16 GPIO155:1; // 27 Data Register for this pin + Uint16 GPIO156:1; // 28 Data Register for this pin + Uint16 GPIO157:1; // 29 Data Register for this pin + Uint16 GPIO158:1; // 30 Data Register for this pin + Uint16 GPIO159:1; // 31 Data Register for this pin +}; + +union GPEDAT_REG { + Uint32 all; + struct GPEDAT_BITS bit; +}; + +struct GPESET_BITS { // bits description + Uint16 GPIO128:1; // 0 Output Set bit for this pin + Uint16 GPIO129:1; // 1 Output Set bit for this pin + Uint16 GPIO130:1; // 2 Output Set bit for this pin + Uint16 GPIO131:1; // 3 Output Set bit for this pin + Uint16 GPIO132:1; // 4 Output Set bit for this pin + Uint16 GPIO133:1; // 5 Output Set bit for this pin + Uint16 GPIO134:1; // 6 Output Set bit for this pin + Uint16 GPIO135:1; // 7 Output Set bit for this pin + Uint16 GPIO136:1; // 8 Output Set bit for this pin + Uint16 GPIO137:1; // 9 Output Set bit for this pin + Uint16 GPIO138:1; // 10 Output Set bit for this pin + Uint16 GPIO139:1; // 11 Output Set bit for this pin + Uint16 GPIO140:1; // 12 Output Set bit for this pin + Uint16 GPIO141:1; // 13 Output Set bit for this pin + Uint16 GPIO142:1; // 14 Output Set bit for this pin + Uint16 GPIO143:1; // 15 Output Set bit for this pin + Uint16 GPIO144:1; // 16 Output Set bit for this pin + Uint16 GPIO145:1; // 17 Output Set bit for this pin + Uint16 GPIO146:1; // 18 Output Set bit for this pin + Uint16 GPIO147:1; // 19 Output Set bit for this pin + Uint16 GPIO148:1; // 20 Output Set bit for this pin + Uint16 GPIO149:1; // 21 Output Set bit for this pin + Uint16 GPIO150:1; // 22 Output Set bit for this pin + Uint16 GPIO151:1; // 23 Output Set bit for this pin + Uint16 GPIO152:1; // 24 Output Set bit for this pin + Uint16 GPIO153:1; // 25 Output Set bit for this pin + Uint16 GPIO154:1; // 26 Output Set bit for this pin + Uint16 GPIO155:1; // 27 Output Set bit for this pin + Uint16 GPIO156:1; // 28 Output Set bit for this pin + Uint16 GPIO157:1; // 29 Output Set bit for this pin + Uint16 GPIO158:1; // 30 Output Set bit for this pin + Uint16 GPIO159:1; // 31 Output Set bit for this pin +}; + +union GPESET_REG { + Uint32 all; + struct GPESET_BITS bit; +}; + +struct GPECLEAR_BITS { // bits description + Uint16 GPIO128:1; // 0 Output Clear bit for this pin + Uint16 GPIO129:1; // 1 Output Clear bit for this pin + Uint16 GPIO130:1; // 2 Output Clear bit for this pin + Uint16 GPIO131:1; // 3 Output Clear bit for this pin + Uint16 GPIO132:1; // 4 Output Clear bit for this pin + Uint16 GPIO133:1; // 5 Output Clear bit for this pin + Uint16 GPIO134:1; // 6 Output Clear bit for this pin + Uint16 GPIO135:1; // 7 Output Clear bit for this pin + Uint16 GPIO136:1; // 8 Output Clear bit for this pin + Uint16 GPIO137:1; // 9 Output Clear bit for this pin + Uint16 GPIO138:1; // 10 Output Clear bit for this pin + Uint16 GPIO139:1; // 11 Output Clear bit for this pin + Uint16 GPIO140:1; // 12 Output Clear bit for this pin + Uint16 GPIO141:1; // 13 Output Clear bit for this pin + Uint16 GPIO142:1; // 14 Output Clear bit for this pin + Uint16 GPIO143:1; // 15 Output Clear bit for this pin + Uint16 GPIO144:1; // 16 Output Clear bit for this pin + Uint16 GPIO145:1; // 17 Output Clear bit for this pin + Uint16 GPIO146:1; // 18 Output Clear bit for this pin + Uint16 GPIO147:1; // 19 Output Clear bit for this pin + Uint16 GPIO148:1; // 20 Output Clear bit for this pin + Uint16 GPIO149:1; // 21 Output Clear bit for this pin + Uint16 GPIO150:1; // 22 Output Clear bit for this pin + Uint16 GPIO151:1; // 23 Output Clear bit for this pin + Uint16 GPIO152:1; // 24 Output Clear bit for this pin + Uint16 GPIO153:1; // 25 Output Clear bit for this pin + Uint16 GPIO154:1; // 26 Output Clear bit for this pin + Uint16 GPIO155:1; // 27 Output Clear bit for this pin + Uint16 GPIO156:1; // 28 Output Clear bit for this pin + Uint16 GPIO157:1; // 29 Output Clear bit for this pin + Uint16 GPIO158:1; // 30 Output Clear bit for this pin + Uint16 GPIO159:1; // 31 Output Clear bit for this pin +}; + +union GPECLEAR_REG { + Uint32 all; + struct GPECLEAR_BITS bit; +}; + +struct GPETOGGLE_BITS { // bits description + Uint16 GPIO128:1; // 0 Output Toggle bit for this pin + Uint16 GPIO129:1; // 1 Output Toggle bit for this pin + Uint16 GPIO130:1; // 2 Output Toggle bit for this pin + Uint16 GPIO131:1; // 3 Output Toggle bit for this pin + Uint16 GPIO132:1; // 4 Output Toggle bit for this pin + Uint16 GPIO133:1; // 5 Output Toggle bit for this pin + Uint16 GPIO134:1; // 6 Output Toggle bit for this pin + Uint16 GPIO135:1; // 7 Output Toggle bit for this pin + Uint16 GPIO136:1; // 8 Output Toggle bit for this pin + Uint16 GPIO137:1; // 9 Output Toggle bit for this pin + Uint16 GPIO138:1; // 10 Output Toggle bit for this pin + Uint16 GPIO139:1; // 11 Output Toggle bit for this pin + Uint16 GPIO140:1; // 12 Output Toggle bit for this pin + Uint16 GPIO141:1; // 13 Output Toggle bit for this pin + Uint16 GPIO142:1; // 14 Output Toggle bit for this pin + Uint16 GPIO143:1; // 15 Output Toggle bit for this pin + Uint16 GPIO144:1; // 16 Output Toggle bit for this pin + Uint16 GPIO145:1; // 17 Output Toggle bit for this pin + Uint16 GPIO146:1; // 18 Output Toggle bit for this pin + Uint16 GPIO147:1; // 19 Output Toggle bit for this pin + Uint16 GPIO148:1; // 20 Output Toggle bit for this pin + Uint16 GPIO149:1; // 21 Output Toggle bit for this pin + Uint16 GPIO150:1; // 22 Output Toggle bit for this pin + Uint16 GPIO151:1; // 23 Output Toggle bit for this pin + Uint16 GPIO152:1; // 24 Output Toggle bit for this pin + Uint16 GPIO153:1; // 25 Output Toggle bit for this pin + Uint16 GPIO154:1; // 26 Output Toggle bit for this pin + Uint16 GPIO155:1; // 27 Output Toggle bit for this pin + Uint16 GPIO156:1; // 28 Output Toggle bit for this pin + Uint16 GPIO157:1; // 29 Output Toggle bit for this pin + Uint16 GPIO158:1; // 30 Output Toggle bit for this pin + Uint16 GPIO159:1; // 31 Output Toggle bit for this pin +}; + +union GPETOGGLE_REG { + Uint32 all; + struct GPETOGGLE_BITS bit; +}; + +struct GPFDAT_BITS { // bits description + Uint16 GPIO160:1; // 0 Data Register for this pin + Uint16 GPIO161:1; // 1 Data Register for this pin + Uint16 GPIO162:1; // 2 Data Register for this pin + Uint16 GPIO163:1; // 3 Data Register for this pin + Uint16 GPIO164:1; // 4 Data Register for this pin + Uint16 GPIO165:1; // 5 Data Register for this pin + Uint16 GPIO166:1; // 6 Data Register for this pin + Uint16 GPIO167:1; // 7 Data Register for this pin + Uint16 GPIO168:1; // 8 Data Register for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFDAT_REG { + Uint32 all; + struct GPFDAT_BITS bit; +}; + +struct GPFSET_BITS { // bits description + Uint16 GPIO160:1; // 0 Output Set bit for this pin + Uint16 GPIO161:1; // 1 Output Set bit for this pin + Uint16 GPIO162:1; // 2 Output Set bit for this pin + Uint16 GPIO163:1; // 3 Output Set bit for this pin + Uint16 GPIO164:1; // 4 Output Set bit for this pin + Uint16 GPIO165:1; // 5 Output Set bit for this pin + Uint16 GPIO166:1; // 6 Output Set bit for this pin + Uint16 GPIO167:1; // 7 Output Set bit for this pin + Uint16 GPIO168:1; // 8 Output Set bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFSET_REG { + Uint32 all; + struct GPFSET_BITS bit; +}; + +struct GPFCLEAR_BITS { // bits description + Uint16 GPIO160:1; // 0 Output Clear bit for this pin + Uint16 GPIO161:1; // 1 Output Clear bit for this pin + Uint16 GPIO162:1; // 2 Output Clear bit for this pin + Uint16 GPIO163:1; // 3 Output Clear bit for this pin + Uint16 GPIO164:1; // 4 Output Clear bit for this pin + Uint16 GPIO165:1; // 5 Output Clear bit for this pin + Uint16 GPIO166:1; // 6 Output Clear bit for this pin + Uint16 GPIO167:1; // 7 Output Clear bit for this pin + Uint16 GPIO168:1; // 8 Output Clear bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFCLEAR_REG { + Uint32 all; + struct GPFCLEAR_BITS bit; +}; + +struct GPFTOGGLE_BITS { // bits description + Uint16 GPIO160:1; // 0 Output Toggle bit for this pin + Uint16 GPIO161:1; // 1 Output Toggle bit for this pin + Uint16 GPIO162:1; // 2 Output Toggle bit for this pin + Uint16 GPIO163:1; // 3 Output Toggle bit for this pin + Uint16 GPIO164:1; // 4 Output Toggle bit for this pin + Uint16 GPIO165:1; // 5 Output Toggle bit for this pin + Uint16 GPIO166:1; // 6 Output Toggle bit for this pin + Uint16 GPIO167:1; // 7 Output Toggle bit for this pin + Uint16 GPIO168:1; // 8 Output Toggle bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFTOGGLE_REG { + Uint32 all; + struct GPFTOGGLE_BITS bit; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO A Data Register (GPIO0 to 31) + union GPASET_REG GPASET; // GPIO A Data Set Register (GPIO0 to 31) + union GPACLEAR_REG GPACLEAR; // GPIO A Data Clear Register (GPIO0 to 31) + union GPATOGGLE_REG GPATOGGLE; // GPIO A Data Toggle Register (GPIO0 to 31) + union GPBDAT_REG GPBDAT; // GPIO B Data Register (GPIO32 to 63) + union GPBSET_REG GPBSET; // GPIO B Data Set Register (GPIO32 to 63) + union GPBCLEAR_REG GPBCLEAR; // GPIO B Data Clear Register (GPIO32 to 63) + union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Data Toggle Register (GPIO32 to 63) + union GPCDAT_REG GPCDAT; // GPIO C Data Register (GPIO64 to 95) + union GPCSET_REG GPCSET; // GPIO C Data Set Register (GPIO64 to 95) + union GPCCLEAR_REG GPCCLEAR; // GPIO C Data Clear Register (GPIO64 to 95) + union GPCTOGGLE_REG GPCTOGGLE; // GPIO C Data Toggle Register (GPIO64 to 95) + union GPDDAT_REG GPDDAT; // GPIO D Data Register (GPIO96 to 127) + union GPDSET_REG GPDSET; // GPIO D Data Set Register (GPIO96 to 127) + union GPDCLEAR_REG GPDCLEAR; // GPIO D Data Clear Register (GPIO96 to 127) + union GPDTOGGLE_REG GPDTOGGLE; // GPIO D Data Toggle Register (GPIO96 to 127) + union GPEDAT_REG GPEDAT; // GPIO E Data Register (GPIO128 to 159) + union GPESET_REG GPESET; // GPIO E Data Set Register (GPIO128 to 159) + union GPECLEAR_REG GPECLEAR; // GPIO E Data Clear Register (GPIO128 to 159) + union GPETOGGLE_REG GPETOGGLE; // GPIO E Data Toggle Register (GPIO128 to 159) + union GPFDAT_REG GPFDAT; // GPIO F Data Register (GPIO160 to 168) + union GPFSET_REG GPFSET; // GPIO F Data Set Register (GPIO160 to 168) + union GPFCLEAR_REG GPFCLEAR; // GPIO F Data Clear Register (GPIO160 to 168) + union GPFTOGGLE_REG GPFTOGGLE; // GPIO F Data Toggle Register (GPIO160 to 168) +}; + +//--------------------------------------------------------------------------- +// GPIO External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +#endif +#ifdef CPU2 +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_i2c.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_i2c.h new file mode 100644 index 00000000000..470f5a398d9 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_i2c.h @@ -0,0 +1,256 @@ +//########################################################################### +// +// FILE: F2837xD_i2c.h +// +// TITLE: I2C Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_I2C_H__ +#define __F2837xD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// I2C Individual Register Bit Definitions: + +struct I2COAR_BITS { // bits description + Uint16 OAR:10; // 9:0 I2C Own address + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union I2COAR_REG { + Uint16 all; + struct I2COAR_BITS bit; +}; + +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable + Uint16 NACK:1; // 1 No-acknowledgment interrupt enable + Uint16 ARDY:1; // 2 Register-access-ready interrupt enable + Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable + Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable + Uint16 SCD:1; // 5 Stop condition detected interrupt enable + Uint16 AAS:1; // 6 Addressed as slave interrupt enable + Uint16 rsvd1:9; // 15:7 Reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit + Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. + Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit + Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. + Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. + Uint16 SCD:1; // 5 Stop condition detected bit. + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 AD0:1; // 8 Address 0 bits + Uint16 AAS:1; // 9 Addressed-as-slave bit + Uint16 XSMT:1; // 10 Transmit shift register empty bit. + Uint16 RSFULL:1; // 11 Receive shift register full bit. + Uint16 BB:1; // 12 Bus busy bit. + Uint16 NACKSNT:1; // 13 NACK sent bit. + Uint16 SDIR:1; // 14 Slave direction bit + Uint16 rsvd2:1; // 15 Reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +struct I2CDRR_BITS { // bits description + Uint16 DATA:8; // 7:0 Receive data + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union I2CDRR_REG { + Uint16 all; + struct I2CDRR_BITS bit; +}; + +struct I2CSAR_BITS { // bits description + Uint16 SAR:10; // 9:0 Slave Address + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union I2CSAR_REG { + Uint16 all; + struct I2CSAR_BITS bit; +}; + +struct I2CDXR_BITS { // bits description + Uint16 DATA:8; // 7:0 Transmit data + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union I2CDXR_REG { + Uint16 all; + struct I2CDXR_BITS bit; +}; + +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count bits. + Uint16 FDF:1; // 3 Free Data Format + Uint16 STB:1; // 4 START Byte Mode + Uint16 IRS:1; // 5 I2C Module Reset + Uint16 DLB:1; // 6 Digital Loopback Mode + Uint16 RM:1; // 7 Repeat Mode + Uint16 XA:1; // 8 Expanded Address Mode + Uint16 TRX:1; // 9 Transmitter Mode + Uint16 MST:1; // 10 Master Mode + Uint16 STP:1; // 11 STOP Condition + Uint16 rsvd1:1; // 12 Reserved + Uint16 STT:1; // 13 START condition bit + Uint16 FREE:1; // 14 Debug Action + Uint16 NACKMOD:1; // 15 NACK mode bit +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code bits. + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 WRITE_ZEROS:4; // 11:8 Reserved + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +struct I2CEMDR_BITS { // bits description + Uint16 BC:1; // 0 Backwards compatibility mode + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level + Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable + Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear + Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag + Uint16 TXFFST:5; // 12:8 Transmit FIFO Status + Uint16 TXFFRST:1; // 13 Transmit FIFO Reset + Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable + Uint16 rsvd1:1; // 15 Reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level + Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable + Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear + Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag + Uint16 RXFFST:5; // 12:8 Receive FIFO Status + Uint16 RXFFRST:1; // 13 Receive FIFO Reset + Uint16 rsvd1:2; // 15:14 Reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + union I2COAR_REG I2COAR; // I2C Own address + union I2CIER_REG I2CIER; // I2C Interrupt Enable + union I2CSTR_REG I2CSTR; // I2C Status + Uint16 I2CCLKL; // I2C Clock low-time divider + Uint16 I2CCLKH; // I2C Clock high-time divider + Uint16 I2CCNT; // I2C Data count + union I2CDRR_REG I2CDRR; // I2C Data receive + union I2CSAR_REG I2CSAR; // I2C Slave address + union I2CDXR_REG I2CDXR; // I2C Data Transmit + union I2CMDR_REG I2CMDR; // I2C Mode + union I2CISRC_REG I2CISRC; // I2C Interrupt Source + union I2CEMDR_REG I2CEMDR; // I2C Extended Mode + union I2CPSC_REG I2CPSC; // I2C Prescaler + Uint16 rsvd1[19]; // Reserved + union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit + union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive +}; + +//--------------------------------------------------------------------------- +// I2C External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct I2C_REGS I2caRegs; +extern volatile struct I2C_REGS I2cbRegs; +#endif +#ifdef CPU2 +extern volatile struct I2C_REGS I2caRegs; +extern volatile struct I2C_REGS I2cbRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_input_xbar.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_input_xbar.h new file mode 100644 index 00000000000..ef3abbe3ab6 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_input_xbar.h @@ -0,0 +1,112 @@ +//########################################################################### +// +// FILE: F2837xD_input_xbar.h +// +// TITLE: INPUT_XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_INPUT_XBAR_H__ +#define __F2837xD_INPUT_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// INPUT_XBAR Individual Register Bit Definitions: + +struct INPUTSELECTLOCK_BITS { // bits description + Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SEL Register + Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SEL Register + Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SEL Register + Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SEL Register + Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SEL Register + Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT7SEL Register + Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT8SEL Register + Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT9SEL Register + Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT10SEL Register + Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT11SEL Register + Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SEL Register + Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SEL Register + Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SEL Register + Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SEL Register + Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SEL Register + Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SEL Register + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union INPUTSELECTLOCK_REG { + Uint32 all; + struct INPUTSELECTLOCK_BITS bit; +}; + +struct INPUT_XBAR_REGS { + Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x) + Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x) + Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x) + Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x) + Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x) + Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x) + Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x) + Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x) + Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x) + Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x) + Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x) + Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x) + Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x) + Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x) + Uint16 rsvd1[16]; // Reserved + union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register +}; + +//--------------------------------------------------------------------------- +// INPUT_XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct INPUT_XBAR_REGS InputXbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_ipc.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_ipc.h new file mode 100644 index 00000000000..411ef4c80b7 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_ipc.h @@ -0,0 +1,313 @@ +//########################################################################### +// +// FILE: F2837xD_ipc.h +// +// TITLE: IPC Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_IPC_H__ +#define __F2837xD_IPC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// IPC Individual Register Bit Definitions: + +struct IPCACK_BITS { // bits description + Uint16 IPC0:1; // 0 Local IPC Flag 0 Acknowledgement + Uint16 IPC1:1; // 1 Local IPC Flag 1 Acknowledgement + Uint16 IPC2:1; // 2 Local IPC Flag 2 Acknowledgement + Uint16 IPC3:1; // 3 Local IPC Flag 3 Acknowledgement + Uint16 IPC4:1; // 4 Local IPC Flag 4 Acknowledgement + Uint16 IPC5:1; // 5 Local IPC Flag 5 Acknowledgement + Uint16 IPC6:1; // 6 Local IPC Flag 6 Acknowledgement + Uint16 IPC7:1; // 7 Local IPC Flag 7 Acknowledgement + Uint16 IPC8:1; // 8 Local IPC Flag 8 Acknowledgement + Uint16 IPC9:1; // 9 Local IPC Flag 9 Acknowledgement + Uint16 IPC10:1; // 10 Local IPC Flag 10 Acknowledgement + Uint16 IPC11:1; // 11 Local IPC Flag 11 Acknowledgement + Uint16 IPC12:1; // 12 Local IPC Flag 12 Acknowledgement + Uint16 IPC13:1; // 13 Local IPC Flag 13 Acknowledgement + Uint16 IPC14:1; // 14 Local IPC Flag 14 Acknowledgement + Uint16 IPC15:1; // 15 Local IPC Flag 15 Acknowledgement + Uint16 IPC16:1; // 16 Local IPC Flag 16 Acknowledgement + Uint16 IPC17:1; // 17 Local IPC Flag 17 Acknowledgement + Uint16 IPC18:1; // 18 Local IPC Flag 18 Acknowledgement + Uint16 IPC19:1; // 19 Local IPC Flag 19 Acknowledgement + Uint16 IPC20:1; // 20 Local IPC Flag 20 Acknowledgement + Uint16 IPC21:1; // 21 Local IPC Flag 21 Acknowledgement + Uint16 IPC22:1; // 22 Local IPC Flag 22 Acknowledgement + Uint16 IPC23:1; // 23 Local IPC Flag 23 Acknowledgement + Uint16 IPC24:1; // 24 Local IPC Flag 24 Acknowledgement + Uint16 IPC25:1; // 25 Local IPC Flag 25 Acknowledgement + Uint16 IPC26:1; // 26 Local IPC Flag 26 Acknowledgement + Uint16 IPC27:1; // 27 Local IPC Flag 27 Acknowledgement + Uint16 IPC28:1; // 28 Local IPC Flag 28 Acknowledgement + Uint16 IPC29:1; // 29 Local IPC Flag 29 Acknowledgement + Uint16 IPC30:1; // 30 Local IPC Flag 30 Acknowledgement + Uint16 IPC31:1; // 31 Local IPC Flag 31 Acknowledgement +}; + +union IPCACK_REG { + Uint32 all; + struct IPCACK_BITS bit; +}; + +struct IPCSTS_BITS { // bits description + Uint16 IPC0:1; // 0 Local IPC Flag 0 Status + Uint16 IPC1:1; // 1 Local IPC Flag 1 Status + Uint16 IPC2:1; // 2 Local IPC Flag 2 Status + Uint16 IPC3:1; // 3 Local IPC Flag 3 Status + Uint16 IPC4:1; // 4 Local IPC Flag 4 Status + Uint16 IPC5:1; // 5 Local IPC Flag 5 Status + Uint16 IPC6:1; // 6 Local IPC Flag 6 Status + Uint16 IPC7:1; // 7 Local IPC Flag 7 Status + Uint16 IPC8:1; // 8 Local IPC Flag 8 Status + Uint16 IPC9:1; // 9 Local IPC Flag 9 Status + Uint16 IPC10:1; // 10 Local IPC Flag 10 Status + Uint16 IPC11:1; // 11 Local IPC Flag 11 Status + Uint16 IPC12:1; // 12 Local IPC Flag 12 Status + Uint16 IPC13:1; // 13 Local IPC Flag 13 Status + Uint16 IPC14:1; // 14 Local IPC Flag 14 Status + Uint16 IPC15:1; // 15 Local IPC Flag 15 Status + Uint16 IPC16:1; // 16 Local IPC Flag 16 Status + Uint16 IPC17:1; // 17 Local IPC Flag 17 Status + Uint16 IPC18:1; // 18 Local IPC Flag 18 Status + Uint16 IPC19:1; // 19 Local IPC Flag 19 Status + Uint16 IPC20:1; // 20 Local IPC Flag 20 Status + Uint16 IPC21:1; // 21 Local IPC Flag 21 Status + Uint16 IPC22:1; // 22 Local IPC Flag 22 Status + Uint16 IPC23:1; // 23 Local IPC Flag 23 Status + Uint16 IPC24:1; // 24 Local IPC Flag 24 Status + Uint16 IPC25:1; // 25 Local IPC Flag 25 Status + Uint16 IPC26:1; // 26 Local IPC Flag 26 Status + Uint16 IPC27:1; // 27 Local IPC Flag 27 Status + Uint16 IPC28:1; // 28 Local IPC Flag 28 Status + Uint16 IPC29:1; // 29 Local IPC Flag 29 Status + Uint16 IPC30:1; // 30 Local IPC Flag 30 Status + Uint16 IPC31:1; // 31 Local IPC Flag 31 Status +}; + +union IPCSTS_REG { + Uint32 all; + struct IPCSTS_BITS bit; +}; + +struct IPCSET_BITS { // bits description + Uint16 IPC0:1; // 0 Set Remote IPC0 Flag + Uint16 IPC1:1; // 1 Set Remote IPC1 Flag + Uint16 IPC2:1; // 2 Set Remote IPC2 Flag + Uint16 IPC3:1; // 3 Set Remote IPC3 Flag + Uint16 IPC4:1; // 4 Set Remote IPC4 Flag + Uint16 IPC5:1; // 5 Set Remote IPC5 Flag + Uint16 IPC6:1; // 6 Set Remote IPC6 Flag + Uint16 IPC7:1; // 7 Set Remote IPC7 Flag + Uint16 IPC8:1; // 8 Set Remote IPC8 Flag + Uint16 IPC9:1; // 9 Set Remote IPC9 Flag + Uint16 IPC10:1; // 10 Set Remote IPC10 Flag + Uint16 IPC11:1; // 11 Set Remote IPC11 Flag + Uint16 IPC12:1; // 12 Set Remote IPC12 Flag + Uint16 IPC13:1; // 13 Set Remote IPC13 Flag + Uint16 IPC14:1; // 14 Set Remote IPC14 Flag + Uint16 IPC15:1; // 15 Set Remote IPC15 Flag + Uint16 IPC16:1; // 16 Set Remote IPC16 Flag + Uint16 IPC17:1; // 17 Set Remote IPC17 Flag + Uint16 IPC18:1; // 18 Set Remote IPC18 Flag + Uint16 IPC19:1; // 19 Set Remote IPC19 Flag + Uint16 IPC20:1; // 20 Set Remote IPC20 Flag + Uint16 IPC21:1; // 21 Set Remote IPC21 Flag + Uint16 IPC22:1; // 22 Set Remote IPC22 Flag + Uint16 IPC23:1; // 23 Set Remote IPC23 Flag + Uint16 IPC24:1; // 24 Set Remote IPC24 Flag + Uint16 IPC25:1; // 25 Set Remote IPC25 Flag + Uint16 IPC26:1; // 26 Set Remote IPC26 Flag + Uint16 IPC27:1; // 27 Set Remote IPC27 Flag + Uint16 IPC28:1; // 28 Set Remote IPC28 Flag + Uint16 IPC29:1; // 29 Set Remote IPC29 Flag + Uint16 IPC30:1; // 30 Set Remote IPC30 Flag + Uint16 IPC31:1; // 31 Set Remote IPC31 Flag +}; + +union IPCSET_REG { + Uint32 all; + struct IPCSET_BITS bit; +}; + +struct IPCCLR_BITS { // bits description + Uint16 IPC0:1; // 0 Clear Remote IPC0 Flag + Uint16 IPC1:1; // 1 Clear Remote IPC1 Flag + Uint16 IPC2:1; // 2 Clear Remote IPC2 Flag + Uint16 IPC3:1; // 3 Clear Remote IPC3 Flag + Uint16 IPC4:1; // 4 Clear Remote IPC4 Flag + Uint16 IPC5:1; // 5 Clear Remote IPC5 Flag + Uint16 IPC6:1; // 6 Clear Remote IPC6 Flag + Uint16 IPC7:1; // 7 Clear Remote IPC7 Flag + Uint16 IPC8:1; // 8 Clear Remote IPC8 Flag + Uint16 IPC9:1; // 9 Clear Remote IPC9 Flag + Uint16 IPC10:1; // 10 Clear Remote IPC10 Flag + Uint16 IPC11:1; // 11 Clear Remote IPC11 Flag + Uint16 IPC12:1; // 12 Clear Remote IPC12 Flag + Uint16 IPC13:1; // 13 Clear Remote IPC13 Flag + Uint16 IPC14:1; // 14 Clear Remote IPC14 Flag + Uint16 IPC15:1; // 15 Clear Remote IPC15 Flag + Uint16 IPC16:1; // 16 Clear Remote IPC16 Flag + Uint16 IPC17:1; // 17 Clear Remote IPC17 Flag + Uint16 IPC18:1; // 18 Clear Remote IPC18 Flag + Uint16 IPC19:1; // 19 Clear Remote IPC19 Flag + Uint16 IPC20:1; // 20 Clear Remote IPC20 Flag + Uint16 IPC21:1; // 21 Clear Remote IPC21 Flag + Uint16 IPC22:1; // 22 Clear Remote IPC22 Flag + Uint16 IPC23:1; // 23 Clear Remote IPC23 Flag + Uint16 IPC24:1; // 24 Clear Remote IPC24 Flag + Uint16 IPC25:1; // 25 Clear Remote IPC25 Flag + Uint16 IPC26:1; // 26 Clear Remote IPC26 Flag + Uint16 IPC27:1; // 27 Clear Remote IPC27 Flag + Uint16 IPC28:1; // 28 Clear Remote IPC28 Flag + Uint16 IPC29:1; // 29 Clear Remote IPC29 Flag + Uint16 IPC30:1; // 30 Clear Remote IPC30 Flag + Uint16 IPC31:1; // 31 Clear Remote IPC31 Flag +}; + +union IPCCLR_REG { + Uint32 all; + struct IPCCLR_BITS bit; +}; + +struct IPCFLG_BITS { // bits description + Uint16 IPC0:1; // 0 Remote IPC0 Flag Status + Uint16 IPC1:1; // 1 Remote IPC1 Flag Status + Uint16 IPC2:1; // 2 Remote IPC2 Flag Status + Uint16 IPC3:1; // 3 Remote IPC3 Flag Status + Uint16 IPC4:1; // 4 Remote IPC4 Flag Status + Uint16 IPC5:1; // 5 Remote IPC5 Flag Status + Uint16 IPC6:1; // 6 Remote IPC6 Flag Status + Uint16 IPC7:1; // 7 Remote IPC7 Flag Status + Uint16 IPC8:1; // 8 Remote IPC8 Flag Status + Uint16 IPC9:1; // 9 Remote IPC9 Flag Status + Uint16 IPC10:1; // 10 Remote IPC10 Flag Status + Uint16 IPC11:1; // 11 Remote IPC11 Flag Status + Uint16 IPC12:1; // 12 Remote IPC12 Flag Status + Uint16 IPC13:1; // 13 Remote IPC13 Flag Status + Uint16 IPC14:1; // 14 Remote IPC14 Flag Status + Uint16 IPC15:1; // 15 Remote IPC15 Flag Status + Uint16 IPC16:1; // 16 Remote IPC16 Flag Status + Uint16 IPC17:1; // 17 Remote IPC17 Flag Status + Uint16 IPC18:1; // 18 Remote IPC18 Flag Status + Uint16 IPC19:1; // 19 Remote IPC19 Flag Status + Uint16 IPC20:1; // 20 Remote IPC20 Flag Status + Uint16 IPC21:1; // 21 Remote IPC21 Flag Status + Uint16 IPC22:1; // 22 Remote IPC22 Flag Status + Uint16 IPC23:1; // 23 Remote IPC23 Flag Status + Uint16 IPC24:1; // 24 Remote IPC24 Flag Status + Uint16 IPC25:1; // 25 Remote IPC25 Flag Status + Uint16 IPC26:1; // 26 Remote IPC26 Flag Status + Uint16 IPC27:1; // 27 Remote IPC27 Flag Status + Uint16 IPC28:1; // 28 Remote IPC28 Flag Status + Uint16 IPC29:1; // 29 Remote IPC29 Flag Status + Uint16 IPC30:1; // 30 Remote IPC30 Flag Status + Uint16 IPC31:1; // 31 Remote IPC31 Flag Status +}; + +union IPCFLG_REG { + Uint32 all; + struct IPCFLG_BITS bit; +}; + +struct IPC_REGS_CPU1 { + union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register + union IPCSTS_REG IPCSTS; // IPC incoming flag status register + union IPCSET_REG IPCSET; // IPC remote flag set register + union IPCCLR_REG IPCCLR; // IPC remote flag clear register + union IPCFLG_REG IPCFLG; // IPC remote flag status register + Uint16 rsvd1[2]; // Reserved + Uint32 IPCCOUNTERL; // IPC Counter Low Register + Uint32 IPCCOUNTERH; // IPC Counter High Register + Uint32 IPCSENDCOM; // Local to Remote IPC Command Register + Uint32 IPCSENDADDR; // Local to Remote IPC Address Register + Uint32 IPCSENDDATA; // Local to Remote IPC Data Register + Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register + Uint32 IPCRECVCOM; // Remote to Local IPC Command Register + Uint32 IPCRECVADDR; // Remote to Local IPC Address Register + Uint32 IPCRECVDATA; // Remote to Local IPC Data Register + Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register + Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register + Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register +}; + +struct IPC_REGS_CPU2 { + union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register + union IPCSTS_REG IPCSTS; // IPC incoming flag status register + union IPCSET_REG IPCSET; // IPC remote flag set register + union IPCCLR_REG IPCCLR; // IPC remote flag clear register + union IPCFLG_REG IPCFLG; // IPC remote flag status register + Uint16 rsvd1[2]; // Reserved + Uint32 IPCCOUNTERL; // IPC Counter Low Register + Uint32 IPCCOUNTERH; // IPC Counter High Register + Uint32 IPCRECVCOM; // Remote to Local IPC Command Register + Uint32 IPCRECVADDR; // Remote to Local IPC Address Register + Uint32 IPCRECVDATA; // Remote to Local IPC Data Register + Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register + Uint32 IPCSENDCOM; // Local to Remote IPC Command Register + Uint32 IPCSENDADDR; // Local to Remote IPC Address Register + Uint32 IPCSENDDATA; // Local to Remote IPC Data Register + Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register + Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register + Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register +}; + +//--------------------------------------------------------------------------- +// IPC External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct IPC_REGS_CPU1 IpcRegs; +#endif +#ifdef CPU2 +extern volatile struct IPC_REGS_CPU2 IpcRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_mcbsp.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_mcbsp.h new file mode 100644 index 00000000000..0f94e760303 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_mcbsp.h @@ -0,0 +1,323 @@ +//########################################################################### +// +// FILE: F2837xD_mcbsp.h +// +// TITLE: MCBSP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_MCBSP_H__ +#define __F2837xD_MCBSP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// MCBSP Individual Register Bit Definitions: + +struct DRR2_BITS { // bits description + Uint16 HWLB:8; // 7:0 High word low byte + Uint16 HWHB:8; // 15:8 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +struct DRR1_BITS { // bits description + Uint16 LWLB:8; // 7:0 Low word low byte + Uint16 LWHB:8; // 15:8 Low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +struct DXR2_BITS { // bits description + Uint16 HWLB:8; // 7:0 High word low byte + Uint16 HWHB:8; // 15:8 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +struct DXR1_BITS { // bits description + Uint16 LWLB:8; // 7:0 Low word low byte + Uint16 LWHB:8; // 15:8 Low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +struct SPCR2_BITS { // bits description + Uint16 XRST:1; // 0 Transmitter reset + Uint16 XRDY:1; // 1 Transmitter ready + Uint16 XEMPTY:1; // 2 Transmitter empty + Uint16 XSYNCERR:1; // 3 Transmit sync error INT flag + Uint16 XINTM:2; // 5:4 Transmit Interupt mode bits + Uint16 GRST:1; // 6 Sample rate generator reset + Uint16 FRST:1; // 7 Frame sync logic reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +struct SPCR1_BITS { // bits description + Uint16 RRST:1; // 0 Receiver reset + Uint16 RRDY:1; // 1 Receiver ready + Uint16 RFULL:1; // 2 Receiver full + Uint16 RSYNCERR:1; // 3 Receive sync error INT flag + Uint16 RINTM:2; // 5:4 Receive Interupt mode bits + Uint16 rsvd1:1; // 6 Reserved + Uint16 DXENA:1; // 7 DX delay enable + Uint16 rsvd2:3; // 10:8 Reserved + Uint16 CLKSTP:2; // 12:11 Clock stop mode + Uint16 RJUST:2; // 14:13 Rx sign extension and justification mode + Uint16 DLB:1; // 15 Digital loopback +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +struct RCR2_BITS { // bits description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length 2 + Uint16 RFRLEN2:7; // 14:8 Receive Frame length 2 + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +struct RCR1_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length 1 + Uint16 RFRLEN1:7; // 14:8 Receive Frame length 1 + Uint16 rsvd2:1; // 15 Reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +struct XCR2_BITS { // bits description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length 2 + Uint16 XFRLEN2:7; // 14:8 Transmit Frame length 2 + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +struct XCR1_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length 1 + Uint16 XFRLEN1:7; // 14:8 Transmit Frame length 1 + Uint16 rsvd2:1; // 15 Reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +struct SRGR2_BITS { // bits description + Uint16 FPER:12; // 11:0 Frame-sync period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd1:1; // 14 Reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +struct SRGR1_BITS { // bits description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +struct MCR2_BITS { // bits description + Uint16 XMCM:2; // 1:0 Transmit data delay + Uint16 XCBLK:3; // 4:2 Transmit frame sync ignore + Uint16 XPABLK:2; // 6:5 Transmit Companding Mode selects + Uint16 XPBBLK:2; // 8:7 Transmit word length 2 + Uint16 XMCME:1; // 9 Transmit Frame length 2 + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +struct MCR1_BITS { // bits description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd1:1; // 1 Reserved + Uint16 RCBLK:3; // 4:2 eceive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 8:7 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd2:6; // 15:10 Reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +struct PCR_BITS { // bits description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:1; // 5 Reserved + Uint16 rsvd3:1; // 6 Reserved + Uint16 SCLKME:1; // 7 Sample clock mode selection + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmit Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 Enable for Receive Interrupt + Uint16 rsvd1:1; // 1 Reserved + Uint16 RINT:1; // 2 Enable for transmit Interrupt + Uint16 rsvd2:13; // 15:3 Reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +struct McBSP_REGS { + union DRR2_REG DRR2; // Data receive register bits 31-16 + union DRR1_REG DRR1; // Data receive register bits 15-0 + union DXR2_REG DXR2; // Data transmit register bits 31-16 + union DXR1_REG DXR1; // Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // Control register 2 + union SPCR1_REG SPCR1; // Control register 1 + union RCR2_REG RCR2; // Receive Control register 2 + union RCR1_REG RCR1; // Receive Control register 1 + union XCR2_REG XCR2; // Transmit Control register 2 + union XCR1_REG XCR1; // Transmit Control register 1 + union SRGR2_REG SRGR2; // Sample rate generator register 2 + union SRGR1_REG SRGR1; // Sample rate generator register 1 + union MCR2_REG MCR2; // Multi-channel register 2 + union MCR1_REG MCR1; // Multi-channel register 1 + Uint16 RCERA; // Receive channel enable partition A + Uint16 RCERB; // Receive channel enable partition B + Uint16 XCERA; // Transmit channel enable partition A + Uint16 XCERB; // Transmit channel enable partition B + union PCR_REG PCR; // Pin Control register + Uint16 RCERC; // Receive channel enable partition C + Uint16 RCERD; // Receive channel enable partition D + Uint16 XCERC; // Transmit channel enable partition C + Uint16 XCERD; // Transmit channel enable partition D + Uint16 RCERE; // Receive channel enable partition E + Uint16 RCERF; // Receive channel enable partition F + Uint16 XCERE; // Transmit channel enable partition E + Uint16 XCERF; // Transmit channel enable partition F + Uint16 RCERG; // Receive channel enable partition G + Uint16 RCERH; // Receive channel enable partition H + Uint16 XCERG; // Transmit channel enable partition G + Uint16 XCERH; // Transmit channel enable partition H + Uint16 rsvd1[4]; // Reserved + union MFFINT_REG MFFINT; // Interrupt enable +}; + +//--------------------------------------------------------------------------- +// MCBSP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct McBSP_REGS McbspaRegs; +extern volatile struct McBSP_REGS McbspbRegs; +#endif +#ifdef CPU2 +extern volatile struct McBSP_REGS McbspaRegs; +extern volatile struct McBSP_REGS McbspbRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_memconfig.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_memconfig.h new file mode 100644 index 00000000000..9dcf877d3cd --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_memconfig.h @@ -0,0 +1,1071 @@ +//########################################################################### +// +// FILE: F2837xD_memconfig.h +// +// TITLE: MEMCONFIG Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_MEMCONFIG_H__ +#define __F2837xD_MEMCONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// MEMCONFIG Individual Register Bit Definitions: + +struct DxLOCK_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 LOCK_D0:1; // 2 D0 RAM access protection and master select fields lock bit + Uint16 LOCK_D1:1; // 3 D1 RAM access protection and master select fields lock bit + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DxLOCK_REG { + Uint32 all; + struct DxLOCK_BITS bit; +}; + +struct DxCOMMIT_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 COMMIT_D0:1; // 2 D0 RAM access protection and master select permanent lock + Uint16 COMMIT_D1:1; // 3 D1 RAM access protection and master select permanent lock + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DxCOMMIT_REG { + Uint32 all; + struct DxCOMMIT_BITS bit; +}; + +struct DxACCPROT0_BITS { // bits description + Uint16 rsvd1:16; // 15:0 Reserved + Uint16 FETCHPROT_D0:1; // 16 Fetch Protection For D0 RAM + Uint16 CPUWRPROT_D0:1; // 17 CPU WR Protection For D0 RAM + Uint16 rsvd2:6; // 23:18 Reserved + Uint16 FETCHPROT_D1:1; // 24 Fetch Protection For D1 RAM + Uint16 CPUWRPROT_D1:1; // 25 CPU WR Protection For D1 RAM + Uint16 rsvd3:6; // 31:26 Reserved +}; + +union DxACCPROT0_REG { + Uint32 all; + struct DxACCPROT0_BITS bit; +}; + +struct DxTEST_BITS { // bits description + Uint16 TEST_M0:2; // 1:0 Selects the different modes for M0 RAM + Uint16 TEST_M1:2; // 3:2 Selects the different modes for M1 RAM + Uint16 TEST_D0:2; // 5:4 Selects the different modes for D0 RAM + Uint16 TEST_D1:2; // 7:6 Selects the different modes for D1 RAM + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DxTEST_REG { + Uint32 all; + struct DxTEST_BITS bit; +}; + +struct DxINIT_BITS { // bits description + Uint16 INIT_M0:1; // 0 RAM Initialization control for M0 RAM. + Uint16 INIT_M1:1; // 1 RAM Initialization control for M1 RAM. + Uint16 INIT_D0:1; // 2 RAM Initialization control for D0 RAM. + Uint16 INIT_D1:1; // 3 RAM Initialization control for D1 RAM. + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DxINIT_REG { + Uint32 all; + struct DxINIT_BITS bit; +}; + +struct DxINITDONE_BITS { // bits description + Uint16 INITDONE_M0:1; // 0 RAM Initialization status for M0 RAM. + Uint16 INITDONE_M1:1; // 1 RAM Initialization status for M1 RAM. + Uint16 INITDONE_D0:1; // 2 RAM Initialization status for D0 RAM. + Uint16 INITDONE_D1:1; // 3 RAM Initialization status for D1 RAM. + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DxINITDONE_REG { + Uint32 all; + struct DxINITDONE_BITS bit; +}; + +struct LSxLOCK_BITS { // bits description + Uint16 LOCK_LS0:1; // 0 LS0 RAM access protection and master select fields lock bit + Uint16 LOCK_LS1:1; // 1 LS1 RAM access protection and master select fields lock bit + Uint16 LOCK_LS2:1; // 2 LS2 RAM access protection and master select fields lock bit + Uint16 LOCK_LS3:1; // 3 LS3 RAM access protection and master select fields lock bit + Uint16 LOCK_LS4:1; // 4 LS4 RAM access protection and master select fields lock bit + Uint16 LOCK_LS5:1; // 5 LS5 RAM access protection and master select fields lock bit + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxLOCK_REG { + Uint32 all; + struct LSxLOCK_BITS bit; +}; + +struct LSxCOMMIT_BITS { // bits description + Uint16 COMMIT_LS0:1; // 0 LS0 RAM access protection and master select permanent lock + Uint16 COMMIT_LS1:1; // 1 LS1 RAM access protection and master select permanent lock + Uint16 COMMIT_LS2:1; // 2 LS2 RAM access protection and master select permanent lock + Uint16 COMMIT_LS3:1; // 3 LS3 RAM access protection and master select permanent lock + Uint16 COMMIT_LS4:1; // 4 LS4 RAM access protection and master select permanent lock + Uint16 COMMIT_LS5:1; // 5 LS5 RAM access protection and master select permanent lock + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxCOMMIT_REG { + Uint32 all; + struct LSxCOMMIT_BITS bit; +}; + +struct LSxMSEL_BITS { // bits description + Uint16 MSEL_LS0:2; // 1:0 Master Select for LS0 RAM + Uint16 MSEL_LS1:2; // 3:2 Master Select for LS1 RAM + Uint16 MSEL_LS2:2; // 5:4 Master Select for LS2 RAM + Uint16 MSEL_LS3:2; // 7:6 Master Select for LS3 RAM + Uint16 MSEL_LS4:2; // 9:8 Master Select for LS4 RAM + Uint16 MSEL_LS5:2; // 11:10 Master Select for LS5 RAM + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxMSEL_REG { + Uint32 all; + struct LSxMSEL_BITS bit; +}; + +struct LSxCLAPGM_BITS { // bits description + Uint16 CLAPGM_LS0:1; // 0 Selects LS0 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS1:1; // 1 Selects LS1 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS2:1; // 2 Selects LS2 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS3:1; // 3 Selects LS3 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS4:1; // 4 Selects LS4 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS5:1; // 5 Selects LS5 RAM as program vs data memory for CLA + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxCLAPGM_REG { + Uint32 all; + struct LSxCLAPGM_BITS bit; +}; + +struct LSxACCPROT0_BITS { // bits description + Uint16 FETCHPROT_LS0:1; // 0 Fetch Protection For LS0 RAM + Uint16 CPUWRPROT_LS0:1; // 1 CPU WR Protection For LS0 RAM + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 FETCHPROT_LS1:1; // 8 Fetch Protection For LS1 RAM + Uint16 CPUWRPROT_LS1:1; // 9 CPU WR Protection For LS1 RAM + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 FETCHPROT_LS2:1; // 16 Fetch Protection For LS2 RAM + Uint16 CPUWRPROT_LS2:1; // 17 CPU WR Protection For LS2 RAM + Uint16 rsvd3:6; // 23:18 Reserved + Uint16 FETCHPROT_LS3:1; // 24 Fetch Protection For LS3 RAM + Uint16 CPUWRPROT_LS3:1; // 25 CPU WR Protection For LS3 RAM + Uint16 rsvd4:6; // 31:26 Reserved +}; + +union LSxACCPROT0_REG { + Uint32 all; + struct LSxACCPROT0_BITS bit; +}; + +struct LSxACCPROT1_BITS { // bits description + Uint16 FETCHPROT_LS4:1; // 0 Fetch Protection For LS4 RAM + Uint16 CPUWRPROT_LS4:1; // 1 CPU WR Protection For LS4 RAM + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 FETCHPROT_LS5:1; // 8 Fetch Protection For LS5 RAM + Uint16 CPUWRPROT_LS5:1; // 9 CPU WR Protection For LS5 RAM + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union LSxACCPROT1_REG { + Uint32 all; + struct LSxACCPROT1_BITS bit; +}; + +struct LSxTEST_BITS { // bits description + Uint16 TEST_LS0:2; // 1:0 Selects the different modes for LS0 RAM + Uint16 TEST_LS1:2; // 3:2 Selects the different modes for LS1 RAM + Uint16 TEST_LS2:2; // 5:4 Selects the different modes for LS2 RAM + Uint16 TEST_LS3:2; // 7:6 Selects the different modes for LS3 RAM + Uint16 TEST_LS4:2; // 9:8 Selects the different modes for LS4 RAM + Uint16 TEST_LS5:2; // 11:10 Selects the different modes for LS5 RAM + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxTEST_REG { + Uint32 all; + struct LSxTEST_BITS bit; +}; + +struct LSxINIT_BITS { // bits description + Uint16 INIT_LS0:1; // 0 RAM Initialization control for LS0 RAM. + Uint16 INIT_LS1:1; // 1 RAM Initialization control for LS1 RAM. + Uint16 INIT_LS2:1; // 2 RAM Initialization control for LS2 RAM. + Uint16 INIT_LS3:1; // 3 RAM Initialization control for LS3 RAM. + Uint16 INIT_LS4:1; // 4 RAM Initialization control for LS4 RAM. + Uint16 INIT_LS5:1; // 5 RAM Initialization control for LS5 RAM. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxINIT_REG { + Uint32 all; + struct LSxINIT_BITS bit; +}; + +struct LSxINITDONE_BITS { // bits description + Uint16 INITDONE_LS0:1; // 0 RAM Initialization status for LS0 RAM. + Uint16 INITDONE_LS1:1; // 1 RAM Initialization status for LS1 RAM. + Uint16 INITDONE_LS2:1; // 2 RAM Initialization status for LS2 RAM. + Uint16 INITDONE_LS3:1; // 3 RAM Initialization status for LS3 RAM. + Uint16 INITDONE_LS4:1; // 4 RAM Initialization status for LS4 RAM. + Uint16 INITDONE_LS5:1; // 5 RAM Initialization status for LS5 RAM. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxINITDONE_REG { + Uint32 all; + struct LSxINITDONE_BITS bit; +}; + +struct GSxLOCK_BITS { // bits description + Uint16 LOCK_GS0:1; // 0 GS0 RAM access protection and master select fields lock bit + Uint16 LOCK_GS1:1; // 1 GS1 RAM access protection and master select fields lock bit + Uint16 LOCK_GS2:1; // 2 GS2 RAM access protection and master select fields lock bit + Uint16 LOCK_GS3:1; // 3 GS3 RAM access protection and master select fields lock bit + Uint16 LOCK_GS4:1; // 4 GS4 RAM access protection and master select fields lock bit + Uint16 LOCK_GS5:1; // 5 GS5 RAM access protection and master select fields lock bit + Uint16 LOCK_GS6:1; // 6 GS6 RAM access protection and master select fields lock bit + Uint16 LOCK_GS7:1; // 7 GS7 RAM access protection and master select fields lock bit + Uint16 LOCK_GS8:1; // 8 GS8 RAM access protection and master select fields lock bit + Uint16 LOCK_GS9:1; // 9 GS9 RAM access protection and master select fields lock bit + Uint16 LOCK_GS10:1; // 10 GS10 RAM access protection and master select fields lock bit + Uint16 LOCK_GS11:1; // 11 GS11 RAM access protection and master select fields lock bit + Uint16 LOCK_GS12:1; // 12 GS12 RAM access protection and master select fields lock bit + Uint16 LOCK_GS13:1; // 13 GS13 RAM access protection and master select fields lock bit + Uint16 LOCK_GS14:1; // 14 GS14 RAM access protection and master select fields lock bit + Uint16 LOCK_GS15:1; // 15 GS15 RAM access protection and master select fields lock bit + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxLOCK_REG { + Uint32 all; + struct GSxLOCK_BITS bit; +}; + +struct GSxCOMMIT_BITS { // bits description + Uint16 COMMIT_GS0:1; // 0 GS0 RAM access protection and master select permanent lock + Uint16 COMMIT_GS1:1; // 1 GS1 RAM access protection and master select permanent lock + Uint16 COMMIT_GS2:1; // 2 GS2 RAM access protection and master select permanent lock + Uint16 COMMIT_GS3:1; // 3 GS3 RAM access protection and master select permanent lock + Uint16 COMMIT_GS4:1; // 4 GS4 RAM access protection and master select permanent lock + Uint16 COMMIT_GS5:1; // 5 GS5 RAM access protection and master select permanent lock + Uint16 COMMIT_GS6:1; // 6 GS6 RAM access protection and master select permanent lock + Uint16 COMMIT_GS7:1; // 7 GS7 RAM access protection and master select permanent lock + Uint16 COMMIT_GS8:1; // 8 GS8 RAM access protection and master select permanent lock + Uint16 COMMIT_GS9:1; // 9 GS9 RAM access protection and master select permanent lock + Uint16 COMMIT_GS10:1; // 10 GS10 RAM access protection and master select permanent lock + Uint16 COMMIT_GS11:1; // 11 GS11 RAM access protection and master select permanent lock + Uint16 COMMIT_GS12:1; // 12 GS12 RAM access protection and master select permanent lock + Uint16 COMMIT_GS13:1; // 13 GS13 RAM access protection and master select permanent lock + Uint16 COMMIT_GS14:1; // 14 GS14 RAM access protection and master select permanent lock + Uint16 COMMIT_GS15:1; // 15 GS15 RAM access protection and master select permanent lock + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxCOMMIT_REG { + Uint32 all; + struct GSxCOMMIT_BITS bit; +}; + +struct GSxMSEL_BITS { // bits description + Uint16 MSEL_GS0:1; // 0 Master Select for GS0 RAM + Uint16 MSEL_GS1:1; // 1 Master Select for GS1 RAM + Uint16 MSEL_GS2:1; // 2 Master Select for GS2 RAM + Uint16 MSEL_GS3:1; // 3 Master Select for GS3 RAM + Uint16 MSEL_GS4:1; // 4 Master Select for GS4 RAM + Uint16 MSEL_GS5:1; // 5 Master Select for GS5 RAM + Uint16 MSEL_GS6:1; // 6 Master Select for GS6 RAM + Uint16 MSEL_GS7:1; // 7 Master Select for GS7 RAM + Uint16 MSEL_GS8:1; // 8 Master Select for GS8 RAM + Uint16 MSEL_GS9:1; // 9 Master Select for GS9 RAM + Uint16 MSEL_GS10:1; // 10 Master Select for GS10 RAM + Uint16 MSEL_GS11:1; // 11 Master Select for GS11 RAM + Uint16 MSEL_GS12:1; // 12 Master Select for GS12 RAM + Uint16 MSEL_GS13:1; // 13 Master Select for GS13 RAM + Uint16 MSEL_GS14:1; // 14 Master Select for GS14 RAM + Uint16 MSEL_GS15:1; // 15 Master Select for GS15 RAM + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxMSEL_REG { + Uint32 all; + struct GSxMSEL_BITS bit; +}; + +struct GSxACCPROT0_BITS { // bits description + Uint16 FETCHPROT_GS0:1; // 0 Fetch Protection For GS0 RAM + Uint16 CPUWRPROT_GS0:1; // 1 CPU WR Protection For GS0 RAM + Uint16 DMAWRPROT_GS0:1; // 2 DMA WR Protection For GS0 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS1:1; // 8 Fetch Protection For GS1 RAM + Uint16 CPUWRPROT_GS1:1; // 9 CPU WR Protection For GS1 RAM + Uint16 DMAWRPROT_GS1:1; // 10 DMA WR Protection For GS1 RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS2:1; // 16 Fetch Protection For GS2 RAM + Uint16 CPUWRPROT_GS2:1; // 17 CPU WR Protection For GS2 RAM + Uint16 DMAWRPROT_GS2:1; // 18 DMA WR Protection For GS2 RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS3:1; // 24 Fetch Protection For GS3 RAM + Uint16 CPUWRPROT_GS3:1; // 25 CPU WR Protection For GS3 RAM + Uint16 DMAWRPROT_GS3:1; // 26 DMA WR Protection For GS3 RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT0_REG { + Uint32 all; + struct GSxACCPROT0_BITS bit; +}; + +struct GSxACCPROT1_BITS { // bits description + Uint16 FETCHPROT_GS4:1; // 0 Fetch Protection For GS4 RAM + Uint16 CPUWRPROT_GS4:1; // 1 CPU WR Protection For GS4 RAM + Uint16 DMAWRPROT_GS4:1; // 2 DMA WR Protection For GS4 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS5:1; // 8 Fetch Protection For GS5 RAM + Uint16 CPUWRPROT_GS5:1; // 9 CPU WR Protection For GS5 RAM + Uint16 DMAWRPROT_GS5:1; // 10 DMA WR Protection For GS5RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS6:1; // 16 Fetch Protection For GS6 RAM + Uint16 CPUWRPROT_GS6:1; // 17 CPU WR Protection For GS6 RAM + Uint16 DMAWRPROT_GS6:1; // 18 DMA WR Protection For GS6RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS7:1; // 24 Fetch Protection For GS7 RAM + Uint16 CPUWRPROT_GS7:1; // 25 CPU WR Protection For GS7 RAM + Uint16 DMAWRPROT_GS7:1; // 26 DMA WR Protection For GS7RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT1_REG { + Uint32 all; + struct GSxACCPROT1_BITS bit; +}; + +struct GSxACCPROT2_BITS { // bits description + Uint16 FETCHPROT_GS8:1; // 0 Fetch Protection For GS8 RAM + Uint16 CPUWRPROT_GS8:1; // 1 CPU WR Protection For GS8 RAM + Uint16 DMAWRPROT_GS8:1; // 2 DMA WR Protection For GS8 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS9:1; // 8 Fetch Protection For GS9 RAM + Uint16 CPUWRPROT_GS9:1; // 9 CPU WR Protection For GS9 RAM + Uint16 DMAWRPROT_GS9:1; // 10 DMA WR Protection For GS9RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS10:1; // 16 Fetch Protection For GS10 RAM + Uint16 CPUWRPROT_GS10:1; // 17 CPU WR Protection For GS10 RAM + Uint16 DMAWRPROT_GS10:1; // 18 DMA WR Protection For GS10RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS11:1; // 24 Fetch Protection For GS11 RAM + Uint16 CPUWRPROT_GS11:1; // 25 CPU WR Protection For GS11 RAM + Uint16 DMAWRPROT_GS11:1; // 26 DMA WR Protection For GS11RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT2_REG { + Uint32 all; + struct GSxACCPROT2_BITS bit; +}; + +struct GSxACCPROT3_BITS { // bits description + Uint16 FETCHPROT_GS12:1; // 0 Fetch Protection For GS12 RAM + Uint16 CPUWRPROT_GS12:1; // 1 CPU WR Protection For GS12 RAM + Uint16 DMAWRPROT_GS12:1; // 2 DMA WR Protection For GS12 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS13:1; // 8 Fetch Protection For GS13 RAM + Uint16 CPUWRPROT_GS13:1; // 9 CPU WR Protection For GS13 RAM + Uint16 DMAWRPROT_GS13:1; // 10 DMA WR Protection For GS13RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS14:1; // 16 Fetch Protection For GS14 RAM + Uint16 CPUWRPROT_GS14:1; // 17 CPU WR Protection For GS14 RAM + Uint16 DMAWRPROT_GS14:1; // 18 DMA WR Protection For GS14RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS15:1; // 24 Fetch Protection For GS15 RAM + Uint16 CPUWRPROT_GS15:1; // 25 CPU WR Protection For GS15 RAM + Uint16 DMAWRPROT_GS15:1; // 26 DMA WR Protection For GS15RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT3_REG { + Uint32 all; + struct GSxACCPROT3_BITS bit; +}; + +struct GSxTEST_BITS { // bits description + Uint16 TEST_GS0:2; // 1:0 Selects the different modes for GS0 RAM + Uint16 TEST_GS1:2; // 3:2 Selects the different modes for GS1 RAM + Uint16 TEST_GS2:2; // 5:4 Selects the different modes for GS2 RAM + Uint16 TEST_GS3:2; // 7:6 Selects the different modes for GS3 RAM + Uint16 TEST_GS4:2; // 9:8 Selects the different modes for GS4 RAM + Uint16 TEST_GS5:2; // 11:10 Selects the different modes for GS5 RAM + Uint16 TEST_GS6:2; // 13:12 Selects the different modes for GS6 RAM + Uint16 TEST_GS7:2; // 15:14 Selects the different modes for GS7 RAM + Uint16 TEST_GS8:2; // 17:16 Selects the different modes for GS8 RAM + Uint16 TEST_GS9:2; // 19:18 Selects the different modes for GS9 RAM + Uint16 TEST_GS10:2; // 21:20 Selects the different modes for GS10 RAM + Uint16 TEST_GS11:2; // 23:22 Selects the different modes for GS11 RAM + Uint16 TEST_GS12:2; // 25:24 Selects the different modes for GS12 RAM + Uint16 TEST_GS13:2; // 27:26 Selects the different modes for GS13 RAM + Uint16 TEST_GS14:2; // 29:28 Selects the different modes for GS14 RAM + Uint16 TEST_GS15:2; // 31:30 Selects the different modes for GS15 RAM +}; + +union GSxTEST_REG { + Uint32 all; + struct GSxTEST_BITS bit; +}; + +struct GSxINIT_BITS { // bits description + Uint16 INIT_GS0:1; // 0 RAM Initialization control for GS0 RAM. + Uint16 INIT_GS1:1; // 1 RAM Initialization control for GS1 RAM. + Uint16 INIT_GS2:1; // 2 RAM Initialization control for GS2 RAM. + Uint16 INIT_GS3:1; // 3 RAM Initialization control for GS3 RAM. + Uint16 INIT_GS4:1; // 4 RAM Initialization control for GS4 RAM. + Uint16 INIT_GS5:1; // 5 RAM Initialization control for GS5 RAM. + Uint16 INIT_GS6:1; // 6 RAM Initialization control for GS6 RAM. + Uint16 INIT_GS7:1; // 7 RAM Initialization control for GS7 RAM. + Uint16 INIT_GS8:1; // 8 RAM Initialization control for GS8 RAM. + Uint16 INIT_GS9:1; // 9 RAM Initialization control for GS9 RAM. + Uint16 INIT_GS10:1; // 10 RAM Initialization control for GS10 RAM. + Uint16 INIT_GS11:1; // 11 RAM Initialization control for GS11 RAM. + Uint16 INIT_GS12:1; // 12 RAM Initialization control for GS12 RAM. + Uint16 INIT_GS13:1; // 13 RAM Initialization control for GS13 RAM. + Uint16 INIT_GS14:1; // 14 RAM Initialization control for GS14 RAM. + Uint16 INIT_GS15:1; // 15 RAM Initialization control for GS15 RAM. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxINIT_REG { + Uint32 all; + struct GSxINIT_BITS bit; +}; + +struct GSxINITDONE_BITS { // bits description + Uint16 INITDONE_GS0:1; // 0 RAM Initialization status for GS0 RAM. + Uint16 INITDONE_GS1:1; // 1 RAM Initialization status for GS1 RAM. + Uint16 INITDONE_GS2:1; // 2 RAM Initialization status for GS2 RAM. + Uint16 INITDONE_GS3:1; // 3 RAM Initialization status for GS3 RAM. + Uint16 INITDONE_GS4:1; // 4 RAM Initialization status for GS4 RAM. + Uint16 INITDONE_GS5:1; // 5 RAM Initialization status for GS5 RAM. + Uint16 INITDONE_GS6:1; // 6 RAM Initialization status for GS6 RAM. + Uint16 INITDONE_GS7:1; // 7 RAM Initialization status for GS7 RAM. + Uint16 INITDONE_GS8:1; // 8 RAM Initialization status for GS8 RAM. + Uint16 INITDONE_GS9:1; // 9 RAM Initialization status for GS9 RAM. + Uint16 INITDONE_GS10:1; // 10 RAM Initialization status for GS10 RAM. + Uint16 INITDONE_GS11:1; // 11 RAM Initialization status for GS11 RAM. + Uint16 INITDONE_GS12:1; // 12 RAM Initialization status for GS12 RAM. + Uint16 INITDONE_GS13:1; // 13 RAM Initialization status for GS13 RAM. + Uint16 INITDONE_GS14:1; // 14 RAM Initialization status for GS14 RAM. + Uint16 INITDONE_GS15:1; // 15 RAM Initialization status for GS15 RAM. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxINITDONE_REG { + Uint32 all; + struct GSxINITDONE_BITS bit; +}; + +struct MSGxTEST_BITS { // bits description + Uint16 TEST_CPUTOCPU:2; // 1:0 CPU to CPU Mode Select + Uint16 TEST_CPUTOCLA1:2; // 3:2 CPU to CLA1 MSG RAM Mode Select + Uint16 TEST_CLA1TOCPU:2; // 5:4 CLA1 to CPU MSG RAM Mode Select + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 rsvd2:2; // 9:8 Reserved + Uint16 rsvd3:6; // 15:10 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union MSGxTEST_REG { + Uint32 all; + struct MSGxTEST_BITS bit; +}; + +struct MSGxINIT_BITS { // bits description + Uint16 INIT_CPUTOCPU:1; // 0 Initialization control for CPU to CPU MSG RAM + Uint16 INIT_CPUTOCLA1:1; // 1 Initialization control for CPUTOCLA1 MSG RAM + Uint16 INIT_CLA1TOCPU:1; // 2 Initialization control for CLA1TOCPU MSG RAM + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:1; // 4 Reserved + Uint16 rsvd3:11; // 15:5 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union MSGxINIT_REG { + Uint32 all; + struct MSGxINIT_BITS bit; +}; + +struct MSGxINITDONE_BITS { // bits description + Uint16 INITDONE_CPUTOCPU:1; // 0 Initialization status for CPU to CPU MSG RAM + Uint16 INITDONE_CPUTOCLA1:1; // 1 Initialization status for CPU to CLA1 MSG RAM + Uint16 INITDONE_CLA1TOCPU:1; // 2 Initialization status for CLA1 to CPU MSG RAM + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:1; // 4 Reserved + Uint16 rsvd3:11; // 15:5 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union MSGxINITDONE_REG { + Uint32 all; + struct MSGxINITDONE_BITS bit; +}; + +struct MEM_CFG_REGS { + union DxLOCK_REG DxLOCK; // Dedicated RAM Config Lock Register + union DxCOMMIT_REG DxCOMMIT; // Dedicated RAM Config Lock Commit Register + Uint16 rsvd1[4]; // Reserved + union DxACCPROT0_REG DxACCPROT0; // Dedicated RAM Config Register + Uint16 rsvd2[6]; // Reserved + union DxTEST_REG DxTEST; // Dedicated RAM TEST Register + union DxINIT_REG DxINIT; // Dedicated RAM Init Register + union DxINITDONE_REG DxINITDONE; // Dedicated RAM InitDone Status Register + Uint16 rsvd3[10]; // Reserved + union LSxLOCK_REG LSxLOCK; // Local Shared RAM Config Lock Register + union LSxCOMMIT_REG LSxCOMMIT; // Local Shared RAM Config Lock Commit Register + union LSxMSEL_REG LSxMSEL; // Local Shared RAM Master Sel Register + union LSxCLAPGM_REG LSxCLAPGM; // Local Shared RAM Prog/Exe control Register + union LSxACCPROT0_REG LSxACCPROT0; // Local Shared RAM Config Register 0 + union LSxACCPROT1_REG LSxACCPROT1; // Local Shared RAM Config Register 1 + Uint16 rsvd4[4]; // Reserved + union LSxTEST_REG LSxTEST; // Local Shared RAM TEST Register + union LSxINIT_REG LSxINIT; // Local Shared RAM Init Register + union LSxINITDONE_REG LSxINITDONE; // Local Shared RAM InitDone Status Register + Uint16 rsvd5[10]; // Reserved + union GSxLOCK_REG GSxLOCK; // Global Shared RAM Config Lock Register + union GSxCOMMIT_REG GSxCOMMIT; // Global Shared RAM Config Lock Commit Register + union GSxMSEL_REG GSxMSEL; // Global Shared RAM Master Sel Register + Uint16 rsvd6[2]; // Reserved + union GSxACCPROT0_REG GSxACCPROT0; // Global Shared RAM Config Register 0 + union GSxACCPROT1_REG GSxACCPROT1; // Global Shared RAM Config Register 1 + union GSxACCPROT2_REG GSxACCPROT2; // Global Shared RAM Config Register 2 + union GSxACCPROT3_REG GSxACCPROT3; // Global Shared RAM Config Register 3 + union GSxTEST_REG GSxTEST; // Global Shared RAM TEST Register + union GSxINIT_REG GSxINIT; // Global Shared RAM Init Register + union GSxINITDONE_REG GSxINITDONE; // Global Shared RAM InitDone Status Register + Uint16 rsvd7[26]; // Reserved + union MSGxTEST_REG MSGxTEST; // Message RAM TEST Register + union MSGxINIT_REG MSGxINIT; // Message RAM Init Register + union MSGxINITDONE_REG MSGxINITDONE; // Message RAM InitDone Status Register + Uint16 rsvd8[10]; // Reserved +}; + +struct EMIF1LOCK_BITS { // bits description + Uint16 LOCK_EMIF1:1; // 0 EMIF1 access protection and master select fields lock bit + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF1LOCK_REG { + Uint32 all; + struct EMIF1LOCK_BITS bit; +}; + +struct EMIF1COMMIT_BITS { // bits description + Uint16 COMMIT_EMIF1:1; // 0 EMIF1 access protection and master select permanent lock + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF1COMMIT_REG { + Uint32 all; + struct EMIF1COMMIT_BITS bit; +}; + +struct EMIF1MSEL_BITS { // bits description + Uint16 MSEL_EMIF1:2; // 1:0 Master Select for EMIF1. + Uint16 rsvd1:2; // 3:2 Reserved + Uint32 KEY:28; // 31:4 KEY to enable the write into MSEL_EMIF1 bits +}; + +union EMIF1MSEL_REG { + Uint32 all; + struct EMIF1MSEL_BITS bit; +}; + +struct EMIF1ACCPROT0_BITS { // bits description + Uint16 FETCHPROT_EMIF1:1; // 0 Fetch Protection For EMIF1 + Uint16 CPUWRPROT_EMIF1:1; // 1 CPU WR Protection For EMIF1 + Uint16 DMAWRPROT_EMIF1:1; // 2 DMA WR Protection For EMIF1 + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF1ACCPROT0_REG { + Uint32 all; + struct EMIF1ACCPROT0_BITS bit; +}; + +struct EMIF1_CONFIG_REGS { + union EMIF1LOCK_REG EMIF1LOCK; // EMIF1 Config Lock Register + union EMIF1COMMIT_REG EMIF1COMMIT; // EMIF1 Config Lock Commit Register + union EMIF1MSEL_REG EMIF1MSEL; // EMIF1 Master Sel Register + Uint16 rsvd1[2]; // Reserved + union EMIF1ACCPROT0_REG EMIF1ACCPROT0; // EMIF1 Config Register 0 + Uint16 rsvd2[22]; // Reserved +}; + +struct EMIF2LOCK_BITS { // bits description + Uint16 LOCK_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF2LOCK_REG { + Uint32 all; + struct EMIF2LOCK_BITS bit; +}; + +struct EMIF2COMMIT_BITS { // bits description + Uint16 COMMIT_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF2COMMIT_REG { + Uint32 all; + struct EMIF2COMMIT_BITS bit; +}; + +struct EMIF2ACCPROT0_BITS { // bits description + Uint16 FETCHPROT_EMIF2:1; // 0 Fetch Protection For EMIF2 + Uint16 CPUWRPROT_EMIF2:1; // 1 CPU WR Protection For EMIF2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF2ACCPROT0_REG { + Uint32 all; + struct EMIF2ACCPROT0_BITS bit; +}; + +struct EMIF2_CONFIG_REGS { + union EMIF2LOCK_REG EMIF2LOCK; // EMIF2 Config Lock Register + union EMIF2COMMIT_REG EMIF2COMMIT; // EMIF2 Config Lock Commit Register + Uint16 rsvd1[4]; // Reserved + union EMIF2ACCPROT0_REG EMIF2ACCPROT0; // EMIF2 Config Register 0 + Uint16 rsvd2[22]; // Reserved +}; + +struct NMAVFLG_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVFLG_REG { + Uint32 all; + struct NMAVFLG_BITS bit; +}; + +struct NMAVSET_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Set + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Set + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Set + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Set + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Set + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Set + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Set + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVSET_REG { + Uint32 all; + struct NMAVSET_BITS bit; +}; + +struct NMAVCLR_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Clear + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Clear + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Clear + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Clear + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Clear + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Clear + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Clear + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVCLR_REG { + Uint32 all; + struct NMAVCLR_BITS bit; +}; + +struct NMAVINTEN_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Interrupt Enable + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Interrupt Enable + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Interrupt Enable + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Interrupt Enable + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Interrupt Enable + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Interrupt Enable + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVINTEN_REG { + Uint32 all; + struct NMAVINTEN_BITS bit; +}; + +struct MAVFLG_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVFLG_REG { + Uint32 all; + struct MAVFLG_BITS bit; +}; + +struct MAVSET_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Set + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Set + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Set + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVSET_REG { + Uint32 all; + struct MAVSET_BITS bit; +}; + +struct MAVCLR_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Clear + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Clear + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Clear + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVCLR_REG { + Uint32 all; + struct MAVCLR_BITS bit; +}; + +struct MAVINTEN_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Interrupt Enable + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Interrupt Enable + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Interrupt Enable + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVINTEN_REG { + Uint32 all; + struct MAVINTEN_BITS bit; +}; + +struct ACCESS_PROTECTION_REGS { + union NMAVFLG_REG NMAVFLG; // Non-Master Access Violation Flag Register + union NMAVSET_REG NMAVSET; // Non-Master Access Violation Flag Set Register + union NMAVCLR_REG NMAVCLR; // Non-Master Access Violation Flag Clear Register + union NMAVINTEN_REG NMAVINTEN; // Non-Master Access Violation Interrupt Enable Register + Uint32 NMCPURDAVADDR; // Non-Master CPU Read Access Violation Address + Uint32 NMCPUWRAVADDR; // Non-Master CPU Write Access Violation Address + Uint32 NMCPUFAVADDR; // Non-Master CPU Fetch Access Violation Address + Uint32 NMDMAWRAVADDR; // Non-Master DMA Write Access Violation Address + Uint32 NMCLA1RDAVADDR; // Non-Master CLA1 Read Access Violation Address + Uint32 NMCLA1WRAVADDR; // Non-Master CLA1 Write Access Violation Address + Uint32 NMCLA1FAVADDR; // Non-Master CLA1 Fetch Access Violation Address + Uint16 rsvd1[10]; // Reserved + union MAVFLG_REG MAVFLG; // Master Access Violation Flag Register + union MAVSET_REG MAVSET; // Master Access Violation Flag Set Register + union MAVCLR_REG MAVCLR; // Master Access Violation Flag Clear Register + union MAVINTEN_REG MAVINTEN; // Master Access Violation Interrupt Enable Register + Uint32 MCPUFAVADDR; // Master CPU Fetch Access Violation Address + Uint32 MCPUWRAVADDR; // Master CPU Write Access Violation Address + Uint32 MDMAWRAVADDR; // Master DMA Write Access Violation Address + Uint16 rsvd2[18]; // Reserved +}; + +struct UCERRFLG_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag + Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag + Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union UCERRFLG_REG { + Uint32 all; + struct UCERRFLG_BITS bit; +}; + +struct UCERRSET_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Set + Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Set + Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Set + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union UCERRSET_REG { + Uint32 all; + struct UCERRSET_BITS bit; +}; + +struct UCERRCLR_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Clear + Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Clear + Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Clear + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union UCERRCLR_REG { + Uint32 all; + struct UCERRCLR_BITS bit; +}; + +struct CERRFLG_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag + Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag + Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CERRFLG_REG { + Uint32 all; + struct CERRFLG_BITS bit; +}; + +struct CERRSET_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Set + Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Set + Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Set + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CERRSET_REG { + Uint32 all; + struct CERRSET_BITS bit; +}; + +struct CERRCLR_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Clear + Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Clear + Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Clear + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CERRCLR_REG { + Uint32 all; + struct CERRCLR_BITS bit; +}; + +struct CEINTFLG_BITS { // bits description + Uint16 CEINTFLAG:1; // 0 Total corrected error count exceeded threshold flag. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTFLG_REG { + Uint32 all; + struct CEINTFLG_BITS bit; +}; + +struct CEINTCLR_BITS { // bits description + Uint16 CEINTCLR:1; // 0 CPU Corrected Error Threshold Exceeded Error Clear. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTCLR_REG { + Uint32 all; + struct CEINTCLR_BITS bit; +}; + +struct CEINTSET_BITS { // bits description + Uint16 CEINTSET:1; // 0 Total corrected error count exceeded flag set. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTSET_REG { + Uint32 all; + struct CEINTSET_BITS bit; +}; + +struct CEINTEN_BITS { // bits description + Uint16 CEINTEN:1; // 0 CPU/DMA Correctable Error Interrupt Enable. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTEN_REG { + Uint32 all; + struct CEINTEN_BITS bit; +}; + +struct MEMORY_ERROR_REGS { + union UCERRFLG_REG UCERRFLG; // Uncorrectable Error Flag Register + union UCERRSET_REG UCERRSET; // Uncorrectable Error Flag Set Register + union UCERRCLR_REG UCERRCLR; // Uncorrectable Error Flag Clear Register + Uint32 UCCPUREADDR; // Uncorrectable CPU Read Error Address + Uint32 UCDMAREADDR; // Uncorrectable DMA Read Error Address + Uint32 UCCLA1READDR; // Uncorrectable CLA1 Read Error Address + Uint16 rsvd1[20]; // Reserved + union CERRFLG_REG CERRFLG; // Correctable Error Flag Register + union CERRSET_REG CERRSET; // Correctable Error Flag Set Register + union CERRCLR_REG CERRCLR; // Correctable Error Flag Clear Register + Uint32 CCPUREADDR; // Correctable CPU Read Error Address + Uint16 rsvd2[6]; // Reserved + Uint32 CERRCNT; // Correctable Error Count Register + Uint32 CERRTHRES; // Correctable Error Threshold Value Register + union CEINTFLG_REG CEINTFLG; // Correctable Error Interrupt Flag Status Register + union CEINTCLR_REG CEINTCLR; // Correctable Error Interrupt Flag Clear Register + union CEINTSET_REG CEINTSET; // Correctable Error Interrupt Flag Set Register + union CEINTEN_REG CEINTEN; // Correctable Error Interrupt Enable Register + Uint16 rsvd3[6]; // Reserved +}; + +struct ROMWAITSTATE_BITS { // bits description + Uint16 WSDISABLE:1; // 0 ROM Wait State Enable/Disable Control + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ROMWAITSTATE_REG { + Uint32 all; + struct ROMWAITSTATE_BITS bit; +}; + +struct ROM_WAIT_STATE_REGS { + union ROMWAITSTATE_REG ROMWAITSTATE; // ROM Wait State Configuration Register +}; + +struct ROMPREFETCH_BITS { // bits description + Uint16 PFENABLE:1; // 0 ROM Prefetch Enable/Disable Control + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ROMPREFETCH_REG { + Uint32 all; + struct ROMPREFETCH_BITS bit; +}; + +struct ROM_PREFETCH_REGS { + union ROMPREFETCH_REG ROMPREFETCH; // ROM Prefetch Configuration Register +}; + +//--------------------------------------------------------------------------- +// MEMCONFIG External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; +extern volatile struct MEM_CFG_REGS MemCfgRegs; +extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; +extern volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; +extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; +extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; +extern volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; +#endif +#ifdef CPU2 +extern volatile struct MEM_CFG_REGS MemCfgRegs; +extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; +extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; +extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_nmiintrupt.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_nmiintrupt.h new file mode 100644 index 00000000000..0bbe21fe210 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_nmiintrupt.h @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: F2837xD_nmiintrupt.h +// +// TITLE: NMIINTRUPT Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_NMIINTRUPT_H__ +#define __F2837xD_NMIINTRUPT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// NMIINTRUPT Individual Register Bit Definitions: + +struct NMICFG_BITS { // bits description + Uint16 NMIE:1; // 0 Global NMI Enable + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union NMICFG_REG { + Uint16 all; + struct NMICFG_BITS bit; +}; + +struct NMIFLG_BITS { // bits description + Uint16 NMIINT:1; // 0 NMI Interrupt Flag + Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag + Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag + Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag + Uint16 CPU1HWBISTERR:1; // 4 HW BIST Error NMI Flag + Uint16 CPU2HWBISTERR:1; // 5 HW BIST Error NMI Flag + Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 CPU2 WDRSn Reset Indication Flag + Uint16 CPU2NMIWDRSn:1; // 10 CPU2 NMIWDRSn Reset Indication Flag + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union NMIFLG_REG { + Uint16 all; + struct NMIFLG_BITS bit; +}; + +struct NMIFLGCLR_BITS { // bits description + Uint16 NMIINT:1; // 0 NMIINT Flag Clear + Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear + Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear + Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear + Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Clear + Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Clear + Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Clear + Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Clear + Uint16 OVF:1; // 11 OVF Flag Clear + Uint16 rsvd3:4; // 15:12 Reserved +}; + +union NMIFLGCLR_REG { + Uint16 all; + struct NMIFLGCLR_BITS bit; +}; + +struct NMIFLGFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force + Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force + Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force + Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Force + Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Force + Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Force + Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Force + Uint16 OVF:1; // 11 OVF Flag Force + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union NMIFLGFRC_REG { + Uint16 all; + struct NMIFLGFRC_BITS bit; +}; + +struct NMISHDFLG_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag + Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag + Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag + Uint16 CPU1HWBISTERR:1; // 4 Shadow CPU1HWBISTERR Flag + Uint16 CPU2HWBISTERR:1; // 5 Shadow CPU2HWBISTERR Flag + Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 Shadow CPU2WDRSn Flag + Uint16 CPU2NMIWDRSn:1; // 10 Shadow CPU2NMIWDRSn Flag + Uint16 OVF:1; // 11 Shadow OVF Flag + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union NMISHDFLG_REG { + Uint16 all; + struct NMISHDFLG_BITS bit; +}; + +struct NMI_INTRUPT_REGS { + union NMICFG_REG NMICFG; // NMI Configuration Register + union NMIFLG_REG NMIFLG; // NMI Flag Register (XRSn Clear) + union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register + union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register + Uint16 NMIWDCNT; // NMI Watchdog Counter Register + Uint16 NMIWDPRD; // NMI Watchdog Period Register + union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register +}; + +//--------------------------------------------------------------------------- +// NMIINTRUPT External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; +#endif +#ifdef CPU2 +extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_output_xbar.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_output_xbar.h new file mode 100644 index 00000000000..aad7cada65b --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_output_xbar.h @@ -0,0 +1,907 @@ +//########################################################################### +// +// FILE: F2837xD_output_xbar.h +// +// TITLE: OUTPUT_XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_OUTPUT_XBAR_H__ +#define __F2837xD_OUTPUT_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// OUTPUT_XBAR Individual Register Bit Definitions: + +struct OUTPUT1MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR +}; + +union OUTPUT1MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT1MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT1MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR +}; + +union OUTPUT1MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT1MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT2MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR +}; + +union OUTPUT2MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT2MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT2MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR +}; + +union OUTPUT2MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT2MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT3MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR +}; + +union OUTPUT3MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT3MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT3MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR +}; + +union OUTPUT3MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT3MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT4MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR +}; + +union OUTPUT4MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT4MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT4MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR +}; + +union OUTPUT4MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT4MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT5MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR +}; + +union OUTPUT5MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT5MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT5MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR +}; + +union OUTPUT5MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT5MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT6MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR +}; + +union OUTPUT6MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT6MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT6MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR +}; + +union OUTPUT6MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT6MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT7MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR +}; + +union OUTPUT7MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT7MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT7MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR +}; + +union OUTPUT7MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT7MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT8MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR +}; + +union OUTPUT8MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT8MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT8MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR +}; + +union OUTPUT8MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT8MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT1MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR +}; + +union OUTPUT1MUXENABLE_REG { + Uint32 all; + struct OUTPUT1MUXENABLE_BITS bit; +}; + +struct OUTPUT2MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR +}; + +union OUTPUT2MUXENABLE_REG { + Uint32 all; + struct OUTPUT2MUXENABLE_BITS bit; +}; + +struct OUTPUT3MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR +}; + +union OUTPUT3MUXENABLE_REG { + Uint32 all; + struct OUTPUT3MUXENABLE_BITS bit; +}; + +struct OUTPUT4MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR +}; + +union OUTPUT4MUXENABLE_REG { + Uint32 all; + struct OUTPUT4MUXENABLE_BITS bit; +}; + +struct OUTPUT5MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR +}; + +union OUTPUT5MUXENABLE_REG { + Uint32 all; + struct OUTPUT5MUXENABLE_BITS bit; +}; + +struct OUTPUT6MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to OUTPUT6 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR +}; + +union OUTPUT6MUXENABLE_REG { + Uint32 all; + struct OUTPUT6MUXENABLE_BITS bit; +}; + +struct OUTPUT7MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR +}; + +union OUTPUT7MUXENABLE_REG { + Uint32 all; + struct OUTPUT7MUXENABLE_BITS bit; +}; + +struct OUTPUT8MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR +}; + +union OUTPUT8MUXENABLE_REG { + Uint32 all; + struct OUTPUT8MUXENABLE_BITS bit; +}; + +struct OUTPUTLATCH_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCH_REG { + Uint32 all; + struct OUTPUTLATCH_BITS bit; +}; + +struct OUTPUTLATCHCLR_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCHCLR_REG { + Uint32 all; + struct OUTPUTLATCHCLR_BITS bit; +}; + +struct OUTPUTLATCHFRC_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCHFRC_REG { + Uint32 all; + struct OUTPUTLATCHFRC_BITS bit; +}; + +struct OUTPUTLATCHENABLE_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCHENABLE_REG { + Uint32 all; + struct OUTPUTLATCHENABLE_BITS bit; +}; + +struct OUTPUTINV_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTINV_REG { + Uint32 all; + struct OUTPUTINV_BITS bit; +}; + +struct OUTPUTLOCK_BITS { // bits description + Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 KEY:16; // 31:16 Write Protection KEY +}; + +union OUTPUTLOCK_REG { + Uint32 all; + struct OUTPUTLOCK_BITS bit; +}; + +struct OUTPUT_XBAR_REGS { + union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1 + union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1 + union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2 + union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2 + union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3 + union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3 + union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4 + union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4 + union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5 + union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5 + union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6 + union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6 + union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7 + union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7 + union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8 + union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8 + union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1 + union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2 + union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3 + union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4 + union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5 + union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6 + union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7 + union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8 + union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch + union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear + union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear + union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable + union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion + Uint16 rsvd1[4]; // Reserved + union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register +}; + +//--------------------------------------------------------------------------- +// OUTPUT_XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_piectrl.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_piectrl.h new file mode 100644 index 00000000000..75f9303244a --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_piectrl.h @@ -0,0 +1,707 @@ +//########################################################################### +// +// FILE: F2837xD_piectrl.h +// +// TITLE: PIECTRL Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_PIECTRL_H__ +#define __F2837xD_PIECTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// PIECTRL Individual Register Bit Definitions: + +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 PIE Enable + Uint16 PIEVECT:15; // 15:1 PIE Vector Address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +struct PIEIER1_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 +}; + +union PIEIER1_REG { + Uint16 all; + struct PIEIER1_BITS bit; +}; + +struct PIEIFR1_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 +}; + +union PIEIFR1_REG { + Uint16 all; + struct PIEIFR1_BITS bit; +}; + +struct PIEIER2_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 +}; + +union PIEIER2_REG { + Uint16 all; + struct PIEIER2_BITS bit; +}; + +struct PIEIFR2_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 +}; + +union PIEIFR2_REG { + Uint16 all; + struct PIEIFR2_BITS bit; +}; + +struct PIEIER3_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 +}; + +union PIEIER3_REG { + Uint16 all; + struct PIEIER3_BITS bit; +}; + +struct PIEIFR3_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 +}; + +union PIEIFR3_REG { + Uint16 all; + struct PIEIFR3_BITS bit; +}; + +struct PIEIER4_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 +}; + +union PIEIER4_REG { + Uint16 all; + struct PIEIER4_BITS bit; +}; + +struct PIEIFR4_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 +}; + +union PIEIFR4_REG { + Uint16 all; + struct PIEIFR4_BITS bit; +}; + +struct PIEIER5_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 +}; + +union PIEIER5_REG { + Uint16 all; + struct PIEIER5_BITS bit; +}; + +struct PIEIFR5_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 +}; + +union PIEIFR5_REG { + Uint16 all; + struct PIEIFR5_BITS bit; +}; + +struct PIEIER6_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 +}; + +union PIEIER6_REG { + Uint16 all; + struct PIEIER6_BITS bit; +}; + +struct PIEIFR6_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 +}; + +union PIEIFR6_REG { + Uint16 all; + struct PIEIFR6_BITS bit; +}; + +struct PIEIER7_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 +}; + +union PIEIER7_REG { + Uint16 all; + struct PIEIER7_BITS bit; +}; + +struct PIEIFR7_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 +}; + +union PIEIFR7_REG { + Uint16 all; + struct PIEIFR7_BITS bit; +}; + +struct PIEIER8_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 +}; + +union PIEIER8_REG { + Uint16 all; + struct PIEIER8_BITS bit; +}; + +struct PIEIFR8_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 +}; + +union PIEIFR8_REG { + Uint16 all; + struct PIEIFR8_BITS bit; +}; + +struct PIEIER9_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 +}; + +union PIEIER9_REG { + Uint16 all; + struct PIEIER9_BITS bit; +}; + +struct PIEIFR9_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 +}; + +union PIEIFR9_REG { + Uint16 all; + struct PIEIFR9_BITS bit; +}; + +struct PIEIER10_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 +}; + +union PIEIER10_REG { + Uint16 all; + struct PIEIER10_BITS bit; +}; + +struct PIEIFR10_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 +}; + +union PIEIFR10_REG { + Uint16 all; + struct PIEIFR10_BITS bit; +}; + +struct PIEIER11_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 +}; + +union PIEIER11_REG { + Uint16 all; + struct PIEIER11_BITS bit; +}; + +struct PIEIFR11_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 +}; + +union PIEIFR11_REG { + Uint16 all; + struct PIEIFR11_BITS bit; +}; + +struct PIEIER12_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 +}; + +union PIEIER12_REG { + Uint16 all; + struct PIEIER12_BITS bit; +}; + +struct PIEIFR12_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 +}; + +union PIEIFR12_REG { + Uint16 all; + struct PIEIFR12_BITS bit; +}; + +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // ePIE Control Register + union PIEACK_REG PIEACK; // Interrupt Acknowledge Register + union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register + union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register + union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register + union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register + union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register + union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register + union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register + union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register + union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register + union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register + union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register + union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register + union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register + union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register + union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register + union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register + union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register + union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register + union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register + union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register + union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register + union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register + union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register + union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register +}; + +//--------------------------------------------------------------------------- +// PIECTRL External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; +#endif +#ifdef CPU2 +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_pievect.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_pievect.h new file mode 100644 index 00000000000..7772256c78b --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_pievect.h @@ -0,0 +1,306 @@ +//########################################################################### +// +// FILE: F2837xD_pievect.h +// +// TITLE: F2837xD Device PIE Vector Table Definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_PIE_VECT_H +#define F2837xD_PIE_VECT_H +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// PIE Interrupt Vector Table Definition: +// Create a user type called PINT (pointer to interrupt): + +typedef __interrupt void (*PINT)(void); + +// Define Vector Table: +struct PIE_VECT_TABLE { + PINT PIE1_RESERVED_INT; // Reserved + PINT PIE2_RESERVED_INT; // Reserved + PINT PIE3_RESERVED_INT; // Reserved + PINT PIE4_RESERVED_INT; // Reserved + PINT PIE5_RESERVED_INT; // Reserved + PINT PIE6_RESERVED_INT; // Reserved + PINT PIE7_RESERVED_INT; // Reserved + PINT PIE8_RESERVED_INT; // Reserved + PINT PIE9_RESERVED_INT; // Reserved + PINT PIE10_RESERVED_INT; // Reserved + PINT PIE11_RESERVED_INT; // Reserved + PINT PIE12_RESERVED_INT; // Reserved + PINT PIE13_RESERVED_INT; // Reserved + PINT TIMER1_INT; // CPU Timer 1 Interrupt + PINT TIMER2_INT; // CPU Timer 2 Interrupt + PINT DATALOG_INT; // Datalogging Interrupt + PINT RTOS_INT; // RTOS Interrupt + PINT EMU_INT; // Emulation Interrupt + PINT NMI_INT; // Non-Maskable Interrupt + PINT ILLEGAL_INT; // Illegal Operation Trap + PINT USER1_INT; // User Defined Trap 1 + PINT USER2_INT; // User Defined Trap 2 + PINT USER3_INT; // User Defined Trap 3 + PINT USER4_INT; // User Defined Trap 4 + PINT USER5_INT; // User Defined Trap 5 + PINT USER6_INT; // User Defined Trap 6 + PINT USER7_INT; // User Defined Trap 7 + PINT USER8_INT; // User Defined Trap 8 + PINT USER9_INT; // User Defined Trap 9 + PINT USER10_INT; // User Defined Trap 10 + PINT USER11_INT; // User Defined Trap 11 + PINT USER12_INT; // User Defined Trap 12 + PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 + PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 + PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 + PINT XINT1_INT; // 1.4 - XINT1 Interrupt + PINT XINT2_INT; // 1.5 - XINT2 Interrupt + PINT ADCD1_INT; // 1.6 - ADCD Interrupt 1 + PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt + PINT WAKE_INT; // 1.8 - Standby and Halt Wakeup Interrupt + PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt + PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt + PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt + PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt + PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt + PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt + PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt + PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt + PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt + PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt + PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt + PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt + PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt + PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt + PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt + PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt + PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt + PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt + PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt + PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt + PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt + PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt + PINT PIE14_RESERVED_INT; // 4.7 - Reserved + PINT PIE15_RESERVED_INT; // 4.8 - Reserved + PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt + PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt + PINT EQEP3_INT; // 5.3 - eQEP3 Interrupt + PINT PIE16_RESERVED_INT; // 5.4 - Reserved + PINT PIE17_RESERVED_INT; // 5.5 - Reserved + PINT PIE18_RESERVED_INT; // 5.6 - Reserved + PINT PIE19_RESERVED_INT; // 5.7 - Reserved + PINT PIE20_RESERVED_INT; // 5.8 - Reserved + PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt + PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt + PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt + PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt + PINT MCBSPA_RX_INT; // 6.5 - McBSPA Receive Interrupt + PINT MCBSPA_TX_INT; // 6.6 - McBSPA Transmit Interrupt + PINT MCBSPB_RX_INT; // 6.7 - McBSPB Receive Interrupt + PINT MCBSPB_TX_INT; // 6.8 - McBSPB Transmit Interrupt + PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt + PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt + PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt + PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt + PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt + PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt + PINT PIE21_RESERVED_INT; // 7.7 - Reserved + PINT PIE22_RESERVED_INT; // 7.8 - Reserved + PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 + PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 + PINT I2CB_INT; // 8.3 - I2CB Interrupt 1 + PINT I2CB_FIFO_INT; // 8.4 - I2CB Interrupt 2 + PINT SCIC_RX_INT; // 8.5 - SCIC Receive Interrupt + PINT SCIC_TX_INT; // 8.6 - SCIC Transmit Interrupt + PINT SCID_RX_INT; // 8.7 - SCID Receive Interrupt + PINT SCID_TX_INT; // 8.8 - SCID Transmit Interrupt + PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt + PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt + PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt + PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt + PINT CANA0_INT; // 9.5 - CANA Interrupt 0 + PINT CANA1_INT; // 9.6 - CANA Interrupt 1 + PINT CANB0_INT; // 9.7 - CANB Interrupt 0 + PINT CANB1_INT; // 9.8 - CANB Interrupt 1 + PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt + PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 + PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 + PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 + PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt + PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 + PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 + PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 + PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 + PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 + PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 + PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 + PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 + PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 + PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 + PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 + PINT XINT3_INT; // 12.1 - XINT3 Interrupt + PINT XINT4_INT; // 12.2 - XINT4 Interrupt + PINT XINT5_INT; // 12.3 - XINT5 Interrupt + PINT PIE23_RESERVED_INT; // 12.4 - Reserved + PINT PIE24_RESERVED_INT; // 12.5 - Reserved + PINT VCU_INT; // 12.6 - VCU Interrupt + PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt + PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt + PINT PIE25_RESERVED_INT; // 1.9 - Reserved + PINT PIE26_RESERVED_INT; // 1.10 - Reserved + PINT PIE27_RESERVED_INT; // 1.11 - Reserved + PINT PIE28_RESERVED_INT; // 1.12 - Reserved + PINT IPC0_INT; // 1.13 - IPC Interrupt 0 + PINT IPC1_INT; // 1.14 - IPC Interrupt 1 + PINT IPC2_INT; // 1.15 - IPC Interrupt 2 + PINT IPC3_INT; // 1.16 - IPC Interrupt 3 + PINT EPWM9_TZ_INT; // 2.9 - ePWM9 Trip Zone Interrupt + PINT EPWM10_TZ_INT; // 2.10 - ePWM10 Trip Zone Interrupt + PINT EPWM11_TZ_INT; // 2.11 - ePWM11 Trip Zone Interrupt + PINT EPWM12_TZ_INT; // 2.12 - ePWM12 Trip Zone Interrupt + PINT PIE29_RESERVED_INT; // 2.13 - Reserved + PINT PIE30_RESERVED_INT; // 2.14 - Reserved + PINT PIE31_RESERVED_INT; // 2.15 - Reserved + PINT PIE32_RESERVED_INT; // 2.16 - Reserved + PINT EPWM9_INT; // 3.9 - ePWM9 Interrupt + PINT EPWM10_INT; // 3.10 - ePWM10 Interrupt + PINT EPWM11_INT; // 3.11 - ePWM11 Interrupt + PINT EPWM12_INT; // 3.12 - ePWM12 Interrupt + PINT PIE33_RESERVED_INT; // 3.13 - Reserved + PINT PIE34_RESERVED_INT; // 3.14 - Reserved + PINT PIE35_RESERVED_INT; // 3.15 - Reserved + PINT PIE36_RESERVED_INT; // 3.16 - Reserved + PINT PIE37_RESERVED_INT; // 4.9 - Reserved + PINT PIE38_RESERVED_INT; // 4.10 - Reserved + PINT PIE39_RESERVED_INT; // 4.11 - Reserved + PINT PIE40_RESERVED_INT; // 4.12 - Reserved + PINT PIE41_RESERVED_INT; // 4.13 - Reserved + PINT PIE42_RESERVED_INT; // 4.14 - Reserved + PINT PIE43_RESERVED_INT; // 4.15 - Reserved + PINT PIE44_RESERVED_INT; // 4.16 - Reserved + PINT SD1_INT; // 5.9 - SD1 Interrupt + PINT SD2_INT; // 5.10 - SD2 Interrupt + PINT PIE45_RESERVED_INT; // 5.11 - Reserved + PINT PIE46_RESERVED_INT; // 5.12 - Reserved + PINT PIE47_RESERVED_INT; // 5.13 - Reserved + PINT PIE48_RESERVED_INT; // 5.14 - Reserved + PINT PIE49_RESERVED_INT; // 5.15 - Reserved + PINT PIE50_RESERVED_INT; // 5.16 - Reserved + PINT SPIC_RX_INT; // 6.9 - SPIC Receive Interrupt + PINT SPIC_TX_INT; // 6.10 - SPIC Transmit Interrupt + PINT PIE51_RESERVED_INT; // 6.11 - Reserved + PINT PIE52_RESERVED_INT; // 6.12 - Reserved + PINT PIE53_RESERVED_INT; // 6.13 - Reserved + PINT PIE54_RESERVED_INT; // 6.14 - Reserved + PINT PIE55_RESERVED_INT; // 6.15 - Reserved + PINT PIE56_RESERVED_INT; // 6.16 - Reserved + PINT PIE57_RESERVED_INT; // 7.9 - Reserved + PINT PIE58_RESERVED_INT; // 7.10 - Reserved + PINT PIE59_RESERVED_INT; // 7.11 - Reserved + PINT PIE60_RESERVED_INT; // 7.12 - Reserved + PINT PIE61_RESERVED_INT; // 7.13 - Reserved + PINT PIE62_RESERVED_INT; // 7.14 - Reserved + PINT PIE63_RESERVED_INT; // 7.15 - Reserved + PINT PIE64_RESERVED_INT; // 7.16 - Reserved + PINT PIE65_RESERVED_INT; // 8.9 - Reserved + PINT PIE66_RESERVED_INT; // 8.10 - Reserved + PINT PIE67_RESERVED_INT; // 8.11 - Reserved + PINT PIE68_RESERVED_INT; // 8.12 - Reserved + PINT PIE69_RESERVED_INT; // 8.13 - Reserved + PINT PIE70_RESERVED_INT; // 8.14 - Reserved +#ifdef CPU1 + PINT UPPA_INT; // 8.15 - uPPA Interrupt + PINT PIE72_RESERVED_INT; // 8.16 - Reserved +#elif defined(CPU2) + PINT PIE71_RESERVED_INT; // 8.15 - Reserved + PINT PIE72_RESERVED_INT; // 8.16 - Reserved +#endif + PINT PIE73_RESERVED_INT; // 9.9 - Reserved + PINT PIE74_RESERVED_INT; // 9.10 - Reserved + PINT PIE75_RESERVED_INT; // 9.11 - Reserved + PINT PIE76_RESERVED_INT; // 9.12 - Reserved + PINT PIE77_RESERVED_INT; // 9.13 - Reserved + PINT PIE78_RESERVED_INT; // 9.14 - Reserved +#ifdef CPU1 + PINT USBA_INT; // 9.15 - USBA Interrupt +#elif defined(CPU2) + PINT PIE79_RESERVED_INT; // 9.15 - Reserved +#endif + PINT PIE80_RESERVED_INT; // 9.16 - Reserved + PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt + PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 + PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 + PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 + PINT ADCD_EVT_INT; // 10.13 - ADCD Event Interrupt + PINT ADCD2_INT; // 10.14 - ADCD Interrupt 2 + PINT ADCD3_INT; // 10.15 - ADCD Interrupt 3 + PINT ADCD4_INT; // 10.16 - ADCD Interrupt 4 + PINT PIE81_RESERVED_INT; // 11.9 - Reserved + PINT PIE82_RESERVED_INT; // 11.10 - Reserved + PINT PIE83_RESERVED_INT; // 11.11 - Reserved + PINT PIE84_RESERVED_INT; // 11.12 - Reserved + PINT PIE85_RESERVED_INT; // 11.13 - Reserved + PINT PIE86_RESERVED_INT; // 11.14 - Reserved + PINT PIE87_RESERVED_INT; // 11.15 - Reserved + PINT PIE88_RESERVED_INT; // 11.16 - Reserved + PINT EMIF_ERROR_INT; // 12.9 - EMIF Error Interrupt + PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt + PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt + PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt + PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt + PINT AUX_PLL_SLIP_INT; // 12.14 - Auxiliary PLL Slip Interrupt + PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt + PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt +}; + +//--------------------------------------------------------------------------- +// PieVect External References & Function Declarations: +// + +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of F2837xD_PIEVECT_H definition +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_sci.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sci.h new file mode 100644 index 00000000000..ae1cf3c422c --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sci.h @@ -0,0 +1,266 @@ +//########################################################################### +// +// FILE: F2837xD_sci.h +// +// TITLE: SCI Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SCI_H__ +#define __F2837xD_SCI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SCI Individual Register Bit Definitions: + +struct SCICCR_BITS { // bits description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +struct SCICTL1_BITS { // bits description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd1:1; // 4 Reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve __interrupt enable + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +struct SCIHBAUD_BITS { // bits description + Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCIHBAUD_REG { + Uint16 all; + struct SCIHBAUD_BITS bit; +}; + +struct SCILBAUD_BITS { // bits description + Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCILBAUD_REG { + Uint16 all; + struct SCILBAUD_BITS bit; +}; + +struct SCICTL2_BITS { // bits description + Uint16 TXINTENA:1; // 0 Transmit __interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd1:4; // 5:2 Reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +struct SCIRXST_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +struct SCIRXEMU_BITS { // bits description + Uint16 ERXDT:8; // 7:0 Receive emulation buffer data + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCIRXEMU_REG { + Uint16 all; + struct SCIRXEMU_BITS bit; +}; + +struct SCIRXBUF_BITS { // bits description + Uint16 SAR:8; // 7:0 Receive Character bits + Uint16 rsvd1:6; // 13:8 Reserved + Uint16 SCIFFPE:1; // 14 Receiver error flag + Uint16 SCIFFFE:1; // 15 Receiver error flag +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +struct SCITXBUF_BITS { // bits description + Uint16 TXDT:8; // 7:0 Transmit data buffer + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCITXBUF_REG { + Uint16 all; + struct SCITXBUF_BITS bit; +}; + +struct SCIFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFORESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd1:5; // 12:8 Reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +struct SCIPRI_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 FREESOFT:2; // 4:3 Emulation modes + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 rsvd3:8; // 15:8 Reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register + union SCILBAUD_REG SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + union SCIRXEMU_REG SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // Reserved + union SCITXBUF_REG SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2[2]; // Reserved + union SCIPRI_REG SCIPRI; // SCI Priority control +}; + +//--------------------------------------------------------------------------- +// SCI External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; +extern volatile struct SCI_REGS ScidRegs; +#endif +#ifdef CPU2 +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; +extern volatile struct SCI_REGS ScidRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_sdfm.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sdfm.h new file mode 100644 index 00000000000..75061150735 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sdfm.h @@ -0,0 +1,534 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm.h +// +// TITLE: SDFM Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SDFM_H__ +#define __F2837xD_SDFM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SDFM Individual Register Bit Definitions: + +struct SDIFLG_BITS { // bits description + Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 + Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 + Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 + Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 + Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 + Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 + Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 + Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 + Uint16 MF1:1; // 8 Modulator Failure for Filter 1 + Uint16 MF2:1; // 9 Modulator Failure for Filter 2 + Uint16 MF3:1; // 10 Modulator Failure for Filter 3 + Uint16 MF4:1; // 11 Modulator Failure for Filter 4 + Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 + Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 + Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 + Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 + Uint16 rsvd1:15; // 30:16 Reserved + Uint16 MIF:1; // 31 Master Interrupt Flag +}; + +union SDIFLG_REG { + Uint32 all; + struct SDIFLG_BITS bit; +}; + +struct SDIFLGCLR_BITS { // bits description + Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 + Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 + Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 + Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 + Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 + Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 + Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 + Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 + Uint16 MF1:1; // 8 Modulator Failure for Filter 1 + Uint16 MF2:1; // 9 Modulator Failure for Filter 2 + Uint16 MF3:1; // 10 Modulator Failure for Filter 3 + Uint16 MF4:1; // 11 Modulator Failure for Filter 4 + Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 + Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 + Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 + Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 + Uint16 rsvd1:15; // 30:16 Reserved + Uint16 MIF:1; // 31 Master Interrupt Flag +}; + +union SDIFLGCLR_REG { + Uint32 all; + struct SDIFLGCLR_BITS bit; +}; + +struct SDCTL_BITS { // bits description + Uint16 rsvd1:13; // 12:0 Reserved + Uint16 MIE:1; // 13 Master Interrupt enable + Uint16 rsvd2:1; // 14 Reserved + Uint16 rsvd3:1; // 15 Reserved +}; + +union SDCTL_REG { + Uint16 all; + struct SDCTL_BITS bit; +}; + +struct SDMFILEN_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 rsvd2:3; // 6:4 Reserved + Uint16 rsvd3:2; // 8:7 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 rsvd5:1; // 10 Reserved + Uint16 MFE:1; // 11 Master Filter Enable. + Uint16 rsvd6:1; // 12 Reserved + Uint16 rsvd7:3; // 15:13 Reserved +}; + +union SDMFILEN_REG { + Uint16 all; + struct SDMFILEN_BITS bit; +}; + +struct SDCTLPARM1_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM1_REG { + Uint16 all; + struct SDCTLPARM1_BITS bit; +}; + +struct SDDFPARM1_BITS { // bits description + Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data Filter Structure (DataFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM1_REG { + Uint16 all; + struct SDDFPARM1_BITS bit; +}; + +struct SDDPARM1_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM1_REG { + Uint16 all; + struct SDDPARM1_BITS bit; +}; + +struct SDCMPH1_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH1_REG { + Uint16 all; + struct SDCMPH1_BITS bit; +}; + +struct SDCMPL1_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL1_REG { + Uint16 all; + struct SDCMPL1_BITS bit; +}; + +struct SDCPARM1_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM1_REG { + Uint16 all; + struct SDCPARM1_BITS bit; +}; + +struct SDDATA1_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA1_REG { + Uint32 all; + struct SDDATA1_BITS bit; +}; + +struct SDCTLPARM2_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM2_REG { + Uint16 all; + struct SDCTLPARM2_BITS bit; +}; + +struct SDDFPARM2_BITS { // bits description + Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data Filter Structure (SincFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM2_REG { + Uint16 all; + struct SDDFPARM2_BITS bit; +}; + +struct SDDPARM2_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM2_REG { + Uint16 all; + struct SDDPARM2_BITS bit; +}; + +struct SDCMPH2_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH2_REG { + Uint16 all; + struct SDCMPH2_BITS bit; +}; + +struct SDCMPL2_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL2_REG { + Uint16 all; + struct SDCMPL2_BITS bit; +}; + +struct SDCPARM2_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM2_REG { + Uint16 all; + struct SDCPARM2_BITS bit; +}; + +struct SDDATA2_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA2_REG { + Uint32 all; + struct SDDATA2_BITS bit; +}; + +struct SDCTLPARM3_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM3_REG { + Uint16 all; + struct SDCTLPARM3_BITS bit; +}; + +struct SDDFPARM3_BITS { // bits description + Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM3_REG { + Uint16 all; + struct SDDFPARM3_BITS bit; +}; + +struct SDDPARM3_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM3_REG { + Uint16 all; + struct SDDPARM3_BITS bit; +}; + +struct SDCMPH3_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH3_REG { + Uint16 all; + struct SDCMPH3_BITS bit; +}; + +struct SDCMPL3_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL3_REG { + Uint16 all; + struct SDCMPL3_BITS bit; +}; + +struct SDCPARM3_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM3_REG { + Uint16 all; + struct SDCPARM3_BITS bit; +}; + +struct SDDATA3_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA3_REG { + Uint32 all; + struct SDDATA3_BITS bit; +}; + +struct SDCTLPARM4_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM4_REG { + Uint16 all; + struct SDCTLPARM4_BITS bit; +}; + +struct SDDFPARM4_BITS { // bits description + Uint16 DOSR:8; // 7:0 SINC Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 SINC FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM4_REG { + Uint16 all; + struct SDDFPARM4_BITS bit; +}; + +struct SDDPARM4_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM4_REG { + Uint16 all; + struct SDDPARM4_BITS bit; +}; + +struct SDCMPH4_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH4_REG { + Uint16 all; + struct SDCMPH4_BITS bit; +}; + +struct SDCMPL4_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL4_REG { + Uint16 all; + struct SDCMPL4_BITS bit; +}; + +struct SDCPARM4_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM4_REG { + Uint16 all; + struct SDCPARM4_BITS bit; +}; + +struct SDDATA4_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA4_REG { + Uint32 all; + struct SDDATA4_BITS bit; +}; + +struct SDFM_REGS { + union SDIFLG_REG SDIFLG; // Interrupt Flag Register + union SDIFLGCLR_REG SDIFLGCLR; // Interrupt Flag Clear Register + union SDCTL_REG SDCTL; // SD Control Register + Uint16 rsvd1; // Reserved + union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable + Uint16 rsvd2[9]; // Reserved + union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 + union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 + union SDDPARM1_REG SDDPARM1; // Integer Parameter Register for Ch1 + union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1 + union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1 + union SDCPARM1_REG SDCPARM1; // Comparator Parameter Register for Ch1 + union SDDATA1_REG SDDATA1; // Filter Data Register (16 or 32bit) for Ch1 + Uint16 rsvd3[8]; // Reserved + union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 + union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 + union SDDPARM2_REG SDDPARM2; // Integer Parameter Register for Ch2 + union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2 + union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2 + union SDCPARM2_REG SDCPARM2; // Comparator Parameter Register for Ch2 + union SDDATA2_REG SDDATA2; // Filter Data Register (16 or 32bit) for Ch2 + Uint16 rsvd4[8]; // Reserved + union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 + union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 + union SDDPARM3_REG SDDPARM3; // Integer Parameter Register for Ch3 + union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3 + union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3 + union SDCPARM3_REG SDCPARM3; // Comparator Parameter Register for Ch3 + union SDDATA3_REG SDDATA3; // Filter Data Register (16 or 32bit) for Ch3 + Uint16 rsvd5[8]; // Reserved + union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 + union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 + union SDDPARM4_REG SDDPARM4; // Integer Parameter Register for Ch4 + union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4 + union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4 + union SDCPARM4_REG SDCPARM4; // Comparator Parameter Register for Ch4 + union SDDATA4_REG SDDATA4; // Filter Data Register (16 or 32bit) for Ch4 + Uint16 rsvd6[56]; // Reserved +}; + +//--------------------------------------------------------------------------- +// SDFM External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct SDFM_REGS Sdfm1Regs; +extern volatile struct SDFM_REGS Sdfm2Regs; +#endif +#ifdef CPU2 +extern volatile struct SDFM_REGS Sdfm1Regs; +extern volatile struct SDFM_REGS Sdfm2Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_spi.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_spi.h new file mode 100644 index 00000000000..30e2e6babb8 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_spi.h @@ -0,0 +1,201 @@ +//########################################################################### +// +// FILE: F2837xD_spi.h +// +// TITLE: SPI Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SPI_H__ +#define __F2837xD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SPI Individual Register Bit Definitions: + +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character Length Control + Uint16 SPILBK:1; // 4 SPI Loopback + Uint16 HS_MODE:1; // 5 High Speed mode control + Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity + Uint16 SPISWRESET:1; // 7 SPI Software Reset + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 SPI Interupt Enable + Uint16 TALK:1; // 1 Master/Slave Transmit Enable + Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control + Uint16 CLK_PHASE:1; // 3 SPI Clock Phase + Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable + Uint16 rsvd1:11; // 15:5 Reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag + Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag + Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +struct SPIBRR_BITS { // bits description + Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control + Uint16 rsvd1:9; // 15:7 Reserved +}; + +union SPIBRR_REG { + Uint16 all; + struct SPIBRR_BITS bit; +}; + +struct SPIFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level + Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable + Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear + Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag + Uint16 TXFFST:5; // 12:8 Transmit FIFO Status + Uint16 TXFIFO:1; // 13 TXFIFO Reset + Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable + Uint16 SPIRST:1; // 15 SPI Reset +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level + Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable + Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear + Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag + Uint16 RXFFST:5; // 12:8 Receive FIFO Status + Uint16 RXFIFORESET:1; // 13 RXFIFO Reset + Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear + Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +struct SPIPRI_BITS { // bits description + Uint16 TRIWIRE:1; // 0 3-wire mode select bit + Uint16 STEINV:1; // 1 SPISTE inversion bit + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 FREE:1; // 4 Free emulation mode + Uint16 SOFT:1; // 5 Soft emulation mode + Uint16 rsvd2:1; // 6 Reserved + Uint16 rsvd3:9; // 15:7 Reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +struct SPI_REGS { + union SPICCR_REG SPICCR; // SPI Configuration Control Register + union SPICTL_REG SPICTL; // SPI Operation Control Register + union SPISTS_REG SPISTS; // SPI Status Register + Uint16 rsvd1; // Reserved + union SPIBRR_REG SPIBRR; // SPI Baud Rate Register + Uint16 rsvd2; // Reserved + Uint16 SPIRXEMU; // SPI Emulation Buffer Register + Uint16 SPIRXBUF; // SPI Serial Input Buffer Register + Uint16 SPITXBUF; // SPI Serial Output Buffer Register + Uint16 SPIDAT; // SPI Serial Data Register + union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register + union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register + union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register + Uint16 rsvd3[2]; // Reserved + union SPIPRI_REG SPIPRI; // SPI Priority Control Register +}; + +//--------------------------------------------------------------------------- +// SPI External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct SPI_REGS SpiaRegs; +extern volatile struct SPI_REGS SpibRegs; +extern volatile struct SPI_REGS SpicRegs; +#endif +#ifdef CPU2 +extern volatile struct SPI_REGS SpiaRegs; +extern volatile struct SPI_REGS SpibRegs; +extern volatile struct SPI_REGS SpicRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_sysctrl.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sysctrl.h new file mode 100644 index 00000000000..dd438aed5f1 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_sysctrl.h @@ -0,0 +1,1964 @@ +//########################################################################### +// +// FILE: F2837xD_sysctrl.h +// +// TITLE: SYSCTRL Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SYSCTRL_H__ +#define __F2837xD_SYSCTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SYSCTRL Individual Register Bit Definitions: + +struct DEVCFGLOCK1_BITS { // bits description + Uint16 CPUSEL0:1; // 0 Lock bit for CPUSEL0 register + Uint16 CPUSEL1:1; // 1 Lock bit for CPUSEL1 register + Uint16 CPUSEL2:1; // 2 Lock bit for CPUSEL2 register + Uint16 CPUSEL3:1; // 3 Lock bit for CPUSEL3 register + Uint16 CPUSEL4:1; // 4 Lock bit for CPUSEL4 register + Uint16 CPUSEL5:1; // 5 Lock bit for CPUSEL5 register + Uint16 CPUSEL6:1; // 6 Lock bit for CPUSEL6 register + Uint16 CPUSEL7:1; // 7 Lock bit for CPUSEL7 register + Uint16 CPUSEL8:1; // 8 Lock bit for CPUSEL8 register + Uint16 CPUSEL9:1; // 9 Lock bit for CPUSEL9 register + Uint16 CPUSEL10:1; // 10 Lock bit for CPUSEL10 register + Uint16 CPUSEL11:1; // 11 Lock bit for CPUSEL11 register + Uint16 CPUSEL12:1; // 12 Lock bit for CPUSEL12 register + Uint16 CPUSEL13:1; // 13 Lock bit for CPUSEL13 register + Uint16 CPUSEL14:1; // 14 Lock bit for CPUSEL14 register + Uint16 rsvd1:1; // 15 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DEVCFGLOCK1_REG { + Uint32 all; + struct DEVCFGLOCK1_BITS bit; +}; + +struct PARTIDL_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 rsvd2:2; // 4:3 Reserved + Uint16 rsvd3:1; // 5 Reserved + Uint16 QUAL:2; // 7:6 Qualification Status + Uint16 PIN_COUNT:3; // 10:8 Device Pin Count + Uint16 rsvd4:1; // 11 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 INSTASPIN:2; // 14:13 Motorware feature set + Uint16 rsvd6:1; // 15 Reserved + Uint16 FLASH_SIZE:8; // 23:16 Flash size in KB + Uint16 rsvd7:4; // 27:24 Reserved + Uint16 PARTID_FORMAT_REVISION:4; // 31:28 Revision of the PARTID format +}; + +union PARTIDL_REG { + Uint32 all; + struct PARTIDL_BITS bit; +}; + +struct PARTIDH_BITS { // bits description + Uint16 rsvd1:8; // 7:0 Reserved + Uint16 FAMILY:8; // 15:8 Device family + Uint16 PARTNO:8; // 23:16 Device part number + Uint16 DEVICE_CLASS_ID:8; // 31:24 Device class ID +}; + +union PARTIDH_REG { + Uint32 all; + struct PARTIDH_BITS bit; +}; + +struct DC0_BITS { // bits description + Uint16 SINGLE_CORE:1; // 0 Single Core vs Dual Core + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC0_REG { + Uint32 all; + struct DC0_BITS bit; +}; + +struct DC1_BITS { // bits description + Uint16 CPU1_FPU_TMU:1; // 0 CPU1's FPU1+TMU1 + Uint16 CPU2_FPU_TMU:1; // 1 CPU2's FPU2+TMU2 + Uint16 CPU1_VCU:1; // 2 CPU1's VCU + Uint16 CPU2_VCU:1; // 3 CPU2's VCU + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 CPU1_CLA1:1; // 6 CPU1.CLA1 + Uint16 rsvd2:1; // 7 Reserved + Uint16 CPU2_CLA1:1; // 8 CPU2.CLA1 + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union DC1_REG { + Uint32 all; + struct DC1_BITS bit; +}; + +struct DC2_BITS { // bits description + Uint16 EMIF1:1; // 0 EMIF1 + Uint16 EMIF2:1; // 1 EMIF2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC2_REG { + Uint32 all; + struct DC2_BITS bit; +}; + +struct DC3_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 + Uint16 EPWM2:1; // 1 EPWM2 + Uint16 EPWM3:1; // 2 EPWM3 + Uint16 EPWM4:1; // 3 EPWM4 + Uint16 EPWM5:1; // 4 EPWM5 + Uint16 EPWM6:1; // 5 EPWM6 + Uint16 EPWM7:1; // 6 EPWM7 + Uint16 EPWM8:1; // 7 EPWM8 + Uint16 EPWM9:1; // 8 EPWM9 + Uint16 EPWM10:1; // 9 EPWM10 + Uint16 EPWM11:1; // 10 EPWM11 + Uint16 EPWM12:1; // 11 EPWM12 + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union DC3_REG { + Uint32 all; + struct DC3_BITS bit; +}; + +struct DC4_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 + Uint16 ECAP2:1; // 1 ECAP2 + Uint16 ECAP3:1; // 2 ECAP3 + Uint16 ECAP4:1; // 3 ECAP4 + Uint16 ECAP5:1; // 4 ECAP5 + Uint16 ECAP6:1; // 5 ECAP6 + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union DC4_REG { + Uint32 all; + struct DC4_BITS bit; +}; + +struct DC5_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 + Uint16 EQEP2:1; // 1 EQEP2 + Uint16 EQEP3:1; // 2 EQEP3 + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DC5_REG { + Uint32 all; + struct DC5_BITS bit; +}; + +struct DC6_BITS { // bits description + Uint16 CLB1:1; // 0 CLB1 + Uint16 CLB2:1; // 1 CLB2 + Uint16 CLB3:1; // 2 CLB3 + Uint16 CLB4:1; // 3 CLB4 + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:1; // 5 Reserved + Uint16 rsvd3:1; // 6 Reserved + Uint16 rsvd4:1; // 7 Reserved + Uint16 rsvd5:8; // 15:8 Reserved + Uint16 rsvd6:16; // 31:16 Reserved +}; + +union DC6_REG { + Uint32 all; + struct DC6_BITS bit; +}; + +struct DC7_BITS { // bits description + Uint16 SD1:1; // 0 SD1 + Uint16 SD2:1; // 1 SD2 + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union DC7_REG { + Uint32 all; + struct DC7_BITS bit; +}; + +struct DC8_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A + Uint16 SCI_B:1; // 1 SCI_B + Uint16 SCI_C:1; // 2 SCI_C + Uint16 SCI_D:1; // 3 SCI_D + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC8_REG { + Uint32 all; + struct DC8_BITS bit; +}; + +struct DC9_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A + Uint16 SPI_B:1; // 1 SPI_B + Uint16 SPI_C:1; // 2 SPI_C + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union DC9_REG { + Uint32 all; + struct DC9_BITS bit; +}; + +struct DC10_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A + Uint16 I2C_B:1; // 1 I2C_B + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union DC10_REG { + Uint32 all; + struct DC10_BITS bit; +}; + +struct DC11_BITS { // bits description + Uint16 CAN_A:1; // 0 CAN_A + Uint16 CAN_B:1; // 1 CAN_B + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union DC11_REG { + Uint32 all; + struct DC11_BITS bit; +}; + +struct DC12_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A + Uint16 McBSP_B:1; // 1 McBSP_B + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 USB_A:2; // 17:16 Decides the capability of the USB_A Module + Uint16 rsvd2:2; // 19:18 Reserved + Uint16 rsvd3:12; // 31:20 Reserved +}; + +union DC12_REG { + Uint32 all; + struct DC12_BITS bit; +}; + +struct DC13_BITS { // bits description + Uint16 uPP_A:1; // 0 uPP_A + Uint16 rsvd1:1; // 1 Reserved + Uint16 rsvd2:14; // 15:2 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DC13_REG { + Uint32 all; + struct DC13_BITS bit; +}; + +struct DC14_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A + Uint16 ADC_B:1; // 1 ADC_B + Uint16 ADC_C:1; // 2 ADC_C + Uint16 ADC_D:1; // 3 ADC_D + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC14_REG { + Uint32 all; + struct DC14_BITS bit; +}; + +struct DC15_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 + Uint16 CMPSS2:1; // 1 CMPSS2 + Uint16 CMPSS3:1; // 2 CMPSS3 + Uint16 CMPSS4:1; // 3 CMPSS4 + Uint16 CMPSS5:1; // 4 CMPSS5 + Uint16 CMPSS6:1; // 5 CMPSS6 + Uint16 CMPSS7:1; // 6 CMPSS7 + Uint16 CMPSS8:1; // 7 CMPSS8 + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC15_REG { + Uint32 all; + struct DC15_BITS bit; +}; + +struct DC17_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered-DAC_A + Uint16 DAC_B:1; // 17 Buffered-DAC_B + Uint16 DAC_C:1; // 18 Buffered-DAC_C + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union DC17_REG { + Uint32 all; + struct DC17_BITS bit; +}; + +struct DC18_BITS { // bits description + Uint16 LS0_1:1; // 0 LS0_1 + Uint16 LS1_1:1; // 1 LS1_1 + Uint16 LS2_1:1; // 2 LS2_1 + Uint16 LS3_1:1; // 3 LS3_1 + Uint16 LS4_1:1; // 4 LS4_1 + Uint16 LS5_1:1; // 5 LS5_1 + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC18_REG { + Uint32 all; + struct DC18_BITS bit; +}; + +struct DC19_BITS { // bits description + Uint16 LS0_2:1; // 0 LS0_2 + Uint16 LS1_2:1; // 1 LS1_2 + Uint16 LS2_2:1; // 2 LS2_2 + Uint16 LS3_2:1; // 3 LS3_2 + Uint16 LS4_2:1; // 4 LS4_2 + Uint16 LS5_2:1; // 5 LS5_2 + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC19_REG { + Uint32 all; + struct DC19_BITS bit; +}; + +struct DC20_BITS { // bits description + Uint16 GS0:1; // 0 GS0 + Uint16 GS1:1; // 1 GS1 + Uint16 GS2:1; // 2 GS2 + Uint16 GS3:1; // 3 GS3 + Uint16 GS4:1; // 4 GS4 + Uint16 GS5:1; // 5 GS5 + Uint16 GS6:1; // 6 GS6 + Uint16 GS7:1; // 7 GS7 + Uint16 GS8:1; // 8 GS8 + Uint16 GS9:1; // 9 GS9 + Uint16 GS10:1; // 10 GS10 + Uint16 GS11:1; // 11 GS11 + Uint16 GS12:1; // 12 GS12 + Uint16 GS13:1; // 13 GS13 + Uint16 GS14:1; // 14 GS14 + Uint16 GS15:1; // 15 GS15 + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union DC20_REG { + Uint32 all; + struct DC20_BITS bit; +}; + +struct PERCNF1_BITS { // bits description + Uint16 ADC_A_MODE:1; // 0 ADC_A mode setting bit + Uint16 ADC_B_MODE:1; // 1 ADC_B mode setting bit + Uint16 ADC_C_MODE:1; // 2 ADC_C mode setting bit + Uint16 ADC_D_MODE:1; // 3 ADC_D mode setting bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 USB_A_PHY:1; // 16 USB_A_PHY + Uint16 rsvd2:1; // 17 Reserved + Uint16 rsvd3:14; // 31:18 Reserved +}; + +union PERCNF1_REG { + Uint32 all; + struct PERCNF1_BITS bit; +}; + +struct FUSEERR_BITS { // bits description + Uint16 ALERR:5; // 4:0 Efuse Autoload Error Status + Uint16 ERR:1; // 5 Efuse Self Test Error Status + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FUSEERR_REG { + Uint32 all; + struct FUSEERR_BITS bit; +}; + +struct SOFTPRES0_BITS { // bits description + Uint16 CPU1_CLA1:1; // 0 CPU1_CLA1 software reset bit + Uint16 rsvd1:1; // 1 Reserved + Uint16 CPU2_CLA1:1; // 2 CPU2_CLA1 software reset bit + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union SOFTPRES0_REG { + Uint32 all; + struct SOFTPRES0_BITS bit; +}; + +struct SOFTPRES1_BITS { // bits description + Uint16 EMIF1:1; // 0 EMIF1 software reset bit + Uint16 EMIF2:1; // 1 EMIF2 software reset bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES1_REG { + Uint32 all; + struct SOFTPRES1_BITS bit; +}; + +struct SOFTPRES2_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 software reset bit + Uint16 EPWM2:1; // 1 EPWM2 software reset bit + Uint16 EPWM3:1; // 2 EPWM3 software reset bit + Uint16 EPWM4:1; // 3 EPWM4 software reset bit + Uint16 EPWM5:1; // 4 EPWM5 software reset bit + Uint16 EPWM6:1; // 5 EPWM6 software reset bit + Uint16 EPWM7:1; // 6 EPWM7 software reset bit + Uint16 EPWM8:1; // 7 EPWM8 software reset bit + Uint16 EPWM9:1; // 8 EPWM9 software reset bit + Uint16 EPWM10:1; // 9 EPWM10 software reset bit + Uint16 EPWM11:1; // 10 EPWM11 software reset bit + Uint16 EPWM12:1; // 11 EPWM12 software reset bit + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union SOFTPRES2_REG { + Uint32 all; + struct SOFTPRES2_BITS bit; +}; + +struct SOFTPRES3_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 software reset bit + Uint16 ECAP2:1; // 1 ECAP2 software reset bit + Uint16 ECAP3:1; // 2 ECAP3 software reset bit + Uint16 ECAP4:1; // 3 ECAP4 software reset bit + Uint16 ECAP5:1; // 4 ECAP5 software reset bit + Uint16 ECAP6:1; // 5 ECAP6 software reset bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union SOFTPRES3_REG { + Uint32 all; + struct SOFTPRES3_BITS bit; +}; + +struct SOFTPRES4_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 software reset bit + Uint16 EQEP2:1; // 1 EQEP2 software reset bit + Uint16 EQEP3:1; // 2 EQEP3 software reset bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union SOFTPRES4_REG { + Uint32 all; + struct SOFTPRES4_BITS bit; +}; + +struct SOFTPRES6_BITS { // bits description + Uint16 SD1:1; // 0 SD1 software reset bit + Uint16 SD2:1; // 1 SD2 software reset bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union SOFTPRES6_REG { + Uint32 all; + struct SOFTPRES6_BITS bit; +}; + +struct SOFTPRES7_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A software reset bit + Uint16 SCI_B:1; // 1 SCI_B software reset bit + Uint16 SCI_C:1; // 2 SCI_C software reset bit + Uint16 SCI_D:1; // 3 SCI_D software reset bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES7_REG { + Uint32 all; + struct SOFTPRES7_BITS bit; +}; + +struct SOFTPRES8_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A software reset bit + Uint16 SPI_B:1; // 1 SPI_B software reset bit + Uint16 SPI_C:1; // 2 SPI_C software reset bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union SOFTPRES8_REG { + Uint32 all; + struct SOFTPRES8_BITS bit; +}; + +struct SOFTPRES9_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A software reset bit + Uint16 I2C_B:1; // 1 I2C_B software reset bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union SOFTPRES9_REG { + Uint32 all; + struct SOFTPRES9_BITS bit; +}; + +struct SOFTPRES11_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A software reset bit + Uint16 McBSP_B:1; // 1 McBSP_B software reset bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 USB_A:1; // 16 USB_A software reset bit + Uint16 rsvd2:1; // 17 Reserved + Uint16 rsvd3:14; // 31:18 Reserved +}; + +union SOFTPRES11_REG { + Uint32 all; + struct SOFTPRES11_BITS bit; +}; + +struct SOFTPRES13_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A software reset bit + Uint16 ADC_B:1; // 1 ADC_B software reset bit + Uint16 ADC_C:1; // 2 ADC_C software reset bit + Uint16 ADC_D:1; // 3 ADC_D software reset bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES13_REG { + Uint32 all; + struct SOFTPRES13_BITS bit; +}; + +struct SOFTPRES14_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 software reset bit + Uint16 CMPSS2:1; // 1 CMPSS2 software reset bit + Uint16 CMPSS3:1; // 2 CMPSS3 software reset bit + Uint16 CMPSS4:1; // 3 CMPSS4 software reset bit + Uint16 CMPSS5:1; // 4 CMPSS5 software reset bit + Uint16 CMPSS6:1; // 5 CMPSS6 software reset bit + Uint16 CMPSS7:1; // 6 CMPSS7 software reset bit + Uint16 CMPSS8:1; // 7 CMPSS8 software reset bit + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES14_REG { + Uint32 all; + struct SOFTPRES14_BITS bit; +}; + +struct SOFTPRES16_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered_DAC_A software reset bit + Uint16 DAC_B:1; // 17 Buffered_DAC_B software reset bit + Uint16 DAC_C:1; // 18 Buffered_DAC_C software reset bit + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union SOFTPRES16_REG { + Uint32 all; + struct SOFTPRES16_BITS bit; +}; + +struct CPUSEL0_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 CPU select bit + Uint16 EPWM2:1; // 1 EPWM2 CPU select bit + Uint16 EPWM3:1; // 2 EPWM3 CPU select bit + Uint16 EPWM4:1; // 3 EPWM4 CPU select bit + Uint16 EPWM5:1; // 4 EPWM5 CPU select bit + Uint16 EPWM6:1; // 5 EPWM6 CPU select bit + Uint16 EPWM7:1; // 6 EPWM7 CPU select bit + Uint16 EPWM8:1; // 7 EPWM8 CPU select bit + Uint16 EPWM9:1; // 8 EPWM9 CPU select bit + Uint16 EPWM10:1; // 9 EPWM10 CPU select bit + Uint16 EPWM11:1; // 10 EPWM11 CPU select bit + Uint16 EPWM12:1; // 11 EPWM12 CPU select bit + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union CPUSEL0_REG { + Uint32 all; + struct CPUSEL0_BITS bit; +}; + +struct CPUSEL1_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 CPU select bit + Uint16 ECAP2:1; // 1 ECAP2 CPU select bit + Uint16 ECAP3:1; // 2 ECAP3 CPU select bit + Uint16 ECAP4:1; // 3 ECAP4 CPU select bit + Uint16 ECAP5:1; // 4 ECAP5 CPU select bit + Uint16 ECAP6:1; // 5 ECAP6 CPU select bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CPUSEL1_REG { + Uint32 all; + struct CPUSEL1_BITS bit; +}; + +struct CPUSEL2_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 CPU select bit + Uint16 EQEP2:1; // 1 EQEP2 CPU select bit + Uint16 EQEP3:1; // 2 EQEP3 CPU select bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CPUSEL2_REG { + Uint32 all; + struct CPUSEL2_BITS bit; +}; + +struct CPUSEL4_BITS { // bits description + Uint16 SD1:1; // 0 SD1 CPU select bit + Uint16 SD2:1; // 1 SD2 CPU select bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union CPUSEL4_REG { + Uint32 all; + struct CPUSEL4_BITS bit; +}; + +struct CPUSEL5_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A CPU select bit + Uint16 SCI_B:1; // 1 SCI_B CPU select bit + Uint16 SCI_C:1; // 2 SCI_C CPU select bit + Uint16 SCI_D:1; // 3 SCI_D CPU select bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL5_REG { + Uint32 all; + struct CPUSEL5_BITS bit; +}; + +struct CPUSEL6_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A CPU select bit + Uint16 SPI_B:1; // 1 SPI_B CPU select bit + Uint16 SPI_C:1; // 2 SPI_C CPU select bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union CPUSEL6_REG { + Uint32 all; + struct CPUSEL6_BITS bit; +}; + +struct CPUSEL7_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A CPU select bit + Uint16 I2C_B:1; // 1 I2C_B CPU select bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union CPUSEL7_REG { + Uint32 all; + struct CPUSEL7_BITS bit; +}; + +struct CPUSEL8_BITS { // bits description + Uint16 CAN_A:1; // 0 CAN_A CPU select bit + Uint16 CAN_B:1; // 1 CAN_B CPU select bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CPUSEL8_REG { + Uint32 all; + struct CPUSEL8_BITS bit; +}; + +struct CPUSEL9_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A CPU select bit + Uint16 McBSP_B:1; // 1 McBSP_B CPU select bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL9_REG { + Uint32 all; + struct CPUSEL9_BITS bit; +}; + +struct CPUSEL11_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A CPU select bit + Uint16 ADC_B:1; // 1 ADC_B CPU select bit + Uint16 ADC_C:1; // 2 ADC_C CPU select bit + Uint16 ADC_D:1; // 3 ADC_D CPU select bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL11_REG { + Uint32 all; + struct CPUSEL11_BITS bit; +}; + +struct CPUSEL12_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 CPU select bit + Uint16 CMPSS2:1; // 1 CMPSS2 CPU select bit + Uint16 CMPSS3:1; // 2 CMPSS3 CPU select bit + Uint16 CMPSS4:1; // 3 CMPSS4 CPU select bit + Uint16 CMPSS5:1; // 4 CMPSS5 CPU select bit + Uint16 CMPSS6:1; // 5 CMPSS6 CPU select bit + Uint16 CMPSS7:1; // 6 CMPSS7 CPU select bit + Uint16 CMPSS8:1; // 7 CMPSS8 CPU select bit + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL12_REG { + Uint32 all; + struct CPUSEL12_BITS bit; +}; + +struct CPUSEL14_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered_DAC_A CPU select bit + Uint16 DAC_B:1; // 17 Buffered_DAC_B CPU select bit + Uint16 DAC_C:1; // 18 Buffered_DAC_C CPU select bit + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union CPUSEL14_REG { + Uint32 all; + struct CPUSEL14_BITS bit; +}; + +struct CPU2RESCTL_BITS { // bits description + Uint16 RESET:1; // 0 CPU2 Reset Control bit + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register +}; + +union CPU2RESCTL_REG { + Uint32 all; + struct CPU2RESCTL_BITS bit; +}; + +struct RSTSTAT_BITS { // bits description + Uint16 CPU2RES:1; // 0 CPU2 Reset Status bit + Uint16 CPU2NMIWDRST:1; // 1 Indicates whether a CPU2.NMIWD reset was issued to CPU2 + Uint16 CPU2HWBISTRST0:1; // 2 Indicates whether a HWBIST reset was issued to CPU2 + Uint16 CPU2HWBISTRST1:1; // 3 Indicates whether a HWBIST reset was issued to CPU2 + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union RSTSTAT_REG { + Uint16 all; + struct RSTSTAT_BITS bit; +}; + +struct LPMSTAT_BITS { // bits description + Uint16 CPU2LPMSTAT:2; // 1:0 CPU2 LPM Status + Uint16 rsvd1:14; // 15:2 Reserved +}; + +union LPMSTAT_REG { + Uint16 all; + struct LPMSTAT_BITS bit; +}; + +struct SYSDBGCTL_BITS { // bits description + Uint16 BIT_0:1; // 0 Used in PLL startup. Only reset by POR. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSDBGCTL_REG { + Uint32 all; + struct SYSDBGCTL_BITS bit; +}; + +struct DEV_CFG_REGS { + union DEVCFGLOCK1_REG DEVCFGLOCK1; // Lock bit for CPUSELx registers + Uint16 rsvd1[6]; // Reserved + union PARTIDL_REG PARTIDL; // Lower 32-bit of Device PART Identification Number + union PARTIDH_REG PARTIDH; // Upper 32-bit of Device PART Identification Number + Uint32 REVID; // Device Revision Number + Uint16 rsvd2[2]; // Reserved + union DC0_REG DC0; // Device Capability: Device Information + union DC1_REG DC1; // Device Capability: Processing Block Customization + union DC2_REG DC2; // Device Capability: EMIF Customization + union DC3_REG DC3; // Device Capability: Peripheral Customization + union DC4_REG DC4; // Device Capability: Peripheral Customization + union DC5_REG DC5; // Device Capability: Peripheral Customization + union DC6_REG DC6; // Device Capability: Peripheral Customization + union DC7_REG DC7; // Device Capability: Peripheral Customization + union DC8_REG DC8; // Device Capability: Peripheral Customization + union DC9_REG DC9; // Device Capability: Peripheral Customization + union DC10_REG DC10; // Device Capability: Peripheral Customization + union DC11_REG DC11; // Device Capability: Peripheral Customization + union DC12_REG DC12; // Device Capability: Peripheral Customization + union DC13_REG DC13; // Device Capability: Peripheral Customization + union DC14_REG DC14; // Device Capability: Analog Modules Customization + union DC15_REG DC15; // Device Capability: Analog Modules Customization + Uint16 rsvd3[2]; // Reserved + union DC17_REG DC17; // Device Capability: Analog Modules Customization + union DC18_REG DC18; // Device Capability: CPU1 Lx SRAM Customization + union DC19_REG DC19; // Device Capability: CPU2 Lx SRAM Customization + union DC20_REG DC20; // Device Capability: GSx SRAM Customization + Uint16 rsvd4[38]; // Reserved + union PERCNF1_REG PERCNF1; // Peripheral Configuration register + Uint16 rsvd5[18]; // Reserved + union FUSEERR_REG FUSEERR; // e-Fuse error Status register + Uint16 rsvd6[12]; // Reserved + union SOFTPRES0_REG SOFTPRES0; // Processing Block Software Reset register + union SOFTPRES1_REG SOFTPRES1; // EMIF Software Reset register + union SOFTPRES2_REG SOFTPRES2; // Peripheral Software Reset register + union SOFTPRES3_REG SOFTPRES3; // Peripheral Software Reset register + union SOFTPRES4_REG SOFTPRES4; // Peripheral Software Reset register + Uint16 rsvd7[2]; // Reserved + union SOFTPRES6_REG SOFTPRES6; // Peripheral Software Reset register + union SOFTPRES7_REG SOFTPRES7; // Peripheral Software Reset register + union SOFTPRES8_REG SOFTPRES8; // Peripheral Software Reset register + union SOFTPRES9_REG SOFTPRES9; // Peripheral Software Reset register + Uint16 rsvd8[2]; // Reserved + union SOFTPRES11_REG SOFTPRES11; // Peripheral Software Reset register + Uint16 rsvd9[2]; // Reserved + union SOFTPRES13_REG SOFTPRES13; // Peripheral Software Reset register + union SOFTPRES14_REG SOFTPRES14; // Peripheral Software Reset register + Uint16 rsvd10[2]; // Reserved + union SOFTPRES16_REG SOFTPRES16; // Peripheral Software Reset register + Uint16 rsvd11[50]; // Reserved + union CPUSEL0_REG CPUSEL0; // CPU Select register for common peripherals + union CPUSEL1_REG CPUSEL1; // CPU Select register for common peripherals + union CPUSEL2_REG CPUSEL2; // CPU Select register for common peripherals + Uint16 rsvd12[2]; // Reserved + union CPUSEL4_REG CPUSEL4; // CPU Select register for common peripherals + union CPUSEL5_REG CPUSEL5; // CPU Select register for common peripherals + union CPUSEL6_REG CPUSEL6; // CPU Select register for common peripherals + union CPUSEL7_REG CPUSEL7; // CPU Select register for common peripherals + union CPUSEL8_REG CPUSEL8; // CPU Select register for common peripherals + union CPUSEL9_REG CPUSEL9; // CPU Select register for common peripherals + Uint16 rsvd13[2]; // Reserved + union CPUSEL11_REG CPUSEL11; // CPU Select register for common peripherals + union CPUSEL12_REG CPUSEL12; // CPU Select register for common peripherals + Uint16 rsvd14[2]; // Reserved + union CPUSEL14_REG CPUSEL14; // CPU Select register for common peripherals + Uint16 rsvd15[46]; // Reserved + union CPU2RESCTL_REG CPU2RESCTL; // CPU2 Reset Control Register + union RSTSTAT_REG RSTSTAT; // Reset Status register for secondary C28x CPUs + union LPMSTAT_REG LPMSTAT; // LPM Status Register for secondary C28x CPUs + Uint16 rsvd16[6]; // Reserved + union SYSDBGCTL_REG SYSDBGCTL; // System Debug Control register +}; + +struct CLKSEM_BITS { // bits description + Uint16 SEM:2; // 1:0 Semaphore for CLKCFG Ownership by CPU1 or CPU2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register +}; + +union CLKSEM_REG { + Uint32 all; + struct CLKSEM_BITS bit; +}; + +struct CLKCFGLOCK1_BITS { // bits description + Uint16 CLKSRCCTL1:1; // 0 Lock bit for CLKSRCCTL1 register + Uint16 CLKSRCCTL2:1; // 1 Lock bit for CLKSRCCTL2 register + Uint16 CLKSRCCTL3:1; // 2 Lock bit for CLKSRCCTL3 register + Uint16 SYSPLLCTL1:1; // 3 Lock bit for SYSPLLCTL1 register + Uint16 SYSPLLCTL2:1; // 4 Lock bit for SYSPLLCTL2 register + Uint16 SYSPLLCTL3:1; // 5 Lock bit for SYSPLLCTL3 register + Uint16 SYSPLLMULT:1; // 6 Lock bit for SYSPLLMULT register + Uint16 AUXPLLCTL1:1; // 7 Lock bit for AUXPLLCTL1 register + Uint16 rsvd1:1; // 8 Reserved + Uint16 rsvd2:1; // 9 Reserved + Uint16 AUXPLLMULT:1; // 10 Lock bit for AUXPLLMULT register + Uint16 SYSCLKDIVSEL:1; // 11 Lock bit for SYSCLKDIVSEL register + Uint16 AUXCLKDIVSEL:1; // 12 Lock bit for AUXCLKDIVSEL register + Uint16 PERCLKDIVSEL:1; // 13 Lock bit for PERCLKDIVSEL register + Uint16 rsvd3:1; // 14 Reserved + Uint16 LOSPCP:1; // 15 Lock bit for LOSPCP register + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CLKCFGLOCK1_REG { + Uint32 all; + struct CLKCFGLOCK1_BITS bit; +}; + +struct CLKSRCCTL1_BITS { // bits description + Uint16 OSCCLKSRCSEL:2; // 1:0 OSCCLK Source Select Bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 INTOSC2OFF:1; // 3 Internal Oscillator 2 Off Bit + Uint16 XTALOFF:1; // 4 Crystal (External) Oscillator Off Bit + Uint16 WDHALTI:1; // 5 Watchdog HALT Mode Ignore Bit + Uint16 rsvd2:10; // 15:6 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CLKSRCCTL1_REG { + Uint32 all; + struct CLKSRCCTL1_BITS bit; +}; + +struct CLKSRCCTL2_BITS { // bits description + Uint16 AUXOSCCLKSRCSEL:2; // 1:0 AUXOSCCLK Source Select Bit + Uint16 CANABCLKSEL:2; // 3:2 CANA Bit Clock Source Select Bit + Uint16 CANBBCLKSEL:2; // 5:4 CANB Bit Clock Source Select Bit + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 rsvd2:2; // 9:8 Reserved + Uint16 rsvd3:6; // 15:10 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CLKSRCCTL2_REG { + Uint32 all; + struct CLKSRCCTL2_BITS bit; +}; + +struct CLKSRCCTL3_BITS { // bits description + Uint16 XCLKOUTSEL:3; // 2:0 XCLKOUT Source Select Bit + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CLKSRCCTL3_REG { + Uint32 all; + struct CLKSRCCTL3_BITS bit; +}; + +struct SYSPLLCTL1_BITS { // bits description + Uint16 PLLEN:1; // 0 SYSPLL enable/disable bit + Uint16 PLLCLKEN:1; // 1 SYSPLL bypassed or included in the PLLSYSCLK path + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSPLLCTL1_REG { + Uint32 all; + struct SYSPLLCTL1_BITS bit; +}; + +struct SYSPLLMULT_BITS { // bits description + Uint16 IMULT:7; // 6:0 SYSPLL Integer Multiplier + Uint16 rsvd1:1; // 7 Reserved + Uint16 FMULT:2; // 9:8 SYSPLL Fractional Multiplier + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union SYSPLLMULT_REG { + Uint32 all; + struct SYSPLLMULT_BITS bit; +}; + +struct SYSPLLSTS_BITS { // bits description + Uint16 LOCKS:1; // 0 SYSPLL Lock Status Bit + Uint16 SLIPS:1; // 1 SYSPLL Slip Status Bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSPLLSTS_REG { + Uint32 all; + struct SYSPLLSTS_BITS bit; +}; + +struct AUXPLLCTL1_BITS { // bits description + Uint16 PLLEN:1; // 0 AUXPLL enable/disable bit + Uint16 PLLCLKEN:1; // 1 AUXPLL bypassed or included in the AUXPLLCLK path + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union AUXPLLCTL1_REG { + Uint32 all; + struct AUXPLLCTL1_BITS bit; +}; + +struct AUXPLLMULT_BITS { // bits description + Uint16 IMULT:7; // 6:0 AUXPLL Integer Multiplier + Uint16 rsvd1:1; // 7 Reserved + Uint16 FMULT:2; // 9:8 AUXPLL Fractional Multiplier + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union AUXPLLMULT_REG { + Uint32 all; + struct AUXPLLMULT_BITS bit; +}; + +struct AUXPLLSTS_BITS { // bits description + Uint16 LOCKS:1; // 0 AUXPLL Lock Status Bit + Uint16 SLIPS:1; // 1 AUXPLL Slip Status Bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union AUXPLLSTS_REG { + Uint32 all; + struct AUXPLLSTS_BITS bit; +}; + +struct SYSCLKDIVSEL_BITS { // bits description + Uint16 PLLSYSCLKDIV:6; // 5:0 PLLSYSCLK Divide Select + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSCLKDIVSEL_REG { + Uint32 all; + struct SYSCLKDIVSEL_BITS bit; +}; + +struct AUXCLKDIVSEL_BITS { // bits description + Uint16 AUXPLLDIV:2; // 1:0 AUXPLLCLK Divide Select + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union AUXCLKDIVSEL_REG { + Uint32 all; + struct AUXCLKDIVSEL_BITS bit; +}; + +struct PERCLKDIVSEL_BITS { // bits description + Uint16 EPWMCLKDIV:2; // 1:0 EPWM Clock Divide Select + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 EMIF1CLKDIV:1; // 4 EMIF1 Clock Divide Select + Uint16 rsvd2:1; // 5 Reserved + Uint16 EMIF2CLKDIV:1; // 6 EMIF2 Clock Divide Select + Uint16 rsvd3:9; // 15:7 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union PERCLKDIVSEL_REG { + Uint32 all; + struct PERCLKDIVSEL_BITS bit; +}; + +struct XCLKOUTDIVSEL_BITS { // bits description + Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Select + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union XCLKOUTDIVSEL_REG { + Uint32 all; + struct XCLKOUTDIVSEL_BITS bit; +}; + +struct LOSPCP_BITS { // bits description + Uint16 LSPCLKDIV:3; // 2:0 LSPCLK Divide Select + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LOSPCP_REG { + Uint32 all; + struct LOSPCP_BITS bit; +}; + +struct MCDCR_BITS { // bits description + Uint16 MCLKSTS:1; // 0 Missing Clock Status Bit + Uint16 MCLKCLR:1; // 1 Missing Clock Clear Bit + Uint16 MCLKOFF:1; // 2 Missing Clock Detect Off Bit + Uint16 OSCOFF:1; // 3 Oscillator Clock Off Bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MCDCR_REG { + Uint32 all; + struct MCDCR_BITS bit; +}; + +struct X1CNT_BITS { // bits description + Uint16 X1CNT:10; // 9:0 X1 Counter + Uint16 rsvd1:6; // 15:10 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union X1CNT_REG { + Uint32 all; + struct X1CNT_BITS bit; +}; + +struct CLK_CFG_REGS { + union CLKSEM_REG CLKSEM; // Clock Control Semaphore Register + union CLKCFGLOCK1_REG CLKCFGLOCK1; // Lock bit for CLKCFG registers + Uint16 rsvd1[4]; // Reserved + union CLKSRCCTL1_REG CLKSRCCTL1; // Clock Source Control register-1 + union CLKSRCCTL2_REG CLKSRCCTL2; // Clock Source Control register-2 + union CLKSRCCTL3_REG CLKSRCCTL3; // Clock Source Control register-3 + union SYSPLLCTL1_REG SYSPLLCTL1; // SYSPLL Control register-1 + Uint16 rsvd2[4]; // Reserved + union SYSPLLMULT_REG SYSPLLMULT; // SYSPLL Multiplier register + union SYSPLLSTS_REG SYSPLLSTS; // SYSPLL Status register + union AUXPLLCTL1_REG AUXPLLCTL1; // AUXPLL Control register-1 + Uint16 rsvd3[4]; // Reserved + union AUXPLLMULT_REG AUXPLLMULT; // AUXPLL Multiplier register + union AUXPLLSTS_REG AUXPLLSTS; // AUXPLL Status register + union SYSCLKDIVSEL_REG SYSCLKDIVSEL; // System Clock Divider Select register + union AUXCLKDIVSEL_REG AUXCLKDIVSEL; // Auxillary Clock Divider Select register + union PERCLKDIVSEL_REG PERCLKDIVSEL; // Peripheral Clock Divider Selet register + union XCLKOUTDIVSEL_REG XCLKOUTDIVSEL; // XCLKOUT Divider Select register + Uint16 rsvd4[2]; // Reserved + union LOSPCP_REG LOSPCP; // Low Speed Clock Source Prescalar + union MCDCR_REG MCDCR; // Missing Clock Detect Control Register + union X1CNT_REG X1CNT; // 10-bit Counter on X1 Clock +}; + +struct CPUSYSLOCK1_BITS { // bits description + Uint16 HIBBOOTMODE:1; // 0 Lock bit for HIBBOOTMODE register + Uint16 IORESTOREADDR:1; // 1 Lock bit for IORESTOREADDR Register + Uint16 PIEVERRADDR:1; // 2 Lock bit for PIEVERRADDR Register + Uint16 PCLKCR0:1; // 3 Lock bit for PCLKCR0 Register + Uint16 PCLKCR1:1; // 4 Lock bit for PCLKCR1 Register + Uint16 PCLKCR2:1; // 5 Lock bit for PCLKCR2 Register + Uint16 PCLKCR3:1; // 6 Lock bit for PCLKCR3 Register + Uint16 PCLKCR4:1; // 7 Lock bit for PCLKCR4 Register + Uint16 PCLKCR5:1; // 8 Lock bit for PCLKCR5 Register + Uint16 PCLKCR6:1; // 9 Lock bit for PCLKCR6 Register + Uint16 PCLKCR7:1; // 10 Lock bit for PCLKCR7 Register + Uint16 PCLKCR8:1; // 11 Lock bit for PCLKCR8 Register + Uint16 PCLKCR9:1; // 12 Lock bit for PCLKCR9 Register + Uint16 PCLKCR10:1; // 13 Lock bit for PCLKCR10 Register + Uint16 PCLKCR11:1; // 14 Lock bit for PCLKCR11 Register + Uint16 PCLKCR12:1; // 15 Lock bit for PCLKCR12 Register + Uint16 PCLKCR13:1; // 16 Lock bit for PCLKCR13 Register + Uint16 PCLKCR14:1; // 17 Lock bit for PCLKCR14 Register + Uint16 PCLKCR15:1; // 18 Lock bit for PCLKCR15 Register + Uint16 PCLKCR16:1; // 19 Lock bit for PCLKCR16 Register + Uint16 SECMSEL:1; // 20 Lock bit for SECMSEL Register + Uint16 LPMCR:1; // 21 Lock bit for LPMCR Register + Uint16 GPIOLPMSEL0:1; // 22 Lock bit for GPIOLPMSEL0 Register + Uint16 GPIOLPMSEL1:1; // 23 Lock bit for GPIOLPMSEL1 Register + Uint16 rsvd1:8; // 31:24 Reserved +}; + +union CPUSYSLOCK1_REG { + Uint32 all; + struct CPUSYSLOCK1_BITS bit; +}; + +struct IORESTOREADDR_BITS { // bits description + Uint32 ADDR:22; // 21:0 restoreIO() routine address + Uint16 rsvd1:10; // 31:22 Reserved +}; + +union IORESTOREADDR_REG { + Uint32 all; + struct IORESTOREADDR_BITS bit; +}; + +struct PIEVERRADDR_BITS { // bits description + Uint32 ADDR:22; // 21:0 PIE Vector Fetch Error Handler Routine Address + Uint16 rsvd1:10; // 31:22 Reserved +}; + +union PIEVERRADDR_REG { + Uint32 all; + struct PIEVERRADDR_BITS bit; +}; + +struct PCLKCR0_BITS { // bits description + Uint16 CLA1:1; // 0 CLA1 Clock Enable Bit + Uint16 rsvd1:1; // 1 Reserved + Uint16 DMA:1; // 2 DMA Clock Enable bit + Uint16 CPUTIMER0:1; // 3 CPUTIMER0 Clock Enable bit + Uint16 CPUTIMER1:1; // 4 CPUTIMER1 Clock Enable bit + Uint16 CPUTIMER2:1; // 5 CPUTIMER2 Clock Enable bit + Uint16 rsvd2:10; // 15:6 Reserved + Uint16 HRPWM:1; // 16 HRPWM Clock Enable Bit + Uint16 rsvd3:1; // 17 Reserved + Uint16 TBCLKSYNC:1; // 18 EPWM Time Base Clock sync + Uint16 GTBCLKSYNC:1; // 19 EPWM Time Base Clock Global sync + Uint16 rsvd4:12; // 31:20 Reserved +}; + +union PCLKCR0_REG { + Uint32 all; + struct PCLKCR0_BITS bit; +}; + +struct PCLKCR1_BITS { // bits description + Uint16 EMIF1:1; // 0 EMIF1 Clock Enable bit + Uint16 EMIF2:1; // 1 EMIF2 Clock Enable bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR1_REG { + Uint32 all; + struct PCLKCR1_BITS bit; +}; + +struct PCLKCR2_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 Clock Enable bit + Uint16 EPWM2:1; // 1 EPWM2 Clock Enable bit + Uint16 EPWM3:1; // 2 EPWM3 Clock Enable bit + Uint16 EPWM4:1; // 3 EPWM4 Clock Enable bit + Uint16 EPWM5:1; // 4 EPWM5 Clock Enable bit + Uint16 EPWM6:1; // 5 EPWM6 Clock Enable bit + Uint16 EPWM7:1; // 6 EPWM7 Clock Enable bit + Uint16 EPWM8:1; // 7 EPWM8 Clock Enable bit + Uint16 EPWM9:1; // 8 EPWM9 Clock Enable bit + Uint16 EPWM10:1; // 9 EPWM10 Clock Enable bit + Uint16 EPWM11:1; // 10 EPWM11 Clock Enable bit + Uint16 EPWM12:1; // 11 EPWM12 Clock Enable bit + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union PCLKCR2_REG { + Uint32 all; + struct PCLKCR2_BITS bit; +}; + +struct PCLKCR3_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 Clock Enable bit + Uint16 ECAP2:1; // 1 ECAP2 Clock Enable bit + Uint16 ECAP3:1; // 2 ECAP3 Clock Enable bit + Uint16 ECAP4:1; // 3 ECAP4 Clock Enable bit + Uint16 ECAP5:1; // 4 ECAP5 Clock Enable bit + Uint16 ECAP6:1; // 5 ECAP6 Clock Enable bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union PCLKCR3_REG { + Uint32 all; + struct PCLKCR3_BITS bit; +}; + +struct PCLKCR4_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 Clock Enable bit + Uint16 EQEP2:1; // 1 EQEP2 Clock Enable bit + Uint16 EQEP3:1; // 2 EQEP3 Clock Enable bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union PCLKCR4_REG { + Uint32 all; + struct PCLKCR4_BITS bit; +}; + +struct PCLKCR6_BITS { // bits description + Uint16 SD1:1; // 0 SD1 Clock Enable bit + Uint16 SD2:1; // 1 SD2 Clock Enable bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union PCLKCR6_REG { + Uint32 all; + struct PCLKCR6_BITS bit; +}; + +struct PCLKCR7_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A Clock Enable bit + Uint16 SCI_B:1; // 1 SCI_B Clock Enable bit + Uint16 SCI_C:1; // 2 SCI_C Clock Enable bit + Uint16 SCI_D:1; // 3 SCI_D Clock Enable bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR7_REG { + Uint32 all; + struct PCLKCR7_BITS bit; +}; + +struct PCLKCR8_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A Clock Enable bit + Uint16 SPI_B:1; // 1 SPI_B Clock Enable bit + Uint16 SPI_C:1; // 2 SPI_C Clock Enable bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union PCLKCR8_REG { + Uint32 all; + struct PCLKCR8_BITS bit; +}; + +struct PCLKCR9_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A Clock Enable bit + Uint16 I2C_B:1; // 1 I2C_B Clock Enable bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union PCLKCR9_REG { + Uint32 all; + struct PCLKCR9_BITS bit; +}; + +struct PCLKCR10_BITS { // bits description + Uint16 CAN_A:1; // 0 CAN_A Clock Enable bit + Uint16 CAN_B:1; // 1 CAN_B Clock Enable bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union PCLKCR10_REG { + Uint32 all; + struct PCLKCR10_BITS bit; +}; + +struct PCLKCR11_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A Clock Enable bit + Uint16 McBSP_B:1; // 1 McBSP_B Clock Enable bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 USB_A:1; // 16 USB_A Clock Enable bit + Uint16 rsvd2:1; // 17 Reserved + Uint16 rsvd3:14; // 31:18 Reserved +}; + +union PCLKCR11_REG { + Uint32 all; + struct PCLKCR11_BITS bit; +}; + +struct PCLKCR12_BITS { // bits description + Uint16 uPP_A:1; // 0 uPP_A Clock Enable bit + Uint16 rsvd1:1; // 1 Reserved + Uint16 rsvd2:14; // 15:2 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union PCLKCR12_REG { + Uint32 all; + struct PCLKCR12_BITS bit; +}; + +struct PCLKCR13_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A Clock Enable bit + Uint16 ADC_B:1; // 1 ADC_B Clock Enable bit + Uint16 ADC_C:1; // 2 ADC_C Clock Enable bit + Uint16 ADC_D:1; // 3 ADC_D Clock Enable bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR13_REG { + Uint32 all; + struct PCLKCR13_BITS bit; +}; + +struct PCLKCR14_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 Clock Enable bit + Uint16 CMPSS2:1; // 1 CMPSS2 Clock Enable bit + Uint16 CMPSS3:1; // 2 CMPSS3 Clock Enable bit + Uint16 CMPSS4:1; // 3 CMPSS4 Clock Enable bit + Uint16 CMPSS5:1; // 4 CMPSS5 Clock Enable bit + Uint16 CMPSS6:1; // 5 CMPSS6 Clock Enable bit + Uint16 CMPSS7:1; // 6 CMPSS7 Clock Enable bit + Uint16 CMPSS8:1; // 7 CMPSS8 Clock Enable bit + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR14_REG { + Uint32 all; + struct PCLKCR14_BITS bit; +}; + +struct PCLKCR16_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered_DAC_A Clock Enable Bit + Uint16 DAC_B:1; // 17 Buffered_DAC_B Clock Enable Bit + Uint16 DAC_C:1; // 18 Buffered_DAC_C Clock Enable Bit + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union PCLKCR16_REG { + Uint32 all; + struct PCLKCR16_BITS bit; +}; + +struct SECMSEL_BITS { // bits description + Uint16 PF1SEL:2; // 1:0 Secondary Master Select for VBUS32_1 Bridge + Uint16 PF2SEL:2; // 3:2 Secondary Master Select for VBUS32_2 Bridge + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 rsvd2:2; // 7:6 Reserved + Uint16 rsvd3:2; // 9:8 Reserved + Uint16 rsvd4:2; // 11:10 Reserved + Uint16 rsvd5:2; // 13:12 Reserved + Uint16 rsvd6:2; // 15:14 Reserved + Uint16 rsvd7:16; // 31:16 Reserved +}; + +union SECMSEL_REG { + Uint32 all; + struct SECMSEL_BITS bit; +}; + +struct LPMCR_BITS { // bits description + Uint16 LPM:2; // 1:0 Low Power Mode setting + Uint16 QUALSTDBY:6; // 7:2 STANDBY Wakeup Pin Qualification Setting + Uint16 rsvd1:7; // 14:8 Reserved + Uint16 WDINTE:1; // 15 Enable for WDINT wakeup from STANDBY + Uint16 M0M1MODE:2; // 17:16 Configuration for M0 and M1 mode during HIB + Uint16 rsvd2:13; // 30:18 Reserved + Uint16 IOISODIS:1; // 31 IO Isolation Disable +}; + +union LPMCR_REG { + Uint32 all; + struct LPMCR_BITS bit; +}; + +struct GPIOLPMSEL0_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 Enable for LPM Wakeup + Uint16 GPIO1:1; // 1 GPIO1 Enable for LPM Wakeup + Uint16 GPIO2:1; // 2 GPIO2 Enable for LPM Wakeup + Uint16 GPIO3:1; // 3 GPIO3 Enable for LPM Wakeup + Uint16 GPIO4:1; // 4 GPIO4 Enable for LPM Wakeup + Uint16 GPIO5:1; // 5 GPIO5 Enable for LPM Wakeup + Uint16 GPIO6:1; // 6 GPIO6 Enable for LPM Wakeup + Uint16 GPIO7:1; // 7 GPIO7 Enable for LPM Wakeup + Uint16 GPIO8:1; // 8 GPIO8 Enable for LPM Wakeup + Uint16 GPIO9:1; // 9 GPIO9 Enable for LPM Wakeup + Uint16 GPIO10:1; // 10 GPIO10 Enable for LPM Wakeup + Uint16 GPIO11:1; // 11 GPIO11 Enable for LPM Wakeup + Uint16 GPIO12:1; // 12 GPIO12 Enable for LPM Wakeup + Uint16 GPIO13:1; // 13 GPIO13 Enable for LPM Wakeup + Uint16 GPIO14:1; // 14 GPIO14 Enable for LPM Wakeup + Uint16 GPIO15:1; // 15 GPIO15 Enable for LPM Wakeup + Uint16 GPIO16:1; // 16 GPIO16 Enable for LPM Wakeup + Uint16 GPIO17:1; // 17 GPIO17 Enable for LPM Wakeup + Uint16 GPIO18:1; // 18 GPIO18 Enable for LPM Wakeup + Uint16 GPIO19:1; // 19 GPIO19 Enable for LPM Wakeup + Uint16 GPIO20:1; // 20 GPIO20 Enable for LPM Wakeup + Uint16 GPIO21:1; // 21 GPIO21 Enable for LPM Wakeup + Uint16 GPIO22:1; // 22 GPIO22 Enable for LPM Wakeup + Uint16 GPIO23:1; // 23 GPIO23 Enable for LPM Wakeup + Uint16 GPIO24:1; // 24 GPIO24 Enable for LPM Wakeup + Uint16 GPIO25:1; // 25 GPIO25 Enable for LPM Wakeup + Uint16 GPIO26:1; // 26 GPIO26 Enable for LPM Wakeup + Uint16 GPIO27:1; // 27 GPIO27 Enable for LPM Wakeup + Uint16 GPIO28:1; // 28 GPIO28 Enable for LPM Wakeup + Uint16 GPIO29:1; // 29 GPIO29 Enable for LPM Wakeup + Uint16 GPIO30:1; // 30 GPIO30 Enable for LPM Wakeup + Uint16 GPIO31:1; // 31 GPIO31 Enable for LPM Wakeup +}; + +union GPIOLPMSEL0_REG { + Uint32 all; + struct GPIOLPMSEL0_BITS bit; +}; + +struct GPIOLPMSEL1_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 Enable for LPM Wakeup + Uint16 GPIO33:1; // 1 GPIO33 Enable for LPM Wakeup + Uint16 GPIO34:1; // 2 GPIO34 Enable for LPM Wakeup + Uint16 GPIO35:1; // 3 GPIO35 Enable for LPM Wakeup + Uint16 GPIO36:1; // 4 GPIO36 Enable for LPM Wakeup + Uint16 GPIO37:1; // 5 GPIO37 Enable for LPM Wakeup + Uint16 GPIO38:1; // 6 GPIO38 Enable for LPM Wakeup + Uint16 GPIO39:1; // 7 GPIO39 Enable for LPM Wakeup + Uint16 GPIO40:1; // 8 GPIO40 Enable for LPM Wakeup + Uint16 GPIO41:1; // 9 GPIO41 Enable for LPM Wakeup + Uint16 GPIO42:1; // 10 GPIO42 Enable for LPM Wakeup + Uint16 GPIO43:1; // 11 GPIO43 Enable for LPM Wakeup + Uint16 GPIO44:1; // 12 GPIO44 Enable for LPM Wakeup + Uint16 GPIO45:1; // 13 GPIO45 Enable for LPM Wakeup + Uint16 GPIO46:1; // 14 GPIO46 Enable for LPM Wakeup + Uint16 GPIO47:1; // 15 GPIO47 Enable for LPM Wakeup + Uint16 GPIO48:1; // 16 GPIO48 Enable for LPM Wakeup + Uint16 GPIO49:1; // 17 GPIO49 Enable for LPM Wakeup + Uint16 GPIO50:1; // 18 GPIO50 Enable for LPM Wakeup + Uint16 GPIO51:1; // 19 GPIO51 Enable for LPM Wakeup + Uint16 GPIO52:1; // 20 GPIO52 Enable for LPM Wakeup + Uint16 GPIO53:1; // 21 GPIO53 Enable for LPM Wakeup + Uint16 GPIO54:1; // 22 GPIO54 Enable for LPM Wakeup + Uint16 GPIO55:1; // 23 GPIO55 Enable for LPM Wakeup + Uint16 GPIO56:1; // 24 GPIO56 Enable for LPM Wakeup + Uint16 GPIO57:1; // 25 GPIO57 Enable for LPM Wakeup + Uint16 GPIO58:1; // 26 GPIO58 Enable for LPM Wakeup + Uint16 GPIO59:1; // 27 GPIO59 Enable for LPM Wakeup + Uint16 GPIO60:1; // 28 GPIO60 Enable for LPM Wakeup + Uint16 GPIO61:1; // 29 GPIO61 Enable for LPM Wakeup + Uint16 GPIO62:1; // 30 GPIO62 Enable for LPM Wakeup + Uint16 GPIO63:1; // 31 GPIO63 Enable for LPM Wakeup +}; + +union GPIOLPMSEL1_REG { + Uint32 all; + struct GPIOLPMSEL1_BITS bit; +}; + +struct TMR2CLKCTL_BITS { // bits description + Uint16 TMR2CLKSRCSEL:3; // 2:0 CPU Timer 2 Clock Source Select Bit + Uint16 TMR2CLKPRESCALE:3; // 5:3 CPU Timer 2 Clock Pre-Scale Value + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union TMR2CLKCTL_REG { + Uint32 all; + struct TMR2CLKCTL_BITS bit; +}; + +struct RESC_BITS { // bits description + Uint16 POR:1; // 0 POR Reset Cause Indication Bit + Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit + Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit + Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit + Uint16 rsvd1:1; // 4 Reserved + Uint16 HWBISTn:1; // 5 HWBISTn Reset Cause Indication Bit + Uint16 HIBRESETn:1; // 6 HIBRESETn Reset Cause Indication Bit + Uint16 rsvd2:1; // 7 Reserved + Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit + Uint16 rsvd3:7; // 15:9 Reserved + Uint16 rsvd4:14; // 29:16 Reserved + Uint16 XRSn_pin_status:1; // 30 XRSN Pin Status + Uint16 TRSTn_pin_status:1; // 31 TRSTn Status +}; + +union RESC_REG { + Uint32 all; + struct RESC_BITS bit; +}; + +struct CPU_SYS_REGS { + union CPUSYSLOCK1_REG CPUSYSLOCK1; // Lock bit for CPUSYS registers + Uint16 rsvd1[4]; // Reserved + Uint32 HIBBOOTMODE; // HIB Boot Mode Register + union IORESTOREADDR_REG IORESTOREADDR; // IORestore() routine Address Register + union PIEVERRADDR_REG PIEVERRADDR; // PIE Vector Fetch Error Address register + Uint16 rsvd2[22]; // Reserved + union PCLKCR0_REG PCLKCR0; // Peripheral Clock Gating Registers + union PCLKCR1_REG PCLKCR1; // Peripheral Clock Gating Registers + union PCLKCR2_REG PCLKCR2; // Peripheral Clock Gating Registers + union PCLKCR3_REG PCLKCR3; // Peripheral Clock Gating Registers + union PCLKCR4_REG PCLKCR4; // Peripheral Clock Gating Registers + Uint16 rsvd3[2]; // Reserved + union PCLKCR6_REG PCLKCR6; // Peripheral Clock Gating Registers + union PCLKCR7_REG PCLKCR7; // Peripheral Clock Gating Registers + union PCLKCR8_REG PCLKCR8; // Peripheral Clock Gating Registers + union PCLKCR9_REG PCLKCR9; // Peripheral Clock Gating Registers + union PCLKCR10_REG PCLKCR10; // Peripheral Clock Gating Registers + union PCLKCR11_REG PCLKCR11; // Peripheral Clock Gating Registers + union PCLKCR12_REG PCLKCR12; // Peripheral Clock Gating Registers + union PCLKCR13_REG PCLKCR13; // Peripheral Clock Gating Registers + union PCLKCR14_REG PCLKCR14; // Peripheral Clock Gating Registers + Uint16 rsvd4[2]; // Reserved + union PCLKCR16_REG PCLKCR16; // Peripheral Clock Gating Registers + Uint16 rsvd5[48]; // Reserved + union SECMSEL_REG SECMSEL; // Secondary Master Select register for common peripherals: Selects between CLA & DMA + union LPMCR_REG LPMCR; // LPM Control Register + union GPIOLPMSEL0_REG GPIOLPMSEL0; // GPIO LPM Wakeup select registers + union GPIOLPMSEL1_REG GPIOLPMSEL1; // GPIO LPM Wakeup select registers + union TMR2CLKCTL_REG TMR2CLKCTL; // Timer2 Clock Measurement functionality control register + Uint16 rsvd6[2]; // Reserved + union RESC_REG RESC; // Reset Cause register +}; + +struct SCSR_BITS { // bits description + Uint16 WDOVERRIDE:1; // 0 WD Override for WDDIS bit + Uint16 WDENINT:1; // 1 WD Interrupt Enable + Uint16 WDINTS:1; // 2 WD Interrupt Status + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union SCSR_REG { + Uint16 all; + struct SCSR_BITS bit; +}; + +struct WDCNTR_BITS { // bits description + Uint16 WDCNTR:8; // 7:0 WD Counter + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union WDCNTR_REG { + Uint16 all; + struct WDCNTR_BITS bit; +}; + +struct WDKEY_BITS { // bits description + Uint16 WDKEY:8; // 7:0 WD KEY + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union WDKEY_REG { + Uint16 all; + struct WDKEY_BITS bit; +}; + +struct WDCR_BITS { // bits description + Uint16 WDPS:3; // 2:0 WD Clock Prescalar + Uint16 WDCHK:3; // 5:3 WD Check Bits + Uint16 WDDIS:1; // 6 WD Disable + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union WDCR_REG { + Uint16 all; + struct WDCR_BITS bit; +}; + +struct WDWCR_BITS { // bits description + Uint16 MIN:8; // 7:0 WD Min Threshold setting for Windowed Watchdog functionality + Uint16 FIRSTKEY:1; // 8 First Key Detect Flag + Uint16 rsvd1:7; // 15:9 Reserved +}; + +union WDWCR_REG { + Uint16 all; + struct WDWCR_BITS bit; +}; + +struct WD_REGS { + Uint16 rsvd1[34]; // Reserved + union SCSR_REG SCSR; // System Control & Status Register + union WDCNTR_REG WDCNTR; // Watchdog Counter Register + Uint16 rsvd2; // Reserved + union WDKEY_REG WDKEY; // Watchdog Reset Key Register + Uint16 rsvd3[3]; // Reserved + union WDCR_REG WDCR; // Watchdog Control Register + union WDWCR_REG WDWCR; // Watchdog Windowed Control Register +}; + +struct CLA1TASKSRCSELLOCK_BITS { // bits description + Uint16 CLA1TASKSRCSEL1:1; // 0 CLA1TASKSRCSEL1 Register Lock bit + Uint16 CLA1TASKSRCSEL2:1; // 1 CLA1TASKSRCSEL2 Register Lock bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CLA1TASKSRCSELLOCK_REG { + Uint32 all; + struct CLA1TASKSRCSELLOCK_BITS bit; +}; + +struct DMACHSRCSELLOCK_BITS { // bits description + Uint16 DMACHSRCSEL1:1; // 0 DMACHSRCSEL1 Register Lock bit + Uint16 DMACHSRCSEL2:1; // 1 DMACHSRCSEL2 Register Lock bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DMACHSRCSELLOCK_REG { + Uint32 all; + struct DMACHSRCSELLOCK_BITS bit; +}; + +struct CLA1TASKSRCSEL1_BITS { // bits description + Uint16 TASK1:8; // 7:0 Selects the Trigger Source for TASK1 of CLA1 + Uint16 TASK2:8; // 15:8 Selects the Trigger Source for TASK2 of CLA1 + Uint16 TASK3:8; // 23:16 Selects the Trigger Source for TASK3 of CLA1 + Uint16 TASK4:8; // 31:24 Selects the Trigger Source for TASK4 of CLA1 +}; + +union CLA1TASKSRCSEL1_REG { + Uint32 all; + struct CLA1TASKSRCSEL1_BITS bit; +}; + +struct CLA1TASKSRCSEL2_BITS { // bits description + Uint16 TASK5:8; // 7:0 Selects the Trigger Source for TASK5 of CLA1 + Uint16 TASK6:8; // 15:8 Selects the Trigger Source for TASK6 of CLA1 + Uint16 TASK7:8; // 23:16 Selects the Trigger Source for TASK7 of CLA1 + Uint16 TASK8:8; // 31:24 Selects the Trigger Source for TASK8 of CLA1 +}; + +union CLA1TASKSRCSEL2_REG { + Uint32 all; + struct CLA1TASKSRCSEL2_BITS bit; +}; + +struct DMACHSRCSEL1_BITS { // bits description + Uint16 CH1:8; // 7:0 Selects the Trigger and Sync Source CH1 of DMA + Uint16 CH2:8; // 15:8 Selects the Trigger and Sync Source CH2 of DMA + Uint16 CH3:8; // 23:16 Selects the Trigger and Sync Source CH3 of DMA + Uint16 CH4:8; // 31:24 Selects the Trigger and Sync Source CH4 of DMA +}; + +union DMACHSRCSEL1_REG { + Uint32 all; + struct DMACHSRCSEL1_BITS bit; +}; + +struct DMACHSRCSEL2_BITS { // bits description + Uint16 CH5:8; // 7:0 Selects the Trigger and Sync Source CH5 of DMA + Uint16 CH6:8; // 15:8 Selects the Trigger and Sync Source CH6 of DMA + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union DMACHSRCSEL2_REG { + Uint32 all; + struct DMACHSRCSEL2_BITS bit; +}; + +struct DMA_CLA_SRC_SEL_REGS { + union CLA1TASKSRCSELLOCK_REG CLA1TASKSRCSELLOCK; // CLA1 Task Trigger Source Select Lock Register + Uint16 rsvd1[2]; // Reserved + union DMACHSRCSELLOCK_REG DMACHSRCSELLOCK; // DMA Channel Triger Source Select Lock Register + union CLA1TASKSRCSEL1_REG CLA1TASKSRCSEL1; // CLA1 Task Trigger Source Select Register-1 + union CLA1TASKSRCSEL2_REG CLA1TASKSRCSEL2; // CLA1 Task Trigger Source Select Register-2 + Uint16 rsvd2[12]; // Reserved + union DMACHSRCSEL1_REG DMACHSRCSEL1; // DMA Channel Trigger Source Select Register-1 + union DMACHSRCSEL2_REG DMACHSRCSEL2; // DMA Channel Trigger Source Select Register-2 +}; + +struct SYNCSELECT_BITS { // bits description + Uint16 EPWM4SYNCIN:3; // 2:0 Selects Sync Input Source for EPWM4 + Uint16 EPWM7SYNCIN:3; // 5:3 Selects Sync Input Source for EPWM7 + Uint16 EPWM10SYNCIN:3; // 8:6 Selects Sync Input Source for EPWM10 + Uint16 ECAP1SYNCIN:3; // 11:9 Selects Sync Input Source for ECAP1 + Uint16 ECAP4SYNCIN:3; // 14:12 Selects Sync Input Source for ECAP4 + Uint16 rsvd1:1; // 15 Reserved + Uint16 rsvd2:11; // 26:16 Reserved + Uint16 SYNCOUT:2; // 28:27 Select Syncout Source + Uint16 rsvd3:3; // 31:29 Reserved +}; + +union SYNCSELECT_REG { + Uint32 all; + struct SYNCSELECT_BITS bit; +}; + +struct ADCSOCOUTSELECT_BITS { // bits description + Uint16 PWM1SOCAEN:1; // 0 PWM1SOCAEN Enable for ADCSOCAO + Uint16 PWM2SOCAEN:1; // 1 PWM2SOCAEN Enable for ADCSOCAO + Uint16 PWM3SOCAEN:1; // 2 PWM3SOCAEN Enable for ADCSOCAO + Uint16 PWM4SOCAEN:1; // 3 PWM4SOCAEN Enable for ADCSOCAO + Uint16 PWM5SOCAEN:1; // 4 PWM5SOCAEN Enable for ADCSOCAO + Uint16 PWM6SOCAEN:1; // 5 PWM6SOCAEN Enable for ADCSOCAO + Uint16 PWM7SOCAEN:1; // 6 PWM7SOCAEN Enable for ADCSOCAO + Uint16 PWM8SOCAEN:1; // 7 PWM8SOCAEN Enable for ADCSOCAO + Uint16 PWM9SOCAEN:1; // 8 PWM9SOCAEN Enable for ADCSOCAO + Uint16 PWM10SOCAEN:1; // 9 PWM10SOCAEN Enable for ADCSOCAO + Uint16 PWM11SOCAEN:1; // 10 PWM11SOCAEN Enable for ADCSOCAO + Uint16 PWM12SOCAEN:1; // 11 PWM12SOCAEN Enable for ADCSOCAO + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 PWM1SOCBEN:1; // 16 PWM1SOCBEN Enable for ADCSOCBO + Uint16 PWM2SOCBEN:1; // 17 PWM2SOCBEN Enable for ADCSOCBO + Uint16 PWM3SOCBEN:1; // 18 PWM3SOCBEN Enable for ADCSOCBO + Uint16 PWM4SOCBEN:1; // 19 PWM4SOCBEN Enable for ADCSOCBO + Uint16 PWM5SOCBEN:1; // 20 PWM5SOCBEN Enable for ADCSOCBO + Uint16 PWM6SOCBEN:1; // 21 PWM6SOCBEN Enable for ADCSOCBO + Uint16 PWM7SOCBEN:1; // 22 PWM7SOCBEN Enable for ADCSOCBO + Uint16 PWM8SOCBEN:1; // 23 PWM8SOCBEN Enable for ADCSOCBO + Uint16 PWM9SOCBEN:1; // 24 PWM9SOCBEN Enable for ADCSOCBO + Uint16 PWM10SOCBEN:1; // 25 PWM10SOCBEN Enable for ADCSOCBO + Uint16 PWM11SOCBEN:1; // 26 PWM11SOCBEN Enable for ADCSOCBO + Uint16 PWM12SOCBEN:1; // 27 PWM12SOCBEN Enable for ADCSOCBO + Uint16 rsvd2:4; // 31:28 Reserved +}; + +union ADCSOCOUTSELECT_REG { + Uint32 all; + struct ADCSOCOUTSELECT_BITS bit; +}; + +struct SYNCSOCLOCK_BITS { // bits description + Uint16 SYNCSELECT:1; // 0 SYNCSEL Register Lock bit + Uint16 ADCSOCOUTSELECT:1; // 1 ADCSOCOUTSELECT Register Lock bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYNCSOCLOCK_REG { + Uint32 all; + struct SYNCSOCLOCK_BITS bit; +}; + +struct SYNC_SOC_REGS { + union SYNCSELECT_REG SYNCSELECT; // Sync Input and Output Select Register + union ADCSOCOUTSELECT_REG ADCSOCOUTSELECT; // External ADC (Off Chip) SOC Select Register + union SYNCSOCLOCK_REG SYNCSOCLOCK; // SYNCSEL and EXTADCSOC Select Lock register +}; + +//--------------------------------------------------------------------------- +// SYSCTRL External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct WD_REGS WdRegs; +extern volatile struct SYNC_SOC_REGS SyncSocRegs; +extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; +extern volatile struct DEV_CFG_REGS DevCfgRegs; +extern volatile struct CLK_CFG_REGS ClkCfgRegs; +extern volatile struct CPU_SYS_REGS CpuSysRegs; +#endif +#ifdef CPU2 +extern volatile struct WD_REGS WdRegs; +extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; +extern volatile struct CLK_CFG_REGS ClkCfgRegs; +extern volatile struct CPU_SYS_REGS CpuSysRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_upp.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_upp.h new file mode 100644 index 00000000000..c33bcc90f2e --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_upp.h @@ -0,0 +1,403 @@ +//########################################################################### +// +// FILE: F2837xD_upp.h +// +// TITLE: UPP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_UPP_H__ +#define __F2837xD_UPP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// UPP Individual Register Bit Definitions: + +struct PERCTL_BITS { // bits description + Uint16 FREE:1; // 0 Emulation control. + Uint16 SOFT:1; // 1 Emulation control. + Uint16 RTEMU:1; // 2 Realtime emulation control. + Uint16 PEREN:1; // 3 Peripheral Enable + Uint16 SOFTRST:1; // 4 Software Reset + Uint16 rsvd1:2; // 6:5 Reserved + Uint16 DMAST:1; // 7 DMA Burst transaction status + Uint16 rsvd2:8; // 15:8 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union PERCTL_REG { + Uint32 all; + struct PERCTL_BITS bit; +}; + +struct CHCTL_BITS { // bits description + Uint16 MODE:2; // 1:0 Operating mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 SDRTXILA:1; // 3 SDR TX Interleve mode + Uint16 DEMUXA:1; // 4 DDR de-multiplexing mode + Uint16 rsvd2:11; // 15:5 Reserved + Uint16 DRA:1; // 16 Data rate + Uint16 rsvd3:14; // 30:17 Reserved + Uint16 rsvd4:1; // 31 Reserved +}; + +union CHCTL_REG { + Uint32 all; + struct CHCTL_BITS bit; +}; + +struct IFCFG_BITS { // bits description + Uint16 STARTPOLA:1; // 0 Polarity of START(SELECT) signal + Uint16 ENAPOLA:1; // 1 Polarity of ENABLE(WRITE) signal + Uint16 WAITPOLA:1; // 2 Polarity of WAIT signal. + Uint16 STARTA:1; // 3 Enable Usage of START (SELECT) signal + Uint16 ENAA:1; // 4 Enable Usage of ENABLE (WRITE) signal + Uint16 WAITA:1; // 5 Enable Usage of WAIT signal + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 CLKDIVA:4; // 11:8 Clock divider for tx mode + Uint16 CLKINVA:1; // 12 Clock inversion + Uint16 TRISENA:1; // 13 Pin Tri-state Control + Uint16 rsvd2:2; // 15:14 Reserved + Uint16 rsvd3:6; // 21:16 Reserved + Uint16 rsvd4:2; // 23:22 Reserved + Uint16 rsvd5:6; // 29:24 Reserved + Uint16 rsvd6:2; // 31:30 Reserved +}; + +union IFCFG_REG { + Uint32 all; + struct IFCFG_BITS bit; +}; + +struct IFIVAL_BITS { // bits description + Uint16 VALA:9; // 8:0 Idle Value + Uint16 rsvd1:7; // 15:9 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union IFIVAL_REG { + Uint32 all; + struct IFIVAL_BITS bit; +}; + +struct THCFG_BITS { // bits description + Uint16 RDSIZEI:2; // 1:0 DMA Read Threshold for DMA Channel I + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 RDSIZEQ:2; // 9:8 DMA Read Threshold for DMA Channel Q + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 TXSIZEA:2; // 17:16 I/O Transmit Threshold Value + Uint16 rsvd3:6; // 23:18 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:6; // 31:26 Reserved +}; + +union THCFG_REG { + Uint32 all; + struct THCFG_BITS bit; +}; + +struct RAWINTST_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt raw status for DMA programming error + Uint16 UOEI:1; // 1 Interrupt raw status for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt raw status for end-of window condition + Uint16 EOLI:1; // 4 Interrupt raw status for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt raw status for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt raw status for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt raw status for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt raw status for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union RAWINTST_REG { + Uint32 all; + struct RAWINTST_BITS bit; +}; + +struct ENINTST_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt enable status for DMA programming error + Uint16 UOEI:1; // 1 Interrupt enable status for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt enable status for end-of window condition + Uint16 EOLI:1; // 4 Interrupt enable status for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt enable status for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt enable status for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt enable status for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt enable status for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union ENINTST_REG { + Uint32 all; + struct ENINTST_BITS bit; +}; + +struct INTENSET_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt enable for DMA programming error + Uint16 UOEI:1; // 1 Interrupt enable for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt enable for end-of window condition + Uint16 EOLI:1; // 4 Interrupt enable for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt enable for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt enable for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt enable for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt enable for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union INTENSET_REG { + Uint32 all; + struct INTENSET_BITS bit; +}; + +struct INTENCLR_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt clear for DMA programming error + Uint16 UOEI:1; // 1 Interrupt clear for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt clear for end-of window condition + Uint16 EOLI:1; // 4 Interrupt clear for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt clear for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt clear for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt clear for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt clear for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union INTENCLR_REG { + Uint32 all; + struct INTENCLR_BITS bit; +}; + +struct CHIDESC1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel I transfer. + Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel I transfer. +}; + +union CHIDESC1_REG { + Uint32 all; + struct CHIDESC1_BITS bit; +}; + +struct CHIDESC2_BITS { // bits description + Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union CHIDESC2_REG { + Uint32 all; + struct CHIDESC2_BITS bit; +}; + +struct CHIST1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Current byte number. + Uint16 LCNT:16; // 31:16 Current line number. +}; + +union CHIST1_REG { + Uint32 all; + struct CHIST1_BITS bit; +}; + +struct CHIST2_BITS { // bits description + Uint16 ACT:1; // 0 Status of DMA descriptor. + Uint16 PEND:1; // 1 Status of DMA. + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel I tranfer. + Uint16 rsvd2:8; // 15:8 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CHIST2_REG { + Uint32 all; + struct CHIST2_BITS bit; +}; + +struct CHQDESC1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel Q transfer. + Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel Q transfer. +}; + +union CHQDESC1_REG { + Uint32 all; + struct CHQDESC1_BITS bit; +}; + +struct CHQDESC2_BITS { // bits description + Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union CHQDESC2_REG { + Uint32 all; + struct CHQDESC2_BITS bit; +}; + +struct CHQST1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Current byte number. + Uint16 LCNT:16; // 31:16 Current line number. +}; + +union CHQST1_REG { + Uint32 all; + struct CHQST1_BITS bit; +}; + +struct CHQST2_BITS { // bits description + Uint16 ACT:1; // 0 Status of DMA descriptor. + Uint16 PEND:1; // 1 Status of DMA. + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel Q tranfer. + Uint16 rsvd2:8; // 15:8 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CHQST2_REG { + Uint32 all; + struct CHQST2_BITS bit; +}; + +struct GINTEN_BITS { // bits description + Uint16 GINTEN:1; // 0 Global Interrupt Enable + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union GINTEN_REG { + Uint32 all; + struct GINTEN_BITS bit; +}; + +struct GINTFLG_BITS { // bits description + Uint16 GINTFLG:1; // 0 Global Interrupt Flag + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union GINTFLG_REG { + Uint32 all; + struct GINTFLG_BITS bit; +}; + +struct GINTCLR_BITS { // bits description + Uint16 GINTCLR:1; // 0 Global Interrupt Clear + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union GINTCLR_REG { + Uint32 all; + struct GINTCLR_BITS bit; +}; + +struct DLYCTL_BITS { // bits description + Uint16 DLYDIS:1; // 0 IO dealy control disable. + Uint16 DLYCTL:2; // 2:1 IO delay control. + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DLYCTL_REG { + Uint32 all; + struct DLYCTL_BITS bit; +}; + +struct UPP_REGS { + Uint32 PID; // Peripheral ID Register + union PERCTL_REG PERCTL; // Peripheral Control Register + Uint16 rsvd1[4]; // Reserved + union CHCTL_REG CHCTL; // General Control Register + union IFCFG_REG IFCFG; // Interface Configuration Register + union IFIVAL_REG IFIVAL; // Interface Idle Value Register + union THCFG_REG THCFG; // Threshold Configuration Register + union RAWINTST_REG RAWINTST; // Raw Interrupt Status Register + union ENINTST_REG ENINTST; // Enable Interrupt Status Register + union INTENSET_REG INTENSET; // Interrupt Enable Set Register + union INTENCLR_REG INTENCLR; // Interrupt Enable Clear Register + Uint16 rsvd2[8]; // Reserved + Uint32 CHIDESC0; // DMA Channel I Descriptor 0 Register + union CHIDESC1_REG CHIDESC1; // DMA Channel I Descriptor 1 Register + union CHIDESC2_REG CHIDESC2; // DMA Channel I Descriptor 2 Register + Uint16 rsvd3[2]; // Reserved + Uint32 CHIST0; // DMA Channel I Status 0 Register + union CHIST1_REG CHIST1; // DMA Channel I Status 1 Register + union CHIST2_REG CHIST2; // DMA Channel I Status 2 Register + Uint16 rsvd4[2]; // Reserved + Uint32 CHQDESC0; // DMA Channel Q Descriptor 0 Register + union CHQDESC1_REG CHQDESC1; // DMA Channel Q Descriptor 1 Register + union CHQDESC2_REG CHQDESC2; // DMA Channel Q Descriptor 2 Register + Uint16 rsvd5[2]; // Reserved + Uint32 CHQST0; // DMA Channel Q Status 0 Register + union CHQST1_REG CHQST1; // DMA Channel Q Status 1 Register + union CHQST2_REG CHQST2; // DMA Channel Q Status 2 Register + Uint16 rsvd6[2]; // Reserved + union GINTEN_REG GINTEN; // Global Peripheral Interrupt Enable Register + union GINTFLG_REG GINTFLG; // Global Peripheral Interrupt Flag Register + union GINTCLR_REG GINTCLR; // Global Peripheral Interrupt Clear Register + union DLYCTL_REG DLYCTL; // IO clock data skew control Register +}; + +//--------------------------------------------------------------------------- +// UPP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct UPP_REGS UppRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_xbar.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_xbar.h new file mode 100644 index 00000000000..d201fda67ce --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_xbar.h @@ -0,0 +1,303 @@ +//########################################################################### +// +// FILE: F2837xD_xbar.h +// +// TITLE: XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_XBAR_H__ +#define __F2837xD_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// XBAR Individual Register Bit Definitions: + +struct XBARFLG1_BITS { // bits description + Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal + Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal + Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal + Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal + Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal + Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal + Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal + Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal + Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal + Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal + Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal + Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal + Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal + Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal + Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal + Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal + Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal + Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal + Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal + Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal + Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal + Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal + Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal + Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal + Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal + Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal + Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal + Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal + Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal + Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal + Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal + Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal +}; + +union XBARFLG1_REG { + Uint32 all; + struct XBARFLG1_BITS bit; +}; + +struct XBARFLG2_BITS { // bits description + Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal + Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal + Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal + Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal + Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal + Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal + Uint16 ADCSOCAO:1; // 6 Input Flag for ADCSOCAO Signal + Uint16 ADCSOCBO:1; // 7 Input Flag for ADCSOCBO Signal + Uint16 rsvd1:1; // 8 Reserved + Uint16 rsvd2:1; // 9 Reserved + Uint16 rsvd3:1; // 10 Reserved + Uint16 rsvd4:1; // 11 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:1; // 13 Reserved + Uint16 rsvd7:1; // 14 Reserved + Uint16 rsvd8:1; // 15 Reserved + Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal + Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal + Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal + Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal + Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal + Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal + Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal + Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal + Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal + Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal + Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal + Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal + Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal + Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal + Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal + Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal +}; + +union XBARFLG2_REG { + Uint32 all; + struct XBARFLG2_BITS bit; +}; + +struct XBARFLG3_BITS { // bits description + Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal + Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal + Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal + Uint16 ADCDEVT1:1; // 3 Input Flag for ADCDEVT1 Signal + Uint16 ADCDEVT2:1; // 4 Input Flag for ADCDEVT2 Signal + Uint16 ADCDEVT3:1; // 5 Input Flag for ADCDEVT3 Signal + Uint16 ADCDEVT4:1; // 6 Input Flag for ADCDEVT4 Signal + Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal + Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal + Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal + Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal + Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal + Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal + Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal + Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal + Uint16 SD2FLT1_COMPL:1; // 15 Input Flag for SD2FLT1.COMPL Signal + Uint16 SD2FLT1_COMPH:1; // 16 Input Flag for SD2FLT1.COMPH Signal + Uint16 SD2FLT2_COMPL:1; // 17 Input Flag for SD2FLT2.COMPL Signal + Uint16 SD2FLT2_COMPH:1; // 18 Input Flag for SD2FLT2.COMPH Signal + Uint16 SD2FLT3_COMPL:1; // 19 Input Flag for SD2FLT3.COMPL Signal + Uint16 SD2FLT3_COMPH:1; // 20 Input Flag for SD2FLT3.COMPH Signal + Uint16 SD2FLT4_COMPL:1; // 21 Input Flag for SD2FLT4.COMPL Signal + Uint16 SD2FLT4_COMPH:1; // 22 Input Flag for SD2FLT4.COMPH Signal + Uint16 rsvd1:9; // 31:23 Reserved +}; + +union XBARFLG3_REG { + Uint32 all; + struct XBARFLG3_BITS bit; +}; + +struct XBARCLR1_BITS { // bits description + Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal + Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal + Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal + Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal + Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal + Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal + Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal + Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal + Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal + Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal + Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal + Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal + Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal + Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal + Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal + Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal + Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal + Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal + Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal + Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal + Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal + Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal + Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal + Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal + Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal + Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal + Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal + Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal + Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal + Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal + Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal + Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal +}; + +union XBARCLR1_REG { + Uint32 all; + struct XBARCLR1_BITS bit; +}; + +struct XBARCLR2_BITS { // bits description + Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal + Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal + Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal + Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal + Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal + Uint16 INPUT7:1; // 5 Input Flag Clear for INPUT7 Signal + Uint16 ADCSOCAO:1; // 6 Input Flag Clear for ADCSOCAO Signal + Uint16 ADCSOCBO:1; // 7 Input Flag Clear for ADCSOCBO Signal + Uint16 rsvd1:1; // 8 Reserved + Uint16 rsvd2:1; // 9 Reserved + Uint16 rsvd3:1; // 10 Reserved + Uint16 rsvd4:1; // 11 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:1; // 13 Reserved + Uint16 rsvd7:1; // 14 Reserved + Uint16 rsvd8:1; // 15 Reserved + Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal + Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal + Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal + Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal + Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal + Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal + Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal + Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal + Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal + Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal + Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal + Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal + Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal + Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal + Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal + Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal +}; + +union XBARCLR2_REG { + Uint32 all; + struct XBARCLR2_BITS bit; +}; + +struct XBARCLR3_BITS { // bits description + Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal + Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal + Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal + Uint16 ADCDEVT1:1; // 3 Input Flag Clear for ADCDEVT1 Signal + Uint16 ADCDEVT2:1; // 4 Input Flag Clear for ADCDEVT2 Signal + Uint16 ADCDEVT3:1; // 5 Input Flag Clear for ADCDEVT3 Signal + Uint16 ADCDEVT4:1; // 6 Input Flag Clear for ADCDEVT4 Signal + Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal + Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal + Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal + Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal + Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal + Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal + Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal + Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal + Uint16 SD2FLT1_COMPL:1; // 15 Input Flag Clear for SD2FLT1.COMPL Signal + Uint16 SD2FLT1_COMPH:1; // 16 Input Flag Clear for SD2FLT1.COMPH Signal + Uint16 SD2FLT2_COMPL:1; // 17 Input Flag Clear for SD2FLT2.COMPL Signal + Uint16 SD2FLT2_COMPH:1; // 18 Input Flag Clear for SD2FLT2.COMPH Signal + Uint16 SD2FLT3_COMPL:1; // 19 Input Flag Clear for SD2FLT3.COMPL Signal + Uint16 SD2FLT3_COMPH:1; // 20 Input Flag Clear for SD2FLT3.COMPH Signal + Uint16 SD2FLT4_COMPL:1; // 21 Input Flag Clear for SD2FLT4.COMPL Signal + Uint16 SD2FLT4_COMPH:1; // 22 Input Flag Clear for SD2FLT4.COMPH Signal + Uint16 rsvd1:9; // 31:23 Reserved +}; + +union XBARCLR3_REG { + Uint32 all; + struct XBARCLR3_BITS bit; +}; + +struct XBAR_REGS { + union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 + union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 + union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 + Uint16 rsvd1[2]; // Reserved + union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 + union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 + union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 + Uint16 rsvd2[18]; // Reserved +}; + +//--------------------------------------------------------------------------- +// XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct XBAR_REGS XbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/include/F2837xD_xint.h b/bsp/tms320f28379d/libraries/headers/include/F2837xD_xint.h new file mode 100644 index 00000000000..f647e68b069 --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/include/F2837xD_xint.h @@ -0,0 +1,143 @@ +//########################################################################### +// +// FILE: F2837xD_xint.h +// +// TITLE: XINT Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_XINT_H__ +#define __F2837xD_XINT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// XINT Individual Register Bit Definitions: + +struct XINT1CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT1 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT1 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT1CR_REG { + Uint16 all; + struct XINT1CR_BITS bit; +}; + +struct XINT2CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT2 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT2 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT2CR_REG { + Uint16 all; + struct XINT2CR_BITS bit; +}; + +struct XINT3CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT3 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT3 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT3CR_REG { + Uint16 all; + struct XINT3CR_BITS bit; +}; + +struct XINT4CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT4 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT4 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT4CR_REG { + Uint16 all; + struct XINT4CR_BITS bit; +}; + +struct XINT5CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT5 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT5 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT5CR_REG { + Uint16 all; + struct XINT5CR_BITS bit; +}; + +struct XINT_REGS { + union XINT1CR_REG XINT1CR; // XINT1 configuration register + union XINT2CR_REG XINT2CR; // XINT2 configuration register + union XINT3CR_REG XINT3CR; // XINT3 configuration register + union XINT4CR_REG XINT4CR; // XINT4 configuration register + union XINT5CR_REG XINT5CR; // XINT5 configuration register + Uint16 rsvd1[3]; // Reserved + Uint16 XINT1CTR; // XINT1 counter register + Uint16 XINT2CTR; // XINT2 counter register + Uint16 XINT3CTR; // XINT3 counter register +}; + +//--------------------------------------------------------------------------- +// XINT External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct XINT_REGS XintRegs; +#endif +#ifdef CPU2 +extern volatile struct XINT_REGS XintRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/tms320f28379d/libraries/headers/source/F2837xD_GlobalVariableDefs.c b/bsp/tms320f28379d/libraries/headers/source/F2837xD_GlobalVariableDefs.c new file mode 100644 index 00000000000..270b63815af --- /dev/null +++ b/bsp/tms320f28379d/libraries/headers/source/F2837xD_GlobalVariableDefs.c @@ -0,0 +1,876 @@ +//########################################################################### +// +// FILE: F2837xD_GlobalVariableDefs.c +// +// TITLE: F2837xD Global Variables and Data Section Pragmas. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "F2837xD_device.h" // F2837xD Headerfile Include File + +//--------------------------------------------------------------------------- +// Define Global Peripheral Variables: +// +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcaRegsFile") +#else +#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile"); +#endif +volatile struct ADC_REGS AdcaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdcbRegsFile") +#else +#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile"); +#endif +volatile struct ADC_REGS AdcbRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdccRegsFile") +#else +#pragma DATA_SECTION(AdccRegs,"AdccRegsFile"); +#endif +volatile struct ADC_REGS AdccRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdcdRegsFile") +#else +#pragma DATA_SECTION(AdcdRegs,"AdcdRegsFile"); +#endif +volatile struct ADC_REGS AdcdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcaResultFile") +#else +#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdcaResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcbResultFile") +#else +#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdcbResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdccResultFile") +#else +#pragma DATA_SECTION(AdccResultRegs,"AdccResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdccResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcdResultFile") +#else +#pragma DATA_SECTION(AdcdResultRegs,"AdcdResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdcdResultRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("AnalogSubsysRegsFile") +#else +#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile"); +#endif +volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; +#endif + +#if __TI_COMPILER_VERSION__ >= 16006000 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanaRegsFile") +#else +#pragma DATA_SECTION(CanaRegs,"CanaRegsFile"); +#endif +volatile struct CAN_REGS CanaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanbRegsFile") +#else +#pragma DATA_SECTION(CanbRegs,"CanbRegsFile"); +#endif +volatile struct CAN_REGS CanbRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss1RegsFile") +#else +#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss2RegsFile") +#else +#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss3RegsFile") +#else +#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss4RegsFile") +#else +#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss5RegsFile") +#else +#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss6RegsFile") +#else +#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss7RegsFile") +#else +#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss8RegsFile") +#else +#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacaRegsFile") +#else +#pragma DATA_SECTION(DacaRegs,"DacaRegsFile"); +#endif +volatile struct DAC_REGS DacaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacbRegsFile") +#else +#pragma DATA_SECTION(DacbRegs,"DacbRegsFile"); +#endif +volatile struct DAC_REGS DacbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DaccRegsFile") +#else +#pragma DATA_SECTION(DaccRegs,"DaccRegsFile"); +#endif +volatile struct DAC_REGS DaccRegs; +//---------------------------------------- + +#ifdef __cplusplus +#pragma DATA_SECTION("Cla1RegsFile") +#else +#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile"); +#endif +volatile struct CLA_REGS Cla1Regs; +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cla1SoftIntRegsFile") +#else +#pragma DATA_SECTION(Cla1SoftIntRegs,"Cla1SoftIntRegsFile"); +#endif +volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClkCfgRegsFile") +#else +#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile"); +#endif +volatile struct CLK_CFG_REGS ClkCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuSysRegsFile") +#else +#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile"); +#endif +volatile struct CPU_SYS_REGS CpuSysRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ1RegsFile") +#else +#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile"); +#endif +volatile struct DCSM_Z1_REGS DcsmZ1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ2RegsFile") +#else +#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile"); +#endif +volatile struct DCSM_Z2_REGS DcsmZ2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmCommonRegsFile") +#else +#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile"); +#endif +volatile struct DCSM_COMMON_REGS DcsmCommonRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaClaSrcSelRegsFile") +#else +#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile"); +#endif +volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("DevCfgRegsFile") +#else +#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile"); +#endif +volatile struct DEV_CFG_REGS DevCfgRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1RegsFile") +#else +#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile"); +#endif +volatile struct EMIF_REGS Emif1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2RegsFile") +#else +#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile"); +#endif +volatile struct EMIF_REGS Emif2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep3RegsFile") +#else +#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile"); +#endif +volatile struct EQEP_REGS EQep3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm7RegsFile") +#else +#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile"); +#endif +volatile struct EPWM_REGS EPwm7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm8RegsFile") +#else +#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile"); +#endif +volatile struct EPWM_REGS EPwm8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm9RegsFile") +#else +#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile"); +#endif +volatile struct EPWM_REGS EPwm9Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm10RegsFile") +#else +#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile"); +#endif +volatile struct EPWM_REGS EPwm10Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm11RegsFile") +#else +#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile"); +#endif +volatile struct EPWM_REGS EPwm11Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm12RegsFile") +#else +#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile"); +#endif +volatile struct EPWM_REGS EPwm12Regs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("EPwmXbarRegsFile") +#else +#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile"); +#endif +volatile struct EPWM_XBAR_REGS EPwmXbarRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("InputXbarRegsFile") +#else +#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile"); +#endif +volatile struct INPUT_XBAR_REGS InputXbarRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("XbarRegsFile") +#else +#pragma DATA_SECTION(XbarRegs,"XbarRegsFile"); +#endif +volatile struct XBAR_REGS XbarRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("OutputXbarRegsFile") +#else +#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile"); +#endif +volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2cbRegsFile") +#else +#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile"); +#endif +volatile struct I2C_REGS I2cbRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("IpcRegsFile") +#else +#pragma DATA_SECTION(IpcRegs,"IpcRegsFile"); +#endif +volatile struct IPC_REGS_CPU1 IpcRegs; +#endif + +//---------------------------------------- +#ifdef CPU2 +#ifdef __cplusplus +#pragma DATA_SECTION("IpcRegsFile") +#else +#pragma DATA_SECTION(IpcRegs,"IpcRegsFile"); +#endif +volatile struct IPC_REGS_CPU2 IpcRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile") +#else +#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile"); +#endif +volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +#endif + +//---------------------------------------- +#ifdef CPU2 +#ifdef __cplusplus +#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile") +#else +#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile"); +#endif +volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct McBSP_REGS McbspaRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("RomPrefetchRegsFile") +#else +#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile"); +#endif +volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemCfgRegsFile") +#else +#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile"); +#endif +volatile struct MEM_CFG_REGS MemCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile"); +#endif +volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile"); +#endif +volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("RomWaitStateRegsFile") +#else +#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile"); +#endif +volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AccessProtectionRegsFile") +#else +#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile"); +#endif +volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemoryErrorRegsFile") +#else +#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile"); +#endif +volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct McBSP_REGS McbspbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("NmiIntruptRegsFile") +#else +#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile"); +#endif +volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +volatile struct PIE_VECT_TABLE PieVectTable; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScidRegsFile") +#else +#pragma DATA_SECTION(ScidRegs,"ScidRegsFile"); +#endif +volatile struct SCI_REGS ScidRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpibRegsFile") +#else +#pragma DATA_SECTION(SpibRegs,"SpibRegsFile"); +#endif +volatile struct SPI_REGS SpibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpicRegsFile") +#else +#pragma DATA_SECTION(SpicRegs,"SpicRegsFile"); +#endif +volatile struct SPI_REGS SpicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm1RegsFile") +#else +#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm2RegsFile") +#else +#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm2Regs; + + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("SyncSocRegsFile") +#else +#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile"); +#endif +volatile struct SYNC_SOC_REGS SyncSocRegs; +#endif + +//---------------------------------------- +#if defined(CPU1) +#ifdef __cplusplus +#pragma DATA_SECTION("UppRegsFile") +#else +#pragma DATA_SECTION(UppRegs,"UppRegsFile"); +#endif +volatile struct UPP_REGS UppRegs; +#endif //defined(CPU1) + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("WdRegsFile") +#else +#pragma DATA_SECTION(WdRegs,"WdRegsFile"); +#endif +volatile struct WD_REGS WdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XintRegsFile") +#else +#pragma DATA_SECTION(XintRegs,"XintRegsFile"); +#endif +volatile struct XINT_REGS XintRegs; + +//-------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EmuBModeVar"); +#else +#pragma DATA_SECTION(EmuBMode,"EmuBModeVar"); +#endif +Uint16 EmuBMode; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("EmuBootPinsVar"); +#else +#pragma DATA_SECTION(EmuBootPins,"EmuBootPinsVar"); +#endif +Uint16 EmuBootPins; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0EccRegsFile") +#else +#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile"); +#endif +volatile struct FLASH_ECC_REGS Flash0EccRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0CtrlRegsFile") +#else +#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile"); +#endif +volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; + + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/bsp/tms320f28379d/rtconfig.h b/bsp/tms320f28379d/rtconfig.h new file mode 100644 index 00000000000..b0372958130 --- /dev/null +++ b/bsp/tms320f28379d/rtconfig.h @@ -0,0 +1,148 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +#define SOC_TMS320F28X + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_8 +#define RT_THREAD_PRIORITY_MAX 8 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define ARCH_TIDSP +#define ARCH_TIDSP_C28X +#define ARCH_CPU_STACK_GROWS_UPWARD + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT + +/* C++ features */ + + +/* Command shell */ + + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + +/* samples: kernel and components samples */ + + +/* example package: hello */ + + +#endif diff --git a/bsp/tms320f28379d/targetConfigs/TMS320F28379D.ccxml b/bsp/tms320f28379d/targetConfigs/TMS320F28379D.ccxml new file mode 100644 index 00000000000..42eb492f1fc --- /dev/null +++ b/bsp/tms320f28379d/targetConfigs/TMS320F28379D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/tms320f28379d/targetConfigs/readme.txt b/bsp/tms320f28379d/targetConfigs/readme.txt new file mode 100644 index 00000000000..d783fef4d6a --- /dev/null +++ b/bsp/tms320f28379d/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/bsp/x1000/.config b/bsp/x1000/.config index e6698d1d906..9ac579ccd9e 100644 --- a/bsp/x1000/.config +++ b/bsp/x1000/.config @@ -121,6 +121,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set diff --git a/bsp/x1000/drivers/Kconfig b/bsp/x1000/drivers/Kconfig index 0f2a2be685e..9eed79acc61 100644 --- a/bsp/x1000/drivers/Kconfig +++ b/bsp/x1000/drivers/Kconfig @@ -30,6 +30,19 @@ if RT_USING_SERIAL config RT_USING_UART2 bool "Using UART2" default y + + if RT_USING_UART2 + choice + prompt "GPIO function pins select" + default CONFIG_SYS_UART2_PC + + config CONFIG_SYS_UART2_PC + bool "PORT C" + + config CONFIG_SYS_UART2_PD + bool "PORT D" + endchoice + endif endif if RT_USING_SDIO diff --git a/bsp/x1000/drivers/usbd/drv_usbd.c b/bsp/x1000/drivers/usbd/drv_usbd.c index cb8c0ea4b70..03470fd8912 100644 --- a/bsp/x1000/drivers/usbd/drv_usbd.c +++ b/bsp/x1000/drivers/usbd/drv_usbd.c @@ -1,8 +1,13 @@ /* - * drv_usbd.c + * Copyright (c) 2006-2018, RT-Thread Development Team * - * Created on: 201721 - * Author: Urey + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-02-01 Urey first + * 2018-12-20 heyuanjie fix bugs + * 2018-12-25 Zhou Yanjie modify the coding style */ #include @@ -145,7 +150,7 @@ static rt_size_t __ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t dwc_ep *pep ; RT_DEBUG_LOG(RT_DEBUG_USB,("%s address = %02x,size = %d\n", __func__,address,size)); - pep = __dwc_hdl.dep[address & 0x0F + DWC_EP_OUT_OFS]; + pep = __dwc_hdl.dep[(address & 0x0F) + DWC_EP_OUT_OFS]; pep->ep_state = EP_DATA; pep->xfer_len = size; // pep->xfer_buff = buffer; diff --git a/bsp/x1000/rtconfig.h b/bsp/x1000/rtconfig.h index 30ccf9e409b..6babbd0b151 100644 --- a/bsp/x1000/rtconfig.h +++ b/bsp/x1000/rtconfig.h @@ -112,6 +112,7 @@ #define RT_USING_DEVICE_IPC #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA /* RT_USING_CAN is not set */ /* RT_USING_HWTIMER is not set */ /* RT_USING_CPUTIME is not set */ diff --git a/bsp/xplorer4330/M0/rtconfig.h b/bsp/xplorer4330/M0/rtconfig.h index 8adbc4e5762..ee849028f22 100644 --- a/bsp/xplorer4330/M0/rtconfig.h +++ b/bsp/xplorer4330/M0/rtconfig.h @@ -74,6 +74,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // #define RT_UART_RX_BUFFER_SIZE 256 // diff --git a/bsp/xplorer4330/M4/rtconfig.h b/bsp/xplorer4330/M4/rtconfig.h index 8adbc4e5762..ee849028f22 100644 --- a/bsp/xplorer4330/M4/rtconfig.h +++ b/bsp/xplorer4330/M4/rtconfig.h @@ -74,6 +74,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // #define RT_UART_RX_BUFFER_SIZE 256 // diff --git a/bsp/zynq7000/rtconfig.h b/bsp/zynq7000/rtconfig.h index 4c042a88f6c..ca304c6ac91 100644 --- a/bsp/zynq7000/rtconfig.h +++ b/bsp/zynq7000/rtconfig.h @@ -72,6 +72,7 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA // #define RT_UART_RX_BUFFER_SIZE 64 // diff --git a/bsp/zynq7000/zynq7000.ld b/bsp/zynq7000/zynq7000.ld index b8f2eb76905..ae9b8ea38d7 100644 --- a/bsp/zynq7000/zynq7000.ld +++ b/bsp/zynq7000/zynq7000.ld @@ -92,7 +92,7 @@ SECTIONS __data_end = .; . = ALIGN(4); - __bss_start = 0; + __bss_start = __data_end; .bss : { *(.bss) diff --git a/components/dfs/src/dfs.c b/components/dfs/src/dfs.c index cf0b2b0ef99..12ae8e9d956 100644 --- a/components/dfs/src/dfs.c +++ b/components/dfs/src/dfs.c @@ -18,6 +18,10 @@ #include #endif +#ifdef RT_USING_DFS_DEVFS +#include +#endif + /* Global variables */ const struct dfs_filesystem_ops *filesystem_operation_table[DFS_FILESYSTEM_TYPES_MAX]; struct dfs_filesystem filesystem_table[DFS_FILESYSTEMS_MAX]; @@ -212,6 +216,11 @@ struct dfs_fd *fd_get(int fd) struct dfs_fd *d; struct dfs_fdtable *fdt; +#ifdef RT_USING_DFS_DEVFS + if ((0 <= fd) && (fd <= 2)) + fd = libc_stdio_get_console(); +#endif + fdt = dfs_fdtable_get(); fd = fd - DFS_FD_OFFSET; if (fd < 0 || fd >= fdt->maxfd) diff --git a/components/libc/compilers/armlibc/stubs.c b/components/libc/compilers/armlibc/stubs.c index 6e9f13d1437..820daeff392 100644 --- a/components/libc/compilers/armlibc/stubs.c +++ b/components/libc/compilers/armlibc/stubs.c @@ -270,7 +270,10 @@ long _sys_flen(FILEHANDLE fh) int _sys_istty(FILEHANDLE fh) { - return 0; + if((STDIN <= fh) && (fh <= STDERR)) + return 1; + else + return 0; } int remove(const char *filename) diff --git a/components/libc/compilers/newlib/syscalls.c b/components/libc/compilers/newlib/syscalls.c index e4cda478cb7..759feafe676 100644 --- a/components/libc/compilers/newlib/syscalls.c +++ b/components/libc/compilers/newlib/syscalls.c @@ -9,6 +9,8 @@ #include #include #include +#include + #include #ifdef RT_USING_DFS @@ -218,7 +220,7 @@ _ssize_t _write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) { #ifndef RT_USING_DFS - if (fd == 0) + if (fileno(stdout) == fd) { rt_device_t console; diff --git a/components/net/at/at_socket/at_socket.c b/components/net/at/at_socket/at_socket.c index 3925f0f57cd..cccb35ae1a5 100644 --- a/components/net/at/at_socket/at_socket.c +++ b/components/net/at/at_socket/at_socket.c @@ -572,10 +572,16 @@ int at_connect(int socket, const struct sockaddr *name, socklen_t namelen) if (result < 0) { - at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); + if (sock != RT_NULL) + { + at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); + } } - at_do_event_changes(sock, AT_EVENT_SEND, RT_TRUE); + if (sock) + { + at_do_event_changes(sock, AT_EVENT_SEND, RT_TRUE); + } return result; } @@ -699,24 +705,27 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f __exit: - if (recv_len > 0) + if (sock != RT_NULL) { - result = recv_len; - at_do_event_changes(sock, AT_EVENT_RECV, RT_FALSE); - errno = 0; - if (!rt_slist_isempty(&sock->recvpkt_list)) + if (recv_len > 0) { - at_do_event_changes(sock, AT_EVENT_RECV, RT_TRUE); + result = recv_len; + at_do_event_changes(sock, AT_EVENT_RECV, RT_FALSE); + errno = 0; + if (!rt_slist_isempty(&sock->recvpkt_list)) + { + at_do_event_changes(sock, AT_EVENT_RECV, RT_TRUE); + } + else + { + at_do_event_clean(sock, AT_EVENT_RECV); + } } else { - at_do_event_clean(sock, AT_EVENT_RECV); + at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); } } - else - { - at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); - } return result; } @@ -807,7 +816,10 @@ int at_sendto(int socket, const void *data, size_t size, int flags, const struct if (result < 0) { - at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); + if (sock != RT_NULL) + { + at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE); + } } else { diff --git a/components/utilities/ulog/backend/console_be.c b/components/utilities/ulog/backend/console_be.c index b2ed3d565dc..04b0d91add7 100644 --- a/components/utilities/ulog/backend/console_be.c +++ b/components/utilities/ulog/backend/console_be.c @@ -45,12 +45,13 @@ void ulog_console_backend_output(struct ulog_backend *backend, rt_uint32_t level int ulog_console_backend_init(void) { + ulog_init(); console.output = ulog_console_backend_output; ulog_backend_register(&console, "console", RT_TRUE); return 0; } -INIT_COMPONENT_EXPORT(ulog_console_backend_init); +INIT_PREV_EXPORT(ulog_console_backend_init); #endif /* ULOG_BACKEND_USING_CONSOLE */ diff --git a/components/utilities/ulog/ulog.c b/components/utilities/ulog/ulog.c index 186154c7c9d..b813678ecd6 100644 --- a/components/utilities/ulog/ulog.c +++ b/components/utilities/ulog/ulog.c @@ -149,7 +149,7 @@ size_t ulog_strcpy(size_t cur_len, char *dst, const char *src) while (*src != 0) { /* make sure destination has enough space */ - if (cur_len++ <= ULOG_LINE_BUF_SIZE) + if (cur_len++ < ULOG_LINE_BUF_SIZE) { *dst++ = *src++; }